Page 1
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-7782P (DAA00002J00)
T
MODEL NAME :
QAL81
BD
GPIO MAP: E4_VC_GPIO_map_rev_0.8
2 2
Dalmore 14 DSC
Ivy Bridge + Panther POINT
2011-05-12
REV : 0.1 (X00)
@ : Nopop Component
3 3
CONN@ : Connector Component
MB Type
TPM
TCM
TPM DIS/TCM DIS 2@ 3@
4 4
MB PCB
MB PCB
Part Number Description
Part Number Description
DAA00002J00 PCB 0LE LA-7782P REV0 M/B DSC
DAA00002J00 PCB 0LE LA-7782P REV0 M/B DSC
A
B
BOM P/N
1@
3@
2@
4@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-7782
LA-7782
LA-7782
1 66Tuesday, May 24, 2011
1 66Tuesday, May 24, 2011
1 66Tuesday, May 24, 2011
E
0.1
0.1
0.1
Page 2
A
B
C
D
E
Block Diagram
1 1
LVDS CONN
HDMI CONN
DOCKING PORT
2 2
EXPRESS
3 3
4 4
PAGE 26
PAGE 38
USB2.0 [3,8]
SATA5
DOCK LAN
USB3.0 [4]
Card
USB10
CPU XDP Port
PCH XDP Port
WiFi ON/OFF
DC/DC Interface
Power On/Off
SW & LED
Thermal
GUARDIAN III
EMC4022
Compal confidential
LVDS Switch
MAX14979
DPC
DPD
VGA
DAI
CRT CONN
On IO board
SDXC/MMC
PCIE5
1/2 Mini Card
PAGE 34 PAGE 34 PAGE 34PAGE 35
USB6
PWM FAN
PAGE 22
A
PAGE 22PAGE 23
PS8171
PAGE 26
PAGE 33
PCIE2
1/2 Mini Card
WLAN
Smart Card
RFID
PAGE 22
iLVDS
dLVDS
DPE
Card Reader
OZ600FJ0
PCI Express BUS
Full Mini Card
WWAN
USB5USB4
TDA8034HN
Fingerprint
CONN
SMSC SIO
ECE5048
Nvidia
N13M
Video Switch
MAX14885E
PCIE1PCIE3
FP_USB
PAGE 39
B
PEG Gen3
PAGE 44-51
dVGA
PAGE 24
PAGE 33
100MHz
Option
China TCM1.2
SSX44BPP
USH
BCM5882
BC BUS
SMSC KBC
MEC5055
PAGE 41 PAGE 41
iVGA
iLVDS
PCIE x1
PAGE 32
USB7
USH Module
PAGE 40
KB CONNTP CONN
Ivy Bridge
Panther Point-M
LPC BUS
33MHz
Memory BUS (DDR3)
1333/1600 MHz
rPGA CPU
988 pins
FDI
Lane x 8
INTEL
PAGE 6-11
DMI2
Lane x 4
USB
SATA
Touch Screen
BT 4.0
Camera
SATA Repeater
PS8513B
BGA
PI5USB1457A USB
PAGE 14-21
PCI Express BUS
HD Audio I/F
SPI
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
W25Q64CVSSIG
64M 4K sector
PAGE 14
Power Share
100MHz
SATA Repeater
PS8520B
PAGE 27
W25Q32BVSSIG
MDC
RJ11
on IO board
32M 4K sector
PCIE4
PAGE 14
E-Module
PAGE 28
HDD
PAGE 27
FFS LNG3DM
PAGE 27
Discrete TPM
AT97SC3204
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
PAGE 32
D
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
PAGE 23
PAGE 41
PAGE 12-13
Trough LVDS Cable
PAGE 37
USB3.0
USB3.0
PAGE 36
HDA Codec
92HD93
PAGE 29
Trough LVDS Cable
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
E-SATA
USB 2.0 Port
USB3.0/2.0
USB3.0/2.0+PS
USB Port
PAGE 37
PAGE 36
PAGE 36
DOCK LAN
INT.Speaker
PAGE 29
HeadPhone &
MIC Jack
DAI
To Docking side
Dig.
MIC
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DIS Block Diagram
DIS Block Diagram
DIS Block Diagram
LA-7782
LA-7782
LA-7782
on IO board
Intel Lewisville
82579LM
LAN SWITCH
PI3L720
RJ45
on IO board
2 66Monday, May 30, 2011
2 66Monday, May 30, 2011
2 66Monday, May 30, 2011
E
PAGE 31
PAGE 31
0.1
0.1
0.1
Page 3
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
USB PORT#
0
1
2
3
4
5
6
7
JUSB1 (Right side Top)
JUSB2 (Right side Bottom)
JESA1 (Right side ESATA)
LK DOCK
M
WLAN
WWAN
JMINI3(Flash)
USH->BIO
DESTINATION
DOCKING8
PM TABLE
C C
power
plane
State
S0
S3
+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
+3.3V_M
+1.05V_M
ON
ON
+3.3V_M
+1.05V_M
(M-OFF)
ON
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
DESTINATION
DD
H
ODD/ E3 Module Bay
NA
NA
ESATA
Dock
USH
9
10 Express card
11
12
13 LCD Touch
0
1
JUSB (Left side)
Bluetooth
Camera
BIO
NA
S5 S4/AC
S5 S4/AC don't exist
B B
A A
ON
OFF
OFFOFF
OFF
OFF
ON
OFF
OFFOFF
need to update Power Status and PM
Table
DSC DP/HDMI Port
Port C
Port D
Port E
Connetion
Dock DP port 2
Dock DP port 1
MB HDMI Conn
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 None
DESTINATION
MINI CARD-1 WWAN
INI CARD-2 WLAN
M
Express card
E3 Module Bay (USB3)
1/2vMINI CARD-3 PCIE
MMI
10/100/1G LOM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-7782
LA-7782
LA-7782
3 66Friday, May 20, 2011
3 66Friday, May 20, 2011
3 66Friday, May 20, 2011
1
0.1
0.1
0.1
Page 4
5
4
3
2
1
EN_INVPWR
ADAPTER
D D
DGPU_PWR_EN
+PWR_SRC
BATTERY
FDC654P
(Q21)
ISL62883
(PU1000)
+VCC_CORE
+BL_PWR_SRC
+GPU_CORE
1.05V_0.8V_PWROK
VT1318M
(PU700)
HDDC_EN
+5V_HDD
MODC_EN
SI3456BDVSI3456BDV
(Q30)(Q27)
+5V_MOD
MCARD_MISC_PWREN
SI3456
(Q42)
MCARD_WWAN_PWREN
SI3456
(Q40)
+VCC_GFXCORE
ALWON
CHARGER
C C
RT8205
(PU100)
+5V_ALW
+3.3V_FLASH
+3.3V_WWAN
+3.3V_ALW
RT8207
(PU200)
B B
DDR_ON
+1.5V_MEM
TPS51212
(PU500)
CPU_VTT_ON
TPS51212
(PU400)
SIO_SLP_A#
SIO_SLP_S3#
SY8033
(PU300)
1.05V_VTTPWRGD
TPS51461
(PU600)
SI3456
(Q38)
AUX_EN_WOWL
PCH_ALW_ON
SI3456
(Q49)
SUS_ON
S13456
(Q54)
AUX_ON
SI3456
(Q34)
SIO_SLP_S3#
SIO_SLP_S3#
TPS22966
(U78)
SIO_SLP_A#
SI3456
(Q58)
CPU1.5V_S3_GATE
(QC3)
SIO_SLP_S3#
NTGS4141NAO4728
(Q59)
0.75V_DDR_VTT_ON
+1.05V_RUN_VTT +1.05V_M
SIO_SLP_S3#
SI4164
Pop option
+1.0V_LAN
+1.8V_RUN
+VCC_SA
+3.3V_WLAN
+3.3V_ALW_PCH
+3.3V_M
+3.3V_LAN+3.3V_SUS
Pop option
+3.3V_RUN
+3.3V_M
+5V_RUN
(Q63)
A A
5
+0.75V_DDR_VTT+1.5V_RUN+1.5V_CPU_VDDQ
+1.05V_RUN
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-7782
LA-7782
LA-7782
4 66Friday, May 20, 2011
4 66Friday, May 20, 2011
4 66Friday, May 20, 2011
1
0.1
0.1
0.1
Page 5
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
B4
A3
B5
A4
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
C8
G12
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
2.2K
2.2K
2.2K
2.2K
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
SMBUS Address [C8]
27
1
129
DOCKING
3
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
202
200
202
200
2
DIMMA
DIMMB
53
51
53
51
XDP1
XDP2
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
SMBUS Address [TBD]
1
10K
G Sensor
WWAN
+3.3V_RUN
SMBUS Address [0x3B]
SMBUS Address [TBD]
10K
4
6
30
32
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
9
8
7
6
M9
L9
7
8
Charger
BATTERY
CONN
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
Express card
SMBUS Address [0x12]
SMBUS Address [TBD]
29
E3 Module Bay
30
T4
GPU
T3
3
SMBUS Address [0xd2]
SMBUS Address [0xXX]
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SMBUS TOPOLOGY
SMBUS TOPOLOGY
SMBUS TOPOLOGY
LA-7782
LA-7782
LA-7782
5 66Friday, May 20, 2011
5 66Friday, May 20, 2011
5 66Friday, May 20, 2011
1
0.1
0.1
0.1
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
1E
B B
1E
MEC 5065
2B
2B
B
B52
53
A49
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
USH_SMBCLK
A50
2.2K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
2.2K
2.2K
2.2K
BAY_SMBDAT
B7
2D
BAY_SMBCLK
A A
A7
2D
2.2K
2.2K
GPU_SMBCLK
B49
2A
B48
2A
5
GPU_SMBDAT
Page 6
5
4
3
2
1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
+1.05V_RUN_VTT
12
RC2
RC2
24.9_0402_1%~D
D D
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
C C
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
B B
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
JCPU1A
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
DP Compensation
+1.05V_RUN_VTT
12
RC1
RC1
24.9_0402_1%~D
A A
eDP_COMPIO and ICOMPO signals should be shorted near
alls and routed with typical impedance <25 mohms
b
5
24.9_0402_1%~D
EDP_COMP
4
24.9_0402_1%~D
PEG_COMP
PEG_CRX_GTX_N0
PEG_CRX_GTX_N1
PEG_CRX_GTX_N2
PEG_CRX_GTX_N3
PEG_CRX_GTX_N4
PEG_CRX_GTX_N5
PEG_CRX_GTX_N6
PEG_CRX_GTX_N7
PEG_CRX_GTX_N8
PEG_CRX_GTX_N9
PEG_CRX_GTX_N10
PEG_CRX_GTX_N11
PEG_CRX_GTX_N12
PEG_CRX_GTX_N13
PEG_CRX_GTX_N14
PEG_CRX_GTX_N15
PEG_CRX_GTX_P0
PEG_CRX_GTX_P1
PEG_CRX_GTX_P2
PEG_CRX_GTX_P3
PEG_CRX_GTX_P4
PEG_CRX_GTX_P5
PEG_CRX_GTX_P6
PEG_CRX_GTX_P7
PEG_CRX_GTX_P8
PEG_CRX_GTX_P9
PEG_CRX_GTX_P10
PEG_CRX_GTX_P11
PEG_CRX_GTX_P12
PEG_CRX_GTX_P13
PEG_CRX_GTX_P14
PEG_CRX_GTX_P15
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N15
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P15
PEG_CRX_GTX_N[0..15] <45>
PEG_CRX_GTX_P[0..15] <45>
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
PEG_CTX_GRX_P[0..15] <45>
PEG_CTX_GRX_N[0..15] <45>
CC1 0.22U_0402_16V7K~DCC1 0.22U_0402_16V7K~D
12
CC2 0.22U_0402_16V7K~DCC2 0.22U_0402_16V7K~D
12
CC3 0.22U_0402_16V7K~DCC3 0.22U_0402_16V7K~D
12
CC4 0.22U_0402_16V7K~DCC4 0.22U_0402_16V7K~D
12
CC5 0.22U_0402_16V7K~DCC5 0.22U_0402_16V7K~D
12
CC6 0.22U_0402_16V7K~DCC6 0.22U_0402_16V7K~D
12
CC7 0.22U_0402_16V7K~DCC7 0.22U_0402_16V7K~D
12
CC8 0.22U_0402_16V7K~DCC8 0.22U_0402_16V7K~D
12
CC9 0.22U_0402_16V7K~DCC9 0.22U_0402_16V7K~D
12
CC10 0.22U_0402_16V7K~DCC10 0.22U_0402_16V7K~D
12
CC11 0.22U_0402_16V7K~DCC11 0.22U_0402_16V7K~D
12
CC12 0.22U_0402_16V7K~DCC12 0.22U_0402_16V7K~D
12
CC13 0.22U_0402_16V7K~DCC13 0.22U_0402_16V7K~D
12
CC14 0.22U_0402_16V7K~DCC14 0.22U_0402_16V7K~D
12
CC15 0.22U_0402_16V7K~DCC15 0.22U_0402_16V7K~D
12
CC16 0.22U_0402_16V7K~DCC16 0.22U_0402_16V7K~D
12
CC17 0.22U_0402_16V7K~DCC17 0.22U_0402_16V7K~D
1 2
CC18 0.22U_0402_16V7K~DCC18 0.22U_0402_16V7K~D
1 2
CC19 0.22U_0402_16V7K~DCC19 0.22U_0402_16V7K~D
1 2
CC20 0.22U_0402_16V7K~DCC20 0.22U_0402_16V7K~D
1 2
CC21 0.22U_0402_16V7K~DCC21 0.22U_0402_16V7K~D
1 2
CC22 0.22U_0402_16V7K~DCC22 0.22U_0402_16V7K~D
1 2
CC23 0.22U_0402_16V7K~DCC23 0.22U_0402_16V7K~D
1 2
CC24 0.22U_0402_16V7K~DCC24 0.22U_0402_16V7K~D
1 2
CC25 0.22U_0402_16V7K~DCC25 0.22U_0402_16V7K~D
1 2
CC26 0.22U_0402_16V7K~DCC26 0.22U_0402_16V7K~D
1 2
CC27 0.22U_0402_16V7K~DCC27 0.22U_0402_16V7K~D
1 2
CC28 0.22U_0402_16V7K~DCC28 0.22U_0402_16V7K~D
1 2
CC29 0.22U_0402_16V7K~DCC29 0.22U_0402_16V7K~D
1 2
CC30 0.22U_0402_16V7K~DCC30 0.22U_0402_16V7K~D
1 2
CC31 0.22U_0402_16V7K~DCC31 0.22U_0402_16V7K~D
1 2
CC32 0.22U_0402_16V7K~DCC32 0.22U_0402_16V7K~D
1 2
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15
2
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
6 66Friday, June 10, 2011
6 66Friday, June 10, 2011
6 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 7
5
Follow DG Rev0.71 SM_DRAMPWROK topology
+3.3V_ALW_PCH
CC156 0.1U_0402_25V6K~DCC156 0.1U_0402_25V6K~D
1 2
5
UC2
UC2
1
RUNPWROK<40,41>
+3.3V_ALW_PCH
D D
+1.05V_RUN_VTT
1 2
RC18 200_0402_1%~DRC18 200_0402_1%~D
PM_DRAM_PWRGD<16>
1 2
RC126 56_0402_5%~D@RC126 56_0402_5%~D@
1 2
RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@
1 2
RC44 62_0402_5%~DRC44 62_0402_5%~D
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
P
B
O
2
A
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
RUN_ON_CPU1.5VS3#<11,43>
RUNPWROK_AND PM_DRAM_PWRGD_CPU
4
+1.5V_CPU_VDDQ
RC64
39_0402_5%~D
39_0402_5%~D
1 2
13
D
D
QC1
QC1
2
G
SSM3K7002FU_SC70-3~D
G
SSM3K7002FU_SC70-3~D
S
S
INTEL suggest RC64 and QC1 NO stuff by default
JCPU1B
JCPU1B
4
12
RC12
RC12
200_0402_1%~D
200_0402_1%~D
1 2
RC28 130_0402_1%~DRC28 130_0402_1%~D
@RC64
@
@
@
3
+3.3V_ALW_PCH
12
RC124
@RC124
@
1K_0402_1%~D
1K_0402_1%~D
SYS_PWROK_XDP
The resistor for HOOK2 should beplaced
such that the stub is very small on CFG0 net
H_CPUPWRGD
SIO_PWRBTN#_R<14,16>
CFG0
SYS_PWROK<16,40>
DDR_XDP_WAN_SMBDAT<12,13,14,15,28,35>
DDR_XDP_WAN_SMBCLK<12,13,14,15,28,35>
+1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
Place near JXDP1
1 2
RC5 1K_0402_1%~DRC5 1K_0402_1%~D
1 2
RC6 0_0402_5%~DRC6 0_0402_5%~D
1 2
RC7 1K_0402_1%~DRC7 1K_0402_1%~D
1 2
RC9 0_0402_5%~D@RC9 0_0402_5%~D@
1 2
RC125 0_0402_5%~DRC125 0_0402_5%~D
1 2
RC127 0_0402_5%~DRC127 0_0402_5%~D
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
CC66
CC66
CC65
CC65
2
XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFG10<9>
CFG11<9>
CFG10
CFG11
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
XDP_TCLK
+1.05V_RUN_VTT +1.05V_RUN_VTT
JXDP1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND1
OBSFN_C0
OBSFN_C1
GND3
GND5
GND7
OBSFN_D0
OBSFN_D1
GND9
GND11
GND13
GND15
TRST#
TMS
GND17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
TD0
54
56
TDI
58
60
1
CFG16
CFG17
CFG0
CFG1
CFG2
CFG3
CFG8
CFG9
CFG4
CFG5
CFG6
CFG7
CLK_XDP
CLK_XDP#
XDP_RST#_RXDP_HOOK2
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
CFG16 <9>
CFG17 <9>
CFG0 <9>
CFG1 <9>
CFG2 <9>
CFG3 <9>
CFG8 <9>
CFG9 <9>
CFG4 <9>
CFG5 <9>
CFG6 <9>
CFG7 <9>
Follow check list 0.5
C C
H_PROCHOT#<41,60,62>
H_THERMTRIP#<22>
CPU_DETECT#<40>
PECI_EC<41>
VR1 TOPOLOGY
1 2
RC57 56_0402_5%~DRC57 56_0402_5%~D
1 2
RC129 0_0402_5%~DRC129 0_0402_5%~D
H_CATERR#
H_PROCHOT#_R
Close to JCPU1
H_THERMTRIP#_R
C26
AN34
AL33
AN33
AL32
AN32
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLOCKS
CLOCKS
DDR3
DDR3
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
BCLK
BCLK#
place RC129 near CPU
PRDY#
PREQ#
TCK
H_PM_SYNC<16>
B B
H_CPUPWRGD<18>
RC25 0_0402_5%~DRC25 0_0402_5%~D
Buffered reset to CPU
A A
PCH_PLTRST#<14,17>
5
H_PM_SYNC
VCCPWRGOOD_0_R
1 2
PM_DRAM_PWRGD_CPU
PCH_PLTRST#_R
UC1
UC1
1
NC
VCC
2
A
GND3Y
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
+3.3V_RUN
5
4
AM34
AP33
V8
AR33
+1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
CC140
CC140
2
PCH_PLTRST#_BUF
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
RC4
75_0402_1%~D
RC4
75_0402_1%~D
12
PCH_PLTRST#_R
1 2
RC10 43_0402_5%~DRC10 43_0402_5%~D
JTAG & BPM
JTAG & BPM
4
TRST#
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
TMS
TDO
TDI
CPU_DMI
A28
CPU_DMI#
A27
CPU_DPLL
A16
CPU_DPLL#
A15
Remove DPLL Ref clock (for eDP only)
DDR3_DRAMRST#_CPU
R8
SM_RCOMP0
AK1
SM_RCOMP1
A5
SM_RCOMP2
A4
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCLK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI_R
AR28
XDP_TDO_R
AP26
XDP_DBRESET#_R
AL35
XDP_OBS0_R
AT28
XDP_OBS1_R
AR29
XDP_OBS2_R
AR30
AT30
XDP_OBS4_R XDP_OBS4
AP32
XDP_OBS5_R
AR31
XDP_OBS6_R
AT31
XDP_OBS7_R
AR32
For ESD concern, please put near CPU
VCCPWRGOOD_0_R
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
1 2
RC13 0_0402_5%~DRC13 0_0402_5%~D
1 2
RC15 0_0402_5%~DRC15 0_0402_5%~D
1 2
RC16 1K_0402_1%~DRC16 1K_0402_1%~D
1 2
RC17 1K_0402_1%~DRC17 1K_0402_1%~D
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>H_SNB_IVB#<18>
Max 500mils
RC50
RC50
4.99K_0402_1%~D
4.99K_0402_1%~D
DDR_HVREF_RST_PCH<15>
DDR_HVREF_RST_GATE<41>
XDP_DBRESET#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3XDP_OBS3_R
XDP_OBS5
XDP_OBS6
XDP_OBS7
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
RC130
RC130
10K_0402_5%~D
10K_0402_5%~D
3
12
RC26 0_0402_5%~DRC26 0_0402_5%~D
RC30 0_0402_5%~DRC30 0_0402_5%~D
RC31 0_0402_5%~DRC31 0_0402_5%~D
RC33 0_0402_5%~DRC33 0_0402_5%~D
RC34 0_0402_5%~DRC34 0_0402_5%~D
RC36 0_0402_5%~DRC36 0_0402_5%~D
RC37 0_0402_5%~DRC37 0_0402_5%~D
RC38 0_0402_5%~DRC38 0_0402_5%~D
RC39 0_0402_5%~DRC39 0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.05V_RUN_VTT
RC48 0_0402_5%~D@ RC48 0_0402_5%~D@
12
XDP_DBRESET# <14,16>
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
1 2
D
S
D
S
13
QC2
QC2
G
G
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
2
DDR_HVREF_RST
1
CC177
CC177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
1 2
RC46 0_0402_5%~DRC46 0_0402_5%~D
1 2
RC47 0_0402_5%~D@RC47 0_0402_5%~D@
1 2
RC23 0_0402_5%~DRC23 0_0402_5%~D
XDP_TDO_R XDP_TDO
RC42
RC42
140_0402_1%~D
140_0402_1%~D
1 2
RC24 0_0402_5%~DRC24 0_0402_5%~D
12
12
RC45
RC45
RC43
RC43
200_0402_1%~D
200_0402_1%~D
25.5_0402_1%~D
25.5_0402_1%~D
2
CLK_XDP
CLK_XDP#
DDR3_DRAMRST# <12>
XDP_TDIXDP_TDI_R
12
XDP_RST#_R
RH107 0_0402_5%~DRH107 0_0402_5%~D
RH106 0_0402_5%~DRH106 0_0402_5%~D
CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>
RC8 1K_0402_1%~DRC8 1K_0402_1%~D
1 2
1 2
DDR_HVREF_RST <12>
M3 control
RH109 0_0402_5%~D@RH109 0_0402_5%~D@
RH108 0_0402_5%~D@RH108 0_0402_5%~D@
12
1 2
1 2
PLTRST_XDP# <17>
CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>
PU/PD for JTAG signals
+3.3V_RUN
XDP_DBRESET#
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
RC19 1K_0402_1%~DRC19 1K_0402_1%~D
RC27 51_0402_1%~DRC27 51_0402_1%~D
RC29 51_0402_1%~DRC29 51_0402_1%~D
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
RC35 51_0402_1%~DRC35 51_0402_1%~D
RC40
RC40
RC41
RC41
12
12
12
12
12
12
51_0402_1%~D
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
+1.05V_RUN_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
7 66Friday, June 10, 2011
7 66Friday, June 10, 2011
7 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 8
5
JCPU1C
JCPU1C
D D
C C
B B
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
K2
M8
N8
N7
M9
N9
M7
V6
J1
J5
J4
J2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
4
M_CLK_DDR0
AB6
SA_CK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12>
3
DDR_B_D[0..63]<13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
2
JCPU1D
JCPU1D
M_CLK_DDR2
AE2
SB_CK[0]
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
AP3
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
SB_CLK#[0]
SB_CKE[0]
SB_CK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
1
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_B_MA[0..15] <13>
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
A A
TYCO_2013620-3_IVYBRIDGE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
8 66Friday, June 10, 2011
8 66Friday, June 10, 2011
8 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 9
5
4
3
2
1
CFG Straps for Processor
CFG2
D D
CFG0<7>
CFG1<7>
CFG2<7>
CFG3<7>
CFG4<7>
CFG5<7>
CFG6<7>
CFG7<7>
CFG8<7>
CFG9<7>
CFG10<7>
CFG11<7>
T9 PAD~D@T9 PAD~D@
+VCC_GFXCORE
1 2
RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
C C
+VCC_CORE
B B
RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
1 2
1 2
1 2
VAXG_VAL_SENSE
12
RC69
@RC69
@
100_0402_1%~D
100_0402_1%~D
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
12
RC71
@RC71
@
100_0402_1%~D
100_0402_1%~D
VSS_VAL_SNESE
T10 PAD~D@T10 PAD~D@
T12 PAD~D@T12 PAD~D@
T14 PAD~D@T14 PAD~D@
CFG16<7>
CFG17<7>
T22PAD~D @T22PAD~D @
T28PAD~D @T28PAD~D @
T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~D @
T31PAD~D @T31PAD~D @
T33PAD~D @T33PAD~D @
T35PAD~D @T35PAD~D @
T36PAD~D @T36PAD~D @
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T40PAD~D @T40PAD~D @
T41PAD~D @T41PAD~D @
T42PAD~D @T42PAD~D @
T43PAD~D @T43PAD~D @ T32 PAD~D@T32 PAD~D@
T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @
T46PAD~D @T46PAD~D @
T47PAD~D @T47PAD~D @
T48PAD~D @T48PAD~D @
T52PAD~D @T52PAD~D @
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE
JCPU1E
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
CFG
CFG
RESERVED
RESERVED
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
T39 PAD~D@T39 PAD~D@
T1 PAD~D@T1 PAD~D@
T2 PAD~D@T2 PAD~D@
T3 PAD~D@T3 PAD~D@
T4 PAD~D@T4 PAD~D@
T5 PAD~D@T5 PAD~D@
T6 PAD~D@T6 PAD~D@
T7 PAD~D@T7 PAD~D@
T8 PAD~D@T8 PAD~D@
T11 PAD~D@T11 PAD~D@
T13 PAD~D@T13 PAD~D@
T15 PAD~D@T15 PAD~D@
T16 PAD~D@T16 PAD~D@
T17 PAD~D@T17 PAD~D@
T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@
T20 PAD~D@T20 PAD~D@
T21 PAD~D@T21 PAD~D@
T23 PAD~D@T23 PAD~D@
T24 PAD~D@T24 PAD~D@
T25 PAD~D@T25 PAD~D@
T26 PAD~D@T26 PAD~D@
T27 PAD~D@T27 PAD~D@
T34 PAD~D@T34 PAD~D@
CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>
T49 PAD~D@T49 PAD~D@
T50 PAD~D@T50 PAD~D@
T51 PAD~D@T51 PAD~D@
T53 PAD~D@T53 PAD~D@
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
01: Reserved - (Device 1 function 1 disabled ; function
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
12
@ RC51
@
1K_0402_1%~D
1K_0402_1%~D
CFG4
1K_0402_1%~D
1K_0402_1%~D
CFG6
CFG5
@ RC54
@
RC54
12
12
disabled
2 enabled)
RC51
RC52
@ RC52
@
1K_0402_1%~D
1K_0402_1%~D
12
RC53
@ RC53
@
1K_0402_1%~D
1K_0402_1%~D
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
CFG7
12
@ RC56
@
1K_0402_1%~D
1K_0402_1%~D
RC56
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
9 66Friday, June 10, 2011
9 66Friday, June 10, 2011
9 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 10
5
+VCC_CORE
94A
D D
C C
B B
A A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
4
POWER
JCPU1F
JCPU1F
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
8.5A
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCSENSE_R
VSSSENSE_R
VTT_SENSE
VSSIO_SENSE_R
+1.05V_RUN_VTT
3
Note: Place the PU resistors close to CPU
RC61 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
VIDSCLK <60>
1 2
RC61 43_0402_5%~DRC61 43_0402_5%~D
+1.05V_RUN_VTT
12
RC63
RC63
130_0402_1%~D
130_0402_1%~D
H
_CPU_SVIDALRT# must be routed between the
DSOUT and VIDSCLK lines to reduce cross
VI
talk. 18 mils spacing to others.
Place RC66, RC70, RC75 near CPU
1 2
RC67 0_0402_5%~DRC67 0_0402_5%~D
1 2
RC68 0_0402_5%~DRC68 0_0402_5%~D
RC98 10_0402_1%~DRC98 10_0402_1%~D
10_0402_1%~D
10_0402_1%~D
12
12
RC133
RC133
2
+1.05V_RUN_VTT
12
CAD Note: Place the PU
resistors close to CPU
RC63 close to CPU 300 - 1500mils
VIDSOUT <60>
+VCC_CORE
RC75
@RC75
@
100_0402_1%~D
100_0402_1%~D
1 2
+1.05V_RUN_VTT
VTT_SENSE <58>
VSSIO_SENSE_R <58>
12
12
RC60
RC60
75_0402_1%~D
75_0402_1%~D
RC66
RC66
100_0402_1%~D
100_0402_1%~D
VCCSENSE <60>
VSSSENSE <60>
RC70
RC70
100_0402_1%~D
100_0402_1%~D
VIDALERT_N <60>
1
Iccmax current changed for PDDG Rev0.7
CPU Power Rail Table
Voltage Rail
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM 1.5
Description
*
5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT
Voltage
0.65-1.3
1.05
0.0-1.1
1.8
1.5
.65-0.9
0
S0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16
*
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
10 66Friday, June 10, 2011
10 66Friday, June 10, 2011
10 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 11
5
4
3
2
1
+1.5V_CPU_VDDQ Source
+3.3V_ALW2
12
RC74
RC74
100K_0402_5%~D
2
+VCC_GFXCORE
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
CC176
CC176
1
+
+
2
61
100K_0402_5%~D
RUN_ON_CPU1.5VS3#
QC4A
QC4A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
JCPU1G
JCPU1G
46A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.5A
B6
A6
A2
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
D D
SIO_SLP_S3#<16,28,36,40,43,56>
CPU1.5V_S3_GATE<41>
C C
B B
1 2
RC96 1K_0402_1%~D@RC96 1K_0402_1%~D@
1 2
RC97 1K_0402_1%~D@RC97 1K_0402_1%~D@
A A
+1.8V_RUN
1 2
RC82 0_0402_5%~DRC82 0_0402_5%~D
1 2
RC79 0_0402_5%~D@RC79 0_0402_5%~D@
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC173
CC173
2
2
5
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC175
CC175
CC174
CC174
2
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
+PWR_SRC_S
5
RUN_ON_CPU1.5VS3# <7,43>
4
+1.5V_MEM +1.5V_CPU_VDDQ
12
RC72
RC72
100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3
3
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
QC4B
QC4B
4
POWER
POWER
SENSE
SENSE
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
QC3
QC3
AO4728L_SO8~D
AO4728L_SO8~D
8
7
6
5
330K_0402_1%~D
330K_0402_1%~D
12
RC143
RC143
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VREFMISC
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
1
2
3
1
4
1
2
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
CC136
CC136
+VCC_GFXCORE
AK35
AK34
AL1
+DIMM0_1_VREF_CPU
B4
+DIMM0_1_CA_CPU
D1
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
2
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
RC140 0_0402_5%~DRC140 0_0402_5%~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
CC135
CC135
12
RC99
RC99
10_0402_1%~D
10_0402_1%~D
12
RC100
RC100
10_0402_1%~D
10_0402_1%~D
+V_SM_VREF_CNT
1 2
1
2
20K_0402_5%~D
20K_0402_5%~D
@
@
RC73
RC73
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC161
CC161
2
1
2
3
+1.5V_MEM
@RC76
@
100_0402_1%~D
100_0402_1%~D
1 2
10U_0402_6.3V6M
10U_0402_6.3V6M
CC162
CC162
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
CC168
CC168
+V_DDR_SMREF
1K_0402_1%~D
1K_0402_1%~D
12
@
@
RC80
RC80
1K_0402_1%~D
1K_0402_1%~D
12
@
@
RC81
RC81
RUN_ON_CPU1.5VS3
RC76
VCC_AXG_SENSE <60>
VSS_AXG_SENSE <60>
+V_SM_VREF should
have 10 mil trace width
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
1
CC163
CC163
CC164
CC164
2
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
2
added VCCSA_VID_0 to Power page
1
CC170
CC170
CC169
CC169
2
2
VCCSA_VID_0 <59>
VCCSA_VID_1 <59>
1 2
RC134 0_0402_5%~D@RC134 0_0402_5%~D@
QC5
@QC5
@
NTR4503NT1G_SOT23-3~D
NTR4503NT1G_SOT23-3~D
1
+1.5V_CPU_VDDQ
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC166
CC166
CC165
CC165
+
+
2
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC172
CC172
CC171
CC171
+
+
2
VCCP_PWRCTRL <58>
+1.5V_CPU_VDDQ
1K_0402_1%~D
1K_0402_1%~D
12
3
2
CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D
CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D
CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D
CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D
CC167
CC167
1K_0402_1%~D
1K_0402_1%~D
12
12
12
12
12
+VCC_SA
VCCSA_SENSE <59>
JCPU1H
JCPU1H
AT35
VSS1
RC84
RC84
+V_SM_VREF_CNT
RC78
RC78
6A
+1.5V_MEM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Ivy Bridge (1/6)
Ivy Bridge (1/6)
Ivy Bridge (1/6)
LA-7782
LA-7782
LA-7782
1
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
0.1
0.1
11 66Friday, June 10, 2011
11 66Friday, June 10, 2011
11 66Friday, June 10, 2011
0.1
Page 12
5
+V_DDR_REFA_M3
+V_DDR_REF
D D
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
All VREF traces should
have 10 mil trace width
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
C C
Layout Note:
Place near JDIMM1
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
+1.5V_MEM
B B
A A
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
Layout Note:
Place near JDIMM1.203,204
+0.75V_DDR_VTT
1
2
CD4
CD4
CD3
CD3
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD8
CD8
CD7
CD7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD17
CD17
CD9
CD9
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD18
CD18
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
5
CD6
CD6
CD5
CD5
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
CD10
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD19
CD19
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD11
CD11
CD51
CD51
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD20
CD20
330U_SX_2VY~D
330U_SX_2VY~D
@CD13
@
1
CD13
CD14
CD14
1
+
+
2
2
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
1 2
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
RD7 0_0402_5%~DRD7 0_0402_5%~D
RD1 0_0402_5%~DRD1 0_0402_5%~D
+3.3V_RUN
1 2
1 2
4
+DIMM1_VREF_DQ
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
DDR_A_D0
DDR_A_D1
CD2
1
2
DDR_CKE0_DIMMA<8>
DDR_CS1_DIMMA#<8>
CD2
1
CD1
CD1
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
DDR_A_D2
2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
CD22
CD22
+0.75V_DDR_VTT
CD21
CD21
2
JDIMM1 H=5.2
JDIMM1
CONN@JDIMM1
CONN@
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013289-2~D
TYCO_2-2013289-2~D
3
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
VSS
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
CK1
VDD
BA1
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
2
2-3A to 1 DIMMs/channel
+1.5V_MEM+1.5V_MEM
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
24
26
28
DDR3_DRAMRST#_R
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20DDR_A_D16
40
DDR_A_D21
42
44
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D30
68
DDR_A_D31
70
72
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.75V_DDR_VTT
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
M_ODT0 <8>
M_ODT1 <8>
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
CD15
CD15
1
2
DDR_XDP_WAN_SMBDAT <7,13,14,15,28,35>
DDR_XDP_WAN_SMBCLK <7,13,14,15,28,35>
+DIMM1_VREF_CA
DDR_HVREF_RST<7>
RD11 0_0402_5%~DRD11 0_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CD16
CD16
1
2
DDR3_DRAMRST#_R
+DIMM0_1_VREF_CPU
DDR_HVREF_RST
+DIMM0_1_CA_CPU
DDR_HVREF_RST
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
12
+V_DDR_REF
+1.5V_MEM
12
1 2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
RD29 0_0402_5%~D@RD29 0_0402_5%~D@
1 2
QD1
QD1
D
S
D
S
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
G
G
2
RD30 0_0402_5%~D@RD30 0_0402_5%~D@
1 2
QD2
QD2
D
S
D
S
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
13
G
G
2
RD27
RD27
1K_0402_1%~D
1K_0402_1%~D
1
DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>
+V_DDR_REFA_M3
+V_DDR_REFB_M3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-7782
LA-7782
LA-7782
12 66Friday, June 10, 2011
12 66Friday, June 10, 2011
12 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 13
5
D D
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
C C
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD25
CD25
2
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
B B
A A
10U_0603_6.3V6M~D
CD30
CD30
CD29
CD29
1
1
2
2
Layout Note:
Place near JDIMM2.203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD39
CD39
2
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD26
CD26
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD31
CD31
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD40
CD40
2
2
5
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD27
CD27
CD28
CD28
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD34
CD34
CD33
CD33
CD32
CD32
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD42
CD42
CD41
CD41
2
All VREF traces should
have 10 mil trace width
330U_SX_2VY~D
330U_SX_2VY~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@CD35
@
1
CD36
CD36
CD35
1
+
+
2
2
4
+V_DDR_REFB_M3
+V_DDR_REF
4
+DIMM2_VREF_DQ
1 2
RD8 0_0402_5%~DRD8 0_0402_5%~D
1 2
RD4 0_0402_5%~DRD4 0_0402_5%~D
+3.3V_RUN
RD5 10K_0402_5%~DRD5 10K_0402_5%~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
+3.3V_RUN
12
3
+1.5V_MEM
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
DDR_B_D0
DDR_B_D1
CD24
CD24
1
CD23
CD23
DDR_CKE2_DIMMB<8>
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
DDR_CS3_DIMMB#<8>
2
10K_0402_5%~D
10K_0402_5%~D
12
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+0.75V_DDR_VTT
RD6
RD6
1
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
CD43
CD43
1
CD44
CD44
2
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013310-2~D
TYCO_2-2013310-2~D
CONN@JDIMM2
CONN@
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
NC
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
2
2-3A to 1 DIMMs/channel
+1.5V_MEM
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.75V_DDR_VTT
JDIMM2 H=9.2
DDR3_DRAMRST#_R <12>
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <8>
M_ODT3 <8>
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
CD37
CD37
2
DDR_XDP_WAN_SMBDAT <7,12,14,15,28,35>
DDR_XDP_WAN_SMBCLK <7,12,14,15,28,35>
+DIMM2_VREF_CA
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CD38
CD38
1
2
1
RD15 0_0402_5%~DRD15 0_0402_5%~D
12
+V_DDR_REF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-7782
LA-7782
LA-7782
13 66Friday, June 10, 2011
13 66Friday, June 10, 2011
13 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 14
5
CMOS settingCMOS_CLR1
TPM setting
Clear ME RTC Registers
Keep ME RTC Registers
12
RH38
RH38
330K_0402_1%~D
330K_0402_1%~D
PCH_INTVRMEN
12
RH39
@RH39
@
330K_0402_1%~D
330K_0402_1%~D
1
1
@
@
ME1 SHORT PADS~D
ME1 SHORT PADS~D
1 2
CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D
PCH_AZ_CODEC_SDOUT<30>
PCH_AZ_CODEC_SYNC<30>
PCH_AZ_CODEC_RST#<30>
PCH_AZ_CODEC_BITCLK<30>
27P_0402_50V8J~D
27P_0402_50V8J~D
Clear CMOSShunt
Keep CMOS
CH101
@CH101
@
Open
ME_CLR1
Shunt
Open
+RTC_CELL
D D
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
*
Low - Enable External VRs
C C
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
+3.3V_ALW_PCH
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
+RTC_CELL
2
2
PCH_AZ_SDOUT
1 2
RH29 33_0402_5%~DR H29 33_0402_5%~D
RH26 33_0402_5%~DR H26 33_0402_5%~D
RH27 33_0402_5%~DR H27 33_0402_5%~D
RH25 33_0402_5%~DR H25 33_0402_5%~D
1
2
1 2
1 2
1 2
PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK
+3.3V_ALW_PCH
12
+3.3V_ALW_PCH_JTAG
12
RH66
RH66
1K_0402_1%~D
1K_0402_1%~D
PCH_AZ_SYNC
12
RH282
@RH282
@
100K_0402_5%~D
100K_0402_5%~D
1 2
RH22 20K_0402_5%~DRH22 20K_0402_5%~D
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
1
1
@
@
CMOS1 SHORT PADS~D
CMOS1 SHORT PADS~D
CH4
CH4
CMOS place near DIMM
RH288
RH288
0_0603_5%~D
0_0603_5%~D
2
2
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RH59 51_0402_1%~DRH59 51_0402_1%~D
RH44 200_0402_1%~DRH44 200_0402_1%~D
RH45 200_0402_1%~DRH45 200_0402_1%~D
RH43 200_0402_1%~DRH43 200_0402_1%~D
PCH_AZ_MDC_SDOUT<31>
Follow INTEL CRB 0.7
B B
S
PCH_AZ_SYNC_Q
1 2
RH31 1M_0402_5%~DRH31 1M_0402_5%~D
INTEL HDA_SYNC
isolation circuit
12
R890
R890
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_PCH_CS0# SPI_PCH_CS0#_R
1 2
R935 47_0402_5%~DR935 47_0402_5%~D
SPI_PCH_DIN SPI_DIN64
1 2
R894 33_0402_5%~DR894 33_0402_5%~D
SPI_WP#_SEL SPI_WP#_SEL_R
SPI_WP#_SEL<40>
A A
1 2
R898 0_0402_5%~D@R898 0_0402_5%~D@
S
G
G
2
+5V_RUN
200 MIL SO8
64Mb Flash ROM 16Mb Flash ROM
U52
U52
1
VCC
/CS
2
DO
/HOLD
3
CLK
/WP
GND4DIO
W25Q64CVSSIG_SO8~D
W25Q64CVSSIG_SO8~D
4
CH2
CH2
15P_0402_50V8J~D
15P_0402_50V8J~D
CH3
CH3
15P_0402_50V8J~D
15P_0402_50V8J~D
PCH_AZ_MDC_BITCLK<31>
PCH_AZ_MDC_SYNC<31>
PCH_AZ_MDC_RST#<31>
PCH_AZ_MDC_SDIN1<31>
PCH_AZ_SYNC
SPI_CLK64
R899 33_0402_5%~DR899 33_0402_5%~D
SPI_DO64
R901 33_0402_5%~DR901 33_0402_5%~D
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
USB_MCARD1_DET#
HDD_DET#_R
BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R
12
12
YH1
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
32.768KHZ_12.5PF_Q13FC1350000~D
PCH_RTCX2_R
12
CH100
@CH100
@
27P_0402_50V8J~D
27P_0402_50V8J~D
SPKR<30>
+3.3V_ALW_PCH
12
1 2
1 2
RH286 0_0402_5%~DRH286 0_0402_5%~D
12
RH287 1K_0402_1%~D@RH287 1K_0402_1%~D@
RH36 33_0402_5%~DR H36 33_0402_5%~D
RH50 1K_0402_1%~DRH50 1K_0402_1%~D
12
12
12
RH48
RH48
RH47
RH47
RH49
RH49
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
C746
C746
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
R891
R891
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_HOLD#
SPI_PCH_CLK SPI_PCH_DO
SPI_PCH_DO
USB_OC0#_R<17>
USB_OC1#_R<17>
USB_OC2#<17>
USB_OC3#<17>
USB_OC4#_R<17>
USB_OC5#<17>
USB_OC6#<17>
SIO_EXT_SMI#<17,41>
SLP_ME_CSW_DEV#<18,40>
USB_MCARD1_DET#<18,35>
PCH_GPIO36<18>
PCH_GPIO37<18>
PCH_GPIO16<18>
TEMP_ALERT#<18,40>
PCH_GPIO15<18>
SIO_EXT_SCI#_R<18>
PCH_RSMRST#_Q<16,42>
PCH_AZ_CODEC_SDIN0<30>
ME_FWP<40>
12
12
12
12
D
D
13
QH7
QH7
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
+3.3V_SPI +3.3V_SPI
8
7
6
5
1 2
RH1 33_0402_5%~DPXDP@ RH1 33_0402_5%~DPXDP@
1 2
RH3 33_0402_5%~DPXDP@ RH3 33_0402_5%~DPXDP@
1 2
RH4 33_0402_5%~DPXDP@ RH4 33_0402_5%~DPXDP@
1 2
RH5 33_0402_5%~DPXDP@ RH5 33_0402_5%~DPXDP@
1 2
RH6 33_0402_5%~DPXDP@ RH6 33_0402_5%~DPXDP@
1 2
RH7 33_0402_5%~DPXDP@ RH7 33_0402_5%~DPXDP@
1 2
RH8 33_0402_5%~DPXDP@ RH8 33_0402_5%~DPXDP@
1 2
RH9 33_0402_5%~DPXDP@ RH9 33_0402_5%~DPXDP@
1 2
RH10 33_0402_5%~DPXDP@ RH10 33_0402_5%~DPXDP@
1 2
RH12 33_0402_5%~DPXDP@ RH12 33_0402_5%~DPXDP@
1 2
RH13 33_0402_5%~DPXDP@ RH13 33_0402_5%~DPXDP@
1 2
RH14 33_0402_5%~DPXDP@ RH14 33_0402_5%~DPXDP@
1 2
RH15 33_0402_5%~DPXDP@ RH15 33_0402_5%~DPXDP@
1 2
RH16 33_0402_5%~DPXDP@ RH16 33_0402_5%~DPXDP@
1 2
RH17 33_0402_5%~DPXDP@ RH17 33_0402_5%~DPXDP@
1 2
RH18 33_0402_5%~DPXDP@ RH18 33_0402_5%~DPXDP@
1 2
RH19 33_0402_5%~DPXDP@ RH19 33_0402_5%~DPXDP@
1 2
RH20 33_0402_5%~DPXDP@ RH20 33_0402_5%~DPXDP@
1 2
RH24 1K_0402_1%~DPXDP@ RH24 1K_0402_1%~DPXDP@
PCH_RTCX1
1 2
1 2
RH32 33_0402_5%~DR H32 33_0402_5%~D
1 2
RH33 33_0402_5%~DR H33 33_0402_5%~D
1 2
RH34 33_0402_5%~DR H34 33_0402_5%~D
1 2
1 2
1 2
USB30_SMI#<29>
100_0402_1%~D
100_0402_1%~D
SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_PCH_DIN SPI_DIN32
SPI_WP#_SEL_R
12
RH2
RH2
10M_0402_5%~D
10M_0402_5%~D
R936 47_0402_5%~DR936 47_0402_5%~D
R895 33_0402_5%~DR895 33_0402_5%~D
RSMRST#_XDP
DDR_XDP_WAN_SMBDAT<7,12,13,15,28,35>
PCH_RTCX2
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_SYNCPCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_MDC_SDIN1
PCH_AZ_SDOUT
PCH_GPIO33
USB30_SMI#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
1 2
1 2
3
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
DDR_XDP_WAN_SMBCLK<7,12,13,15,28,35>
A20
C20
D20
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
+3.3V_ALW_PCH
1
PXDP@
PXDP@
CH1
CH1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
RH284 0_0402_5%~DPXDP@ RH284 0_0402_5%~DPXDP@
RH285 0_0402_5%~DPXDP@ RH285 0_0402_5%~DPXDP@
JTAG
JTAG
RH283 1K_0402_1%~DPXDP@ RH283 1K_0402_1%~DPXDP@
RH21 0_0402_5%~DPXDP@ RH21 0_0402_5%~DPXDP@
1 2
1 2
RTCIHDA
RTCIHDA
SPI
SPI
1.05V_0.8V_PWROK<41,60>
SIO_PWRBTN#_R<7,16>
UH4A
UH4A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_ EN# / GPIO33
HDA_DOCK_ RST# / GPIO 13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
BBS_BIT0 - BIOS BOOT STRAP BIT 0
200 MIL SO8
U53
U53
1
2
3
4
W25Q32BVSSIG_SO8~D
W25Q32BVSSIG_SO8~D
8
CS#
VCC
7
DO
HOLD#
6
WP#
CLK
5
GND
DI
1.05V_0.8V_PWROK_R
1 2
PCH_PWRBTN#_XDP
1 2
DDR_XDP_WAN_SMBDAT_R2
DDR_XDP_WAN_SMBCLK_R2
FWH0 / L AD0
FWH1 / L AD1
FWH2 / L AD2
FWH3 / L AD3
LPC
LPC
FWH4 / L FRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA
SATA
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
R897 33_0402_5%~DR897 33_0402_5%~D
SPI_DO32
R900 33_0402_5%~DR900 33_0402_5%~D
+3.3V_ALW_PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
LPC_LAD0
C38
LPC_LAD1
A38
LPC_LAD2
B37
LPC_LAD3
C37
LPC_LFRAME#
D36
LPC_LDRQ0#
E36
LPC_LDRQ1#
K36
IRQ_SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
C745
C745
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
1 2
1 2
2
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A 0
11
OBSDATA_A 1
13
GND4
15
OBSDATA_A 2
17
OBSDATA_A 3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B 0
29
OBSDATA_B 1
31
GND10
33
OBSDATA_B 2
35
OBSDATA_B 3
37
GND12
39
PWRGOO D/HOOK0
41
HOOK1
43
VCC_OBS_ AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
LPC_LFRAME# <33,35,40,41>
LPC_LDRQ0# <40>
LPC_LDRQ1# <40>
IRQ_SERIRQ <33,40,41>
PSATA_PRX_DTX_N0_C <28>
PSATA_PRX_DTX_P0_C <28>
PSATA_PTX_DRX_N0_C <28>
PSATA_PTX_DRX_P0_C <28>
SATA_ODD_PRX_DTX_N1_C <29>
SATA_ODD_PRX_DTX_P1_C <29>
SATA_ODD_PTX_DRX_N1_C <29>
SATA_ODD_PTX_DRX_P1_C <29>
ESATA_PRX_DTX_N4_C <38>
ESATA_PRX_DTX_P4_C <38>
ESATA_PTX_DRX_N4_C <38>
ESATA_PTX_DRX_P4_C <38>
SATA_PRX_DKTX_N5_C <39>
SATA_PRX_DKTX_P5_C <39>
SATA_PTX_DKRX_N5_C <39>
SATA_PTX_DKRX_P5_C <39>
SATA_COMP
SATA3_COMP
RBIAS_SATA3
SATA_ACT#
HDD_DET#_R
BBS_BIT0_R
1 2
RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D
1 2
RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D
1 2
RH46 750_0402_1%~DRH46 750_0402_1%~D
D
D
1 3
QH1 BSS138W-7-F_SOT323-3~D
QH1 BSS138W-7-F_SOT323-3~D
PCH_PLTRST#<7,17>
SPI_HOLD#
SPI_PCH_CLKSPI_CLK32
JXDP2
JXDP2
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK 4
ITPCLK#/HOOK5
VCC_OBS_ CD
RESET#/HOO K6
DBR#/HOOK 7
LPC_LAD0 <33,35,40,41>
LPC_LAD1 <33,35,40,41>
LPC_LAD2 <33,35,40,41>
LPC_LAD3 <33,35,40,41>
+1.05V_RUN
+1.05V_RUN
SATA_ACT# <44>
1 2
RH290 0_0402_5%~DRH290 0_0402_5%~D
S
S
G
G
2
JSPI1
JSPI1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
G1
18
G2
HRS_FH12-16S-0P5SH(55)~D
HRS_FH12-16S-0P5SH(55)~D
CONN@
CONN@
GND1
GND3
GND5
GND7
GND9
GND11
GND13
GND15
TD0
TRST#
TDI
TMS
GND17
SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
SPI_PCH_CS0#
PCH_SPI_CS0#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
XDP_FN16
XDP_FN17
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
RSMRST#_XDP
XDP_DBRESET#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMSPCH_JTAG_TCK
PCH_GPIO33
RH355 100K_0402_5%~DRH355 100K_0402_5%~D
IRQ_SERIRQ
RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D
BBS_BIT0_R
HDD
INTEL feedback 0302
ODD/ E Module Bay
SPKR
No Reboot Strap
SPKR
E-SATA
DOCK
+3.3V_RUN
12
RH30
RH30
10K_0402_5%~D
10K_0402_5%~D
PCH_SATA_MOD_EN# <41>
1 2
RH345 0_0402_5%~DRH345 0_0402_5%~D
1 2
RH346 0_0402_5%~DRH346 0_0402_5%~D
1 2
RH347 0_0402_5%~DRH347 0_0402_5%~D
1 2
RH348 0_0402_5%~DRH348 0_0402_5%~D
1 2
RH349 0_0402_5%~DRH349 0_0402_5%~D
+3.3V_M
1 2
RH350 0_0402_5%~DRH350 0_0402_5%~D
+3.3V_ALW_PCH
XDP_DBRESET# <7,16>
+3.3V_RUN
12
12
12
RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D
+3.3V_RUN
12
RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@
Low = Default
High = No Reboot
HDD_DET# <28>
+3.3V_SPI
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/8)
PCH (1/8)
ze Document Number Rev
PCH (1/8)
LA-7782
LA-7782
LA-7782
14 66Friday, June 10, 2011
14 66Friday, June 10, 2011
14 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 15
5
D D
PCIE_PRX_WANTX_N1<35>
WWAN (Mini Card 1)--->
WLAN (Mini Card 2)--->
EXPRESS Card--->
E3 Module Bay--->
1/2 MINI CARD-3 PCIE
(Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
WWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI --->
B B
PP (Mini Card 3)--->
Express card--->
WLAN (Mini Card 2)--->
eModule Bay--->
A A
PCIE_PRX_WANTX_P1<35>
PCIE_PTX_WANRX_N1<35>
PCIE_PTX_WANRX_P1<35>
PCIE_PRX_WLANTX_N2<35>
PCIE_PRX_WLANTX_P2<35>
PCIE_PTX_WLANRX_N2<35>
PCIE_PTX_WLANRX_P2<35>
PCIE_PRX_EXPTX_N3<36>
PCIE_PRX_EXPTX_P3<36>
PCIE_PTX_EXPRX_N3<36>
PCIE_PTX_EXPRX_P3<36>
PCIE_PRX_EMBTX_N4<29>
PCIE_PRX_EMBTX_P4<29>
PCIE_PTX_EMBRX_N4<29>
PCIE_PTX_EMBRX_P4<29>
PCIE_PRX_WPANTX_N5<35>
PCIE_PRX_WPANTX_P5<35>
PCIE_PTX_WPANRX_N5<35>
PCIE_PTX_WPANRX_P5<35>
PCIE_PRX_MMITX_N6<34>
PCIE_PRX_MMITX_P6<34>
PCIE_PTX_MMIRX_N6<34>
PCIE_PTX_MMIRX_P6<34>
PCIE_PRX_GLANTX_N7<32>
PCIE_PRX_GLANTX_P7<32>
PCIE_PTX_GLANRX_N7<32>
PCIE_PTX_GLANRX_P7<32>
CLK_PCIE_MINI1#<35>
CLK_PCIE_MINI1<35>
+3.3V_ALW_PCH
MINI1CLK_REQ#<35>
CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>
LANCLK_REQ#<32>
CLK_PCIE_MMI#<34>
CLK_PCIE_MMI<34>
+3.3V_RUN
MMICLK_REQ#<34>
CLK_PCIE_MINI3#<35>
CLK_PCIE_MINI3<35>
+3.3V_ALW_PCH
MINI3CLK_REQ#<35>
CLK_PCIE_EXP#<36>
CLK_PCIE_EXP<36>
+3.3V_ALW_PCH
EXPCLK_REQ#<36>
CLK_PCIE_MINI2#<35>
CLK_PCIE_MINI2<35>
+3.3V_ALW_PCH
MINI2CLK_REQ#<35>
+3.3V_ALW_PCH
CLK_PCIE_EMB#<29>
CLK_PCIE_EMB<29>
+3.3V_ALW_PCH
EMBCLK_REQ#<29>
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
RH307 0_0402_5%~DRH307 0_0402_5%~D
RH308 0_0402_5%~DRH308 0_0402_5%~D
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
RH82 0_0402_5%~DRH82 0_0402_5%~D
RH83 0_0402_5%~DRH83 0_0402_5%~D
RH85 0_0402_5%~DRH85 0_0402_5%~D
RH86 0_0402_5%~DRH86 0_0402_5%~D
RH87 10K_0402_5%~DRH87 10K_0402_5%~D
RH88 0_0402_5%~DRH88 0_0402_5%~D
RH90 0_0402_5%~DRH90 0_0402_5%~D
RH152 10K_0402_5%~DRH152 10K_0402_5%~D
RH92 0_0402_5%~DRH92 0_0402_5%~D
RH93 0_0402_5%~DRH93 0_0402_5%~D
RH94 10K_0402_5%~DRH94 10K_0402_5%~D
RH95 0_0402_5%~DRH95 0_0402_5%~D
RH96 0_0402_5%~DRH96 0_0402_5%~D
RH97 10K_0402_5%~DRH97 10K_0402_5%~D
RH98 10K_0402_5%~DRH98 10K_0402_5%~D
RH310 0_0402_5%~DRH310 0_0402_5%~D
RH312 0_0402_5%~DRH312 0_0402_5%~D
RH104 10K_0402_5%~DRH104 10K_0402_5%~D
RH280 0_0402_5%~DRH280 0_0402_5%~D
RH281 0_0402_5%~DRH281 0_0402_5%~D
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
5
1 2
1 2
4
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_MMI#
PCIE_MMI
MMICLK_REQ#
PCIE_MINI3#
PCIE_MINI3
MINI3CLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PEG_B_CLKRQ#
PCIE_EMB#
PCIE_EMB
EMBCLK_REQ#
CLK_BCLK_ITP#
CLK_BCLK_ITP
UH4B
UH4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
3
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
PCH_GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
GFX_CLK_REQ#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
PCI_TPM_TCM
SIO_14M
CLK_80H
JETWAY_14M
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
2
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <32>
LAN_SMBDATA <32>
SML1_SMBCLK <41>
SML1_SMBDATA <41>
PCH_CL_CLK1 <35>
PCH_CL_DATA1 <35>
PCH_CL_RST1# <35>
CLK_PCIE_VGA# <45>
CLK_PCIE_VGA <45>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_PCI_LOOPBACK <17>
1 2
RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D
RH311 22_0402_5%~DRH311 22_0402_5%~D
RH313 22_0402_5%~DRH313 22_0402_5%~D
RH314 22_0402_5%~DRH314 22_0402_5%~D
RH315 22_0402_5%~D@RH315 22_0402_5%~D@
12
12
12
12
2
+3.3V_RUN
QH5A
QH5A
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
3
4
QH5B
QH5B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
+3.3V_ALW_PCH
SML1_SMBCLK
SML1_SMBDATA
DDR_HVREF_RST_PCH
PCH_GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
LAN_SMBCLK
LAN_SMBDATA
3.3V_RUN_GFX_ON<40,49>
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
DDR_XDP_WAN_SMBCLK <7,12,13,14,28,35>
DDR_XDP_WAN_SMBDAT <7,12,13,14,28,35>
RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D
RH300 1K_0402_1%~DRH300 1K_0402_1%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
RH304 10K_0402_5%~DRH304 10K_0402_5%~D
RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D
RH80
RH80
10K_0402_5%~D
10K_0402_5%~D
RH74 10K_0402_5%~DRH74 10K_0402_5%~D
RH75 10K_0402_5%~DRH75 10K_0402_5%~D
RH91 10K_0402_5%~DRH91 10K_0402_5%~D
RH76 10K_0402_5%~DRH76 10K_0402_5%~D
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
RH183 10K_0402_5%~DRH183 10K_0402_5%~D
CLOCK TERMINATION for FCIM and need close to PCH
12
+1.05V_RUN
CLK_PCI_TPM_TCM <33>
CLK_SIO_14M <40>
PCLK_80H <35>
JETWAY_CLK14M <33>
RH309 0_0402_5%~DRH309 0_0402_5%~D
RH99
RH99
1M_0402_5%~D
1M_0402_5%~D
25MHZ_10PF_Q22FA2380049900~D
25MHZ_10PF_Q22FA2380049900~D
2
CH18
CH18
1
12P_0402_50V8J~D
12P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8)
PCH (2/8)
PCH (2/8)
LA-7782
LA-7782
LA-7782
1
1 2
1 2
12
13
D
D
2
G
G
S
S
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3
OUT
4
GND
1
+3.3V_ALW_PCH
+3.3V_ALW_PCH
12
12
12
12
12
+3.3V_LAN
12
12
GFX_CLK_REQ#
QH2
QH2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
12
YH2
YH2
1
IN
2
GND
15 66Friday, June 10, 2011
15 66Friday, June 10, 2011
15 66Friday, June 10, 2011
2
CH19
CH19
1
12P_0402_50V8J~D
12P_0402_50V8J~D
0.1
0.1
0.1
Page 16
5
+3.3V_ALW_PCH
1 2
RH318 10K_0402_5%~D@ RH318 10K_0402_5%~D@
1 2
RH144 10K_0402_5%~DRH144 10K_0402_5%~D
1 2
D D
+3.3V_RUN
C C
B B
SYS_PWROK<7,40>
RESET_OUT#<41>
PM_APWROK<41>
PM_DRAM_PWRGD<7>
PCH_RSMRST#_Q<14,42>
ME_SUS_PWR_ACK<41>
SIO_PWRBTN#_R<7,14>
SIO_PWRBTN#<41>
AC_PRESENT<41>
+3.3V_ALW_PCH
A A
RH142 10K_0402_5%~DRH142 10K_0402_5%~D
1 2
RH319 10K_0402_5%~D@ RH319 10K_0402_5%~D@
1 2
RH140 10K_0402_5%~DRH140 10K_0402_5%~D
1 2
RH137 8.2K_0402_5%~DRH137 8.2K_0402_5%~D
1 2
RH138 8.2K_0402_5%~D@RH138 8.2K_0402_5%~D@
+1.05V_RUN
1 2
RH111 49.9_0402_1%~DRH111 49.9_0402_1%~D
1 2
RH112 750_0402_1%~DRH112 750_0402_1%~D
SUSACK#<40> PCH_DPWROK <40>
SUS_STAT#/LPCPD#
ME_SUS_PWR_ACK
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_RI#
CLKRUN#
ME_RESET#
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
DMI_COMP_R
RBIAS_CPY
1 2
RH114 0_0402_5%~D@ RH114 0_0402_5%~D@
1 2
RH116 0_0402_5%~DRH116 0_0402_5%~D
1 2
RH117 0_0402_5%~DRH117 0_0402_5%~D
1 2
RH118 0_0402_5%~DRH118 0_0402_5%~D
1 2
RH320 0_0402_5%~DRH320 0_0402_5%~D
1 2
RH120 0_0402_5%~DRH120 0_0402_5%~D
1 2
RH121 0_0402_5%~DRH121 0_0402_5%~D
1 2
RH122 0_0402_5%~DRH122 0_0402_5%~D
1 2
RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PM_DRAM_PWRGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#_R
AC_PRESENT
PCH_BATLOW#
PCH_RI#
XDP_DBRESET#<7,14>
RH141 8.2K_0402_5%~D@RH141 8.2K_0402_5%~D@
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R SUSACK#_R
UH4C
UH4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
4
RH357 0_0402_5%~DRH357 0_0402_5%~D
1 2
+3.3V_RUN
UC3
@UC3
@
1
ME_RESET#
12
1 2
RH113 0_0402_5%~DRH113 0_0402_5%~D
1 2
RH321 0_0402_5%~D@ RH321 0_0402_5%~D@
1 2
RH323 0_0402_5%~DRH323 0_0402_5%~D
DMI
DMI
System Power Management
System Power Management
2
SYS_PWROKRESET_OUT#
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
FDI
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
CH99
@CH99
@
1 2
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
P
B
4
O
A
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
H_PM_SYNC
SIO_SLP_LAN#
SYS_RESET#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
RH127 330K_0402_1%~DRH127 330K_0402_1%~D
1 2
RH129 330K_0402_1%~D@RH129 330K_0402_1%~D@
1 2
3
PCH_CRT_BLU
1 2
RH131 150_0402_1%~DRH131 150_0402_1%~D
RH132 150_0402_1%~DRH132 150_0402_1%~D
RH133 150_0402_1%~DRH133 150_0402_1%~D
RH134 100K_0402_5%~DRH134 100K_0402_5%~D
1 2
1 2
1 2
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
Disabled
LOW: RH129 STUFFED,
RH127 UNSTUFFED
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 <6>
FDI_LSYNC1 <6>
PCH_PCIE_WAKE# <41>
CLKRUN# <33,40,41>
T56 PAD~DT56 PAD~D
T57 PAD~DT57 PAD~D
T58 PAD~DT58 PAD~D
SIO_SLP_S5# <41>
T59 PAD~DT59 PAD~D
SIO_SLP_S4# <40>
SIO_SLP_S3# <11,28,36,40,43,56>
SIO_SLP_A# <40,43,57>
T62 PAD~DT62 PAD~D
SIO_SLP_SUS# <40>
T63 PAD~DT63 PAD~D
H_PM_SYNC <7>
SIO_SLP_LAN# <32,40>
Minimum speacing of 20mils for LVD_IBG
+RTC_CELL
PCH_CRT_HSYNC<25>
PCH_CRT_VSYNC<25>
2.2K_0402_5%~D
2.2K_0402_5%~D
@
@
PANEL_BKEN_PCH<24>
ENVDD_PCH<24,40>
BIA_PWM_PCH<24>
LDDC_CLK_PCH<23>
LDDC_DATA_PCH<23>
1 2
RH344 2.37K_0402_1%~DRH344 2.37K_0402_1%~D
LCD_ACLK-_PCH<23>
LCD_ACLK+_PCH<23>
LCD_A0-_PCH<23>
LCD_A1-_PCH<23>
LCD_A2-_PCH<23>
LCD_A0+_PCH<23>
LCD_A1+_PCH<23>
LCD_A2+_PCH<23>
LCD_BCLK-_PCH<23>
LCD_BCLK+_PCH<23>
LCD_B0-_PCH<23>
LCD_B1-_PCH<23>
LCD_B2-_PCH<23>
LCD_B0+_PCH<23>
LCD_B1+_PCH<23>
LCD_B2+_PCH<23>
PCH_CRT_BLU<25>
PCH_CRT_GRN<25>
PCH_CRT_RED<25>
RH123 20_0402_1%~DRH123 20_0402_1%~D
1 2
1 2
RH124 20_0402_1%~DRH124 20_0402_1%~D
1K_0402_0.5%~D
1K_0402_0.5%~D
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
RH316
RH316
PANEL_BKEN_PCH
ENVDD_PCH
BIA_PWM_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
LVD_IBG
LCD_ACLK-_PCH
LCD_ACLK+_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
LCD_BCLK-_PCH
LCD_BCLK+_PCH
LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH
LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
HSYNC
VSYNC
CRT_IREF
12
RH126
RH126
2
@
@
RH317
RH317
MAX14885EETL has internal 3K pu for
PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
Intel request DDPB can not support eDP
UH4D
UH4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
PCH_CRT_DDC_CLK <25>
PCH_CRT_DDC_DAT <25>
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8)
PCH (3/8)
PCH (3/8)
LA-7782
LA-7782
LA-7782
1
16 66Friday, June 10, 2011
16 66Friday, June 10, 2011
16 66Friday, June 10, 2011
0.1
0.1
0.1
Page 17
+3.3V_RUN
5
4
3
2
1
PLTRST_GPU#<45>
PLTRST_USH#<33>
PLTRST_MMI#<34>
PLTRST_XDP#<7>
PLTRST_LAN#<32>
PLTRST_EMB#<29>
PCH_PLTRST#
5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LCD_CBL_DET#
BT_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
+3.3V_RUN
5
1
P
B
2
A
G
3
1 2
RH343 0_0402_5%~DRH343 0_0402_5%~D
1 2
RH335 0_0402_5%~DRH335 0_0402_5%~D
1 2
RH336 0_0402_5%~DRH336 0_0402_5%~D
1 2
RH337 0_0402_5%~DRH337 0_0402_5%~D
1 2
RH338 0_0402_5%~DRH338 0_0402_5%~D
1 2
RH340 0_0402_5%~DRH340 0_0402_5%~D
CLK_PCI_5048<40>
CLK_PCI_MEC<41>
CLK_PCI_DOCK<39>
CLK_PCI_LOOPBACK<15>
CH102
CH102
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
UH3
UH3
PCH_PLTRST#_EC
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PCIE_MCARD2_DET#<35>
BT_DET#<42>
LCD_CBL_DET#<24>
CAM_MIC_CBL_DET#<24>
HDD_FALL_INT<28>
RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 22_0402_5%~DRH103 22_0402_5%~D
RH105 22_0402_5%~DRH105 22_0402_5%~D
PCH_PLTRST#_EC <33,35,36,40,41>
1 2
RH334 0_0402_5%~DRH334 0_0402_5%~D
12
12
12
12
4
USB3RN1<37>
USB3RN2<37>
USB3RN4<39>
USB3RP1<37>
USB3RP2<37>
USB3RP4<39>
USB3TN1<37>
USB3TN2<37>
USB3TN4<39>
USB3TP1<37>
USB3TP2<37>
USB3TP4<39>
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
BT_DET#
BBS_BIT1
PCI_GNT3#
LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
T104PAD~D @T104PAD~D @
PCH_PLTRST#
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
FFS_PCH_INT
UH4E
UH4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3TP1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
RSVD
RSVD
USB30
USB30
PCI
PCI
USB
USB
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
0 0
0 1
1 0
1 1
LPC
Reserved (NAND)
PCI
SPI
3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBP13USBP13+
USBRBIAS
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
USBP0- <37>
USBP0+ <37>
USBP1- <37>
USBP1+ <37>
USBP2- <38>
USBP2+ <38>
USBP3- <39>
USBP3+ <39>
USBP4- <35>
USBP4+ <35>
USBP5- <35>
USBP5+ <35>
USBP6- <35>
USBP6+ <35>
USBP7- <33>
USBP7+ <33>
USBP8- <39>
USBP8+ <39>
USBP9- <31>
USBP9+ <31>
USBP10- <36>
USBP10+ <36>
USBP11- <42>
USBP11+ <42>
USBP12- <24>
USBP12+ <24>
USBP13- <24>
USBP13+ <24>
1 2
RH151
RH151
22.6_0402_1%~D
22.6_0402_1%~D
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
1 2
RH339 0_0402_5%~DRH339 0_0402_5%~D
1 2
RH341 0_0402_5%~DRH341 0_0402_5%~D
1 2
RH356 0_0402_5%~DRH356 0_0402_5%~D
SIO_EXT_SMI#
BBS_BIT1
----->Right Side Top
----->Right Side Bottom
----->Right side E-SATA
----->MLK DOCK
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash
----->USH
----->DOCK
----->Left side
----->Express Card
----->Blue Tooth
----->Camera
----->LCD Touch
USB_OC0# <37>
USB_OC1# <37>
USB_OC2# <14>
USB_OC3# <14>
USB_OC4# <31>
USB_OC5# <14>
USB_OC6# <14>
SIO_EXT_SMI# <14,41>
USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC4#_R <14>
12
RH342
@RH342
@
1K_0402_1%~D
1K_0402_1%~D
2
INTEL feedback 0307
USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
RPH1
RPH1
4 5
3 6
2 7
1 8
RPH2
RPH2
4 5
3 6
2 7
1 8
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/8)
PCH (4/8)
PCH (4/8)
LA-7782
LA-7782
LA-7782
17 66Friday, June 10, 2011
17 66Friday, June 10, 2011
17 66Friday, June 10, 2011
1
0.1
0.1
0.1
1 2
D D
C C
RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D
1 2
RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~DRH327 10K_0402_5%~D
1 2
RH330 10K_0402_5%~DRH330 10K_0402_5%~D
1 2
RH328 10K_0402_5%~DRH328 10K_0402_5%~D
1 2
RH332 10K_0402_5%~D@RH332 10K_0402_5%~D@
1 2
RH331 10K_0402_5%~DRH331 10K_0402_5%~D
PCI_GNT3#
12
RH333
@RH333
@
1K_0402_1%~D
1K_0402_1%~D
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
A A
PCH_PLTRST#<7,14>
Low = A16 swap
High = Default
Page 18
5
4
3
2
1
+3.3V_ALW_PCH
RH53
RH53
4.7K_0402_5%~D
D D
C C
B B
A A
4.7K_0402_5%~D
1 2
SLP_ME_CSW_DEV#
12
RH353
RH353
1K_0402_1%~D
1K_0402_1%~D
@
@
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
+3.3V_ALW_PCH
SIO_EXT_WAKE#
RH177 10K_0402_5%~DRH177 10K_0402_5%~D
RH354 1K_0402_1%~DRH354 1K_0402_1%~D
+3.3V_ALW_PCH
RH170 10K_0402_5%~DRH170 10K_0402_5%~D
+3.3V_RUN
RH171 10K_0402_5%~D@RH171 10K_0402_5%~D@
RH173 1K_0402_1%~D@RH173 1K_0402_1%~D@
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH181 10K_0402_5%~DRH181 10K_0402_5%~D
RH178 10K_0402_5%~DRH178 10K_0402_5%~D
1 2
RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D
1 2
RH163 10K_0402_5%~DRH163 10K_0402_5%~D
1 2
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
12
12
12
12
12
12
12
PCH_GPIO15
PCH_GPIO36
12
PCH_GPIO37
12
PCH_GPIO17
12
PCH_GPIO16
12
KB_DET#
PCH_GPIO36
PCH_GPIO37
TEMP_ALERT#
PCH_GPIO22
PCH_GPIO7
PCH_GPIO17
IO_LOOP#
PCH_GPIO16
5
1 2
INTEL feedback 0302
RH174 10K_0402_5%~DRH174 10K_0402_5%~D
RH172 10K_0402_5%~DRH172 10K_0402_5%~D
RH273 1K_0402_1%~D@RH273 1K_0402_1%~D@
RH265 10K_0402_5%~D@RH265 10K_0402_5%~D@
SIO_EXT_SCI#_R<14>
SIO_EXT_SCI#<41>
IO_LOOP#<31>
SIO_EXT_WAKE#<40>
PM_LANPHY_ENABLE<32>
PCH_GPIO15<14>
DBC_ENABLE for E4 12"
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
PCH_GPIO16<14>
PCIE_MCARD1_DET#<35>
E3_PAID_TS_DET#<24>
SLP_ME_CSW_DEV#<14,40>
DGPU_HOLD_RST#<45>
USB_MCARD1_DET#<14,35>
PCH_GPIO36<14>
PCH_GPIO37<14>
TEMP_ALERT#<14,40>
KB_DET#<42>
+3.3V_RUN
TPM_ID0
FFS_INT2<28>
RH267
1@ RH267
1@
10K_0402_5%~D
10K_0402_5%~D
1 2
RH270
2@ RH270
2@
10K_0402_5%~D
10K_0402_5%~D
1 2
SIO_EXT_SCI#
1 2
RH259 0_0402_5%~DRH259 0_0402_5%~D
USH_DET#
IO_LOOP#
PCH_GPIO7
PM_LANPHY_ENABLE
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO22
E3_PAID_TS_DET#
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#
USB_MCARD1_DET#
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
+3.3V_RUN
TPM_ID1
4
12
RH268
3@ RH268
3@
20K_0402_5%~D
20K_0402_5%~D
12
RH271
4@ RH271
4@
2.2K_0402_5%~D
2.2K_0402_5%~D
UH4F
UH4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
China TPM
No TPM, No China TPM
TBD
TPM
GPIO
GPIO
NCTF
NCTF
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
0
0
1 1
3
TPM_ID1TPM_ID0
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
0
1
CONTACTLESS_DET#
PCIE_MCARD3_DET#
SIO_A20GATE
SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R
INIT3_3V#
DF_TVS
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
CONTACTLESS_DET# <33>
DGPU_PWROK <40,64>USH_DET#<33>
PCIE_MCARD3_DET# <35>
USB_MCARD2_DET# <35>
SIO_A20GATE <41>
SIO_RCIN# <41>
H_CPUPWRGD <7>
T106PAD~D@T106PAD~D
@
T108PAD~D @T108PAD~D @
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
1
2
H_SNB_IVB#<7>
2
+1.05V_RUN_VTT
12
RH262 56_0402_5%~DRH262 56_0402_5%~D
CH97
CH97
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
RH150 0_0402_5%~DRH150 0_0402_5%~D
CONTACTLESS_DET#
RH256 10K_0402_5%~DRH256 10K_0402_5%~D
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
USH_DET#
PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
+VCCDFTERM
12
RH158 10K_0402_5%~DRH158 10K_0402_5%~D
RH203 10K_0402_5%~DRH203 10K_0402_5%~D
1 2
RH263 10K_0402_5%~DRH263 10K_0402_5%~D
1 2
RH164 100K_0402_5%~DRH164 100K_0402_5%~D
RH149 need to close to CPU
RH149
RH149
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
RH358 1K_0402_1%~DRH358 1K_0402_1%~D
DMI & FDI Termination Voltage
DF_TVS
Set to Vss when LOW
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/8)
PCH (5/8)
PCH (5/8)
LA-7782
LA-7782
LA-7782
+3.3V_RUN
12
+3.3V_RUN
12
12
DF_TVSDF_TVS_R
0.1
0.1
18 66Friday, June 10, 2011
18 66Friday, June 10, 2011
18 66Friday, June 10, 2011
1
0.1
Page 19
5
4
3
2
1
LH1
POWER
+1.05V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH30
CH30
CH32
CH32
2
D D
+1.05V_RUN
+1.05V_RUN
C C
+3.3V_RUN
B B
@ RH247
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
1 2
RH247
CH51
CH51
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
2
+1.05V_RUN
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH46
CH45
CH45
2
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
CH46
CH44
CH44
+1.05V_RUN_VTT
1
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH33
CH33
1
2
1
CH47
CH47
2
1U_0402_6.3V6K~D
1
CH31
CH31
2
+VCCAPLLEXP
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
CH40
CH40
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH48
CH48
+VCCAPLL_FDI
UH4G
UH4G
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
DMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
DFT / SPI HVCMOS
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
+VCCADAC
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CH34
CH34
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CH103
CH103
2
1
CH43
CH43
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCCLKDMI
1
CH50
CH50
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CH52
CH52
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+VCCSPI
1
CH54
CH54
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH35
CH35
2
1 2
+VCCDFTERM
LH1
BLM18PG181SN1_0603~D
BLM18PG181SN1_0603~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CH36
CH36
2
+1.8V_RUN_LVDS
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CH104
CH104
2
+3.3V_RUN
CH49
CH49
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
RH205 0_0603_5%~DRH205 0_0603_5%~D
1
CH106
CH106
2
RH276
@RH276
@
0_0805_5%~D
0_0805_5%~D
PJP66
@PJP66
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
RH202 0_0603_5%~DRH202 0_0603_5%~D
RH204 0_0603_5%~D@RH204 0_0603_5%~D@
12
+3.3V_RUN
100NH_HK1608R10J-T_5%_0603~D
100NH_HK1608R10J-T_5%_0603~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH105
CH105
1
2
+1.05V_RUN_VTT
12
INTEL feedback 0302
12
12
12
INTEL feedback 0307
LH8
LH8
12
0.1uH inductor, 200mA
CPN: SHI0110BJ0L
+1.05V_RUN
+3.3V_RUN
+1.8V_RUN
+3.3V_M
+3.3V_RUN
+3.3V_RUN
+1.8V_RUN
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1
1.05
1.05
1.1
.05
S0 Iccmax
Current (A)
0.001
5
5
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
VccASW
VccSPI
VccDSW3_3 0.001
1.05
3.3
3.3
0.903
0.01
1.8 0.002VCCDFTERM
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
0.095
0.01
VccVRM 1.5 0.167
1.05VccClkDMI 0.07
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.04
+1.05V_RUN
+VCCAPLL_FDI
1 2
RH195 0.022_0805_1%@RH195 0.022_0805_1%@
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
RH197 0_0603_5%~DRH197 0_0603_5%~D
A A
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
PCH (6/8)
PCH (6/8)
PCH (6/8)
LA-7782
LA-7782
LA-7782
19 66Tuesday, June 07, 2011
19 66Tuesday, June 07, 2011
19 66Tuesday, June 07, 2011
1
0.1
0.1
0.1
of
Page 20
5
4
3
2
1
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW2
D D
+1.05V_RUN
C C
+3.3V_RUN
1 2
RH215 0.022_0805_1%RH215 0.022_0805_1%
Note: If EMI concern, pop
with SHI00008S0L, 10UH +-20%
1 2
RH201 0_0402_5%~DRH201 0_0402_5%~D
1 2
RH253 0_0402_5%~D@RH253 0_0402_5%~D@
LH3
@ LH3
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
+1.05V_M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
+1.05V_RUN
@
@
CH58
CH58
2
+3.3V_RUN_VCC_CLKF33
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
@
@
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH73
CH73
2
Note: Place VCCDIFFCLKN with a trace
specially for XCLK_RCOMP (RH100.2)
B B
+1.05V_M
RH248 0.022_0805_1%@RH248 0.022_0805_1%@
A A
+1.05V_RUN
1 2
+1.05V_M_VCCSUS
+1.05V_RUN_VTT
+1.05V_RUN
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
5
1
CH85
CH85
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
LH6
LH6
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
1 2
LH7
LH7
1
CH96
CH96
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1
CH94
CH94
+
+
2
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
1 2
RH200 0.022_0805_1%@RH200 0.022_0805_1%@
CH55
CH55
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
@
@
CH57
CH57
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH64
CH64
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH67
CH67
2
CH74
CH74
1
CH78
CH78
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
CH79
CH79
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
1
CH84
CH84
2
1
1
CH87
CH87
CH86
CH86
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH92
CH92
1U_0402_6.3V6K~D
1
CH93
CH93
CH95
CH95
1
+
+
2
2
+VCCACLK
1
2
1
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH65
CH65
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH68
CH68
2
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
CH81
CH81
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+VCCSST
+1.05V_M_VCCSUS
1
CH83
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+RTC_CELL
1
2
4
+VCCDSW3_3
+PCH_VCCDSW
+3.3V_RUN_VCC_CLKF33
+VCCAPLL_CPY_PCH
+VCCSUS1
@
@
CH61
CH61
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH69
CH69
+VCCRTCEXT
@CH83
@
1
CH88
CH88
CH89
CH89
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
UH4J
UH4J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3[5]
BH23
VCCAPLLDMI2
AL29
VCCIO[14]
AL24
DCPSUS[3]
AA19
VCCASW[1]
AA21
VCCASW[2]
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
AD29
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
DCPRTC
Y49
VCCVRM[4]
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO[7]
AF33
VCCDIFFCLKN[1]
AF34
VCCDIFFCLKN[2]
AG34
VCCDIFFCLKN[3]
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS[1]
V19
DCPSUS[2]
BJ8
V_PROC_IO
A22
VCCRTC
1
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
CH90
CH90
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
POWER
POWER
N26
VCCIO[29]
P26
VCCIO[30]
P28
VCCIO[31]
T27
VCCIO[32]
T29
VCCIO[33]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
V5REF
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
VCCAPLLSATA
SATA USB
SATA USB
VCCASW[22]
VCCASW[23]
HDA
HDA
VCCASW[21]
VCCSUSHDA
3
CPURTC
CPURTC
1
CH56
CH56
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CH59
CH59
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+PCH_V5REF_SUS
+VCCA_USBSUS
+PCH_V5REF_RUN
1
2
1
CH91
CH91
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
2
CH70
CH70
1U_0603_10V7K~D
1U_0603_10V7K~D
+3.3V_RUN
1
CH76
CH76
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN
CH60
CH60
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH66
CH66
2
1
CH72
CH72
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH82
CH82
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
2
+1.05V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN
CH75
CH75
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH77
CH77
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
@CH80
@
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
+1.05V_M
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CRB 0.7 RH208,RH213 trace width 20mil.
+3.3V_RUN
+1.05V_RUN
LH5
@LH5
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
CH80
+1.05V_RUN
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
D
1 3
QH4
RH208
RH208
RH213
RH213
PCH (7/8)
PCH (7/8)
PCH (7/8)
LA-7782
LA-7782
LA-7782
QH4
+3.3V_ALW_PCH+5V_ALW_PCH
12
+3.3V_RUN+5V_RUN
12
+VCCA_USBSUS
+1.05V_RUN
1
2
21
1
2
21
1
2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
ALW_ENABLE<43>
10_0402_1%~D
10_0402_1%~D
10_0402_1%~D
10_0402_1%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+5V_ALW_PCH+5V_ALW
S
S
1
CH98
CH98
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH62
@CH62
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
20 66Friday, June 10, 2011
20 66Friday, June 10, 2011
20 66Friday, June 10, 2011
12
G
G
DH2
DH2
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_SUS
CH63
CH63
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DH3
DH3
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_RUN
CH71
CH71
1U_0603_10V7K~D
1U_0603_10V7K~D
RH278
RH278
20K_0402_5%~D
20K_0402_5%~D
0.1
0.1
0.1
Page 21
5
D D
C C
B B
A A
UH4H
UH4H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
4
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
UH4I
UH4I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (8/8)
PCH (8/8)
PCH (8/8)
LA-7782
LA-7782
LA-7782
21 66Monday, May 23, 2011
21 66Monday, May 23, 2011
21 66Monday, May 23, 2011
1
0.1
0.1
0.1
Page 22
5
4
3
2
1
DSC only
+FAN1_VOUT
1 2
12
R403
R403
10K_0402_5%~D
10K_0402_5%~D
SMSC request
1 2
VGA_THERMDN
VGA_THERMDP
BC_INT#_EMC4022
FAN1_TACH_FB
FAN1_DET#
EMC4022_GPIO2
ACAV_IN <41,62,63>
BC_INT#_EMC4022 <41>
R3934.7K_0402_5%~D R3934.7K_0402_5%~D
JFAN1
+FAN1_VOUT
Place under CPU
Place C266 close to the Q12 as possible
C
C
C
E
E
3 1
Q14
Q14
H_THERMTRIP#<7>
THERMTRIP_VGA#<45>
C
E
E
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
2
B
B
+1.05V_RUN_VTT
2
B
B
Q12
Q12
100P_0402_50V8J~D
100P_0402_50V8J~D
1
31
@
@
C277
C277
C
C
2
R398
R398
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
PMST3904_SOT323-3~D
PMST3904_SOT323-3~D
+3.3V_RUN_GFX
10K_0402_5%~D
10K_0402_5%~D
@
@
12
R400
R400
PMST3904_SOT323-3~D
PMST3904_SOT323-3~D
E
E
B
B
2
Q13
Q13
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
2
B
B
Q15
Q15
2.2K_0402_5%~D
2.2K_0402_5%~D
12
THERMB3
@
@
D D
100P_0402_50V8J~D
100P_0402_50V8J~D
C C
100P_0402_50V8J~D
100P_0402_50V8J~D
B B
2
C266
C266
1
(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14
(2) DP5/DN5 for Skin on Q13, place Q13 close to Vcore VR choke.
1
C272
@C272
@
2
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
+3.3V_M
12
C
C
E
E
3 1
R399
R399
REM_DIODE1_P_4022
REM_DIODE1_N_4022
REM_DIODE2_P_4022
REM_DIODE2_N_4022
R395
R395
8.2K_0402_5%~D
8.2K_0402_5%~D
THERMATRIP2#
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
+3.3V_M
12
C
C
2
B
B
E
E
Q115
Q115
3 1
C278
C278
R396
R396
8.2K_0402_5%~D
8.2K_0402_5%~D
THERMATRIP3#
1
2
C279
C279
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+5V_RUN
1
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0805_10V6K~D
10U_0805_10V6K~D
C275
C275
C276
C276
1
+3.3V_RUN
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C738
C738
C305
C305
1
1
2
2
MAX8731_IINP<62>
RB751S40T1_SOD523-2~DD2RB751S40T1_SOD523-2~D
D2
2 1
1 2
R1639 0_0603_5%~DR1639 0_0603_5%~D
+3.3V_M
R389 10K_0402_5%~DR389 10K_0402_5%~D
1 2
C270 2200P_0402_50V7K~DC270 2200P_0402_50V7K~D
1 2
C271 2200P_0402_50V7K~DC271 2200P_0402_50V7K~D
PCH_PWRGD#<41>
FAN1_DET#
FAN1_TACH_FB
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C219
C219
1
2
+3.3V_RUN_EMC_VDDL
VDD_PWRGD
1 2
1 2
R391 1K_0402_1%~DR391 1K_0402_1%~D
+RTC_CELL
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C282
C282
2
REM_DIODE1_N_4022
REM_DIODE1_P_4022
REM_DIODE2_N_4022
REM_DIODE2_P_4022
VGA_THERMDP
VGA_THERMDN
12
VSET_4022
FAN1_TACH_FB
EMC4022_GPIO2
FAN1_DET#
12
R406
R406
953_0402_1%~D
953_0402_1%~D
1
2
3
4
MOLEX_53398-0471~D
MOLEX_53398-0471~D
VCP2
R3874.7K_0402_5%~D R3874.7K_0402_5%~D
3V_PWROK#
1
2
VSET_4022
JFAN1
1
2
5
3
G1
6
4
G2
CONN@
CONN@
U9
U9
2
VDDH
3
VDDH
6
VDDL
13
VDD_PWRGD
23
DN1/THERM
24
DP1/VREF_T
26
DN2/DP4
27
DP2/DN4
30
DP3/DN5
29
DN3/DP5
31
VCP
25
VIN
28
VSET
10
TACH/GPIO1
11
GPIO2
15
GPIO3/PWM/THERMTRIP_SIO
12
3V_PWROK#
16
RTC_PWR3V
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
EMC4022-1-EZK-TR_QFN32_5X5~D
EMC4022-1-EZK-TR_QFN32_5X5~D
C274
C274
THERMTRIP2#
THERMTRIP3#
POWER_SW#
ACAVAIL_CLR
ATF_INT#/BC_IRQ#
SMCLK/BC_CLK
SMDATA/BC_DATA
ADDR_MODE/XEN
POWER_SW#
17
18
FAN_OUT
FAN_OUT
VDD
TEST1
TEST2
VSS
19
20
21
9
5
4
8
7
1
32
14
22
33
U10
U10
SYS_SHDN#
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
THERMATRIP2#
THERMATRIP3#
POWER_SW#
BC_INT#_EMC4022
+VCC_4022
+ADDR_XEN
+RTC_CELL
5
P
4
O
G
3
B
A
C281 0.1U_0402_25V6K~DC281 0.1U_0402_25V6K~D
1
2
1
2
1 2
R390 47K_0402_1%~D@R390 47K_0402_1%~D@
BC_CLK_EMC4022 <41>
BC_DAT_EMC4022 <41>
+VCC_4022
DOCK_PWR_SW# <41>
POWER_SW_IN# <41>
VGA_THERMDN <46>
C1104
C1104
470P_0402_50V7K~D
470P_0402_50V7K~D
VGA_THERMDP <46>
12
R385 10K_0402_5%~DR385 10K_0402_5%~D
12
R426 10K_0402_5%~DR426 10K_0402_5%~D
12
R402 10K_0402_5%~DR402 10K_0402_5%~D
12
R404 10K_0402_5%~DR404 10K_0402_5%~D
THERM_STP# <54>
+RTC_CELL
+3.3V_M
12
R388
R388
22_0402_5%~D
22_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C273
C273
C1179
C1179
2
2
+3.3V_M
Rest=953, Tp=88degree
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FAN & Thermal Sensor
FAN & Thermal Sensor
FAN & Thermal Sensor
LA-7782
LA-7782
LA-7782
22 66Friday, June 10, 2011
22 66Friday, June 10, 2011
22 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 23
5
4
3
2
1
Channel A
U84
U84
LCD_ACLK+_GPU<46>
D D
C C
LCD_ACLK-_GPU<46>
LCD_A2+_GPU<46>
LCD_A2-_GPU<46>
LCD_A1+_GPU<46>
LCD_A1-_GPU<46>
LCD_A0+_GPU<46>
LCD_A0-_GPU<46>
LDDC_CLK_GPU<45>
LDDC_DATA_GPU<45>
LCD_ACLK+_PCH<16>
LCD_ACLK-_PCH<16>
LCD_A2+_PCH<16>
LCD_A2-_PCH<16>
LCD_A1+_PCH<16>
LCD_A1-_PCH<16>
LCD_A0+_PCH<16>
LCD_A0-_PCH<16>
LDDC_CLK_PCH<16>
LDDC_DATA_PCH<16>
LDDC_CLK_GPU
LDDC_DATA_GPU
LDDC_CLK_PCH
LDDC_DATA_PCH
31
NC0+
30
NC0-
26
NC1+
25
NC1-
22
NC2+
21
NC2-
18
NC3+
17
NC3-
5
AUX1B
13
AUX1A
33
AUX1
29
NO0+
28
NO0-
24
NO1+
23
NO1-
20
NO2+
19
NO2-
16
NO3+
15
NO3-
6
AUX2B
14
AUX2A
32
AUX2
MAX14979EETX+T_TQFN36_6X6~D
MAX14979EETX+T_TQFN36_6X6~D
COM0+
COM0-
COM1+
COM1-
COM2+
COM2-
COM3+
COM3AUX0A
AUX0B
AUX0
GND
TPAD
V+
SEL
35
36
1
2
3
7
8
9
10
4
12
34
27
11
37
DGPU_SELECT#
+3.3V_RUN +3.3V_RUN
0.1U_0402_25V6K~D
@C1146
0.1U_0402_25V6K~D
@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C1146
C1145
C1145
1
1
2
2
SW_LVDS_ACLK+ <24>
SW_LVDS_ACLK- <24>
SW_LVDS_A2+ <24>
SW_LVDS_A2- <24>
SW_LVDS_A1+ <24>
SW_LVDS_A1- <24>
SW_LVDS_A0+ <24>
SW_LVDS_A0- <24>
LDDC_DATA_SW <24>
DGPU_SELECT# <24,25,40>
0
1
ChanelSEL
COM=NO
Source
GPUCOM=NC
PCH
LCD_BCLK+_GPU<46>
LCD_BCLK-_GPU<46>
LCD_B2+_GPU<46>
LCD_B2-_GPU<46>
LCD_B1+_GPU<46>
LCD_B1-_GPU<46>
LCD_B0+_GPU<46>
LCD_B0-_GPU<46>
LCD_BCLK+_PCH<16>
LCD_BCLK-_PCH<16>LDDC_CLK_SW <24>
LCD_B2+_PCH<16>
LCD_B2-_PCH<16>
LCD_B1+_PCH<16>
LCD_B1-_PCH<16>
LCD_B0+_PCH<16>
LCD_B0-_PCH<16>
Channel B
U85
U85
31
NC0+
30
NC0-
26
NC1+
25
NC1-
22
NC2+
21
NC2-
18
NC3+
17
NC3-
5
AUX1B
13
AUX1A
33
AUX1
29
NO0+
28
NO0-
24
NO1+
23
NO1-
20
NO2+
19
NO2-
16
NO3+
15
NO3-
6
AUX2B
14
AUX2A
32
AUX2
MAX14979EETX+T_TQFN36_6X6~D
MAX14979EETX+T_TQFN36_6X6~D
COM0+
COM0-
COM1+
COM1-
COM2+
COM2-
COM3+
COM3AUX0A
AUX0B
AUX0
GND
TPAD
V+
SEL
35
36
1
2
3
7
8
9
10
4
12
34
DGPU_SELECT#
27
11
37
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
@C1150
@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C1150
C1149
C1149
1
2
SW_LVDS_BCLK+ <24>
SW_LVDS_BCLK- <24>
SW_LVDS_B2+ <24>
SW_LVDS_B2- <24>
SW_LVDS_B1+ <24>
SW_LVDS_B1- <24>
SW_LVDS_B0+ <24>
SW_LVDS_B0- <24>
0
1
ChanelSEL
COM=NO
Source
GPUCOM=NC
PCH
+3.3V_RUN_GFX
B B
A A
+3.3V_RUN
1 2
R1122 2.2K_0402_5%~DR1122 2.2K_0402_5%~D
1 2
R1121 2.2K_0402_5%~DR1121 2.2K_0402_5%~D
1 2
R1124 2.2K_0402_5%~DR1124 2.2K_0402_5%~D
1 2
R1123 2.2K_0402_5%~DR1123 2.2K_0402_5%~D
LDDC_CLK_GPU
LDDC_DATA_GPU
LDDC_CLK_PCH
LDDC_DATA_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
LVDS SW
LVDS SW
LVDS SW
LA-7782
LA-7782
LA-7782
23 66Friday, June 10, 2011
23 66Friday, June 10, 2011
23 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 24
5
JLVDS1
JLVDS1
BATT_WHITE_LED
BATT_YELLOW_LED
BREATH_WHITE_LED
D D
C C
DISP_ON/OFF#
CONNTST_GND
LCD_B_CLK+
LCD_B_CLK-
LVDS_A_CLK+
LVDS_A_CLK-
46
MGND6
45
MGND5
44
MGND4
43
MGND3
42
MGND2
41
MGND1
ACES_59003-0400C-001
ACES_59003-0400C-001
CONN@
CONN@
GND
VR_SRC
VR_SRC
VR_SRC
PWM
VR_GND
VR_GND
VR_GND
GND
LVDS_B2+
LVDS_B2-
LVDS_B1+
LVDS_B1-
LVDS_B0+
LVDS_B0-
GND
GND
LVDS_A2+
LVDS_A2-
LVDS_A1+
LVDS_A1-
LVDS_A0+
LVDS_A0-
EDID_DATA
EDID_CLK
BIST
V_EDID
LCD_VDD
LCD_VDD
CONNTST
NC
DGPU_SELECT#<23,25,40>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BIA_PWM_LVDS
12
1 2
C246 0.1U_0603_50V7K~DC246 0.1U_0603_50V7K~D
1 2
LE92 BLM18BB221SN1D_2P~DLE92 BLM18BB221SN1D_2P~D
LDDC_DATA_SW
LDDC_CLK_SW
LCD_TST
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
R1137
R1137
10K_0402_5%~D
10K_0402_5%~D
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
+5V_ALW for panel side LED power
+5V_ALW
BATT_WHITE_LED <44>
BATT_YELLOW_LED <44>
BREATH_WHITE_LED <44>
+BL_PWR_SRC
DISP_ON
BIA_PWM_LVDS
SW_LVDS_B2+ <23>
SW_LVDS_B2- <23>
SW_LVDS_B1+ <23>
SW_LVDS_B1- <23>
SW_LVDS_B0+ <23>
SW_LVDS_B0- <23>
SW_LVDS_A2+ <23>
SW_LVDS_A2- <23>
SW_LVDS_A1+ <23>
SW_LVDS_A1- <23>
SW_LVDS_A0+ <23>
SW_LVDS_A0- <23>
LDDC_DATA_SW <23>
LDDC_CLK_SW <23>
LCD_TST <40>
+3.3V_RUN
+LCDVDD
LCD_CBL_DET# <17>
D66
D66
21
+3.3V_RUN
U3
U3
5
1
P
4
OE#
A2Y
G
74AHCT1G125GW_SOT353-5~D
74AHCT1G125GW_SOT353-5~D
3
D68
D68
21
For Webcam
B B
Q23
+CAMERA_VDD
10U_0805_10V6K~D
10U_0805_10V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C300
C300
C299
C299
1
1
2
2
CCD_OFF<40>
CCD_OFF
Webcam PWR CTRL
A A
Q23
PMV65XP_SOT23-3~D
PMV65XP_SOT23-3~D
D
S
D
S
1 3
G
G
2
+3.3V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C301
C301
1
2
4
PANEL_HDD_LED <44>
5P_0402_50V8C~D
5P_0402_50V8C~D
1
1
@
@
C40
C40
2
2
5P_0402_50V8C~D
5P_0402_50V8C~D
1
1
@
@
C42
C42
2
2
BIA_PWM_PCH <16>
C244
C244
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
BIA_PWM_GPU <45>
BIA_PWM_EC <41>
USBP12-<17>
USBP12+<17>
SW_LVDS_BCLK+ <23>
5P_0402_50V8C~D
5P_0402_50V8C~D
SW_LVDS_BCLK- <23>
@
@
C41
C41
SW_LVDS_ACLK+ <23>
5P_0402_50V8C~D
5P_0402_50V8C~D
SW_LVDS_ACLK- <23>
@
@
C43
C43
DISP_ON
+CAMERA_VDD
JCAM1
JCAM1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
G1
10
G2
JST_BM08B-SRSS-TB1-LF-SN~D
JST_BM08B-SRSS-TB1-LF-SN~D
CONN@
CONN@
USBP12- USBP12_D-
USBP12+
+3.3V_RUN
Place near to JLVDS1
+LCDVDD
Close to JLVDS1.42,43
12
R1138
R1138
100K_0402_5%~D
100K_0402_5%~D
CAM_MIC_CBL_DET#
USBP12_D+
USBP12_D-
DMIC_CLK
DMIC0
3
1
L10
@L10
@
DLW21SN121SQ2L_4P~D
DLW21SN121SQ2L_4P~D
4
4
1
1
1 2
R427 0_0402_5%~DR427 0_0402_5%~D
1 2
R428 0_0402_5%~DR428 0_0402_5%~D
1 2
R159 2.2K_0402_5%~DR159 2.2K_0402_5%~D
1 2
R160 2.2K_0402_5%~DR160 2.2K_0402_5%~D
1
2
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
2
D8
PESD5V0U2BT_SOT23-3~DD8PESD5V0U2BT_SOT23-3~D
3
2
LDDC_CLK_SW
LDDC_DATA_SW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C298
C298
D67
D67
D64
D64
D69
D69
CAM_MIC_CBL_DET# <17>
DMIC_CLK <30>
DMIC0 <30>
3
USBP12_D+
2
3
+3.3V_RUN
Close to JLVD1.41
21
PANEL_BKEN_PCH <16>
21
PANEL_BKEN_DGPU <45>
21
PANEL_BKEN_EC <40>
2
LCD Power
+3.3V_ALW
+LCDVDD
130_0402_1%~D
130_0402_1%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
12
R413
R413
D53
D53
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
ENVDD_PCH<16,40>
LCD_VCC_TEST_EN<40>
ENVDD_GPU<45>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C243
C243
1
2
2 1
D6
D6
2
1
3
BAT54CW_SOT323-3~D
BAT54CW_SOT323-3~D
61
Q19A
Q19A
EN_LCDPWR
2
Q20
Q20
PDTC124EU_SC70-3~D
PDTC124EU_SC70-3~D
1
2
2
40mil
1000P_0402_50V7K~D
1000P_0402_50V7K~D
C297
C297
EN_INVPWR<41>
+PWR_SRC_S +3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
12
R414
R414
5
13
+PWR_SRC
12
R422
R422
100K_0402_5%~D
100K_0402_5%~D
1 2
R423 47K_0402_5%~DR423 47K_0402_5%~D
12
R412
R412
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q19B
Q19B
4
FDC654P-G_SSOT-6~D
FDC654P-G_SSOT-6~D
4 5
PWR_SRC_ON
EN_INVPWR
+LCDVDD
4 5
1M_0402_5%~D
1M_0402_5%~D
12
R1632
R1632
Q21
Q21
D
D
S
S
G
G
3
Q22
Q22
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
D
1 3
1
Q18
Q18
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
S
S
6
2
1
G
G
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C293
C293
1
2
40mil
6
2
1
1
C296
C296
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
2
S
S
G
G
2
FDC654P: P CHANNAL
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C292
C292
1
2
+BL_PWR_SRC
Panel backlight power control by EC
Touch Screen Connector
+5V_TSP +5V_RUN+5V_RUN
Q32
10K_0402_5%~D
10K_0402_5%~D
12
R431
R431
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q125A
Q125A
TOUCH_SCREEN_PD#<40>
2
3
Q125B
Q125B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
Q32
PMV65XP_SOT23-3~D
PMV65XP_SOT23-3~D
D
S
D
S
1 3
G
G
2
USBP13-<17>
USBP13+<17>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C306
C306
1
2
E3_PAID_TS_DET#<18>
2
3
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
1
Place close JTCH1
+5V_TSP
JTCH1
JTCH1
D86
@D86
@
1
2
3
4
5
6
1
2
3
4
5
6
CONN@
CONN@
8
G2
G1
TYCO_1734595-6
TYCO_1734595-6
7
+5V_TSP
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C302
C302
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP & CAM &TS Conn
eDP & CAM &TS Conn
eDP & CAM &TS Conn
LA-7782
LA-7782
LA-7782
24 66Friday, June 10, 2011
24 66Friday, June 10, 2011
24 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 25
2
1
+5V_RUN
U18
U18
MAX14885E
MAX14885E
7
REDA
17
REDB
8
GRNA
18
GRNB
9
BLUA
19
BLUB
5
SCLA
15
SCLB
6
SDAA
16
SDAB
2
EN
3
SHA
13
SHB
4
SVA
14
SVB
1
S00
40
S01
39
S10
38
S11
30
GND
20
GND
10
GND
41
GPAD
MAX14885EETL+T_TQFN40_5X5~D
MAX14885EETL+T_TQFN40_5X5~D
0
0
0
0
1
GPU_CRT_CLK_DDC<45>
GPU_CRT_DAT_DDC<45>
+3.3V_RUN
GPU_CRT_RED<45>
PCH_CRT_RED<16>
GPU_CRT_GRN<45>
PCH_CRT_GRN<16>
GPU_CRT_BLU<45>
PCH_CRT_BLU<16>
PCH_CRT_DDC_CLK<16>
PCH_CRT_DDC_DAT<16>
1 2
R416 100K_0402_5%~DR416 100K_0402_5%~D
GPU_CRT_HSYNC<45>
PCH_CRT_HSYNC<16>
GPU_CRT_VSYNC<45>
PCH_CRT_VSYNC<16>
EDID_SELECT#<40>
CRT_SWITCH<40>
DGPU_SELECT#<23,24,40>
CRT_EN
CRT_SWITCH
CRT_SWITCH
B B
Channel A --> GPU
C
hannel B --> PCH
CRT_SWITCH
DGPU_SELECT#
EDID_SELECT#
VCC
VCC
RED1
RED2
GRN1
GRN2
BLU1
BLU2
SCL1
SCL2
SDA1
SDA2
SH1
SH2
SV1
SV2
29
21
11
VL
33
24
32
23
31
22
35
26
34
25
37
28
36
27
12
NC
1 1
01 1
1
C1182
C1182
1U_0603_10V7K~D
1U_0603_10V7K~D
2
RED_CRT <31>
RED_DOCK <39>
GREEN_CRT <31>
GREEN_DOCK <39>
BLUE_CRT <31>
BLUE_DOCK <39>
CLK_DDC2_CRT <31>
CLK_DDC2_DOCK <39>
DAT_DDC2_CRT <31>
DAT_DDC2_DOCK <39>
HSYNC_BUF <31>
HSYNC_DOCK <39>
VSYNC_BUF <31>
VSYNC_DOCK <39>
10
+3.3V_RUN
1
C1181
C1181
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
Port 1 --> MB Port RGB
Port 2 --> Docking Port RGB
A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CRT/Video switch
CRT/Video switch
CRT/Video switch
LA-7782
LA-7782
LA-7782
25 66Friday, June 10, 2011
25 66Friday, June 10, 2011
25 66Friday, June 10, 2011
0.1
0.1
0.1
Page 26
2
+5V_RUN
21
3
D4
D4
NC
NC
BAT1000-7-F_SOT23-3~D
BAT1000-7-F_SOT23-3~D
+5V_RUN_HDMI
+3.3V_RUN
12
PJP54
@PJP54
@
PAD-OPEN1x1m
PAD-OPEN1x1m
OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
OUT4p
OUT4n
HPDX
SDA
SCL
Close to U19 VCC pins
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
C354
C354
1
2
TMDSE_RP_P2
22
TMDSE_RP_N2
23
TMDSE_RP_P1
19
TMDSE_RP_N1
20
TMDSE_RP_P0
16
TMDSE_RP_N0
17
TMDSE_RP_CLK
13
TMDSE_RP_CLK#
14
7
8
9
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C355
C355
1
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@
@
@
@
C340
C340
C342
C342
1
1
1
2
2
2
DPE_GPU_HPD <45>
TMDS_E_GPU_DDC# <46>
TMDS_E_GPU_DDC <46>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@
@
C344
C344
HIGH LOW MID
NoSetting1 Setting2
EnableAPD (Auto power down) Disable
High level Mid level
Low level
+3.3V_RUN_HDMI
46
2
15
21
U19
39
38
42
41
45
44
48
47
30
32
34
25
29
28
12
11
27
33
10
35
4
1
6
3
U19
IN1p
IN1n
IN2p
IN2n
IN3p
IN3n
IN4p
IN4n
HPD_SINK
DDC_EN
DDCBUF
OE#
SDA_SINK
SCL_SINK
PIO
ASQ0
ASQ1
APD
EMI0
EMI1
REXT
PEQ
CEXT
PRE
B B
C346 0.1U_0402_10V7K~DC346 0.1U_0402_10V7K~D
TMDSE_GPU_P2<46>
TMDSE_GPU_N2<46>
TMDSE_GPU_P1<46>
TMDSE_GPU_N1<46>
TMDSE_GPU_P0<46>
TMDSE_GPU_N0<46>
TMDSE_GPU_CLK<46>
TMDSE_GPU_CLK#<46>
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
+5V_RUN
21
0_0402_5%~D
0_0402_5%~D
12
A A
@
@
R1168
R1168
D70
D70
HDMI_HPD_SINK
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
+5V_HDMI_DDC
+3.3V_RUN_HDMI
+3.3V_RUN_HDMI
12
R443
R443
4.7K_0402_5%~D
4.7K_0402_5%~D
HDMI_OE#
13
D
D
2
G
G
S
S
1 2
R476 4.7K_0402_5%~D@R476 4.7K_0402_5%~D@
1 2
R478 4.7K_0402_5%~D@R478 4.7K_0402_5%~D@
1 2
R480 4.7K_0402_5%~D@R480 4.7K_0402_5%~D@
1 2
R482 4.7K_0402_5%~D@R482 4.7K_0402_5%~D@
1 2
R484 4.7K_0402_5%~D@R484 4.7K_0402_5%~D@
1 2
R486 4.7K_0402_5%~D@R486 4.7K_0402_5%~D@
12
C347 0.1U_0402_10V7K~DC347 0.1U_0402_10V7K~D
12
C348 0.1U_0402_10V7K~DC348 0.1U_0402_10V7K~D
12
C349 0.1U_0402_10V7K~DC349 0.1U_0402_10V7K~D
12
C350 0.1U_0402_10V7K~DC350 0.1U_0402_10V7K~D
12
C351 0.1U_0402_10V7K~DC351 0.1U_0402_10V7K~D
12
C352 0.1U_0402_10V7K~DC352 0.1U_0402_10V7K~D
12
C353 0.1U_0402_10V7K~DC353 0.1U_0402_10V7K~D
12
R472 4.7K_0402_5%~DR472 4.7K_0402_5%~D
1 2
R473 4.7K_0402_5%~D@R473 4.7K_0402_5%~D@
1 2
R474 4.7K_0402_5%~D@R474 4.7K_0402_5%~D@
R460 1.5K_0402_5%~DR460 1.5K_0402_5%~D
1 2
R461 1.5K_0402_5%~DR461 1.5K_0402_5%~D
1 2
R475 4.7K_0402_5%~DR475 4.7K_0402_5%~D
1 2
Q25
Q25
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
TMDSE_GPU_C_P2
TMDSE_GPU_C_N2
TMDSE_GPU_C_P1
TMDSE_GPU_C_N1
TMDSE_GPU_C_P0
TMDSE_GPU_C_N0
TMDSE_GPU_C_CLK
TMDSE_GPU_C_CLK#
12
499_0402_1%~D
499_0402_1%~D
12
R467
R467
HDMI_PIO
R477 4.7K_0402_5%~D@R477 4.7K_0402_5%~D@
1 2
HDMI_APD
R479 4.7K_0402_5%~D@R479 4.7K_0402_5%~D@
1 2
HDMI_EMI0
R481 4.7K_0402_5%~D@R481 4.7K_0402_5%~D@
1 2
HDMI_EMI1
R483 4.7K_0402_5%~D@R483 4.7K_0402_5%~D@
1 2
HDMI_PEQ
R485 4.7K_0402_5%~D@R485 4.7K_0402_5%~D@
1 2
HDMI_PRE
R487 4.7K_0402_5%~D@R487 4.7K_0402_5%~D@
1 2
+3.3V_RUN_HDMI
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C358
C358
1
2
HDMI_HPD_SINK
HDMI_OE#
HDMI_SDA_SINK
HDMI_SCL_SINK
HDMI_PIO
HDMI_APD
HDMI_EMI0
HDMI_EMI1
HDMI_PEQ
HDMI_PRE
26
VCC540VCC6
VCC1
VCC2
VCC3
VCC4
GND5
GND324GND4
GND2
GND1
GND637GND7
GND8
PS8171QFN48G_QFN48_7X7
36
31
18
PS8171QFN48G_QFN48_7X7
43
49
5
DDCBUF (Active Buffer)
PIO (HPD setting) HPD=HPD_SINKHPD=HPD_SINK#
PEQ (level of EQ)
PRE (pre-emphasis) NoLow level High level
0.5A_15V_SMD1812P050TFF20.5A_15V_SMD1812P050TF
0_1206_5%~D
0_1206_5%~D
21
@R5
@
R5
F2
1 2
+VDISPLAY_VCC
1
2
TMDSE_RP_CLK#
TMDSE_RP_CLK
TMDSE_RP_N0
TMDSE_RP_P0
TMDSE_RP_N1
TMDSE_RP_P1
TMDSE_RP_N2
TMDSE_RP_P2
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C337
C337
2
HDMI_HPD_SINK
10U_0805_10V6K~D
10U_0805_10V6K~D
C338
C338
R1164
R1164
10K_0402_5%~D
10K_0402_5%~D
1 2
HDMI_SDA_SINK
HDMI_SCL_SINK
HDMI_CEC
TMDSE_CON_CLK#
TMDSE_CON_CLK
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_CON_N1
TMDSE_CON_P1
TMDSE_CON_N2
TMDSE_CON_P2
R451 0_0402_5%~D@R451 0_0402_5%~D@
L19
L19
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R459 0_0402_5%~D@R459 0_0402_5%~D@
R462 0_0402_5%~D@R462 0_0402_5%~D@
L20
L20
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R466 0_0402_5%~D@R466 0_0402_5%~D@
R468 0_0402_5%~D@R468 0_0402_5%~D@
L21
L21
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R469 0_0402_5%~D@R469 0_0402_5%~D@
R470 0_0402_5%~D@R470 0_0402_5%~D@
L22
L22
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R471 0_0402_5%~D@R471 0_0402_5%~D@
HDMI_HPD_SINK_R
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
JHDMI1
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
TYCO_2041270-1
TYCO_2041270-1
CONN@
CONN@
TMDSE_CON_CLK#
3
3
TMDSE_CON_CLK
2
2
TMDSE_CON_N0
3
3
TMDSE_CON_P0
2
2
TMDSE_CON_N1
3
3
TMDSE_CON_P1
2
2
TMDSE_CON_N2
3
3
TMDSE_CON_P2
2
2
GND
GND
GND
GND
20
21
22
23
HDMI_CEC
DPE_GPU_HPD
R1165 10K_0402_5%~DR1165 10K_0402_5%~D
R1128 100K_0402_5%~DR1128 100K_0402_5%~D
12
1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDMI port
HDMI port
HDMI port
LA-7782
LA-7782
LA-7782
26 66Friday, June 10, 2011
26 66Friday, June 10, 2011
26 66Friday, June 10, 2011
0.1
0.1
0.1
Page 27
5
4
3
2
1
AUX/DDC GPU for DPC to E-DOCK
U20
C357
D D
DPC_GPU_AUX/DDC<46>
DPC_DOCK_AUX<39>
DPC_GPU_AUX#/DDC<46>
DPC_DOCK_AUX#<39>
C C
C357
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C360 0.1U_0402_10V7K~DC360 0.1U_0402_10V7K~D
DPC_CA_DET<39>
DPC_GPU_AUX_CDPC_GPU_AUX/DDC
12
DPC_DOCK_AUX DPC_GPU_AUX/DDC
DPC_GPU_AUX#_CDPC_GPU_AUX#/DDC
12
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
U20
1
2
3
4
5
6
7
C365
C365
VCC
BE0
BE3
A0
B0
BE1
A1
BE2
B1
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+5V_RUN
12
1
5
P
NC
A2Y
G
U21
U21
NC7SZ04P5X-G_SC70-5~D
NC7SZ04P5X-G_SC70-5~D
3
14
13
12
A3
11
B3
10
9
A2
8
B2
DPC_CA_DET#DPC_CA_DET
4
+3.3V_RUN
DPC_GPU_AUX#/DDCDPC_DOCK_AUX#
1 2
C356
C356
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
AUX/DDC GPU for DPD to E-DOCK
C367
C367
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DPD_GPU_AUX_CDPD_GPU_AUX/DDC
DPD_GPU_AUX/DDC<46>
DPD_DOCK_AUX<39>
DPD_GPU_AUX#/DDC<46>
DPD_DOCK_AUX#<39>
DPD_CA_DET<39>
12
DPD_DOCK_AUX DPD_GPU_AUX/DDC
DPD_GPU_AUX#_CDPD_GPU_AUX#/DDC
12
C368 0.1U_0402_10V7K~DC368 0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
U23
U23
1
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+5V_RUN
12
C369
C369
5
P
A2Y
G
3
1
14
VCC
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
DPD_CA_DET#DPD_CA_DET
NC
4
U24
U24
NC7SZ04P5X-G_SC70-5~D
NC7SZ04P5X-G_SC70-5~D
+3.3V_RUN
DPD_GPU_AUX#/DDCDPD_DOCK_AUX#
1 2
C366
C366
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
There is a new die for PI3C3125. Sample availabe on May.
+3.3V_RUN
+3.3V_RUN
12
3
4
12
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
2
R1530
R1530
2.2K_0402_5%~D
2.2K_0402_5%~D
R1523 0_0402_5%~D@R1523 0_0402_5%~D@
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q113B
Q113B
DPC_DOCK_AUX#
R1539
R1539
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
R1538 0_0402_5%~D@R1538 0_0402_5%~D@
Q113A
Q113A
DPC_DOCK_AUX
1 2
DPD_CA_DET
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
C1175
C1175
2
+3.3V_ALW2
R1065
R1065
100K_0402_5%~D
100K_0402_5%~D
2
+5V_RUN
12
R1063
R1063
100K_0402_5%~D
100K_0402_5%~D
12
61
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q109B
Q109B
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
Q109A
Q109A
+5V_RUN
+3.3V_ALW2
R1532
R1532
100K_0402_5%~D
100K_0402_5%~D
B B
DPC_CA_DET
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
2
2
C1174
C1174
12
R1537
R1537
100K_0402_5%~D
100K_0402_5%~D
12
61
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q110B
Q110B
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
Q110A
Q110A
5
+3.3V_RUN
5
+3.3V_RUN
2
12
R1066
R1066
2.2K_0402_5%~D
2.2K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q111B
Q111B
4
12
R1062
R1062
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
R1064 0_0402_5%~D@R1064 0_0402_5%~D@
61
Q111A
Q111A
DPD_DOCK_AUX
1 2
R1067 0_0402_5%~D@R1067 0_0402_5%~D@
DPD_DOCK_AUX#
A A
DELL CONFIDENTIAL/PROPRIETARY
1 2
R491 1M_0402_5%~DR491 1M_0402_5%~D
1 2
R492 1M_0402_5%~DR492 1M_0402_5%~D
5
DPD_CA_DET
DPC_CA_DET
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP AUX SW
DP AUX SW
DP AUX SW
LA-7782
LA-7782
LA-7782
27 66Friday, June 10, 2011
27 66Friday, June 10, 2011
27 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 28
5
D D
+3.3V_RUN
12
PJP53
PJP53
PAD-OPEN1x1m
PAD-OPEN1x1m
4
3
2
1
Free Fall Sensor
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C C
+3.3V_RUN
1 2
R501 10K_0402_5%~DR501 10K_0402_5%~D
1 2
R502 10K_0402_5%~DR502 10K_0402_5%~D
1 2
R503 100K_0402_5%~DR503 100K_0402_5%~D
B B
FFS_INT2<18>
FFS_INT2
2
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
HDD_FALL_INT
+3.3V_RUN
12
R508
R508
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
2
+3.3V_RUN_FFS
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C388
C388
C387
C387
2
R506
@R506
@
100K_0402_5%~D
100K_0402_5%~D
FFS_INT2_Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q29B
Q29B
HDD_FALL_INT
FFS_INT2
PSATA_PTX_DRX_P0_C<14>
PSATA_PTX_DRX_N0_C<14>
PSATA_PRX_DTX_N0_C<14>
PSATA_PRX_DTX_P0_C<14>
HDD_FALL_INT<17>
DDR_XDP_WAN_SMBDAT<7,12,13,14,15,35>
DDR_XDP_WAN_SMBCLK<7,12,13,14,15,35>
+5V_HDD
12
3
5
Q29A
Q29A
4
U88
U88
LNG3DM
LNG3DM
1
VDD_IO
14
VDD
11
INT 1
9
INT 2
7
SDO/SA0
6
SDA / SDI / SDO
4
SCL/SPC
8
CS
LNG3DMTR_LGA16_3X3~D
LNG3DMTR_LGA16_3X3~D
+3.3V_RUN
+5V_HDD
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
C395
C395
2
10
RES
13
RES
15
RES
16
RES
5
GND
12
GND
2
NC
3
NC
12
C383 0.01U_0402_16V7K~DC383 0.01U_0402_16V7K~D
12
C384 0.01U_0402_16V7K~DC384 0.01U_0402_16V7K~D
12
C385 0.01U_0402_16V7K~DC385 0.01U_0402_16V7K~D
12
C386 0.01U_0402_16V7K~DC386 0.01U_0402_16V7K~D
PJP64
PJP64
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
HDD_DET#<14>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C396
C396
2
+3.3V_RUN_HDD
+5V_HDD
FFS_INT2_Q
For HDD Temp.
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
HDD_DET#
JSATA1
JSATA1
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
17
GND
18
Reserved
19
GND
20
12V
21
12V
22
12V
JAE_SP100421-HDD
JAE_SP100421-HDD
CONN@
CONN@
GND1
GND2
23
24
Main SATA +5V Default
HDD PWR
+PWR_SRC_S
+3.3V_ALW2
12
R500
R500
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q28A
RUN_ON<36,40,43,56,64>
SIO_SLP_S3#<11,16,36,40,43,56>
1 2
R1621 0_0402_5%~D@R1621 0_0402_5%~D@
1 2
R1624 0_0402_5%~DR1624 0_0402_5%~D
@R505
@
100K_0402_5%~D
100K_0402_5%~D
R505
12
Q28A
2
5
12
100K_0402_5%~D
100K_0402_5%~D
HDD_EN_5V
3
4
+5V_ALW
R499
R499
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q28B
Q28B
6
2
1
D
D
Q27
@
Q27
G
G
3
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
C393
C393
1
2
@
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
S
S
+5V_HDD
4 5
10U_0805_10V6K~D
10U_0805_10V6K~D
1
12
C394
C394
R504
R504
2
100K_0402_5%~D
100K_0402_5%~D
112
+5V_RUN
2
PJP3
@PJP3
@
JUMP_43X79
JUMP_43X79
SHORT DEFAULT
+5V_HDD Source
Pleace near HDD CONN
+3.3V_RUN_HDD
A A
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
2
C399
C399
C402
C402
2
Pleace near HDD CONN
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDD CONNECTOR
HDD CONNECTOR
HDD CONNECTOR
LA-7782
LA-7782
LA-7782
28 66Friday, June 10, 2011
28 66Friday, June 10, 2011
28 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 29
5
+3.3V_ALW
ZODD_WAKE#
1 2
R510 10K_0402_5%~DR510 10K_0402_5%~D
R513 10K_0402_5%~DR513 10K_0402_5%~D
+3.3V_ALW_PCH
D D
R514 100K_0402_5%~DR514 100K_0402_5%~D
1 2
1 2
MOD_MD
USB30_SMI#
4
3
2
1
For ODD
+3.3V_ALW
12
R515
R515
100K_0402_5%~D
100K_0402_5%~D
USB30_EN
61
Q123A
Q123A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
2
+5VMOD Source
MODC_EN<40>
R512
R512
100K_0402_5%~D
100K_0402_5%~D
+PWR_SRC_S
5
12
R507
R507
100K_0402_5%~D
100K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q31B
Q31B
4
+3.3V_ALW2
12
R509
R509
100K_0402_5%~D
100K_0402_5%~D
MODC_EN#
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q31A
Q31A
2
12
MOD_EN
+5V_ALW
3
1
2
6
2
1
D
D
Q30
Q30
G
G
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
S
S
+5V_MOD +5V_RUN
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
4 5
10U_0805_10V6K~D
10U_0805_10V6K~D
C400
C400
1
C401
C401
2
@PJP4
@
12
R511
R511
100K_0402_5%~D
100K_0402_5%~D
PJP4
112
JUMP_43X79
JUMP_43X79
2
JSATA2
JSATA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
REFCLK+
REFCLKGND
PETX+
PETXGND
GND
PERX+
PERXGND
+5V
CLKREQ#
WAKE#
PERST#
SMB_DATA
SMB_CLK
HPD
GND1
GND2
TYCO_2-2129116-3
TYCO_2-2129116-3
CONN@
CONN@
MOD_SATA_PCIE#_DET
32
33
+5V_MOD
PCIE_PTX_EMBRX_P4_C
C4090.1U_0402_10V7K~D C4090.1U_0402_10V7K~D
12
PCIE_PTX_EMBRX_N4_C
C4080.1U_0402_10V7K~D C4080.1U_0402_10V7K~D
12
+5V_MOD
ZODD_WAKE# <40>
USB30_SMI# <14>
SATA_ODD_PTX_DRX_P1
SATA_ODD_PTX_DRX_N1
SATA_ODD_PRX_DTX_N1
SATA_ODD_PRX_DTX_P1
MOD_MD
SATA_ODD_PTX_DRX_P1_C<14>
SATA_ODD_PTX_DRX_N1_C<14>
SATA_ODD_PRX_DTX_N1_C<14>
SATA_ODD_PRX_DTX_P1_C<14>
+5V_MOD
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C398
C398
C397
C397
2
2
C C
Pleace near ODD CONN
B B
MOD_MD
DEVICE_DET#<41>
CLK_PCIE_EMB<15>
CLK_PCIE_EMB#<15>
PCIE_PRX_EMBTX_P4<15>
PCIE_PRX_EMBTX_N4<15>
PCIE_PTX_EMBRX_P4<15>
PCIE_PTX_EMBRX_N4<15>
EMBCLK_REQ#<15>
PCIE_WAKE#<35,36,41>
PLTRST_EMB#<17>
BAY_SMBDAT<41,53>
BAY_SMBCLK<41,53>
MOD_SATA_PCIE#_DET<40>
Q76
Q76
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
S
D
S
13
G
G
2
MODC_EN#
Q123B
Q123B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
5
USB30_EN
+3.3V_ALW
12
C407 0.01U_0402_16V7K~DC407 0.01U_0402_16V7K~D
12
C406 0.01U_0402_16V7K~DC406 0.01U_0402_16V7K~D
12
C405 0.01U_0402_16V7K~DC405 0.01U_0402_16V7K~D
12
C404 0.01U_0402_16V7K~DC404 0.01U_0402_16V7K~D
EMBCLK_REQ#
PCIE_WAKE#
PLTRST_EMB#
BAY_SMBDAT
BAY_SMBCLK
1 2
R1183 10K_0402_5%~DR1183 10K_0402_5%~D
ZODD_WAKE#
USB30_SMI#
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ODD CONNECTOR
ODD CONNECTOR
ODD CONNECTOR
LA-7782
LA-7782
LA-7782
29 66Friday, June 10, 2011
29 66Friday, June 10, 2011
29 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 30
2
Internal Speakers Header
15 mils trace
INT_SPK_L+
INT_SPK_LINT_SPK_R+
INT_SPK_R-
C973 680P_0402_50V7K~D@C973 680P_0402_50V7K~D@
C974 680P_0402_50V7K~D@C974 680P_0402_50V7K~D@
C975 680P_0402_50V7K~D@C975 680P_0402_50V7K~D@
1
1
1
1
2
2
2
B B
2
Close to U72 pin5
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK
12
R1077
@R1077
@
47_0402_5%~D
47_0402_5%~D
1
C978
@C978
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
Place closely to Pin 13.
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Add for solve pop noise and detect issue
A A
Place closely to Pin 14
+3.3V_RUN
39.2K_0402_1%~D
39.2K_0402_1%~D
12
R1081
R1081
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
DVDD_IO should match
with HDA Bus level
L91 BLM18BD121SN1D_2P~DL91 BLM18BD121SN1D_2P~D
1 2
L92 BLM18BD121SN1D_2P~DL92 BLM18BD121SN1D_2P~D
1 2
L93 BLM18BD121SN1D_2P~DL93 BLM18BD121SN1D_2P~D
1 2
L94 BLM18BD121SN1D_2P~DL94 BLM18BD121SN1D_2P~D
1 2
C976 680P_0402_50V7K~D@C976 680P_0402_50V7K~D@
Close to U72 pin6
12
R1076
@R1076
@
10_0402_1%~D
10_0402_1%~D
1
C977
@C977
@
10P_0402_50V8J~D
10P_0402_50V8J~D
2
AUD_SENSE_A
2
Q107A
Q107A
AUD_SENSE_B
R1079
R1079
2
Q106A
Q106A
61
12
61
12
R1086
R1086
20K_0402_1%~D
20K_0402_1%~D
3
5
Q107B
Q107B
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
12
R1080
R1080
20K_0402_1%~D
20K_0402_1%~D
3
5
Q106B
Q106B
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
JSPK1
CONN@JSPK1
INT_SPKL_L+
INT_SPKR_LINT_SPKR_R+
INT_SPKR_R-
MOLEX_53398-0471~D
MOLEX_53398-0471~D
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
2
3
1
PESD5V0U2BT_SOT23-3~D
2
3
@DE2
@
DE2
1
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output
AUD_NB_MUTE#<40>
+3.3V_RUN
R1083
R1083
2.49K_0402_1%~D
2.49K_0402_1%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+3.3V_RUN
1
C980
C980
12
2
1
2
R1078
R1078
2.49K_0402_1%~D
2.49K_0402_1%~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
C979
C979
+3.3V_RUN
2
12
CONN@
1
1
2
2
3
5
3
G1
4
6
4
G2
@DE1
@
DE1
PCH_AZ_CODEC_BITCLK<14>
PCH_AZ_CODEC_SDOUT<14>
PCH_AZ_CODEC_SYNC<14>
PCH_AZ_CODEC_SDIN0<14>
PCH_AZ_CODEC_RST#<14>
1 2
10K_0402_5%~DR1099 10K_0402_5%~DR1099
+VDDA_AVDD
12
R1087
R1087
100K_0402_5%~D
100K_0402_5%~D
AUD_HP_NB_SENSE <31,40>
C967
@C967
@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+VDDA_AVDD
12
R1082
R1082
100K_0402_5%~D
100K_0402_5%~D
DOCK_MIC_DET <40>DOCK_HP_DET<40>
2
+3.3V_RUN_DVDD+3.3V_RUN +3.3V_RUN_DVDD
PJP65
@PJP65
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
1U_0603_10V7K~D
1U_0603_10V7K~D
1
C952
C952
2
Place R1096 close to codec
1 2
R1096
R1096
I2S_MCLK
I2S_BCLK
I2S_DO
I2S_LRCLK
I2S_DI#
Place R1097 close to codec
place at AGND and DGND plane
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
Resistor SENSE_A SENSE_B
39.2K
20K
10K
5.11K
2.49K
PORT B
PORT C
PORT D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C994
C994
2
33_0402_5%~D
33_0402_5%~D
1 2
1 2
@
@
C981
C981
1 2
@
@
C982
C982
1 2
@
@
C983
C983
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C953
C953
2
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SDOUT
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
33_0402_5%~DR1097 33_0402_5%~DR1097
PORT A
PORT B
NA
SPDIFOUT0
Pull-up to AVDD
External MICPORT A
HeadPhone Out
Dock Audio
Internal SPK
+DVDD_CORE
10U_0805_10V6K~D
10U_0805_10V6K~D
1
C954
C954
2
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
Place C994, C952~C957 close to Codec
U72
U72
1
DVDD_CORE
3
DVDD_IO
9
DVDD
6
BITCLK
5
SDATA_OUT
10
SYNC
8
SDATA_IN
11
RESET#
15
I2S_MCLK
16
I2S_SCLK
17
I2S_DOUT
18
I2S_LRCLK
24
I2S_DIN
19
No Connect
20
No Connect
47
EAPD
7
DVSS
42
PVSS
49
GND
92HD90B2X5NLGXYAX8_QFN48_7X7~D
92HD90B2X5NLGXYAX8_QFN48_7X7~D
place at Codec bottom side
PJP62
@PJP62
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
R162, R163, R164, R165,R166 CO-lay with U73
DMIC1/GPIO0/SPDIFOUT1
SPDIFOUT0//GPIO3/Aux_Out
DAI_BCLK#
DAI_LRCK#
DAI_DO#
DAI_12MHZ#
AVDD1
AVDD2
PVDD
PVDD
SENSE_A
SENSE_B
PORTA_L
PORTA_R
VrefOut_A
PORTB_L
PORTB_R
PORTD_+L
PORTD_-L
PORTD_+R
PORTD_-R
MONO_OUT
PC_BEEP
DMIC_CLK/GPIO 1
DMIC_0/GPIO 2
CAP+
CAP-
VREFFILT
CAP2
Vreg
AVSS1
AVSS
AVSS
R162 22_0402_5%~D@R162 22_0402_5%~D@
R163 0_0402_5%~D@R163 0_0402_5%~D@
R164 0_0402_5%~D@R164 0_0402_5%~D@
R165 22_0402_5%~D@R165 22_0402_5%~D@
V-
1 2
1 2
1 2
1 2
PORT E
PORT F
EN_I2S_NB_CODEC#<40>
EN_I2S_NB_CODEC#
DMIC0
SPDIFOUT1 (DMIC1)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
27
38
45
39
13
14
28
29
23
31
32
40
41
44
43
25
12
2
4
46
48
36
35
21
22
34
37
26
30
33
DMIC_CLK_L
place close to pin27 place close to pin38
+VDDA_AVDD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1U_0603_10V7K~D
1U_0603_10V7K~D
1
1
C957
C957
2
2
+VDDA_PVDD
AUD_SENSE_A
AUD_SENSE_B
MIC_IN_L
MIC_IN_R
+VREFOUT
AUD_HP_OUT_L
AUD_HP_OUT_R
INT_SPK_L+
INT_SPK_L-
INT_SPK_R+
INT_SPK_R-
AUD_PC_BEEP
1
C962
C962
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
Place C962 close to Codec
2
+3.3V_RUN +3.3V_RUN
2
1
I2S_BCLK DAI_BCLK#
I2S_LRCLK
I2S_DO
R1540
R1540
1K_0402_1%~D
1K_0402_1%~D
C1105 0.1U_0402_25V6K~DC1105 0.1U_0402_25V6K~D
C1106 0.1U_0402_25V6K~DC1106 0.1U_0402_25V6K~D
1 2
LE3 BLM18BB221SN1D_2P~DLE3 BLM18BB221SN1D_2P~D
Place LE3 close to codec
1 2
R169 0_0402_5%~D@R169 0_0402_5%~D@
T90 PAD~D@ T90 PAD~D@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C1103
C1103
U73
U73
16
VCC
2
1A
4
2A
6
3A
10
4A
12
5A
14
6A
1
OE1#
12
15
OE2#
CD74HC366M96_SO16~D
CD74HC366M96_SO16~D
1
BLM21PG600SN1D_0805~D
10U_0805_10V6K~D
10U_0805_10V6K~D
1
C956
C956
C955
C955
2
1 2
1U_0402_6.3V6K~DC1163 1U_0402_6.3V6K~DC1163
+VREFOUT
1 2
R1143 2.2K_0402_5%~DR1143 2.2K_0402_5%~D
12
12
BLM21PG600SN1D_0805~D
DMIC_CLK <24>
DMIC0 <24>
Place C963~C966 close to Codec
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C963
C963
2
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
3
3
@D54
@
D54
1
I2S_DI#
1 2
R166 0_0402_5%~D@R166 0_0402_5%~D@
1
GND
3
1Y#
5
2Y#
7
3Y#
9
4Y#
11
5Y#
13
6Y#
8
1
1
2
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C959
C959
2
1
+3.3V_RUN
1
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
+5V_RUN
10U_0805_10V6K~D
10U_0805_10V6K~D
@D57
@
D57
3
1
0_0805_5%~D
0_0805_5%~D
12
R1095
R1095
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C961
C961
C960
C960
2
SPKR <14>
BEEP <41>
DAI_LRCK#
DAI_DO#
DAI_12MHZ#I2S_MCLK
2
D58
@D58
@
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DAI_DI
+VREFOUT
DAI_BCLK# <39>
DAI_LRCK# <39>
DAI_DO# <39>
DAI_12MHZ# <39>
DAI_DI <39>
L77
L77
1 2
MIC_IN_R <31>
AUD_HP_OUT_L <31>
AUD_HP_OUT_R <31>
R1119 100K_0402_5%~DR1119 100K_0402_5%~D
R1120 100K_0402_5%~DR1120 100K_0402_5%~D
R1141 10K_0402_5%~D@ R1141 10K_0402_5%~D@
R1142 10K_0402_5%~D@ R1142 10K_0402_5%~D@
1U_0603_10V7K~D
1U_0603_10V7K~D
1
1
C964
C964
C965
C965
2
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
3
2
@D55
@
D55
1
DAI_DI
10U_0805_10V6K~D
10U_0805_10V6K~D
1
C958
C958
2
1 2
1 2
1 2
1 2
10U_0805_10V6K~D
10U_0805_10V6K~D
C966
C966
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
@D56
@
D56
+5V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Azalia (HD) Codec
Azalia (HD) Codec
Azalia (HD) Codec
LA-7782
LA-7782
LA-7782
30 66Friday, June 10, 2011
30 66Friday, June 10, 2011
30 66Friday, June 10, 2011
1U_0603_10V7K~D
1U_0603_10V7K~D
1
C1180
C1180
2
0.1
0.1
0.1
Page 31
5
4
3
2
1
I/O board CONN.
Change to TYCO_2041300-2_60P-T and Horizonal reverse to SSI
JIO1
JIO1
2
2
SW_LAN_TX0+<32>
D D
SW1
SW1
NTC033-XJ1J-X260CM_4P
VOL_UP<41>
LID_CL#<40,44>
NTC033-XJ1J-X260CM_4P
3
4
1
2
Media Board
JMDIA1
JMDIA1
1
1
2
2
3
3
4
4
5
5
6
6
G1
7
7
G2
8
8
TYCO_2041070-8~D
TYCO_2041070-8~D
CONN@
CONN@
+5V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C50
C50
1
2
9
10
POWER_SW#_MB<41,42>
POWER_SW#_MB
D23
@D23
@
3
1
2
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
POWER & INSTANT ON SWITCH
Defult on,
WIRELESS_ON/OFF#:
LOW: ON
HIGH: OFF
C C
+3.3V_ALW
1
2
C1001
C1001
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
VOL_MUTE<41>
VOL_DOWN<41>
WIRELESS_ON#/OFF<40>
SW_LAN_TX0-<32>
SW_LAN_TX1-<32>
SW_LAN_TX1+<32>
SW_LAN_TX2+<32>
SW_LAN_TX2-<32>
SW_LAN_TX3-<32>
SW_LAN_TX3+<32>
+3.3V_LAN
LED_100_ORG#<32>
LED_10_GRN#<32>
LAN_ACTLED_YEL#<32>
USB_OC4#<17>
USBP9+<17>
USBP9-<17>
USB_SIDE_EN#<40>
AUD_HP_NB_SENSE<30,40>
+3.3V_LAN
1
C997
C997
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
Place close
to JIO1.13
+5V_RUN
DETECT_GND
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND62GND
64
GND
66
GND
TYCO_2041300-2
TYCO_2041300-2
CONN@
CONN@
GND
GND
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
63
65
MIC_IN_R
PCH_AZ_MDC_RST1#
Analog_GND
IO_LOOP# <18>
VSYNC_BUF <25>
HSYNC_BUF <25>
RED_CRT <25>
GREEN_CRT <25>
BLUE_CRT <25>
DAT_DDC2_CRT <25>
CLK_DDC2_CRT <25>
AUD_HP_OUT_R <30>
MIC_IN_R <30>
AUD_HP_OUT_L <30>
+3.3V_ALW_PCH
PCH_AZ_MDC_SDIN1 <14>
PCH_AZ_MDC_SYNC <14>
PCH_AZ_MDC_SDOUT <14>
PCH_AZ_MDC_BITCLK <14>
+3.3V_ALW_PCH
1
C1000
C1000
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
Place close
to JIO1.35
+5V_ALW
1
C1003
C1003
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
LED Board
JLED1
+5V_ALW
B B
1
C1002
C1002
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
SATA_LED<44>
BATT_WHITE<44>
BATT_YELLOW<44>
WLAN_LED<44>
JLED1
1
1
2
2
3
3
4
4
5
7
5
G1
6
8
6
G2
TYCO_2041084-6~D
TYCO_2041084-6~D
CONN@
CONN@
Q44
Q44
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
G
G
PCH_AZ_MDC_RST1#
12
R751
R751
100K_0402_5%~D
100K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR SW/Sub-board Connector
PWR SW/Sub-board Connector
PWR SW/Sub-board Connector
LA-7782
LA-7782
LA-7782
31 66Friday, June 10, 2011
31 66Friday, June 10, 2011
31 66Friday, June 10, 2011
1
0.1
0.1
0.1
D
D
R752
R752
10K_0402_5%~D
10K_0402_5%~D
1 3
2
PCH_AZ_MDC_RST#<14>
A A
MDC_RST_DIS#<40>
+5V_ALW
12
5
Page 32
5
+3.3V_LAN
1 2
R545 10K_0402_5%~D@ R545 10K_0402_5%~D@
1 2
R546 10K_0402_5%~D@ R546 10K_0402_5%~D@
D D
PM_LANPHY_ENABLE<18>
C C
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
10K_0402_5%~D
10K_0402_5%~D
1 2
R555 0_0402_5%~DR555 0_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
33P_0402_50V8J~D
33P_0402_50V8J~D
2
C470
C470
1
PCIE_PRX_GLANTX_P7<15>
12
12
R1144 0_0402_5%~DR1144 0_0402_5%~D
3
OUT
4
PCIE_PRX_GLANTX_N7<15>
PCIE_PTX_GLANRX_P7<15>
PCIE_PTX_GLANRX_N7<15>
1 2
+3.3V_LAN
R549
R549
R557
@R557
@
Y3
Y3
25MHZ_18PF_X3G025000DI1H-H~D
25MHZ_18PF_X3G025000DI1H-H~D
1
IN
2
GND
GND
LANCLK_REQ#<15>
PLTRST_LAN#<17>
CLK_PCIE_LAN<15>
CLK_PCIE_LAN#<15>
LAN_SMBCLK<15>
LAN_SMBDATA<15>
33P_0402_50V8J~D
33P_0402_50V8J~D
2
C471
C471
1
1 2
R1187 0_0402_5%~DR1187 0_0402_5%~D
12
C458 0.1U_0402_10V7K~DC458 0.1U_0402_10V7K~D
12
C459 0.1U_0402_10V7K~DC459 0.1U_0402_10V7K~D
1 2
C460 0.1U_0402_10V7K~DC460 0.1U_0402_10V7K~D
1 2
C461 0.1U_0402_10V7K~DC461 0.1U_0402_10V7K~D
1 2
R551 0_0402_5%~DR551 0_0402_5%~D
1 2
R552 0_0402_5%~DR552 0_0402_5%~D
SMBus Device Address 0xC8
LAN_DISABLE#_R<40>
T142 PAD~DT142 PAD~D
T143 PAD~DT143 PAD~D
1K_0402_1%~D
1K_0402_1%~D
12
R561
R561
4
+3.3V_RUN
12
R547
R547
10K_0402_5%~D
10K_0402_5%~D
LANCLK_REQ#_R
CLK_PCIE_LAN
CLK_PCIE_LAN#
PCIE_PRX_GLANTX_P7_C
PCIE_PRX_GLANTX_N7_C
PCIE_PTX_GLANRX_P7_C
PCIE_PTX_GLANRX_N7_C
LAN_SMBCLK_R
LAN_SMBDATA_R
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALO
XTALI
LAN_TEST_EN
RES_BIAS
3.01K_0402_1%~D
3.01K_0402_1%~D
12
R562
R562
U31
U31
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
MDI
MDI
PCIE
PCIE
RSVD_VCC3P3_1
RSVD_VCC3P3_2
SMBUS
SMBUS
VDD3P3_OUT
JTAG LED
JTAG LED
82579_QFN48_6X6~D
82579_QFN48_6X6~D
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
RSVD_NC
VDD3P3_IN
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD1P0_47
VDD1P0_46
VDD1P0_37
VDD1P0_43
VDD1P0_11
VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8
CTRL_1P0
VSS_EPAD
13
14
17
18
20
21
23
24
6
+RSVD_VCC3P3_1
1
+RSVD_VCC3P3_2
2
5
4
15
19
29
47
46
37
43
11
40
22
16
8
REGCTL_PNP10
7
49
3
LAN_TX0+
LAN_TX0-
LAN_TX1+
LAN_TX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
R553 4.7K_0402_5%~DR553 4.7K_0402_5%~D
R554 4.7K_0402_5%~DR554 4.7K_0402_5%~D
+3.3V_LAN_OUT
+1.0V_LAN
12
12
1
C464
C464
1U_0603_10V7K~D
1U_0603_10V7K~D
2
2
REGCTL_PNP10
+3.3V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
C466
C466
2
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
L29
L29
1 2
4.7UH_CBC2012T4R7M_20%~D
4.7UH_CBC2012T4R7M_20%~D
Idc max=330mA
+1.0V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C468
C468
C467
C467
2
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
+1.0V_LAN
C462
C462
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
R548
@R548
@
0_0805_5%~D
0_0805_5%~D
1 2
C463
C463
Place R548, C462, C463 and L29 close to U31
+3.3V_LAN
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C1177
C1177
1
1
C469
C469
2
2
22U_0805_6.3V6M~D
C1178
C1178
1
2
Place C1178 close to pin5
+1.05V_M
+3.3V_M
+1.0V_LAN POWER OPTIONS
R563
@ R563
Need to verify A3 silicon drive
power before removing C427
KDS crystal vender verify
driving level in A3
+3.3V_LAN
B B
LAN_TX3-
1 2
L37 12NH_0603CS-120EJTS_5%~DL37 12NH_0603CS-120EJTS_5%~D
1 2
L36 12NH_0603CS-120EJTS_5%~DL36 12NH_0603CS-120EJTS_5%~D
LAN_TX2-
1 2
L35 12NH_0603CS-120EJTS_5%~DL35 12NH_0603CS-120EJTS_5%~D
1 2
L34 12NH_0603CS-120EJTS_5%~DL34 12NH_0603CS-120EJTS_5%~D
LAN_TX1-
1 2
L32 12NH_0603CS-120EJTS_5%~DL32 12NH_0603CS-120EJTS_5%~D
LAN_TX1+
1 2
L33 12NH_0603CS-120EJTS_5%~DL33 12NH_0603CS-120EJTS_5%~D
1 2
L31 12NH_0603CS-120EJTS_5%~DL31 12NH_0603CS-120EJTS_5%~D
1 2
L30 12NH_0603CS-120EJTS_5%~DL30 12NH_0603CS-120EJTS_5%~D
DOCKED
DOCKED<40>
A A
Layout Notice : Place bead as
close PI3L500 as possible
FROM NIC DOCKED
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C472
C472
2
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
1: TO DOCK
0: TO RJ45
1
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C473
C473
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C474
C474
2
LAN_TX3-R
LAN_TX3+RLAN_TX3+
LAN_TX2-R
LAN_TX2+RLAN_TX2+
LAN_TX1-R
LAN_TX1+R
LAN_TX0-RLAN_TX0LAN_TX0+RLAN_TX0+
39
U32
U32
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
PI3L720ZHEX_TQFN42_9X3P5~D
VDD1VDD4VDD8VDD14VDD21VDD30VDD
4
LAN ANALOG
S
WITCH
38
B0+
37
B0-
34
B1+
33
B1-
29
B2+
28
B2-
25
B3+
24
B3-
17
LEDB0
18
LEDB1
41
LEDB2
36
C0+
35
C0-
32
C1+
31
C1-
27
C2+
26
C2-
23
C3+
22
C3-
19
LEDC0
20
LEDC1
40
LEDC2
SW_LAN_TX3SW_LAN_TX3+
SW_LAN_TX2SW_LAN_TX2+
SW_LAN_TX1SW_LAN_TX1+
SW_LAN_TX0SW_LAN_TX0+
LAN_ACTLED_YEL#
LED_100_ORG#
LED_10_GRN#
DOCK_LOM_TRD3DOCK_LOM_TRD3+
DOCK_LOM_TRD2DOCK_LOM_TRD2+
DOCK_LOM_TRD1DOCK_LOM_TRD1+
DOCK_LOM_TRD0DOCK_LOM_TRD0+
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
SW_LAN_TX3- <31>
SW_LAN_TX3+ <31>
SW_LAN_TX2- <31>
SW_LAN_TX2+ <31>
SW_LAN_TX1- <31>
SW_LAN_TX1+ <31>
SW_LAN_TX0- <31>
SW_LAN_TX0+ <31>
LAN_ACTLED_YEL# <31>
LED_100_ORG# <31>
LED_10_GRN# <31>
DOCK_LOM_TRD3- <39>
DOCK_LOM_TRD3+ <39>
DOCK_LOM_TRD2- <39>
DOCK_LOM_TRD2+ <39>
DOCK_LOM_TRD1- <39>
DOCK_LOM_TRD1+ <39>
DOCK_LOM_TRD0- <39>
DOCK_LOM_TRD0+ <39>
DOCK_LOM_ACTLED_YEL# <39>
DOCK_LOM_SPD100LED_ORG# <39>
DOCK_LOM_SPD10LED_GRN# <39>
TO
DOCK
3
Shared with PCH
1.05V SVR
STUFF: R548
NO STUFF: L29
Internal SRV
*
STUFF: L29
NO STUFF: R548
SIO_SLP_LAN#<16,40>
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
2
+3.3V_ALW2
2
+3.3V_LAN
1
B
2
A
12
R565
R565
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q35A
Q35A
C478
C478
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
5
P
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
U15
U15
Q34
Q34
SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S
12
R564
R564
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q35B
Q35B
5
4
WLAN_LAN_DISB# <40>
SI3456DDV-T1-GE3_TSOP6~D
ENAB_3VLAN
1M_0402_5%~D
1M_0402_5%~D
12
R1638
R1638
D
D
6
S
S
2
1
G
G
3
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
C477
C477
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Intel 82579 (Hanksville) / LAN SW
Intel 82579 (Hanksville) / LAN SW
Intel 82579 (Hanksville) / LAN SW
LA-7782
LA-7782
LA-7782
1
@
0_1206_5%~D
0_1206_5%~D
1 2
+3.3V_LAN+3.3V_ALW
45
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
C475
C475
C476
C476
2
2
0.1
0.1
32 66Friday, June 10, 2011
32 66Friday, June 10, 2011
32 66Friday, June 10, 2011
0.1
Page 33
5
4
3
2
1
D D
+3.3V_RUN_TPM
C C
R873 0_0402_5%~D1@ R873 0_0402_5%~D1@
CLK_PCI_TPM_TCM
12
RE5
@ RE5
@
33_0402_5%~D
33_0402_5%~D
1
@
@
CE3
CE3
27P_0402_50V8J~D
27P_0402_50V8J~D
2
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
PJP61
PJP61
CLK_PCI_TPM_TCM<15>
PCH_PLTRST#_EC<17,35,36,40,41>
+3.3V_RUN_TPM+3.3V_RUN
+3.3V_SB3V
SP_TPM_LPC_EN<40>
LPC_LAD0<14,35,40,41>
LPC_LAD1<14,35,40,41>
LPC_LAD2<14,35,40,41>
LPC_LAD3<14,35,40,41>
LPC_LFRAME#<14,35,40,41>
IRQ_SERIRQ<14,40,41>
CLKRUN#<16,40,41>
+3.3V_SB3V
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1@
1@
1
C44
C44
2
SP_TPM_LPC_EN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
TCM_BA1
ATMEL TPM for E4
4700P_0402_25V7K~D
4700P_0402_25V7K~D
1@
1@
1
C45
C45
2
U39
1@ U39
1@
5
SB3V
28
LPCPD#
26
LAD0
23
LAD1
20
LAD2
17
LAD3
21
LCLK
22
LFRAME#
16
LRESET#
27
SERIRQ
15
CLKRUN#
1
ATEST_1
2
ATEST_2
3
ATEST_3
AT97SC3204-X2A14-AB_TSSOP28
AT97SC3204-X2A14-AB_TSSOP28
VCC_0
VCC_1
VCC_2
V_BAT
NBO_13
NBO_14
GPIO6
TESTBI
TESTI
NC_7
GND_4
GND_11
GND_18
GND_25
10
19
24
12
13
14
6
9
8
7
4
11
18
25
+3.3V_RUN_TPM
JETWAY_CLK14M
NC_P
1 2
C554 1U_0402_6.3V6K~DC554 1U_0402_6.3V6K~D
TCM_BA0
PP
1 2
R656 4.7K_0402_5%~D@R656 4.7K_0402_5%~D@
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
1
C551
C551
C550
C550
2
2
JETWAY_CLK14M <15>
+3.3V_RUN_TPM
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C552
C552
2
2
+3.3V_SUS
1 2
R589 2.2K_0402_5%~DR589 2.2K_0402_5%~D
C553
C553
+3.3V_SUS
+3.3V_RUN
1 2
R585 2.2K_0402_5%~DR585 2.2K_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C53
C53
1
2
+5V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C51
C51
1
2
1
2
USH_SMBCLK
USH_SMBDAT
JUSH1
JUSH1
1
1
USBP7-<17>
USBP7+<17>
USH_SMBCLK<41>
USH_SMBDAT<41>
BCM5882_ALERT#<40>
BT_COEX_STATUS2<42>
BT_PRI_STATUS<42>
PLTRST_USH#<17>
USH_PWR_STATE#<40>
CONTACTLESS_DET#<18>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C52
C52
USH_DET#<18>
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
TYCO_2-2041070-0
TYCO_2-2041070-0
Co-lay U37 and U38
LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay
VDD_0
VDD_1
VDD_2
GND_4
NC_5
NC_12
NC_13
NC_1
NC_2
NC_6
NC_8
NC_P
+3.3V_RUN_TPM
10
19
24
11
18
25
4
5
12
13
1
2
6
8
14
+3.3V_SB3V
JETWAY_CLK14M
NC_P
JETWAY_CLK14M
12
@
@
RE6
RE6
33_0402_5%~D
33_0402_5%~D
1
@
@
CE4
CE4
27P_0402_50V8J~D
27P_0402_50V8J~D
2
B B
+3.3V_RUN_TPM
12
12
R658
@R658
12
@
10K_0402_5%~D
10K_0402_5%~D
12
R660
R660
10K_0402_5%~D
10K_0402_5%~D
TCM_BA0
TCM_BA1
R657
@R657
@
10K_0402_5%~D
10K_0402_5%~D
R659
R659
10K_0402_5%~D
10K_0402_5%~D
A A
LOW:Power Down Mode
High:Working Mode
SP_TPM_LPC_EN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLK_PCI_TPM_TCM
LPC_LFRAME#
PCH_PLTRST#_EC
IRQ_SERIRQ
CLKRUN#
PP
TCM_BA1
TCM_BA0
U37
4@ U37
4@
28
LPCPD#
26
LAD0
23
LAD1
20
LAD2
17
LAD3
21
LCLK
22
LFRAME#
16
LRESET#
27
SERIRQ
15
CLKRUN#
7
PP
3
BA_1
9
BA_0
SSX44-B-D-T1_TSSOP28~D
SSX44-B-D-T1_TSSOP28~D
GND_11
GND_18
GND_25
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH conn/TPM
USH conn/TPM
USH conn/TPM
LA-7782
LA-7782
LA-7782
33 66Friday, June 10, 2011
33 66Friday, June 10, 2011
33 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 34
A
1 1
B
C
D
E
+3.3V_RUN
+1.5V_RUN
+PE_VDDH
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1
C573
C573
C574
C574
2
2
2 2
place close to pin U38.32
3 3
L47
L47
1 2
BLM18BD601SN1D_0603~D
BLM18BD601SN1D_0603~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C562
C562
C561
C561
2
2
CLK_PCIE_MMI<15>
CLK_PCIE_MMI#<15>
PCIE_PRX_MMITX_P6<15>
PCIE_PRX_MMITX_N6<15>
PCIE_PTX_MMIRX_P6<15>
PCIE_PTX_MMIRX_N6<15>
PLTRST_MMI#<17>
MMICLK_REQ#<15>
L45
L45
BLM18PG471SN1D_2P~D
BLM18PG471SN1D_2P~D
1 2
C569 0.1U_0402_10V7K~DC569 0.1U_0402_10V7K~D
1 2
C571 0.1U_0402_10V7K~DC571 0.1U_0402_10V7K~D
1 2
C567 0.1U_0402_10V7K~DC567 0.1U_0402_10V7K~D
1 2
C568 0.1U_0402_10V7K~DC568 0.1U_0402_10V7K~D
1 2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C577
C577
2
2
1 2
L44 BLM18BD601SN1D_0603~DL44 BLM18BD601SN1D_0603~D
C578 4.7U_0603_6.3V6K~DC578 4.7U_0603_6.3V6K~D
R677 191_0402_1%~DR677 191_0402_1%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C576
C576
C575
C575
2
+3.3VDDH
+VDDH_SD
+PE_VDDH+PE_VDDH
12
PCIE_PRX_MMITX_P6_C
PCIE_PRX_MMITX_N6_C
PCIE_PTX_MMIRX_P6_C
PCIE_PTX_MMIRX_N6_C
1 2
U38
U38
16
3.3VDDH
9
VDDH
32
PE_VDDH
2
PE_REFCLKP
1
PE_REFCLKM
6
PE_TXP
7
PE_TXM
5
PE_RXP
4
PE_RXM
3
PE_REXT
33
GPAD
13
PE_RST#
14
MULTI-IO1
31
MULTI-IO2
OZ600FJ0LN_QFN32_5X5~D
OZ600FJ0LN_QFN32_5X5~D
DVDD
AVDD
SKT_VCC
MMI_VCC_OUT
SD_D1
SD_D2
MMI_D0
MS_D1
MS_D2
MMI_D3
MMI_D4
MMI_D5
MMI_D6
MMI_D7
MS_CD#
SD_CMD/MS_BS
MMI_CLK
SD_CD#
SD_WPI
+OZ_DVDD
10
+OZ_AVDD
8
+SKT_VCC
17
15
SD/MMCDAT1_R
28
SD/MMCDAT2_R
26
SD/MMCDAT0_R
29
27
25
SD/MMCDAT3_R
24
SD/MMCDAT4_R
23
SD/MMCDAT5_R
22
SD/MMCDAT6_R
21
SD/MMCDAT7_R
20
11
SD/MMCCMD_R
19
SD/MMCCLK_R
18
SD/MMCCD#
12
SDWP
30
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C563
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C565
C565
2
2
R663 33_0402_5%~DR663 33_0402_5%~D
1 2
R664 33_0402_5%~DR664 33_0402_5%~D
1 2
R665 33_0402_5%~DR665 33_0402_5%~D
1 2
R668 33_0402_5%~DR668 33_0402_5%~D
1 2
R669 33_0402_5%~DR669 33_0402_5%~D
1 2
R670 33_0402_5%~DR670 33_0402_5%~D
1 2
R672 33_0402_5%~DR672 33_0402_5%~D
1 2
R673 33_0402_5%~DR673 33_0402_5%~D
1 2
R674 33_0402_5%~DR674 33_0402_5%~D
1 2
1 2
R676 33_0402_5%~DR676 33_0402_5%~D
C563
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
C566
C566
2
EMI request
SD/MMCCLK
@
@
RE678
RE678
33_0402_5%~D
33_0402_5%~D
1 2
1
CE757
@CE757
@
10P_0402_50V8J~D
10P_0402_50V8J~D
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
C564
C564
SD/MMCDAT1
SD/MMCDAT2
SD/MMCDAT0
SD/MMCDAT3
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7
SD/MMCCMD
SD/MMCCLK
+3.3V_RUN_CARD
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
C559
C559
C560
C560
2
+3.3V_RUN_CARD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C570
C570
2
2
Note: The trace need to route as
daisy-chain and the trace of SD signals
need to route as short as possible
JSD1
CONN@JSD1
SD/MMCCLK
SD/MMCCMD
10K_0402_5%~D
10K_0402_5%~D
12
SD/MMCDAT0
R826
R826
C572
C572
SD/MMCDAT1
SD/MMCDAT2
SD/MMCDAT3
SD/MMCDAT4
SD/MMCDAT5
SD/MMCDAT6
SD/MMCDAT7
SDWP
SD/MMCCD#
SD/MMCCD#
SDWP
CONN@
8
CLK/SD-5
9
VCC/VDD/SD-4
10
VSS1/SD-3
12
CMD/SD-2
4
DAT0/SD-7
3
DAT1/SD-8
15
DAT2/SD-9
14
DAT3/SD-1
13
DAT4/MMC-10
11
DAT5/MMC-11
7
DAT6/MMC-12
5
DAT7/MMC-13
1
WP SW/SD
2
CD SW/SD
16
GND SW
17
CD SW
18
WP SW
19
CD&WP/SW/GND
20
CD&WP/SW/GND
6
GND/VSS2/SD6
T-SOL_156-3000000901~D
T-SOL_156-3000000901~D
GND1
GND2
21
22
only for MMC/SD
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Card Reader OZ600FJ0
Card Reader OZ600FJ0
Card Reader OZ600FJ0
LA-7782
LA-7782
LA-7782
34 66Friday, June 10, 2011
34 66Friday, June 10, 2011
34 66Friday, June 10, 2011
E
0.1
0.1
0.1
Page 35
5
USB_MCARD2_DET#
PCIE_MCARD2_DET#_R
D D
R694 100K_0402_5%~DR694 100K_0402_5%~D
1 2
R695 100K_0402_5%~DR695 100K_0402_5%~D
+3.3V_RUN
12
+3.3V_PCIE_WWAN
DDR_XDP_WAN_SMBCLK<7,12,13,14,15,28>
DDR_XDP_WAN_SMBDAT<7,12,13,14,15,28>
Mini WWAN/GPS/LTE H=5.2
CONN@
CONN@
JMINI1
JMINI1
1
1
3
3
5
MINI1CLK_REQ#<15>
CLK_PCIE_MINI1#<15>
CLK_PCIE_MINI1<15>
PCIE_PRX_WANTX_N1<15>
PCIE_PRX_WANTX_P1<15>
PCIE_PTX_WANRX_N1<15>
PCIE_PTX_WANRX_P1<15>
PCIE_MCARD2_DET#<17>
+1.5V_RUN
C C
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
33P_0402_50V8J~D
1
1
C594
C594
C593
C593
2
2
+3.3V_PCIE_WWAN
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C610
C610
C611
C611
2
2
B B
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
C597 0.1U_0402_10V7K~DC597 0.1U_0402_10V7K~D
PCIE_PTX_WANRX_N1_C
1 2
PCIE_PTX_WANRX_P1_C
1 2
C599 0.1U_0402_10V7K~DC599 0.1U_0402_10V7K~D
R725 0_0402_5%~DR725 0_0402_5%~D
HW_GPS_DISABLE2#<40>
33P_0402_50V8J~D
33P_0402_50V8J~D
1
C612
C612
2
1 2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
C613
C613
2
PCIE_MCARD2_DET#_R
33P_0402_50V8J~D
33P_0402_50V8J~D
1
C614
C614
2
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
1
1
@
@
+
+
+
+
C1176
C1176
C615
C615
2
2
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
TYCO_1775861-1~D
TYCO_1775861-1~D
SIM Card Push-Push
+SIM_PWR
UIM_RESET
UIM_CLK
1
C616
C616
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
UIM_RESET
A A
UIM_CLK
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
@C629
@
@C628
@
1
1
C629
C628
2
2
JSIM1
JSIM1
1
VCC
2
RST
3
CLK
4
NC
MOLEX_475531001
MOLEX_475531001
CONN@
CONN@
U40
@U40
@
1
2
3
SRV05-4.TCT_SOT23-6~D
SRV05-4.TCT_SOT23-6~D
5
GND
GND
GND
VPP
6
5
4
5
UIM_VPP
6
UIM_DATA
7
I/O
8
NC
9
10
UIM_VPP
+SIM_PWR
UIM_DATA
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
@C631
@
@C630
@
1
1
C631
C630
2
2
+3.3V_PCIE_WWAN+3.3V_PCIE_WW AN
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
GND2
LED_WWAN_OUT#
PWR
Rail
+3.3V
+3.3Vaux
+1.5V
4
R1157 0_0402_5%~DR1157 0_0402_5%~D
R1158 0_0402_5%~DR1158 0_0402_5%~D
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
1 2
R704 0_0402_5%~DR704 0_0402_5%~D
WWAN_SMBCLK
WWAN_SMBDAT
USBP5USBP5+
USB_MCARD2_DET#
LED_WWAN_OUT#LED_WWAN_OUT#
+3.3V_PCIE_WWAN
R719
R719
G
G
2
1 2
100K_0402_5%~D
100K_0402_5%~D
S
S
Q77
Q77
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Voltage
Tolerance
+-9%
+-9%
+-5%
4
+3.3V_PCIE_WWAN
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
@R1159
@
@R1160
@
12
12
R1159
R1160
12
12
R697 0_0402_5%~D@ R697 0_0402_5%~D@
13
D
D
WWAN_SMBCLK
WWAN_SMBDAT
+1.5V_RUN
+SIM_PWR
WWAN_RADIO_DIS# <40>
PCH_PLTRST#_EC <17,33,36,40,41>
USBP5- <17>
USBP5+ <17>
USB_MCARD2_DET# <18>
PCIE_MCARD2_DET#USB_MCARD2_DET#
1 2
WIRELESS_LED# <40,44>
Primary Power Aux Power
Peak Normal Normal
1000 750
330
500
250 (Wake enable)
250
5 (Not wake enable)
375
NA
3
WLAN_RADIO_DIS#<40>
COEX2_WLAN_ACTIVE<42>
COEX1_BT_ACTIVE<42>
COEX2_WLAN_ACTIVE
C600
@C600
@
33P_0402_50V8J~D
33P_0402_50V8J~D
1 2
R693 0_0402_5%~D@ R693 0_0402_5%~D@
D31
D31
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
MINI2CLK_REQ#<15>
CLK_PCIE_MINI2#<15>
CLK_PCIE_MINI2<15>
HOST_DEBUG_RX<41>
PCIE_PRX_WLANTX_N2<15>
PCIE_PRX_WLANTX_P2<15>
PCIE_PTX_WLANRX_N2<15>
PCIE_PTX_WLANRX_P2<15>
1
2
PCIE_MCARD1_DET#<18>
PCH_CL_CLK1<15>
PCH_CL_DATA1<15>
PCH_CL_RST1#<15>
WLAN_RADIO_DIS#_R
21
PCIE_WAKE#<29,36,41>
MSCLK<41>
PCIE_WAKE#
1 2
R700 0_0402_5%~DR700 0_0402_5%~D
1 2
R702 0_0402_5%~DR702 0_0402_5%~D
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
C596 0.1U_0402_10V7K~DC596 0.1U_0402_10V7K~D
PCIE_PTX_WLANRX_N2_C
1 2
PCIE_PTX_WLANRX_P2_C
1 2
C598 0.1U_0402_10V7K~DC598 0.1U_0402_10V7K~D
1 2
R707 0_0402_5%~DR707 0_0402_5%~D
2
Mini WLAN/WIMAX H=4
+3.3V_WLAN
check
+1.5V_RUN
+3.3V_WLAN
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C601
C601
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@ C603
@
1
1
2
C603
C602
C602
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C605
C605
C604
C604
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
C606
C606
1
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
1
C607
C607
C608
C608
1
2
1/2 Minicard Pink Pather/60GHz Card H=4
CONN@
CONN@
JMINI3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
2
JMINI3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
TYCO_1775861-1~D
TYCO_1775861-1~D
1 2
1 2
1 2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
2
C623
C623
MINI3CLK_REQ#
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
PCH_PLTRST#_EC
PCLK_80H
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
2
1
PCIE_WAKE#
1 2
R709 0_0402_5%~DR709 0_0402_5%~D
PCIE_PTX_WPANRX_N5_C
PCIE_PTX_WPANRX_P5_C
PCIE_MCARD3_DET#
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C624
C624
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
C626
C626
C625
C625
2
1
COEX2_WLAN_ACTIVE
MINI3CLK_REQ#<15>
CLK_PCIE_MINI3#<15>
CLK_PCIE_MINI3<15>
PCLK_80H<15>
PCIE_PRX_WPANTX_N5<15>
PCIE_PRX_WPANTX_P5<15>
PCIE_PTX_WPANRX_N5<15>
PCIE_PTX_WPANRX_P5<15>
+3.3V_RUN
+1.5V_RUN
+3.3V_PCIE_FLASH
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C620
C620
C619
C619
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C617 0.1U_0402_10V7K~DC617 0.1U_0402_10V7K~D
C618 0.1U_0402_10V7K~DC618 0.1U_0402_10V7K~D
PCIE_MCARD3_DET#<18>
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@ C621
@
1
1
C621
2
2
R711 100K_0402_5%~DR711 100K_0402_5%~D
C622
C622
CONN@
CONN@
JMINI2
JMINI2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
TYCO_1775861-1~D
TYCO_1775861-1~D
WIMAX_LED#
WLAN_LED#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3.3V_PCIE_FLASH+3.3V_PCIE_FLASH
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
R718
R718
+3.3V_WLAN
1 2
1
PCIE_MCARD1_DET#
1 2
R698 0_0402_5%~D@ R698 0_0402_5%~D@
+1.5V_RUN
R705
R705
100K_0402_5%~D
100K_0402_5%~D
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
1 2
R710 0_0402_5%~DR710 0_0402_5%~D
USBP6USBP6+
USB_MCARD3_DET#
PCIE_MCARD1_DET#
USB_MCARD1_DET#
MSDATA
WLAN_RADIO_DIS#_R
R703 0_0402_5%~DR703 0_0402_5%~D
USBP4USBP4+PCIE_MCARD1_DET#
USB_MCARD1_DET#
WIMAX_LED#
WLAN_LED#
1 2
R706 0_0402_5%~D@ R706 0_0402_5%~D@
WIMAX_LED# STUDY FOR DEBUG
1 2
100K_0402_5%~D
100K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q124A
Q124A
USB_MCARD3_DET# PCIE_MCARD3_DET#
+1.5V_RUN
PCH_PLTRST#_EC
R712 100K_0402_5%~D@R712 100K_0402_5%~D@
WPAN Noise
USB_MCARD3_DET#
1
@C627
@
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
1 2
R692 100K_0402_5%~DR692 100K_0402_5%~D
PCIE_MCARD1_DET#USB_MCARD1_DET#
1 2
R699 100K_0402_5%~D@R699 100K_0402_5%~D@
1 2
R701 100K_0402_5%~DR701 100K_0402_5%~D
1 2
C595 4700P_0402_25V7K~DC595 4700P_0402_25V7K~D
PCH_PLTRST#_EC
12
MSDATA
+3.3V_WLAN
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
Q124B
Q124B
1 2
R708 0_0402_5%~D@R708 0_0402_5%~D@
LPC_LFRAME# <14,33,40,41>
LPC_LAD3 <14,33,40,41>
LPC_LAD2 <14,33,40,41>
LPC_LAD1 <14,33,40,41>
LPC_LAD0 <14,33,40,41>
USBP6- <17>
USBP6+ <17>
12
C627
+3.3V_ALW_PCH
+3.3V_RUN
HOST_DEBUG_TX <41>
USBP4- <17>
USBP4+ <17>
USB_MCARD1_DET# <14,18>
MSDATA <41>
WIRELESS_LED#WIRELESS_LED#
just reserve
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Mini Card
Mini Card
Mini Card
LA-7782
LA-7782
LA-7782
35 66Friday, June 10, 2011
35 66Friday, June 10, 2011
35 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 36
5
4
3
2
1
Power Control for Mini card2
+3.3V_ALW
D D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
AUX_EN_WOWL<40>
C C
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
MCARD_WWAN_PWREN<40>
B B
+3.3V_ALW
Q39A
Q39A
2
12
R716
R716
100K_0402_5%~D
100K_0402_5%~D
Power Control for Mini card1
Q41A
Q41A
12
100K_0402_5%~D
100K_0402_5%~D
+PWR_SRC_S
100K_0402_5%~D
100K_0402_5%~D
12
R713
R713
5
61
+3.3V_ALW
100K_0402_5%~D
100K_0402_5%~D
12
R721
R721
MCARD_WWAN_PWREN#
61
2
R726
R726
100K_0402_5%~D
100K_0402_5%~D
6
12
R714
R714
2
1
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q39B
Q39B
4
Q38
Q38
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
S
S
45
G
G
3
1M_0402_5%~D
1M_0402_5%~D
12
+PWR_SRC_S
5
R1620
R1620
12
3
4
+3.3V_ALW
100K_0402_5%~D
100K_0402_5%~D
R722
R722
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q41B
Q41B
1
2
+3.3V_WLAN
12
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C632
C632
Q40
Q40
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
4700P_0402_25V7K~D
1M_0402_5%~D
1M_0402_5%~D
12
4700P_0402_25V7K~D
1
R1625
R1625
C644
C644
2
R715
R715
20K_0402_5%~D
20K_0402_5%~D
+3.3V_PCIE_WWAN
12
R723
R723
1K_0402_1%~D
1K_0402_1%~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
Q73
Q73
G
G
S
S
MCARD_WWAN_PWREN#
2
+1.5V_RUN
+3.3V_RUN +3.3V_CARD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C635
C635
2
SIO_SLP_S3#<11,16,28,40,43,56>
RUN_ON<28,40,43,56,64>
PCH_PLTRST#_EC<17,33,35,40,41>
1 2
R734 0_0402_5%~DR734 0_0402_5%~D
1 2
R717 0_0402_5%~D@R717 0_0402_5%~D@
0.1U_0402_25V6K~D
+3.3V_RUN
+3.3V_CARD
+1.5V_CARD
+1.5V_RUN
USBP10-<17>
USBP10+<17>
1
2
1
C634
C634
2
EXPRCRD_STBY_R#
Note: Add connection on pin4, pin5, pin 13
and pin14 to support GMT 2nd source part
Power Control for Mini card3
+3.3V_ALW
+3.3V_ALW
Q43A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
MCARD_MISC_PWREN<40>
A A
Q43A
2
12
R733
R733
100K_0402_5%~D
100K_0402_5%~D
+PWR_SRC_S
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
12
R728
R728
61
100K_0402_5%~D
12
R729
R729
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q43B
Q43B
5
4
Q42
Q42
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
1M_0402_5%~D
1M_0402_5%~D
12
R1628
R1628
1
2
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C650
C650
+3.3V_PCIE_FLASH
12
20K_0402_5%~D
20K_0402_5%~D
R730
R730
+3.3V_CARDAUX
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C646
C646
2
Express Card PWR S/W
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C633
C633
U41
U41
17
12
20
1
6
19
4
5
13
14
16
TPS2231MRGPR-2_QFN20_4X4~D
TPS2231MRGPR-2_QFN20_4X4~D
AUXOUT
AUXIN
3.3VIN23.3VOUT
1.5VOUT
1.5VIN
SHDN#
STBY#
SYSRST#
CPUSB#
OC#
NC
NC
RCLKEN
NC
NC
NC
Express Card Conn.
1 2
R724 0_0402_5%~D@R724 0_0402_5%~D@
1 2
R727 0_0402_5%~D@R727 0_0402_5%~D@
1
1
4
4
L49 DLW21SN900SQ2L_0805_4P~DL49 DLW 21SN900SQ2L_0805_4P~D
+3.3V_CARD
2
2
3
3
CARD_SMBDAT<41>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C649
C649
PCIE_PRX_EXPTX_N3<15>
2
PCIE_PRX_EXPTX_P3<15>
PCIE_PTX_EXPRX_N3<15>
PCIE_PTX_EXPRX_P3<15>
PERST#
CPPE#
GND
PAD
CARD_SMBCLK<41>
CLK_PCIE_EXP#<15>
CLK_PCIE_EXP<15>
+3.3V_CARDAUX
0.1U_0402_25V6K~D
R731
R731
+1.5V_CARD
2.2K_0402_5%~D
2.2K_0402_5%~D
12
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C640
C640
C641
C641
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C645
R732
R732
C645
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C642
C642
C643
C643
2
2
15
3
11
CARD_RESET#
8
EXPRCRD_CPPE#
10
CPUSB#
9
18
7
21
+3.3V_SUS
2.2K_0402_5%~D
2.2K_0402_5%~D
12
USBP10_DUSBP10_D+
CPUSB#
CARD_SMBCLK
CARD_SMBDAT
PCIE_WAKE#<29,35,41>
EXPCLK_REQ#<15>
CARD_RESET#
EXPRCRD_CPPE#
C647 0.1U_0402_10V7K~DC647 0.1U_0402_10V7K~D
PCIE_PTX_EXPRX_N3_C
1 2
PCIE_PTX_EXPRX_P3_C
1 2
C648 0.1U_0402_10V7K~DC648 0.1U_0402_10V7K~D
+1.5V_CARD+3.3V_SUS
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C637
C637
2
CONN@
CONN@
JEXP1
JEXP1
1
GND1
2
USB_D-
3
USB_D+
4
CPUSB#
5
RESERVED
6
RESERVED
7
SMB_CLK
8
SMB_DAT
9
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PER_N0
PER_P0
GND
PET_N0
PET_P0
GND
GND
GND
GND
GND
T-SOL_5421005002000-9_NR
T-SOL_5421005002000-9_NR
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C638
C638
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCIE-SATA SW / PCIE PWR
PCIE-SATA SW / PCIE PWR
PCIE-SATA SW / PCIE PWR
LA-7782
LA-7782
LA-7782
36 66Friday, June 10, 2011
36 66Friday, June 10, 2011
36 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 37
5
D D
4
3
2
1
D79
L97
USB3RN2<17>
USB3RP2<17>
USB3TN2<17>
USB3TP2<17>
C C
USB_PWR_SHR_EN#<40>
B B
USB3RN2
USB3RP2 USB3RP2_D+
12
C410 0.01U_0402_16V7K~DC410 0.01U_0402_16V7K~D
C411 0.01U_0402_16V7K~DC411 0.01U_0402_16V7K~D
USB3TP2_C USB3TP2_D+
12
R1626 0_0402_5%~DR1626 0_0402_5%~D
L97
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R1608 0_0402_5%~D@R1608 0_0402_5%~D@
R1609 0_0402_5%~D@R1609 0_0402_5%~D@
1 2
3
3
2
2
1 2
1 2
L98
L98
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
1 2
R1612 0_0402_5%~D@R1612 0_0402_5%~D@
1 2
R1607 0_0402_5%~D@R1607 0_0402_5%~D@
3
3
2
2
SB#
USBP0-<17>
USBP0+<17>
USB3RN2_D- USB3RN2_D-
USB3TN2_D-USB3TN2_C
USB_PWR_SHR_VBUS_EN<40>
+5V_ALW +5V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C715
C715
2
USB3RN2_DUSB3RP2_D+
USB3TN2_DUSB3TP2_D+
USBP1+<17>
USBP1-<17>
U2
U2
8
7
6
5
CEN
CB
DM
TDM
DP
TDP
SELCDP
VDD
Thermal Pad
SLG55584AVTR_TDFN8_2X2
SLG55584AVTR_TDFN8_2X2
D79
1
2
4
5
3
8
8
IP4292CZ10-TB_XSON10U10~D
IP4292CZ10-TB_XSON10U10~D
1 2
R784 0_0402_5%~DR784 0_0402_5%~D
PWRSHARE_EN
1
USBP0_D-
2
USBP0_D+
3
SEL
4
9
10
USB3RP2_D+
9
USB3TN2_D-
7
USB3TP2_D+
6
L52
L52
4
4
1
1
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
R737 0_0402_5%~D@R737 0_0402_5%~D@
R739 0_0402_5%~D@R739 0_0402_5%~D@
R1614
R1614
10K_0402_5%~D
10K_0402_5%~D
1 2
R1613
@ R1613
@
10K_0402_5%~D
10K_0402_5%~D
1 2
1 2
1 2
+5V_ALW
2
G
G
USBP1_D+
3
3
USBP1_D-
2
2
R816
R816
100K_0402_5%~D
100K_0402_5%~D
1 2
PWRSHARE_EN#
13
D
D
Q48
Q48
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
+5V_USB_CHG_PWR
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C655
C655
2
+5V_ALW
10U_0805_10V6K~D
10U_0805_10V6K~D
1
C676
C676
2
JUSB2
USB3TP2_D+
USB3TN2_D-
USBP1_DUSBP1_D+
USB3RP2_D+
2
3
D73
PESD5V0U2BT_SOT23-3~D
D73
PESD5V0U2BT_SOT23-3~D
USB3RN2_D-
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
ESATA_USB_PWR_EN#<40>
C675
C675
PWRSHARE_EN#
1
2
JUSB2
9
SSTX+
1
VBUS
8
SSTX-
2
D-
7
GND
3
D+
6
SSRX+
4
GND
5
SSRX-
SANTA_370300-1
SANTA_370300-1
U48
U48
1
GND
2
IN
3
IN
4
EN1#
EN2#5FAULT#2
TPS2560DRCR-PG1.1_SON10_3X3~D
TPS2560DRCR-PG1.1_SON10_3X3~D
GND
GND
GND
GND
FAULT1#
OUT1
OUT2
T-PAD
10
11
12
13
+SATA_SIDE_PWR
10
9
8
7
ILIM
6
11
USB_OC1# <17>
USB_OC0# <17>
+5V_USB_CHG_PWR
12
R748
R748
24.9K_0402_1%~D
24.9K_0402_1%~D
USBP0_R_D-
+5V_USB_CHG_PWR
150U_B2_6.3V-M~D
150U_B2_6.3V-M~D
1
+
+
C651
C651
2
JUSB1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C654
C654
3
2
USB3TP1_D+
USB3TN1_D-
USBP0_R_DUSBP0_R_D+
USB3RP1_D+
2
D72
PESD5V0U2BT_SOT23-3~D
D72
PESD5V0U2BT_SOT23-3~D
USB3RN1_D-
1
JUSB1
9
SSTX+
1
VBUS
8
SSTX-
2
D-
7
GND
3
D+
6
SSRX+
4
GND
5
SSRX-
SANTA_370300-1
SANTA_370300-1
GND
GND
GND
GND
10
11
12
13
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
USB x2
USB x2
USB x2
LA-7782
LA-7782
LA-7782
37 66Friday, June 10, 2011
37 66Friday, June 10, 2011
37 66Friday, June 10, 2011
1
0.1
0.1
0.1
D78
L95
USB3RN1<17>
USB3RP1<17>
USB3TN1<17>
A A
USB3TP1<17>
USB3RN1
USB3RP1 USB3RP1_D+
12
C412 0.01U_0402_16V7K~DC412 0.01U_0402_16V7K~D
USB3TP1_C USB3TP1_D+
12
C413 0.01U_0402_16V7K~DC413 0.01U_0402_16V7K~D
5
L95
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
1 2
R1605 0_0402_5%~D@R1605 0_0402_5%~D@
1 2
R1604 0_0402_5%~D@R1604 0_0402_5%~D@
L96
L96
4
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R1606 0_0402_5%~D@R1606 0_0402_5%~D@
R1603 0_0402_5%~D@R1603 0_0402_5%~D@
4
1
1 2
1 2
3
3
2
2
3
2
USB3RN1_DUSB3RP1_D+
USB3TN1_DUSB3TP1_D+
3
2
USB3TN1_D-USB3TN1_C
4
D78
1
2
4
5
3
8
8
IP4292CZ10-TB_XSON10U10~D
IP4292CZ10-TB_XSON10U10~D
USBP0_D+ USBP0_R_D+
USBP0_D-
USB3RN1_D-USB3RN1_D-
10
USB3RP1_D+
9
USB3TN1_D-
7
USB3TP1_D+
6
L51
L51
4
4
1
1
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
1 2
R736 0_0402_5%~D@ R736 0_0402_5%~D@
1 2
R740 0_0402_5%~D@ R740 0_0402_5%~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3
2
2
3
Page 38
5
4
3
2
1
ESATA Repeater
D D
ESATA_PTX_DRX_P4_C<14>
ESATA_PTX_DRX_N4_C<14>
ESATA_PRX_DTX_N4_C<14>
ESATA_PRX_DTX_P4_C<14>
C C
ESATA_PTX_DRX_P4_C
ESATA_PTX_DRX_N4_C
ESATA_PRX_DTX_N4_C
ESATA_PRX_DTX_P4_C ESATA_PRX_DTX_P4
+3.3V_RUN_U44
1 2
R741 0_0402_5%~DR741 0_0402_5%~D
ESATA_PTX_DRX_P4
12
C663 0.01U_0402_16V7K~DC663 0.01U_0402_16V7K~D
C664 0.01U_0402_16V7K~DC664 0.01U_0402_16V7K~D
C665 0.01U_0402_16V7K~DC665 0.01U_0402_16V7K~D
C666 0.01U_0402_16V7K~DC666 0.01U_0402_16V7K~D
ESATA_PTX_DRX_N4
12
ESATA_PRX_DTX_N4
12
12
+3.3V_RUN +3.3V_RUN_U44
U44
U44
7
EN
17
NC_GND_VDD
19
NC_GND_VDD
18
NC_GND_VDD
1
A_INp
2
A_INn
4
B_OUTn
5
B_OUTp
3
GND
13
GND
21
GND
PS8513BTQFN20GTR-A0_TQFN20_4X4
PS8513BTQFN20GTR-A0_TQFN20_4X4
PJP9
PJP9
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
VCC
VCC
PREXT/NC/VDD
NC/GND/VDD
A_PRE
B_PRE
A_OUTp
A_OUTn
B_INp
B_INn
6
16
20
10
9
8
15
14
11
12
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1
C662
C662
C661
C661
2
2
REXT
ESATA_PE1
ESATA_PE2
ESATA_PTX_DRX_P4_RP
ESATA_PTX_DRX_N4_RP
ESATA_PRX_DTX_P4_RP
ESATA_PRX_DTX_N4_RP
+SATA_SIDE_PWR
150U_B2_6.3V-M~D
150U_B2_6.3V-M~D
1
C667
C667
+
+
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
12
R1595
R1595
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C668
C668
1
2
0_0402_5%~D
@
0_0402_5%~D
@
0_0402_5%~D
12
R1594
R1594
0_0402_5%~D
12
12
R742
R742
R743
R743
JESA1
JESA1
1
USBP2_DUSBP2_D+
B B
L90
L90
USBP2+<17>
USBP2-<17>
1
1
4
4
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
1 2
R1150 0_0402_5%~D@R1150 0_0402_5%~D@
1 2
R1151 0_0402_5%~D@R1151 0_0402_5%~D@
USBP2_D+
2
2
USBP2_D-
3
3
2
3
D74
D74
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
1
ESATA_PTX_DRX_P4_RP
ESATA_PTX_DRX_N4_RP
ESATA_PRX_DTX_N4_RP
ESATA_PRX_DTX_P4_RP SATA_PRX_DTX_P4
SATA_PTX_DRX_P4
1 2
C671 0.01U_0402_16V7K~DC671 0.01U_0402_16V7K~D
SATA_PTX_DRX_N4
1 2
C672 0.01U_0402_16V7K~DC672 0.01U_0402_16V7K~D
SATA_PRX_DTX_N4
1 2
C673 0.01U_0402_16V7K~DC673 0.01U_0402_16V7K~D
1 2
C674 0.01U_0402_16V7K~DC674 0.01U_0402_16V7K~D
VBUS
2
D-
3
D+
4
GND
5
GND
6
A+
7
A-
8
GND
9
B-
10
B+
11
GND
12
GND
13
GND
14
GND
15
GND
TYCO_2129156-3
TYCO_2129156-3
CONN@
CONN@
ESATA
ESATA
USB
USB
Place D74 close to JESATA1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB/ESATA/IO/MDC
USB/ESATA/IO/MDC
USB/ESATA/IO/MDC
LA-7782
LA-7782
LA-7782
38 66Friday, June 10, 2011
38 66Friday, June 10, 2011
38 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 39
2
CONN@
CONN@
JDOCK1
JDOCK1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
Shield_G
JAE_WD2F144WB1
JAE_WD2F144WB1
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
2
4
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
149
150
151
152
159
160
161
162
163
164
DPC_CA_DET
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
DPC_DOCK_AUX
DPC_DOCK_AUX#
DPC_GPU_HPDDPD_GPU_HPD
SATA_PRX_DKTX_P5
SATA_PRX_DKTX_N5
SATA_PTX_DKRX_P5
SATA_PTX_DKRX_N5
DOCK_DET_R#
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
C703
C703
1
2
DOCK_AC_OFF <40,63>
DOCK_LOM_SPD100LED_ORG# <32>
DPC_CA_DET <27>DPD_CA_DET<27>
C691 0.1U_0402_10V7K~DC691 0.1U_0402_10V7K~D
12
C680 0.1U_0402_10V7K~DC680 0.1U_0402_10V7K~D
12
C682 0.1U_0402_10V7K~DC682 0.1U_0402_10V7K~D
12
C684 0.1U_0402_10V7K~DC684 0.1U_0402_10V7K~D
12
C693 0.1U_0402_10V7K~DC693 0.1U_0402_10V7K~D
12
C686 0.1U_0402_10V7K~DC686 0.1U_0402_10V7K~D
12
C688 0.1U_0402_10V7K~DC688 0.1U_0402_10V7K~D
12
C694 0.1U_0402_10V7K~DC694 0.1U_0402_10V7K~D
12
DPC_DOCK_AUX <27>
DPC_DOCK_AUX# <27>
ACAV_DOCK_SRC# <63>
DAT_DDC2_DOCK <25>
CLK_DDC2_DOCK <25>
12
C697 0.01U_0402_16V7K~DC697 0.01U_0402_16V7K~D
12
C698 0.01U_0402_16V7K~DC698 0.01U_0402_16V7K~D
1 2
C699 0.01U_0402_16V7K~DC699 0.01U_0402_16V7K~D
1 2
C700 0.01U_0402_16V7K~DC700 0.01U_0402_16V7K~D
USBP8+ <17>
USBP8- <17>
USBP3+ <17>
USBP3- <17>
CLK_KBD <41>
DAT_KBD <41>
USB3RN4 <17>
USB3RP4 <17>
USB3TN4 <17>
USB3TP4 <17>
BREATH_LED# <40,44>
DOCK_LOM_ACTLED_YEL# <32>
DOCK_LOM_TRD0+ <32>
DOCK_LOM_TRD0- <32>
DOCK_LOM_TRD1+ <32>
DOCK_LOM_TRD1- <32>
+LOM_VCT
DOCK_LOM_TRD2+ <32>
DOCK_LOM_TRD2- <32>
DOCK_LOM_TRD3+ <32>
DOCK_LOM_TRD3- <32>
DOCK_DCIN_IS+ <62>
DOCK_DCIN_IS- <62>
DOCK_POR_RST# <41>
+DOCK_PWR_BAR
12
RE11
@RE11
@
10_0402_1%~D
10_0402_1%~D
1
CE8
@CE8
@
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
2
DPC_GPU_LANE_P0 <46>
DPC_GPU_LANE_N0 <46>
DPC_GPU_LANE_P1 <46>
DPC_GPU_LANE_N1 <46>
DPC_GPU_LANE_P2 <46>
DPC_GPU_LANE_N2 <46>
DPC_GPU_LANE_P3 <46>
DPC_GPU_LANE_N3 <46>
SATA_PRX_DKTX_P5_C <14>
SATA_PRX_DKTX_N5_C <14>
SATA_PTX_DKRX_P5_C <14>
SATA_PTX_DKRX_N5_C <14>
+LOM_VCT
1
@
@
C701
C701
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
D32
D32
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
DOCK_AC_OFF
2
SLICE_BAT_PRES#
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
@
@
1
CE6
CE6
2
DOCK_DET_1
DPD_CA_DET
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1
DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2
DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
DPD_DOCK_AUX
DPD_DOCK_AUX#
BLUE_DOCK
RED_DOCK
GREEN_DOCK
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
2
3
@
C702
C702
@
1
D33
D33
DOCK_LOM_SPD10LED_GRN#<32>
DPD_GPU_LANE_P0<46>
DPD_GPU_LANE_N0<46>
DPD_GPU_LANE_P1<46>
DPD_GPU_LANE_N1<46>
DPD_GPU_LANE_P2<46>
DPD_GPU_LANE_N2<46>
DPD_GPU_LANE_P3<46>
DPD_GPU_LANE_N3<46>
B B
A A
DPD_GPU_HPD<45> DPC_GPU_HPD <45>
Close to DOCK
Its for Enhance ESD on dock issue.
DPD_GPU_HPD
12
R757
R757
100K_0402_5%~D
100K_0402_5%~D
C690 0.1U_0402_10V7K~DC690 0.1U_0402_10V7K~D
C679 0.1U_0402_10V7K~DC679 0.1U_0402_10V7K~D
C681 0.1U_0402_10V7K~DC681 0.1U_0402_10V7K~D
C683 0.1U_0402_10V7K~DC683 0.1U_0402_10V7K~D
C692 0.1U_0402_10V7K~DC692 0.1U_0402_10V7K~D
C685 0.1U_0402_10V7K~DC685 0.1U_0402_10V7K~D
C687 0.1U_0402_10V7K~DC687 0.1U_0402_10V7K~D
C689 0.1U_0402_10V7K~DC689 0.1U_0402_10V7K~D
1
2
+DOCK_PWR_BAR
12
12
12
12
12
12
12
12
DPD_DOCK_AUX<27>
DPD_DOCK_AUX#<27>
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
C695
C695
+NBDOCK_DC_IN_SS
BLUE_DOCK<25>
RED_DOCK<25>
GREEN_DOCK<25>
HSYNC_DOCK<25>
VSYNC_DOCK<25>
CLK_MSE<41>
DAT_MSE<41>
DAI_BCLK#<30>
DAI_LRCK#<30>
DAI_DI<30>
DAI_DO#<30>
DAI_12MHZ#<30>
D_LAD0<40>
D_LAD1<40>
D_LAD2<40>
D_LAD3<40>
D_LFRAME#<40>
D_CLKRUN#<40>
D_SERIRQ<40>
D_DLDRQ1#<40>
CLK_PCI_DOCK<17>
DOCK_SMB_CLK<41>
DOCK_SMB_DAT<41>
DOCK_SMB_ALERT#<40,63>
DOCK_PSID<53>
DOCK_PWR_BTN#<41>
SLICE_BAT_PRES#<40,63> DOCK_DET# <40>
1
2
21
1
DAI_BCLK#DAI_12MHZ#
12
RE12
@RE12
@
10_0402_1%~D
10_0402_1%~D
1
CE9
@CE9
@
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
2
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1
C696
C696
Close to DOCK
2
Its for Enhance ESD on dock issue.
DPC_GPU_HPD
12
R758
R758
100K_0402_5%~D
100K_0402_5%~D
DOCK_DET#
1 2
R755 100K_0402_5%~DR755 100K_0402_5%~D
CLK_PCI_DOCK
12
R756
R756
33_0402_5%~D
33_0402_5%~D
1
C704
C704
12P_0402_50V8J~D
12P_0402_50V8J~D
2
+3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DOCKING CONN
DOCKING CONN
DOCKING CONN
LA-7782
LA-7782
LA-7782
39 66Friday, June 10, 2011
39 66Friday, June 10, 2011
39 66Friday, June 10, 2011
0.1
0.1
0.1
Page 40
+3.3V_ALW
1 2
R796 10K_0402_5%~DR796 10K_0402_5%~D
1 2
R798 100K_0402_5%~DR798 100K_0402_5%~D
1 2
R761 100K_0402_5%~DR761 100K_0402_5%~D
1 2
D D
C C
B B
R763 100K_0402_5%~DR763 100K_0402_5%~D
1 2
R760 100K_0402_5%~DR760 100K_0402_5%~D
1 2
R774 100K_0402_5%~DR774 100K_0402_5%~D
1 2
R776 100K_0402_5%~DR776 100K_0402_5%~D
1 2
R768 10K_0402_5%~DR768 10K_0402_5%~D
1 2
R769 100K_0402_5%~DR769 100K_0402_5%~D
1 2
R778 100K_0402_5%~DR778 100K_0402_5%~D
1 2
R762 10K_0402_5%~DR762 10K_0402_5%~D
+3.3V_RUN
1 2
R457 100K_0402_5%~DR457 100K_0402_5%~D
1 2
R766 100K_0402_5%~DR766 100K_0402_5%~D
1 2
R772 10K_0402_5%~D@ R772 10K_0402_5%~D@
1 2
R767 100K_0402_5%~DR767 100K_0402_5%~D
1 2
R775 10K_0402_5%~DR775 10K_0402_5%~D
1 2
R1582 100K_0402_5%~DR1582 100K_0402_5%~D
1 2
R1583 100K_0402_5%~DR1583 100K_0402_5%~D
1 2
R1154 100K_0402_5%~DR1154 100K_0402_5%~D
1 2
R3 100K_0402_5%~DR3 100K_0402_5%~D
+3.3V_ALW
VGA_ID
1 2
R800 100K_0402_5%~D@R800 100K_0402_5%~D@
5
DYN_TURB_PWR_ALRT#
HW_GPS_DISABLE2#
PROCHOT_GATE
CPU_DETECT#
SLICE_BAT_PRES#
WWAN_RADIO_DIS#
USB_PWR_SHR_EN#
USB_SIDE_EN#
ESATA_USB_PWR_EN#
USB_PWR_SHR_VBUS_EN
DOCK_SMB_ALERT#
MCARD_PCIE_SATA#
WIRELESS_ON#/OFF
SP_TPM_LPC_EN
LCD_TST
SYS_LED_MASK#
DGPU_PWR_EN
GFX_MEM_VTT_ON
DP_HDMI_HPD
CHARGE_EN
VGA_ID
1 2
R803 100K_0402_5%~DR803 100K_0402_5%~D
CRT_SWITCH<25>
MDC_RST_DIS#<31>
MCARD_MISC_PWREN<36>
PROCHOT_GATE<62>
DOCK_SMB_ALERT#<39,63>
TOUCH_SCREEN_PD#<24>
USB_SIDE_EN#<31>
EN_I2S_NB_CODEC#<30>
USH_PWR_STATE#<33>
EN_DOCK_PWR_BAR<63>
PANEL_BKEN_EC<24>
ENVDD_PCH<16,24>
LCD_TST<24>
PSID_DISABLE#<53>
PBAT_PRES#<53,63>
DOCKED<32>
DOCK_DET#<39>
AUD_NB_MUTE#<30>
MCARD_WWAN_PWREN<36>
LCD_VCC_TEST_EN<24>
CCD_OFF<24>
AUD_HP_NB_SENSE<30,31>
ESATA_USB_PWR_EN#<37>
MODULE_ON<63>
SLICE_BAT_ON<63>
SLICE_BAT_PRES#<39,63>
MODULE_BATT_PRES#<53,63>
CHARGE_MODULE_BATT<63>
CHARGE_PBATT<63>
DEFAULT_OVRDE<63>
USB_PWR_SHR_EN#<37>
GFX_MEM_VTT_ON<49>
CPU_DETECT#<7>
DGPU_PWR_EN<45,64>
MOD_SATA_PCIE#_DET<29>
DP_HDMI_HPD<45>
ZODD_WAKE#<29>
BCM5882_ALERT#<33>
SUSACK#<16>
EDID_SELECT#<25>
DGPU_PWROK<18,64>
3.3V_RUN_GFX_ON<15,49>
SLP_ME_CSW_DEV#<14,18>
LAN_DISABLE#_R<32>
SYS_LED_MASK#<44>
SIO_EXT_WAKE#<18>
WIRELESS_LED#<35,44>
USB_PWR_SHR_VBUS_EN<37>
WLAN_RADIO_DIS#<35>
WIRELESS_ON#/OFF<31>
BT_RADIO_DIS#<42>
WWAN_RADIO_DIS#<35>
SYS_PWROK<7,16>
DGPU_SELECT#<23,24,25>
CPU_VTT_ON<58>
PCH_DPWROK<16>
R797 0_0402_5%~DR797 0_0402_5%~D
1 2
VGA_ID0
Discrete
0
UMA 1
A A
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ME_FWP
12
R793
@ R793
@
1K_0402_1%~D
1K_0402_1%~D
5
4
CRT_SWITCH
MDC_RST_DIS#
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WWAN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
CHARGE_MODULE_BATT
CHARGE_PBATT
DEFAULT_OVRDE
USB_PWR_SHR_EN#
GFX_MEM_VTT_ON
MCARD_PCIE_SATA#
CPU_DETECT#
DGPU_PWR_EN
MOD_SATA_PCIE#_DET
DP_HDMI_HPD
ZODD_WAKE#
BCM5882_ALERT#
EDID_SELECT#
DGPU_PWROK
VGA_ID
3.3V_RUN_GFX_ON
SLP_ME_CSW_DEV#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
DYN_TURB_PWR_ALRT#
WIRELESS_LED#
USB_PWR_SHR_VBUS_EN
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
DGPU_SELECT#
CPU_VTT_ON
1 2
R802 0_0402_5%~D@R802 0_0402_5%~D@
4
U46
U46
B52
GPIOA0
A49
GPIOA1
B53
GPIOA2
A50
GPIOA3
B54
GPIOA4
A51
GPIOA5
B55
GPIOA6
A52
GPIOA7
A33
GPIOB0
B36
GPIOB1
A34
GPOC2
B37
GPOC3
A35
GPOC4
B38
GPOC5
A36
GPOC6/TACH4
A37
GPIOC7
B40
GPIOD0
A38
GPIOC1
B41
GPIOC0
A39
GPIOB7
B42
GPIOB6
A40
GPIOB5
B43
GPIOB4
A41
GPIOB3
B44
GPIOB2
B32
GPIOD1
A31
GPIOD2
B33
GPIOD3
B15
GPIOD4
A15
GPIOD5
B16
GPIOD6
A16
GPIOD7
A1
GPIOE0/RXD
B2
GPIOE1/TXD
A2
GPIOE2/RTS#
B3
GPIOE3/DSR#
A3
GPIOE4/CTS#
B45
GPIOE5/DTR#
A42
GPIOE6/RI#
B4
GPIOE7/DCD#
A59
GPIOF0
B62
GPIOF1
A58
GPIOF2
B61
GPIOF3/TACH8
A56
GPIOF4/TACH7
B59
GPIOF5
A55
GPIOF6
B58
GPIOF7
B47
GPIOG0/TACH5
A45
GPIOG1
B48
GPIOG2
A46
GPIOG3
B49
GPIOG4
A47
GPIOG5
B50
GPIOG6
A48
GPIOG7/TACH6
B13
GPIOH0
A13
GPIOH1
A53
SYSOPT1/GPIOH2
B57
SYSOPT0/GPIOH3
B14
GPIOH4
A14
GPIOH5
B17
GPIOH6
B18
GPIOH7
+3.3V_ALW_U46
1
2
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
GPIOK1/TACH3
14.318MHZ/GPIOM0
ECE5048-LZY_DQFN132_11X11~D
ECE5048-LZY_DQFN132_11X11~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
C710
C710
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
VSS
EP
DB Version 0.4
DB Version 0.4
3
2
PJP7
PJP7
PAD-OPEN1x1m
PAD-OPEN1x1m
12
1
C709
C709
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
SIO_SLP_A#
B63
0.75V_DDR_VTT_ON
A60
A61
B65
A62
1 2
B66
R765 0_0402_5%~DR765 0_0402_5%~D
A63
B67
A64
SIO_SLP_LAN#
A5
SIO_SLP_SUS#
B6
A6
MODC_EN
B7
DOCK_HP_DET
A7
DOCK_MIC_DET
B8
ME_FWP
A8
MASK_SATA_LED#
B9
B10
LED_SATA_DIAG_OUT#
A10
TEMP_ALERT#_R TEMP_ALERT#
B11
RUN_ON
A11
B12
A12
SUS_ON
B60
A57
BAT1_LED#
B64
B68
BAT2_LED#
A9
B1
USH_PWR_ON
A18
A44
HW_GPS_DISABLE2#
B34
BREATH_LED#
B39
B51
LPC_LAD0
A27
LPC_LAD1
A26
LPC_LAD2
B26
LPC_LAD3
B25
LPC_LFRAME#
A21
PCH_PLTRST#_EC
B22
CLK_PCI_5048
A28
CLKRUN#
B20
LPC_LDRQ0#
A23
LPC_LDRQ1#
A22
IRQ_SERIRQ
B21
CLK_SIO_14M
A32
B35
D_LAD0
B29
D_LAD1
B28
D_LAD2
A25
D_LAD3
A24
D_LFRAME#
B23
D_CLKRUN#
A19
D_DLDRQ1#
B24
D_SERIRQ
A20
BC_INT#_ECE5048
A29
BC_DAT_ECE5048
B31
BC_CLK_ECE5048
A30
RUNPWROK
A4
SP_TPM_LPC_EN
B56
B19
B46
B27
C1
1 2
R804 1K_0402_1%~DR804 1K_0402_1%~D
+CAP_LDO
1
2
1
C714
C714
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
C708
C708
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
SIO_SLP_A# <16,43,57>
0.75V_DDR_VTT_ON <55>
SIO_SLP_S4# <16>
SIO_SLP_S3# <11,16,28,36,43,56>
IMVP_PWRGD <60>
IMVP_VR_ON <60>
DOCK_AC_OFF_EC
AUX_EN_WOWL <36>
WLAN_LAN_DISB# <32>
SIO_SLP_LAN# <16,32>
SIO_SLP_SUS# <16>
GPIO_PSID_SELECT <53>
MODC_EN <29>
DOCK_HP_DET <30>
DOCK_MIC_DET <30>
ME_FWP <14>
MASK_SATA_LED# <44>
1.8V_RUN_PWRGD <56>
LED_SATA_DIAG_OUT# <44>
RUN_ON <28,36,43,56,64>
SPI_WP#_SEL <14>
SUS_ON <43>
BAT1_LED# <44>
BAT2_LED# <44>
HW_GPS_DISABLE2# <35>
BREATH_LED# <39,44>
LPC_LAD0 <14,33,35,41>
LPC_LAD1 <14,33,35,41>
LPC_LAD2 <14,33,35,41>
LPC_LAD3 <14,33,35,41>
LPC_LFRAME# <14,33,35,41>
PCH_PLTRST#_EC <17,33,35,36,41>
CLK_PCI_5048 <17>
CLKRUN# <16,33,41>
LPC_LDRQ0# <14>
LPC_LDRQ1# <14>
IRQ_SERIRQ <14,33,41>
CLK_SIO_14M <15>
EC_32KHZ_ECE5048 <41>
D_LAD0 <39>
D_LAD1 <39>
D_LAD2 <39>
D_LAD3 <39>
D_LFRAME# <39>
D_CLKRUN# <39>
D_DLDRQ1# <39>
D_SERIRQ <39>
BC_INT#_ECE5048 <41>
BC_DAT_ECE5048 <41>
BC_CLK_ECE5048 <41>
RUNPWROK <7,41>
SP_TPM_LPC_EN <33>
+CAP_LDO trace width 20 mils
1
2
trace width 20 mils
trace width 20 mils
T117PAD~D @T117PAD~D @
R794
@R794
@
10_0402_1%~D
10_0402_1%~D
C712
@C712
@
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
C707
C707
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
ACAV_IN_NB <41,62,63>
DOCK_AC_OFF_EC <63>
R738 0_0402_5%~DR738 0_0402_5%~D
12
1
2
2
1
2
1 2
CLK_PCI_5048CLK_SIO_14M
R795
@R795
@
10_0402_1%~D
10_0402_1%~D
C713
@C713
@
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
1
+3.3V_ALW
C706
C706
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+3.3V_ALW
1
B
2
A
12
1
2
1
C705
C705
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
C711 0.1U_0402_25V6K~D@ C711 0.1U_0402_25V6K~D@
1 2
5
P
2 1
4
O
D34
@D34
@
G
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
U47
@U47
@
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
TEMP_ALERT# <14,18>
+3.3V_ALW
LID_CL_SIO#
12
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
RUN_ON
CPU_VTT_ON
0.75V_DDR_VTT_ON
SLICE_BAT_ON
SUS_ON
12
R805
R805
100K_0402_5%~D
100K_0402_5%~D
R807 10_0402_1%~DR807 10_0402_1%~D
1
C716
C716
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
DOCK_AC_OFF <39,63>
R770
@R770
@
33K_0402_5%~D
33K_0402_5%~D
R777 100K_0402_5%~DR777 100K_0402_5%~D
R780 100K_0402_5%~DR780 100K_0402_5%~D
R782 100K_0402_5%~DR782 100K_0402_5%~D
R786 100K_0402_5%~DR786 100K_0402_5%~D
R789 100K_0402_5%~DR789 100K_0402_5%~D
R790 100K_0402_5%~DR790 100K_0402_5%~D
R791 100K_0402_5%~DR791 100K_0402_5%~D
R878 100K_0402_5%~DR878 100K_0402_5%~D
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ECE5048
ECE5048
ECE5048
LA-7782
LA-7782
LA-7782
1
+3.3V_RUN
12
12
12
12
12
12
12
12
LID_CL# <31,44>
40 66Friday, June 10, 2011
40 66Friday, June 10, 2011
40 66Friday, June 10, 2011
0.1
0.1
0.1
Page 41
5
+3.3V_ALW
C720
C720
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
5
U50
1.05V_VTTPWRGD<58,59>
VCCSAPWROK<59>
Modify name ne t
+3.3V_ALW
D D
C C
JTAG_RST#
1.05V_VTTPWRGD
VCCSAPWROK
PCIE_WAKE#
1 2
R759 10K_0402_5%~DR759 10K_0402_5%~D
BC_DAT_EMC4022
12
R821 100K_0402_5%~DR821 100K_0402_5%~D
BC_DAT_ECE5048
1 2
R814 100K_0402_5%~DR814 100K_0402_5%~D
BC_DAT_ECE1117
1 2
R817 100K_0402_5%~DR817 100K_0402_5%~D
PBAT_SMBDAT
1 2
R818 2.2K_0402_5%~DR818 2.2K_0402_5%~ D
PBAT_SMBCLK
1 2
R820 2.2K_0402_5%~DR820 2.2K_0402_5%~ D
LPC_LDRQ#_MEC
1 2
R823 100K_0402_5%~D@R823 100K_0402_5%~D@
CHARGER_SMBDAT
1 2
R827 2.2K_0402_5%~DR827 2.2K_0402_5%~ D
CHARGER_SMBCLK
1 2
R828 2.2K_0402_5%~DR828 2.2K_0402_5%~ D
+3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
12
R824
R824
JTAG_RST# citc uit
cl
100_0402_1%~D
100_0402_1%~D
12
@
@
1
R836
R836
2
ose to U51.B57
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C735
C735
32 KHz Clock
C741
C741
1 2
22P_0402_50V8J~D
22P_0402_50V8J~D
MEC_XTAL2
Y6
Y6
32.768KHZ_12.5PF_Q13FC1350000~D
32.768KHZ_12.5PF_Q13FC1350000~D
C743
C743
22P_0402_50V8J~D
22P_0402_50V8J~D
11
12
13
14
R885
@R885
@
C747
@ C747
@
1 2
1 2
+3.3V_ALW
CONN@
CONN@
JDEG2
JDEG2
1
1
2
2 2
3
3
4
4 4
5
5
6
6 6
7
7
8
8 8
9
9
10
10 10
G1
G2
G3
G4
ACES_87153-10411
ACES_87153-10411
12
1
2
49.9_0402_1%~D
49.9_0402_1%~D
12
R864
R864
MSCLK
MSDATA
HOST_DEB_RX
MEC_XTAL1
B B
A A
Place closely pin A29
CLK_PCI_MEC
10_0402_1%~D
10_0402_1%~D
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
U50
1
P
B
2
A
3
1
1
2
2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
12
R858
R858
R859
R859
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
JTAG1
@SHORT PADS~D
@SHORT PADS~D
CONN@JTAG1
CONN@
10K_0402_5%~D
10K_0402_5%~D
12
R861
R861
R860
R860
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
R853 0_0402_5%~DR8 53 0_0402_5%~D
R855 0_0402_5%~DR8 55 0_0402_5%~D
1.05V_0.8V_PWROK
C736 0.1U_0402_25V6K~ DC736 0.1U_0402_25V6K~D
12
DOCK_POR_RST#<39>
EC_32KHZ_ECE5048<40>
+3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
12
R847
R847
R848
R848
1 2
1 2
1.05V_0.8V_PWROK <14,60>
SML1_SMBDATA<15>
SML1_SMBCLK<15>
CLK_TP_SIO<42>
DAT_TP_SIO<42>
CLK_KBD<39 >
DAT_KBD<39>
CLK_MSE<39>
DAT_MSE<39>
PBAT_SMBDAT<53>
PBAT_SMBCLK<53>
DOCK_POR_RST#
PCH_ALW_ON<43>
BIA_PWM_EC<24>
BC_CLK_ECE5048<40>
BC_DAT_ECE5048<40>
BC_INT#_ECE5048<40>
BC_CLK_EMC4022<22>
BC_DAT_EMC4022<22>
BC_INT#_EMC4022<22>
PCH_PCIE_WAKE#<16>
PCIE_WAKE#<29,35,36>
BC_CLK_ECE1117<42>
BC_DAT_ECE1117<42>
BC_INT#_ECE1117<42>
BEEP<30>
SIO_SLP_S5#<16>
ACAV_IN_NB< 40,62,63>
SIO_EXT_SMI#<14,17>
SIO_RCIN#<18>
IRQ_SERIRQ<14,33,40>
PCH_PLTRST#_EC<17,33,35,36,40>
CLK_PCI_MEC<17>
LPC_LFRAME#<14,33,35,40>
LPC_LAD0< 14,33,35,40>
LPC_LAD1< 14,33,35,40>
LPC_LAD2< 14,33,35,40>
LPC_LAD3< 14,33,35,40>
CLKRUN#<16,33,4 0>
SIO_EXT_SCI#<18>
MEC_XTAL2 MEC_XTAL2_R
R1068 0_0402_5%~DR1068 0_0402_5%~D
1 2
R867 0_0402_5%~DR867 0_0402_ 5%~D
100K_0402_5%~D
@R850
100K_0402_5%~D
@
12
R849
R849
R850
HOST_DEBUG_TXHOST_DEB_TX
HOST_DEBUG_RX
R875 C744
240K 4700p
*
130K 4700p
4700p
62K
4700p
33K
4700p
8.2K
4700p
4.3K
700p
2K
4
4700p
1K
BOARD_ID rise time is measured from 5%~68%.
5
12
REV
X00
X01
X02
A00
4
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
PCH_ALW_ON
BIA_PWM_EC
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
BC_CLK_EMC4022
BC_DAT_EMC4022
BC_INT#_EMC4022
PCH_PCIE_WAKE#
PCIE_WAKE#
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
BEEP
SIO_SLP_S5#
ACAV_IN_NB
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC_XTAL1
BOARD_ID
4
+RTC_CELL
R815
R815
0_0402_5%~D
0_0402_5%~D
+RTC_CELL_VBAT
1 2
U51
U51
PS/2 INTERFACE
PS/2 INTERFACE
A5
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
A37
GPIO110/PS2_CLK2/GPTP-IN6
B40
GPIO111/PS2_DAT2/GPTP-OUT6
A38
GPIO112/PS2_CLK1A
B41
GPIO113/PS2_DAT1A
A39
GPIO114/PS2_CLK0A
B42
GPIO115/PS2_DAT0A
B59
GPIO154/I2C1C_DATA/PS2_CLK1B
A56
GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
JTAG INTERFACE
A51
GPIO145/I2C1K_DATA/JTAG_TDI
B55
GPIO146/I2C1K_CLK/JTAG_TDO
B56
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
A53
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
B57
JTAG_RST#
FAN PWM & TACH
FAN PWM & TACH
B22
GPIO050/FAN_TACH1
A21
GPIO051/FAN_TACH2
B23
GPIO052/FAN_TACH3
B24
GPIO053/PWM0
A23
GPIO054/PWM1
B25
GPIO055/PWM2
A24
GPIO056/PWM3
BC-LINK
BC-LINK
A43
GPIO123/BCM_A_CLK
B45
GPIO122/BCM_A_DAT
A42
GPIO121/BCM_A_INT#
A12
GPIO022/BCM_B_CLK
B13
GPIO023/BCM_B_DAT
A13
GPIO024/BCM_B_INT#
B20
GPIO044/BCM_C_CLK
A18
GPIO043/BCM_C_DAT
B19
GPIO042/BCM_C_INT#
A20
GPIO047/LSBCM_D_CLK
B21
GPIO046/LSBCM_D_DAT
A19
GPIO045/LSBCM_D_INT#
A16
GPIO032/GPTP-IN3/BCM_E_CLK
B16
GPIO31/GPTP-OUT2/BCM_E_DAT
A15
GPIO30/GPTP-IN2/BCM_E_INT#
HOST INTERFACE
HOST INTERFACE
A6
GPIO011/nSMI
A27
GPIO061/LPCPD#
B29
LDRQ#
A28
SER_IRQ
B30
LRESET#
A29
PCI_CLK
B31
LFRAME#
A30
LAD0
B32
LAD1
A31
LAD2
B33
LAD3
A32
CLKRUN#
A33
GPIO100/nEC_SCI
MASTER CLOCK
MASTER CLOCK
A61
XTAL1
A62
XTAL2
B62
GPIO160/32KHZ_OUT
B34
NC1
A64
NC2
B68
NC3
15mil
C740 close to U51.B12
+3.3V_ALW
12
R875
R875
240K_0402_5%~D
240K_0402_5%~D
1
C744
C744
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
SYSTEM_ID
C723
C723
AGND
B66
A11
B64
VBAT
VTR[1]
DB Version 0.12
DB Version 0.12
VSS[1]
VSS[4]
B11
B60
+3.3V_ALW
+3.3V_ALW_U51
1
A22
least
15mil
12
1
2
2
B35
A41
A58
A52
A26
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]B3VTR[8]
MISC INTERFACE
MISC INTERFACE
GPIO124/GPTP-OUT5/UART_RX
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GPIO014/GPTP-IN7/HSPI_CS1
GPIO040/GPTP-OUT3/HSPI_CS2
SMBUS INTERFACE
SMBUS INTERFACE
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
DELL PWR SW INF
DELL PWR SW INF
VR_CAP
VSS_RO
B12
B54
+VR_CAP
1
C740
C740
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
R871
R871
1K_0402_1%~D
1K_0402_1%~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C742
C742
CHIPSET_ID for BID
function
3
PJP8
PJP8
PAD-OPEN1x1m
PAD-OPEN1x1m
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C727
C727
C732
C732
2
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/HSPI_SCLK
GPIO104/HSPI_MISO
GPIO106/HSPI_MOSI
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
PROCHOT#/PWM4
GPIO001/ECSPI_CS1
GPIO002/ECSPI_CS2
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO026/GPTP-IN1
GPIO027/GPTP-OUT1
GPIO041
GPIO107/nRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
PECI
PECI
PECI_VREF
PECI
I2S
I2S
I2S_DAT
I2S_CLK
I2S_WS
EP
MEC5055-LZY_DQFN132_11X11~D
MEC5055-LZY_DQFN132_11X11~D
C1
RESET_OUT#
2
G
G
3
12
A10
B10
B14
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
A55
A57
B61
B65
A46
B2
A2
B8
B18
A8
B9
A9
A14
B15
A17
B39
A44
B47
A54
B58
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
A59
B63
A60
A63
B67
B1
A1
B51
A48
B17
B27
B28
+3.3V_M
12
R893
R893
100K_0402_5%~D
100K_0402_5%~D
13
D
D
Q50
Q50
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
1
C731
C731
C729
C729
2
2
2
SYSTEM_ID
BOARD_ID
DDR_ON
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR
DDR_HVREF_RST_GATE
DYN_TUR_CURRNT_SET#
CPU1.5V_S3_GATE
MSDATA
MSCLK
SIO_A20GATE
PS_ID
FWP#
PROCHOT#_EC
R884 1K_0402_1%~DR884 1K_0402 _1%~D
R886 1K_0402_1%~DR886 1K_0402 _1%~D
R887 1K_0402_1%~DR887 1K_0402 _1%~D
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
PM_APWROK
1.05V_A_PWRGD
ALW_PW RGD_3V_5V
DEVICE_DET#
RESET_OUT#
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
USH_SMBDAT
USH_SMBCLK
LAT_ON_SW#
ALWON
VCI_IN1#
POWER_SW _IN#
ACAV_IN
DOCK_PWR_SW #
+PECI_VREF
PECI_EC_R
R863 43_0402_5%~DR863 43_0402_5%~D
PCH_PWRGD# <22>
2
+3.3V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C726
C726
2
1 2
1 2
1 2
1 2
FWP#
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
1
C725
C725
C728
C728
C739
C739
C730
C730
2
2
2
DDR_ON <55>
HOST_DEBUG_TX < 35>
HOST_DEBUG_RX <35>
RUNPWROK <7,40>
EN_INVPWR <24 >
PCH_SATA_MOD_EN# < 14>
DDR_HVREF_RST_GATE <7>
DYN_TUR_CURRNT_SET# <62>
CPU1.5V_S3_GATE <11>
MSDATA <35>
MSCLK <35>
SIO_A20GATE <1 8>
PS_ID <53>
VOL_MUTE
VOL_MUTE <31>
VOL_UP
VOL_UP <31>
VOL_DOWN
PECI_EC <7>
VCI_IN1#
VOL_DOWN <31>
Bat2 = Amber L ED
B
at1 = Blue LED
20mA drive pin s
R863 close to
U51& least 250mils
1 2
R862 0_0402_5%~DR862 0_0402_5%~D
1
C737
C737
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
R1156 100K_0402_5%~DR1156 100K_0402_5%~D
1 2
R869 10K_0402_5%~DR869 10K_0402_5%~D
1 2
R876 100K_0402_5%~DR876 100K_0402_5%~D
1 2
R880 100K_0402_5%~DR880 100K_0402_5%~D
1 2
R881 100K_0402_5%~DR881 100K_0402_5%~D
1 2
R882 100K_0402_5%~DR882 100K_0402_5%~D
1.05V_0.8V_PWROK
1 2
R883 10K_0402_5%~DR883 10K_0402_5%~D
RESET_OUT#
1 2
R843 8.2K_0402_5%~D@ R843 8.2K_0402_5%~D@
CPU1.5V_S3_GATE
1 2
R889 100K_0402_5%~DR889 100K_0402_5%~D
PCH_RSMRST#
1 2
R892 10K_0402_5%~DR892 10K_0402_5%~D
2
+1.05V_RUN_VTT
+RTC_CELL
12
MSDATA
DDR_ON
PCH_ALW_ON
DOCK_POR_RST#
EN_INVPWR
ME_SUS_PWR_ACK < 16>
1.5V_SUS_PWRGD <55>
PM_APWROK <16>
1.05V_A_PWRGD < 57>
ALW_PW RGD_3V_5V <54>
DEVICE_DET# <29>
RESET_OUT# < 16>
PCH_RSMRST# <42>
AC_PRESENT <16>
SIO_PWRBTN# <16>
DOCK_SMB_DAT <39>
DOCK_SMB_CLK <39>
BAY_SMBDAT <29,53>
BAY_SMBCLK <29,53>
GPU_SMBDAT < 45>
GPU_SMBCLK <45>
CHARGER_SMBDAT <62>
CHARGER_SMBCLK <62>
CARD_SMBDAT <36>
CARD_SMBCLK <36>
USH_SMBDAT <33>
USH_SMBCLK <33>
ALWON <54>
ACAV_IN <22,62,63>
GPIO024/THSEL_STRAP note
i.THSEL_STRAP =1 (selects thermistor on diode channel 1)
ii.THSEL_STRAP = 0 (selects remote diode on diode channel 1)
+3.3V_ALW
12
R872
R872
10K_0402_5%~D
10K_0402_5%~D
R879
@R879
@
10K_0402_5%~D
10K_0402_5%~D
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
POWER_SW _IN#< 22>
DOCK_PWR_SW #<22>
+1.05V_RUN_VTT
1 2
R1179 10K_040 2_5%~D@ R1179 10K_0 402_5%~D@
PROCHOT#_EC
1 2
R812 100K_0402_5%~D@R812 100K_0402_5%~D@
1
+RTC_CELL
POWER_SW _IN#
DOCK_PWR_SW #
LAT_ON_SW#
DYN_TUR_CURRNT_SET#
12
1
2
+RTC_CELL
12
R825 10K_0402_5%~DR825 10K_0402_5%~D
1
2
+RTC_CELL
12
13
D
D
2
G
G
S
S
R1180 0_0402_5%~DR1180 0_0402_5%~D
RUNPWROK
RUN_ON_ENABLE#<43>
AC_PRESENT
LCD_SMBCLK
LCD_SMBDAT
DOCK_SMB_DAT
DOCK_SMB_CLK
BAY_SMBDAT
BAY_SMBCLK
DEVICE_DET#
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
VOL_MUTE
VOL_DOWN
VOL_UP
GPU_SMBDAT
GPU_SMBCLK
R810
R810
100K_0402_5%~D
100K_0402_5%~D
R811 10K_0402_5%~DR811 10K _0402_5%~D
C722
C722
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
R819
R819
100K_0402_5%~D
100K_0402_5%~D
1 2
C734
C734
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
R870
R870
100K_0402_5%~D
100K_0402_5%~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
1 2
R1169 100K_0402_5%~DR1169 100K_0402_5%~D
R1197 100K_0402_5%~DR1197 100K_0402_5%~D
R1118 100K_0402_5%~DR1118 100K_0402_5%~D
R829 4.7K_0402_5%~DR8 29 4.7K_0402_5%~D
R822 4.7K_0402_5%~DR8 22 4.7K_0402_5%~D
C721
@C721
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
1 2
C733
@C733
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
Q47
@
Q47
@
+3.3V_RUN
12
R799
R799
10K_0402_5%~D
10K_0402_5%~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
2
G
G
S
S
12
R835 10K_0402_5%~DR835 10K_0402_5%~D
12
R418 2.2K_0402_5%~DR418 2.2K_0402_5%~ D
12
R420 2.2K_0402_5%~DR420 2.2K_0402_5%~ D
12
R838 2.2K_0402_5%~DR838 2.2K_0402_5%~ D
12
R841 2.2K_0402_5%~DR841 2.2K_0402_5%~ D
12
R854 2.2K_0402_5%~DR854 2.2K_0402_5%~ D
12
R856 2.2K_0402_5%~DR856 2.2K_0402_5%~ D
12
R1171 100K_04 02_5%~DR1171 100K_0402_5%~D
12
R1125 100K_04 02_5%~DR1125 100K_0402_5%~D
12
R845 4.7K_0402_5%~DR8 45 4.7K_0402_5%~D
12
R846 4.7K_0402_5%~DR8 46 4.7K_0402_5%~D
12
R851 4.7K_0402_5%~DR8 51 4.7K_0402_5%~D
12
R852 4.7K_0402_5%~DR8 52 4.7K_0402_5%~D
12
12
12
12
12
POWER_SW #_MB <31,42>
DOCK_PWR_BTN# < 39>
Q45
Q45
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MEC5055
MEC5055
MEC5055
ze Doc ument Number Rev
LA-7782
LA-7782
LA-7782
1
H_PROCHOT# <7,60,62>
+3.3V_ALW_PCH
+3.3V_ALW
+5V_RUN
+3.3V_RUN
41 66Friday, June 10, 2011
41 66Friday, June 10, 2011
41 66Friday, June 10, 2011
0.1
0.1
0.1
Page 42
5
+3.3V_TP
1
C755
C755
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
D D
TP_CLK
TP_DATA
2
3
D37
PESD5V0U2BT_SOT23-3~D
D37
PESD5V0U2BT_SOT23-3~D
1
Place close to JTP1
C C
RSMRST circuit
+3.3V_ALW
+5V_ALW
1
2
U4
U4
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
VCC
RESET#
2
C289
C289
GND
RT9818A-46GU3_SC70-3~D
RT9818A-46GU3_SC70-3~D
3
R1622
R1622
RSMRST#
1 2
10K_0402_5%~D
10K_0402_5%~D
PCH_RSMRST#<41>
EC SIDE
PCH_RSMRST#
DAT_TP_SIO<41>
CLK_TP_SIO<41>
4
R1623
@R1623
@
0_0402_5%~D
0_0402_5%~D
1 2
+3.3V_TP
4.7K_0402_5%~D
4.7K_0402_5%~D
12
R903
R903
10P_0402_50V8J~D
10P_0402_50V8J~D
C752
C752
1
2
PCH_RSMRST#_Q
4.7K_0402_5%~D
4.7K_0402_5%~D
12
Touch Pad
R902
R902
L54 BLM18AG601SN1D_0603~DL54 BLM18AG601SN1D_0603~D
L55 BLM18AG601SN1D_0603~DL55 BLM18AG601SN1D_0603~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1
C751
C751
2
+3.3V_ALW
5
1
B
2
A
3
12
12
1 2
C288 0.1U_0402_25V6K~DC288 0.1U_0402_25V6K~D
U7
U7
P
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
10P_0402_50V8J~D
10P_0402_50V8J~D
1
C750
C750
2
PCH_RSMRST#_Q <14,16>
Pin reverse for PT
Touch Pad Conn. Pitch=0.5mm
TP_DATA
TP_CLK
10P_0402_50V8J~D
10P_0402_50V8J~D
1
C749
C749
+3.3V_TP
2
TP_CLK
TP_DATA
PS2_DAT_TS
PS2_CLK_TS
+3.3V_ALW +3.3V_RUN +3.3V_TP
1 2
R1161 0_0603_5%~DR1161 0_0603_5%~D
1 2
R1162 0_0603_5%~D@R1162 0_0603_5%~D@
JTP1
JTP1
1
1
2
2
3
3
4
4
5
5
6
6
G1
7
7
G2
8
8
TYCO_2041070-8
TYCO_2041070-8
CONN@
CONN@
2
BlueTooth
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
9
10
BT_DET#<17>
COEX1_BT_ACTIVE<35>
BT_COEX_STATUS2<33>
BT_PRI_STATUS<33>
BT_ACTIVE<44>
BT_RADIO_DIS#<40>
COEX2_WLAN_ACTIVE<35>
USBP11-<17>
USBP11+<17>
+3.3V_RUN
BT_COEX_STATUS2
BT_PRI_STATUS
10K_0402_5%~D
10K_0402_5%~D
33P_0402_50V8J~D
33P_0402_50V8J~D
12
R904
R904
C753
C753
1
2
1 2
R1133 1K_0402_1%~DR1133 1K_0402_1%~D
1 2
R1134 1K_0402_1%~DR1134 1K_0402_1%~D
+3.3V_RUN
C748
C748
100P_0402_50V8J~D
100P_0402_50V8J~D
@C754
@
C754
1
2
BT_COEX_STATUS2
BT_PRI_STATUS
1
CONN@
CONN@
JBT1
JBT1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
G1
14
G2
E&T_3703-E12N-03R
E&T_3703-E12N-03R
Power Switch for debug
POWER_SW#_MB<31,41>
100P_0402_50V8J~D
100P_0402_50V8J~D
C759
@C759
@
1
2
@SHORT PADS~D
@SHORT PADS~D
112
PWRSW1
@PWRSW1
@
2
Place on Bottom
LVDS cable@
LVDS cable@
Part Number Description
Part Number Description
DC020003Y0L
B B
+3.3V_ALW
1
2
C756
C756
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+5V_RUN
1
2
C758
C758
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
Place close to JKB1
A A
Change KB connector to same as JSC1
KB Conn. Pitch=1.0mm
JKB1
KB_DET#<18>
+3.3V_ALW
+5V_RUN
BC_INT#_ECE1117<41>
BC_DAT_ECE1117<41>
BC_CLK_ECE1117<41>
KB_DET#
PS2_CLK_TS
PS2_DAT_TS
JKB1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
FCI_10089709-010010LF~D
FCI_10089709-010010LF~D
CONN@
CONN@
DC020003Y0L
RTC BATT@
RTC BATT@
Part Number Description
Part Number Description
GC20323MX00
GC20323MX00
FAN@
FAN@
Part Number Description
Part Number Description
DC28A000800
DC28A000800
Speak@
Speak@
Part Number Description
Part Number Description
PK230003Q0L
PK230003Q0L
H-CONN SET ZJX MB-LCD
H-CONN SET ZJX MB-LCD
14 WXGA+(-1ch)
14 WXGA+(-1ch)
BATT CR2032 3V
BATT CR2032 3V
220MAH MAXELL
220MAH MAXELL
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
SPK PACK ZJX 2.0W 4 OHM FG
SPK PACK ZJX 2.0W 4 OHM FG
@LED Board FFC
@LED Board FFC
Part Number
Part Number
NBX0000RP0L
NBX0000RP0L
@MEDIA Board FFC
@MEDIA Board FFC
Part Number
Part Number
NBX0000RS0L FFC 12P G P.5 PAD.3 75MM MB-VOLUME/B 0FD
NBX0000RS0L FFC 12P G P.5 PAD.3 75MM MB-VOLUME/B 0FD
LVDS cable@
LVDS cable@
Part Number Description
Part Number Description
DC02C00180L H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL
DC02C00180L H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL
UMA DC_IN wire cable@
UMA DC_IN wire cable@
Part Number Description
Part Number Description
DC30100BN0
DC30100BN0
Battery bridge cable@
Battery bridge cable@
Part Number Description
Part Number Description
DC020014Z10
DC020014Z10
Description
Description
FFC 6P H P1 PAD=0.7 87.4MM MB-LED/B 0FD
FFC 6P H P1 PAD=0.7 87.4MM MB-LED/B 0FD
Description
Description
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
H-CONN SET 0FD M/B-BATTERY 9PIN
H-CONN SET 0FD M/B-BATTERY 9PIN
MDC wire set cable@
MDC wire set cable@
Part Number Description
Part Number Description
DC30100BL0L CONN SET 0FD
DC30100BL0L CONN SET 0FD
Part Number Description
Part Number Description
@KB FFC
@KB FFC
Part Number Description
Part Number Description
@BT wire cable
@BT wire cable
Part Number Description
Part Number Description
T/P FFC@
T/P FFC@
NBX0000RR0L
NBX0000RR0L
SP070007V0L
SP070007V0L
DC020014Y0L
DC020014Y0L
MDC-RJ11
MDC-RJ11
FFC 8P F P0.5
FFC 8P F P0.5
PAD=0.3 136MM
PAD=0.3 136MM
MB-TP/B 0FD
MB-TP/B 0FD
S SOCKET TYCO 1770551-1
S SOCKET TYCO 1770551-1
10P H5.9 SMART
10P H5.9 SMART
H-CONN SET 0FD MB-BT
H-CONN SET 0FD MB-BT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
TP/KB/BT/FAN/RESET
TP/KB/BT/FAN/RESET
TP/KB/BT/FAN/RESET
LA-7782
LA-7782
LA-7782
42 66Friday, June 10, 2011
42 66Friday, June 10, 2011
42 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 43
5
+3.3V_ALW_PCH Source
+3.3V_ALW2
12
R907
R907
100K_0402_5%~D
100K_0402_5%~D
ALW_ON_3.3V#
61
ALW_ENABLE<20>
D D
Q51A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PCH_ALW_ON<41>
Q51A
2
+3.3V_SUS Source
+3.3V_ALW2
12
R915
R915
100K_0402_5%~D
100K_0402_5%~D
Q53A
Q53A
2
SUS_ON_3.3V#
61
C C
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
SUS_ON<40>
+PWR_SRC_S
12
3
5
4
+PWR_SRC_S
12
3
5
4
R905
R905
100K_0402_5%~D
100K_0402_5%~D
ALW_ENABLE
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q51B
Q51B
R911
R911
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q53B
Q53B
+3.3V_M Source
+3.3V_ALW2
12
61
Q57A
B B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
SIO_SLP_A#<16,40,57>
SIO_SLP_A#
Q57A
2
+PWR_SRC_S
R918
R918
100K_0402_5%~D
100K_0402_5%~D
A_ON_3.3V#
5
12
R917
R917
100K_0402_5%~D
100K_0402_5%~D
A_ENABLE
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q57B
Q57B
4
4
+3.3V_ALW +3.3V_ALW_PCH
1M_0402_5%~D
1M_0402_5%~D
12
R1619
R1619
+3.3V_ALW
SUS_ENABLE
1M_0402_5%~D
1M_0402_5%~D
12
R1618
R1618
+3.3V_ALW
1M_0402_5%~D
1M_0402_5%~D
12
R1617
R1617
Q49
Q49
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
2
1
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
2
1
3
1
C762
C762
3300P_0402_50V7K~D
3300P_0402_50V7K~D
2
Q54
Q54
S
S
45
G
G
3
1
C767
C767
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
Q58
Q58
S
S
45
G
G
3
1
C770
C770
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
1
2
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C760
C760
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
12
+3.3V_SUS
C765
C765
+3.3V_M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C768
C768
12
12
R908
R908
20K_0402_5%~D
20K_0402_5%~D
R914
R914
20K_0402_5%~D
20K_0402_5%~D
R919
@R919
@
20K_0402_5%~D
20K_0402_5%~D
DC/DC Interface
A_ON_3.3V#
3
2
1
+1.5V_RUN Source
Q59
Q59
NTGS4141NT1G_TSOP6~D
NTGS4141NT1G_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
1
C771
C771
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
+1.5V_RUN
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
C769
C769
12
20K_0402_5%~D
20K_0402_5%~D
R921
R921
R920
R920
+1.5V_MEM
470K_0402_5%~D
470K_0402_5%~D
12
R1610
R1610
+3.3V_ALW2
12
R909
R909
100K_0402_5%~D
100K_0402_5%~D
2
RUN_ON_ENABLE#
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q52A
Q52A
RUN_ON_ENABLE#<41>
SIO_SLP_S3#<11,16,28,36,40,56>
RUN_ON<28,36,40,56,64>
1 2
R735 0_0402_5%~DR735 0_0402_5%~D
1 2
R744 0_0402_5%~D@ R744 0_0402_5%~D@
+PWR_SRC_S
12
1.5V_RUN_ENABLE
3
5
4
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q52B
Q52B
+1.05V_RUN Source
2
G
G
+3.3V_M
12
R916
R916
39_0603_5%~D
39_0603_5%~D
+3.3V_M_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
Q60
Q60
S
S
+5V_ALW
C1199
C1199
1U_0603_10V7K~D
1U_0603_10V7K~D
12
SIO_SLP_S3#<11,16,28,36,40,56>
RUN_ON<28,36,40,56,64>
PJP6
PJP6
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
+3.3V_ALW
+3.3V_ALW_U78
1 2
R749 0_0402_5%~DR749 0_0402_5%~D
1 2
R747 0_0402_5%~D@ R747 0_0402_5%~D@
+5V_ALW_U78
C1198
C1198
1U_0603_10V7K~D
1U_0603_10V7K~D
+PWR_SRC_S
2
G
G
12
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP5
PJP5
1
2
3
4
5
6
7
1
2
12
1.05V_RUN_ENABLE
13
D
D
S
S
U78
U78
VIN1
VIN1
ON1
VBIAS
ON2
VIN2
VIN2
SLG59M232VTR
SLG59M232VTR
R930
R930
100K_0402_5%~D
100K_0402_5%~D
Q64
Q64
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
14
VOUT1
13
VOUT1
12
CT1
11
GND
10
CT2
9
VOUT2
8
VOUT2
15
GPAD
+1.05V_M
Q63
Q63
SI4164DY-T1-GE3_SO8~D
SI4164DY-T1-GE3_SO8~D
8
7
5
470K_0402_5%~D
470K_0402_5%~D
12
R1611
R1611
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
1 2
@C1197
@
1 2
C1196
C1196
C1197
+1.05V_RUN
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
36
4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
C773
C773
2
12
C772
C772
1
R931
R931
20K_0402_5%~D
20K_0402_5%~D
2
+3.3V_RUN Source
+3.3V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
C764
C764
1
2
R913
R913
20K_0402_5%~D
20K_0402_5%~D
+5V_RUN Source
+5V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
C761
C761
1
2
R910
R910
20K_0402_5%~D
20K_0402_5%~D
+3.3V_SUS +1.5V_RUN +3.3V_RUN+5V_RUN+3.3V_ALW_PCH
12
R922
@R922
@
1K_0402_1%~D
1K_0402_1%~D
+3.3V_SUS_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q65
SUS_ON_3.3V#
A A
Q65
2
G
G
ALW_ON_3.3V#
S
S
12
R928
@R928
@
1K_0402_1%~D
1K_0402_1%~D
+3.3V_ALWPCH_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
RUN_ON_ENABLE#
Q66
Q66
2
G
G
S
S
12
@R923
@
1K_0402_1%~D
1K_0402_1%~D
+5V_RUN_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
2
G
G
S
S
R923
@
@
Q67
Q67
12
R924
@R924
@
1K_0402_1%~D
1K_0402_1%~D
+1.5V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q68
2
Q68
G
G
S
S
2
G
G
12
R929
@R929
@
39_0603_5%~D
39_0603_5%~D
+3.3V_RUN_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
@
@
Q69
Q69
S
S
+1.05V_RUN +0.75V_DDR_VTT+1.5V_CPU_VDDQ
2
G
G
12
R925
@R925
@
39_0402_5%~D
39_0402_5%~D
+1.05V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q70
Q70
S
S
RUN_ON_CPU1.5VS3#<7,11>
2
G
G
12
R926
R926
220_0402_5%~D
220_0402_5%~D
+1.5V_CPU_VDDQ_CHG
13
D
D
S
S
12
R927
R927
22_0603_5%~D
22_0603_5%~D
+DDR_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Q71
Q71
SSM3K7002FU_SC70-3~D
13
D
D
Q72
Q72
2
G
G
S
S
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Discharg Circuit
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
POWER CONTROL
POWER CONTROL
POWER CONTROL
LA-7782
LA-7782
LA-7782
43 66Friday, June 10, 2011
43 66Friday, June 10, 2011
43 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 44
5
4
3
2
1
+3.3V_ALW
12
R932
R932
10K_0402_5%~D
Q74B
D D
LED_SATA_DIAG_OUT#<40>
C C
WIRELESS_LED#<35,40>
BT_ACTIVE<42>
SATA_ACT#<14>
MASK_SATA_LED#<40>
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q74B
4
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q78B
Q78B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
12
R950
R950
100K_0402_5%~D
100K_0402_5%~D
D59
D59
3
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
D62
D62
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
Q80B
Q80B
4
5
10K_0402_5%~D
Q74A
Q74A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
21
2
MASK_BASE_LEDS#
21
Q80A
Q80A
DMN66D0LDW-7_SOT363-6~D
3
DMN66D0LDW-7_SOT363-6~D
SYS_LED_MASK#
+3.3V_ALW
12
R937
R937
100K_0402_5%~D
100K_0402_5%~D
Q78A
Q78A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
MASK_BASE_LEDS#
2
2
HDD LED solution for White LED
+5V_ALW
61
2
61
2
Q75
Q75
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1 3
1 2
R934 4.7K_0402_5%~DR934 4.7K_0402_5%~D
PANEL_HDD_LED
Q81
Q81
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1 3
1 2
R938 4.7K_0402_5%~DR938 4.7K_0402_5%~D
WLAN LED solution for White LED
+5V_ALW
61
2
Q79
Q79
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1 3
1 2
R939 4.7K_0402_5%~DR939 4.7K_0402_5%~D
SATA_LED <31>
PANEL_HDD_LED <24>
WLAN_LED <31>
Q83B
Q83B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
BAT2_LED#<40>
BAT1_LED#<40>
BREATH_LED#<39,40>
4
5
MASK_BASE_LEDS#
Q83A
Q83A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
2
MASK_BASE_LEDS#
Q84B
Q84B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
Q84A
Q84A
2
MASK_BASE_LEDS#
BAT2_LED#_Q
BAT1_LED#_Q
3
61
R949
R949
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
R958
R958
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
R951
R951
475_0402_1%~D
475_0402_1%~D
1 2
R953
R953
475_0402_1%~D
475_0402_1%~D
1 2
LTW-193ZDS5_WHITE~D
LTW-193ZDS5_WHITE~D
LED1
LED1
BREATH_WHITE_LED_SNIFFBREATH_LED#_Q
21
Place LED1 close to SW1
Battery LED
BATT_WHITE <31>
BATT_YELLOW <31>
BATT_WHITE_LED <24>
BATT_YELLOW_LED <24>
1 2
R957 1K_0402_1%~DR957 1K_0402_1%~D
1 2
R955
R955
4.7K_0402_5%~D
4.7K_0402_5%~D
Breath LED
+5V_ALW
BREATH_WHITE_LED <24>
B B
+3.3V_ALW
C778 0.1U_0402_25V6K~DC778 0.1U_0402_25V6K~D
1 2
5
U58
Fiducial Mark
FD1
@FD1
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
A A
FD2
@FD2
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD3
@FD3
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD4
@FD4
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
H1
@H1
@
H_3P3
H_3P3
H2
@H2
@
H_3P3
H_3P3
1
H4
@H4
@
H3
@H3
@
H_3P3
H_3P3
H_3P0
H_3P0
1
1
1
5
LED Circuit Control Table
H6
@H6
@
H7
@H7
@
H5
@H5
@
H_3P0
H_3P0
H_3P0
H_3P0
H_3P0
H_3P0
1
1
1
SYS_LED_MASK# LID_CL#
0
1 0
H12
@H12
@H8
@
H_3P2
H_3P2
H8
@H10
@1H9
@H9
@
H_3P3
H_3P3
H_3P0
H_3P0
1
1
@
@H13
H_3P0
H_3P0
@
H_3P0
H_3P0
1
4
H10
X
11
H16
@H16
H13
@H14
@
H_3P0
H_3P0
1
@
H15
@H15
@
H14
H_3P0
H_3P0
H_3P0
H_3P0
1
1
H19
@H19
@
H17
@H17
@
H_2P3
H_2P3
1
1
H_3P0x2P0
H_3P0x2P0
1
H20
@H20
@
H_2P0N
H_2P0N
1
SYS_LED_MASK#<40>
@H22
@
H_3P0
H_3P0
3
H22
1
SYS_LED_MASK#
LID_CL#
LID_CL#<31,40>
H23
@H23
@
H_2P3
H_2P3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
B
2
A
U58
P
MASK_BASE_LEDS#
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
2
EMI CLIP
CLIP1
CLIP1
EMI_CLIP
EMI_CLIP
GND
CLIP2
CLIP2
EMI_CLIP
EMI_CLIP
GND
1
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAD and Standoff
PAD and Standoff
PAD and Standoff
LA-7782
LA-7782
LA-7782
1
44 66Friday, June 10, 2011
44 66Friday, June 10, 2011
44 66Friday, June 10, 2011
0.1
0.1
0.1
Page 45
5
PEG_CTX_GRX_P[0..15]<6>
PEG_CTX_GRX_N[0..15]<6>
PEG_CRX_GTX_P[0..15]<6>
PEG_CRX_GTX_N[0..15]<6>
D D
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
PEG_CRX_GTX_P6
PEG_CRX_GTX_N6
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
PEG_CRX_GTX_P8
PEG_CRX_GTX_N8
PEG_CRX_GTX_P9
PEG_CRX_GTX_N9
C C
PEG_CRX_GTX_P10
PEG_CRX_GTX_N10
PEG_CRX_GTX_P11
PEG_CRX_GTX_N11
PEG_CRX_GTX_P12
PEG_CRX_GTX_N12
PEG_CRX_GTX_P13
PEG_CRX_GTX_N13
PEG_CRX_GTX_P14
PEG_CRX_GTX_N14
PEG_CRX_GTX_P15
PEG_CRX_GTX_N15
B B
CV1 0.22U_0402_16V7K~DCV1 0.22U_0402_16V7K~D
CV2 0.22U_0402_16V7K~DCV2 0.22U_0402_16V7K~D
CV4 0.22U_0402_16V7K~DCV4 0.22U_0402_16V7K~D
CV3 0.22U_0402_16V7K~DCV3 0.22U_0402_16V7K~D
CV5 0.22U_0402_16V7K~DCV5 0.22U_0402_16V7K~D
CV6 0.22U_0402_16V7K~DCV6 0.22U_0402_16V7K~D
CV7 0.22U_0402_16V7K~DCV7 0.22U_0402_16V7K~D
CV8 0.22U_0402_16V7K~DCV8 0.22U_0402_16V7K~D
CV9 0.22U_0402_16V7K~DCV9 0.22U_0402_16V7K~D
CV10 0.22U_0402_16V7K~DCV10 0.22U_0402_16V7K~D
CV11 0.22U_0402_16V7K~DCV11 0.22U_0402_16V7K~D
CV12 0.22U_0402_16V7K~DCV12 0.22U_0402_16V7K~D
CV14 0.22U_0402_16V7K~DCV14 0.22U_0402_16V7K~D
CV15 0.22U_0402_16V7K~DCV15 0.22U_0402_16V7K~D
CV16 0.22U_0402_16V7K~DCV16 0.22U_0402_16V7K~D
CV17 0.22U_0402_16V7K~DCV17 0.22U_0402_16V7K~D
CV18 0.22U_0402_16V7K~DCV18 0.22U_0402_16V7K~D
CV19 0.22U_0402_16V7K~DCV19 0.22U_0402_16V7K~D
CV20 0.22U_0402_16V7K~DCV20 0.22U_0402_16V7K~D
CV21 0.22U_0402_16V7K~DCV21 0.22U_0402_16V7K~D
CV22 0.22U_0402_16V7K~DCV22 0.22U_0402_16V7K~D
CV23 0.22U_0402_16V7K~DCV23 0.22U_0402_16V7K~D
CV24 0.22U_0402_16V7K~DCV24 0.22U_0402_16V7K~D
CV25 0.22U_0402_16V7K~DCV25 0.22U_0402_16V7K~D
CV26 0.22U_0402_16V7K~DCV26 0.22U_0402_16V7K~D
CV27 0.22U_0402_16V7K~DCV27 0.22U_0402_16V7K~D
CV28 0.22U_0402_16V7K~DCV28 0.22U_0402_16V7K~D
CV29 0.22U_0402_16V7K~DCV29 0.22U_0402_16V7K~D
CV30 0.22U_0402_16V7K~DCV30 0.22U_0402_16V7K~D
CV31 0.22U_0402_16V7K~DCV31 0.22U_0402_16V7K~D
CV32 0.22U_0402_16V7K~DCV32 0.22U_0402_16V7K~D
CV33 0.22U_0402_16V7K~DCV33 0.22U_0402_16V7K~D
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CRX_GTX_P[0..15]
PEG_CRX_GTX_N[0..15]
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N15
+3.3V_RUN_GFX
DGPU_PEX_RST DGPU_PEX_RST_R
1 2
don't connect to PCH
+3.3V_RUN+3.3V_RUN
RV33
RV33
100K_0402_5%~D
100K_0402_5%~D
DGPU_HOLD_RST#<18>
PLTRST_GPU#<17>
A A
12
5
1
P
B
2
A
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
5
O
UV14
UV14
1
2
4
+3.3V_RUN_GFX
CV87
CV87
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
12
RV29
RV29
2.2K_0402_5%~D
2.2K_0402_5%~D
DGPU_PEX_RST
4
CLK_PCIE_VGA<15>
CLK_PCIE_VGA#<15>
1 2
RV21 10K_0402_5%~DRV21 10K_0402_5%~D
RV13 200_0402_1%~D@RV13 200_0402_1%~D@
RV18
RV18
0_0402_5%~D
0_0402_5%~D
1 2
12
RV15 2.49K_0402_1%~DRV15 2.49K_0402_1%~D
4
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N15
CLK_REQ#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
UV1A
UV1A
AN12
PEX_RX0
AM12
PEX_RX0_N
AN14
PEX_RX1
AM14
PEX_RX1_N
AP14
PEX_RX2
AP15
PEX_RX2_N
AN15
PEX_RX3
AM15
PEX_RX3_N
AN17
PEX_RX4
AM17
PEX_RX4_N
AP17
PEX_RX5
AP18
PEX_RX5_N
AN18
PEX_RX6
AM18
PEX_RX6_N
AN20
PEX_RX7
AM20
PEX_RX7_N
AP20
PEX_RX8
AP21
PEX_RX8_N
AN21
PEX_RX9
AM21
PEX_RX9_N
AN23
PEX_RX10
AM23
PEX_RX10_N
AP23
PEX_RX11
AP24
PEX_RX11_N
AN24
PEX_RX12
AM24
PEX_RX12_N
AN26
PEX_RX13
AM26
PEX_RX13_N
AP26
PEX_RX14
AP27
PEX_RX14_N
AN27
PEX_RX15
AM27
PEX_RX15_N
AK14
PEX_TX0
AJ14
PEX_TX0_N
AH14
PEX_TX1
AG14
PEX_TX1_N
AK15
PEX_TX2
AJ15
PEX_TX2_N
AL16
PEX_TX3
AK16
PEX_TX3_N
AK17
PEX_TX4
AJ17
PEX_TX4_N
AH17
PEX_TX5
AG17
PEX_TX5_N
AK18
PEX_TX6
AJ18
PEX_TX6_N
AL19
PEX_TX7
AK19
PEX_TX7_N
AK20
PEX_TX8
AJ20
PEX_TX8_N
AH20
PEX_TX9
AG20
PEX_TX9_N
AK21
PEX_TX10
AJ21
PEX_TX10_N
AL22
PEX_TX11
AK22
PEX_TX11_N
AK23
PEX_TX12
AJ23
PEX_TX12_N
AH23
PEX_TX13
AG23
PEX_TX13_N
AK24
PEX_TX14
AJ24
PEX_TX14_N
AL25
PEX_TX15
AK25
PEX_TX15_N
AL13
PEX_REFCLK
AK13
PEX_REFCLK_N
AK12
PEX_CLKREQ_N
AJ26
PEX_TSTCLK_OUT
AK26
PEX_TSTCLK_OUT_N
AJ12
PEX_RST_N
AP29
PEX_TERMP
N13M_FCBGA908~D
N13M_FCBGA908~D
3
Part 1 of 7
Part 1 of 7
PCI EXPRESS
PCI EXPRESS
CLK_27M_IN
1
CV34
CV34
2
20P_0402_50V8J~D
20P_0402_50V8J~D
GPU_SMBCLK_R
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
PEX_WAKE_N
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACsI2C GPIO
DACsI2C GPIO
DACA_VDD
DACA_VREF
DACA_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
PLLVDD
SP_PLLVDD
VID_PLLVDD
XTAL_IN
XTAL_OUT
CLK
CLK
XTAL_SSIN
XTAL_OUTBUFF
27MHZ_12PF_X1E000021042600~D
27MHZ_12PF_X1E000021042600~D
1
2
RV30 0_0402_5%~DRV30 0_0402_5%~D
RV26 0_0402_5%~DRV26 0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
GPU_VID_5
P6
GPU_VID_4
M3
BIA_PWM_GPU
L6
ENVDD_GPU
P5
PANEL_BKEN_DGPU
P7
GPU_VID_2
L7
GPU_VID_3
M7
N8
THERMTRIP_VGA#
M1
GPU_GPIO9
M2
FBVREF_ALTV
L1
GPU_VID_1
M5
GPU_HOT#
N3
GPU_VID_6
M4
N4
DPC_GPU_HPD
P2
R8
DPD_GPU_HPD
M6
DPE_GPU_HPD
R1
P3
P4
P1
AJ11
GPU_CRT_RED
AK9
GPU_CRT_GRN
AL10
GPU_CRT_BLU
AL9
GPU_CRT_HSYNC
AM9
GPU_CRT_VSYNC
AN9
+DACA_VDD
AG10
DACA_VREF
AP9
DACA_RSET
AP8
GPU_CRT_CLK_DDC_R
R4
GPU_CRT_DAT_DDC_R
R5
I2CB_SCL
R7
I2CB_SDA
R6
LDDC_CLK_GPU
R2
LDDC_DATA_GPU
R3
GPU_SMBCLK_R
T4
GPU_SMBDAT_R
T3
AD8
AE8
AD7
CLK_27M_IN
H3
CLK_27M_OUT
H2
XTALSSIN
H1
XTALOUTBUFF
J4
YV1
YV1
3
IN
OUT
4
GND
GND
1 2
QV14B
@QV14B
@
3
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
QV14A
@QV14A
@
1 2
GPU_VID_5 <64>
GPU_VID_4 <64>
BIA_PWM_GPU <24>
ENVDD_GPU <24>
PANEL_BKEN_DGPU <24>
GPU_VID_2 <64>
GPU_VID_3 <64>
THERMTRIP_VGA# <22>
FBVREF_ALTV <51,52>
GPU_VID_1 <64>
GPU_HOT# <64>
GPU_VID_6 <64>
DPC_GPU_HPD <39>
DPD_GPU_HPD <39>
DPE_GPU_HPD <26>
GPU_CRT_RED <25>
GPU_CRT_GRN <25>
GPU_CRT_BLU <25>
GPU_CRT_HSYNC <25>
GPU_CRT_VSYNC <25>
CV13 0.01U_0402_16V7K~DCV13 0.01U_0402_16V7K~D
1 2
1 2
RV6 124_0402_1%~DRV6 124_0402_1%~D
RV10
RV10
33_0402_5%~D
33_0402_5%~D
12
RV14
RV14
12
33_0402_5%~D
33_0402_5%~D
LDDC_CLK_GPU <23>
LDDC_DATA_GPU <23>
+CLK_PLLVDD
1 2
RV12 10K_0402_5%~DRV12 10K_0402_5%~D
1 2
RV16 10K_0402_5%~DRV16 10K_0402_5%~D
CLK_27M_OUT
1
CV35
CV35
2
20P_0402_50V8J~D
20P_0402_50V8J~D
GPU_SMBCLK
DGPU_PWR_EN
GPU_SMBDATGPU_SMBDAT_R
GPU_SMBCLK <41>
DGPU_PWR_EN <40,64>
GPU_SMBDAT <41>
GPU_CRT_CLK_DDC <25>
GPU_CRT_DAT_DDC <25>
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV85
CV85
1
2
2
GPU_CRT_RED
GPU_CRT_GRN
GPU_CRT_BLU
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV86
CV86
1
2
2
1
2
1
2
DPC_GPU_HPD
DPD_GPU_HPD
DPE_GPU_HPD
Close to GPU
1 2
RV3 150_0402_1%~DRV3 150_0402_1%~D
1 2
RV4 150_0402_1%~DRV4 150_0402_1%~D
1 2
RV5 150_0402_1%~DRV5 150_0402_1%~D
1U_0603_10V7K~D
1U_0603_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV200
CV200
CV202
CV202
1
12
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV89
CV89
CV88
CV88
1
2
+3.3V_RUN_GFX
RV23 4.7K_0402_5%~D@ RV23 4.7K_0402_5%~D@
RV24 4.7K_0402_5%~D@ RV24 4.7K_0402_5%~D@
RV104 10K_0402_5%~DRV104 10K_0402_5%~D
RV27 2.2K_0402_5%~DRV27 2.2K_0402_5%~D
RV28 2.2K_0402_5%~DRV28 2.2K_0402_5%~D
RV102 10K_0402_5%~DRV102 10K_0402_5%~D
RV103 10K_0402_5%~DRV103 10K_0402_5%~D
12
LV8
LV8
1
+3.3V_RUN_GFX
12
+1.05V_PEX_VDD
DP_HDMI_HPD <40>
DV2
DV2
2 1
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
DV3
DV3
2 1
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
DV4
DV4
2 1
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
ENVDD_GPU
1
CV107
CV107
2
1
2
1 2
1 2
1 2
1 2
1 2
1 2
RV1 100K_0402_5%~DRV1 100K_0402_5%~D
LV13
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
LV13
BLM18PG300SN1D_2P~D
BLM18PG300SN1D_2P~D
CV111
CV111
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
BLM18PG181SN1D_2P
BLM18PG181SN1D_2P
1
CV112
CV112
CV73
CV73
2
MAX14885EETL has internal 3K pu for
GPU_CRT_CLK_DDC and GPU_CRT_DAT_DDC
GPU_CRT_CLK_DDC
GPU_CRT_DAT_DDC
GPU_HOT#
I2CB_SCL
12
I2CB_SDA
12
GPU_GPIO9
THERMTRIP_VGA#
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
N12P PCIE,I2C,DAC,GPIO
N12P PCIE,I2C,DAC,GPIO
N12P PCIE,I2C,DAC,GPIO
LA-7782
LA-7782
LA-7782
45 66Friday, June 10, 2011
45 66Friday, June 10, 2011
45 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 46
5
LCD_ACLK+_GPU<23>
LCD_ACLK-_GPU<23>
LCD_A0+_GPU<23>
LCD_A0-_GPU<23>
LCD_A1+_GPU<23>
LCD_A1-_GPU<23>
LCD_A2+_GPU<23>
D D
TO DOCKING
TO DOCKING
C C
TO MB HDMI
1 2
RV38 100K_0402_5%~DRV38 100K_0402_5%~D
1 2
RV37 100K_0402_5%~DRV37 100K_0402_5%~D
1 2
RV35 100K_0402_5%~DRV35 100K_0402_5%~D
1 2
RV36 100K_0402_5%~DRV36 100K_0402_5%~D
Decive ID change to 0x1056
B B
+3.3V_RUN_GFX
+3.3V_RUN_GFX
RV49
RV49
45.3K_0402_1%~D
45.3K_0402_1%~D
A A
RV51
RV50
@ RV51
@
@ RV50
@
1 2
1 2
1 2
45.3K_0402_1%~D
45.3K_0402_1%~D
34.8K_0402_1%~D
34.8K_0402_1%~D
DPC_GPU_AUX/DDC
DPC_GPU_AUX#/DDC
DPD_GPU_AUX/DDC
DPD_GPU_AUX#/DDC
1 2
RV39 1.5K_0402_5%~DRV39 1.5K_0402_5%~D
1 2
RV40 1.5K_0402_5%~DRV40 1.5K_0402_5%~D
RV53
RV53
RV52
RV52
1 2
1 2
34.8K_0402_1%~D
34.8K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
LCD_A2-_GPU<23>
LCD_BCLK+_GPU<23>
LCD_BCLK-_GPU<23>
LCD_B0+_GPU<23>
LCD_B0-_GPU<23>
LCD_B1+_GPU<23>
LCD_B1-_GPU<23>
LCD_B2+_GPU<23>
LCD_B2-_GPU<23>
DPC_GPU_LANE_P0<39>
DPC_GPU_LANE_N0<39>
DPC_GPU_LANE_P1<39>
DPC_GPU_LANE_N1<39>
DPC_GPU_LANE_P2<39>
DPC_GPU_LANE_N2<39>
DPC_GPU_LANE_P3<39>
DPC_GPU_LANE_N3<39>
DPD_GPU_LANE_P0<39>
DPD_GPU_LANE_N0<39>
DPD_GPU_LANE_P1<39>
DPD_GPU_LANE_N1<39>
DPD_GPU_LANE_P2<39>
DPD_GPU_LANE_N2<39>
DPD_GPU_LANE_P3<39>
DPD_GPU_LANE_N3<39>
TMDSE_GPU_P2<26>
TMDSE_GPU_N2<26>
TMDSE_GPU_P1<26>
TMDSE_GPU_N1<26>
TMDSE_GPU_P0<26>
TMDSE_GPU_N0<26>
TMDSE_GPU_CLK<26>
TMDSE_GPU_CLK#<26>
DPC_GPU_AUX/DDC<27>
DPC_GPU_AUX#/DDC<27>
DPD_GPU_AUX/DDC<27>
DPD_GPU_AUX#/DDC<27>
TMDS_E_GPU_DDC<26>
TMDS_E_GPU_DDC#<26>
TMDS_E_GPU_DDC
TMDS_E_GPU_DDC#
RV54
RV54
RV97
RV97
1 2
1 2
10K_0402_1%~D
10K_0402_1%~D
34.8K_0402_1%~D
34.8K_0402_1%~D
RV98
@ RV98
@
10K_0402_1%~D
10K_0402_1%~D
1 2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
DPC_GPU_AUX/DDC
DPC_GPU_AUX#/DDC
DPD_GPU_AUX/DDC
DPD_GPU_AUX#/DDC
TMDS_E_GPU_DDC
TMDS_E_GPU_DDC#
???
4
UV1D
UV1D
AM6
IFPA_TXC
AN6
IFPA_TXC_N
AP3
IFPA_TXD0
AN3
IFPA_TXD0_N
AN5
IFPA_TXD1
AM5
IFPA_TXD1_N
AL6
IFPA_TXD2
AK6
IFPA_TXD2_N
AJ6
IFPA_TXD3
AH6
IFPA_TXD3_N
AJ9
IFPB_TXC
AH9
IFPB_TXC_N
AP6
IFPB_TXD4
AP5
IFPB_TXD4_N
AM7
IFPB_TXD5
AL7
IFPB_TXD5_N
AN8
IFPB_TXD6
AM8
IFPB_TXD6_N
AK8
IFPB_TXD7
AL8
IFPB_TXD7_N
AK1
IFPC_L0
AJ1
IFPC_L0_N
AJ3
IFPC_L1
AJ2
IFPC_L1_N
AH3
IFPC_L2
AH4
IFPC_L2_N
AG5
IFPC_L3
AG4
IFPC_L3_N
AM1
IFPD_L0
AM2
IFPD_L0_N
AM3
IFPD_L1
AM4
IFPD_L1_N
AL3
IFPD_L2
AL4
IFPD_L2_N
AK4
IFPD_L3
AK5
IFPD_L3_N
AD2
IFPE_L0
AD3
IFPE_L0_N
AD1
IFPE_L1
AC1
IFPE_L1_N
AC2
IFPE_L2
AC3
IFPE_L2_N
AC4
IFPE_L3
AC5
IFPE_L3_N
AE3
IFPF_L0
AE4
IFPF_L0_N
AF4
IFPF_L1
AF5
IFPF_L1_N
AD4
IFPF_L2
AD5
IFPF_L2_N
AG1
IFPF_L3
AF1
IFPF_L3_N
AG3
IFPC_AUX_I2CW_SCL
AG2
IFPC_AUX_I2CW_SDA_N
AK3
IFPD_AUX_I2CX_SCL
AK2
IFPD_AUX_I2CX_SDA_N
AB3
IFPE_AUX_I2CY_SCL
AB4
IFPE_AUX_I2CY_SDA_N
AF3
IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N
N13M_FCBGA908~D
N13M_FCBGA908~D
Part 4 of 7
Part 4 of 7
NC
NC
GENERAL
GENERAL
MULTI_STRAP_REF0_GND
LVDS/TMDS
LVDS/TMDS
GND_SENSE
TEST
TEST
JTAG_TRST_N
SERIAL
SERIAL
NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
BUFRST_N
CEC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
VDD_SENSE
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK
3
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
L2
L3
J2
J7
J6
J5
J3
J1
K3
K4
L4
RV11
RV11
1 2
10K_0402_5%~D
10K_0402_5%~D
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
MULTI_STRAP_REF0_GND
VGA_THERMDP <22>
1
CV37
@CV37
@
100P_0402_50V8J~D
100P_0402_50V8J~D
2
VGA_THERMDN <22>
GPU_VDD_SENSE <64>
+3.3V_RUN_GFX
1 2
RV93 40.2K_0402_1%~DRV93 40.2K_0402_1%~D
Use 16mils trace for sense pin
L5
GPU_TESTMODE
AK11
GPU_JTAG_TCK
AM10
GPU_JTAG_TDI
AM11
GPU_JTAG_TDO
AP12
GPU_JTAG_TMS
AP11
GPU_JTAG_TRST#
AN11
H6
H5
H7
H4
GPU_VSS_SENSE <64>
ROM_SI_GPU
ROM_SO_GPU
ROM_SCLK_GPU
TV2@TV2@
TV3@TV3@
TV4@TV4@
1 2
RV9
RV9
1K_0402_1%~D
1K_0402_1%~D
+3.3V_RUN_GFX
10K_0402_5%~D
10K_0402_5%~D
12
RV25
RV25
2
UV1F
UV1F
AG11
A2
A33
AA13
AA15
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
10K_0402_5%~D
10K_0402_5%~D
@
@
12
RV20
RV20
10K_0402_5%~D
10K_0402_5%~D
12
RV8
RV8
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
N13M_FCBGA908~D
N13M_FCBGA908~D
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
Part 6 of 7
Part 6 of 7
GND
GND
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
1
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
RV55
@ RV55
@
4.99K_0402_1%~D
4.99K_0402_1%~D
RV57
RV57
RV56
RV56
1 2
34.8K_0402_1%~D
34.8K_0402_1%~D
RV58
@ RV58
@
1 2
1 2
34.8K_0402_1%~D
34.8K_0402_1%~D
15K_0402_1%~D
15K_0402_1%~D
RV60
RV59
@ RV59
@
15K_0402_1%~D
15K_0402_1%~D
1 2
5
RV41
RV99
@ RV60
@
1 2
10K_0402_1%~D
10K_0402_1%~D
RV99
@ RV41
@
1 2
1 2
1 2
20K_0402_1%~D
20K_0402_1%~D
4.99K_0402_1%~D
4.99K_0402_1%~D
Hynix 128Mx16 GDDR5 part stuff RV53=35K
**
Samsung 128Mx16 GDDR5 part stuff RV53=45K
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
N12P DP, STRAP, GND
N12P DP, STRAP, GND
N12P DP, STRAP, GND
LA-7782
LA-7782
LA-7782
46 66Friday, June 10, 2011
46 66Friday, June 10, 2011
46 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 47
5
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
10U_0603_6.3V6M~D
CV78
CV78
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CV79
CV79
BLM18PG181SN1D_2P
BLM18PG181SN1D_2P
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV173
CV173
2
10U_0603_6.3V6M~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
LV11
LV11
1
D D
C C
A/B
2
1
2
+1.05V_PEX_VDD
+1.8V_RUN_GFX
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV39
CV39
1
CV47
CV47
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
@
LV10
LV10
@
1
CV55
CV55
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV175
CV175
1
2
CV40
CV40
BLM18AG121SN1D_0603~D
BLM18AG121SN1D_0603~D
CV169
CV169
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
CV48
CV48
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
CV56
CV56
2
+IFPAB_PLLVDD
1
2
+IFPAB_IOVDD
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV172
CV172
2
Close to Pinclose to the GPU
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
12
CV109
CV109
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV166
CV166
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV125
CV124
CV124
@
@
CV126
CV126
1U_0603_10V7K~D
1U_0603_10V7K~D
CV125
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV127
CV127
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV167
CV167
1
CV168
CV168
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV174
CV174
1
2
C/D
+3.3V_RUN_GFX
B B
+1.05V_PEX_VDD
LV6
LV6
MMZ1608R301AT_2P~D
MMZ1608R301AT_2P~D
1 2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV94
CV94
1
2
LV9
LV9
BLM18PG221SN1D_2P~D
BLM18PG221SN1D_2P~D
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV118
CV118
2
1U_0603_10V7K~D
1U_0603_10V7K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
12
CV96
CV96
CV95
CV95
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV119
CV119
1
1
CV120
CV120
2
2
+IFPCD_PLLVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV97
CV97
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV121
CV121
1
2
CV98
CV98
1
2
+IFPCD_IOVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV122
CV122
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV100
CV100
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV194
CV194
1
2
E/F
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV206
CV206
1
2
+1.5V_MEM_GFX
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CV115
CV115
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
@
@
1
CV160
CV160
2
+3.3V_RUN_GFX
+1.05V_PEX_VDD
4
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CV116
CV116
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CV161
CV161
2
+IFPAB_PLLVDD
IFPAB_RSET
+IFPAB_IOVDD
+IFPCD_PLLVDD
IFPC_RSET
+IFPCD_IOVDD
IFPD_RSET
+IFPEF_PLLVDD
IFPEF_RSET
+IFPEF_IOVDD
LV15
LV15
MMZ1608R301AT_2P~D
MMZ1608R301AT_2P~D
1 2
LV12
LV12
BLM18PG221SN1D_2P~D
BLM18PG221SN1D_2P~D
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV195
CV195
2
1
2
1
2
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
M27
N27
P27
R27
V27
W27
W30
W33
AH8
AG8
AG9
AF7
AF8
AF6
AG7
AN2
AG6
AB8
AD6
AC7
AC8
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV102
CV102
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV110
CV110
UV1E
UV1E
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
H8
FBVDDQ_29
H9
FBVDDQ_30
L27
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
T27
FBVDDQ_36
T30
FBVDDQ_37
T33
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
Y27
FBVDDQ_43
IFPAB_PLLVDD
AJ8
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
IFPC_PLLVDD
IFPC_RSET
IFPC_IOVDD
IFPD_PLLVDD
IFPD_RSET
IFPD_IOVDD
IFPEF_PLLVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
N13M_FCBGA908~D
N13M_FCBGA908~D
1U_0603_10V7K~D
1U_0603_10V7K~D
12
CV103
CV103
+IFPEF_IOVDD
1U_0603_10V7K~D
1U_0603_10V7K~D
1
12
CV183
CV183
2
3
Part 5 of 7
Part 5 of 7
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_PLLVDD
POWER
POWER
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
FB_GND_SENSE
FB_VDDQ_SENSE
PEX_PLL_HVDD
PEX_SVDD_3V3
+IFPEF_PLLVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV105
CV105
CV104
CV104
1
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV184
CV184
1
2
1
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV193
CV193
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
VDD33_0
VDD33_1
VDD33_2
VDD33_3
CV101
CV101
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AG19
AG21
AG22
AG24
AH21
AH25
AG26
J8
K8
L8
M8
J27
H27
H25
F2
F1
AH12
AG12
+3.3V_RUN_VDD33
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CV212
CV212
1
2
PLACE UNDER BGA PLACE NEAR GPU
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV214
CV214
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV63
CV63
1
1
2
2
1 2
RV42 40.2_0402_1%~DRV42 40.2_0402_1%~D
1 2
RV44 40.2_0402_1%~DRV44 40.2_0402_1%~D
1 2
RV43 60.4_0402_1%~DRV43 60.4_0402_1%~D
1 2
RV126 100_0402_1%~DRV126 100_0402_1%~D
1 2
RV125 100_0402_1%~DRV125 100_0402_1%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV64
CV64
CV108
CV108
1
1
1
2
2
2
+3.3V_RUN_GFX
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CV211
CV211
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CV213
CV213
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV99
CV99
1
BLM18AG121SN1D_0603~D
2
CV106
CV106
1 2
BLM18AG121SN1D_0603~D
+1.5V_MEM_GFX
+1.5V_MEM_GFX
+3.3V_RUN_GFX
CV205
CV205
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
RV7 0_0603_5%~DRV7 0_0603_5%~D
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV65
CV65
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
CV70
CV70
12
LV14
LV14
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CV52
CV52
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CV54
CV54
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
+1.05V_PEX_VDD
1
CV204
CV204
2
Near GPU Near Ball
+3.3V_RUN_VDD33
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
CV123
CV123
CV170
CV170
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV198
CV198
2
0.1U_0402_10V7K~D
1
1
CV75
CV75
CV68
CV68
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
CV51
CV51
CV53
CV53
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV76
CV76
+1.05V_PEX_VDD
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
CV67
CV67
2
+1.05V_PEX_VDD
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
CV71
CV71
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
CV69
CV69
2
2
1
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
CV74
CV74
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
CV77
CV77
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CV215
CV215
CV197
CV197
2
A A
IFPAB_RSET
IFPC_RSET
IFPD_RSET
IFPEF_RSET
@RV32
@
1 2
1K_0402_1%~D
1K_0402_1%~D
RV45
RV45
1 2
1K_0402_1%~D
1K_0402_1%~D
RV47
RV47
1 2
1K_0402_1%~D
1K_0402_1%~D
RV48
RV48
1 2
1K_0402_1%~D
1K_0402_1%~D
5
RV32
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
N12P Power
N12P Power
N12P Power
LA-7782
LA-7782
LA-7782
47 66Friday, June 10, 2011
47 66Friday, June 10, 2011
47 66Friday, June 10, 2011
1
0.1
0.1
0.1
of
Page 48
5
D D
4
3
2
1
+GPU_CORE
Caps on Power Side
C C
B B
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
R13
R15
R17
R18
R20
R22
U13
U15
U17
U18
U20
U22
UV1G
UV1G
VDD_0
Part 7 of 7
Part 7 of 7
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
P12
VDD_30
P14
VDD_31
P16
VDD_32
P19
VDD_33
P21
VDD_34
P23
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
T12
VDD_42
T14
VDD_43
T16
VDD_44
T19
VDD_45
T21
VDD_46
T23
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
V13
VDD_54
V15
VDD_55
POWER
POWER
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
+GPU_CORE
N1
N1
3M_FCBGA908~D
3M_FCBGA908~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
N12P Power GFX Core
N12P Power GFX Core
N12P Power GFX Core
LA-7782
LA-7782
LA-7782
1
0.1
0.1
48 66Friday, May 20, 2011
48 66Friday, May 20, 2011
48 66Friday, May 20, 2011
0.1
of
Page 49
5
4
3
2
1
FBA_D[0..63]
FBA_CMD[0..31]
FBA_DBI[0..7]
FBA_EDC[0..7]
D D
+1.5V_MEM_GFX
10K_0402_5%~D
10K_0402_5%~D
12
RV66
RV66
CKE_H
FBA_CMD30
+1.5V_MEM_GFX
10K_0402_5%~D
10K_0402_5%~D
12
RV68
RV68
CKE_L
FBA_CMD14
C C
FBA_CMD29
10K_0402_5%~D
10K_0402_5%~D
12
RV71
RV71
RST_H*
FBA_CMD13
10K_0402_5%~D
10K_0402_5%~D
12
RV72
RV72
RST_L*
B B
for Test/Debug
+1.5V_MEM_GFX
1.1K_0402_1%~D
1.1K_0402_1%~D
@RV77
@
12
RV77
16mil
+FB_VREF
0.01U_0402_16V7K~D
@RV78
@
12
RV78
1
2
BLM18PG300SN1D_2P~D
BLM18PG300SN1D_2P~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV199
CV199
2
0.01U_0402_16V7K~D
@ CV128
@
CV128
1 2
1.1K_0402_1%~D
1.1K_0402_1%~D
A A
+1.05V_PEX_VDD
FBA_D[0..63] <51,52>
FBA_CMD[0..31] <51,52>
FBA_DBI[0..7] <51,52>
+1.5V_MEM_GFX
LV7
LV7
5
FBA_EDC[0..7] <51,52>
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
+FBA_PLL_AVDD
+FB_VREF
+FBA_PLL_AVDD
CV82
0.1U_0402_10V7K~D
CV82
0.1U_0402_10V7K~D
1
2
12
12
RV46
RV46
60.4_0402_1%~D
60.4_0402_1%~D
+FBA_PLL_AVDD
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CV135
CV135
CV72
CV72
1
1
2
2
UV1B
UV1B
L28
FBA_D00
M29
FBA_D01
L29
FBA_D02
M28
FBA_D03
N31
FBA_D04
P29
FBA_D05
R29
FBA_D06
P28
FBA_D07
J28
FBA_D08
H29
FBA_D09
J29
FBA_D10
H28
FBA_D11
G29
FBA_D12
E31
FBA_D13
E32
FBA_D14
F30
FBA_D15
C34
FBA_D16
D32
FBA_D17
B33
FBA_D18
C33
FBA_D19
F33
FBA_D20
F32
FBA_D21
H33
FBA_D22
H32
FBA_D23
P34
FBA_D24
P32
FBA_D25
P31
FBA_D26
P33
FBA_D27
L31
FBA_D28
L34
FBA_D29
L32
FBA_D30
L33
FBA_D31
AG28
FBA_D32
AF29
FBA_D33
AG29
FBA_D34
AF28
FBA_D35
AD30
FBA_D36
AD29
FBA_D37
AC29
FBA_D38
AD28
FBA_D39
AJ29
FBA_D40
AK29
FBA_D41
AJ30
FBA_D42
AK28
FBA_D43
AM29
FBA_D44
AM31
FBA_D45
AN29
FBA_D46
AM30
FBA_D47
AN31
FBA_D48
AN32
FBA_D49
AP30
FBA_D50
AP32
FBA_D51
AM33
FBA_D52
AL31
FBA_D53
AK33
FBA_D54
AK32
FBA_D55
AD34
FBA_D56
AD32
FBA_D57
AC30
FBA_D58
AD33
FBA_D59
AF31
FBA_D60
AG34
FBA_D61
AG32
FBA_D62
AG33
FBA_D63
U27
FBA_PLL_AVDD
H26
FB_VREF
K27
FB_DLL_AVDD
E1
FB_CLAMP
R28
FBA_DEBUG0
AC28
FBA_DEBUG1
RV61
RV61
60.4_0402_1%~D
60.4_0402_1%~D
N13M_FCBGA908~D
N13M_FCBGA908~D
+FBA_PLL_AVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV81
CV81
1
2
Part 2 of 7
Part 2 of 7
MEMORY INTERFACE
A
MEMORY INTERFACE
A
FBA_CMD_RFU0
FBA_CMD_RFU1
THE FBA_ECKBxx ARE
THE FBA_ECKBxx ARE
USED ON GK107. NC
USED ON GK107. NC
ON GF108 AND GF117
ON GF108 AND GF117
FBA_WCKB01_N
FBA_WCKB23_N
FBA_WCKB45_N
FBA_WCKB67_N
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB23
FBA_WCKB45
FBA_WCKB67
4
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
P30
F31
F34
M32
AD31
AL29
AM32
AF34
M30
H30
E34
M34
AF30
AK31
AM34
AF32
M31
G31
E33
M33
AE31
AK30
AN33
AF33
R32
AC32
R30
R31
AB31
AC31
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
FBA_WCK01
FBA_WCK01#
FBA_WCK23
FBA_WCK23#
FBA_WCK45
FBA_WCK45#
FBA_WCK67
FBA_WCK67#
CLKA0 <51>
CLKA0# <51>
CLKA1 <52>
CLKA1# <52>
FBA_WCK01 <51>
FBA_WCK01# <51>
FBA_WCK23 <51>
FBA_WCK23# <51>
FBA_WCK45 <52>
FBA_WCK45# <52>
FBA_WCK67 <52>
FBA_WCK67# <52>
GFX_MEM_VTT_ON#
GDDR5 CMD Mapping Table
<0..31> <32..63> Memory
C
MD12 CMD28 RAS#
CMD15 CMD31 CAS#
CMD5 CMD21 WE#
CMD0 CMD16 CS#
CMD8 CMD24 ABI#
CMD10 CMD26 A0_A10
CMD11 CMD27 A1_A9
CMD2 CMD18 A2_BA0
CMD1 CMD17 A3_BA3
CMD3 CMD19 A4_BA2
CMD4 CMD20 A5_BA1
CMD7 CMD23 A6_A11
CMD6 CMD22 A7_A8
CMD9 CMD25 A12_FRU
CMD14 CMD30 CKE#
CMD13 CMD29 RESET#
+1.8V_RUN_GFX
39_0402_5%~D
39_0402_5%~D
12
+1.8V_RUN_GFX_CHG
13
D
D
2
G
G
S
S
+1.5V_MEM_GFX +1.05V_PEX_VDD +3.3V_RUN_GFX
39_0402_5%~D
39_0402_5%~D
12
RV128
RV127
RV127
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
QV10
QV10
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RV128
+1.5V_MEM_GFX_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
QV11
QV11
13
D
D
2
G
G
S
S
3
2
G
G
39_0402_5%~D
39_0402_5%~D
12
+1.05V_PEX_VDD_CHG
13
D
D
S
S
RV129
RV129
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
QV12
QV12
3.3V_RUN_GFX_ON#
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3.3V_RUN_GFX_ON<15,40>
GFX_MEM_VTT_ON<40>
12
+3.3V_RUN_GFX_CHG
13
D
D
2
G
G
S
S
+1.8V_RUN_GFX Source
+1.8V_RUN +1.8V_RUN_GFX
1.05V_RUN_VTT_GFX#_EN 1.05V_RUN_VTT_GFX#_EN_R
1 2
RV95 0_0402_5%~DRV95 0_0402_5%~D
+3.3V_RUN_GFX Source
+3.3V_ALW2
12
RV92
RV92
100K_0402_5%~D
100K_0402_5%~D
3.3V_RUN_GFX_ON#
61
QV6A
QV6A
2
+3.3V_ALW2 +1.5V_MEM
100K_0402_5%~D
100K_0402_5%~D
12
RV69
RV69
GFX_MEM_VTT_ON#
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
QV2A
QV2A
2
39_0402_5%~D
39_0402_5%~D
RV130
RV130
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
QV13
QV13
+PWR_SRC_S
5
+PWR_SRC_S
5
+PWR_SRC_S
2
G
G
+3.3V_ALW +3.3V_RUN_GFX
12
RV91
RV91
100K_0402_5%~D
100K_0402_5%~D
3.3V_RUN_GFX_EN
1M_0402_5%~D
1M_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
12
3
4
12
RV94
RV94
QV6B
QV6B
+1.5V_MEM_GFX Source
100K_0402_5%~D
100K_0402_5%~D
RV67
RV67
GFX_MEM_VTT_EN
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
QV2B
QV2B
8
7
5
470K_0402_5%~D
470K_0402_5%~D
12
RV80
RV80
+1.05V_RUN_VTT_GFX Source
+1.05V_M
100K_0402_5%~D
100K_0402_5%~D
12
RV73
RV73
1.05V_RUN_VTT_GFX#_EN
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
470K_0402_5%~D
470K_0402_5%~D
13
D
D
S
S
12
QV4
QV4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
N12P Memory
N12P Memory
N12P Memory
LA-7782
LA-7782
LA-7782
QV7
QV7
PMV45EN_SOT23-3~D
PMV45EN_SOT23-3~D
D
S
D
S
1 3
G
G
2
QV5
QV5
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
3300P_0402_50V7K~D
3300P_0402_50V7K~D
CV186
CV186
1
2
QV1
QV1
SI4164DY-T1-GE3_SO8~D
SI4164DY-T1-GE3_SO8~D
QV3
QV3
SI4164DY-T1-GE3_SO8~D
SI4164DY-T1-GE3_SO8~D
8
7
5
RV81
RV81
1
2
36
4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
CV129
CV129
2
4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
CV132
CV132
1
2
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
1
2
1
2
1
2
36
20K_0402_5%~D
20K_0402_5%~D
12
RV96
RV96
CV50
CV50
20K_0402_5%~D
20K_0402_5%~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
CV49
CV49
+1.5V_MEM_GFX
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
CV45
CV45
+1.05V_PEX_VDD
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
CV46
CV46
1
2
49 66Friday, June 10, 2011
49 66Friday, June 10, 2011
49 66Friday, June 10, 2011
RV90
RV90
20K_0402_5%~D
20K_0402_5%~D
RV70
RV70
20K_0402_5%~D
20K_0402_5%~D
RV74
RV74
0.1
0.1
0.1
Page 50
5
4
3
2
1
CHANNEL-B NOT TO USE, NEED TO BE DISABLED
UV1C
D D
C C
B B
+FBA_PLL_AVDD
+1.5V_MEM_GFX
+FBA_PLL_AVDD
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV83
CV83
1
2
12
RV63
RV63
60.4_0402_1%~D
60.4_0402_1%~D
UV1C
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
H17
G14
G20
12
RV62
RV62
60.4_0402_1%~D
60.4_0402_1%~D
Part 3 of 7
Part 3 of 7
FBB_D00
FBB_D01
FBB_D02
FBB_D03
FBB_D04
FBB_D05
FBB_D06
FBB_D07
FBB_D08
FBB_D09
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_PLL_AVDD
FBB_DEBUG0
FBB_DEBUG1
THE FBA_ECKBxx ARE
THE FBA_ECKBxx ARE
USED ON GK107.
USED ON GK107.
NC ON GF108 AND
NC ON GF108 AND
GF117
GF117
N13M_FCBGA908~D
N13M_FCBGA908~D
MEMORY INTERFACE
B
MEMORY INTERFACE
B
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_CMD_RFU0
FBB_CMD_RFU1
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
E11
E3
A3
C9
F23
F27
C30
A24
D9
E4
B2
A9
D22
D28
A30
B23
D10
D5
C3
B9
E23
E28
B30
A23
C12
C20
D12
E12
E20
F20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
N12P Memory (2)
N12P Memory (2)
N12P Memory (2)
LA-7782
LA-7782
LA-7782
50 66Friday, May 20, 2011
50 66Friday, May 20, 2011
50 66Friday, May 20, 2011
1
0.1
0.1
0.1
of
Page 51
5
Memory Partition A - Lower 32
UV4
bits
RV109
RV109
1.33K_0402_1%~D
1.33K_0402_1%~D
RV110
RV110
1.33K_0402_1%~D
1.33K_0402_1%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV152
CV152
1
CV177
CV177
2
+1.5V_MEM_GFX
RV112
RV112
549_0402_1%~D
549_0402_1%~D
RV114
RV114
549_0402_1%~D
549_0402_1%~D
+FBA_VREFC_L
FBA_EDC0
FBA_EDC2
FBA_DBI0
FBA_DBI2
FBA_CMD14
FBA_CMD9
FBA_CMD6
FBA_CMD7
FBA_CMD4
FBA_CMD3
FBA_CMD1
FBA_CMD2
FBA_CMD11
FBA_CMD10
FBA_SEN0
FBA_CMD8
FBA_CMD12
FBA_CMD0
FBA_CMD15
FBA_CMD5
FBA_WCK01#
FBA_WCK01
FBA_WCK23#
FBA_WCK23
FBA_CMD13
+1.5V_MEM_GFX
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV153
CV153
1
2
12
12
???
D D
CLKA0<49>
CLKA0#<49>
RV105
RV105
40.2_0402_1%~D
40.2_0402_1%~D
1 2
1 2
RV106
RV106
40.2_0402_1%~D
40.2_0402_1%~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CV165
CV165
2
C C
B B
A A
CLKA0
CLKA0#
RV17 1K_0402_1%~DRV17 1K_0402_1%~D
1 2
RV22 1K_0402_1%~DRV22 1K_0402_1%~D
1 2
RV108 121_0402_1%~DRV108 121_0402_1%~D
1 2
FBA_WCK01#<49>
FBA_WCK01<49>
FBA_WCK23#<49>
FBA_WCK23<49>
+FBA_VREFD_L
+FBA_VREFC_L
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CV41
CV41
1
2
+FBA_VREFD_L
RV111
RV111
931_0402_1%
931_0402_1%
RV113
RV113
931_0402_1%
931_0402_1%
FBVREF_ALTV<45,52>
2
G
G
1
2
CV207
CV207
820P_0402_50V7K~D
820P_0402_50V7K~D
1
2
CV208
CV208
820P_0402_50V7K~D
820P_0402_50V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CV176
CV176
2
2
12
12
13
D
D
QV8
QV8
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
5
12
12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
UV4
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
J5
A12/RFU/NC
K4
A8/A7 A10/A0
K5
A11/A6 A9/A1
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
H11
BA0/A2 BA2/A4
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
4
NORMAL
4
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ2H24MFR-T2C
H5GQ2H24MFR-T2C
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
+1.5V_MEM_GFX
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CV42
CV42
1
2
64X32 GDDR5
???
+1.5V_MEM_GFX
FBA_WCK23#<49>
FBA_WCK23<49>
FBA_WCK01#<49>
FBA_WCK01<49>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
1
CV188
CV188
CV178
CV178
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CV130
CV130
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CLKA0
CLKA0#
FBA_CMD14
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD1
FBA_CMD2
FBA_CMD4
FBA_CMD3
FBA_CMD7
FBA_CMD6
1K_0402_1%~D
1K_0402_1%~D
1 2
RV107
RV107
121_0402_1%~D
121_0402_1%~D
FBA_CMD8
FBA_CMD15
FBA_CMD5
FBA_CMD12
FBA_CMD0
+FBA_VREFD_L
+FBA_VREFC_L
FBA_CMD13
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV142
CV142
CV141
CV141
1
2
+1.5V_MEM_GFX
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV154
CV154
1
CV131
CV131
2
3
FBA_EDC3
FBA_EDC1
FBA_DBI3
FBA_DBI1
RV19
RV19
1 2
FBA_SEN0
FBA_WCK23#
FBA_WCK23
FBA_WCK01#
FBA_WCK01
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV143
CV143
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV155
CV155
1
2
C13
R13
D13
P13
K10
K11
H10
H11
G12
A10
U10
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV151
CV151
1
2
C10
R10
D11
G11
P11
G14
B10
D10
G10
P10
H14
K14
UV5
UV5
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
J5
A12/RFU/NC
K4
A8/A7 A10/A0
K5
A11/A6 A9/A1
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5
BA0/A2 BA2/A4
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
VREFD
VREFD
J14
VREFC
J2
RESET#
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
VDD
VDD
VDD
VDD
L11
VDD
VDD
VDD
L14
VDD
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
VSS
VSS
VSS
L10
VSS
VSS
T10
VSS
VSS
VSS
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
MIRROR
2
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ2H24MFR-T2C
H5GQ2H24MFR-T2C
2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
+1.5V_MEM_GFX
1
FBA_CMD[0..31]
FBA_D[0..31]
FBA_DBI[0..3]
FBA_EDC[0..3]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CV137
CV137
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV139
CV139
1
1
1
CV138
CV138
2
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV140
CV140
1
2
FBA_CMD[0..31] <49,52>
FBA_D[0..31] <49>
FBA_DBI[0..3] <49>
FBA_EDC[0..3] <49>
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV182
CV182
CV179
CV179
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
VRAM A Lower
VRAM A Lower
VRAM A Lower
LA-7782
LA-7782
LA-7782
51 66Friday, June 10, 2011
51 66Friday, June 10, 2011
51 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 52
5
Memory Partition A - Upper 32 bits
UV3
UV3
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
RV64
RV64
RV119
RV119
1.33K_0402_1%~D
1.33K_0402_1%~D
RV120
RV120
1.33K_0402_1%~D
1.33K_0402_1%~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV157
CV157
1
CV192
CV192
2
+1.5V_MEM_GFX
RV122
RV122
549_0402_1%~D
549_0402_1%~D
RV124
RV124
549_0402_1%~D
549_0402_1%~D
+FBA_VREFC_H
FBA_EDC7
FBA_EDC5
FBA_DBI7
FBA_DBI5
FBA_CMD30
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD17
FBA_CMD18
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD22
FBA_CMD24
FBA_CMD31
FBA_CMD21
FBA_CMD28
FBA_CMD16
FBA_WCK67#
FBA_WCK67
FBA_WCK45#
FBA_WCK45
FBA_CMD29
+1.5V_MEM_GFX
1
2
12
12
???
D D
CLKA1<49>
CLKA1#<49>
RV115
RV115
40.2_0402_1%~D
40.2_0402_1%~D
1 2
1 2
RV116
RV116
40.2_0402_1%~D
40.2_0402_1%~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CV190
CV190
2
C C
B B
A A
CLKA1
CLKA1#
1K_0402_1%~D
1K_0402_1%~D
+1.5V_MEM_GFX
RV34 1K_0402_1%~DRV34 1K_0402_1%~D
RV118 121_0402_1%~DRV118 121_0402_1%~D
+FBA_VREFD_H
+FBA_VREFC_H
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
+FBA_VREFD_H
RV121
RV121
931_0402_1%
931_0402_1%
RV123
RV123
931_0402_1%
931_0402_1%
FBVREF_ALTV<45,51>
2
G
G
5
1 2
1 2
1 2
FBA_WCK67#<49>
FBA_WCK67<49> FBA_WCK67<49>
FBA_WCK45#<49>
FBA_WCK45<49>
12
1
2
CV209
CV209
12
820P_0402_50V7K~D
820P_0402_50V7K~D
1
2
CV210
CV210
820P_0402_50V7K~D
820P_0402_50V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CV43
CV43
1U_0402_6.3V6K~D
1
1
CV191
CV191
2
2
12
12
13
D
D
QV9
QV9
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV158
CV158
FBA_SEN2
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
J5
A12/RFU/NC
K4
A8/A7 A10/A0
K5
A11/A6 A9/A1
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
H11
BA0/A2 BA2/A4
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
4
MIRROR
4
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ2H24MFR-T2C
H5GQ2H24MFR-T2C
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
+1.5V_MEM_GFX
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CV44
CV44
1
2
3
UV6
UV6
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
FBA_WCK45#
FBA_WCK45
FBA_WCK67#
FBA_WCK67
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV144
CV144
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV162
CV162
1
2
C13
R13
D13
P13
K10
K11
H10
H11
G12
L12
A10
U10
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV156
CV156
1
2
C10
R10
D11
G11
L11
P11
G14
L14
B10
D10
G10
L10
P10
T10
H14
K14
EDC1 EDC2
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
J5
A12/RFU/NC
K4
A8/A7 A10/A0
K5
A11/A6 A9/A1
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5
BA0/A2 BA2/A4
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
CS# WE#
L3
CAS# RAS#
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
VREFD
VREFD
J14
VREFC
J2
RESET#
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
?
??
FBA_WCK45#<49>
FBA_WCK45<49>
FBA_WCK67#<49>
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
1
CV189
CV189
CV180
CV180
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CV134
CV134
2
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
FBA_CMD30
FBA_CMD25
FBA_CMD22
FBA_CMD23
FBA_CMD20
FBA_CMD19
FBA_CMD17
FBA_CMD18
FBA_CMD27
FBA_CMD26
RV65
RV65
1K_0402_1%~D
1K_0402_1%~D
1 2
1 2
RV117
RV117
121_0402_1%~D
121_0402_1%~D
+FBA_VREFD_H
+FBA_VREFC_H
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV145
CV145
1
2
+1.5V_MEM_GFX
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CV133
CV133
2
FBA_EDC6
FBA_DBI4
FBA_DBI6
CLKA1
CLKA1#
FBA_SEN2
FBA_CMD24
FBA_CMD28
FBA_CMD16
FBA_CMD31
FBA_CMD21
FBA_CMD29
CV146
CV146
CV159
CV159
NORMAL
H5GQ2H24MFR-T2C
H5GQ2H24MFR-T2C
2
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
1
FBA_D32
FBA_D33FBA_EDC4
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
+1.5V_MEM_GFX
FBA_CMD[0..31]
FBA_D[32..63]
FBA_DBI[4..7]
FBA_EDC[4..7]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV147
1
CV149
CV149
2
CV147
1
1
1
CV148
CV148
2
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV150
CV150
1
2
FBA_CMD[0..31] <49,51>
FBA_DBI[4..7] <49>
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CV181
CV181
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
VRAM A Upper
VRAM A Upper
VRAM A Upper
LA-7782
LA-7782
LA-7782
1
FBA_D[32..63] <49>
FBA_EDC[4..7] <49>
CV185
CV185
52 66Friday, June 10, 2011
52 66Friday, June 10, 2011
52 66Friday, June 10, 2011
0.1
0.1
0.1
Page 53
5
4
3
2
1
+3.3V_RTC_LDO
PD4
PD4
RB715FGT106_UMD3
RB715FGT106_UMD3
+COINCELL
12
PR1
PR1
1K_0402_5%~D
1K_0402_5%~D
Z4012
2
3
1
1
2
PU1
PU1
1
NO
2
V+
GND
NC3COM
TS5A63157DCKR_SC70-6~D
TS5A63157DCKR_SC70-6~D
COIN RTC Battery
+COINCELL
TYCO_2-1775293-2~D
+RTC_CELL
PC3
PC3
1U_0603_10V4Z~D
1U_0603_10V4Z~D
6
IN
5
4
+5V_ALW
PS_ID <41>
TYCO_2-1775293-2~D
JRTC1
JRTC1
1
3
1
G
4
22G
ESD Diodes
1
@
@
PD1
PD1
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
Media Bay Battery Connector
MBATT1
12
MBATT1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
SUYIN_150010GR006M500ZR
SUYIN_150010GR006M500ZR
Z5304
Z5305
Z5306
D D
PC2
PC2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
Primary Battery Connector
11
GND
10
GND
9
9
8
8
7
7
6
6
PBATT1
PBATT1
5
5
4
4
3
3
2
2
1
1
12
PC5
PC5
C C
2200P_0402_50V7K~D
2200P_0402_50V7K~D
SUYIN_200275MR009G50PZR
SUYIN_200275MR009G50PZR
B B
Z4304
Z4305
Z4306
GND
NB_PSID
2
3
PR3
PR3
100_0402_5%~D
100_0402_5%~D
GND
1 2
1
@
@
PD5
PD5
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
2
3
PR7
PR7
100_0402_5%~D
100_0402_5%~D
1 2
100_0402_5%~D
100_0402_5%~D
1
2
PR4
PR4
100_0402_5%~D
100_0402_5%~D
1 2
ESD Diodes
PR9
PR9
100_0402_5%~D
100_0402_5%~D
1 2
PL4
PL4
BLM18BD102SN1D_0603~D
BLM18BD102SN1D_0603~D
@
@
PD2
PD2
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
3
PR5
PR5
1 2
1
@
@
PD6
PD6
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
2
3
PR8
PR8
100_0402_5%~D
100_0402_5%~D
1 2
12
MBATT+_C
BAY_SMBCLK <29,41>
BAY_SMBDAT <29,41>
PBAT_SMBCLK <41>
PBAT_SMBDAT <41>
PR14
PR14
1 2
100K_0402_1%~D
100K_0402_1%~D
PR16
PR16
1 2
15K_0402_1%~D
15K_0402_1%~D
PBATT+_C
PR11
@ PR11
@
1 2
0_0402_5%~D
0_0402_5%~D
D
D
1 3
2
B
B
E
E
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
2 1
12
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
PC1
PC1
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
12
PC4
PC4
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
S
S
PQ2
PQ2
FDV301N_G_NL_SOT23-3~D
FDV301N_G_NL_SOT23-3~D
G
G
2
C
C
PQ3
PQ3
MMST3904-7-F_SOT323~D
MMST3904-7-F_SOT323~D
3 1
PL1
PL1
PJP1
@ PJP1
@
1 2
1 2
@ PJP2
@
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PR13
PR13
33_0402_5%~D
33_0402_5%~D
1 2
+3.3V_ALW
PBATT+
PR15
PR15
10K_0402_1%~D
10K_0402_1%~D
PR2
PR2
PR17
PR17
1 2
10K_0402_5%~D@
10K_0402_5%~D@
12
100K_0402_5%~D
100K_0402_5%~D
+3.3V_ALW
PR6
PR6
+3.3V_ALW
PR12
PR12
12
100K_0402_5%~D
100K_0402_5%~D
1 2
2.2K_0402_5%~D
2.2K_0402_5%~D
MODULE_BATT_PRES# <40,63>
PBAT_PRES# <40,63>
DOCK_PSID<39> GPIO_PSID_SELECT <40>
NB_PSID_TS5A63157
PSID_DISABLE# <40>
MPBATT+
PL2
PL2
PL3
PL3
PJP2
+5V_ALW
12
DC_IN+ Source
+DC_IN
PL5
PL5
FBMA-L18-453215-900LMA90T_1812~D
FBMA-L18-453215-900LMA90T_1812~D
1 2
1
12
PD13
2
PL6
PL6
1 2
PD13
@
@
12
VZ0603M260APT_0603
VZ0603M260APT_0603
PC16
PC16
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
MOLEX_87438-0743
MOLEX_87438-0743
7
7
6
6
-DCIN_JACK
5
5
4
4
+DCIN_JACK
3
PJPDC1
PJPDC1
3
2
2
1
1
A A
PC13
PC13
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
FBMA-L18-453215-900LMA90T_1812~D
FBMA-L18-453215-900LMA90T_1812~D
12
PC18
PC18
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
5
+DC_IN
PC10
PC10
12
PR23
@ PR23
@
4.7K_0805_5%~D
4.7K_0805_5%~D
12
1 2
PR20
PR20
1M_0402_5%~D
1M_0402_5%~D
0.022U_0805_50V7K~D
0.022U_0805_50V7K~D
12
PR26
PR26
4
PQ5
PQ5
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
1
S
2
S
3
S
4
G
PR24
PR24
1 2
10K_0402_5%~D
10K_0402_5%~D
1M_0402_5%~D
1M_0402_5%~D
8
D
7
D
6
D
5
D
SOFT_START_GC <63>
12
12
PC12
PC12
PC11
PC11
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
12
12
PC15
PC14
PC14
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC15
PR22
PR22
100K_0402_5%~D
100K_0402_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3.3V_ALW
+PWR_SRC
PR25
PR25
0_0402_5%
0_0402_5%
VSB_N_002
1 2
12
12
PC8
PC8
PR19
PR19
100K_0402_1%
PR21
PR21
22K_0402_1%
22K_0402_1%
1 2
VSB_N_003
13
D
D
PQ6
PQ6
2
G
SSM3K7002FU_SC70-3
G
SSM3K7002FU_SC70-3
S
S
12
PC17
PC17
.1U_0402_16V7K
.1U_0402_16V7K
100K_0402_1%
VSB_N_001
2
TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
0.22U_0603_25V7K
0.22U_0603_25V7K
2
+PWR_SRC_S
13
12
PC9
PC9
PQ4
PQ4
0.1U_0603_25V7K
0.1U_0603_25V7K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+DCIN
+DCIN
ze Document Number Rev
+DCIN
LA-7782
LA-7782
LA-7782
1
0.1
0.1
53 66Friday, June 10, 2011
53 66Friday, June 10, 2011
53 66Friday, June 10, 2011
0.1
Page 54
A
B
C
D
E
2VREF_6182
1 1
1U_0603_16V6K
1U_0603_16V6K
PJP100
PJP100
1 2
PAD-OPEN 1x3m
+PWR_SRC
PAD-OPEN 1x3m
PL100
@ PL100
@
1UH_PCMB053T-1R0MS_7A_20%
1UH_PCMB053T-1R0MS_7A_20%
2 2
12
+3.3V_ALWP
3.3VALWP
TDC 4.729A
Peak Current 6.756A
+DC1_PWR_SRC
12
12
PC102
PC102
PC100
PC100
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
12
12
PC119
PC119
PC103
PC103
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
1 2
1
+
+
PC110
PC110
2
220U_D_6.3VM_R25M
220U_D_6.3VM_R25M
PQ100
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
PL101
PL101
PQ100
12
PR109
PR109
@
@
4.7_1206_5%
4.7_1206_5%
SNUB_3V
12
@
@
+3.3V_RTC_LDO
3 5
241
3 5
241
PC112
PC112
680P_0603_50V7K
680P_0603_50V7K
PR100
PR100
0_0402_5%
0_0402_5%
1 2
10U_0805_6.3V6M
10U_0805_6.3V6M
PC108
PC108
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
PQ102
PQ102
FDMC8878_POWER33-8-5
FDMC8878_POWER33-8-5
+3.3V_ALW2
12
PC107
PC107
LX_3V
PR107
PR107
1 2
2.2_0603_5%
2.2_0603_5%
LG_3V
OCP current 8.107A
PR111
PR113
PD100
PD100
MMSZ5229BS_SOD323~D
MMSZ5229BS_SOD323~D
3 3
+PWR_SRC
1 2
PR113
499K_0402_1%~D
499K_0402_1%~D
PR111
300K_0402_1%
300K_0402_1%
12
13K_0402_1%
13K_0402_1%
20K_0402_1%
20K_0402_1%
143K_0402_1%~D
143K_0402_1%~D
BST_3V
UG_3V
12
PC115
PC115
@
@
1U_0603_10V6K
1U_0603_10V6K
PR101
PR101
1 2
PR103
PR103
1 2
PR105
PR105
1 2
25
7
8
9
10
11
12
12
PU100
PU100
P PAD
VO2
VREG3
BOOT2
UGATE2
PHASE2
LGATE2
2VREF_6182
ENTRIP2
3
PQ104B
PR115
PR115
2K_0402_1%~D
2K_0402_1%~D
1 2
PR116
PR116
1 2
PQ104B
PC117
PC117
@
@
5
4
2
12
1U_0603_10V6K
1U_0603_10V6K
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
ALWON<41>
4 4
THERM_STP#<22>
0_0402_5%
0_0402_5%
A
ENTRIP1
61
2
13
PQ105
PQ105
PDTC115EU_SOT323-3
PDTC115EU_SOT323-3
PQ104A
PQ104A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR114
PR114
100K_0402_1%
100K_0402_1%
1 2
B
+5V_ALW2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
12
PC101
PC101
FB_3V
ENTRIP2
6
ENTRIP2
EN
13
+DC1_PWR_SRC
FB_5V
2
5
4
3
FB1
FB2
REF
TONSEL
SKIPSEL
VIN16GND
14
17
15
12
PC114
PC114
4.7U_0805_10V6K
4.7U_0805_10V6K
12
PC116
PC116
0.1U_0603_25V7K
0.1U_0603_25V7K
PR102
PR102
30.9K_0402_1%
30.9K_0402_1%
1 2
PR104
PR104
20K_0402_1%
20K_0402_1%
1 2
PR106
PR106
86.6K_0402_1%
86.6K_0402_1%
ENTRIP1
1 2
1
ENTRIP1
24
VO1
23
PGOOD
BOOT1
UGATE1
PHASE1
LGATE1
NC18VREG5
BST_5V
22
UG_5V
21
LX_5V
20
LG_5V
19
RT8205LZQW(2) WQFN 24P PWM
RT8205LZQW(2) WQFN 24P PWM
+5V_ALW2
+3.3V_ALWP
1 2
2.2_0603_5%
2.2_0603_5%
+5V_ALWP
+DC1_PWR_SRC
12
PC104
PC104
0.1U_0402_25V6
0.1U_0402_25V6
PR108
PR108
BST1_5VBST1_3V
+3.3V_ALW
PR112
PR112
100K_0402_1%
100K_0402_1%
12
PC106
PC106
PC105
PC105
2200P_0402_50V7K
2200P_0402_50V7K
PC109
PC109
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
1 2
PJP101
PJP101
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP102
PJP102
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP103
PJP103
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP104
PJP104
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
D
12
12
PC118
PC118
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PQ103
PQ103
ALW_PWRGD_3V_5V <41>
+5V_ALW
+3.3V_ALW
PQ101
PQ101
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
PR110
PR110
@
@
3 5
241
PL102
PL102
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
1 2
12
4.7_1206_5%
4.7_1206_5%
SNUB_5V
12
PC113
PC113
@
@
680P_0603_50V7K
680P_0603_50V7K
1
+
+
PC111
PC111
2
220U_D_6.3VM_R25M
220U_D_6.3VM_R25M
+5V_ALWP
5VALWP
TDC 9.044A
Peak Current 12.874A
OCP current 15.5A
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/+3.3V_ALW
+5V_ALW/+3.3V_ALW
+5V_ALW/+3.3V_ALW
LA-7782
LA-7782
LA-7782
54 66Friday, June 10, 2011
54 66Friday, June 10, 2011
54 66Friday, June 10, 2011
E
0.1
0.1
0.1
Page 55
5
4
3
2
1
1.5Volt +/- 5%
TDC 9.74A
Peak Current 13.915A
OCP current 16.698A
PJP200
+PWR_SRC
D D
+1.5V_MEN_P
C C
Mode Level +0.75V_P +V_DDR_REF
5 L off off
S
S3 L off on
B B
S0 H on on
Note: S3 - sleep ; S5 - power off
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
1
+
+
PC214
PC214
330U_SX_2VY~D
330U_SX_2VY~D
2
@
@
PJP200
1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D
1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D
1 2
1
+
+
PC208
PC208
330U_SX_2VY~D
330U_SX_2VY~D
2
PL200
PL200
1.5V_B+
12
PR203
PR203
@
@
12
PC200
PC200
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
12
PC209
@ PC209
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
SNUB_1.5V
12
4.7_1206_5%
4.7_1206_5%
PJP204
PU200
PU200
PAD
GND
PJP204
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
21
1
2
3
+V_DDR_REF
4
5
@ PR207
@
0_0402_5%~D
0_0402_5%~D
PR209
PR209
0_0402_5%~D
0_0402_5%~D
1 2
+1.5V_MEN_P
+1.5V_MEN_P
PR207
12
PR200
PR200
1 2
2.2_0603_5%~D
2.2_0603_5%~D
12
12
PC201
PC201
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
DDR_ON<41>
PC203
PC203
PC202
PC202
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1.5V_SUS_PWRGD<41>
PR206
PR206
0_0402_5%~D
0_0402_5%~D
1 2
5
PQ200
PQ200
123
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
5
PQ201
PQ201
213
SIR818DP-T1-GE3_POWERPAK8-5
SIR818DP-T1-GE3_POWERPAK8-5
12
@
@
+1.5V_MEN_P
1 2
4
+5V_ALW
4
+3.3V_ALW
PR204
PR204
100K_0402_1%~D
100K_0402_1%~D
PC212
PC212
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.75V_DDR_VTT_ON<40>
PC204
PC204
0.22U_0603_16V7K~D
0.22U_0603_16V7K~D
12
PR202
PR202
5.1_0603_5%~D
5.1_0603_5%~D
1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
PJP201
PJP201
2
112
JUMP_1x3m
JUMP_1x3m
PJP202
PJP202
2
112
JUMP_1x3m
JUMP_1x3m
PC210
PC210
0_0402_5%~D
0_0402_5%~D
1 2
BOOT_1.5V
DH_1.5V
SW_1.5V
DL_1.5V
15
LGATE
PR201
PR201
5.1K_0402_1%~D
5.1K_0402_1%~D
1 2
PC207
PC207
1U_0603_10V6K~D
1U_0603_10V6K~D
CS_1.5V
VDD_1.5V
14
PGND
13
CS
12
VDDP
11
VDD
+5V_ALW
1.5V_SUS_PWRGD
1M_0402_1%~D
1M_0402_1%~D
1 2
+1.5V_MEN_P
PR208
PR208
1.5V_B+
S5_1.5V
S3_1.5V
+1.5V_MEM +0.75V_DDR_VTT
17
16
PHASE
UGATE
RT8207MZQW_WQFN20_3X3
RT8207MZQW_WQFN20_3X3
PGOOD
TON
9
10
PR205
PR205
+0.75V_P
18
8
BOOT
S5
VLDOIN_1.5V
19
20
VLDOIN
VTTGND
VTTSNS
S3
6
7
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
VTT
VTTREF
VDDQ
FB
PJP203
PJP203
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
12
12
PC205
PC205
PC206
PC206
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
12
PC213
PC213
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
@
@
+0.75V_P
+V_DDR_REF
PC211
PC211
0.033U_0402_16V7~D
0.033U_0402_16V7~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.5V_MEN/+0.75V_DDR_VTT
+1.5V_MEN/+0.75V_DDR_VTT
+1.5V_MEN/+0.75V_DDR_VTT
LA-7782
LA-7782
LA-7782
55 66Friday, June 10, 2011
55 66Friday, June 10, 2011
55 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 56
A
B
C
D
1 1
PU300
PJP301
+3.3V_ALW
2 2
RUN_ON<28,36,40,43,64>
SIO_SLP_S3#<11,16,28,36,40,43>
PJP301
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
PR303 0_0402_5%@PR303 0_0402_5%@
PR306 0_0402_5%PR306 0_0402_5%
12
1 2
1 2
PC300
PC300
22U_0805_6.3VAM
22U_0805_6.3VAM
EN_1.8VSPEN_1.8VSP
1.8VSP_VIN
12
PC307
PC307
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PR304
@PR304
@
47K_0402_5%
47K_0402_5%
12
PU300
10
PVIN
9
PVIN
8
SVIN
5
EN
12
PC304
PC304
@
@
0.1U_0402_10V7K
0.1U_0402_10V7K
PR300
PR300
10K_0402_5%~D
10K_0402_5%~D
4
2
LX
PG
3
LX
6
FB
TP
NC
NC
7
1
11
SYN470DBC_DFN10_3X3
SYN470DBC_DFN10_3X3
12
1.8VSP_LX
1.8VSP_FB
+3.3V_RUN
1.8V_RUN_PWRGD <40>
PL301
PR301
PR301
@
@
4.7_0805_5%~D
4.7_0805_5%~D
PC305
PC305
@
@
680P_0603_50V7K
680P_0603_50V7K
PL301
1 2
20K_0402_1%
20K_0402_1%
10K_0402_1%
10K_0402_1%
PR302
PR302
PR305
PR305
1UH_PH041H-1R0MS_3.8A_20%
1UH_PH041H-1R0MS_3.8A_20%
12
SNUB_1.8VSP
12
12
12
12
PC301
PC301
12
22P_0402_50V8J
22P_0402_50V8J
PC302
PC302
<Vo=1.8V> VFB=0.6V
1.8Volt +/-5%
T
DC 0.85A
Peak Current 1.215A
OCP current 1.458A
+1.8V_RUNP
12
12
PC306
PC306
PC303
PC303
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
47P_0402_50V8J~D
47P_0402_50V8J~D
Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V
3 3
PJP300
PJP300
+1.8V_RUNP
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
+1.8V_RUN
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.8V_RUN
+1.8V_RUN
+1.8V_RUN
LA-7782
LA-7782
LA-7782
D
56 66Friday, June 10, 2011
56 66Friday, June 10, 2011
56 66Friday, June 10, 2011
0.1
0.1
0.1
Page 57
5
4
3
+V1.05SP_B+
2
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
PJP400
PJP400
1
+PWR_SRC
D D
PR402
PR402
60.4K_0402_1%
60.4K_0402_1%
1 2
PR403
PR403
0_0402_5%
SIO_SLP_A#<16,40,43>
0_0402_5%
1 2
S0 mode be high level
PC407
PC407
0.1U_0402_16V7K
C C
0.1U_0402_16V7K
1.05V_A_PWRGD<41>
12
@
@
+3.3V_ALW
PR400
PR400
100K_0402_1%~D
100K_0402_1%~D
TRIP_+V1.05SP
EN_+V1.05SP
FB_+V1.05SP
RF_+V1.05SP
12
PR405
PR405
470K_0402_1%
470K_0402_1%
12
PU400
PU400
1
2
3
4
5
4.99K_0402_1%
4.99K_0402_1%
VBST
PGOOD
TRIP
DRVH
EN
VFB
RF
TPS51212DSCR_SON10_3X3
TPS51212DSCR_SON10_3X3
PR406
PR406
SW
V5IN
DRVL
TP
12
10
9
8
7
6
11
BST_+V1.05SP
UG_+V1.05SP
SW_+V1.05SP
LG_+V1.05SP
12
PC405
PC405
1U_0603_6.3V6M
1U_0603_6.3V6M
PR401
PR401
2.2_0603_5%
2.2_0603_5%
1 2
+5V_ALW
PC404
PC404
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
PQ401
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
PQ401
PQ400
PQ400
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
3 5
241
12
@PR404
@
4.7_1206_5%
4.7_1206_5%
12
@PC408
@
1000P_0603_50V7K
1000P_0603_50V7K
12
PC402
PC402
PC401
PC401
0.1U_0402_25V6
0.1U_0402_25V6
PL400
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
PR404
PC408
PL400
1 2
12
12
2200P_0402_50V7K
2200P_0402_50V7K
12
PC403
PC403
PC400
PC400
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
+1.05V_MP
1
+
+
PC406
PC406
2
220U_D2_4VM
220U_D2_4VM
+1.05Volt +/- 5%
PJP401
PR407
PR407
10K_0402_1%
B B
10K_0402_1%
1 2
+1.05V_MP
PJP401
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
PJP402
PJP402
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
+1.05V_M
TDC 4.7A
Peak Current 6.5A
OCP current 7.8A
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.05V_M
+1.05V_M
+1.05V_M
LA-7782
LA-7782
LA-7782
57 66Friday, June 10, 2011
57 66Friday, June 10, 2011
57 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 58
5
4
3
+V1.05S_VCCPP_B+
2
PJP500
PJP500
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
1
+PWR_SRC
+3.3V_RUN
12
D D
1.05V_VTTPWRGD<41,59>
PR501
PR501
84.5K_0402_1%~D
84.5K_0402_1%~D
1 2
PR503
PR503
0_0402_5%
0_0402_5%
CPU_VTT_ON<40>
C C
1 2
@
@
PC506
PC506
0.1U_0402_16V7K
0.1U_0402_16V7K
12
TRIP_+V1.05S_VCCPP
EN_+V1.05S_VCCPP
FB_+V1.05S_VCCPP
RF_+V1.05S_VCCPP
12
PR505
PR505
470K_0402_1%
470K_0402_1%
PR500
PR500
100K_0402_5%
100K_0402_5%
1 2
PU500
PU500
1
PGOOD
2
TRIP
3
4
5
DRVH
EN
VFB
RF
TPS51212DSCR_SON10_3X3
TPS51212DSCR_SON10_3X3
VBST
SW
V5IN
DRVL
PQ500
PQ500
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
PR502
PR502
2.2_0603_5%
2.2_0603_5%
1 2
BST_+V1.05S_VCCPP
10
UG_+V1.05S_VCCPP
9
SW_+V1.05S_VCCPP
8
7
LG_+V1.05S_VCCPP
6
11
TP
PC504
PC504
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
+5V_ALW
12
PC505
PC505
1U_0603_6.3V6M
1U_0603_6.3V6M
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
PQ501
PQ501
3 5
241
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D
12
PR504
@PR504
@
4.7_1206_5%
4.7_1206_5%
12
PC508
@PC508
@
1000P_0603_50V7K
3 5
241
1000P_0603_50V7K
PC502
PC502
PC501
PC501
0.1U_0402_25V6
0.1U_0402_25V6
PL500
PL500
1 2
12
12
2200P_0402_50V7K
2200P_0402_50V7K
12
PC503
PC503
PC500
PC500
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
+1.05VTTP
1
+
12
@
@
PC510
PC510
.1U_0402_16V7K
.1U_0402_16V7K
+
PC507
PC507
2
220U_D2_4VM
220U_D2_4VM
Local sense put on HW site
PR507
PR507
4.32K_0402_1%
4.32K_0402_1%
B B
PR510
PR510
10K_0402_1%
10K_0402_1%
1 2
12
PR514
@PR514
@
10_0402_1%~D
10_0402_1%~D
A A
5
12
PR509
PR509
71.5K_0402_1%
71.5K_0402_1%
PQ502
PQ502
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
12
+3.3V_RUN
VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB)
PR511
PR511
10K_0402_5%
10K_0402_5%
13
D
D
2
G
G
S
S
PC509
PC509
@
@
.01U_0402_16V7K~D
.01U_0402_16V7K~D
1 2
12
+1.05VTTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)
VCCP_PWRCTRL <11>
PJP501
PJP501
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
PJP502
PJP502
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
3
From GPIO
+1.05V_RUN_VTT
VTT_SENSE_FB
VSSIO_SENSE_R_FB
2
PR508
PR508
0_0402_5%
0_0402_5%
PR513
PR513
0_0402_5%
0_0402_5%
12
12
VTT_SENSE <10>
VSSIO_SENSE_R <10>
+1.05Volt +/- 2%
TDC 6A
Peak Current 8.5A
OCP current 10.2A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
LA-7782
LA-7782
LA-7782
1
58 66Friday, June 10, 2011
58 66Friday, June 10, 2011
58 66Friday, June 10, 2011
0.1
0.1
0.1
Page 59
5
4
3
2
1
VID [0] VID[1] VCCSA Vout
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PR601
PR601
1K_0402_5%
D D
PR600
PR600
0_0402_5%
0_0402_5%
VCCSAPWROK<41>
12
+3.3V_RUN
12
PR603
PR603
100K_0402_5%
100K_0402_5%
+VCCSA_PWRGD+VCCSA_PWRGD
1K_0402_5%
PR602
PR602
0_0402_5%
0_0402_5%
1 2
PR604
PR604
0_0402_5%
0_0402_5%
1 2
PR605
PR605
1K_0402_5%
1K_0402_5%
12
VCCSA_VID_1 <11>
VCCSA_VID_0 <11>
12
+5V_ALW
PR607
PR610
@PR610
@
PR607
0_0402_5%
0_0402_5%
1 2
PR608
PR608
2.2_0603_1%
2.2_0603_1%
1 2
12
+VCCSA_BT_1+VCCSA_BT
12
PC604
@ PC604
@
1000P_0603_50V7K
1000P_0603_50V7K
12
PR609
PR609
@
@
4.7_0805_5%~D
4.7_0805_5%~D
1.05V_VTTPWRGD <41,58>
PC603
PC603
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
PL600
PL600
1 2
PC606
PC606
PC605
PC605
1 2
@
@
@
@
22U_0805_6.3V6M
22U_0805_6.3V6M
PR606
PR606
10_0402_1%
12
3300P_0402_50V7K
3300P_0402_50V7K
10_0402_1%
19
20
21
22
23
24
PC617
PC617
12
PU600
PU600
PGND
PGND
PGND
VIN
VIN
VIN
PC602
PC602
2.2U_0603_10V7K
2.2U_0603_10V7K
1 2
C C
PC613
PC613
PC614
PC614
1 2
10U_0805_25V6M
10U_0805_25V6M
0.1U_0603_25V7K
0.1U_0603_25V7K
GNDA_VCCSA
2
2
PC615
PC615
1
1
10U_0805_25V6M
10U_0805_25V6M
PC616
PC616
0.22U_0402_10V6K
0.22U_0402_10V6K
1
PC600
PC600
2
2200P_0402_50V7K
+3.3V_ALW
B B
PJP600
PJP600
1 2
PAD-OPEN 1x2m
PAD-OPEN 1x2m
2200P_0402_50V7K
+VCCSA_PWR_SRC +VCCSA_PWR_SRC
PC601
PC601
1 2
12
17
18
V5FILT
V5DRV
TPS51461RGER_QFN24_4X4~D
TPS51461RGER_QFN24_4X4~D
GND
VREF
1
2
12
PR613
PR613
5.1K_0402_1%~D
5.1K_0402_1%~D
1U_0603_10V6K
1U_0603_10V6K
15
16
VID1
PGOOD
COMP
SLEW
3
4
1 2
PC618
PC618
0.01U_0402_25V7K
0.01U_0402_25V7K
+VCCSA_EN
13
14
EN
VID0
12
BST
+VCCSA_PHASE
11
SW
10
SW
9
SW
8
SW
7
SW
25
TP
VOUT
MODE
5
6
33K_0402_5%
33K_0402_5%
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network
VCCSA
TDC 4.2A
Peak Current 6A
OCP current 7.2A
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2
12
PC607
PC607
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PR611
PR611
100_0402_5%
100_0402_5%
PR612
PR612
0_0402_5%
0_0402_5%
PC608
PC608
PC609
PC609
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
12
12
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
12
PC611
PC611
PC610
PC610
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_50V7K
2200P_0402_50V7K
VCCSA_SENSE <11>
PC612
PC612
1 2
+VCCSA_P
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
PJP601
PJP601
+VCCSA_P
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP602
PJP602
PAD-OPEN1x1m
PAD-OPEN1x1m
+VCC_SA
12
GNDA_VCCSA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+VCC_SA
+VCC_SA
ze Document Number Rev
+VCC_SA
LA-7782
LA-7782
LA-7782
59 66Friday, June 10, 2011
59 66Friday, June 10, 2011
1
59 66Friday, June 10, 2011
0.1
0.1
0.1
Page 60
5
Local sense put on HW site
VCC_AXG_SENSE<11>
VSS_AXG_SENSE<11>
D D
4
PC703
PC703
@
@
12
330P_0402_50V7K~D
330P_0402_50V7K~D
PC706
PC706
1 2
0.01U_0402_50V7K
0.01U_0402_50V7K
PR702
PR702
3.57K_0402_1%
3.57K_0402_1%
PR704
PR704
499_0402_1%~D
499_0402_1%~D
12
12
390P_0402_50V7K
390P_0402_50V7K
PC704
PC704
12
PR701
PR701
2K_0402_1%
2K_0402_1%
PR703
PR703
267K_0402_1%
267K_0402_1%
3
PC701
PC701
330P_0402_50V7K~D
330P_0402_50V7K~D
12
PC702
PC702
12
150P_0402_50V8F~D
150P_0402_50V8F~D
PC705
PC705
1 2
47P_0402_50V8J~D
47P_0402_50V8J~D
2
12
12
12
PR705
PR705
42.2K_0402_1%~D
42.2K_0402_1%~D
VCC_core
TDC 52A
Peak Current 94A
OCP current 116A
Load line -1.9mV/A
FSW=400kHz
1
VSUMG+<61>
12
12
PR707
PR707
2.61K_0402_1%
2.61K_0402_1%
12
PR709
PR709
PH700
PH700
VSUMG-<61>
PR714
PR714
1 2
3.83K_0402_1%
3.83K_0402_1%
C C
H_PROCHOT#<7,41,62>
+1.05V_RUN_VTT
PR739 54.9_0402_1%PR739 54.9_0402_1%
PR744 75_0402_5%@ PR744 75_0402_5%@
B B
PR746 130_0402_1%PR746 130_0402_1%
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
10KB_0402_5%_ERTJ0ER103J
10KB_0402_5%_ERTJ0ER103J
PC716
PC716
VSUMG-<61>
.1U_0402_16V7K
.1U_0402_16V7K
470K_0402_5%_ TSM0B474J4702RE
470K_0402_5%_ TSM0B474J4702RE
PR721
PR721
12
27.4K_0402_1%
27.4K_0402_1%
PR733
@PR733
@
1 2
0_0402_5%
0_0402_5%
SCLK
12
ALERT#
12
SDA
12
PC766
PC766
12
PH701
PH701
12
VIDSCLK<10>
VIDALERT_N<10>
VIDSOUT<10>
11K_0402_1%
11K_0402_1%
12
12
PC708
@ PC708
@
0.022U_0402_25V7K
0.022U_0402_25V7K
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
+5V_RUN
12
PC729
PC729
43P_0402_50V8J
43P_0402_50V8J
12
PC709
PC709
0.068U_0603_50V7K~D
0.068U_0603_50V7K~D
PC717
PC717
PC718
PC718
PR722 0_0402_5%PR722 0_0402_5%
PR726 0_0402_5%PR726 0_0402_5%
PR727 0_0402_5%PR727 0_0402_5%
PR730 0_0402_5%PR730 0_0402_5%
IMVP_VR_ON<40>
1.05V_0.8V_PWROK<14,41>
1 2
3.83K_0402_1%
3.83K_0402_1%
PC710
PC710
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
12
12
1 2
1 2
1 2
1 2
PR734
PR734
+5V_RUN
VSUM+
PR712
@PR712
@
649_0402_1%~D
649_0402_1%~D
1 2
PR713
PR713
348_0402_1%~D
348_0402_1%~D
1 2
ISEN1G<61>
ISEN2G<61>
PR715
@PR715
@
1 2
0_0402_5%
0_0402_5%
ALERT#
SDA
VR_HOT#
PR731 0_0402_5%@ PR731 0_0402_5%@
1 2
1 2
PR732 0_0402_5%PR732 0_0402_5%
470K_0402_5%_ TSM0B474J4702RE
470K_0402_5%_ TSM0B474J4702RE
PR736
PR736
27.4K_0402_1%
27.4K_0402_1%
COMP
PC734
PC734
PC736
PC736
VSUM-
PC738
PC738
12
ISEN1G
ISEN2G
NTCG
SCLK
VR_EN
NTC
12
PH702
PH702
12
@
@
PC730 10P_0402_25V8J
PC730 10P_0402_25V8J
12
PR741 0_0402_5%@ PR741 0_0402_5%@
1 2
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PC711
@PC711
@
3300P_0402_50V7K~D
3300P_0402_50V7K~D
PU700
PU700
1
ISUMPG
2
ISEN1G
3
ISEN2G
4
NTCG
5
SCLK
6
ALERT#
7
SDA
8
VR_HOT#
9
VR_ON
10
NTC
41
TP
40
11
ISEN3
12
12
0.01UF_0402_25V7K
0.01UF_0402_25V7K
PC746
PC746
@PR763
@
1 2
649_0402_1%~D
649_0402_1%~D
0.22U_0603_10V7K
0.22U_0603_10V7K
PR763
12
PC747
@ PC747
@
0.068U_0402_16V7K
0.068U_0402_16V7K
PR759
PR759
523_0402_1%
523_0402_1%
@
@
PC751
PC751
1 2
2200P_0402_25V7K~D
2200P_0402_25V7K~D
12
12
PR755
PR755
12
2.61K_0402_1%
2.61K_0402_1%
PR756 11K_0402_1%PR756 11K_0402_1%
PH703
PH703
VSUM-
12
PC750
A A
PC750
.1U_0402_16V7K
.1U_0402_16V7K
PC745
PC745
10KB_0402_5%_ERTJ0ER103J
10KB_0402_5%_ERTJ0ER103J
PR708
@PR708
@
IMVP_PWRGD
1 2
0_0402_5%
0_0402_5%
PWMG2 <61>
LGATE1G <61>
PHASE1G <61>
UGATE1G <61>
PGOODG
36
37
35
31
34
33
39
ISUMNG
ISEN2
32
38
FBG
RTNG
COMPG
PWM2G
PGOODG
LGATE1G
PHASE1G
UGATE1G
ISEN212FB17ISUMP14ISEN3/FB2
COMP
PGOOD
ISUMN
RTN16ISEN1
18
19
15
13
20
PGOOD
COMP
ISEN1
BOOT1G <61>
BOOT1G
30
BOOT2
29
UGATE2
28
PHASE2
27
LGATE2
26
VCCP
25
VDD
24
PWM3
23
LGATE1
22
PHASE1
21
UGATE1
BOOT1
ISL95836HRTZ-T_TQFN40_5X5~D
ISL95836HRTZ-T_TQFN40_5X5~D
BOOT1
PR735 0_0402_5%PR735 0_0402_5%
1 2
499_0402_1%~D
499_0402_1%~D
330P_0402_50V7K
330P_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
PR745
PR745
3.57K_0402_1%
3.57K_0402_1%
@
@
PC744
PC744
1 2
PC748
PC748
1 2
PR737 1.91K_0402_1%PR737 1.91K_0402_1%
PC732
PC732
390P_0402_50V7K
390P_0402_50V7K
12
PR749
PR749
12
12
12
Local sense put on HW site
PR710
PR710
BOOT2
UGATE2
PHASE2
LGATE2
VCCP
LGATE1
PHASE1
UGATE1
IMVP_PWRGD <40>
12
47P_0402_50V8J~D
47P_0402_50V8J~D
PR750
PR750
267K_0402_1%
267K_0402_1%
PR753
PR753
2K_0402_1%
2K_0402_1%
1 2
+5V_RUN
12
12
PC707
PC707
0_0603_5%
0_0603_5%
PWM3_1
12
PR716
PR716
PWM3
+3.3V_RUN
PC733
PC733
12
PC737
PC737
12
150P_0402_50V8F~D
150P_0402_50V8F~D
PC739
PC739
680P_0402_50V7K~D
680P_0402_50V7K~D
1 2
VCCSENSE <10>
VSSSENSE <10>
1U_0603_10V6K
1U_0603_10V6K
PU701
PU701
5
VCC
6
FCCM
2
PWM
3
GND
ISL6208CRZ-T_QFN8_3X3
ISL6208CRZ-T_QFN8_3X3
@PR718
@
0_0402_5%~D
0_0402_5%~D
1 2
0_0402_5%~D
0_0402_5%~D
12
PC720
PC720
1U_0603_10V6K
1U_0603_10V6K
5.76K_0402_1%
5.76K_0402_1%
12
1 2
BOOT
UGATE
PHASE
LGATE
PGND
PR718
1 2
0_0402_5%~D
0_0402_5%~D
1_0402_1%~D
1_0402_1%~D
12
PC721
PC721
1U_0603_10V6K
1U_0603_10V6K
PHASE2
BOOT2
LGATE2
PR751
PR751
BOOT1
4.7_0603_5%~D
4.7_0603_5%~D
LGATE1
4.7_0603_5%~D
4.7_0603_5%~D
BOOT3
1
8
7
4
9
+5V_RUN
PR723
PR723
PR728
PR728
12
UGATE2
PR738
PR738
4.7_0603_5%~D
4.7_0603_5%~D
UGATE1
PHASE1
PR758
PR758
12
PR711
PR711
12
PC712
PC712
0.22U_0603_16V7K
0.22U_0603_16V7K
UGATE3
PHASE3
LGATE3
1 2
12
PC731
PC731
0.22U_0603_16V7K
0.22U_0603_16V7K
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
1 2
PC749
PC749
0.22U_0603_16V7K
0.22U_0603_16V7K
PC774
PC774
@
@
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1 2
PQ703
PQ703
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
2
3
4
PC772
PC772
@
@
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PQ702
PQ702
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
2
3
4
PC773
PC773
@
@
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PQ701
PQ701
2
3
4
1 2
1
8
1
8
1
7
6
5
8
+VCC_PWR_SRC
12
12
PC713
PC713
PC714
PC714
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
7
6
5
PR719
PR719
@
@
4.7_1206_5%
4.7_1206_5%
+VCC_PWR_SRC
PC725
PC725
10U_0805_25V6K
10U_0805_25V6K
7
6
5
12
@
@
12
PR740
PR740
@
@
4.7_1206_5%
4.7_1206_5%
+VCC_PWR_SRC
12
PC741
PC741
PC740
PC740
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
12
@
@
12
PR760
PR760
@
@
4.7_1206_5%
4.7_1206_5%
PL706
@PL706
@
HCB4532KF-800T90_1812
HCB4532KF-800T90_1812
1 2
PJP700
PJP700
1 2
PAD-OPEN 1x3m
12
12
PC767
10U_0805_25V6K
10U_0805_25V6K
@
@
680P_0603_50V7K
680P_0603_50V7K
680P_0603_50V7K
680P_0603_50V7K
PC719
PC719
680P_0603_50V7K
680P_0603_50V7K
PC726
PC726
10U_0805_25V6K
10U_0805_25V6K
ISEN2
PC742
PC742
@
@
P1_SW
ISEN1
VSUM+
PC700
PC700
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
P3_SW
ISEN3
10K_0603_1%
10K_0603_1%
VSUM+
12
PC727
PC727
@
@
10U_0805_25V6K
10U_0805_25V6K
P2_SW
PR742
PR742
1 2
10K_0603_1%
10K_0603_1%
PR747
PR747
VSUM+
1 2
3.65K_0603_1%
3.65K_0603_1%
VSUM-
12
10U_0805_25V6K
10U_0805_25V6K
PR761
PR761
1 2
10K_0603_1%
10K_0603_1%
PR764
PR764
1 2
3.65K_0603_1%
3.65K_0603_1%
VSUM-
PC767
3.65K_0603_1%
3.65K_0603_1%
12
PC743
PC743
PC715
PC715
12
12
12
PC735
PC735
12
PC752
PC752
PAD-OPEN 1x3m
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PL703
PL703
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR720
PR720
1 2
PR725
PR725
1 2
VSUM-
PR729
PR729
1_0402_5%
1_0402_5%
12
12
12
PC728
PC728
PC768
PC768
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PL702
PL702
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR752
PR752
12
1_0402_5%
1_0402_5%
12
PC769
PC769
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PL701
PL701
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR766
PR766
12
1_0402_5%
1_0402_5%
12
1
+
+
PC722
PC722
2
12
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
+PWR_SRC
+VCC_CORE
PR717
@PR717
@
ISEN1
12
10K_0402_1%
10K_0402_1%
PR724
@PR724
@
ISEN2
12
10K_0402_1%
10K_0402_1%
1
+
+
PC724
PC724
PC723
PC723
2
100U_25V_M
100U_25V_M
100U_25V_M
100U_25V_M
+VCC_CORE
PR743
@PR743
@
ISEN1
12
10K_0402_1%
10K_0402_1%
PR748
@PR748
@
ISEN3
12
10K_0402_1%
10K_0402_1%
+VCC_CORE
PR762
@PR762
@
ISEN2
12
PR765
@PR765
@
ISEN3
12
1
+
+
2
100U_25V_M
100U_25V_M
Compal Electronics, Inc.
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Title
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-7782
LA-7782
LA-7782
60 66Friday, June 10, 2011
60 66Friday, June 10, 2011
60 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 61
5
+5V_RUN
D D
PWMG2<60>
C C
12
PR767
PR767
12
PC757
PC757
0_0603_5%
0_0603_5%
PU702
PU702
5
VCC
6
FCCM
2
PWM
3
GND
ISL6208CRZ-T_QFN8_3X3
ISL6208CRZ-T_QFN8_3X3
1U_0603_10V6K
1U_0603_10V6K
BOOT
UGATE
PHASE
LGATE
PGND
UGATE2G
PR768
PR768
4.7_0603_5%~D
4.7_0603_5%~D
BOOT2G
1
8
0.22U_0603_16V7K
0.22U_0603_16V7K
PHASE2G
7
LGATE2G
4
9
4
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
1 2
12
PC758
PC758
PC775
PC775
@
@
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PQ705
PQ705
3
PJP702
+GFX_PWR_SRC
12
@
@
10U_0805_25V6K
10U_0805_25V6K
PL705
PL705
PR771
PR771
3.65K_0603_1%
3.65K_0603_1%
12
PC755
PC755
PC756
PC756
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
VSUMG+ <60>
ISEN2G <60>
12
PC770
PC770
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
12
PC754
PC754
PC753
PC753
10U_0805_25V6K
10U_0805_25V6K
2
3
4
1
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
7
GP2_SW
6
5
PC759
PC759
@
8
@
PR769
PR769
@
@
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
12
12
12
PR770
PR770
680P_0603_50V7K
680P_0603_50V7K
4.7_1206_5%
4.7_1206_5%
10K_0603_1%
10K_0603_1%
12
PJP702
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PL707
@PL707
@
HCB4532KF-800T90_1812
HCB4532KF-800T90_1812
1 2
PR773 10K_0402_1%PR773 10K_0402_1%
+GFX_PWR_SRC
2
+VCC_PWR_SRC
+VCC_GFXCORE
PR772 1_0402_5%PR772 1_0402_5%
12
1 2
1
VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line -3.9mV/A
FSW=400kHz
VSUMG- <60>
ISEN1G <60>
12
12
PC761
PC761
PC760
PC760
10U_0805_25V6K
PQ704
PQ704
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
B B
PHASE1G<60>
BOOT1G<60>
A A
5
UGATE1G<60>
PC764
PC764
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
12
PR779
PR779
4.7_0603_5%~D
4.7_0603_5%~D
LGATE1G<60>
2
3
4
PC776
PC776
@
@
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
4
1
7
6
5
8
@
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GP1_SW
@
@
12
PC765
PC765
680P_0603_50V7K
680P_0603_50V7K
12
PR776
PR776
4.7_1206_5%
4.7_1206_5%
10U_0805_25V6K
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR777
PR777
10K_0603_1%
10K_0603_1%
1 2
1 2
ISEN1G<60>
3
10U_0805_25V6K
10U_0805_25V6K
PL704
PL704
PR774
PR774
3.65K_0603_1%
3.65K_0603_1%
PC762
PC762
@
@
VSUMG+ <60>
12
12
10U_0805_25V6K
10U_0805_25V6K
12
PC771
PC771
PC763
PC763
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+VCC_GFXCORE
12
PR775
PR775
PR778
PR778
1 2
1_0402_5%
1_0402_5%
10K_0402_1%
10K_0402_1%
ISEN2G <60>
VSUMG- <60>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
+VCC_GFXCORE
+VCC_GFXCORE
+VCC_GFXCORE
LA-7782
LA-7782
LA-7782
61 66Friday, June 10, 2011
61 66Friday, June 10, 2011
61 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 62
A
PD1300@
PD1300@
2 1
ES2AA-13-F
ES2AA-13-F
PQ1300
PQ1300
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
8
+DC_IN_SS
1 1
7
5
E2 AC_OK=17.7 Volt
PR1313
TI bq24745 = 316K
Intersil ISL88731 = 226K
Maxim = 383K
49.9K_0402_1%~D
49.9K_0402_1%~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
2 2
Vref
TI bq24747 = 3.3V
Intersil ISL88731C = 3.2V
VDDP
TI bq24747 = 6V
Intersil ISL88731C = 5.1V
GNDA_CHG
CHARGER_SMBCLK<41>
CHARGER_SMBDAT<41>
PR1317
PR1317
12
PC1307
PC1307
12
+5V_ALW
PC1316
PC1316
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+SDC_IN
PR1313
PR1313
1 2
226K_0402_1%~D
226K_0402_1%~D
GNDA_CHG
MAX8731A_LDO
ACAV_IN<22,41,63>
12
MAX8731_IINP<22>
1
2
36
4
PR1300
PR1300
1 2
0_0402_5%~D
0_0402_5%~D
MAX8731_REF
12
PR1311
PR1310
PR1310
PR1311
@
@
10K_0402_1%~D
10K_0402_1%~D
12
PR1316
PR1316
15.8K_0402_1%~D
15.8K_0402_1%~D
12
PR1329
PR1329
@
@
8.45K_0402_1%~D
8.45K_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
12
PC1323
PC1323
@
@
PR1325
PR1325
12
PC1324
PC1324
220P_0402_50V8J~D
220P_0402_50V8J~D
DC_BLOCK_GC <63>
+CHGR_DC_IN<63>
PR1320
PR1320
1 2
0_0402_5%~D
0_0402_5%~D
1 2
PR1323
@ PR1323
@
200K_0402_5%~D
200K_0402_5%~D
12
PC1321
@PC1321
@
4.7K_0402_5%~D
4.7K_0402_5%~D
120P_0402_50VNPO~D
120P_0402_50VNPO~D
1 2
12
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
+DOCK_PWR_BAR
+DC_IN_SS
PC1320
PC1320
@
@
12
PC1326
PC1326
PC1325
PC1325
@
@
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
CSS_GC<63>
BAT54CW_SOT323~D
BAT54CW_SOT323~D
Maximum charging current is 7.2A
3 3
4 4
DYN_TUR_CURRENT_SET#
90W
130W
DYN_TUR_CURRNT_SET#<41>
High
Low
PQ1309
PQ1309
RHU002N06_SOT323-3~D
RHU002N06_SOT323-3~D
+3.3V_ALW2
12
PR1341
PR1341
150K_0402_1%~D
150K_0402_1%~D
12
12
PR1349
PR1349
PR1350
PR1350
162K_0402_1%~D
162K_0402_1%~D
113K_0402_1%~D
113K_0402_1%~D
13
D
D
2
G
G
S
S
MAX8731_IINP
12
PC1341
PC1341
100P_0402_50V8J~D
100P_0402_50V8J~D
PR1343
PR1343
20K_0402_1%~D
20K_0402_1%~D
1 2
12
Adapter Protection Circuit for Turbo Mode
+5V_ALW
PC1340
PC1340
220P_0402_50V8J~D
220P_0402_50V8J~D
12
PC1336
PC1336
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
2
3
PR1309
@PR1309
@
1 2
1_0805_5%~D
1_0805_5%~D
@PC1318
@
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1 2
56P_0402_50V8~D
56P_0402_50V8~D
12
@
@
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12
PC1337
PC1337
@
@
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
3
2
B
PD1302
PD1302
GNDA_CHG
PC1318
12
12
PC1327
PC1327
1U_0603_10V6K~D
1U_0603_10V6K~D
8
P
+
-
G
4
+SDC_IN
PR1302
PR1302
1 2
0_0402_5%~D
0_0402_5%~D
1
PC1306
PC1306
0.1U_0805_50V7M~D
0.1U_0805_50V7M~D
12
MAX8731_IINP
PR1324
@PR1324
@
1 2
7.5K_0402_5%~D
7.5K_0402_5%~D
MAX8731_REF
PR1327
@ PR1327
@
1 2
10K_0402_5%~D
10K_0402_5%~D
@
@
GNDA_CHG
PR1340
PR1340
1.8M_0402_1%
1.8M_0402_1%
1 2
PU1303A
PU1303A
1
O
LM393DR_SO8~D
LM393DR_SO8~D
@
@
12
PC1300
PC1300
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PQ1302
PQ1302
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
PC1303
PC1303
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
GNDA_CHG
+DCIN
22
2
13
11
10
9
14
8
6
5
4
3
7
12
12
29
PC1328
PC1328
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+5V_ALW
PR1334
PR1334
1 2
221K_0402_1%~D
221K_0402_1%~D
2
PR1301
PR1301
0.01_1206_1%~D
0.01_1206_1%~D
4
3
13
D
D
2
G
G
S
S
CSSP_1
PR1303
PR1303
10K_0402_5%~D
10K_0402_5%~D
12
PR1304
PR1304
10_0402_5%~D
10_0402_5%~D
PC1304
PC1304
0.047U_0603_25V7M~D
0.047U_0603_25V7M~D
1 2
1
28
PU1300
PU1300
DCIN
CSSP
ICREF
ACIN
ACOK
VDDSMB
SCL
SDA
NC
VICM
FBO
EAI
EAO
VREF
CE
GND
TP
ISL88731C_QFN28_5X5~D
ISL88731C_QFN28_5X5~D
PR1339
PR1339
0_0402_5%~D
0_0402_5%~D
1 2
61
PQ1307A
PQ1307A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1
2
13
D
D
2
G
G
S
S
CSSN_1
12
12
PR1305
PR1305
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
27
ICOUT
CSSN
BOOT
VDDP
UGATE
PHASE
LGATE
PGND
CSOP
CSON
VFB
NC
GNDA_CHG
PQ1307B
PQ1307B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
10_0402_5%~D
10_0402_5%~D
PQ1301
PQ1301
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
NTGD4161PT1G_TSOP6~D
NTGD4161PT1G_TSOP6~D
S
S
12
PR1306
PR1306
100K_0402_1%~D
100K_0402_1%~D
PC1305
PC1305
1 2
GNDA_CHG
ICOUT
26
PR1318
PR1318
2.2_0603_1%~D
2.2_0603_1%~D
BOOT
1 2
25
MAX8731A_LDO
21
24
PR1322
PR1322
0_0603_5%~D
0_0603_5%~D
12
PC1317
@ PC1317
@
220P_0402_50V7K~D
220P_0402_50V7K~D
VFB
1 2
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
5
12
PR1328
PR1328
100_0402_5%~D
100_0402_5%~D
PJP1301
PJP1301
23
20
19
18
17
15
16
H_PROCHOT# <7,41,60>
3
4
+PWR_SRC
PQ1303A
PQ1303A
G
G
1
PR1307
PR1307
4.7_0603_5%~D
4.7_0603_5%~D
12
PC1310
PC1310
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
CHG_LGATE
BOOT_D
@
@
D
D
65
NTGD4161PT1G_TSOP6~D
NTGD4161PT1G_TSOP6~D
12
100K_0402_1%~D
100K_0402_1%~D
PR1319
PR1319
PD1301
PD1301
BAT54HT1G_SOD323-2~D
BAT54HT1G_SOD323-2~D
CHG_UGATE
+VCHGR_B
+VCHGR
PC1338
PC1338
100P_0402_50V8J~D
100P_0402_50V8J~D
C
PL1300
@ PL1300
@
1UH_PCMB053T-1R0MS_7A_20%
1UH_PCMB053T-1R0MS_7A_20%
12
12
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
PQ1303B
PQ1303B
S
S
G
G
3
1 2
PC1311
PC1311
1 2
MAX8731_REF
+DC_IN
PR1335
PR1335
PR1346
PR1346
1U_0603_10V6K~D
1U_0603_10V6K~D
232K_0402_1%~D
232K_0402_1%~D
22.6K_0402_1%~D
22.6K_0402_1%~D
12
PJP1300
PJP1300
D
D
42
PR1312
PR1312
0_0402_5%~D
0_0402_5%~D
1 2
12
PC1309
PC1309
1U_0603_10V6K~D
1U_0603_10V6K~D
GNDA_CHG
PC1319
PC1319
@
@
PQ1305
PQ1305
12
12
PR1336
PR1336
47K_0402_1%~D
47K_0402_1%~D
12
12
PR1347
PR1347
42.2K_0402_1%~D
42.2K_0402_1%~D
+3.3V_ALW
5
PU1302
PU1302
4
O
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
12
PC1301
PC1301
PC1302
PC1302
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
47P_0402_50V8J~D
47P_0402_50V8J~D
DOCK_DCIN_IS+ <39>
DOCK_DCIN_IS- <39>
DK_CSS_GC <63>
5
PQ1304
PQ1304
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
4
123
12
3300P_0402_50V7K~D
3300P_0402_50V7K~D
5
4
123
SI7716ADN-T1-GE3_POWERPAK8-5
SI7716ADN-T1-GE3_POWERPAK8-5
1M_0402_1%~D
1M_0402_1%~D
1 2
+5V_ALW
5
6
12
PC1339
PC1339
100P_0402_50V8J~D
100P_0402_50V8J~D
PC1342
PC1342
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
12
1
P
B
2
PROCHOT_GATE <40>
A
G
To preset system to throtlle
switching from AC to DC
CHAGER_SRC
12
PL1301
12
PC1322
PC1322
1000P_0603_50V7K~D
1000P_0603_50V7K~D
PR1332
PR1332
4.7_1206_5%~D
4.7_1206_5%~D
1 2
PU1303B
PU1303B
P
7
O
G
LM393DR_SO8~D
LM393DR_SO8~D
PR1351
PR1351
100K_0402_5%~D
100K_0402_5%~D
PL1301
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
GNDA_CHG
+3.3V_ALW
12
13
D
D
S
S
PC1333
@PC1333
@
1 2
2
G
G
PQ1306
PQ1306
RHU002N06_SOT323-3~D
RHU002N06_SOT323-3~D
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
PR1333
PR1333
8
+
-
4
12
PC1312
PC1312
PC1313
PC1313
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PR1326
PR1326
0.01_1206_1%~D
0.01_1206_1%~D
+VCHGR_L
4
12
3
12
PR1330
PR1330
10_0402_5%~D
10_0402_5%~D
PC1334
PC1334
1 2
0.22U_0603_25V7K~D
0.22U_0603_25V7K~D
MAX8731_REF
12
PR1338
PR1338
10K_0402_1%~D
10K_0402_1%~D
12
PR1348
PR1348
@
@
41.2K_0402_1%~D
41.2K_0402_1%~D
ACAV_IN <22,41,63>
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
2
PR1331
PR1331
PR1342
PR1342
0_0402_5%~D
0_0402_5%~D
1 2
12
PC1314
PC1314
10U_1206_25V6M~D
10U_1206_25V6M~D
12
0_0402_5%~D
0_0402_5%~D
PC1329
PC1329
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC1335
@PC1335
@
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
D
12
PC1315
PC1315
10U_1206_25V6M~D
10U_1206_25V6M~D
+VCHGR
12
12
PC1330
PC1330
10U_1206_25V6M~D
10U_1206_25V6M~D
GNDA_CHG
ACAV_IN_NB <40,41,63>
12
12
PC1331
PC1331
PC1332
PC1332
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Charger
Charger
ze Document Number Rev
Charger
LA-7782
LA-7782
LA-7782
D
62 66Friday, June 10, 2011
62 66Friday, June 10, 2011
62 66Friday, June 10, 2011
0.1
0.1
0.1
Page 63
5
+3.3V_ALW2
PC915
PC915
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
ACAV_IN<22,41,62>
CHARGE_MODULE_BATT<40>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
D D
PQ909
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
MODULE_BATT_PRES#<40,53>
CHARGE_PBATT<40>
C C
PBAT_PRES#<40,53>
B B
A A
SLICE_BAT_PRES#<39,40>
PQ909
+3.3V_ALW2
PC916
PC916
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
PU901
PU901
ACAV_IN<22,41,62>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PQ916
PQ916
2
G
G
DEFAULT_OVRDE<40>
12
PD917
PD917
PD916
PD916
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
2
G
G
1
2
13
SLICE_BAT_ON<40>
12
0_0402_5%~D
0_0402_5%~D
1
2
13
D
D
S
S
5
P
B
A
G
3
D
D
S
S
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PR961
PR961
1 2
5
B
A
O
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
+VCHGR
5
PU902
PU902
P
4
O
G
3
12
PR908
PR908
10K_0402_5%~D
10K_0402_5%~D
+VCHGR
4
PR915
PR915
@
@
1 2
100K_0402_5%~D
100K_0402_5%~D
12
PR920
PR920
10K_0402_5%~D
10K_0402_5%~D
2
1 2
PR935 0_0402_5%~DPR935 0_0402_5%~D
+3.3V_ALW2
PQ915
PQ915
FDN338P_G_NL_SOT23-3~D
FDN338P_G_NL_SOT23-3~D
1
3
1
3
1 3
2
2
2
12
PC914
PC914
1500P_0402_7K~D
1500P_0402_7K~D
12
PR900
PR900
PC900
PC900
@
@
1 2
100K_0402_5%~D
100K_0402_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PR906
PR906
10K_0402_5%~D
10K_0402_5%~D
61
PQ904A
PQ904A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
12
PC904
PC904
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PR919
PR919
10K_0402_5%~D
10K_0402_5%~D
61
PQ910A
PQ910A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR926
PR926
0_0402_5%~D
0_0402_5%~D
1 2
PBATT+
PR931
PR931
200K_0402_1%~D
200K_0402_1%~D
2
12
PR938
PR938
@
@
499K_0402_1%~D
499K_0402_1%~D
+DC_IN
1 2
PR946 100K_0402_5%~DPR946 100K_0402_5%~D
ACAV_DOCK_SRC#<39>
+SDC_IN
ACAV_IN<22,41,62>
+3.3V_ALW2
DOCK_SMB_ALERT# <39,40>
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
PQ913
PQ913
8
7
5
4
3
5
PQ908B
PQ908B
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PD910
PD910
1 2
12
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
61
PQ907A
PQ907A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
PR944 47_0805_5%~DPR944 47_0805_5%~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
SOFT_START_GC<53>
1 2
PR951 0_0402_5%~DPR951 0_0402_5%~D
DC_BLOCK_GC<62>
1 2
PR955 0_0402_5%~DPR955 0_0402_5%~D
1 2
PR957 0_0402_5%~DPR957 0_0402_5%~D
PQ900
PQ900
4
1 2
61
PQ908A
PQ908A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
3
5
4
PR936
PR936
1 2
0_0402_5%~D
0_0402_5%~D
PBAT_PRES#<40,53>
PC910
PC910
1 2
PR948 0_0402_5%~DPR948 0_0402_5%~D
8
7
5
PR916
PR916
20K_0402_1%~D
20K_0402_1%~D
2
PD911
PD911
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PQ907B
PQ907B
SLICE_BAT_PRES#<39,40>
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
+DOCK_PWR_BAR
+DC_IN_SS
+CHGR_DC_IN<62>
CD3301_DCIN
12
ACAVDK_SRC
12
PC911
PC911
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
ERC1
2
PD912
PD912
PR932
PR932
4
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
0_0402_5%~D
0_0402_5%~D
4
1 2
61
1 2
12
ACAVIN
P33ALW2
PR921
PR921
20K_0402_1%~D
20K_0402_1%~D
PQ906A
PQ906A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PD913
PD913
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
1 2
PR939 0_0402_5%~DPR939 0_0402_5%~D
1 2
PR940 0_0402_5%~DPR940 0_0402_5%~D
1 2
PR943 0_0402_5%~DPR943 0_0402_5%~D
PU900
PU900
1
DC_IN
2
SS_GC
3
ERC1
4
ACAVDK_SRC
5
GND
6
SDC_IN
7
DC_BLK_GC
8
ACAV_IN
9
P33ALW2
37
TP
CSS_GC<62>
DK_CSS_GC<62>
PC912
PC912
3
MPBATT+
12
12
PR903
PR903
PR904
PR904
390K_0402_5%~D
390K_0402_5%~D
620K_0402_5%~D
620K_0402_5%~D
3
12
5
PR909
PR909
390K_0402_5%~D
390K_0402_5%~D
PBATT+
12
PR913
PR913
390K_0402_5%~D
390K_0402_5%~D
12
PR922
PR922
3
PR925
PR925
5
1 2
PQ906B
PQ906B
0_0402_5%~D
0_0402_5%~D
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PQ905B
PQ905B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PD915
PD915
1 2
3
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
5
4
PR937
PR937
0_0402_5%~D
0_0402_5%~D
1 2
CHGVR_DCIN
DK_PWRBAR
DC_IN_SS
35
36
34
NC
DC_IN_SS
CHARGERVR_DCIN
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
ERC2
ERC3
PC913
PC913
@
@
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
MPBATT+
12
PR933
PR933
PR934 100K_0402_5%~D@PR934 100K_0402_5%~D@
510K_0402_5%~D
510K_0402_5%~D
MODULE_BATT_PRES# <40,53>
1 2
33
32
28
29
31
30
NC
GND
PBatt+
DK_PWRBAR
BLK_MOSFET_GC
DK_AC_OFF_EN
ACAV_IN_NB
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
SS_DCBLK_GC
EN_DK_PWRBAR17P33ALW
16
15
18
P33ALW
EN_DK_PWRBAR
12
STSTART_DCBLOCK_GC
3301_PWRSRC
1 2
12
0.047U_0603_25V7K~D
0.047U_0603_25V7K~D
12
PR914
PR914
620K_0402_5%~D
620K_0402_5%~D
3
5
4
390K_0402_5%~D
390K_0402_5%~D
MODULE_ON <40>
1 2
PBATT+
PR941
PR941
0_0402_5%~D
0_0402_5%~D
P50ALW
PBATT_OFF
GND
CD3301RHHR_QFN36_6X6~D
CD3301RHHR_QFN36_6X6~D
1 2
PR959 0_0402_5%~DPR959 0_0402_5%~D
PR960 0_0402_5%~DPR960 0_0402_5%~D
1 2
PR963 0_0402_5%~DPR963 0_0402_5%~D
4
820_0603_1%~D
820_0603_1%~D
1 2
PQ910B
PQ910B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
27
26
25
24
23
22
21
20
19
1 2
1
S
2
S
3
S
4
G
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
PQ901
PQ901
PR905
PR905
820_0603_1%~D
820_0603_1%~D
1 2
12
PC903
PC903
0.01U_0603_25V7K~D
61
PQ905A
PQ905A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
P50ALW
CD_PBATT_OFF
0.01U_0603_25V7K~D
PQ912
PQ912
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
1
S
2
S
3
S
4
G
12
PC907
PC907
0.01U_0603_25V7K~D
0.01U_0603_25V7K~D
2
12
PR928
PR928
@
@
499K_0402_1%~D
499K_0402_1%~D
1 2
PR945 0_0402_5%~DPR945 0_0402_5%~D
1 2
PR947 0_0402_5%~DPR947 0_0402_5%~D
1 2
PR949 0_0402_5%~DPR949 0_0402_5%~D
3301_ACAV_IN_NB
DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#
+3.3V_ALW
EN_DOCK_PWR_BAR <40>
1 2
1M_0402_5%~D
1M_0402_5%~D
@
@
+PWR_SRC
3
PR962
PR962
D
D
D
D
PQ904B
PQ904B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR917
PR917
DK_AC_OFF
8
D
7
D
6
D
5
D
MPBATT_IN_SS
8
7
PBATT_IN_SS
6
5
DEFAULT_OVRDE<40>
12
PR923
PR923
10K_0402_5%~D
10K_0402_5%~D
PQ911
PQ911
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
13
D
D
2
G
G
S
S
+5V_ALW
1 2
PR953 0_0402_5%~DPR953 0_0402_5%~D
BLKNG_MOSFET_GC
1 2
PR956 0_0402_5%~DPR956 0_0402_5%~D
1 2
PR958 0_0402_5%~DPR958 0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PR901
PR901
330K_0402_5%~D
330K_0402_5%~D
1 2
PR912
PR912
330K_0402_5%~D
330K_0402_5%~D
1 2
ACAV_IN <22,41,62>
SLICE_BAT_ON <40>
DOCK_AC_OFF <39,40>
1 2
PR954 0_0402_5%~DPR954 0_0402_5%~D
SLICE_BAT_PRES# <39,40>
+NBDOCK_DC_IN_SS
ACAV_IN_NB <40,41,62>
2
2
3
PQ902
PQ902
8
D
7
D
6
D
5
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
PD903
PD903
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PD904
PD904
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PD905
PD905
2
3
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
PQ914
PQ914
8
D
7
D
6
D
5
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
PD907
PD907
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PD908
PD908
RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
1M_0402_5%~D
DOCK_AC_OFF_EC <40>
1M_0402_5%~D
2
PD901
PD901
1
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
1
S
2
S
3
S
4
G
12
12
12
PR910
PR910
499K_0402_1%~D
499K_0402_1%~D
1
1
S
2
S
3
S
4
G
12
12
12
PR924
PR924
499K_0402_1%~D
499K_0402_1%~D
1 2
PR952
PR952
1
ES2AA-13-F SMA
ES2AA-13-F SMA
PD902
PD902
2 1
PQ903
PQ903
1
8
S
D
2
7
S
D
3
+DOCK_PWR_BAR
PR942
@PR942
@
0_0402_5%~D
0_0402_5%~D
1 2
6
D
5
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
PR907
PR907
330K_0402_5%~D
330K_0402_5%~D
1 2
S
4
G
PR911
PR911
0_0402_5%~D
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Selector
Selector
ze Document Number Rev
Selector
LA-7782
LA-7782
LA-7782
1
12
PC902
PC902
0.47U_0805_25V7K~D
0.47U_0805_25V7K~D
1 2
STSTART_DCBLOCK_GC
+PWR_SRC
12
12
PC906
PC906
PC905
PC905
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1
0.1
63 66Friday, June 10, 2011
63 66Friday, June 10, 2011
63 66Friday, June 10, 2011
0.1
Page 64
8
H H
DGPU_PWR_EN<40,45>
RUN_ON<28,36,40,43,56>
GNDA_GPU_CORE
PR1004
G G
GNDA_GPU_CORE
+3.3V_RUN
PR1017
PR1017
0_0402_5%
0_0402_5%
GPU_HOT#<45>
1 2
249K_0402_1%
249K_0402_1%
PC1015
PC1015
1 2
GNDA_GPU_CORE
PR1046
PR1046
1.4K_0402_1%
1.4K_0402_1%
12
12
12
PR1024
PR1024
6.81K_0402_1%~D
6.81K_0402_1%~D
PC1013
PC1013
47P_0402_50V8J~D
47P_0402_50V8J~D
1 2
1 2
1 2
324K_0402_1%~D
324K_0402_1%~D
+GPU_CORE
GPU_VDD_SENSE<46>
GPU_VSS_SENSE<46>
PR1028
PR1028
DGPU_PWROK
F F
GNDA_GPU_CORE
E E
PR1023
@ PR1023
@
D D
150P_0402_50V8J
150P_0402_50V8J
C C
B B
PR1004
10K_0402_1%
10K_0402_1%
1 2
PR1010
PR1010
1.91K_0402_1%
1.91K_0402_1%
1 2
12
PR1013
PR1013
1.91K_0402_1%
1.91K_0402_1%
PR1019
PR1019
100K_0402_5%
100K_0402_5%
1 2
PH1001
PH1001
PR1025
PR1025
499_0402_1%~D
499_0402_1%~D
1 2
PR1027
PR1027
3.57K_0402_1%
3.57K_0402_1%
1 2
ISEN2_VGA
ISEN1_VGA
12
PR1030
PR1030
249K_0402_1%
249K_0402_1%
1 2
PR1020
PR1020
47K_0402_1%~D
47K_0402_1%~D
1 2
PC1009
@PC1009
@
22P_0402_50V8J
22P_0402_50V8J
PC1012
PC1012
1 2
470P_0402_50V8J~D
470P_0402_50V8J~D
1 2
PR1032
PR1032
10_0402_5%
10_0402_5%
1 2
PR1036
PR1036
0_0402_5%
0_0402_5%
PR1043
PR1043
0_0402_5%
0_0402_5%
1 2
PR1044
PR1044
10_0402_5%
10_0402_5%
1 2
VSUM-_VGA
+3.3V_RUN
PR1050
@PR1050
@
0_0402_5%
0_0402_5%
470K_0402_5%_TSM0B474J4702RE
470K_0402_5%_TSM0B474J4702RE
1 2
PC1011
PC1011
1000P_0402_50V7K
1000P_0402_50V7K
GNDA_GPU_CORE GNDA_GPU_CORE
GNDA_GPU_CORE
7
Initial voltage is 0.975V
PR1056 10K_0402_1%
PR1056 10K_0402_1%
1 2
PR1057 10K_0402_1%@ PR1057 10K_0402_1%@
1 2
PR1054 10K_0402_1%
GPU_VID6
GPU_VID5
39
37
38
VR_ON
CLK_EN#
DPRSLPVR
ISEN111VSEN12RTN13ISUM-14ISUM+15VDD
12
12
PR1054 10K_0402_1%
1 2
PR1058 10K_0402_1%@ PR1058 10K_0402_1%@
1 2
PR1052 10K_0402_1%
PR1052 10K_0402_1%
1 2
PR1059 10K_0402_1%@ PR1059 10K_0402_1%@
1 2
GPU_VID3
GPU_VID4
GPU_VID1
GPU_VID0
GPU_VID2
35
VID031VID132VID233VID334VID536VID6
VID4
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
VIN
IMON18BOOT119UGATE1
ISL62883CHRTZ-T_TQFN40_5X5
ISL62883CHRTZ-T_TQFN40_5X5
17
16
20
12
12
PC1018
PC1018
1U_0603_10V6K
1U_0603_10V6K
PR1033
PR1033
@
@
82.5_0402_5%
82.5_0402_5%
PC1026
PC1026
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
PR1045
PR1045
953_0402_1%
953_0402_1%
1 2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1K_0402_1%~D
1K_0402_1%~D
PC1019
PC1019
PR1000
PR1000
10K_0402_1%
10K_0402_1%
1 2
PR1001
@PR1001
@
10K_0402_1%
10K_0402_1%
1 2
PC1004
PC1004
22P_0402_50V8J
22P_0402_50V8J
1 2
CLK_ENABLE#_VGA
12
GNDA_GPU_CORE
12
PC1016
PC1016
0.22U_0402_10V4Z
0.22U_0402_10V4Z
PC1025
PC1025
330P_0402_50V7K
330P_0402_50V7K
PC1031
PC1031
1000P_0402_50V7K
1000P_0402_50V7K
40
PU1000
PU1000
1
PGOOD
2
PSI#
3
RBIAS
4
VR_TT#
5
NTC
6
VW
7
COMP
8
FB
9
ISEN3
10
ISEN2
41
AGND
12
PC1017
PC1017
0.22U_0402_10V4Z
0.22U_0402_10V4Z
12
12
PR1002
PR1002
PR1005
PR1005
PR1006
PR1006
PR1011
PR1011
PR1014
PR1014
PR1016
PR1016
PR1018
PR1018
30
29
28
27
26
25
24
23
22
21
1 2
PR1026
PR1026
0_0402_5%
0_0402_5%
1 2
PR1029
PR1029
0_0402_5%
0_0402_5%
1 2
PR1031
PR1031
1_0402_5%
1_0402_5%
0.22U_0603_25V7K
0.22U_0603_25V7K
PC1027
PC1027
0.068U_0603_50V7K~D
0.068U_0603_50V7K~D
12
12
12
12
12
12
12
12
12
6
PR1022 0_0402_5%PR1022 0_0402_5%
1 2
PC1010
PC1010
1U_0603_10V6K
1U_0603_10V6K
+5V_RUN
+VGA_B+
+5V_RUN
12
PC1028
PC1028
0.1U_0402_16V7K
0.1U_0402_16V7K
PR1035
PR1035
12
PR1041
PR1041
11K_0402_1%
11K_0402_1%
PR1060 10K_0402_1%@ PR1060 10K_0402_1%@
1 2
PR1051 10K_0402_1%
PR1051 10K_0402_1%
1 2
PR1061 10K_0402_1%@ PR1061 10K_0402_1%@
1 2
PR1049 10K_0402_1%
PR1049 10K_0402_1%
1 2
PR1062 10K_0402_1%@ PR1062 10K_0402_1%@
1 2
PR1047 10K_0402_1%
PR1047 10K_0402_1%
1 2
BOOT2_VGA BOOT2_2_VGA
GPU_VID_6 <45>
GPU_VID_5 <45>
GPU_VID_4 <45>
GPU_VID_3 <45>
GPU_VID_2 <45>
GPU_VID_1 <45>
1 2
PR1021
PR1021
0_0402_5%
0_0402_5%
VSUM+_VGA
12
2.61K_0402_1%
2.61K_0402_1%
12
PH1000
PH1000
10K_0402_1%_TSM0A103F34D1RZ
10K_0402_1%_TSM0A103F34D1RZ
Layout Note:
Place near Phase1 Choke
VSUM-_VGA
5
+3.3V_RUN_GFX
+5V_RUN
BOOT1_VGA
PR1003
PR1003
4.7_0603_5%~D
4.7_0603_5%~D
UGATE1_VGA
4.7_0603_5%~D
4.7_0603_5%~D
PHASE1_VGA
LGATE1_VGA
12
PR1034
PR1034
UGATE2_VGA
PHASE2_VGA
LGATE2_VGA
BOOT1_1_VGA
12
PC1005
PC1005
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
PC1024
PC1024
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
4
PQ1001
PQ1001
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
2
3
4
12
PC1008
@ PC1008
@
2200P_0402_50V7K
2200P_0402_50V7K
2
3
4
12
PC1014
@ PC1014
@
2200P_0402_50V7K
2200P_0402_50V7K
3
1
7
6
5
8
PQ1000
PQ1000
CSD87351Q5D_SON8~D
CSD87351Q5D_SON8~D
1
7
6
5
8
@
@
+VGA_B+
PC1007
PC1007
1000P_0603_50V7K
1000P_0603_50V7K
12
PC1001
PC1001
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
12
@PR1007
@
2.2_1206_5%
2.2_1206_5%
PC1020
PC1020
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PC1032
PC1032
@
@
1000P_0603_50V7K
1000P_0603_50V7K
PC1002
PC1002
P2_VGA_SW
VSUM+_VGA
PR1007
12
PC1021
PC1021
P1_VGA_SW
12
12
@PR1037
@
2.2_1206_5%
2.2_1206_5%
12
12
PC1003
PC1003
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2200P_0402_50V7K
12
12
PR1008
PR1008
3.65K_0402_1%
3.65K_0402_1%
ISEN2_VGA
+GPU_CORE
TDC 35A
Peak Current 42A
OCP current 51A
No Load line
FSW=400kHz
12
PC1022
PC1022
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
12
PR1038
PR1038
3.65K_0402_1%
3.65K_0402_1%
VSUM+_VGA
PR1037
2
2
12
PC1000
PC1000
10U_1206_25V6M
10U_1206_25V6M
PL1000
PL1000
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
PR1012
PR1012
10K_0402_1%~D
10K_0402_1%~D
10K_0402_1%~D
10K_0402_1%~D
+VGA_B+
12
PC1023
PC1023
10U_1206_25V6M
10U_1206_25V6M
12
PR1039
PR1039
ISEN1_VGA
12
PR1015
PR1015
+GPU_CORE
1 2
12
PL1001
PL1001
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
10K_0402_1%~D
10K_0402_1%~D
10K_0402_1%~D
10K_0402_1%~D
1 2
PR1042
PR1042
12
+GPU_CORE
PJP1000
PJP1000
JUMP_1X3m
JUMP_1X3m
VSUM-_VGA
112
12
VSUM-_VGA
PR1009
PR1009
1_0402_5%
1_0402_5%
12
PR1040
PR1040
1_0402_5%
1_0402_5%
1
+PWR_SRC
+GPU_CORE
1
+
+
PC1006
PC1006
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
+GPU_CORE
1
1
+
+
+
+
PC1030
PC1030
PC1029
PC1029
2
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
12
PC1033
PC1033
0.1U_0402_16V7K
PJP1004
PJP1004
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
A A
GNDA_GPU_CORE
8
7
0.1U_0402_16V7K
GNDA_GPU_CORE
6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
Compal Electronics, Inc.
+GPU_CORE
+GPU_CORE
ze Document Number Rev
+GPU_CORE
LA-7782
LA-7782
LA-7782
64 66Friday, June 10, 2011
64 66Friday, June 10, 2011
64 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 65
5
4
3
2
1
+VCC_CORE
1
PC1100
PC1100
10U_0805_4VAM
10U_0805_4VAM
2
D D
1
PC1105
PC1105
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1101
PC1101
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1106
PC1106
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1102
PC1102
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1107
PC1107
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1103
PC1103
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1108
PC1108
10U_0805_4VAM
10U_0805_4VAM
2
+VCC_CORE +VCC_GFXCORE
1
PC1104
PC1104
10U_0805_4VAM
10U_0805_4VAM
2
1
PC1109
PC1109
10U_0805_4VAM
10U_0805_4VAM
2
+VCC_GFXCORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1112
PC1112
PC1111
PC1111
1
1
2
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1113
PC1113
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1114
PC1114
1
1
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1115
PC1115
PC1116
PC1116
1
2
22U_0805_6.3V6M
PC1118
PC1118
1
1
PC1117
PC1117
2
2
+VCC_CORE
1
PC1119
PC1119
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1143
PC1143
22U_0805_6.3VAM
22U_0805_6.3VAM
2
C C
1
PC1160
PC1160
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1168
PC1168
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1120
PC1120
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1144
PC1144
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1161
PC1161
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1121
PC1121
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1145
PC1145
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1162
PC1162
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
+
+
PC1172
PC1172
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
PC1122
PC1122
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1146
PC1146
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1163
PC1163
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
2
1
+
+
+
+
PC1174
PC1174
PC1173
PC1173
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
PC1123
PC1123
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1153
PC1153
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
PC1164
PC1164
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
1
+
+
+
+
2
PC1187
PC1187
PC1175
PC1175
2
@
@
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC1135
PC1135
PC1136
1
2
1
+
+
2
PC1136
1
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
PC1156
PC1156
+
+
2
22U_0805_6.3V6M
PC1137
PC1137
PC1138
1
2
PC1157
PC1157
PC1138
1
2
Below is 458544_CRV_PDDG_0.5 Table 5-8.
5 x 22 µF (0805)
Socket Bottom
5 x (0805) no-stuff
sites
7 x 22 µF (0805)
Socket Top
2 x (0805) no-stuff
sites
+1.05V_RUN_VTT
PC1126
PC1126
22U_0805_6.3VAM
22U_0805_6.3VAM
1
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
2
+1.05V_RUN_VTT
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
PC1127
PC1127
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
PC1147
PC1147
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
PC1129
PC1129
PC1128
PC1128
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
PC1149
PC1149
PC1148
PC1148
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
@
@
1
1
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
2
1
PC1131
PC1131
PC1130
PC1130
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
@
@
PC1150
PC1150
PC1151
PC1151
2
2
1
+
+
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
PC1124
PC1124
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
@
@
PC1125
PC1125
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
@
@
PC1132
PC1132
22U_0805_6.3VAM
22U_0805_6.3VAM
PC1152
PC1152
330U_X_2VM_R6M
330U_X_2VM_R6M
PC1165
PC1165
22U_0805_6.3VAM
22U_0805_6.3VAM
@
@
1
1
PC1133
PC1133
PC1134
PC1134
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PC1154
PC1154
PC1155
PC1155
2
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
PC1166
PC1166
+
+
2
B B
+GPU_CORE (place under GPU) +GPU_CORE (place near GPU)
+GPU_CORE +GPU_CORE
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1176
PC1176
PC1177
12
A A
12
PC1177
12
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
12
PC1190
PC1190
PC1189
PC1189
5
4.7U_0603_6.3V6K~D
PC1178
PC1178
PC1179
12
12
PC1179
12
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
12
PC1191
PC1191
PC1192
PC1192
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1181
PC1181
PC1180
PC1180
12
12
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
@
@
@
12
@
12
PC1193
PC1193
PC1209
PC1209
4.7U_0603_6.3V6K~D
PC1182
PC1182
12
12
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
@
@
12
12
PC1210
PC1210
+GPU_CORE +GPU_CORE
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
@
@
PC1183
PC1183
PC1184
PC1184
12
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
@
@
@
@
PC1211
PC1211
PC1194
PC1194
12
4.7U_0603_6.3V6K~D
@
@
PC1185
PC1185
PC1186
12
12
PC1186
12
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1195
PC1195
12
4
@
@
@
@
PC1197
PC1197
PC1196
PC1196
12
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22U_0805_6.3V6M
22U_0805_6.3V6M
47U_0805_6.3V6M~D
47U_0805_6.3V6M~D
PC1213
PC1213
PC1212
PC1212
12
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1214
PC1214
12
3
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1216
PC1216
PC1215
PC1215
12
12
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
PC1218
PC1218
PC1217
PC1217
12
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-7782
LA-7782
LA-7782
65 66Friday, June 10, 2011
65 66Friday, June 10, 2011
65 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 66
5
R e qu e st
R e qu e st
Ite m
Ite m Issu e D escr ip tion
Ite mIte m
D D
C C
P a ge# T it le
P a ge#P ag e#
Title
TitleTit le
D ate
D ateD ate
R e qu e stRequ est
O w ner
O w ner
O w nerO wn er
4
V ersio n C h ange L ist ( P . I. R . L ist )
V ersio n C h ange L ist ( P . I. R . L ist )
V ersio n C h ange L ist ( P . I. R . L ist )V ersion Cha n ge L ist ( P . I . R . L ist )
Issu e D escr ip tionDat e
Issu e D escr ip tionIss u e D escr ip tion
3
Pag e 1
Pag e 1
Pag e 1P ag e 1
2
So l u tion D es c rip tion
So l u tion D es c rip tion R e v.
So l u tion D es c rip tionSo lu tion D es c rip tion
1
R e v.P a ge#
R e v.Re v .
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 1
PWR_PIR 1
PWR_PIR 1
LA-7782
LA-7782
LA-7782
66 66Friday, June 10, 2011
66 66Friday, June 10, 2011
66 66Friday, June 10, 2011
1
0.1
0.1
0.1
Page 67
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