COMPAL LA-7782P Schematics

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

PCB NO :
BOM P/N :

LA-7782P (DAA00002J00)
T

MODEL NAME :

QAL81

BD

GPIO MAP: E4_VC_GPIO_map_rev_0.8

2 2

Dalmore 14 DSC

Ivy Bridge + Panther POINT

2011-05-12

REV : 0.1 (X00)

@ : Nopop Component

3 3

CONN@ : Connector Component

MB Type

TPM

TCM

TPM DIS/TCM DIS 2@ 3@

4 4

MB PCB

MB PCB

Part Number Description

Part Number Description

DAA00002J00 PCB 0LE LA-7782P REV0 M/B DSC

DAA00002J00 PCB 0LE LA-7782P REV0 M/B DSC

A

B

BOM P/N

1@

3@

2@

4@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-7782

LA-7782

LA-7782

1 66Tuesday, May 24, 2011

1 66Tuesday, May 24, 2011

1 66Tuesday, May 24, 2011

E

0.1

0.1

0.1

A

B

C

D

E

Block Diagram

1 1

LVDS CONN

HDMI CONN

DOCKING PORT

2 2

EXPRESS

3 3

4 4

PAGE 26

PAGE 38

USB2.0 [3,8]

SATA5

DOCK LAN

USB3.0 [4]

Card

USB10

CPU XDP Port

PCH XDP Port

WiFi ON/OFF

DC/DC Interface

Power On/Off
SW & LED

Thermal

GUARDIAN III
EMC4022

Compal confidential

LVDS Switch

MAX14979

DPC

DPD
VGA

DAI

CRT CONN

On IO board

SDXC/MMC

PCIE5

1/2 Mini Card

PAGE 34 PAGE 34 PAGE 34PAGE 35

USB6

PWM FAN

PAGE 22

A

PAGE 22PAGE 23

PS8171

PAGE 26

PAGE 33

PCIE2

1/2 Mini Card

WLAN

Smart Card

RFID

PAGE 22

iLVDS

dLVDS

DPE

Card Reader

OZ600FJ0

PCI Express BUS

Full Mini Card

WWAN

USB5USB4

TDA8034HN

Fingerprint
CONN

SMSC SIO

ECE5048

Nvidia
N13M

Video Switch
MAX14885E

PCIE1PCIE3

FP_USB

PAGE 39

B

PEG Gen3

PAGE 44-51

dVGA

PAGE 24

PAGE 33

100MHz

Option

China TCM1.2

SSX44BPP

USH

BCM5882

BC BUS

SMSC KBC

MEC5055

PAGE 41 PAGE 41

iVGA

iLVDS

PCIE x1

PAGE 32

USB7

USH Module

PAGE 40

KB CONNTP CONN

Ivy Bridge

Panther Point-M

LPC BUS

33MHz

Memory BUS (DDR3)

1333/1600 MHz

rPGA CPU

988 pins

FDI

Lane x 8

INTEL

PAGE 6-11

DMI2
Lane x 4

USB

SATA

Touch Screen

BT 4.0

Camera

SATA Repeater

PS8513B

BGA

PI5USB1457A USB

PAGE 14-21

PCI Express BUS

HD Audio I/F

SPI

S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s

W25Q64CVSSIG

64M 4K sector

PAGE 14

Power Share

100MHz

SATA Repeater

PS8520B

PAGE 27

W25Q32BVSSIG

MDC

RJ11

on IO board

32M 4K sector

PCIE4

PAGE 14

E-Module

PAGE 28

HDD

PAGE 27

FFS LNG3DM

PAGE 27

Discrete TPM
AT97SC3204

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

PAGE 32

D

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

PAGE 23

PAGE 41

PAGE 12-13

Trough LVDS Cable

PAGE 37

USB3.0

USB3.0

PAGE 36

HDA Codec
92HD93

PAGE 29

Trough LVDS Cable

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

E-SATA

USB 2.0 Port

USB3.0/2.0

USB3.0/2.0+PS

USB Port

PAGE 37

PAGE 36

PAGE 36

DOCK LAN

INT.Speaker

PAGE 29

HeadPhone &
MIC Jack

DAI

To Docking side

Dig.
MIC

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DIS Block Diagram

DIS Block Diagram

DIS Block Diagram
LA-7782

LA-7782

LA-7782

on IO board

Intel Lewisville

82579LM

LAN SWITCH
PI3L720

RJ45

on IO board

2 66Monday, May 30, 2011

2 66Monday, May 30, 2011

2 66Monday, May 30, 2011

E

PAGE 31

PAGE 31

0.1

0.1

0.1

5

4

3

2

1

POWER STATES

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF

S4 (Suspend to DISK) / M3 ON ON OFF

S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH HIGH

LOW HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP

SLP

S5#

S4#

HIGH HIGH

LOW

LOW

SLP
A#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

OFF

OFF

CLOCKS

OFF

OFF

OFF

PCH

USB PORT#

0
1
2
3
4
5
6
7

JUSB1 (Right side Top)
JUSB2 (Right side Bottom)
JESA1 (Right side ESATA)

LK DOCK

M
WLAN
WWAN
JMINI3(Flash)
USH->BIO

DESTINATION

DOCKING8

PM TABLE

C C

power
plane

State

S0

S3

+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO

ON

+3.3V_SUS
+1.5V_MEM

ON ON

ON

+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN

OFFON

+3.3V_M
+1.05V_M

ON

ON

+3.3V_M
+1.05V_M
(M-OFF)

ON

OFF

SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5

DESTINATION

DD

H
ODD/ E3 Module Bay
NA
NA
ESATA
Dock

USH

9
10 Express card
11
12
13 LCD Touch

0
1

JUSB (Left side)

Bluetooth
Camera

BIO
NA

S5 S4/AC

S5 S4/AC don't exist

B B

A A

ON

OFF

OFFOFF

OFF

OFF

ON

OFF

OFFOFF

need to update Power Status and PM
Table

DSC DP/HDMI Port

Port C
Port D
Port E

Connetion
Dock DP port 2
Dock DP port 1
MB HDMI Conn

PCI EXPRESS

Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 None

DESTINATION

MINI CARD-1 WWAN

INI CARD-2 WLAN

M
Express card
E3 Module Bay (USB3)
1/2vMINI CARD-3 PCIE
MMI
10/100/1G LOM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

Index and Config.

Index and Config.
LA-7782

LA-7782

LA-7782

3 66Friday, May 20, 2011

3 66Friday, May 20, 2011

3 66Friday, May 20, 2011

1

0.1

0.1

0.1

5

4

3

2

1

EN_INVPWR

ADAPTER

D D

DGPU_PWR_EN

+PWR_SRC

BATTERY

FDC654P

(Q21)

ISL62883
(PU1000)

+VCC_CORE

+BL_PWR_SRC

+GPU_CORE

1.05V_0.8V_PWROK

VT1318M
(PU700)

HDDC_EN

+5V_HDD

MODC_EN

SI3456BDVSI3456BDV

(Q30)(Q27)

+5V_MOD

MCARD_MISC_PWREN

SI3456

(Q42)

MCARD_WWAN_PWREN

SI3456

(Q40)

+VCC_GFXCORE

ALWON

CHARGER

C C

RT8205
(PU100)

+5V_ALW

+3.3V_FLASH

+3.3V_WWAN

+3.3V_ALW

RT8207
(PU200)

B B

DDR_ON

+1.5V_MEM

TPS51212

(PU500)

CPU_VTT_ON

TPS51212

(PU400)

SIO_SLP_A#

SIO_SLP_S3#

SY8033
(PU300)

1.05V_VTTPWRGD

TPS51461

(PU600)

SI3456

(Q38)

AUX_EN_WOWL

PCH_ALW_ON

SI3456

(Q49)

SUS_ON

S13456

(Q54)

AUX_ON

SI3456

(Q34)

SIO_SLP_S3#

SIO_SLP_S3#

TPS22966

(U78)

SIO_SLP_A#

SI3456

(Q58)

CPU1.5V_S3_GATE

(QC3)

SIO_SLP_S3#

NTGS4141NAO4728

(Q59)

0.75V_DDR_VTT_ON

+1.05V_RUN_VTT +1.05V_M

SIO_SLP_S3#

SI4164

Pop option

+1.0V_LAN

+1.8V_RUN

+VCC_SA

+3.3V_WLAN

+3.3V_ALW_PCH

+3.3V_M

+3.3V_LAN+3.3V_SUS

Pop option

+3.3V_RUN

+3.3V_M

+5V_RUN

(Q63)

A A

5

+0.75V_DDR_VTT+1.5V_RUN+1.5V_CPU_VDDQ

+1.05V_RUN

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Power Rail

Power Rail

Power Rail
LA-7782

LA-7782

LA-7782

4 66Friday, May 20, 2011

4 66Friday, May 20, 2011

4 66Friday, May 20, 2011

1

0.1

0.1

0.1

5

SMBUS Address [0x9a]

H14
C9

MEM_SMBCLK
MEM_SMBDATA

PCH

D D

B4

A3

B5
A4

LAN_SMBCLK
LAN_SMBDATA

2.2K

2.2K

DOCK_SMB_CLK
DOCK_SMB_DAT

LCD_SMBCLK
LCD_SMDATA

+3.3V_ALW_PCH

C8

G12

E14M16

SML1_SMBDATA

SML1_SMBCLK

B6A5

3A

3A

1A
1A

C C

1B
1B

2.2K

2.2K

2.2K

2.2K

4

2.2K

2.2K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_LAN

28
31

LOM

+3.3V_ALW

+3.3V_ALW

2N7002
2N7002

SMBUS Address [C8]

27

1
129

DOCKING

3

SMBUS Address
APR_EC: 0x48

SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13

202
200

202

200

2

DIMMA

DIMMB

53
51

53
51

XDP1

XDP2

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

SMBUS Address [TBD]

1

10K

G Sensor

WWAN

+3.3V_RUN

SMBUS Address [0x3B]

SMBUS Address [TBD]

10K

4
6

30
32

2.2K

4

+3.3V_ALW

100 ohm
100 ohm

+3.3V_ALW

+3.3V_SUS

+3.3V_ALW

+3.3V_ALW

+3.3V_RUN

9
8

7
6

M9
L9

7
8

Charger

BATTERY
CONN

SMBUS Address [0x16]

USH

SMBUS Address [0xa4]

Express card

SMBUS Address [0x12]

SMBUS Address [TBD]

29

E3 Module Bay

30

T4

GPU

T3

3

SMBUS Address [0xd2]

SMBUS Address [0xXX]

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SMBUS TOPOLOGY

SMBUS TOPOLOGY

SMBUS TOPOLOGY
LA-7782

LA-7782

LA-7782

5 66Friday, May 20, 2011

5 66Friday, May 20, 2011

5 66Friday, May 20, 2011

1

0.1

0.1

0.1

KBC

A56

1C1CB59

PBAT_SMBCLK
PBAT_SMBDAT

2.2K

2.2K

2.2K

1E

B B

1E

MEC 5065

2B
2B

B

B52

53

A49

USH_SMBDAT

2.2K

2.2K

CARD_SMBCLK
CARD_SMBDAT

USH_SMBCLK

A50

2.2K

B50

A47

CHARGER_SMBCLK
CHARGER_SMBDAT

1G
1G

2.2K

2.2K

2.2K

BAY_SMBDAT

B7

2D

BAY_SMBCLK

A A

A7

2D

2.2K

2.2K

GPU_SMBCLK

B49

2A

B48

2A

5

GPU_SMBDAT

5

4

3

2

1

(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2

+1.05V_RUN_VTT

12

RC2

RC2

24.9_0402_1%~D

D D

DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>

C C

FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16>
FDI_FSYNC1<16>

FDI_INT<16>
FDI_LSYNC0<16>

FDI_LSYNC1<16>

(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1

B B

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

JCPU1A

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

DP Compensation

+1.05V_RUN_VTT

12

RC1

RC1

24.9_0402_1%~D

A A

eDP_COMPIO and ICOMPO signals should be shorted near

alls and routed with typical impedance <25 mohms

b

5

24.9_0402_1%~D

EDP_COMP

4

24.9_0402_1%~D

PEG_COMP

PEG_CRX_GTX_N0
PEG_CRX_GTX_N1
PEG_CRX_GTX_N2
PEG_CRX_GTX_N3
PEG_CRX_GTX_N4
PEG_CRX_GTX_N5
PEG_CRX_GTX_N6
PEG_CRX_GTX_N7
PEG_CRX_GTX_N8
PEG_CRX_GTX_N9
PEG_CRX_GTX_N10
PEG_CRX_GTX_N11
PEG_CRX_GTX_N12
PEG_CRX_GTX_N13
PEG_CRX_GTX_N14
PEG_CRX_GTX_N15

PEG_CRX_GTX_P0
PEG_CRX_GTX_P1
PEG_CRX_GTX_P2
PEG_CRX_GTX_P3
PEG_CRX_GTX_P4
PEG_CRX_GTX_P5
PEG_CRX_GTX_P6
PEG_CRX_GTX_P7
PEG_CRX_GTX_P8
PEG_CRX_GTX_P9
PEG_CRX_GTX_P10
PEG_CRX_GTX_P11
PEG_CRX_GTX_P12
PEG_CRX_GTX_P13
PEG_CRX_GTX_P14
PEG_CRX_GTX_P15

PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N15

PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P15

PEG_CRX_GTX_N[0..15] <45>

PEG_CRX_GTX_P[0..15] <45>

PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0

PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1

PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2

PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3

PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4

PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5

PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6

PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7

PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8

PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9

PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10

PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11

PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12

PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13

PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14

PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

PEG_CTX_GRX_P[0..15] <45>
PEG_CTX_GRX_N[0..15] <45>

CC1 0.22U_0402_16V7K~DCC1 0.22U_0402_16V7K~D

12

CC2 0.22U_0402_16V7K~DCC2 0.22U_0402_16V7K~D

12

CC3 0.22U_0402_16V7K~DCC3 0.22U_0402_16V7K~D

12

CC4 0.22U_0402_16V7K~DCC4 0.22U_0402_16V7K~D

12

CC5 0.22U_0402_16V7K~DCC5 0.22U_0402_16V7K~D

12

CC6 0.22U_0402_16V7K~DCC6 0.22U_0402_16V7K~D

12

CC7 0.22U_0402_16V7K~DCC7 0.22U_0402_16V7K~D

12

CC8 0.22U_0402_16V7K~DCC8 0.22U_0402_16V7K~D

12

CC9 0.22U_0402_16V7K~DCC9 0.22U_0402_16V7K~D

12

CC10 0.22U_0402_16V7K~DCC10 0.22U_0402_16V7K~D

12

CC11 0.22U_0402_16V7K~DCC11 0.22U_0402_16V7K~D

12

CC12 0.22U_0402_16V7K~DCC12 0.22U_0402_16V7K~D

12

CC13 0.22U_0402_16V7K~DCC13 0.22U_0402_16V7K~D

12

CC14 0.22U_0402_16V7K~DCC14 0.22U_0402_16V7K~D

12

CC15 0.22U_0402_16V7K~DCC15 0.22U_0402_16V7K~D

12

CC16 0.22U_0402_16V7K~DCC16 0.22U_0402_16V7K~D

12

CC17 0.22U_0402_16V7K~DCC17 0.22U_0402_16V7K~D

1 2

CC18 0.22U_0402_16V7K~DCC18 0.22U_0402_16V7K~D

1 2

CC19 0.22U_0402_16V7K~DCC19 0.22U_0402_16V7K~D

1 2

CC20 0.22U_0402_16V7K~DCC20 0.22U_0402_16V7K~D

1 2

CC21 0.22U_0402_16V7K~DCC21 0.22U_0402_16V7K~D

1 2

CC22 0.22U_0402_16V7K~DCC22 0.22U_0402_16V7K~D

1 2

CC23 0.22U_0402_16V7K~DCC23 0.22U_0402_16V7K~D

1 2

CC24 0.22U_0402_16V7K~DCC24 0.22U_0402_16V7K~D

1 2

CC25 0.22U_0402_16V7K~DCC25 0.22U_0402_16V7K~D

1 2

CC26 0.22U_0402_16V7K~DCC26 0.22U_0402_16V7K~D

1 2

CC27 0.22U_0402_16V7K~DCC27 0.22U_0402_16V7K~D

1 2

CC28 0.22U_0402_16V7K~DCC28 0.22U_0402_16V7K~D

1 2

CC29 0.22U_0402_16V7K~DCC29 0.22U_0402_16V7K~D

1 2

CC30 0.22U_0402_16V7K~DCC30 0.22U_0402_16V7K~D

1 2

CC31 0.22U_0402_16V7K~DCC31 0.22U_0402_16V7K~D

1 2

CC32 0.22U_0402_16V7K~DCC32 0.22U_0402_16V7K~D

1 2

PEG_CTX_GRX_P0

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_P10

PEG_CTX_GRX_N10

PEG_CTX_GRX_P11

PEG_CTX_GRX_N11

PEG_CTX_GRX_P12

PEG_CTX_GRX_N12

PEG_CTX_GRX_P13

PEG_CTX_GRX_N13

PEG_CTX_GRX_P14

PEG_CTX_GRX_N14

PEG_CTX_GRX_P15

PEG_CTX_GRX_N15

2

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)
LA-7782

LA-7782

LA-7782

6 66Friday, June 10, 2011

6 66Friday, June 10, 2011

6 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

Follow DG Rev0.71 SM_DRAMPWROK topology

+3.3V_ALW_PCH

CC156 0.1U_0402_25V6K~DCC156 0.1U_0402_25V6K~D

1 2

5

UC2

UC2

1

RUNPWROK<40,41>

+3.3V_ALW_PCH

D D

+1.05V_RUN_VTT

1 2

RC18 200_0402_1%~DRC18 200_0402_1%~D

PM_DRAM_PWRGD<16>

1 2

RC126 56_0402_5%~D@RC126 56_0402_5%~D@

1 2

RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@

1 2

RC44 62_0402_5%~DRC44 62_0402_5%~D

H_THERMTRIP#
H_CATERR#
H_PROCHOT#

P

B

O

2

A

G

74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

3

RUN_ON_CPU1.5VS3#<11,43>

RUNPWROK_AND PM_DRAM_PWRGD_CPU

4

+1.5V_CPU_VDDQ

RC64

39_0402_5%~D

39_0402_5%~D

1 2
13

D

D

QC1

QC1

2

G

SSM3K7002FU_SC70-3~D

G

SSM3K7002FU_SC70-3~D

S

S

INTEL suggest RC64 and QC1 NO stuff by default

JCPU1B

JCPU1B

4

12

RC12

RC12
200_0402_1%~D

200_0402_1%~D

1 2

RC28 130_0402_1%~DRC28 130_0402_1%~D

@RC64

@

@

@

3

+3.3V_ALW_PCH

12

RC124

@RC124

@

1K_0402_1%~D

1K_0402_1%~D

SYS_PWROK_XDP

The resistor for HOOK2 should beplaced
such that the stub is very small on CFG0 net

H_CPUPWRGD

SIO_PWRBTN#_R<14,16>

CFG0

SYS_PWROK<16,40>

DDR_XDP_WAN_SMBDAT<12,13,14,15,28,35>

DDR_XDP_WAN_SMBCLK<12,13,14,15,28,35>

+1.05V_RUN_VTT

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

Place near JXDP1

1 2

RC5 1K_0402_1%~DRC5 1K_0402_1%~D

1 2

RC6 0_0402_5%~DRC6 0_0402_5%~D

1 2

RC7 1K_0402_1%~DRC7 1K_0402_1%~D

1 2

RC9 0_0402_5%~D@RC9 0_0402_5%~D@

1 2

RC125 0_0402_5%~DRC125 0_0402_5%~D

1 2

RC127 0_0402_5%~DRC127 0_0402_5%~D

2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

CC66

CC66

CC65

CC65

2

XDP_PREQ#
XDP_PRDY#

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

CFG10<9>
CFG11<9>

CFG10
CFG11

XDP_OBS4
XDP_OBS5

XDP_OBS6
XDP_OBS7

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1

DDR_XDP_SMBCLK_R1

XDP_TCLK

+1.05V_RUN_VTT +1.05V_RUN_VTT

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A CONN@

SAMTE_BSH-030-01-L-D-A CONN@

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15
TRST#

TMS

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58
60

1

CFG16
CFG17

CFG0
CFG1

CFG2
CFG3

CFG8
CFG9

CFG4
CFG5

CFG6
CFG7

CLK_XDP
CLK_XDP#

XDP_RST#_RXDP_HOOK2
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

CFG16 <9>
CFG17 <9>

CFG0 <9>
CFG1 <9>

CFG2 <9>
CFG3 <9>

CFG8 <9>
CFG9 <9>

CFG4 <9>
CFG5 <9>

CFG6 <9>
CFG7 <9>

Follow check list 0.5

C C

H_PROCHOT#<41,60,62>

H_THERMTRIP#<22>

CPU_DETECT#<40>

PECI_EC<41>

VR1 TOPOLOGY

1 2

RC57 56_0402_5%~DRC57 56_0402_5%~D

1 2

RC129 0_0402_5%~DRC129 0_0402_5%~D

H_CATERR#

H_PROCHOT#_R

Close to JCPU1

H_THERMTRIP#_R

C26

AN34

AL33

AN33

AL32

AN32

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

BCLK

BCLK#

place RC129 near CPU

PRDY#

PREQ#

TCK

H_PM_SYNC<16>

B B

H_CPUPWRGD<18>

RC25 0_0402_5%~DRC25 0_0402_5%~D

Buffered reset to CPU

A A

PCH_PLTRST#<14,17>

5

H_PM_SYNC

VCCPWRGOOD_0_R

1 2

PM_DRAM_PWRGD_CPU

PCH_PLTRST#_R

UC1

UC1

1

NC

VCC

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

SN74LVC1G07DCKR_SC70-5~D

Open drain buffer

+3.3V_RUN

5
4

AM34

AP33

V8

AR33

+1.05V_RUN_VTT

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

CC140

CC140

2

PCH_PLTRST#_BUF

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

RC4

75_0402_1%~D

RC4

75_0402_1%~D

12

PCH_PLTRST#_R

1 2

RC10 43_0402_5%~DRC10 43_0402_5%~D

JTAG & BPM

JTAG & BPM

4

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TMS

TDO

TDI

CPU_DMI

A28

CPU_DMI#

A27

CPU_DPLL

A16

CPU_DPLL#

A15

Remove DPLL Ref clock (for eDP only)

DDR3_DRAMRST#_CPU

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCLK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI_R

AR28

XDP_TDO_R

AP26

XDP_DBRESET#_R

AL35

XDP_OBS0_R

AT28

XDP_OBS1_R

AR29

XDP_OBS2_R

AR30
AT30

XDP_OBS4_R XDP_OBS4

AP32

XDP_OBS5_R

AR31

XDP_OBS6_R

AT31

XDP_OBS7_R

AR32

For ESD concern, please put near CPU

VCCPWRGOOD_0_R

Avoid stub in the PWRGD path
while placing resistors RC25 & RC130

1 2

RC13 0_0402_5%~DRC13 0_0402_5%~D

1 2

RC15 0_0402_5%~DRC15 0_0402_5%~D

1 2

RC16 1K_0402_1%~DRC16 1K_0402_1%~D

1 2

RC17 1K_0402_1%~DRC17 1K_0402_1%~D

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>H_SNB_IVB#<18>

Max 500mils

RC50

RC50

4.99K_0402_1%~D

4.99K_0402_1%~D

DDR_HVREF_RST_PCH<15>
DDR_HVREF_RST_GATE<41>

XDP_DBRESET#

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3XDP_OBS3_R

XDP_OBS5
XDP_OBS6
XDP_OBS7

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

RC130

RC130
10K_0402_5%~D

10K_0402_5%~D

3

12

RC26 0_0402_5%~DRC26 0_0402_5%~D

RC30 0_0402_5%~DRC30 0_0402_5%~D
RC31 0_0402_5%~DRC31 0_0402_5%~D
RC33 0_0402_5%~DRC33 0_0402_5%~D
RC34 0_0402_5%~DRC34 0_0402_5%~D
RC36 0_0402_5%~DRC36 0_0402_5%~D
RC37 0_0402_5%~DRC37 0_0402_5%~D
RC38 0_0402_5%~DRC38 0_0402_5%~D
RC39 0_0402_5%~DRC39 0_0402_5%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+1.05V_RUN_VTT

RC48 0_0402_5%~D@ RC48 0_0402_5%~D@

12

XDP_DBRESET# <14,16>

SM_RCOMP2
SM_RCOMP1
SM_RCOMP0

1 2

D

S

D

S

13

QC2

QC2

G

G

BSS138W-7-F_SOT323-3~D

BSS138W-7-F_SOT323-3~D

2

DDR_HVREF_RST

1

CC177

CC177

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

2

1 2

RC46 0_0402_5%~DRC46 0_0402_5%~D

1 2

RC47 0_0402_5%~D@RC47 0_0402_5%~D@

1 2

RC23 0_0402_5%~DRC23 0_0402_5%~D

XDP_TDO_R XDP_TDO

RC42

RC42

140_0402_1%~D

140_0402_1%~D

1 2

RC24 0_0402_5%~DRC24 0_0402_5%~D

12

12

RC45

RC45

RC43

RC43

200_0402_1%~D

200_0402_1%~D

25.5_0402_1%~D

25.5_0402_1%~D

2

CLK_XDP
CLK_XDP#

DDR3_DRAMRST# <12>

XDP_TDIXDP_TDI_R

12

XDP_RST#_R

RH107 0_0402_5%~DRH107 0_0402_5%~D
RH106 0_0402_5%~DRH106 0_0402_5%~D

CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>

RC8 1K_0402_1%~DRC8 1K_0402_1%~D

1 2
1 2

DDR_HVREF_RST <12>

M3 control

RH109 0_0402_5%~D@RH109 0_0402_5%~D@
RH108 0_0402_5%~D@RH108 0_0402_5%~D@

12

1 2
1 2

PLTRST_XDP# <17>

CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>

PU/PD for JTAG signals

+3.3V_RUN

XDP_DBRESET#

XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TDO

XDP_TCLK
XDP_TRST#

RC19 1K_0402_1%~DRC19 1K_0402_1%~D

RC27 51_0402_1%~DRC27 51_0402_1%~D
RC29 51_0402_1%~DRC29 51_0402_1%~D
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
RC35 51_0402_1%~DRC35 51_0402_1%~D

RC40

RC40
RC41

RC41

12

12
12
12
12

12

51_0402_1%~D

51_0402_1%~D

12

51_0402_1%~D

51_0402_1%~D

+1.05V_RUN_VTT

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)
LA-7782

LA-7782

LA-7782

7 66Friday, June 10, 2011

7 66Friday, June 10, 2011

7 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

JCPU1C

JCPU1C

D D

C C

B B

DDR_A_D[0..63]<12>

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10
AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8
AK9

AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

K2
M8

N8
N7

M9
N9
M7

V6

J1
J5
J4
J2

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

4

M_CLK_DDR0

AB6

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]

SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0 <12>
M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12>

3

DDR_B_D[0..63]<13>

DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AM5
AM6
AR3

AN3
AN2
AN1

AN9

AN8
AR6
AR5
AR9

AJ11

AH11

AR8

AJ12

AH12

AT11
AN14
AR14

AT14

AT12
AN15
AR15

AT15

AA10

2

JCPU1D

JCPU1D

M_CLK_DDR2

AE2

SB_CK[0]

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]

AP3

SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]
SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR#2
DDR_CKE2_DIMMB

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2 <13>
M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

DDR_B_MA[0..15] <13>

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

A A

TYCO_2013620-3_IVYBRIDGE

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)
LA-7782

LA-7782

LA-7782

8 66Friday, June 10, 2011

8 66Friday, June 10, 2011

8 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

CFG0<7>
CFG1<7>
CFG2<7>
CFG3<7>
CFG4<7>
CFG5<7>
CFG6<7>
CFG7<7>
CFG8<7>
CFG9<7>
CFG10<7>
CFG11<7>

T9 PAD~D@T9 PAD~D@

+VCC_GFXCORE

1 2

RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@

C C

+VCC_CORE

B B

RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@

RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@

RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@

1 2

1 2

1 2

VAXG_VAL_SENSE

12

RC69

@RC69

@

100_0402_1%~D

100_0402_1%~D

VSSAXG_VAL_SENSE

VCC_VAL_SNESE

12

RC71

@RC71

@

100_0402_1%~D

100_0402_1%~D

VSS_VAL_SNESE

T10 PAD~D@T10 PAD~D@
T12 PAD~D@T12 PAD~D@
T14 PAD~D@T14 PAD~D@

CFG16<7>
CFG17<7>

T22PAD~D @T22PAD~D @

T28PAD~D @T28PAD~D @
T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~D @
T31PAD~D @T31PAD~D @
T33PAD~D @T33PAD~D @
T35PAD~D @T35PAD~D @
T36PAD~D @T36PAD~D @
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T40PAD~D @T40PAD~D @
T41PAD~D @T41PAD~D @
T42PAD~D @T42PAD~D @
T43PAD~D @T43PAD~D @ T32 PAD~D@T32 PAD~D@
T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @
T46PAD~D @T46PAD~D @

T47PAD~D @T47PAD~D @
T48PAD~D @T48PAD~D @

T52PAD~D @T52PAD~D @

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE

JCPU1E

JCPU1E

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

CFG

CFG

RESERVED

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

T39 PAD~D@T39 PAD~D@

T1 PAD~D@T1 PAD~D@
T2 PAD~D@T2 PAD~D@
T3 PAD~D@T3 PAD~D@
T4 PAD~D@T4 PAD~D@

T5 PAD~D@T5 PAD~D@

T6 PAD~D@T6 PAD~D@
T7 PAD~D@T7 PAD~D@
T8 PAD~D@T8 PAD~D@

T11 PAD~D@T11 PAD~D@
T13 PAD~D@T13 PAD~D@
T15 PAD~D@T15 PAD~D@
T16 PAD~D@T16 PAD~D@

T17 PAD~D@T17 PAD~D@
T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@
T20 PAD~D@T20 PAD~D@
T21 PAD~D@T21 PAD~D@

T23 PAD~D@T23 PAD~D@
T24 PAD~D@T24 PAD~D@
T25 PAD~D@T25 PAD~D@
T26 PAD~D@T26 PAD~D@
T27 PAD~D@T27 PAD~D@

T34 PAD~D@T34 PAD~D@

CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>

T49 PAD~D@T49 PAD~D@
T50 PAD~D@T50 PAD~D@
T51 PAD~D@T51 PAD~D@

T53 PAD~D@T53 PAD~D@

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition
0:Lane Reversed

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2

01: Reserved - (Device 1 function 1 disabled ; function

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

@ RC51

@

1K_0402_1%~D

1K_0402_1%~D

CFG4

1K_0402_1%~D

1K_0402_1%~D

CFG6
CFG5

@ RC54

@

RC54

12

12

disabled

2 enabled)

RC51

RC52

@ RC52

@

1K_0402_1%~D

1K_0402_1%~D

12

RC53

@ RC53

@

1K_0402_1%~D

1K_0402_1%~D

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CFG7

12

@ RC56

@

1K_0402_1%~D

1K_0402_1%~D

RC56

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following xxRESETB de assertion

A A

0: PEG Wait for BIOS for training

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)

LA-7782

LA-7782

LA-7782

9 66Friday, June 10, 2011

9 66Friday, June 10, 2011

9 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

+VCC_CORE

94A

D D

C C

B B

A A

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

4

POWER

JCPU1F

JCPU1F

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

POWER

PEG AND DDR

PEG AND DDR

CORE SUPPLY

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

8.5A

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

VCCSENSE_R
VSSSENSE_R

VTT_SENSE
VSSIO_SENSE_R

+1.05V_RUN_VTT

3

Note: Place the PU resistors close to CPU
RC61 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

VIDSCLK <60>

1 2

RC61 43_0402_5%~DRC61 43_0402_5%~D

+1.05V_RUN_VTT

12

RC63

RC63
130_0402_1%~D

130_0402_1%~D

H

_CPU_SVIDALRT# must be routed between the

DSOUT and VIDSCLK lines to reduce cross

VI
talk. 18 mils spacing to others.

Place RC66, RC70, RC75 near CPU

1 2

RC67 0_0402_5%~DRC67 0_0402_5%~D

1 2

RC68 0_0402_5%~DRC68 0_0402_5%~D

RC98 10_0402_1%~DRC98 10_0402_1%~D

10_0402_1%~D

10_0402_1%~D

12

12

RC133

RC133

2

+1.05V_RUN_VTT

12

CAD Note: Place the PU
resistors close to CPU
RC63 close to CPU 300 - 1500mils

VIDSOUT <60>

+VCC_CORE

RC75

@RC75

@

100_0402_1%~D

100_0402_1%~D

1 2

+1.05V_RUN_VTT

VTT_SENSE <58>
VSSIO_SENSE_R <58>

12

12

RC60

RC60
75_0402_1%~D

75_0402_1%~D

RC66

RC66
100_0402_1%~D

100_0402_1%~D

VCCSENSE <60>

VSSSENSE <60>

RC70

RC70
100_0402_1%~D

100_0402_1%~D

VIDALERT_N <60>

1

Iccmax current changed for PDDG Rev0.7

CPU Power Rail Table

Voltage Rail

VCC

VCCIO

VAXG

VCCPLL

VDDQ

VCCSA

+1.5V_MEM 1.5

Description

*

5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT

Voltage

0.65-1.3

1.05

0.0-1.1

1.8

1.5

.65-0.9

0

S0 Iccmax
Current (A)

53

8.5

26

3

5

6

12-16

*

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)

LA-7782

LA-7782

LA-7782

10 66Friday, June 10, 2011

10 66Friday, June 10, 2011

10 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+3.3V_ALW2

12

RC74

RC74
100K_0402_5%~D

2

+VCC_GFXCORE

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

CC176

CC176

1

+

+

2

61

100K_0402_5%~D

RUN_ON_CPU1.5VS3#

QC4A

QC4A
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

JCPU1G

JCPU1G

46A

AT24
AT23
AT21
AT20
AT18

AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24

AL23

AL21

AL20

AL18

AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17
AH24
AH23
AH21
AH20
AH18
AH17

1.5A

B6
A6
A2

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

D D

SIO_SLP_S3#<16,28,36,40,43,56>

CPU1.5V_S3_GATE<41>

C C

B B

1 2

RC96 1K_0402_1%~D@RC96 1K_0402_1%~D@

1 2

RC97 1K_0402_1%~D@RC97 1K_0402_1%~D@

A A

+1.8V_RUN

1 2

RC82 0_0402_5%~DRC82 0_0402_5%~D

1 2

RC79 0_0402_5%~D@RC79 0_0402_5%~D@

+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC173

CC173

2

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CC175

CC175

CC174

CC174

2

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCCPLL1
VCCPLL2
VCCPLL3

+PWR_SRC_S

5

RUN_ON_CPU1.5VS3# <7,43>

4

+1.5V_MEM +1.5V_CPU_VDDQ

12

RC72

RC72
100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3

3

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

QC4B

QC4B

4

POWER

POWER

SENSE

SENSE

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

QC3

QC3

AO4728L_SO8~D

AO4728L_SO8~D

8
7
6
5

330K_0402_1%~D

330K_0402_1%~D

12

RC143

RC143

VAXG_SENSE

VSSAXG_SENSE

LINES

LINES

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

SA RAIL

SA RAIL

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

1
2
3

1

4

1

2

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

CC136

CC136

+VCC_GFXCORE

AK35
AK34

AL1

+DIMM0_1_VREF_CPU

B4

+DIMM0_1_CA_CPU

D1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

2

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

A19

RC140 0_0402_5%~DRC140 0_0402_5%~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

12

CC135

CC135

12

RC99

RC99
10_0402_1%~D

10_0402_1%~D

12

RC100

RC100
10_0402_1%~D

10_0402_1%~D

+V_SM_VREF_CNT

1 2

1

2

20K_0402_5%~D

20K_0402_5%~D

@

@

RC73

RC73

+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU

10U_0402_6.3V6M

10U_0402_6.3V6M

1

CC161

CC161

2

1

2

3

+1.5V_MEM

@RC76

@

100_0402_1%~D

100_0402_1%~D

1 2

10U_0402_6.3V6M

10U_0402_6.3V6M

CC162

CC162

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

CC168

CC168

+V_DDR_SMREF

1K_0402_1%~D

1K_0402_1%~D

12

@

@

RC80

RC80

1K_0402_1%~D

1K_0402_1%~D

12

@

@

RC81

RC81

RUN_ON_CPU1.5VS3

RC76

VCC_AXG_SENSE <60>
VSS_AXG_SENSE <60>

+V_SM_VREF should
have 10 mil trace width

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

1

CC163

CC163

CC164

CC164

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

2

added VCCSA_VID_0 to Power page

1

CC170

CC170

CC169

CC169

2

2

VCCSA_VID_0 <59>
VCCSA_VID_1 <59>

1 2

RC134 0_0402_5%~D@RC134 0_0402_5%~D@

QC5

@QC5

@

NTR4503NT1G_SOT23-3~D

NTR4503NT1G_SOT23-3~D

1

+1.5V_CPU_VDDQ

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC166

CC166

CC165

CC165

+

+

2

2

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

1

CC172

CC172

CC171

CC171

+

+

2

VCCP_PWRCTRL <58>

+1.5V_CPU_VDDQ

1K_0402_1%~D

1K_0402_1%~D

12

3

2

CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D

CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D

CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D

CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D

CC167

CC167

1K_0402_1%~D

1K_0402_1%~D

12

12

12

12

12

+VCC_SA

VCCSA_SENSE <59>

JCPU1H

JCPU1H

AT35

VSS1

RC84

RC84

+V_SM_VREF_CNT

RC78

RC78

6A

+1.5V_MEM

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Ivy Bridge (1/6)

Ivy Bridge (1/6)

Ivy Bridge (1/6)

LA-7782

LA-7782

LA-7782

1

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

0.1

0.1

11 66Friday, June 10, 2011

11 66Friday, June 10, 2011

11 66Friday, June 10, 2011

0.1

5

+V_DDR_REFA_M3

+V_DDR_REF

D D

Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3

All VREF traces should
have 10 mil trace width

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>

DDR_A_MA[0..15]<8>

C C

Layout Note:
Place near JDIMM1

+1.5V_MEM

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

2

+1.5V_MEM

B B

A A

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

Layout Note:
Place near JDIMM1.203,204

+0.75V_DDR_VTT

1

2

CD4

CD4

CD3

CD3

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD8

CD8

CD7

CD7

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD17

CD17

CD9

CD9

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD18

CD18

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

5

CD6

CD6

CD5

CD5

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD10

CD10

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD19

CD19

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD11

CD11

CD51

CD51

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD20

CD20

330U_SX_2VY~D

330U_SX_2VY~D

@CD13

@

1

CD13

CD14

CD14

1

+

+

2

2

RD2 10K_0402_5%~DRD2 10K_0402_5%~D

1 2
1 2

RD3 10K_0402_5%~DRD3 10K_0402_5%~D

RD7 0_0402_5%~DRD7 0_0402_5%~D

RD1 0_0402_5%~DRD1 0_0402_5%~D

+3.3V_RUN

1 2

1 2

4

+DIMM1_VREF_DQ

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

DDR_A_D0
DDR_A_D1

CD2

1

2

DDR_CKE0_DIMMA<8>

DDR_CS1_DIMMA#<8>

CD2

1

CD1

CD1

DDR_A_BS2<8>

M_CLK_DDR0<8>

DDR_A_BS0<8>
DDR_A_WE#<8>

DDR_A_CAS#<8>

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

DDR_A_D2

2

DDR_A_D3
DDR_A_D8

DDR_A_D9 DDR_A_D13
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

CD22

CD22

+0.75V_DDR_VTT

CD21

CD21

2

JDIMM1 H=5.2

JDIMM1

CONN@JDIMM1

CONN@

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

TYCO_2-2013289-2~D

TYCO_2-2013289-2~D

3

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0
ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD

VDD
CK1

VDD
BA1

VDD

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SDA

SCL
VTT

2

2-3A to 1 DIMMs/channel

+1.5V_MEM+1.5V_MEM

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22
24
26
28

DDR3_DRAMRST#_R

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20DDR_A_D16

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

74
76

DDR_A_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

S0#

NC

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA14
DDR_A_MA11DDR_A_MA12

DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8

DDR_A_MA4DDR_A_MA5
DDR_A_MA2

DDR_A_MA0DDR_A_MA1
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

+0.75V_DDR_VTT

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>

M_CLK_DDR#1 <8>M_CLK_DDR#0<8>

DDR_A_BS1 <8>
DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>

M_ODT0 <8>
M_ODT1 <8>

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

CD15

CD15

1

2

DDR_XDP_WAN_SMBDAT <7,13,14,15,28,35>

DDR_XDP_WAN_SMBCLK <7,13,14,15,28,35>

+DIMM1_VREF_CA

DDR_HVREF_RST<7>

RD11 0_0402_5%~DRD11 0_0402_5%~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD16

CD16

1

2

DDR3_DRAMRST#_R

+DIMM0_1_VREF_CPU

DDR_HVREF_RST

+DIMM0_1_CA_CPU

DDR_HVREF_RST

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

12

+V_DDR_REF

+1.5V_MEM

12

1 2

RD28 1K_0402_1%~DRD28 1K_0402_1%~D

RD29 0_0402_5%~D@RD29 0_0402_5%~D@

1 2

QD1

QD1

D

S

D

S

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

G

G

2

RD30 0_0402_5%~D@RD30 0_0402_5%~D@

1 2

QD2

QD2

D

S

D

S

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

G

G

2

RD27

RD27
1K_0402_1%~D

1K_0402_1%~D

1

DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>

+V_DDR_REFA_M3

+V_DDR_REFB_M3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

LA-7782

LA-7782

LA-7782

12 66Friday, June 10, 2011

12 66Friday, June 10, 2011

12 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

D D

Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>

DDR_B_MA[0..15]<8>

C C

+1.5V_MEM

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD25

CD25

2

+1.5V_MEM

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

B B

A A

10U_0603_6.3V6M~D

CD30

CD30

CD29

CD29

1

1

2

2

Layout Note:
Place near JDIMM2.203,204

+0.75V_DDR_VTT

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD39

CD39

2

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD26

CD26

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD31

CD31

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD40

CD40

2

2

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD27

CD27

CD28

CD28

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD34

CD34

CD33

CD33

CD32

CD32

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD42

CD42

CD41

CD41

2

All VREF traces should
have 10 mil trace width

330U_SX_2VY~D

330U_SX_2VY~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@CD35

@

1

CD36

CD36

CD35

1

+

+

2

2

4

+V_DDR_REFB_M3

+V_DDR_REF

4

+DIMM2_VREF_DQ

1 2

RD8 0_0402_5%~DRD8 0_0402_5%~D

1 2

RD4 0_0402_5%~DRD4 0_0402_5%~D

+3.3V_RUN

RD5 10K_0402_5%~DRD5 10K_0402_5%~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

2

+3.3V_RUN

12

3

+1.5V_MEM

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

DDR_B_D0
DDR_B_D1

CD24

CD24

1

CD23

CD23

DDR_CKE2_DIMMB<8>

DDR_B_BS2<8>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_BS0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<8>

2

10K_0402_5%~D

10K_0402_5%~D

12

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

+0.75V_DDR_VTT

RD6

RD6

1

2

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

CD43

CD43

1

CD44

CD44

2

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

TYCO_2-2013310-2~D

TYCO_2-2013310-2~D

CONN@JDIMM2

CONN@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1
CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122

NC

124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

2-3A to 1 DIMMs/channel

+1.5V_MEM

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#_R
DDR_B_D14

DDR_B_D15
DDR_B_D20

DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

+0.75V_DDR_VTT

JDIMM2 H=9.2

DDR3_DRAMRST#_R <12>

DDR_CKE3_DIMMB <8>

M_CLK_DDR3 <8>

M_CLK_DDR#3 <8>

DDR_B_BS1 <8>

DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>

M_ODT2 <8>
M_ODT3 <8>

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

CD37

CD37

2

DDR_XDP_WAN_SMBDAT <7,12,14,15,28,35>

DDR_XDP_WAN_SMBCLK <7,12,14,15,28,35>

+DIMM2_VREF_CA

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD38

CD38

1

2

1

RD15 0_0402_5%~DRD15 0_0402_5%~D

12

+V_DDR_REF

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

LA-7782

LA-7782

LA-7782

13 66Friday, June 10, 2011

13 66Friday, June 10, 2011

13 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

CMOS settingCMOS_CLR1

TPM setting
Clear ME RTC Registers
Keep ME RTC Registers

12

RH38

RH38
330K_0402_1%~D

330K_0402_1%~D

PCH_INTVRMEN

12

RH39

@RH39

@

330K_0402_1%~D

330K_0402_1%~D

1

1

@

@

ME1 SHORT PADS~D

ME1 SHORT PADS~D

1 2

CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D

PCH_AZ_CODEC_SDOUT<30>

PCH_AZ_CODEC_SYNC<30>

PCH_AZ_CODEC_RST#<30>

PCH_AZ_CODEC_BITCLK<30>

27P_0402_50V8J~D

27P_0402_50V8J~D

Clear CMOSShunt
Keep CMOS

CH101

@CH101

@

Open

ME_CLR1

Shunt
Open

+RTC_CELL

D D

INTVRMEN- Integrated SUS

1.1V VRM Enable

High - Enable Internal VRs

*

Low - Enable External VRs

C C

PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.

+3.3V_ALW_PCH

On Die PLL VR is supplied by

1.5V when sampled high, 1.8 V
when sampled low

+RTC_CELL

2

2

PCH_AZ_SDOUT

1 2

RH29 33_0402_5%~DR H29 33_0402_5%~D
RH26 33_0402_5%~DR H26 33_0402_5%~D
RH27 33_0402_5%~DR H27 33_0402_5%~D
RH25 33_0402_5%~DR H25 33_0402_5%~D

1

2

1 2
1 2
1 2

PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK

+3.3V_ALW_PCH

12

+3.3V_ALW_PCH_JTAG

12

RH66

RH66
1K_0402_1%~D

1K_0402_1%~D

PCH_AZ_SYNC

12

RH282

@RH282

@

100K_0402_5%~D

100K_0402_5%~D

1 2

RH22 20K_0402_5%~DRH22 20K_0402_5%~D

1 2

RH23 20K_0402_5%~DRH23 20K_0402_5%~D

1 2

RH11 1M_0402_5%~DRH11 1M_0402_5%~D

1

1

@

@

CMOS1 SHORT PADS~D

CMOS1 SHORT PADS~D
CH4

CH4

CMOS place near DIMM

RH288

RH288
0_0603_5%~D

0_0603_5%~D

2

2

1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH59 51_0402_1%~DRH59 51_0402_1%~D
RH44 200_0402_1%~DRH44 200_0402_1%~D
RH45 200_0402_1%~DRH45 200_0402_1%~D

RH43 200_0402_1%~DRH43 200_0402_1%~D

PCH_AZ_MDC_SDOUT<31>

Follow INTEL CRB 0.7

B B

S

PCH_AZ_SYNC_Q

1 2

RH31 1M_0402_5%~DRH31 1M_0402_5%~D

INTEL HDA_SYNC
isolation circuit

12

R890

R890

3.3K_0402_5%~D

3.3K_0402_5%~D

SPI_PCH_CS0# SPI_PCH_CS0#_R

1 2

R935 47_0402_5%~DR935 47_0402_5%~D

SPI_PCH_DIN SPI_DIN64

1 2

R894 33_0402_5%~DR894 33_0402_5%~D

SPI_WP#_SEL SPI_WP#_SEL_R

SPI_WP#_SEL<40>

A A

1 2

R898 0_0402_5%~D@R898 0_0402_5%~D@

S

G

G

2

+5V_RUN

200 MIL SO8

64Mb Flash ROM 16Mb Flash ROM

U52

U52

1

VCC

/CS

2

DO

/HOLD

3

CLK

/WP
GND4DIO

W25Q64CVSSIG_SO8~D

W25Q64CVSSIG_SO8~D

4

CH2

CH2

15P_0402_50V8J~D

15P_0402_50V8J~D

CH3

CH3

15P_0402_50V8J~D

15P_0402_50V8J~D

PCH_AZ_MDC_BITCLK<31>
PCH_AZ_MDC_SYNC<31>

PCH_AZ_MDC_RST#<31>

PCH_AZ_MDC_SDIN1<31>

PCH_AZ_SYNC

SPI_CLK64

R899 33_0402_5%~DR899 33_0402_5%~D

SPI_DO64

R901 33_0402_5%~DR901 33_0402_5%~D

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
USB_MCARD1_DET#

HDD_DET#_R

BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R

12

12

YH1

YH1

32.768KHZ_12.5PF_Q13FC1350000~D

32.768KHZ_12.5PF_Q13FC1350000~D

PCH_RTCX2_R

12

CH100

@CH100

@

27P_0402_50V8J~D

27P_0402_50V8J~D

SPKR<30>

+3.3V_ALW_PCH

12

1 2
1 2

RH286 0_0402_5%~DRH286 0_0402_5%~D

12

RH287 1K_0402_1%~D@RH287 1K_0402_1%~D@

RH36 33_0402_5%~DR H36 33_0402_5%~D
RH50 1K_0402_1%~DRH50 1K_0402_1%~D

12

12

12

RH48

RH48

RH47

RH47

RH49

RH49

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

C746

C746

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1 2

R891

R891

3.3K_0402_5%~D

3.3K_0402_5%~D

SPI_HOLD#
SPI_PCH_CLK SPI_PCH_DO
SPI_PCH_DO

USB_OC0#_R<17>
USB_OC1#_R<17>

USB_OC2#<17>
USB_OC3#<17>

USB_OC4#_R<17>

USB_OC5#<17>
USB_OC6#<17>

SIO_EXT_SMI#<17,41>
SLP_ME_CSW_DEV#<18,40>
USB_MCARD1_DET#<18,35>

PCH_GPIO36<18>

PCH_GPIO37<18>

PCH_GPIO16<18>

TEMP_ALERT#<18,40>
PCH_GPIO15<18>

SIO_EXT_SCI#_R<18>

PCH_RSMRST#_Q<16,42>

PCH_AZ_CODEC_SDIN0<30>

ME_FWP<40>

12
12
12
12

D

D

13

QH7

QH7
SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

+3.3V_SPI +3.3V_SPI

8
7
6
5

1 2

RH1 33_0402_5%~DPXDP@ RH1 33_0402_5%~DPXDP@

1 2

RH3 33_0402_5%~DPXDP@ RH3 33_0402_5%~DPXDP@

1 2

RH4 33_0402_5%~DPXDP@ RH4 33_0402_5%~DPXDP@

1 2

RH5 33_0402_5%~DPXDP@ RH5 33_0402_5%~DPXDP@

1 2

RH6 33_0402_5%~DPXDP@ RH6 33_0402_5%~DPXDP@

1 2

RH7 33_0402_5%~DPXDP@ RH7 33_0402_5%~DPXDP@

1 2

RH8 33_0402_5%~DPXDP@ RH8 33_0402_5%~DPXDP@

1 2

RH9 33_0402_5%~DPXDP@ RH9 33_0402_5%~DPXDP@

1 2

RH10 33_0402_5%~DPXDP@ RH10 33_0402_5%~DPXDP@

1 2

RH12 33_0402_5%~DPXDP@ RH12 33_0402_5%~DPXDP@

1 2

RH13 33_0402_5%~DPXDP@ RH13 33_0402_5%~DPXDP@

1 2

RH14 33_0402_5%~DPXDP@ RH14 33_0402_5%~DPXDP@

1 2

RH15 33_0402_5%~DPXDP@ RH15 33_0402_5%~DPXDP@

1 2

RH16 33_0402_5%~DPXDP@ RH16 33_0402_5%~DPXDP@

1 2

RH17 33_0402_5%~DPXDP@ RH17 33_0402_5%~DPXDP@

1 2

RH18 33_0402_5%~DPXDP@ RH18 33_0402_5%~DPXDP@

1 2

RH19 33_0402_5%~DPXDP@ RH19 33_0402_5%~DPXDP@

1 2

RH20 33_0402_5%~DPXDP@ RH20 33_0402_5%~DPXDP@

1 2

RH24 1K_0402_1%~DPXDP@ RH24 1K_0402_1%~DPXDP@

PCH_RTCX1

1 2

1 2

RH32 33_0402_5%~DR H32 33_0402_5%~D

1 2

RH33 33_0402_5%~DR H33 33_0402_5%~D

1 2

RH34 33_0402_5%~DR H34 33_0402_5%~D

1 2
1 2
1 2

USB30_SMI#<29>

100_0402_1%~D

100_0402_1%~D

SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_PCH_DIN SPI_DIN32
SPI_WP#_SEL_R

12

RH2

RH2
10M_0402_5%~D

10M_0402_5%~D

R936 47_0402_5%~DR936 47_0402_5%~D
R895 33_0402_5%~DR895 33_0402_5%~D

RSMRST#_XDP

DDR_XDP_WAN_SMBDAT<7,12,13,15,28,35>

PCH_RTCX2
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN

PCH_AZ_BITCLK

PCH_AZ_SYNCPCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_CODEC_SDIN0
PCH_AZ_MDC_SDIN1

PCH_AZ_SDOUT

PCH_GPIO33

USB30_SMI#

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_DO
PCH_SPI_DIN

1 2
1 2

3

XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17

DDR_XDP_WAN_SMBCLK<7,12,13,15,28,35>

A20
C20
D20
G22
K22
C17

N34

L34

T10

K34

E34
G34
C34
A34

A36

C36
N32

J3
H7
K5
H1

T3

Y14

T1

V4
U3

+3.3V_ALW_PCH

1

PXDP@

PXDP@

CH1

CH1

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2

RH284 0_0402_5%~DPXDP@ RH284 0_0402_5%~DPXDP@

RH285 0_0402_5%~DPXDP@ RH285 0_0402_5%~DPXDP@

JTAG

JTAG

RH283 1K_0402_1%~DPXDP@ RH283 1K_0402_1%~DPXDP@

RH21 0_0402_5%~DPXDP@ RH21 0_0402_5%~DPXDP@

1 2
1 2

RTCIHDA

RTCIHDA

SPI

SPI

1.05V_0.8V_PWROK<41,60>
SIO_PWRBTN#_R<7,16>

UH4A

UH4A

RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN

HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

HDA_DOCK_ EN# / GPIO33
HDA_DOCK_ RST# / GPIO 13

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

BBS_BIT0 - BIOS BOOT STRAP BIT 0

200 MIL SO8

U53

U53

1
2
3
4

W25Q32BVSSIG_SO8~D

W25Q32BVSSIG_SO8~D

8

CS#

VCC

7

DO

HOLD#

6

WP#

CLK

5

GND

DI

1.05V_0.8V_PWROK_R

1 2

PCH_PWRBTN#_XDP

1 2

DDR_XDP_WAN_SMBDAT_R2

DDR_XDP_WAN_SMBCLK_R2

FWH0 / L AD0
FWH1 / L AD1
FWH2 / L AD2
FWH3 / L AD3

LPC

LPC

FWH4 / L FRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA

SATA

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

R897 33_0402_5%~DR897 33_0402_5%~D

SPI_DO32

R900 33_0402_5%~DR900 33_0402_5%~D

+3.3V_ALW_PCH

XDP_FN0
XDP_FN1

XDP_FN2
XDP_FN3

XDP_FN4
XDP_FN5

XDP_FN6
XDP_FN7

LPC_LAD0

C38

LPC_LAD1

A38

LPC_LAD2

B37

LPC_LAD3

C37

LPC_LFRAME#

D36

LPC_LDRQ0#

E36

LPC_LDRQ1#

K36

IRQ_SERIRQ

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

C745

C745

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1 2

1 2
1 2

2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12

39

PWRGOO D/HOOK0

41

HOOK1

43

VCC_OBS_ AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A CONN@

SAMTE_BSH-030-01-L-D-A CONN@

LPC_LFRAME# <33,35,40,41>
LPC_LDRQ0# <40>

LPC_LDRQ1# <40>
IRQ_SERIRQ <33,40,41>

PSATA_PRX_DTX_N0_C <28>
PSATA_PRX_DTX_P0_C <28>
PSATA_PTX_DRX_N0_C <28>
PSATA_PTX_DRX_P0_C <28>

SATA_ODD_PRX_DTX_N1_C <29>
SATA_ODD_PRX_DTX_P1_C <29>
SATA_ODD_PTX_DRX_N1_C <29>
SATA_ODD_PTX_DRX_P1_C <29>

ESATA_PRX_DTX_N4_C <38>
ESATA_PRX_DTX_P4_C <38>
ESATA_PTX_DRX_N4_C <38>
ESATA_PTX_DRX_P4_C <38>

SATA_PRX_DKTX_N5_C <39>
SATA_PRX_DKTX_P5_C <39>
SATA_PTX_DKRX_N5_C <39>
SATA_PTX_DKRX_P5_C <39>

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_ACT#
HDD_DET#_R
BBS_BIT0_R

1 2

RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D

1 2

RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D

1 2

RH46 750_0402_1%~DRH46 750_0402_1%~D

D

D

1 3

QH1 BSS138W-7-F_SOT323-3~D

QH1 BSS138W-7-F_SOT323-3~D

PCH_PLTRST#<7,17>

SPI_HOLD#
SPI_PCH_CLKSPI_CLK32

JXDP2

JXDP2

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK 4

ITPCLK#/HOOK5

VCC_OBS_ CD

RESET#/HOO K6

DBR#/HOOK 7

LPC_LAD0 <33,35,40,41>
LPC_LAD1 <33,35,40,41>
LPC_LAD2 <33,35,40,41>
LPC_LAD3 <33,35,40,41>

+1.05V_RUN

+1.05V_RUN

SATA_ACT# <44>

1 2

RH290 0_0402_5%~DRH290 0_0402_5%~D

S

S

G

G

2

JSPI1

JSPI1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

G1

18

G2

HRS_FH12-16S-0P5SH(55)~D

HRS_FH12-16S-0P5SH(55)~D

CONN@

CONN@

GND1

GND3

GND5

GND7

GND9

GND11

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
SPI_PCH_CS0#
PCH_SPI_CS0#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

XDP_FN16
XDP_FN17

XDP_FN8
XDP_FN9

XDP_FN10
XDP_FN11

XDP_FN12
XDP_FN13

XDP_FN14
XDP_FN15

RSMRST#_XDP
XDP_DBRESET#

PCH_JTAG_TDO
PCH_JTAG_TDI

PCH_JTAG_TMSPCH_JTAG_TCK

PCH_GPIO33

RH355 100K_0402_5%~DRH355 100K_0402_5%~D

IRQ_SERIRQ

RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D

BBS_BIT0_R

HDD

INTEL feedback 0302

ODD/ E Module Bay

SPKR

No Reboot Strap

SPKR

E-SATA

DOCK

+3.3V_RUN

12

RH30

RH30
10K_0402_5%~D

10K_0402_5%~D

PCH_SATA_MOD_EN# <41>

1 2

RH345 0_0402_5%~DRH345 0_0402_5%~D

1 2

RH346 0_0402_5%~DRH346 0_0402_5%~D

1 2

RH347 0_0402_5%~DRH347 0_0402_5%~D

1 2

RH348 0_0402_5%~DRH348 0_0402_5%~D

1 2

RH349 0_0402_5%~DRH349 0_0402_5%~D

+3.3V_M

1 2

RH350 0_0402_5%~DRH350 0_0402_5%~D

+3.3V_ALW_PCH

XDP_DBRESET# <7,16>

+3.3V_RUN

12

12

12

RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D

+3.3V_RUN

12

RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@

Low = Default
High = No Reboot

HDD_DET# <28>

+3.3V_SPI

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8)

PCH (1/8)

ze Document Number Rev

PCH (1/8)

LA-7782

LA-7782

LA-7782

14 66Friday, June 10, 2011

14 66Friday, June 10, 2011

14 66Friday, June 10, 2011

1

0.1

0.1

0.1

5

D D

PCIE_PRX_WANTX_N1<35>

WWAN (Mini Card 1)--->

WLAN (Mini Card 2)--->

EXPRESS Card--->

E3 Module Bay--->

1/2 MINI CARD-3 PCIE
(Mini Card 3)--->

C C

MMI --->

10/100/1G LAN --->

WWAN (Mini Card 1)--->

10/100/1G LAN --->

MMI --->

B B

PP (Mini Card 3)--->

Express card--->

WLAN (Mini Card 2)--->

eModule Bay--->

A A

PCIE_PRX_WANTX_P1<35>
PCIE_PTX_WANRX_N1<35>
PCIE_PTX_WANRX_P1<35>

PCIE_PRX_WLANTX_N2<35>
PCIE_PRX_WLANTX_P2<35>
PCIE_PTX_WLANRX_N2<35>
PCIE_PTX_WLANRX_P2<35>

PCIE_PRX_EXPTX_N3<36>

PCIE_PRX_EXPTX_P3<36>
PCIE_PTX_EXPRX_N3<36>
PCIE_PTX_EXPRX_P3<36>

PCIE_PRX_EMBTX_N4<29>

PCIE_PRX_EMBTX_P4<29>
PCIE_PTX_EMBRX_N4<29>
PCIE_PTX_EMBRX_P4<29>

PCIE_PRX_WPANTX_N5<35>
PCIE_PRX_WPANTX_P5<35>
PCIE_PTX_WPANRX_N5<35>
PCIE_PTX_WPANRX_P5<35>

PCIE_PRX_MMITX_N6<34>

PCIE_PRX_MMITX_P6<34>
PCIE_PTX_MMIRX_N6<34>
PCIE_PTX_MMIRX_P6<34>

PCIE_PRX_GLANTX_N7<32>

PCIE_PRX_GLANTX_P7<32>
PCIE_PTX_GLANRX_N7<32>
PCIE_PTX_GLANRX_P7<32>

CLK_PCIE_MINI1#<35>
CLK_PCIE_MINI1<35>

+3.3V_ALW_PCH

MINI1CLK_REQ#<35>

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

LANCLK_REQ#<32>

CLK_PCIE_MMI#<34>
CLK_PCIE_MMI<34>

+3.3V_RUN

MMICLK_REQ#<34>

CLK_PCIE_MINI3#<35>

CLK_PCIE_MINI3<35>

+3.3V_ALW_PCH

MINI3CLK_REQ#<35>

CLK_PCIE_EXP#<36>

CLK_PCIE_EXP<36>

+3.3V_ALW_PCH

EXPCLK_REQ#<36>

CLK_PCIE_MINI2#<35>

CLK_PCIE_MINI2<35>

+3.3V_ALW_PCH

MINI2CLK_REQ#<35>

+3.3V_ALW_PCH

CLK_PCIE_EMB#<29>

CLK_PCIE_EMB<29>

+3.3V_ALW_PCH

EMBCLK_REQ#<29>
CLK_CPU_ITP#<7>

CLK_CPU_ITP<7>

RH307 0_0402_5%~DRH307 0_0402_5%~D
RH308 0_0402_5%~DRH308 0_0402_5%~D
RH81 10K_0402_5%~DRH81 10K_0402_5%~D

RH82 0_0402_5%~DRH82 0_0402_5%~D
RH83 0_0402_5%~DRH83 0_0402_5%~D

RH85 0_0402_5%~DRH85 0_0402_5%~D
RH86 0_0402_5%~DRH86 0_0402_5%~D
RH87 10K_0402_5%~DRH87 10K_0402_5%~D

RH88 0_0402_5%~DRH88 0_0402_5%~D
RH90 0_0402_5%~DRH90 0_0402_5%~D
RH152 10K_0402_5%~DRH152 10K_0402_5%~D

RH92 0_0402_5%~DRH92 0_0402_5%~D
RH93 0_0402_5%~DRH93 0_0402_5%~D
RH94 10K_0402_5%~DRH94 10K_0402_5%~D

RH95 0_0402_5%~DRH95 0_0402_5%~D
RH96 0_0402_5%~DRH96 0_0402_5%~D
RH97 10K_0402_5%~DRH97 10K_0402_5%~D

RH98 10K_0402_5%~DRH98 10K_0402_5%~D

RH310 0_0402_5%~DRH310 0_0402_5%~D
RH312 0_0402_5%~DRH312 0_0402_5%~D
RH104 10K_0402_5%~DRH104 10K_0402_5%~D

RH280 0_0402_5%~DRH280 0_0402_5%~D
RH281 0_0402_5%~DRH281 0_0402_5%~D

PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2

5

1 2

1 2

4

12
12
12

12
12

12
12

12
12
12

12
12
12

12
12
12

12
12
12

12
12

4

PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4

PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5

PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6

PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MMI#
PCIE_MMI

MMICLK_REQ#

PCIE_MINI3#
PCIE_MINI3

MINI3CLK_REQ#

PCIE_EXP#
PCIE_EXP

EXPCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PEG_B_CLKRQ#

PCIE_EMB#
PCIE_EMB

EMBCLK_REQ#
CLK_BCLK_ITP#

CLK_BCLK_ITP

UH4B

UH4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

3

PCH_SMB_ALERT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12
H14
C9

A12
C8
G12

C13
E14
M16

M7

T11

P10

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

Y47

K43
F47
H47
K49

MEM_SMBCLK
MEM_SMBDATA

DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA

PCH_GPIO74
SML1_SMBCLK
SML1_SMBDATA

PCH_CL_CLK1

PCH_CL_DATA1

PCH_CL_RST1#

GFX_CLK_REQ#

CLK_PCIE_VGA#
CLK_PCIE_VGA

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_BCLK
CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

CLK_PCI_LOOPBACK

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

PCI_TPM_TCM
SIO_14M
CLK_80H
JETWAY_14M

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

2

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <32>

LAN_SMBDATA <32>

SML1_SMBCLK <41>

SML1_SMBDATA <41>

PCH_CL_CLK1 <35>

PCH_CL_DATA1 <35>

PCH_CL_RST1# <35>

CLK_PCIE_VGA# <45>
CLK_PCIE_VGA <45>

CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>

CLK_PCI_LOOPBACK <17>

1 2

RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D

RH311 22_0402_5%~DRH311 22_0402_5%~D
RH313 22_0402_5%~DRH313 22_0402_5%~D
RH314 22_0402_5%~DRH314 22_0402_5%~D
RH315 22_0402_5%~D@RH315 22_0402_5%~D@

12
12
12
12

2

+3.3V_RUN

QH5A

QH5A

2

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

6 1

5

3

4

QH5B

QH5B

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

+3.3V_ALW_PCH

SML1_SMBCLK
SML1_SMBDATA

DDR_HVREF_RST_PCH
PCH_GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#

LAN_SMBCLK
LAN_SMBDATA

3.3V_RUN_GFX_ON<40,49>

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

DDR_XDP_WAN_SMBCLK <7,12,13,14,28,35>

DDR_XDP_WAN_SMBDAT <7,12,13,14,28,35>

RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D

RH300 1K_0402_1%~DRH300 1K_0402_1%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
RH304 10K_0402_5%~DRH304 10K_0402_5%~D

RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D

RH80

RH80

10K_0402_5%~D

10K_0402_5%~D

RH74 10K_0402_5%~DRH74 10K_0402_5%~D
RH75 10K_0402_5%~DRH75 10K_0402_5%~D

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

RH76 10K_0402_5%~DRH76 10K_0402_5%~D
RH77 10K_0402_5%~DRH77 10K_0402_5%~D

RH78 10K_0402_5%~DRH78 10K_0402_5%~D
RH79 10K_0402_5%~DRH79 10K_0402_5%~D

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

CLOCK TERMINATION for FCIM and need close to PCH

12

+1.05V_RUN

CLK_PCI_TPM_TCM <33>

CLK_SIO_14M <40>

PCLK_80H <35>

JETWAY_CLK14M <33>

RH309 0_0402_5%~DRH309 0_0402_5%~D

RH99

RH99
1M_0402_5%~D

1M_0402_5%~D

25MHZ_10PF_Q22FA2380049900~D

25MHZ_10PF_Q22FA2380049900~D

2

CH18

CH18

1

12P_0402_50V8J~D

12P_0402_50V8J~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8)

PCH (2/8)

PCH (2/8)
LA-7782

LA-7782

LA-7782

1

1 2
1 2

12

13

D

D

2

G

G

S

S

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2

3

OUT

4

GND

1

+3.3V_ALW_PCH

+3.3V_ALW_PCH

12
12
12
12
12

+3.3V_LAN

12
12

GFX_CLK_REQ#

QH2

QH2

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

12

YH2

YH2

1

IN

2

GND

15 66Friday, June 10, 2011

15 66Friday, June 10, 2011

15 66Friday, June 10, 2011

2

CH19

CH19

1

12P_0402_50V8J~D

12P_0402_50V8J~D

0.1

0.1

0.1

5

+3.3V_ALW_PCH

1 2

RH318 10K_0402_5%~D@ RH318 10K_0402_5%~D@

1 2

RH144 10K_0402_5%~DRH144 10K_0402_5%~D

1 2

D D

+3.3V_RUN

C C

B B

SYS_PWROK<7,40>

RESET_OUT#<41>

PM_APWROK<41>

PM_DRAM_PWRGD<7>

PCH_RSMRST#_Q<14,42>

ME_SUS_PWR_ACK<41>

SIO_PWRBTN#_R<7,14>

SIO_PWRBTN#<41>

AC_PRESENT<41>

+3.3V_ALW_PCH

A A

RH142 10K_0402_5%~DRH142 10K_0402_5%~D

1 2

RH319 10K_0402_5%~D@ RH319 10K_0402_5%~D@

1 2

RH140 10K_0402_5%~DRH140 10K_0402_5%~D

1 2

RH137 8.2K_0402_5%~DRH137 8.2K_0402_5%~D

1 2

RH138 8.2K_0402_5%~D@RH138 8.2K_0402_5%~D@

+1.05V_RUN

1 2

RH111 49.9_0402_1%~DRH111 49.9_0402_1%~D

1 2

RH112 750_0402_1%~DRH112 750_0402_1%~D

SUSACK#<40> PCH_DPWROK <40>

SUS_STAT#/LPCPD#

ME_SUS_PWR_ACK

PCH_PCIE_WAKE#

SIO_SLP_LAN#

PCH_RI#

CLKRUN#
ME_RESET#

DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>

DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>

DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>

DMI_COMP_R
RBIAS_CPY

1 2

RH114 0_0402_5%~D@ RH114 0_0402_5%~D@

1 2

RH116 0_0402_5%~DRH116 0_0402_5%~D

1 2

RH117 0_0402_5%~DRH117 0_0402_5%~D

1 2

RH118 0_0402_5%~DRH118 0_0402_5%~D

1 2

RH320 0_0402_5%~DRH320 0_0402_5%~D

1 2

RH120 0_0402_5%~DRH120 0_0402_5%~D

1 2

RH121 0_0402_5%~DRH121 0_0402_5%~D

1 2

RH122 0_0402_5%~DRH122 0_0402_5%~D

1 2

RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

SIO_PWRBTN#_R

AC_PRESENT

PCH_BATLOW#

PCH_RI#

XDP_DBRESET#<7,14>

RH141 8.2K_0402_5%~D@RH141 8.2K_0402_5%~D@

PCH_DPWROK PCH_RSMRST#_R

ME_SUS_PWR_ACK_R SUSACK#_R

UH4C

UH4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

4

RH357 0_0402_5%~DRH357 0_0402_5%~D

1 2

+3.3V_RUN

UC3

@UC3

@

1

ME_RESET#

12

1 2

RH113 0_0402_5%~DRH113 0_0402_5%~D

1 2

RH321 0_0402_5%~D@ RH321 0_0402_5%~D@

1 2

RH323 0_0402_5%~DRH323 0_0402_5%~D

DMI

DMI

System Power Management

System Power Management

2

SYS_PWROKRESET_OUT#

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI

FDI

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

CH99

@CH99

@

1 2

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

P

B

4

O

A

G

74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

3

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PCH_DPWROK

PCH_PCIE_WAKE#

CLKRUN#

SUS_STAT#/LPCPD#

SUSCLK

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_S3#

SIO_SLP_A#

SIO_SLP_SUS#

H_PM_SYNC

SIO_SLP_LAN#

SYS_RESET#

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

RH127 330K_0402_1%~DRH127 330K_0402_1%~D

1 2

RH129 330K_0402_1%~D@RH129 330K_0402_1%~D@

1 2

3

PCH_CRT_BLU

1 2

RH131 150_0402_1%~DRH131 150_0402_1%~D
RH132 150_0402_1%~DRH132 150_0402_1%~D
RH133 150_0402_1%~DRH133 150_0402_1%~D
RH134 100K_0402_5%~DRH134 100K_0402_5%~D

1 2
1 2
1 2

PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH

DSWODVREN - On Die DSW VR Enable

Enabled (DEFAULT)

HIGH: RH127 STUFFED,
RH129 UNSTUFFED

Disabled

LOW: RH129 STUFFED,
RH127 UNSTUFFED

FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>

FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 <6>
FDI_LSYNC1 <6>

PCH_PCIE_WAKE# <41>

CLKRUN# <33,40,41>

T56 PAD~DT56 PAD~D

T57 PAD~DT57 PAD~D
T58 PAD~DT58 PAD~D

SIO_SLP_S5# <41>

T59 PAD~DT59 PAD~D

SIO_SLP_S4# <40>

SIO_SLP_S3# <11,28,36,40,43,56>

SIO_SLP_A# <40,43,57>

T62 PAD~DT62 PAD~D

SIO_SLP_SUS# <40>

T63 PAD~DT63 PAD~D

H_PM_SYNC <7>

SIO_SLP_LAN# <32,40>

Minimum speacing of 20mils for LVD_IBG

+RTC_CELL

PCH_CRT_HSYNC<25>
PCH_CRT_VSYNC<25>

2.2K_0402_5%~D

2.2K_0402_5%~D

@

@

PANEL_BKEN_PCH<24>

ENVDD_PCH<24,40>

BIA_PWM_PCH<24>

LDDC_CLK_PCH<23>
LDDC_DATA_PCH<23>

1 2

RH344 2.37K_0402_1%~DRH344 2.37K_0402_1%~D

LCD_ACLK-_PCH<23>
LCD_ACLK+_PCH<23>

LCD_A0-_PCH<23>
LCD_A1-_PCH<23>
LCD_A2-_PCH<23>

LCD_A0+_PCH<23>
LCD_A1+_PCH<23>
LCD_A2+_PCH<23>

LCD_BCLK-_PCH<23>
LCD_BCLK+_PCH<23>

LCD_B0-_PCH<23>
LCD_B1-_PCH<23>
LCD_B2-_PCH<23>

LCD_B0+_PCH<23>
LCD_B1+_PCH<23>
LCD_B2+_PCH<23>

PCH_CRT_BLU<25>
PCH_CRT_GRN<25>
PCH_CRT_RED<25>

RH123 20_0402_1%~DRH123 20_0402_1%~D

1 2
1 2

RH124 20_0402_1%~DRH124 20_0402_1%~D

1K_0402_0.5%~D

1K_0402_0.5%~D

+3.3V_RUN

2.2K_0402_5%~D

2.2K_0402_5%~D

12

12

RH316

RH316

PANEL_BKEN_PCH
ENVDD_PCH

BIA_PWM_PCH
LDDC_CLK_PCH

LDDC_DATA_PCH

LVD_IBG

LCD_ACLK-_PCH
LCD_ACLK+_PCH

LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH

LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH

LCD_BCLK-_PCH
LCD_BCLK+_PCH

LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH

LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT

HSYNC
VSYNC

CRT_IREF

12

RH126

RH126

2

@

@

RH317

RH317

MAX14885EETL has internal 3K pu for
PCH_CRT_DDC_CLK and PCH_CRT_DDC_DAT

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

Intel request DDPB can not support eDP

UH4D

UH4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

PCH_CRT_DDC_CLK <25>

PCH_CRT_DDC_DAT <25>

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8)

PCH (3/8)

PCH (3/8)

LA-7782

LA-7782

LA-7782

1

16 66Friday, June 10, 2011

16 66Friday, June 10, 2011

16 66Friday, June 10, 2011

0.1

0.1

0.1

+3.3V_RUN

5

4

3

2

1

PLTRST_GPU#<45>
PLTRST_USH#<33>
PLTRST_MMI#<34>
PLTRST_XDP#<7>
PLTRST_LAN#<32>
PLTRST_EMB#<29>

PCH_PLTRST#

5

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

PCI_REQ1#

LCD_CBL_DET#

BT_DET#

PCH_GPIO3

CAM_MIC_CBL_DET#

+3.3V_RUN

5

1

P

B

2

A

G

3

1 2

RH343 0_0402_5%~DRH343 0_0402_5%~D

1 2

RH335 0_0402_5%~DRH335 0_0402_5%~D

1 2

RH336 0_0402_5%~DRH336 0_0402_5%~D

1 2

RH337 0_0402_5%~DRH337 0_0402_5%~D

1 2

RH338 0_0402_5%~DRH338 0_0402_5%~D

1 2

RH340 0_0402_5%~DRH340 0_0402_5%~D

CLK_PCI_5048<40>

CLK_PCI_MEC<41>

CLK_PCI_DOCK<39>

CLK_PCI_LOOPBACK<15>

CH102

CH102

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1 2

UH3

UH3

PCH_PLTRST#_EC

4

O

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

PCIE_MCARD2_DET#<35>

BT_DET#<42>

LCD_CBL_DET#<24>

CAM_MIC_CBL_DET#<24>

HDD_FALL_INT<28>

RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 22_0402_5%~DRH103 22_0402_5%~D

RH105 22_0402_5%~DRH105 22_0402_5%~D

PCH_PLTRST#_EC <33,35,36,40,41>

1 2

RH334 0_0402_5%~DRH334 0_0402_5%~D

12
12
12

12

4

USB3RN1<37>
USB3RN2<37>

USB3RN4<39>
USB3RP1<37>
USB3RP2<37>

USB3RP4<39>
USB3TN1<37>
USB3TN2<37>

USB3TN4<39>
USB3TP1<37>
USB3TP2<37>

USB3TP4<39>

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ1#
BT_DET#
BBS_BIT1
PCI_GNT3#

LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#

T104PAD~D @T104PAD~D @

PCH_PLTRST#

PCI_5048
PCI_MEC
PCI_DOCK

PCI_LOOPBACKOUT

FFS_PCH_INT

UH4E

UH4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

RSVD

RSVD

USB30

USB30

PCI

PCI

USB

USB

RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25
RSVD26

RSVD27
RSVD28

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

Boot BIOS Strap

BBS_BIT1 Boot BIOS Location

*

SATA_SLPD
(BBS_BIT0)

0 0

0 1

1 0

1 1

LPC

Reserved (NAND)

PCI

SPI

3

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8
RSVD9

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

USBP0­USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9­USBP9+
USBP10­USBP10+
USBP11­USBP11+
USBP12­USBP12+
USBP13­USBP13+

USBRBIAS

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#

USBP0- <37>
USBP0+ <37>
USBP1- <37>
USBP1+ <37>
USBP2- <38>
USBP2+ <38>
USBP3- <39>
USBP3+ <39>
USBP4- <35>
USBP4+ <35>
USBP5- <35>
USBP5+ <35>
USBP6- <35>
USBP6+ <35>
USBP7- <33>
USBP7+ <33>
USBP8- <39>
USBP8+ <39>
USBP9- <31>
USBP9+ <31>
USBP10- <36>
USBP10+ <36>
USBP11- <42>
USBP11+ <42>
USBP12- <24>
USBP12+ <24>
USBP13- <24>
USBP13+ <24>

1 2

RH151

RH151

22.6_0402_1%~D

22.6_0402_1%~D

Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils

1 2

RH339 0_0402_5%~DRH339 0_0402_5%~D

1 2

RH341 0_0402_5%~DRH341 0_0402_5%~D

1 2

RH356 0_0402_5%~DRH356 0_0402_5%~D

SIO_EXT_SMI#

BBS_BIT1

----->Right Side Top

----->Right Side Bottom

----->Right side E-SATA

----->MLK DOCK

----->WLAN/WIMAX

----->WWAN/UWB

----->Flash

----->USH

----->DOCK

----->Left side

----->Express Card

----->Blue Tooth

----->Camera

----->LCD Touch

USB_OC0# <37>
USB_OC1# <37>
USB_OC2# <14>
USB_OC3# <14>
USB_OC4# <31>
USB_OC5# <14>
USB_OC6# <14>
SIO_EXT_SMI# <14,41>

USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC4#_R <14>

12

RH342

@RH342

@

1K_0402_1%~D

1K_0402_1%~D

2

INTEL feedback 0307

USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R

USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

RPH1

RPH1

4 5
3 6
2 7
1 8

RPH2

RPH2

4 5
3 6
2 7
1 8

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8)

PCH (4/8)

PCH (4/8)

LA-7782

LA-7782

LA-7782

17 66Friday, June 10, 2011

17 66Friday, June 10, 2011

17 66Friday, June 10, 2011

1

0.1

0.1

0.1

1 2

D D

C C

RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D

1 2

RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D

1 2

RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D

1 2

RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D

1 2

RH327 10K_0402_5%~DRH327 10K_0402_5%~D

1 2

RH330 10K_0402_5%~DRH330 10K_0402_5%~D

1 2

RH328 10K_0402_5%~DRH328 10K_0402_5%~D

1 2

RH332 10K_0402_5%~D@RH332 10K_0402_5%~D@

1 2

RH331 10K_0402_5%~DRH331 10K_0402_5%~D

PCI_GNT3#

12

RH333

@RH333

@

1K_0402_1%~D

1K_0402_1%~D

A16 swap override Strap/Top-Block

Swap Override jumper

PCI_GNT#3

B B

A A

PCH_PLTRST#<7,14>

Low = A16 swap
High = Default

5

4

3

2

1

+3.3V_ALW_PCH

RH53

RH53

4.7K_0402_5%~D

D D

C C

B B

A A

4.7K_0402_5%~D

1 2

SLP_ME_CSW_DEV#

12

RH353

RH353
1K_0402_1%~D

1K_0402_1%~D

@

@

Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)

SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE

ENABLED - HIGH DEFAULT
DISABLED - LOW

+3.3V_ALW_PCH

SIO_EXT_WAKE#

RH177 10K_0402_5%~DRH177 10K_0402_5%~D
RH354 1K_0402_1%~DRH354 1K_0402_1%~D

+3.3V_ALW_PCH

RH170 10K_0402_5%~DRH170 10K_0402_5%~D

+3.3V_RUN

RH171 10K_0402_5%~D@RH171 10K_0402_5%~D@
RH173 1K_0402_1%~D@RH173 1K_0402_1%~D@

RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH181 10K_0402_5%~DRH181 10K_0402_5%~D
RH178 10K_0402_5%~DRH178 10K_0402_5%~D

1 2

RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D

1 2

RH163 10K_0402_5%~DRH163 10K_0402_5%~D

1 2

RH272 10K_0402_5%~DRH272 10K_0402_5%~D

12

12

12
12

12
12
12

PCH_GPIO15

PCH_GPIO36

12

PCH_GPIO37

12

PCH_GPIO17

12

PCH_GPIO16

12

KB_DET#

PCH_GPIO36
PCH_GPIO37

TEMP_ALERT#
PCH_GPIO22
PCH_GPIO7

PCH_GPIO17

IO_LOOP#

PCH_GPIO16

5

1 2

INTEL feedback 0302

RH174 10K_0402_5%~DRH174 10K_0402_5%~D
RH172 10K_0402_5%~DRH172 10K_0402_5%~D

RH273 1K_0402_1%~D@RH273 1K_0402_1%~D@

RH265 10K_0402_5%~D@RH265 10K_0402_5%~D@

SIO_EXT_SCI#_R<14>

SIO_EXT_SCI#<41>

IO_LOOP#<31>

SIO_EXT_WAKE#<40>

PM_LANPHY_ENABLE<32>

PCH_GPIO15<14>

DBC_ENABLE for E4 12"

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

PCH_GPIO16<14>

PCIE_MCARD1_DET#<35>

E3_PAID_TS_DET#<24>
SLP_ME_CSW_DEV#<14,40>
DGPU_HOLD_RST#<45>

USB_MCARD1_DET#<14,35>

PCH_GPIO36<14>
PCH_GPIO37<14>

TEMP_ALERT#<14,40>

KB_DET#<42>

+3.3V_RUN

TPM_ID0

FFS_INT2<28>

RH267

1@ RH267

1@

10K_0402_5%~D

10K_0402_5%~D

1 2

RH270

2@ RH270

2@

10K_0402_5%~D

10K_0402_5%~D

1 2

SIO_EXT_SCI#

1 2

RH259 0_0402_5%~DRH259 0_0402_5%~D

USH_DET#
IO_LOOP#
PCH_GPIO7

PM_LANPHY_ENABLE
PCH_GPIO15

PCH_GPIO16

PCH_GPIO17
PCH_GPIO22

E3_PAID_TS_DET#
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#
USB_MCARD1_DET#
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

+3.3V_RUN

TPM_ID1

4

12

RH268

3@ RH268

3@

20K_0402_5%~D

20K_0402_5%~D

12

RH271

4@ RH271

4@

2.2K_0402_5%~D

2.2K_0402_5%~D

UH4F

UH4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

China TPM

No TPM, No China TPM

TBD
TPM

GPIO

GPIO

NCTF

NCTF

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

CPU/MISC

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

0
0

1 1

3

TPM_ID1TPM_ID0

C40
B41
C41
A40

P4
AU16
P5
AY11
AY10
T14
AY1

AH8
AK11
AH10
AK10

P37

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

0
1

CONTACTLESS_DET#

PCIE_MCARD3_DET#

SIO_A20GATE

SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R

INIT3_3V#

DF_TVS

NC_1

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

CONTACTLESS_DET# <33>
DGPU_PWROK <40,64>USH_DET#<33>

PCIE_MCARD3_DET# <35>

USB_MCARD2_DET# <35>

SIO_A20GATE <41>

SIO_RCIN# <41>
H_CPUPWRGD <7>

T106PAD~D@T106PAD~D

@

T108PAD~D @T108PAD~D @

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

1

2

H_SNB_IVB#<7>

2

+1.05V_RUN_VTT

12

RH262 56_0402_5%~DRH262 56_0402_5%~D

CH97

CH97

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1 2

RH150 0_0402_5%~DRH150 0_0402_5%~D

CONTACTLESS_DET#

RH256 10K_0402_5%~DRH256 10K_0402_5%~D

SIO_A20GATE
SIO_RCIN#

SIO_EXT_SCI#
USH_DET#

PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)

+VCCDFTERM

12

RH158 10K_0402_5%~DRH158 10K_0402_5%~D
RH203 10K_0402_5%~DRH203 10K_0402_5%~D

1 2

RH263 10K_0402_5%~DRH263 10K_0402_5%~D

1 2

RH164 100K_0402_5%~DRH164 100K_0402_5%~D

RH149 need to close to CPU

RH149

RH149

2.2K_0402_5%~D

2.2K_0402_5%~D

1 2

RH358 1K_0402_1%~DRH358 1K_0402_1%~D

DMI & FDI Termination Voltage

DF_TVS

Set to Vss when LOW
Set to Vcc when HIGH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8)

PCH (5/8)

PCH (5/8)

LA-7782

LA-7782

LA-7782

+3.3V_RUN

12

+3.3V_RUN

12
12

DF_TVSDF_TVS_R

0.1

0.1

18 66Friday, June 10, 2011

18 66Friday, June 10, 2011

18 66Friday, June 10, 2011

1

0.1

5

4

3

2

1

LH1

POWER

+1.05V_RUN

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CH30

CH30

CH32

CH32

2

D D

+1.05V_RUN

+1.05V_RUN

C C

+3.3V_RUN

B B

@ RH247

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

1 2

RH247

CH51

CH51

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

2

+1.05V_RUN

1UH_LB2012T1R0M_20%~D

1UH_LB2012T1R0M_20%~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CH46

CH45

CH45

2

2

+1.05V_+1.5V_1.8V_RUN

+1.05V_RUN

CH46

CH44

CH44

+1.05V_RUN_VTT

1

2

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH33

CH33

1

2

1

CH47

CH47

2

1U_0402_6.3V6K~D

1

CH31

CH31

2

+VCCAPLLEXP

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

CH40

CH40

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH48

CH48

+VCCAPLL_FDI

UH4G

UH4G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

POWER

VCC CORE

VCC CORE

VCCIO

VCCIO

FDI

FDI

CRTLVDS

CRTLVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

DMI

DMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

DFT / SPI HVCMOS

VCCADAC

VSSADAC

VCCALVDS
VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

U48

U47

AK36
AK37

AM37
AM38
AP36
AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+VCCADAC

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

CH34

CH34

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

CH103

CH103

2

1

CH43

CH43

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+1.05V_+1.5V_1.8V_RUN

+1.05V_RUN_VCCCLKDMI

1

CH50

CH50
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

CH52

CH52

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+VCCSPI

1

CH54

CH54
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH35

CH35

2

1 2

+VCCDFTERM

LH1

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CH36

CH36

2

+1.8V_RUN_LVDS

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

CH104

CH104

2

+3.3V_RUN

CH49

CH49
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

RH205 0_0603_5%~DRH205 0_0603_5%~D

1

CH106

CH106

2

RH276

@RH276

@

0_0805_5%~D

0_0805_5%~D

PJP66

@PJP66

@

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

RH202 0_0603_5%~DRH202 0_0603_5%~D

RH204 0_0603_5%~D@RH204 0_0603_5%~D@

12

+3.3V_RUN

100NH_HK1608R10J-T_5%_0603~D

100NH_HK1608R10J-T_5%_0603~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CH105

CH105

1

2

+1.05V_RUN_VTT

12

INTEL feedback 0302

12

12

12

INTEL feedback 0307

LH8

LH8

12

0.1uH inductor, 200mA

CPN: SHI0110BJ0L

+1.05V_RUN

+3.3V_RUN

+1.8V_RUN

+3.3V_M

+3.3V_RUN

+3.3V_RUN

+1.8V_RUN

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC3

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1

1.05

1.05

1.1

.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.228

0.063

0.08

0.08

1.7

0.047

1.05VccIO 3.711

VccASW

VccSPI

VccDSW3_3 0.001

1.05

3.3

3.3

0.903

0.01

1.8 0.002VCCDFTERM

3.3VccRTC 2 (mA)

3.3VccSus3_3

3.3VccSusHDA

0.095

0.01

VccVRM 1.5 0.167

1.05VccClkDMI 0.07

1.05VccSSC

VccDIFFCLKN 0.055

1.05

VccALVDS 3.3

0.095

0.001

1.8VccTX_LVDS 0.04

+1.05V_RUN

+VCCAPLL_FDI

1 2

RH195 0.022_0805_1%@RH195 0.022_0805_1%@

+1.5V_RUN +1.05V_+1.5V_1.8V_RUN

RH197 0_0603_5%~DRH197 0_0603_5%~D

A A

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (6/8)

PCH (6/8)

PCH (6/8)
LA-7782

LA-7782

LA-7782

19 66Tuesday, June 07, 2011

19 66Tuesday, June 07, 2011

19 66Tuesday, June 07, 2011

1

0.1

0.1

0.1

of

5

4

3

2

1

+1.05V_RUN

+3.3V_ALW_PCH

+3.3V_ALW2

D D

+1.05V_RUN

C C

+3.3V_RUN

1 2

RH215 0.022_0805_1%RH215 0.022_0805_1%

Note: If EMI concern, pop
with SHI00008S0L, 10UH +-20%

1 2

RH201 0_0402_5%~DRH201 0_0402_5%~D

1 2

RH253 0_0402_5%~D@RH253 0_0402_5%~D@

LH3

@ LH3

@

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

+1.05V_M

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

+1.05V_RUN

@

@

CH58

CH58

2

+3.3V_RUN_VCC_CLKF33

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

@

@

2

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH73

CH73

2

Note: Place VCCDIFFCLKN with a trace
specially for XCLK_RCOMP (RH100.2)

B B

+1.05V_M

RH248 0.022_0805_1%@RH248 0.022_0805_1%@

A A

+1.05V_RUN

1 2

+1.05V_M_VCCSUS

+1.05V_RUN_VTT

+1.05V_RUN

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

5

1

CH85

CH85

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

2

LH6

LH6

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

1 2

LH7

LH7

1

CH96

CH96
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

1

CH94

CH94

+

+

2

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

1 2

RH200 0.022_0805_1%@RH200 0.022_0805_1%@

CH55

CH55

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

@

@

CH57

CH57

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CH64

CH64

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH67

CH67

2

CH74

CH74

1

CH78

CH78

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

CH79

CH79
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

1

CH84

CH84

2

1

1

CH87

CH87

CH86

CH86

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+1.05V_RUN_VCCA_A_DPL

+1.05V_RUN_VCCA_B_DPL

220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH92

CH92

1U_0402_6.3V6K~D

1

CH93

CH93

CH95

CH95

1

+

+

2

2

+VCCACLK

1

2

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CH65

CH65

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CH68

CH68

2

2

+1.05V_+1.5V_1.8V_RUN

+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL

CH81

CH81
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCCSST
+1.05V_M_VCCSUS

1

CH83
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+RTC_CELL

1

2

4

+VCCDSW3_3

+PCH_VCCDSW

+3.3V_RUN_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

@

@

CH61

CH61
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH69

CH69

+VCCRTCEXT

@CH83

@

1

CH88

CH88

CH89

CH89

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

UH4J

UH4J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

1

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

CH90

CH90
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

POWER

POWER

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

VCC3_3[1]
VCC3_3[8]
VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]
VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]
VCCIO[3]
VCCIO[4]

T23
T24
V23
V24
P24

T26

M26

AN23
AN24

P34

N20
N22
P20
P22

AA16
W16
T34

AJ2

AF13

AH13
AH14

AF14
AK1

AF11

AC16
AC17
AD17

T21

V21

T19

P32

VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCSUS3_3[1]

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPCMISC

PCI/GPIO/LPCMISC

VCCAPLLSATA

SATA USB

SATA USB

VCCASW[22]

VCCASW[23]

HDA

HDA

VCCASW[21]

VCCSUSHDA

3

CPURTC

CPURTC

1

CH56

CH56
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

CH59

CH59

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+PCH_V5REF_SUS

+VCCA_USBSUS

+PCH_V5REF_RUN

1

2

1

CH91

CH91

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

2

CH70

CH70
1U_0603_10V7K~D

1U_0603_10V7K~D

+3.3V_RUN

1

CH76

CH76

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+VCCSATAPLL

+1.05V_+1.5V_1.8V_RUN

CH60

CH60

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH66

CH66

2

1

CH72

CH72

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

CH82

CH82
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

2

2

+1.05V_RUN

+1.05V_RUN

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_RUN

CH75

CH75

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH77

CH77
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

@CH80

@

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

+1.05V_M

+3.3V_ALW_PCH

+3.3V_ALW_PCH

CRB 0.7 RH208,RH213 trace width 20mil.

+3.3V_RUN

+1.05V_RUN

LH5

@LH5

@

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

CH80

+1.05V_RUN

+3.3V_ALW_PCH

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

ze Document Number Rev

Size Document Number Rev

Size Document Number Rev

Si

Date: Sheet of

Date: Sheet of

Date: Sheet of

D

D

1 3

QH4

RH208

RH208

RH213

RH213

PCH (7/8)

PCH (7/8)

PCH (7/8)

LA-7782

LA-7782

LA-7782

QH4

+3.3V_ALW_PCH+5V_ALW_PCH

12

+3.3V_RUN+5V_RUN

12

+VCCA_USBSUS

+1.05V_RUN

1

2

21

1

2

21

1

2

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

ALW_ENABLE<43>

10_0402_1%~D

10_0402_1%~D

10_0402_1%~D

10_0402_1%~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

+5V_ALW_PCH+5V_ALW

S

S

1

CH98

CH98

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH62

@CH62

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

20 66Friday, June 10, 2011

20 66Friday, June 10, 2011

20 66Friday, June 10, 2011

12

G

G

DH2

DH2
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

CH63

CH63

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

DH3

DH3
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

CH71

CH71
1U_0603_10V7K~D

1U_0603_10V7K~D

RH278

RH278

20K_0402_5%~D

20K_0402_5%~D

0.1

0.1

0.1