Compal LA-7781P QAL80, Latitude E6430, LA-7781P Dalmore 14 UMA Schematic
A
B
C
D
E
COMPAL CONFIDENTIAL
QA
1 1
PCB NO :
BOM P/N :
GPIO MAP: E4_VC_GPIO_map_rev_1.1
L
A-7781P (DA60000OP10)
4319EK31L01
MODEL NAME :
L80
2 2
Dalmore 14 UMA
I
y Bridge + Panther POINT
@
v
2012-02-24
REV : 1.0 (A00)
@ : Nopop Component
3 3
CONN@ : Connector Component
MB Type
ATG Non-TPM
BOM P/N
L52
L01TPM
L02Non-TPM
1@
2@
5@ATG TPM L51
5@
1@
2@
4 4
M
M
PCB
B
B
PCB
P
P
art Number
art Number
D
D
A60000OP10
A60000OP10
Description
Description
PCB 0LD LA-7781P REV1 M/B UMA
PCB 0LD LA-7781P REV1 M/B UMA
A
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
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A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
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tle
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
C
C
C
ver Sheet
o
o
o
ver Sheet
ver Sheet
L
L
L
-7781
-7781
-7781
A
A
A
E
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
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0
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A
B
ck Diagram
lo
1 1
On IO board
CRT CONN
VGA
VGA
For MB/DOCK
Video Switch
PI3V713-AZLEX
PAGE 23
HDMI CONN
PAGE 25
DOCKING PORT
PAGE 37
D
2 2
EXPRESS
Card
USB10
3 3
AI
U
SB2.0 [3,6]
S
ATA5
D
O
CK LAN
U
SB3.0 [4]
1/2 Mini Card
PP
PCIE5
1/2 Mini Card
PAGE 33
USB8
Smart Card
LVDS CONN
SDXC/MMC
PCIE2
WLAN
PAGE 33 PAGE 33PAGE 34
PAGE 32
Full Mini Card
WWAN
USB5USB4
TDA8034HN
CPU XDP Port
PCH XDP Port
W
Fi ON/OFF
i
RFID
Fingerprint
CONN
SMSC SIO
D
C
/DC Interface
L
E
4 4
D
Thermal
GUARDIAN III
EMC4021
PWM FAN
PAGE 22
PAGE 22
A
ECE5048
B
PAGE 22
Card Reader
OZ600FJ0
PCI Express BUS
F
B
O
P_USB
BC BUS
PCIE1PCIE3
PAGE 38
VGA
DPB
DPC
D
D
P
LVDS
PAGE 32
100MHz
tion
p
China TCM1.2
SSX44B
PAGE 31
USH
BCM5882
USB7
U
SH Module
SMSC KBC
MEC5055
TP CONN
PAGE 40 PAGE 40
PCIE x1
LPC BUS
33MHz
PAGE 39
KB CONN
Ivy Bridge
rPGA CPU
FDI
Lane x 8
I
TEL
N
P
nther Point-M
a
B
G
A
SPI
W25Q64CVSSIG
64M 4K sector
W25Q32BVSSIG
32M 4K sector
Discrete TPM
AT97SC3204
C
Memory BUS (DDR3)
1333/1600 MHz
PAGE 6-11
D
M
I2
L
a
ne x 4
U
SB
PAGE 14-21
PCI Express BUS
H
D Audio I/F
S
-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PAGE 14
PAGE 14
FFS LNG3DM
P
IE4
C
E-Module
PAGE 27
PAGE 31
C
S
ATA
PI5USB1457A USB
Power Share
100MHz
HDD
PAGE 26
PAGE 26
D
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Touch Screen
BT 4.0
PAGE 22
PAGE 40
Camera
SATA Repeater
PS8513B
PAGE 36
PAGE 35
HDA Codec
9
M
D
C
RJ11
on IO board
D
E
PAGE 12-13
T
ough Cable
r
E-SATA
U
SB3.0
U
SB3.0
on IO board
USB 2.0 Port
USB3.0/2.0
USB3.0/2.0+PS
USB Port
PAGE 36
PAGE 35
PAGE 35
Intel Lewisville
DOCK LAN
INT.Speaker
HD93
2
PAGE 28
Combo Jack
D
I
A
D
i
g.
PAGE 28
T
o
Docking side
MIC
T
ough LVDS Cable
r
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
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mpal Electronics, Inc.
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tle
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
U
U
U
MA Block Diagram
M
M
A Block Diagram
A Block Diagram
L
L
L
-7781
-7781
A
A
A
-7781
E
2
2
2
82579LM
LAN SWITCH
PAGE 30
PI3L720
RJ45
on IO board
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
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PAGE 30
1
1
1
0
0
.
.
.0
5
4
3
2
1
POWER STATES
CH
S
H
USB PORT#
0
1
2
3
4
5
6
7
8
9
1
0
11
1
2
3
1
0
1
JUSB1 (Right side Top)
JUSB2 (Right side Bottom)
J
E
DOCKING
WLAN
WWAN
D
O
U
S
JMINI3(Flash)
J
U
E
x
Bluetooth
Camera
LCD Touch
S
L
P
SLP
S3#
S4#
H
IGH HIGH
HIGH
L
O
W HIGH HIGH ON ON ON OFF
LOW HIGH HIGH
LOW
LOW
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
+PWR_SRC_S
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
O
N
ower
p
plane
Signal
State
S
(Full ON) / M0
0
D D
S3 (Suspend to RAM) / M3
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S
3
(Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
P
TABLE
M
C C
State
S
0
S
3
S
L
SLP
S5#
H
+
3
+1.5V_MEM
P
A#
HIGH
HIGH
GH
I
.3V_SUS
ON ON
ON
ALWAYS
PLANE
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
ON
M
PLANE
ON
OFFON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
+
+
3.3V_M
1
.05V_M
ON
ON
+
3
+1.05V_M
(M-OFF)
ON
OFF
CLOCKS
OFF
OFF
O
FF
.3V_M
S
A
TA
SATA 0
ATA 1
S
SATA 2
SATA 3
S
A
TA 4
SATA 5
D
E
STINATION
HDD
O
DD/ E3 Module Bay
N
A
N
A
E
S
ATA
Dock
P
U
DESTINATION
SA1 (Right side ESATA)
CKING
H->BIO
SB (Left side)
press card
B
O
I
NA
S5 S4/AC
S
5
S4/AC don't exist
B B
A A
5
ON
OFF
OFFOFF
OFF
OFF
ON
OFF
OFFOFF
need to update Power Status and PM
Table
4
P
C
U
A DP/HDMI Port
M
Port B
Port C
P
o
rt D
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Connetion
MB HDMI Conn
Dock DP port 2
Dock DP port 1
2
I EXPRESS
Lane 1
L
ane 2
Lane 3
Lane 4
L
ne 5
a
Lane 6
L
ne 7
a
MINI CARD-1 WWAN
M
Express card
E
1
MMI
10/100/1G LOM
Lane 8 None
D
ELL CONFIDENTIAL/PROPRIETARY
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tle
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
D
STINATION
E
NI CARD-2 WLAN
I
3 Module Bay (USB3)
/2vMINI CARD-3 PCIE
C
C
C
mpal Electronics, Inc.
o
o
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mpal Electronics, Inc.
mpal Electronics, Inc.
I
I
I
ndex and Config.
n
n
dex and Config.
dex and Config.
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
1
0
0
.
.
3
3
3
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
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5
E
N_INVPWR
D D
4
F
D
C654P
(
21)
Q
+
B
L_PWR_SRC
3
2
DC_EN
O
O_SLP_S3#
I
S
M
1
ADAPTER
S
I3456BDVSI3456BDV
+
V_MOD
5
(Q30)(Q27)
S
I
(Q42)
ARD_MISC_PWREN
C
M
3456
S
I
(Q40)
ARD_WWAN_PWREN
C
M
3456
B
A
TTERY
+PWR_SRC
1
.
05V_0.8V_PWROK
I
SL95836
(PU700)
+
CC_GFXCORE
V
+
5
V_HDD
A
LWON
IO_SLP_A#
S
S
I
3456
(
58)
Q
+3.3V_M
+
.3V_WWAN
3
+
O_SLP_S3#
I
S
+
5
3.3V_FLASH
V_RUN
C C
B B
A A
I
L95836
S
(
PU700)
05V_0.8V_PWROK
.
1
+
CC_CORE
V
C
H
ARGER
T
P
S51212
T
(PU500)
U_VTT_ON
P
C
+
1
.05V_RUN_VTT +1.05V_M
S
O_SLP_S3#
I
S
I
4164
(Q63)
S51212
P
(PU400)
O_SLP_A#
I
S
P
op option
S
O_SLP_S3#
I
A
O
4728
(QC3)
R
T
8207
(
P
U200)
R_ON
D
D
+
1
.5V_MEM
S
O_SLP_S3#
I
NTGS4141N
(
59)
Q
IO_SLP_S3#
S
S
8033
Y
(
P
U300)
+
1
0.75V_DDR_VTT_ON
.8V_RUN
T
P
(
P
+
V
05V_VTTPWRGD
.
1
S51461
U600)
CC_SA
S
I
(Q38)
+
3
.3V_WLAN
X_EN_WOWL
U
A
3456
H_ALW_ON
C
P
S
I
3456
(Q49)
+
.3V_ALW_PCH
3
RT8205
(
PU100)
+
3
.3V_ALW
S
1
3456
(Q54)
+
3
.3V_SUS
S_ON
U
S
+
3.3V_M
+
V_ALW
5
O_SLP_LAN#
I
S
S
I3456
(Q34) (U78)
+
3
.3V_LAN
P
p option
o
+
.3V_RUN
3
O_SLP_S3#
I
S
TPS22966
+
.05V_RUN
1
5
+
1.0V_LAN
+
1
.5V_RUN+1.5V_CPU_VDDQ
4
+
0
.75V_DDR_VTT
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
ower Rail
o
o
wer Rail
wer Rail
L
L
L
-7781
-7781
A
A
A
-7781
4
4
4
1
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1
1
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1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
5
S
MBUS Address [0x9a]
B
4
A3
B5
A4
A56
MEM_SMBCLK
M
M_SMBDATA
E
L
N_SMBCLK
A
LAN_SMBDATA
2.2K
2
2K
.
D
O
CK_SMB_CLK
D
O
CK_SMB_DAT
L
CD_SMBCLK
LCD_SMDATA
P
B
AT_SMBCLK
PBAT_SMBDAT
+
3.3V_ALW_PCH
H14
C
9
P
H
D D
C C
C
C
8
G12
E
14M16
S
M
L1_SMBDATA
S
ML1_SMBCLK
B
6A5
3
A
3A
1A
1A
1B
1B
K
BC
1C1CB59
2.
2.2K
2
.
2.2K
2K
2K
2
2
2
2.2K
2
.
.2K
.
2
2
.
4
2K
2K
2K
.
2K
.
2K
+3.3V_ALW_PCH
+
3.3V_LAN
2
8
3
1
LOM
+
3.3V_ALW
+
3.3V_ALW
+
3.3V_ALW
1
0 ohm
0
1
0
0 ohm
2N7002
2
7002
N
S
BUS Address [C8]
M
127
1
29
7
6
D
OCKING
BATTERY
CONN
3
S
MBUS Address
A
R_EC: 0x48
P
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
S
MBUS Address [0x16]
2
2
202
2
2
02
00
0
0
5
3
5
1
5
3
5
1
30
3
2
D
IMMA
D
IMMB
XDP1
XDP2
1
0
K
1
K
0
4
G
6
SMBUS Address [A0]
SMBUS Address [A4]
S
MBUS Address [TBD]
SMBUS Address [TBD]
+
3.3V_RUN
Sensor
W
AN
W
S
M
BUS Address [3B]
SMBUS Address [TBD]
1
+
A
2.2K
50
U
B53
A
9
4
B52
B50
A47
B
7
A7
SH_SMBCLK
U
S
H_SMBDAT
CARD_SMBCLK
CARD_SMBDAT
C
HARGER_SMBCLK
CHARGER_SMBDAT
BAY_SMBDAT
BAY_SMBCLK
2
.
2K
2
2K
.
2
.2K
2
.
2K
2
.
2K
2
.
2K
4
1E
B B
M
E
C 5065
A A
1E
2B
2B
1G
1G
2
D
2
D
5
3.3V_ALW
+
3.3V_SUS
+
3.3V_ALW
+
3.3V_ALW
M
9
9
L
U
S
H
S
M
BUS Address [0xa4]
7
8
Express card
9
8
C
h
arger
SMBUS Address [0x12]
S
BUS Address [TBD]
M
2
9
E
3 Module Bay
3
0
3
S
M
BUS Address [0xd2]
C
C
C
mpal Electronics, Inc.
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o
o
mpal Electronics, Inc.
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
mpal Electronics, Inc.
S
S
S
MBUS TOPOLOGY
M
M
BUS TOPOLOGY
BUS TOPOLOGY
L
L
L
-7781
-7781
A
A
A
-7781
5
5
5
1
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
4
3
2
1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
+
.05V_RUN_VTT
1
12
C
C
2
2
R
R
24.9_0402_1%~D
D D
DM
D
M
I_CRX_PTX_N0<16>
D
M
I_CRX_PTX_N1<16>
D
M
I_CRX_PTX_N2<16>
D
M
I_CRX_PTX_N3<16>
D
I_CRX_PTX_P0<16>
M
D
I_CRX_PTX_P1<16>
M
D
M
I_CRX_PTX_P2<16>
D
MI_CRX_PTX_P3<16>
D
M
I_CTX_PRX_N0<16>
D
I_CTX_PRX_N1<16>
M
D
I_CTX_PRX_N2<16>
M
D
I_CTX_PRX_N3<16>
M
D
M
I_CTX_PRX_P0<16>
D
M
I_CTX_PRX_P1<16>
D
M
I_CTX_PRX_P2<16>
D
I_CTX_PRX_P3<16>
M
F
D
I_CTX_PRX_N0<16>
F
D
I_CTX_PRX_N1<16>
F
I_CTX_PRX_N2<16>
D
F
I_CTX_PRX_N3<16>
D
F
D
C C
B B
I_CTX_PRX_N4<16>
F
D
I_CTX_PRX_N5<16>
F
I_CTX_PRX_N6<16>
D
F
I_CTX_PRX_N7<16>
D
F
D
I_CTX_PRX_P0<16>
F
D
I_CTX_PRX_P1<16>
F
I_CTX_PRX_P2<16>
D
F
D
I_CTX_PRX_P3<16>
F
DI_CTX_PRX_P4<16>
F
D
I_CTX_PRX_P5<16>
F
I_CTX_PRX_P6<16>
D
F
I_CTX_PRX_P7<16>
D
F
D
I_FSYNC0<16>
F
I_FSYNC1<16>
D
F
D
I_INT<16>
F
I_LSYNC0<16>
D
F
D
I_LSYNC1<16>
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
I_CRX_PTX_N0
D
M
I_CRX_PTX_N1
D
I_CRX_PTX_N2
M
D
MI_CRX_PTX_N3
D
M
I_CRX_PTX_P0
D
I_CRX_PTX_P1
M
D
I_CRX_PTX_P2
M
D
M
I_CRX_PTX_P3
D
MI_CTX_PRX_N0
D
I_CTX_PRX_N1
M
D
I_CTX_PRX_N2
M
D
I_CTX_PRX_N3
M
D
I_CTX_PRX_P0
M
D
M
I_CTX_PRX_P1
D
M
I_CTX_PRX_P2
D
I_CTX_PRX_P3
M
F
I_CTX_PRX_N0
D
F
I_CTX_PRX_N1
D
F
I_CTX_PRX_N2
D
F
I_CTX_PRX_N3
D
F
I_CTX_PRX_N4
D
F
D
I_CTX_PRX_N5
F
I_CTX_PRX_N6
D
F
D
I_CTX_PRX_N7
F
I_CTX_PRX_P0
D
F
I_CTX_PRX_P1
D
F
I_CTX_PRX_P2
D
F
I_CTX_PRX_P3
D
F
D
I_CTX_PRX_P4
F
D
I_CTX_PRX_P5
F
D
I_CTX_PRX_P6
F
I_CTX_PRX_P7
D
F
I_FSYNC0
D
F
DI_FSYNC1
F
I_INT
D
F
I_LSYNC0
D
F
I_LSYNC1
D
E
P_COMP
D
PU1A
PU1A
C
C
J
J
B27
M
I_RX#[0]
D
B25
M
I_RX#[1]
D
A25
M
I_RX#[2]
D
B24
M
I_RX#[3]
D
B28
I_RX[0]
M
D
B26
I_RX[1]
M
D
A24
I_RX[2]
M
D
B23
I_RX[3]
M
D
G21
I_TX#[0]
M
D
E22
I_TX#[1]
M
D
F21
I_TX#[2]
M
D
D21
I_TX#[3]
M
D
G22
I_TX[0]
M
D
D22
I_TX[1]
M
D
F20
I_TX[2]
M
D
C21
I_TX[3]
M
D
A21
D
I0_TX#[0]
F
H19
D
I0_TX#[1]
F
E19
D
I0_TX#[2]
F
F18
D
I0_TX#[3]
F
B21
I1_TX#[0]
D
F
C20
I1_TX#[1]
D
F
D18
D
I1_TX#[2]
F
E17
I1_TX#[3]
D
F
A22
D
I0_TX[0]
F
G19
D
I0_TX[1]
F
E20
I0_TX[2]
D
F
G18
I0_TX[3]
D
F
B20
I1_TX[0]
D
F
C19
I1_TX[1]
D
F
D19
I1_TX[2]
D
F
F17
I1_TX[3]
D
F
J18
DI0_FSYNC
F
J17
I1_FSYNC
D
F
H20
I_INT
D
F
J19
D
I0_LSYNC
F
H17
D
I1_LSYNC
F
A18
e
D
P_COMPIO
A17
e
D
P_ICOMPO
B16
e
D
P_HPD#
C15
e
D
P_AUX
D15
e
P_AUX#
D
C17
e
P_TX[0]
D
F16
e
P_TX[1]
D
C16
e
P_TX[2]
D
G15
e
P_TX[3]
D
C18
e
P_TX#[0]
D
E16
e
D
P_TX#[1]
D16
e
D
P_TX#[2]
F15
e
D
P_TX#[3]
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
G_ICOMPI
G_ICOMPO
G_RCOMPO
G_RX#[0]
PE
G_RX#[1]
PE
E
G_RX#[2]
P
G_RX#[3]
PE
G_RX#[4]
PE
G_RX#[5]
PE
G_RX#[6]
PE
G_RX#[7]
PE
G_RX#[8]
PE
G_RX#[9]
PE
G_RX#[10]
G_RX#[11]
G_RX#[12]
G_RX#[13]
G_RX#[14]
G_RX#[15]
PE
G_RX[0]
PE
G_RX[1]
PE
G_RX[2]
PE
G_RX[3]
PE
G_RX[4]
P
G_RX[5]
E
P
G_RX[6]
E
P
G_RX[7]
E
P
G_RX[8]
E
P
G_RX[9]
E
P
G_RX[10]
E
P
E
G_RX[11]
P
E
G_RX[12]
P
E
G_RX[13]
P
G_RX[14]
E
P
G_RX[15]
E
P
G_TX#[0]
E
P
G_TX#[1]
E
P
G_TX#[2]
E
P
G_TX#[3]
E
P
E
G_TX#[4]
P
E
G_TX#[5]
P
E
G_TX#[6]
P
G_TX#[7]
E
P
G_TX#[8]
E
P
G_TX#[9]
E
P
E
G_TX#[10]
P
E
G_TX#[11]
P
E
G_TX#[12]
P
G_TX#[13]
E
P
G_TX#[14]
E
P
G_TX#[15]
E
P
E
G_TX[0]
P
E
G_TX[1]
P
G_TX[2]
E
P
G_TX[3]
E
P
G_TX[4]
E
P
G_TX[5]
E
P
E
G_TX[6]
P
E
G_TX[7]
P
E
G_TX[8]
P
G_TX[9]
E
P
G_TX[10]
E
P
E
G_TX[11]
P
E
G_TX[12]
P
E
G_TX[13]
P
G_TX[14]
E
P
E
G_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PE
PE
PE
DMI
DMI
ntel(R) FDI
ntel(R) FDI
I
I
DP
DP
e
e
PE
PE
PE
PE
PE
PE
CI EXPRESS* - GRAPHICS
CI EXPRESS* - GRAPHICS
P
P
24.9_0402_1%~D
P
E
G_COMP
P
G Compensation
E
P
EG_ICOMPI and R COMPO signals s hould be shorte d and routed
with - max leng th = 500 mils - typical impeda nce = 43 mohms
PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils
- typical imped ance = 14.5 moh ms
J
J
PU1I
PU1I
C
C
T35
V
S
S161
T34
V
S
S162
T33
V
S163
S
T32
V
S164
S
T31
V
SS165
T30
V
S
S166
T29
V
S
S167
T28
V
S168
S
T27
V
S169
S
T26
V
S
S170
P9
V
S
S171
P8
V
S
S172
P6
V
S
S173
P5
V
S
S174
P3
V
S175
S
P2
V
S176
S
N35
V
SS177
N34
V
S
S178
N33
V
S179
S
N32
V
S180
S
N31
V
S
S181
N30
V
S
S182
N29
V
S183
S
N28
V
S184
S
N27
V
S185
S
N26
V
S
S186
M34
V
S187
S
L33
V
S188
S
L30
V
SS189
L27
V
S
S190
L9
V
S191
S
L8
V
S192
S
L6
V
S
S193
L5
V
S194
S
L4
V
S195
S
L3
V
S
S196
L2
V
S
S197
L1
V
S198
S
K35
V
SS199
K32
V
S
S200
K29
V
S
S201
K26
S202
S
V
J34
S
S203
V
J31
S
S204
V
H33
S
S205
V
H30
S206
S
V
H27
SS207
V
H24
S208
S
V
H21
S
S209
V
H18
S
S210
V
H15
S
S211
V
H13
S
S212
V
H10
S
S213
V
H9
S
S214
V
H8
S215
S
V
H7
S216
S
V
H6
S217
S
V
H5
S218
S
V
H4
S219
S
V
H3
S
S220
V
H2
S
S221
V
H1
S
S222
V
G35
S
S223
V
G32
S224
S
V
G29
S
S225
V
G26
SS226
V
G23
S227
S
V
G20
S228
S
V
G17
S229
S
V
G11
S230
S
V
F34
S231
S
V
F31
S232
S
V
F29
S
S233
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
F22
S234
S
V
F19
S235
S
V
E30
S
S236
V
E27
S
S237
V
E24
S
S238
V
E21
S239
S
V
E18
S240
S
V
E15
S241
S
V
E13
S242
S
V
E10
S
S243
V
E9
S
S244
V
E8
S
S245
V
E7
S246
S
V
E6
S
S247
V
E5
S
S248
V
E4
S
S249
V
E3
SS250
V
E2
S251
S
V
E1
S252
S
V
D35
S253
S
V
D32
S254
S
V
D29
S255
S
V
D26
S
S256
V
D20
S
S257
V
D17
S
S258
V
C34
S
S259
V
C31
S
S260
V
C28
S
S261
V
C27
S262
S
V
C25
S263
S
V
C23
S264
S
V
C10
S265
S
V
C1
S266
S
V
B22
S267
S
V
B19
S268
S
V
V
V
SS
S
S
B17
S269
S
V
B15
S270
S
V
B13
S
S271
V
B11
S272
S
V
B9
S
S273
V
B8
S
S274
V
B7
S
S275
V
B5
S
S276
V
B3
S
S277
V
B2
S
S278
V
A35
S
S279
V
A32
S
S280
V
A29
S
S281
V
A26
S
S282
V
A23
S
S283
V
A20
S
S284
V
A3
S
S285
V
D
Compensation
P
+
.05V_RUN_VTT
1
12
R
R
C1
C1
24.9_0402_1%~D
A A
e
D
P_COMPIO and IC OMPO signals sh ould be shorted near
balls and route d with typical impedance <25 m ohms
5
24.9_0402_1%~D
E
DP_COMP
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
tle
i
i
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
I
I
I
y Bridge (1/6)
v
v
v
y Bridge (1/6)
y Bridge (1/6)
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
1
.
0
0
0
.
6
6
6
.
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
llow DG Rev0.71 SM_DRAMPWROK topology
Fo
+
3
.3V_ALW_PCH
C
C
156 0.1U_0402_25V6K~D
156 0.1U_0402_25V6K~D
C
C
1 2
5
U
U
C
C
2
2
1
U
NPWROK<39,40>
R
+
.3V_ALW_PCH
3
D D
+
.05V_RUN_VTT
1
C C
B B
ffered reset to CPU
u
B
A A
P
1 2
R
R
18 200_0402_1%~D
18 200_0402_1%~D
C
C
M
P
2
1
C
C
126 56_0402_5%~D@
126 56_0402_5%~D@
R
R
1 2
R
R
128 49.9_0402_1%~D@
128 49.9_0402_1%~D@
C
C
1 2
44 62_0402_5%~D
44 62_0402_5%~D
C
C
R
R
ollow check list 0.5
F
PROCHOT#<40,51,52>
_
H
_
THERMTRIP#<22>
H
_
CPUPWRGD<18>
H
C
H_PLTRST#<14,17>
_DRAM_PWRGD<16>
H
_THERMTRIP#
H
_
CATERR#
H
PROCHOT#
_
SNB_IVB#<18>
_
H
P
U_DETECT#<39>
C
CI_EC<40>
E
P
R1 TOPOLOGY
V
1 2
R
R
C
C
57 56_0402_5%~D
57 56_0402_5%~D
1 2
R
R
129 0_0402_5%~D@
129 0_0402_5%~D@
C
C
_
PM_SYNC<16>
H
1 2
R
R
C
C
25 0_0402_5%~D@
25 0_0402_5%~D@
5
1
2
3
P
B
2
A
N_ON_CPU1.5VS3#<11,42>
U
R
H
_CATERR#
H
_PROCHOT#_R
C
H
_THERMTRIP#_R
H
PM_SYNC
_
V
C
P
M
P
C
H_PLTRST#_R
U
U
1
C
C
1
V
N
C
C
C
A
G
Y
D
N
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
pen drain buffer
O
R
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
ose to JCBU1
l
CPWRGOOD_0_R
_DRAM_PWRGD_CP U
+
3
.3V_RUN
1
2
5
P
H_PLTRST#_BUF
C
4
NPWROK_AND
U
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+
.5V_CPU_VDDQ
1
RC
64
39_0402_5%~D
39_0402_5%~D
1 2
13
D
D
Q
Q
C
2
G
G
NTEL suggest RC64 and QC1 NO stuff by default
I
J
J
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
+
1
.05V_RUN_VTT
C
C
C
C
140
140
C
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
C
C
PU1B
PU1B
R
OC_SELECT#
P
K
TOCC#
S
TERR#
A
C
E
CI
P
OCHOT#
R
P
ERMTRIP#
H
T
_SYNC
M
P
COREPWRGOOD
N
U
M
_DRAMPWROK
S
SET#
E
R
75_0402_1%~D
75_0402_1%~D
R
R
12
C
C
4
4
1 2
R
R
C10 43_0402_5%~D
C10 43_0402_5%~D
4
12
RC
RC
12
12
200_0402_1%~D
200_0402_1%~D
1 2
28 130_0402_1%~D
28 130_0402_1%~D
C
C
R
R
@RC64
@
1
@
1
@
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
P
C
H_PLTRST#_R
4
P
_DRAM_PWRGD_CP U
M
P
D
P
LL_REF_CLK#
D
LOCKS
LOCKS
C
C
M
S
S
S
S
DR3
DR3
D
D
MISC
MISC
TAG & BPM
TAG & BPM
J
J
C
B
C
B
LL_REF_CLK
_DRAMRST#
M
_RCOMP[0]
_RCOMP[1]
M
_RCOMP[2]
M
DY#
R
P
EQ#
R
P
T
T
R
ST#
T
T
B
D
P
M#[0]
B
P
M#[1]
B
M#[2]
P
B
M#[3]
P
B
M#[4]
P
B
M#[5]
P
B
M#[6]
P
B
P
M#[7]
B
3
+
.3V_ALW_PCH
3
1
124
@RC124
@
RC
1K_0402_5%~D
1K_0402_5%~D
2
S
S_PWROK_XDP
Y
e resistor for HOOK2 should be placed
h
T
such that the s tub is very sma ll on CFG0 net
H
_
CPUPWRGD
S
O_PWRBTN#_R<14,16>
I
C
FG0_R
S_PWROK<16,39>
Y
S
R_XDP_WAN_SM BDAT<12,13,14,15,27,34>
D
D
R_XDP_WAN_SM BCLK<12,13,14,15,27,34>
D
D
C
P
LK
LK#
C
M
D
T
D
R#
C
U_DMI#
P
A27
C
P
U_DPLL
A16
C
P
U_DPLL#
A15
emove DPLL Ref clock (for eDP only)
R
D
R3_DRAMRST#_CPU
D
R8
S
M_RCOMP0
AK1
S
_RCOMP1
M
A5
S
_RCOMP2
M
A4
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
X
P_PRDY#
D
AP29
X
D
P_PREQ#
AP27
X
P_TCLK
D
AR26
K
X
D
P_TMS
AR27
S
X
P_TRST#
D
AP30
X
P_TDI_R
D
AR28
I
X
P_TDO_R
D
AP26
O
X
P_DBRESET#_R
D
AL35
X
D
P_OBS0_R
AT28
X
D
P_OBS1_R
AR29
X
D
P_OBS2_R
AR30
X
DP_OBS3_R
AT30
X
P_OBS4_R
D
AP32
X
P_OBS5_R
D
AR31
X
P_OBS6_R
D
AT31
X
D
P_OBS7_R
AR32
or ESD concern, please put near CPU
F
V
void stub in th e PWRGD path
A
while placing r esistors RC25 & RC130
U_DMI
A28
1 2
13 0_0402_5%~D@
13 0_0402_5%~D@
C
C
R
R
1 2
C
C
15 0_0402_5%~D@
15 0_0402_5%~D@
R
R
1 2
R
R
16 1K_0402_5%~D
16 1K_0402_5%~D
C
C
1 2
C
C
17 1K_0402_5%~D
17 1K_0402_5%~D
R
R
a
x 500mils
M
1 2
R
R
27 0_0402_5%~D@
E
E27 0_0402_5%~D@
1 2
28 0_0402_5%~D@
28 0_0402_5%~D@
E
E
R
R
1 2
R
R
29 0_0402_5%~D@
E
E
29 0_0402_5%~D@
1 2
30 0_0402_5%~D@
E
E
30 0_0402_5%~D@
R
R
1 2
E31 0_0402_5%~D@RE31 0_0402_5%~D@
R
1 2
32 0_0402_5%~D@
32 0_0402_5%~D@
E
E
R
R
2
26 0_0402_5%~D@
26 0_0402_5%~D@
1 2
30 0_0402_5%~D@
30 0_0402_5%~D@
1 2
31 0_0402_5%~D@
31 0_0402_5%~D@
1 2
33 0_0402_5%~D@
33 0_0402_5%~D@
1 2
34 0_0402_5%~D@
34 0_0402_5%~D@
1 2
36 0_0402_5%~D@
36 0_0402_5%~D@
1 2
37 0_0402_5%~D@
37 0_0402_5%~D@
1 2
38 0_0402_5%~D@
38 0_0402_5%~D@
1 2
39 0_0402_5%~D@
39 0_0402_5%~D@
12
3
1
C
C
130
130
R
R
10K_0402_5%~D
10K_0402_5%~D
R
R
C
C
C
C
R
R
R
R
C
C
R
R
C
C
R
R
C
C
C
C
R
R
C
C
R
R
C
C
R
R
R
R
C
C
CPWRGOOD_0_R
C
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R
R
C
C
R
R
C
C
R
R
C
C
C
C
R
R
R
R
125 0_0402_5%~D@
125 0_0402_5%~D@
C
C
127 0_0402_5%~D@
127 0_0402_5%~D@
C
C
R
R
L
K_CPU_DMI <15>
C
K_CPU_DMI# <15>
L
C
C
C
R
R
4.99K_0402_1%~D
4.99K_0402_1%~D
X
P_PREQ#_R
D
X
P_TCLK_R
D
X
D
P_TMS_R
X
D
P_TRST#_R
X
P_TDI
D
X
D
P_TDO
X
P_DBRESET#
D
X
D
P_OBS0
X
P_OBS1
D
X
P_OBS2
D
X
DP_OBS3
X
P_OBS4
D
X
D
P_OBS5
X
P_OBS6
D
X
P_OBS7
D
+1
.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
ace near JXDP1
l
P
1 2
5 1K_0402_5%~D@
5 1K_0402_5%~D@
1 2
6 0_0402_5%~D@
6 0_0402_5%~D@
1 2
7 1K_0402_5%~D@
7 1K_0402_5%~D@
1 2
9 0_0402_5%~D@
9 0_0402_5%~D@
1 2
1 2
+
1
.05V_RUN_VTT
1
50
50
2
S
_RCOMP2
M
S
_RCOMP1
M
S
M
_RCOMP0
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
C
C
C
C
C
C
66
66
65
65
2
F
G10<9>
C
G11<9>
F
C
1 2
48 0_0402_5%~D@
C
RC
48 0_0402_5%~D@
R
S
S
G
G
2
1
2
D
R_HVREF_RST_PCH<15>
D
R_HVREF_RST_GATE<40>
D
D
X
D
P_DBRESET# <14,16>
2
X
D
P_PREQ#_R
X
D
P_PRDY#
X
P_OBS0
D
X
P_OBS1
D
X
DP_OBS2
X
D
P_OBS3
C
F
G10
C
F
G11
X
D
P_OBS4
X
D
P_OBS5
X
P_OBS6
D
X
P_OBS7
D
H
CPUPWRGD_XDP
_
C
D_PWRBTN#_XDP
F
X
D
P_HOOK2
S
Y
S_PWROK_XDP
D
D
R_XDP_SMBDAT_R1
D
R_XDP_SMBCLK_R1
D
X
D
P_TCLK_R
D
D
13
Q
Q
C
C
2
2
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
D
R_HVREF_RST
D
C
C
177
C
C
177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
46 0_0402_5%~D@RC46 0_0402_5%~D@
RC
47 0_0402_5%~D@
C
C
47 0_0402_5%~D@
R
R
12
12
42
43
45
42
C
C
R
R
140_0402_1%~D
140_0402_1%~D
45
43
C
C
RC
RC
R
R
25.5_0402_1%~D
25.5_0402_1%~D
2
+
.05V_RUN_VTT
1
R3_DRAMRST# <12>
D
D
1 2
1 2
12
200_0402_1%~D
200_0402_1%~D
J
J
DP1
DP1
X
X
1
G
D0
N
3
O
B
SFN_A0
5
O
B
SFN_A1
7
G
D2
N
9
O
SDATA_A0
B
11
O
B
SDATA_A1
13
G
N
D4
15
O
SDATA_A2
B
17
O
SDATA_A3
B
19
G
N
D6
21
O
B
SFN_B0
23
O
B
SFN_B1
25
D8
N
G
27
SDATA_B0
B
O
29
B
SDATA_B1
O
31
N
D10
G
33
B
SDATA_B2
O
35
SDATA_B3
B
O
37
D12
N
G
39
W
RGOOD/HOOK0
P
41
O
OK1
H
43
C
C_OBS_AB
V
45
O
OK2
H
47
OK3
O
H
49
D14
N
G
51
A
D
S
53
C
L
S
55
C
K1
T
57
C
K0
T
59
D16
N
G
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
X
P_RST#_R
D
C
K_XDP
L
H
H
107 0_0402_5%~D@
107 0_0402_5%~D@
R
R
C
L
K_XDP#
106 0_0402_5%~D@
106 0_0402_5%~D@
H
H
R
R
L
K_XDP_ITP<9>
C
K_XDP_ITP#<9>
L
C
D
tle
Title
i
i
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
+
.05V_RUN_VTT
1
2
N
D1
G
B
SFN_C0
O
SFN_C1
B
O
D3
N
G
SDATA_C0
B
O
B
SDATA_C1
O
N
D5
G
B
SDATA_C2
O
SDATA_C3
B
O
D7
N
G
SFN_D0
B
O
B
SFN_D1
O
D9
N
G
SDATA_D0
B
O
SDATA_D1
B
O
N
D11
G
B
SDATA_D2
O
B
SDATA_D3
O
N
D13
G
PCLK/HOOK4
T
I
PCLK#/HOOK5
T
I
C_OBS_CD
C
V
SET#/HOOK6
E
R
R#/HOOK7
B
D
N
D15
G
D
0
T
R
ST#
T
D
I
T
S
M
T
D17
N
G
1 2
R
R
8 1K_0402_5%~DPXDP@
8 1K_0402_5%~DPXDP@
C
C
1 2
1 2
R
R
R
R
D
R_HVREF_RST <12>
D
3 control
M
/PD for JTAG signals
U
P
X
P_DBRESET#
D
X
P_TMS
D
X
D
P_TDI_R
X
P_PREQ#
D
X
D
P_TDO_R
X
D
P_TCLK
X
D
P_TRST#
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
C
G16
F
4
C
G17
F
6
8
CF
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1 2
109 0_0402_5%~D@
109 0_0402_5%~D@
H
H
1 2
H
H
108 0_0402_5%~D@
108 0_0402_5%~D@
o
o
o
v
v
v
I
I
I
L
L
L
G0_R
C
G1_R
F
C
G2
F
C
G3
F
C
F
G8
C
F
G9
C
G4
F
C
G5_R
F
C
G6
F
C
G7
F
C
K_XDP
L
C
K_XDP#
L
X
DP_RST#_R
X
P_DBRESET#
D
X
P_TDO
D
X
P_TRST#_R
D
X
P_TDI
D
X
P_TMS_R
D
19 1K_0402_5%~D
19 1K_0402_5%~D
C
C
R
R
C
C
R
R
C
C
R
R
C
C
R
R
C
C
R
R
R
R
C
C
R
R
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
y Bridge (1/6)
y Bridge (1/6)
y Bridge (1/6)
-7781
A
A
A
-7781
-7781
12
27 51_0402_1%~D
27 51_0402_1%~D
12
29 51_0402_1%~D
29 51_0402_1%~D
12
32 51_0402_1%~D@
32 51_0402_1%~D@
12
35 51_0402_1%~D
35 51_0402_1%~D
12
40
40
12
51_0402_1%~D
1
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
41
41
F
G16 <9>
C
F
G17 <9>
C
C
G0_R <9>
F
G1_R <9>
F
C
C
F
G2 <9>
C
G3 <9>
F
F
G8 <9>
C
G9 <9>
F
C
C
G4 <9>
F
C
G5_R <9>
F
C
F
G6 <9>
G7 <9>
F
C
TRST_XDP# <17>
L
P
K_CPU_ITP <15>
L
C
K_CPU_ITP# <15>
L
C
+
3
+
.05V_RUN_VTT
1
7
7
7
o
o
o
.3V_RUN
f
f
f
0
.
.
.
0
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
5
JC
JC
PU1C
PU1C
D D
C C
B B
R_A_D[0..63]<12>
D
D
D
R_A_BS0<12>
D
D
R_A_BS1<12>
D
DR_A_BS2<12>
D
D
R_A_CAS#<12>
D
D
R_A_RAS#<12>
D
DR_A_WE#<12>
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DR_A_D6
D
D
D
D
D
D
D
D
D
D
D
DR_A_D12
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DR_A_D38
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
R_A_BS0
D
D
R_A_BS1
D
D
D
R_A_BS2
D
D
R_A_CAS#
D
R_A_RAS#
D
D
R_A_WE#
D
R_A_D0
R_A_D1
R_A_D2
R_A_D3
R_A_D4
R_A_D5
R_A_D7
R_A_D8
R_A_D9
R_A_D10
R_A_D11
R_A_D13
R_A_D14
R_A_D15
R_A_D16
R_A_D17
R_A_D18
R_A_D19
R_A_D20
R_A_D21
R_A_D22
R_A_D23
R_A_D24
R_A_D25
R_A_D26
R_A_D27
R_A_D28
R_A_D29
R_A_D30
R_A_D31
R_A_D32
R_A_D33
R_A_D34
R_A_D35
R_A_D36
R_A_D37
R_A_D39
R_A_D40
R_A_D41
R_A_D42
R_A_D43
R_A_D44
R_A_D45
R_A_D46
R_A_D47
R_A_D48
R_A_D49
R_A_D50
R_A_D51
R_A_D52
R_A_D53
R_A_D54
R_A_D55
R_A_D56
R_A_D57
R_A_D58
R_A_D59
R_A_D60
R_A_D61
R_A_D62
R_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AE8
AD9
AF9
C5
S
_DQ[0]
A
D5
S
A
_DQ[1]
D3
S
_DQ[2]
A
D2
S
_DQ[3]
A
D6
S
_DQ[4]
A
C6
S
_DQ[5]
A
C2
S
A
_DQ[6]
C3
S
A
_DQ[7]
F10
S
A
_DQ[8]
F8
S
_DQ[9]
A
S
_DQ[10]
A
G9
S
_DQ[11]
A
F9
S
_DQ[12]
A
F7
S
A
_DQ[13]
G8
S
A
_DQ[14]
G7
S
A
_DQ[15]
K4
S
A
_DQ[16]
K5
S
_DQ[17]
A
K1
S
_DQ[18]
A
J1
S
_DQ[19]
A
J5
S
A
_DQ[20]
J4
S
A
_DQ[21]
J2
S
A
_DQ[22]
K2
S
A
_DQ[23]
M8
S
_DQ[24]
A
S
_DQ[25]
A
N8
S
A
_DQ[26]
N7
S
A
_DQ[27]
S
_DQ[28]
A
M9
S
_DQ[29]
A
N9
S
_DQ[30]
A
M7
S
A
_DQ[31]
S
A
_DQ[32]
S
_DQ[33]
A
S
_DQ[34]
A
S
_DQ[35]
A
S
A
_DQ[36]
S
A
_DQ[37]
AJ5
S
A
_DQ[38]
AJ6
S
_DQ[39]
A
AJ8
S
A_DQ[40]
S
A
_DQ[41]
AJ9
S
A
_DQ[42]
S
_DQ[43]
A
S
_DQ[44]
A
S
A
_DQ[45]
AL9
S
A
_DQ[46]
AL8
S
_DQ[47]
A
S
_DQ[48]
A
S
A
_DQ[49]
S
A
_DQ[50]
S
_DQ[51]
A
S
_DQ[52]
A
S
_DQ[53]
A
S
A
_DQ[54]
S
_DQ[55]
A
S
_DQ[56]
A
S
A
_DQ[57]
S
A
_DQ[58]
S
_DQ[59]
A
S
A
_DQ[60]
S
A
_DQ[61]
S
_DQ[62]
A
S
A
_DQ[63]
_BS[0]
SA
SA
_BS[1]
V6
SA_BS[2]
_CAS#
SA
SA
_RAS#
SA
_WE#
4
CLK_DDR0
_
M
AB6
S
_CK[0]
A
_CLK#[0]
SA
S
_CKE[0]
A
SA
_CK[1]
SA
_CLK#[1]
SA
_CKE[1]
S
A
_CK[2]
S
A
_CLK#[2]
S
_CKE[2]
A
S
A
_CK[3]
S
A
_CLK#[3]
S
_CKE[3]
A
S
_CS#[0]
A
S
_CS#[1]
A
S
_CS#[2]
A
S
A
_CS#[3]
S
_ODT[0]
A
S
_ODT[1]
A
S
A
_ODT[2]
S
_ODT[3]
A
S
A
_DQS#[0]
S
_DQS#[1]
A
S
_DQS#[2]
A
S
_DQS#[3]
A
S
A
_DQS#[4]
S
A
_DQS#[5]
S
_DQS#[6]
A
S
_DQS#[7]
A
S
_DQS[0]
A
S
_DQS[1]
A
S
_DQS[2]
A
S
A
_DQS[3]
S
A
_DQS[4]
S
_DQS[5]
A
S
A
_DQS[6]
S
A
_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
S
_MA[0]
A
S
_MA[1]
A
S
A
_MA[2]
S
A
_MA[3]
S
A
_MA[4]
S
_MA[5]
A
S
_MA[6]
A
S
A
_MA[7]
S
A
_MA[8]
S
A
_MA[9]
S
A
_MA[10]
S
_MA[11]
A
S
_MA[12]
A
S
_MA[13]
A
S
_MA[14]
A
S
_MA[15]
A
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
CLK_DDR#0
_
M
D
R_CKE0_DIMMA
D
_
CLK_DDR1
M
CLK_DDR#1
_
M
D
R_CKE1_DIMMA
D
R_CS0_DIMMA#
D
D
D
R_CS1_DIMMA#
D
ODT0
_
M
ODT1
_
M
D
R_A_DQS#0
D
D
R_A_DQS#1
D
R_A_DQS#2
D
D
R_A_DQS#3
D
D
R_A_DQS#4
D
D
R_A_DQS#5
D
D
R_A_DQS#6
D
D
R_A_DQS#7
D
D
R_A_DQS0
D
D
R_A_DQS1
D
D
R_A_DQS2
D
D
D
R_A_DQS3
D
R_A_DQS4
D
D
D
R_A_DQS5
D
R_A_DQS6
D
D
R_A_DQS7
D
D
D
R_A_MA0
D
D
R_A_MA1
D
R_A_MA2
D
D
D
R_A_MA3
D
D
R_A_MA4
D
R_A_MA5
D
D
D
R_A_MA6
D
D
R_A_MA7
D
R_A_MA8
D
D
D
R_A_MA9
D
R_A_MA10
D
D
R_A_MA11
D
D
D
R_A_MA12
D
R_A_MA13
D
D
D
R_A_MA14
D
D
R_A_MA15
D
CLK_DDR0 <12>
M_
CLK_DDR#0 <12>
M_
D
R_CKE0_DIMMA <12>
D
CLK_DDR1 <12>
_
M
_CLK_DDR#1 <12>
M
R_CKE1_DIMMA <12>
D
D
R_CS0_DIMMA# <12>
D
D
R_CS1_DIMMA# <12>
D
D
ODT0 <12>
_
M
ODT1 <12>
_
M
R_A_DQS#[0..7] <12>
D
D
R_A_DQS[0..7] <12>
D
D
R_A_MA[0..15] <12>
D
D
3
D
R_B_D[0..63]<13>
D
R_B_BS0<13>
D
D
DR_B_BS1<13>
D
R_B_BS2<13>
D
D
D
R_B_CAS#<13>
D
DR_B_RAS#<13>
D
R_B_WE#<13>
D
D
D
R_B_D0
D
D
R_B_D1
D
D
R_B_D2
D
D
R_B_D3
D
D
D
R_B_D4
D
R_B_D5
D
R_B_D6
D
D
D
D
R_B_D7
D
D
R_B_D8
D
D
R_B_D9
D
D
R_B_D10
D
D
R_B_D11
D
D
R_B_D12
D
R_B_D13
D
D
R_B_D14
D
D
R_B_D15
D
R_B_D16
D
D
D
R_B_D17
D
D
R_B_D18
D
D
R_B_D19
D
D
R_B_D20
D
D
R_B_D21
D
D
R_B_D22
D
R_B_D23
D
D
R_B_D24
D
D
D
R_B_D25
D
D
R_B_D26
D
D
R_B_D27
D
R_B_D28
D
D
D
R_B_D29
D
D
R_B_D30
D
D
R_B_D31
D
D
D
R_B_D32
D
R_B_D33
D
D
R_B_D34
D
D
D
R_B_D35
D
D
R_B_D36
D
R_B_D37
D
D
R_B_D38
D
D
R_B_D39
D
D
D
R_B_D40
D
R_B_D41
D
D
D
R_B_D42
D
R_B_D43
D
D
DR_B_D44
D
R_B_D45
D
D
R_B_D46
D
D
D
R_B_D47
D
D
R_B_D48
D
R_B_D49
D
D
R_B_D50
D
D
DR_B_D51
D
D
R_B_D52
D
R_B_D53
D
D
R_B_D54
D
D
D
R_B_D55
D
R_B_D56
D
D
D
R_B_D57
D
D
R_B_D58
D
R_B_D59
D
D
R_B_D60
D
D
R_B_D61
D
D
D
R_B_D62
D
R_B_D63
D
R_B_BS0
D
D
D
D
R_B_BS1
D
D
R_B_BS2
D
R_B_CAS#
D
D
D
R_B_RAS#
D
R_B_WE#
D
AM5
AM6
AJ11
AH11
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AT8
AT9
AR8
AA9
AA7
AB8
AB9
2
J
J
PU1D
PU1D
C
C
CLK_DDR2
_
M
AE2
S
_CK[0]
B
S
B
C9
_DQ[0]
B
S
A7
B
_DQ[1]
S
B
_DQ[2]
S
C8
_DQ[3]
B
S
A9
_DQ[4]
B
S
A8
B
_DQ[5]
S
D9
B
_DQ[6]
S
D8
B
_DQ[7]
S
G4
B
_DQ[8]
S
F4
_DQ[9]
B
S
F1
_DQ[10]
B
S
G1
_DQ[11]
B
S
G5
B
_DQ[12]
S
F5
B
_DQ[13]
S
F2
B
_DQ[14]
S
G2
B
_DQ[15]
S
J7
_DQ[16]
B
S
J8
_DQ[17]
B
S
_DQ[18]
B
S
K9
_DQ[19]
B
S
J9
_DQ[20]
B
S
J10
B
_DQ[21]
S
K8
B
_DQ[22]
S
K7
B
_DQ[23]
S
M5
B
_DQ[24]
S
N4
_DQ[25]
B
S
N2
B_DQ[26]
S
N1
_DQ[27]
B
S
M4
_DQ[28]
B
S
N5
_DQ[29]
B
S
M2
_DQ[30]
B
S
M1
B
_DQ[31]
S
_DQ[32]
B
S
B
_DQ[33]
S
B
_DQ[34]
S
B
_DQ[35]
S
B
_DQ[36]
S
B
_DQ[37]
S
B
_DQ[38]
S
B
_DQ[39]
S
_DQ[40]
B
S
B
_DQ[41]
S
_DQ[42]
B
S
_DQ[43]
B
S
_DQ[44]
B
S
_DQ[45]
B
S
_DQ[46]
B
S
_DQ[47]
B
S
_DQ[48]
B
S
_DQ[49]
B
S
_DQ[50]
B
S
_DQ[51]
B
S
_DQ[52]
B
S
_DQ[53]
B
S
_DQ[54]
B
S
_DQ[55]
B
S
_DQ[56]
B
S
_DQ[57]
B
S
_DQ[58]
B
S
_DQ[59]
B
S
_DQ[60]
B
S
_DQ[61]
B
S
_DQ[62]
B
S
_DQ[63]
B
S
S
B
_BS[0]
S
_BS[1]
B
R6
S
B
_BS[2]
S
_CAS#
B
S
B
_RAS#
S
_WE#
B
_CLK#[0]
S
B
_CKE[0]
S
_CK[1]
B
S
_CLK#[1]
B
S
B
_CKE[1]
B
_CK[2]
S
B
_CLK#[2]
S
B_CKE[2]
S
_CK[3]
B
S
_CLK#[3]
B
S
_CKE[3]
B
S
B
_CS#[0]
S
B
_CS#[1]
S
B
_CS#[2]
S
B
_CS#[3]
S
S
_ODT[0]
B
S
B
_ODT[1]
_ODT[2]
B
S
_ODT[3]
B
S
S
_DQS#[0]
B
S
B
_DQS#[1]
S
B
_DQS#[2]
_DQS#[3]
B
S
S
_DQS#[4]
B
S
B
_DQS#[5]
S
_DQS#[6]
B
S
_DQS#[7]
B
S
B
_DQS[0]
S
B
_DQS[1]
S
_DQS[2]
B
B
_DQS[3]
S
S
B
_DQS[4]
S
_DQS[5]
B
S
_DQS[6]
B
DR SYSTEM MEMORY B
DR SYSTEM MEMORY B
S
B
_DQS[7]
D
D
B
_MA[0]
S
B
_MA[1]
S
B
_MA[2]
S
_MA[3]
B
S
B
_MA[4]
S
_MA[5]
B
S
_MA[6]
B
S
_MA[7]
B
S
_MA[8]
B
S
B
_MA[9]
S
_MA[10]
B
S
B
_MA[11]
S
B
_MA[12]
S
B
_MA[13]
S
B
_MA[14]
S
_MA[15]
B
S
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
CLK_DDR#2
_
M
R_CKE2_DIMMB
D
D
CLK_DDR3
_
M
CLK_DDR#3
_
M
R_CKE3_DIMMB
D
D
R_CS2_DIMMB#
D
D
R_CS3_DIMMB#
D
D
ODT2
_
M
ODT3
_
M
R_B_DQS#0
D
D
D
R_B_DQS#1
D
D
R_B_DQS#2
D
R_B_DQS#3
D
D
R_B_DQS#4
D
D
D
R_B_DQS#5
D
R_B_DQS#6
D
D
DR_B_DQS#7
D
R_B_DQS0
D
D
D
R_B_DQS1
D
D
R_B_DQS2
D
R_B_DQS3
D
D
R_B_DQS4
D
D
D
R_B_DQS5
D
R_B_DQS6
D
D
D
R_B_DQS7
D
R_B_MA0
D
D
D
R_B_MA1
D
D
R_B_MA2
D
D
R_B_MA3
D
R_B_MA4
D
D
D
R_B_MA5
D
D
R_B_MA6
D
R_B_MA7
D
D
R_B_MA8
D
D
R_B_MA9
D
D
D
R_B_MA10
D
DR_B_MA11
D
R_B_MA12
D
D
D
R_B_MA13
D
D
R_B_MA14
D
R_B_MA15
D
D
1
_
CLK_DDR2 <13>
M
M_
CLK_DDR#2 <13>
DD
R_CKE2_DIMMB <13>
CLK_DDR3 <13>
M_
_
CLK_DDR#3 <13>
M
D
R_CKE3_DIMMB <13>
D
R_CS2_DIMMB# <13>
D
D
D
R_CS3_DIMMB# <13>
D
ODT2 <13>
_
M
_
ODT3 <13>
M
R_B_DQS#[0..7] <13>
D
D
R_B_DQS[0..7] <13>
D
D
R_B_MA[0..15] <13>
D
D
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
A A
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
TYCO_2013620-3_IVYBRIDGE
2
LL CONFIDENTIAL/PROPRIETARY
E
D
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
tle
i
i
i
tle
tle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
y Bridge (1/6)
v
v
v
y Bridge (1/6)
y Bridge (1/6)
I
I
I
-7781
A
A
A
-7781
-7781
L
L
L
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
8
8
8
1
1Friday, February 24, 2012
f
f
f
o
o
o
0
.
.
.
0
0
1
1
1
5
D D
C
F
G0_R<7>
C
F
G1_R<7>
C
G5_R<7>
F
+
CC_GFXCORE
V
V
XG_VAL_SENSE
1 2
R
R
C
C
122 49.9_0402_ 1%~D@
122 49.9_0402_ 1%~D@
CC_CORE
V
C
C
R
R
R
R
C
C
R
R
C
C
1 2
123 49.9_0402_ 1%~D@
123 49.9_0402_ 1%~D@
1 2
120 49.9_0402_ 1%~D@
120 49.9_0402_ 1%~D@
1 2
121 49.9_0402_ 1%~D@
121 49.9_0402_ 1%~D@
C C
+
B B
A
12
@
@
C
C
R
R
100_0402_1%~D
100_0402_1%~D
V
S
SAXG_VAL_SENSE
V
C_VAL_SNESE
C
12
C
C
@
@
R
R
100_0402_1%~D
100_0402_1%~D
V
S_VAL_SNESE
S
69
69
71
71
1 2
36 0_0402_5%~D@
36 0_0402_5%~D@
E
E
R
R
1 2
34 0_0402_5%~D@
34 0_0402_5%~D@
E
E
R
R
1 2
35 0_0402_5%~D@
35 0_0402_5%~D@
E
E
R
R
C
F
G2<7>
C
F
G3<7>
C
F
G4<7>
C
G6<7>
F
C
G7<7>
F
C
G8<7>
F
C
G9<7>
F
C
FG10<7>
C
F
G11<7>
9
9
PAD~D@
PAD~D@
T
T
0 PAD~D@
0 PAD~D@
1
1
T
T
T
T
1
1
2 PAD~D@
2 PAD~D@
4 PAD~D@
4 PAD~D@
1
1
T
T
C
G16<7>
F
C
G17<7>
F
2PAD~D @
2PAD~D @
2
2
T
T
2
2
8PAD~D @
8PAD~D @
T
T
T
T
2
2
9PAD~D @
9PAD~D @
0PAD~D @
0PAD~D @
3
3
T
T
3
3
1PAD~D @
1PAD~D @
T
T
T
T
3PAD~D @
3
3
3PAD~D @
T
T
5PAD~D @
3
35PAD~D @
T
T
3
3
6PAD~D @
6PAD~D @
T
T
3
7PAD~D @
7PAD~D @
3
T
T
8PAD~D @
3
3
8PAD~D @
T
T
4
4
0PAD~D @
0PAD~D @
4
4
1PAD~D @
1PAD~D @
T
T
T
T
2PAD~D @
2PAD~D @
4
4
T
T
4
4
3PAD~D @
3PAD~D @
T
T
4PAD~D @
4PAD~D @
4
4
5PAD~D @
4
4
5PAD~D @
T
T
T
T
6PAD~D @
4
4
6PAD~D @
7PAD~D @
7PAD~D @
4
4
T
T
8PAD~D @
4
4
8PAD~D @
T
T
T
T
2PAD~D @
2PAD~D @
5
5
4
C
FG0
C
G1
F
C
FG2
C
F
G3
C
F
G4
C
F
G5
C
F
G6
C
G7
F
C
G8
F
C
G9
F
C
G10
F
C
F
G11
C
F
G12
C
F
G13
C
F
G14
C
F
G15
C
F
G16
C
F
G17
V
XG_VAL_SENSE
A
V
SAXG_VAL_SENSE
S
V
C_VAL_SNESE
C
V
S_VAL_SNESE
S
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
AJ31
AH31
AJ33
AH33
AJ26
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
J15
CPU1E
CPU1E
J
J
F
G[0]
C
F
G[1]
C
F
G[2]
C
FG[3]
C
G[4]
F
C
G[5]
F
C
G[6]
F
C
G[7]
F
C
G[8]
F
C
G[9]
F
C
G[10]
F
C
G[11]
F
C
G[12]
F
C
G[13]
F
C
G[14]
F
C
G[15]
F
C
G[16]
F
C
G[17]
F
C
VA
XG_VAL_SENSE
VS
SAXG_VAL_SENSE
V
C_VAL_SENSE
C
V
S_VAL_SENSE
S
RS
VD5
S
VD8
R
VD9
RS
RS
VD10
VD11
RS
VD12
RS
RS
VD13
VD14
RS
VD15
S
R
S
VD16
R
VD17
S
R
VD18
S
R
S
VD19
R
VD20
S
R
SVD21
R
S
VD22
R
S
VD23
R
R
SVD24
R
S
VD25
S
VD27
R
FG
FG
C
C
ESERVED
ESERVED
R
R
VC
C_DIE_SENSE
V
S_DIE_SENSE
S
VD_NCTF1
S
R
S
VD_NCTF2
R
VD_NCTF3
S
R
RS
VD_NCTF4
VD_NCTF5
S
R
VD_NCTF6
S
R
VD_NCTF7
S
R
S
VD_NCTF8
R
SVD_NCTF9
R
VD_NCTF10
S
R
B
B
C
VD_NCTF11
S
R
VD_NCTF12
S
R
VD_NCTF13
S
R
R
VD28
S
R
VD29
S
R
VD30
S
R
VD31
S
VD32
RS
RS
VD33
VD34
S
R
VD35
S
R
VD37
RS
VD38
S
R
VD39
S
R
VD40
S
R
S
VD51
R
S
VD52
R
C
LK_ITP
LK_ITP#
3
T
T
9 PAD~D@
9 PAD~D@
3
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
K
E
Y
3
T
T
PAD~D@
PAD~D@
1
1
2
2
PAD~D@
PAD~D@
T
T
PAD~D@
PAD~D@
3
3
T
T
4
4
PAD~D@
PAD~D@
T
T
T
T
PAD~D@
PAD~D@
5
5
T
T
PAD~D@
PAD~D@
6
6
T
T
PAD~D@
PAD~D@
7
7
8
8
PAD~D@
PAD~D@
T
T
1 PAD~D@
1 PAD~D@
1
1
T
T
13 PAD~D@T1
3 PAD~D@
T
T
T
5 PAD~D@
5 PAD~D@
1
1
T
T
6 PAD~D@
6 PAD~D@
1
1
T
T
7 PAD~D@
7 PAD~D@
1
1
8 PAD~D@
8 PAD~D@
1
1
T
T
9 PAD~D@
1
1
9 PAD~D@
T
T
T
T
0 PAD~D@
0 PAD~D@
2
2
T
T
1 PAD~D@
1 PAD~D@
2
2
2
2
3 PAD~D@
3 PAD~D@
T
T
2
2
4 PAD~D@
4 PAD~D@
T
T
25 PAD~D@T2
5 PAD~D@
T
T
26 PAD~D@T26 PAD~D@
2
2
7 PAD~D@
7 PAD~D@
T
T
T
T
3
3
2 PAD~D@
2 PAD~D@
4 PAD~D@
4 PAD~D@
3
3
T
T
C
L
K_XDP_ITP <7>
C
K_XDP_ITP# <7>
L
T
T
9 PAD~D@
9 PAD~D@
4
4
5
5
0 PAD~D@
0 PAD~D@
T
T
1 PAD~D@
1 PAD~D@
5
5
T
T
T
T
3 PAD~D@
5
3 PAD~D@
5
2
CF
G Straps for Processor
C
F
G2
12
C
C
51
@
51
@
R
R
1K_0402_5%~D
1K_0402_5%~D
P
EG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
C
G2
F
definition matches socket pin map definition
0:Lane Reversed
C
FG4
12
R
R
C
C
52
@
52
@
1K_0402_5%~D
1K_0402_5%~D
D
isplay Port Presence Strap
1 : Disabled; No Physical Display Port
C
F
G4
attached to Embedded Display Port
0
: Enabled; An external Display Port device is
connected to the Embedded Display Port
C
G6
F
C
G5
F
1
12
54
@
54
@
C
C
R
R
1K_0402_5%~D
1K_0402_5%~D
P
CIE Port Bifurcation Straps
1
1
C
F
G[6:5]
: (Default) x16 - Device 1 functions 1 and 2 disabled
1
0: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
0
1: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2
R
R
C
C
53
@
53
@
1K_0402_5%~D
1K_0402_5%~D
1
C
F
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
P
EG DEFER TRAINING
C
FG7
A A
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
G7
12
C
C
56
@
56
@
R
R
1K_0402_5%~D
1K_0402_5%~D
1: (Default) PEG Train immediately
following xxRESETB de assertion
0
:
PEG Wait for BIOS for training
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
i
i
Title
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
I
I
I
y Bridge (1/6)
v
v
vy Bridge (1/6)
y Bridge (1/6)
L
L
L
-7781
A
A
-7781
-7781
A
1
1
1
1
0
.
.
.
0
9
9
9
0
1Friday, February 24, 2012
61Friday, February 24, 2012
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
+
CC_CORE
V
53A
D D
C C
B B
A A
5
4
JC
JC
PU1F
PU1F
AG35
V
C
C1
AG34
V
C
C2
AG33
V
C3
C
AG32
V
C4
C
AG31
V
C5
C
AG30
V
CC6
AG29
V
C
C7
AG28
V
C
C8
AG27
V
CC9
AG26
V
C
C10
AF35
V
C
C11
AF34
V
C12
C
AF33
V
C13
C
AF32
V
C14
C
AF31
V
CC15
AF30
V
C
C16
AF29
V
C
C17
AF28
V
C18
C
AF27
V
C19
C
AF26
V
C20
C
AD35
V
C
C21
AD34
V
C22
C
AD33
V
C23
C
AD32
V
C24
C
AD31
V
C
C25
AD30
V
C
C26
AD29
V
C27
C
AD28
V
C28
C
AD27
V
C29
C
AD26
V
C
C30
AC35
V
C31
C
AC34
V
C32
C
AC33
V
C
C33
AC32
V
C
C34
AC31
V
C
C35
AC30
V
C36
C
AC29
V
C37
C
AC28
V
C
C38
AC27
V
C39
C
AC26
V
C40
C
AA35
V
C41
C
AA34
V
C
C42
AA33
V
C43
C
AA32
V
C44
C
AA31
V
C
C45
AA30
V
C
C46
AA29
V
C
C47
AA28
V
C
C48
AA27
V
C
C49
AA26
V
C
C50
Y35
V
C51
C
Y34
V
C
C52
Y33
V
C
C53
Y32
V
C54
C
Y31
V
CC55
Y30
V
C
C56
Y29
V
C57
C
Y28
V
C58
C
Y27
V
C
C59
Y26
V
C60
C
V35
V
C61
C
V34
V
C
C62
V33
V
C63
C
V32
V
C64
C
V31
V
C
C65
V30
V
C66
C
V29
V
C67
C
V28
V
C
C68
V27
V
C69
C
V26
V
C70
C
U35
V
C
C71
U34
C
C72
V
U33
C73
C
V
U32
C74
C
V
U31
C75
C
V
U30
C76
C
V
U29
C77
C
V
U28
C78
C
V
U27
C
C79
V
U26
C
C80
V
R35
C
C81
V
R34
C
C82
V
R33
C
C83
V
R32
C
C84
V
R31
C85
C
V
R30
C
C86
V
R29
C87
C
V
R28
C88
C
V
R27
C
C89
V
R26
C90
C
V
P35
C91
C
V
P34
C92
C
V
P33
C93
C
V
P32
C94
C
V
P31
C95
C
V
P30
C96
C
V
P29
C97
C
V
P28
C98
C
V
P27
C99
C
V
P26
C
C100
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
4
POWER
POWER
PEG AND DDR
PEG AND DDR
ORE SUPPLY
ORE SUPPLY
C
C
V
S
SENSE LINES SVID
SENSE LINES SVID
CIO1
C
V
CIO2
C
V
CIO3
C
V
CIO4
C
V
C
CIO5
V
C
CIO6
V
C
CIO7
V
CIO8
C
V
C
CIO9
V
C
CIO10
V
C
CIO11
V
C
CIO12
V
CIO13
C
V
CIO14
C
V
CIO15
C
V
CIO16
C
V
C
CIO17
V
C
CIO18
V
C
CIO19
V
C
CIO20
V
CIO21
C
V
CIO22
C
V
CIO23
C
V
CIO24
C
V
C
CIO25
V
CIO26
C
V
CIO27
C
V
CIO28
C
V
CIO29
C
V
C
CIO30
V
CIO31
C
V
C
CIO32
V
C
CIO33
V
C
CIO34
V
C
CIO35
V
CIO36
C
V
C
CIO37
V
CIO38
C
V
CIO39
C
V
C
CIO40
V
V
DALERT#
I
V
IDSCLK
V
I
DSOUT
V
C_SENSE
C
V
S_SENSE
S
C
CIO_SENSE
V
S_SENSE_VCCIO
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
3
+
.05V_RUN_VTT
1
8
5A
.
Note: Place the PU resistors c lose to CPU
RC61 close to C PU 300 - 1500mi ls
H
_CPU_SVIDALRT#
H
CPU_SVIDALRT#
_
V
DSCLK
I
V
I
DSOUT
V
CSENSE_R
C
V
S
SSENSE_R
V
T
T_SENSE
V
SIO_SENSE_R
S
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
V
I
DSCLK <51>
P
lace RC66, RC70, RC75 near CPU
1 2
67 0_0402_5%~D@
67 0_0402_5%~D@
C
C
R
R
1 2
68 0_0402_5%~D@
68 0_0402_5%~D@
C
C
R
R
3
R
R
C98 10_0402_1%~D
C98 10_0402_1%~D
10_0402_1%~D
10_0402_1%~D
12
R
R
C
C
133
133
1 2
R
R
61 43_0402_5%~D
61 43_0402_5%~D
C
C
+
1
.05V_RUN_VTT
C
D Note: Place t he PU
12
63
C
C
63
R
R
130_0402_1%~D
130_0402_1%~D
H
CPU_SVIDALRT# must be routed between the
_
VIDSOUT and VIDSCLK lines to reduce cross
talk. 18 mils spacing to others.
12
A
resistors close to CPU
RC63 close to C PU 300 - 1500mi ls
V
DSOUT <51>
I
75
@
C
C75
@
R
R
100_0402_1%~D
100_0402_1%~D
1 2
+
1
.05V_RUN_VTT
V
T
T_SENSE <49>
V
S
SIO_SENSE_R <49>
2
+
1
.05V_RUN_VTT
12
+
V
CC_CORE
12
12
2
C
C
60
60
R
R
75_0402_1%~D
75_0402_1%~D
R
R
C
C
66
66
100_0402_1%~D
100_0402_1%~D
V
CSENSE <51>
C
V
S
SSENSE <5 1>
70
70
C
C
R
R
100_0402_1%~D
100_0402_1%~D
1
V
I
DALERT_N <51>
Iccmax current changed for PDD G Rev0.7
C
U Power Rail Table
P
V
ltage Rail
o
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+
1
.5V_MEM 1.5
D
escription
*
5
A
to Mem control ler(+1.5V_CPU_V DDQ)
5-6A to 2 DIMMs /channel
2-5A to +1.5V_R UN & +0.75V_DDR _VTT
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
L
L
L
A
A
A
Voltage
0
.
1.05
0
.
1.8
1
0.65-0.9
I
I
I
y Bridge (1/6)
v
y Bridge (1/6)
y Bridge (1/6)
v
v
-7781
-7781
-7781
1
65-1.3
0-1.1
.5
S
0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16
1
1
1
0 6
0 6
0 6
o
o
o
f
f
f
*
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+
1.5V_CPU_VDDQ Source
+
.3V_ALW2
3
12
C
C
74
74
R
R
100K_0402_5%~D
1
+
+
2
2
+
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
C
C
C
C
176
176
61
V
CC_GFXCORE
100K_0402_5%~D
R
N_ON_CPU1.5VS3#
U
C
C
4A
4A
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
A
3
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.5A
B6
A6
A2
D D
S
I
O_SLP_S3#<16,27,35,39,42,47>
C
P
U1.5V_S3_GATE<40>
C C
B B
1 2
R
R
96 1K_0402_5%~D@
96 1K_0402_5%~D@
C
C
1 2
C
97 1K_0402_5%~D@
97 1K_0402_5%~D@
C
R
R
A A
+
1
.8V_RUN
R
R
R
R
+
DIMM0_1_VREF_CPU
+
D
IMM0_1_CA_CPU
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
173
173
2
5
1 2
82 0_0402_5%~D@
82 0_0402_5%~D@
C
C
1 2
79 0_0402_5%~D@
79 0_0402_5%~D@
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
174
174
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
175
175
2
4
+
P
WR_SRC_S
12
3
5
4
R
U
N_ON_CPU1.5VS3# <7,42>
P
P
OWER
J
J
C
PU1G
PU1G
C
V
A
XG1
V
XG2
A
V
XG3
A
V
A
XG4
V
XG5
A
V
XG6
A
V
XG7
A
V
A
XG8
V
A
XG9
V
XG10
A
V
A
XG11
V
A
XG12
V
A
XG13
V
XG14
A
V
A
XG15
V
A
XG16
V
XG17
A
V
XG18
A
V
A
XG19
V
XG20
A
V
XG21
A
V
AXG22
V
XG23
A
V
XG24
A
V
XG25
A
V
XG26
A
V
XG27
A
V
XG28
A
V
A
XG29
V
XG30
A
V
XG31
A
V
A
XG32
V
XG33
A
V
XG34
A
V
A
XG35
V
XG36
A
V
XG37
A
V
XG38
A
V
XG39
A
V
XG40
A
V
XG41
A
V
XG42
A
V
AXG43
V
XG44
A
V
XG45
A
V
A
XG46
A
XG47
V
XG48
A
V
A
XG49
V
XG50
A
V
XG51
A
V
XG52
A
V
XG53
A
V
A
XG54
V
CPLL1
C
V
C
CPLL2
V
C
CPLL3
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
OWER
RAPHICS
RAPHICS
G
G
.8V RAIL
.8V RAIL
1
1
4
Q
+
.5V_MEM
1
R
R
72
72
C
C
330K_0402_5%~D
330K_0402_5%~D
R
U
N_ON_CPU1.5VS3
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
C
C
4B
4B
ENSE
ENSE
S
S
Q
3
3
C
C
AO4304L_SO8
AO4304L_SO8
8
7
6
5
4
1M_0402_5%~D
1M_0402_5%~D
12
R
R
C
C
143
143
V
LINES
LINES
_DIMM_VREFDQ
A
S
REFMISC
REFMISC
_DIMM_VREFDQ
B
S
V
V
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
A RAIL
A RAIL
S
S
V
A
XG_SENSE
SAXG_SENSE
S
S
M
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CSA_SENSE
C
V
C
CSA_VID[0]
V
CSA_VID[1]
C
V
C
CIO_SEL
V
_VREF
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
DQ10
D
DQ11
D
DQ12
D
DQ13
D
DQ14
D
DQ15
D
C
CSA1
CSA2
C
CSA3
C
C
CSA4
CSA5
C
CSA6
C
C
CSA7
CSA8
C
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
1
2
0.022U_0402_25V7K~D
0.022U_0402_25V7K~D
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
1
2
3
C
C
C
C
136
136
5A
6A
+
.5V_CPU_VDDQ
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
C
C
135
135
2
+
CC_GFXCORE
V
12
R
R
100_0402_1%~D
100_0402_1%~D
12
R
R
100_0402_1%~D
100_0402_1%~D
+
IMM0_1_VREF_CPU
D
+
D
IMM0_1_CA_CPU
1 2
140 0_0402_5%~D@
140 0_0402_5%~D@
C
C
R
R
20K_0402_5%~D
20K_0402_5%~D
12
@
@
R
R
C
C
73
73
99
C
C
99
100
C
C
100
+
_SM_VREF_CNT
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
3
+
1
.5V_MEM
1K_0402_1%~D
1K_0402_1%~D
12
@
@
R
R
C
C
80
80
1K_0402_1%~D
1K_0402_1%~D
12
@
@
R
R
C
C
81
81
76
@
76
@
C
C
R
R
100_0402_1%~D
100_0402_1%~D
1
+
V_SM_VREF should
have 10 mil trace width
+
IMM0_1_VREF_CPU
D
+
IMM0_1_CA_CPU
D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C
C
161
161
C
C
C
C
C
C
C162
C162
163
163
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
1
1
C
C
C
C
C
C
C
C
168
169
169
168
2
2
a
dded VCCSA_VID_0 to Power page
V
V
3
+
V
_DDR_SMREF
R
U
N_ON_CPU1.5VS3
2
V
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C164
C164
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C
C
170
170
2
2
CCSA_VID_0 <50>
CSA_VID_1 <50>
C
1
R
R
134 0_0402_5%~D@
134 0_0402_5%~D@
C
C
@
@
NTR4503NT1G_SOT23-3~D
NTR4503NT1G_SOT23-3~D
1
C_AXG_SENSE <51>
C
S_AXG_SENSE <51>
S
+
.5V_CPU_VDDQ
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
C
C
C
C
166
166
165
165
2
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
+
+
C
C
C
C
171
172
172
171
2
V
C
CP_PWRCTRL <49>
2
+
1
.5V_CPU_VDDQ
1K_0402_1%~D
2
5
5
C
C
Q
Q
3
2
C
C
C
C
C
C
C
C
C
C
C
C
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
C
C
C
1
2
C
C
C
+
+
C
C
167
167
1K_0402_1%~D
12
R
R
C
C
+
_SM_VREF_CNT
V
84
84
1K_0402_1%~D
1K_0402_1%~D
12
R
R
C
C
78
78
178 0.1U_04 02_10V7K~D
178 0.1U_04 02_10V7K~D
2
1
179 0.1U_04 02_10V7K~D
179 0.1U_04 02_10V7K~D
12
149 0.1U_04 02_10V7K~D
149 0.1U_04 02_10V7K~D
12
150 0.1U_04 02_10V7K~D
150 0.1U_04 02_10V7K~D
1
2
+
VCC_SA
V
C
CSA_SENSE <50>
2
6
A
+
.5V_MEM
1
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
C
PU1H
PU1H
J
J
AT35
S1
S
V
AT32
S2
S
V
AT29
S3
S
V
AT27
S4
S
V
AT25
S5
S
V
AT22
S6
S
V
AT19
S
S7
V
AT16
S8
S
V
AT13
S
S9
V
AT10
S10
S
V
AT7
S11
S
V
AT4
S12
S
V
AT3
S13
S
V
AR25
S14
S
V
AR22
S15
S
V
AR19
S16
S
V
AR16
S17
S
V
AR13
S18
S
V
AR10
S19
S
V
AR7
S20
S
V
AR4
S21
S
V
AR2
S22
S
V
AP34
S23
S
V
AP31
S24
S
V
AP28
S25
S
V
AP25
S26
S
V
AP22
S27
S
V
AP19
S28
S
V
AP16
S29
S
V
AP13
S30
S
V
AP10
S31
S
V
AP7
S32
S
V
AP4
S33
S
V
AP1
S34
S
V
AN30
S35
S
V
AN27
S36
S
V
AN25
S37
S
V
AN22
S38
S
V
AN19
SS39
V
AN16
S40
S
V
AN13
S41
S
V
AN10
S
S42
V
AN7
S
S43
V
AN4
S
S44
V
AM29
S
S45
V
AM25
S
S46
V
AM22
S47
S
V
AM19
S48
S
V
AM16
S49
S
V
AM13
S50
S
V
AM10
S51
S
V
AM7
S52
S
V
AM4
S
S53
V
AM3
S
S54
V
AM2
S
S55
V
AM1
S
S56
V
AL34
S
S57
V
AL31
S
S58
V
AL28
S59
VS
AL25
S60
VS
AL22
S61
VS
AL19
S62
VS
AL16
VSS63
AL13
S64
VS
AL10
VS
S65
AL7
VS
S66
AL4
VS
S67
AL2
V
S68
S
AK33
V
S69
S
AK30
V
S70
S
AK27
V
S
S71
AK25
V
S
S72
AK22
V
S
S73
AK19
V
S74
S
AK16
V
S75
S
AK13
V
S76
S
AK10
V
S
S77
AK7
V
S
S78
AK4
V
S
S79
AJ25
V
S80
S
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
tle
i
itle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
1
SS
SS
V
V
I
I
I
y Bridge (1/6)
y Bridge (1/6)
v
v
v
y Bridge (1/6)
L
L
L
A-7781
A-7781
A
-7781
1
S81
VS
S82
VS
V
S
S83
VS
S84
V
S
S85
V
S
S86
V
S87
S
V
S88
S
V
S
S89
V
S
S90
V
S
S91
V
S
S92
V
S
S93
V
S
S94
V
S95
S
V
S96
S
V
S98
S
V
S99
S
V
S100
S
V
S
S101
V
S
S102
V
S
S103
V
S
S104
V
S105
S
V
S106
S
V
S107
S
V
S108
S
V
S109
S
V
S
S110
V
S
S111
V
S
S112
V
S
S113
V
S114
S
V
S115
S
V
S
S116
V
S
S117
V
S
S118
V
S119
S
V
S120
S
V
S121
S
V
S
S122
V
S
S123
V
S
S124
V
S125
S
V
S126
S
V
S127
S
V
S
S128
V
S
S129
V
S
S130
V
S131
S
V
S132
S
V
S
S133
V
S
S134
V
S135
S
V
S136
S
V
S
S137
V
S
S138
V
S
S139
V
S140
S
V
S141
S
V
S
S142
V
S
S143
V
S144
S
V
S145
S
V
S
S146
V
S
S147
V
S148
S
V
S149
S
V
S
S150
V
S
S151
V
S152
S
V
S153
S
V
S
S154
V
S155
S
V
S156
S
V
S157
S
V
S
S158
V
S159
S
V
S160
S
1
1
1
1 6
1 6
1 6
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
o
o
o
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
5
_DDR_REFA_M3
+V
+
V
_DDR_REF
D D
o
pulate RD1, De-Populate RD7 for Intel DDR3
P
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
ll VREF traces should
A
have 10 mil trace width
D
R_A_DQS#[0..7]<8>
D
R_A_D[0..63]<8>
D
D
D
R_A_DQS[0..7]<8>
D
D
R_A_MA[0..15]<8>
D
C C
a
yout Note:
L
Place near JDIMM1
+
.5V_MEM
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
3
3
2
+
1
.5V_MEM
B B
A A
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
1
D
D
7
7
2
2
a
yout Note:
L
Place near JDIMM1.203,204
+
.75V_DDR_VTT
0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
17
17
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
4
4
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
C
C
1
D
D
9
9
8
8
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
18
18
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
5
C
C
C
C
D
D
D
D
6
5
6
5
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
D
D
10
10
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
19
19
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
C
C
1
1
D
D
11
51
51
11
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
D
D
20
20
330U_SX_2VY~D
330U_SX_2VY~D
@
@
1
C
C
C
C
1
+
+
D
D
D
D
14
13
13
14
2
2
2 10K_0402_5%~D
D
D
2 10K_0402_5%~D
R
R
1 2
1 2
D
D
3 10K_0402_5%~D
3 10K_0402_5%~D
R
R
1 2
D
D
R
R
1 2
RD
+
3
.3V_RUN
4
IMM1 H=5.2
+
IMM1_VREF_DQ
7 0_0402_5%~D@
7 0_0402_5%~D@
1 0_0402_5%~D@RD1 0_0402_5%~D@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
D
D
D
D
4
D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
D
R_A_D0
D
D
R_A_D1
D
C
C
C
C
1
D
D
D
D
2
2
1
1
R_CKE0_DIMMA<8>
D
R_A_BS2<8>
D
_
CLK_DDR0<8>
M
CLK_DDR#0<8>
_
M
R_A_BS0<8>
D
D
R_A_WE#<8>
D
D
D
R_A_CAS#<8>
D
R_CS1_DIMMA#<8>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
D
DR_A_D2
2
D
DR_A_D3
D
D
R_A_D8
D
R_A_D9
D
D
D
R_A_DQS#1
D
R_A_DQS1
D
D
D
R_A_D10
D
D
R_A_D11
D
R_A_D16
D
D
DR_A_D17
D
D
R_A_DQS#2
D
R_A_DQS2
D
D
R_A_D18
D
D
R_A_D19
D
D
R_A_D24
D
D
R_A_D25
D
D
D
R_A_D26
D
D
R_A_D27
D
D
R_CKE0_DIMMA
D
D
R_A_BS2
D
R_A_MA12
D
D
R_A_MA9
D
D
R_A_MA8
D
D
R_A_MA5
D
D
R_A_MA3
D
D
R_A_MA1
D
M
_
CLK_DDR0
M
_
CLK_DDR#0
D
R_A_MA10
D
D
D
R_A_BS0
D
R_A_WE#
D
D
R_A_CAS#
D
D
R_A_MA13
D
D
D
R_CS1_DIMMA#
D
D
R_A_D32
D
R_A_D33
D
D
R_A_DQS#4
D
D
R_A_DQS4
D
D
R_A_D34
D
D
R_A_D35
D
D
D
R_A_D40
D
R_A_D41
D
D
DR_A_D42
D
D
R_A_D43
D
D
R_A_D48
D
R_A_D49
D
D
D
R_A_DQS#6
D
D
R_A_DQS6
D
R_A_D50
D
D
R_A_D51
D
D
D
R_A_D56
D
R_A_D57
D
D
D
R_A_D58
D
D
R_A_D59
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
+
.75V_DDR_VTT
C
C
D
D
21
21
0
C
C
D
D
22
22
2
+
.5V_MEM
1
JD
J
J
IMM1
IMM1
D
D
1
EF_DQ
VR
3
V
S
S
5
D
0
Q
7
D
1
Q
9
V
S
S
11
D
0
M
13
V
SS
15
DQ
2
17
DQ
3
19
V
S
S
21
DQ
8
23
D
Q
9
25
V
S
S
27
D
S1#
Q
29
D
Q
S1
31
V
S
S
33
D
Q
10
35
D
Q
11
37
V
S
S
39
D
Q
16
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
18
Q
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
25
Q
61
V
S
S
63
D
3
M
65
V
SS
67
D
Q
26
69
D
Q
27
71
V
S
S
73
C
E0
K
75
V
D
D
7
7
N
C
79
B
A
2
81
V
D
D
83
A
2/BC#
1
5
8
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
7
9
A
1
99
V
D
D
101
C
K
0
103
C
K
0#
105
V
D
D
107
A
0/AP
1
109
B
0
A
111
V
D
D
113
W
E
#
115
C
A
S#
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
Q
S4
139
V
S
S
141
D
34
Q
143
D
35
Q
145
S
S
V
147
Q
40
D
149
Q
41
D
151
S
S
V
153
M
5
D
155
S
S
V
157
Q
42
D
159
43
Q
D
161
S
S
V
163
48
Q
D
165
49
Q
D
167
S
S
V
169
S6#
Q
D
171
S6
Q
D
173
S
S
V
175
50
Q
D
177
Q
51
D
179
S
S
V
181
56
Q
D
183
Q
57
D
185
S
S
V
187
7
M
D
189
S
S
V
191
58
Q
D
193
Q
59
D
195
S
S
V
197
0
A
S
199
D
DSPD
V
201
A
1
S
203
T
T
V
205
N
D1
G
TYCO_2-2013289-2~D
TYCO_2-2013289-2~D
CONN@
CONN@
3
-
3A to 1 DIMMs/channel
.5V_MEM
1
2
D
R_A_D4
D
D
R_A_D5
D
D
D
R_A_DQS#0
D
D
R_A_DQS0
D
D
R_A_D6
D
D
R_A_D7
D
DR_A_D12
D
D
R_A_D13
D
R3_DRAMRST#_R
D
D
R_A_D14
D
D
R_A_D15
D
D
R_A_D20
D
D
D
R_A_D21
D
D
R_A_D22
D
R_A_D23
D
D
R_A_D28
D
D
DR_A_D29
D
D
R_A_DQS#3
D
R_A_DQS3
D
D
R_A_D30
D
D
D
R_A_D31
D
D
R_CKE1_DIMMA
D
D
R_A_MA15
D
R_A_MA14
D
D
R_A_MA11
D
D
R_A_MA7
D
D
R_A_MA6
D
D
R_A_MA4
D
D
R_A_MA2
D
D
R_A_MA0
D
M
_
CLK_DDR1
M
CLK_DDR#1
_
D
DR_A_BS1
D
D
R_A_RAS#
D
DR_CS0_DIMMA#
M
_
ODT0
M
_
ODT1
D
R_A_D36
D
D
R_A_D37
D
D
R_A_D38
D
D
D
R_A_D39
D
R_A_D44
D
D
D
R_A_D45
D
R_A_DQS#5
D
D
R_A_DQS5
D
D
D
R_A_D46
D
R_A_D47
D
D
D
R_A_D52
D
R_A_D53
D
D
D
R_A_D54
D
D
R_A_D55
D
D
R_A_D60
D
D
R_A_D61
D
R_A_DQS#7
D
D
D
R_A_DQS7
D
R_A_D62
D
D
R_A_D63
D
+
.75V_DDR_VTT
0
D
R_CKE1_DIMMA <8>
D
CLK_DDR1 <8>
_
M
CLK_DDR#1 <8>
_
M
R_A_BS1 <8>
D
D
R_A_RAS# <8>
D
D
D
R_CS0_DIMMA# <8>
D
_
ODT0 <8>
M
ODT1 <8>
_
M
+
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
C
C
1
D
D
15
15
2
R_XDP_WAN_SM BDAT <7,13,14,15,27,34>
D
D
D
R_XDP_WAN_SM BCLK <7,13,14,15,27,34>
D
+
2
V
S
S
4
D
4
Q
6
D
Q
5
8
V
S
S
10
D
Q
S0#
12
D
S0
Q
14
V
S
S
16
D
6
Q
18
D
7
Q
20
V
S
S
22
D
Q
12
24
D
13
Q
26
V
S
S
28
D
M
1
30
R
SET#
E
32
V
S
S
34
D
Q
14
36
D
Q
15
38
V
S
S
40
D
20
Q
42
D
21
Q
44
V
S
S
46
D
M
2
48
V
S
S
50
D
22
Q
52
D
23
Q
54
V
S
S
56
D
Q
28
58
D
29
Q
60
V
S
S
62
D
Q
S3#
64
D
Q
S3
66
V
S
S
68
D
30
Q
70
D
Q
31
72
V
S
S
74
C
K
E1
76
V
D
D
78
A
1
5
80
A
4
1
82
V
D
D
84
A
1
1
6
8
A
7
88
V
D
D
9
0
A
6
2
9
A
4
94
V
D
D
6
9
A
2
9
8
A
0
100
V
D
D
102
C
1
K
104
C
K
1#
106
V
D
D
108
B
1
A
110
R
A
S#
112
V
D
D
114
S
#
0
116
O
D
T0
118
V
D
D
120
O
T1
D
1
22
N
C
124
V
D
D
126
V
EF_CA
R
128
S
S
V
130
Q
36
D
132
37
Q
D
134
S
S
V
136
4
M
D
138
S
S
V
140
38
Q
D
142
39
Q
D
144
S
S
V
146
Q
44
D
148
Q
45
D
150
S
S
V
152
S5#
Q
D
154
Q
S5
D
156
S
S
V
158
46
Q
D
160
Q
47
D
162
S
S
V
164
52
Q
D
166
Q
53
D
168
S
S
V
170
6
M
D
172
S
S
V
174
54
Q
D
176
55
Q
D
178
S
S
V
180
60
Q
D
182
61
Q
D
184
S
S
V
186
S7#
Q
D
188
S7
Q
D
190
S
S
V
192
Q
62
D
194
63
Q
D
196
S
S
V
198
V
ENT#
E
200
D
A
S
202
C
L
S
204
T
T
V
206
N
D2
G
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
P
3
D
IMM1_VREF_CA
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
2
R3_DRAMRST#_R<13>
D
D
+
D
IMM0_1_VREF_CPU
R_HVREF_RST<7>
D
D
+
D
IMM0_1_CA_CPU
3 Circuit (Processor Generated SO-DIMM VREF_DQ)
M
12
11 0_0402_5%~D@
D
D
11 0_0402_5%~D@
R
R
C
C
D
D
16
16
2
1
+
1
.5V_MEM
1
27
27
D
D
R
R
1K_0402_5%~D
1K_0402_5%~D
D
R3_DRAMRST#_R
D
D
D
R_HVREF_RST
D
D
R_HVREF_RST
1
D
D
28 1K_ 0402_5%~D
28 1K_ 0402_5%~D
R
R
29 0_0402_5%~D@
29 0_0402_5%~D@
D
D
R
R
D30 0_0402_5%~D@RD
30 0_0402_5%~D@
R
V
_DDR_REF
+
E
LL CONFIDENTIAL/PROPRIETARY
D
Title
i
i
tle
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
2
1 2
1
1
QD
QD
D
S
D
S
BSS138_G_SOT23-3
BSS138_G_SOT23-3
13
G
G
2
1 2
D
D
2
2
Q
Q
D
S
D
S
BSS138_G_SOT23-3
BSS138_G_SOT23-3
13
G
G
2
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
RIII-SODIMM SLOT1
RIII-SODIMM SLOT1
D
D
D
RIII-SODIMM SLOT1
D
D
D
A
A
A-7781
-7781
-7781
L
L
L
R3_DRAMRST# <7>
D
D
1
+
V
_DDR_REFA_M3
_DDR_REFB_M3
V
+
2 6
2 6
2 6
1
1
1
.
0
0
0
.
.
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
5
D D
o
pulate RD4, De-Populate RD8 for Intel DDR3
P
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
D
D
R_B_DQS#[0..7]<8>
D
R_B_D[0..63]<8>
D
D
D
R_B_DQS[0..7]<8>
D
R_B_MA[0..15]<8>
D
C C
+
1
.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
25
25
2
+
.5V_MEM
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
B B
A A
10U_0603_6.3V6M~D
C
C
C
C
1
1
D
D
D
D
29
29
30
30
2
2
yout Note:
a
L
Place near JDIMM2.203,204
+
.75V_DDR_VTT
0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
39
39
2
a
L
Place near JDIMM2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD
CD26
26
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
1
1
31
31
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C
C
D
D
40
40
2
2
5
yout Note:
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
D
D
D
D
27
27
28
28
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
C
C
1
1
D
D
D
D
33
33
32
32
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
D
D
D
D
42
41
41
42
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
D
D
34
34
ll VREF traces should
A
have 10 mil trace width
10U_0603_6.3V6M~D
330U_SX_2VY~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
@
1
C
C
C
C
1
+
+
D
D
D
D
35
36
35
36
2
2
+
V
_DDR_REFB_M3
+
_DDR_REF
V
4
+
IMM2_VREF_DQ
D
1 2
8 0_0402_5%~D@RD8 0_0402_5%~D@
RD
1 2
4 0_0402_5%~D@
4 0_0402_5%~D@
D
D
R
R
+
.3V_RUN
3
5 10K_0402_5%~D
D
D
5 10K_0402_5%~D
R
R
4
1
2
12
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
3
C
C
D
D
23
23
D
D
D
D
.3V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
R_CKE2_DIMMB<8>
R_B_BS2<8>
D
D
_
CLK_DDR2<8>
M
CLK_DDR#2<8>
_
M
D
R_B_BS0<8>
D
R_B_WE#<8>
D
D
D
R_B_CAS#<8>
D
R_CS3_DIMMB#<8>
12
3
+
.5V_MEM
1
D
R_B_D0
D
D
R_B_D1
D
C
C
D
D
24
24
D
D
R_B_D2
D
D
R_B_D3
D
D
R_B_D8
D
DR_B_D9
D
R_B_DQS#1
D
D
D
R_B_DQS1
D
R_B_D10
D
D
D
R_B_D11
D
D
R_B_D16
D
D
R_B_D17
D
R_B_DQS#2
D
D
R_B_DQS2
D
D
R_B_D18
D
D
DR_B_D19
D
R_B_D24
D
D
DR_B_D25
D
D
R_B_D26
D
R_B_D27
D
D
R_CKE2_DIMMB
D
D
R_B_BS2
D
D
R_B_MA12
D
D
R_B_MA9
D
D
D
R_B_MA8
D
D
R_B_MA5
D
R_B_MA3
D
D
R_B_MA1
D
M
CLK_DDR2
_
M
CLK_DDR#2
_
D
D
R_B_MA10
D
R_B_BS0
D
D
R_B_WE#
D
D
DR_B_CAS#
D
D
R_B_MA13
D
R_CS3_DIMMB#
D
D
R_B_D32
D
D
DR_B_D33
D
D
R_B_DQS#4
D
D
R_B_DQS4
D
D
R_B_D34
D
DR_B_D35
D
D
R_B_D40
D
R_B_D41
D
D
R_B_D42
D
D
R_B_D43
D
D
D
R_B_D48
D
R_B_D49
D
D
DR_B_DQS#6
D
R_B_DQS6
D
D
R_B_D50
D
D
D
R_B_D51
D
R_B_D56
D
D
DR_B_D57
D
D
R_B_D58
D
R_B_D59
D
10K_0402_5%~D
10K_0402_5%~D
+
0.75V_DDR_VTT
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
R
R
D
D
6
6
C
C
C
1
2
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
P
C
1
D
D
D
D
44
44
43
43
2
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
D
D
IMM2
IMM2
J
J
1
R
EF_DQ
V
3
VS
S
5
0
DQ
7
DQ
1
9
V
S
S
11
D
0
M
13
V
S
S
15
D
2
Q
17
D
3
Q
19
S
VS
21
8
DQ
23
D
9
Q
25
S
VS
27
D
S1#
Q
29
D
S1
Q
31
VS
S
33
D
10
Q
35
D
11
Q
37
V
S
S
39
D
16
Q
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
Q
18
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
Q
25
61
V
S
S
63
D
3
M
65
V
S
S
67
D
26
Q
69
D
Q
27
71
V
S
S
73
C
K
E0
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
8
5
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
9
7
A
1
99
V
D
D
101
C
K
0
103
C
K
0#
105
V
D
D
107
A
0/AP
1
109
B
A
0
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
32
Q
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
S4
Q
139
V
S
S
141
D
Q
34
143
D
Q
35
145
V
S
S
147
D
40
Q
149
D
41
Q
151
V
S
S
153
D
5
M
155
V
S
S
157
D
42
Q
159
D
Q
43
161
S
S
V
163
48
Q
D
165
49
Q
D
167
S
S
V
169
S6#
Q
D
171
Q
S6
D
173
S
S
V
175
Q
50
D
177
Q
51
D
179
S
S
V
181
Q
56
D
183
Q
57
D
185
S
S
V
187
M
7
D
189
S
S
V
191
Q
58
D
193
59
Q
D
195
S
S
V
197
A
0
S
199
DSPD
D
V
201
1
A
S
203
T
T
V
205
N
D1
G
TYCO_2-2013310-2~D
TYCO_2-2013310-2~D
CONN@
CONN@
2
VS
S
4
D
Q
4
6
D
5
Q
8
V
S
S
10
D
S0#
Q
12
D
S0
Q
14
V
S
S
16
D
Q
6
18
D
Q
7
20
V
S
S
22
D
12
Q
24
D
13
Q
26
V
S
S
28
D
M
1
30
R
E
SET#
32
V
S
S
34
D
Q
14
36
D
Q
15
38
V
S
S
40
D
20
Q
42
D
21
Q
44
V
SS
46
D
M
2
48
V
S
S
50
D
22
Q
52
D
23
Q
54
V
S
S
56
D
Q
28
58
D
Q
29
60
V
S
S
62
D
S3#
Q
64
D
S3
Q
66
V
S
S
68
D
Q
30
70
D
31
Q
72
V
S
S
74
C
K
E1
76
V
D
D
78
A
15
80
A
1
4
82
V
D
D
84
A
1
1
8
A
7
88
V
DD
9
A
6
9
A
4
94
V
D
D
9
A
2
9
A
0
100
V
D
D
102
C
K
1
104
C
K
1#
106
V
D
D
108
B
1
A
110
R
A
S#
112
V
D
D
114
S
#
0
116
O
T0
D
118
V
D
D
120
O
T1
D
1
N
C
124
V
D
D
126
V
EF_CA
R
128
V
S
S
130
D
Q36
132
D
37
Q
134
V
S
S
136
D
4
M
138
V
S
S
140
D
38
Q
142
D
39
Q
144
V
S
S
146
44
Q
D
148
Q
45
D
150
S
S
V
152
Q
S5#
D
154
Q
S5
D
156
S
S
V
158
Q
46
D
160
47
Q
D
162
S
S
V
164
52
Q
D
166
53
Q
D
168
S
S
V
170
6
M
D
172
S
S
V
174
54
Q
D
176
55
Q
D
178
S
S
V
180
Q
60
D
182
61
Q
D
184
S
S
V
186
Q
S7#
D
188
S7
Q
D
190
S
S
V
192
Q
62
D
194
63
Q
D
196
S
S
V
198
V
ENT#
E
200
A
D
S
202
L
C
S
204
T
T
V
206
N
D2
G
2
3A to 1 DIMMs/channel
2-
+
.5V_MEM
1
D
R_B_D4
D
D
D
R_B_D5
D
D
R_B_DQS#0
D
R_B_DQS0
D
D
DR_B_D6
D
D
R_B_D7
D
D
R_B_D12
D
D
R_B_D13
D
R3_DRAMRST#_R
D
D
D
R_B_D14
D
R_B_D15
D
D
R_B_D20
D
D
R_B_D21
D
D
R_B_D22
D
D
DR_B_D23
D
D
R_B_D28
D
D
R_B_D29
D
R_B_DQS#3
D
D
R_B_DQS3
D
D
D
R_B_D30
D
R_B_D31
D
D
D
R_CKE3_DIMMB
D
D
R_B_MA15
D
D
R_B_MA14
D
R_B_MA11
D
D
D
R_B_MA7
6
D
D
R_B_MA6
0
D
D
R_B_MA4
2
D
D
R_B_MA2
6
D
DR_B_MA0
8
M
CLK_DDR3
_
M
CLK_DDR#3
_
D
D
R_B_BS1
D
D
R_B_RAS#
D
DR_CS2_DIMMB#
M
_ODT2
M
_ODT3
22
D
R_B_D36
D
D
D
R_B_D37
D
R_B_D38
D
D
R_B_D39
D
D
R_B_D44
D
D
D
R_B_D45
D
R_B_DQS#5
D
D
R_B_DQS5
D
D
R_B_D46
D
D
DR_B_D47
D
D
R_B_D52
D
R_B_D53
D
D
D
R_B_D54
D
R_B_D55
D
D
R_B_D60
D
D
D
R_B_D61
D
D
R_B_DQS#7
D
R_B_DQS7
D
D
R_B_D62
D
D
R_B_D63
D
+
0
.75V_DDR_VTT
2
D
J
D
R3_DRAMRST#_R <12>
D
R_CKE3_DIMMB <8>
D
D
CLK_DDR3 <8>
_
M
CLK_DDR#3 <8>
_
M
R_B_BS1 <8>
D
D
R_B_RAS# <8>
D
D
D
R_CS2_DIMMB# <8>
D
ODT2 <8>
_
M
_
ODT3 <8>
M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
D
D
D
D
1
IMMB H=9.2
+
D
IMM2_VREF_CA
12
15 0_0402_5%~D@
D
D
15 0_0402_5%~D@
R
R
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
C
D
D
37
37
R_XDP_WAN_SM BDAT <7,12,14,15,27,34>
R_XDP_WAN_SM BCLK <7,12,14,15,27,34>
C
1
D
D
38
38
2
LL CONFIDENTIAL/PROPRIETARY
E
D
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
tle
tle
Title
i
i
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
RIII-SODIMM SLOT2
D
D
D
RIII-SODIMM SLOT2
RIII-SODIMM SLOT2
D
D
D
-7781
-7781
A
A
A
-7781
L
L
L
+
_DDR_REF
V
3 6
3 6
3 6
1
1
1
f
f
f
o
o
1
o
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
2
2
1
101
H
H
101
2
R
R
R
R
R
R
R
TC_CELL
+
1 2
H
H
29 33_0402_5%~D
29 33_0402_5%~D
R
R
1
R
R
H
H
26 33_0402_5%~D
26 33_0402_5%~D
1 2
27 33_0402_5%~D
27 33_0402_5%~D
H
H
R
R
1 2
H
H
25 33_0402_5%~D
25 33_0402_5%~D
R
R
R
R
H
H
1
35 47_0402_5%~D
35 47_0402_5%~D
9
9
1 2
94 33_0402_5%~D
8
8
94 33_0402_5%~D
1 2
98 0_0402_5%~D@
8
8
98 0_0402_5%~D@
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
o signal should be PU to the ALWAYS rail.
S
3
.3V_ALW_PCH
+
12
R
R
66
66
H
H
1K_0402_5%~D
1K_0402_5%~D
P
H_AZ_SYNC
C
12
282
@
282
@
H
H
R
R
100K_0402_5%~D
100K_0402_5%~D
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
1 2
H
H
22 20K_0402_5%~D
22 20K_0402_5%~D
R
R
1 2
R
R
23 20K_0402_5%~D
23 20K_0402_5%~D
H
H
1 2
R
R
11 1M_0402_5%~D
11 1M_0402_5%~D
H
H
1
1
@
@
C
C
C
C
OS place near DIMM
M
C
P
C
H_AZ_SDOUT
P
H_AZ_SYNC_Q
C
2
P
H_AZ_RST#
C
P
C
H_AZ_BITCLK
3
.3V_ALW_PCH
+
12
288
@
288
@
H
H
R
R
0_0603_5%~D
0_0603_5%~D
+
3
.3V_ALW_PCH_JTAG
C
H_AZ_SYNC_Q
P
1 2
31 1M_0402_5%~D
31 1M_0402_5%~D
TEL HDA_SYNC
N
I
isolation circuit
8
8
90
90
R
R
3.3K_0402_5%~D
3.3K_0402_5%~D
P
I_PCH_CS0#_R
S
2
S
PI_DIN64
S
I_WP#_SEL_R
P
2
M
M
OS1 SHORT PADS~D
OS1 SHORT PADS~D
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4
4
H
H
R
R
RH
RH
llow INTEL CRB 0.7
o
F
V_RUN
5
+
1
0 MIL SO8
0
2
4Mb Flash ROM
6
X76@
X76@
2
1
/
C
S
2
D
O
3
/
W
P
4
G
D
N
W25Q64CVSSIG_SO8~D
W25Q64CVSSIG_SO8~D
2
R
R
59 51_0402_1%~D
59 51_0402_1%~D
H
H
44 200_0402_1%~D
H
H
44 200_0402_1%~D
45 200_0402_1%~D
45 200_0402_1%~D
43 200_0402_1%~D
43 200_0402_1%~D
H
H
R
R
U
U
5
5
e
V
WINBOND
2
2
ndor
C
H_AZ_MDC_SDOUT<30>
P
S
S
G
G
2
V
/
H
OLD
C
D
M
OS_CLR1
C
h
S
p
O
ME_CLR1
Sh
Open
TC_CELL
R
+
D D
INTVRMEN- Integrated SUS
1.1V VRM Enable
i
gh - Enable Internal VRs
*
H
Low - Enable External VRs
C C
P
P
B B
P
S
A A
C
Clear CMOS
unt
en
K
TPM setting
Cl
unt
ear ME RTC Registers
Keep ME RTC Registers
12
38
38
RH
RH
330K_0402_1%~D
330K_0402_1%~D
P
H_INTVRMEN
C
1
R
R
H
H
39
@
39
@
330K_0402_1%~D
330K_0402_1%~D
2
1
1
@
@
M
M
E
E
1 SHORT PADS~D
1 SHORT PADS~D
1 2
5 1U_0402_6.3V6K~D
5 1U_0402_6.3V6K~D
H
H
C
C
C
H_AZ_CODEC_SDOUT<29>
C
H_AZ_CODEC_SYNC<29>
P
C
H_AZ_CODEC_RST#<29>
P
C
H_AZ_CODEC_BITCLK<29>
27P_0402_50V8J~D
27P_0402_50V8J~D
S
P
I_PCH_CS0#
S
I_PCH_DIN
P
S
I_WP#_SEL
P
I_WP#_SEL<39>
M
OS setting
e
ep CMOS
C
C
@
@
WINBOND
EON
MXIC
5
4
U
B_OC2#<17>
B_OC3#<17>
B_OC5#<17>
B_OC6#<17>
2
2
H
H
C
C
15P_0402_50V8J~D
15P_0402_50V8J~D
12
C
C
H
H
3
3
15P_0402_50V8J~D
15P_0402_50V8J~D
12
@
@
H_AZ_MDC_BITCLK<30>
C
P
C
H_AZ_MDC_SYNC<30>
P
H_AZ_MDC_RST#<30>
C
P
H_AZ_CODEC_SDIN0< 29>
C
H_AZ_MDC_SDIN1<30>
P
_FWP<39>
P
CH_AZ_SYNC
P
I_CLK64
1 2
99 33_0402_5%~D
99 33_0402_5%~D
8
8
R
R
I_DO64
P
1 2
01 33_0402_5%~D
9
9
01 33_0402_5%~D
R
R
o
.
N
SB_OC0#_R
US
B_OC1#_R
US
B_OC2#
US
B_OC3#
U
S
B_OC4#_R
U
B_OC5#
S
U
B_OC6#
S
S
O_EXT_SMI#
I
S
L
P_ME_CSW_DEV#
U
S
B_MCARD1_DET#
H_GPIO36
C
P
C
H_GPIO37
P
P
H_GPIO16
C
T
EMP_ALERT#
P
C
H_GPIO15
S
I
O_EXT_SCI#_R
12
P
2
C
C
H
H
100
100
27P_0402_50V8J~D
27P_0402_50V8J~D
KR<29>
P
S
3
.3V_ALW_PCH
+
12
48
48
H
H
R
R
@
@
1
91
91
8
8
R
R
3.3K_0402_5%~D
3.3K_0402_5%~D
2
A
000039A2L
S
B_OC0#_R<17>
S
U
B_OC1#_R<17>
S
U
S
U
S
U
B_OC4#_R<17>
US
S
U
S
U
I
O_EXT_SMI#<17,40>
S
P_ME_CSW_DEV#<18,39>
L
S
B_MCARD1_DET#<18,34>
S
U
C
H_GPIO36<18>
P
C
H_GPIO37<18>
P
C
H_GPIO16<18>
P
E
MP_ALERT#<18,39>
T
C
H_GPIO15<18>
P
I
O_EXT_SCI#_R<18>
S
H_RSMRST#_Q<16,41>
C
P
C
P
E
M
12
12
12
12
D
D
13
Q
7
QH
H
7
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
3
.3V_SPI
+
8
C
C
7
S
6
K
L
S
5
O
I
76@ configuration for ROM part
X
7
640631L01 SA000039A1L
X
X7640631L02
X7640631L03 SA000046400
X7640631L04 SA00004G600
4
RH
H
H
R
R
H
H
R
R
RH
RH
R
R
H
H
R
R
H
H
H
H
R
R
R
R
H
H
D
D_DET#_R
B
S_BIT0_R
B
Y
Y
H
H
1
1
32.768KHZ_12.5PF_Q13FC1350000~D
32.768KHZ_12.5PF_Q13FC1350000~D
H_RTCX2_R
C
1
12
49
49
H
H
R
R
@
@
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
46
46
7
7
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
P
I_HOLD#
S
S
P
I_PCH_CLK
S
I_PCH_DO
P
2
5
U
H
RH
RH
H
H
R
R
RH
R
R
H
H
H
H
R
R
R
R
H
H
R
R
H
H
R
R
H
H
R
R
H
H
H
H
R
R
1 2
R
R
H
H
286 0_0402_5%~D@
286 0_0402_5%~D@
1 2
R
R
32 33_0402_5%~D
32 33_0402_5%~D
H
H
1 2
33 33_0402_5%~D
33 33_0402_5%~D
H
H
R
R
1 2
R
R
34 33_0402_5%~D
34 33_0402_5%~D
H
H
1 2
R
R
H
H
287 1K_0402_5%~D@
287 1K_0402_5%~D@
1 2
H
H
36 33_0402_5%~D
36 33_0402_5%~D
R
R
1 2
H
H
50 1K_0402_5%~D
50 1K_0402_5%~D
R
R
S
B30_SMI#<28>
U
12
47
47
H
H
R
R
@
@
100_0402_1%~D
100_0402_1%~D
SA00003K80L
00003K80L
A
S
SA00004LI00
SA000041P00
1 33_0402_5%~DPXDP@RH1 33_0402_5%~DPXDP@
3 33_0402_5%~DPXDP@
3 33_0402_5%~DPXDP@
4 33_0402_5%~DPXDP@
4 33_0402_5%~DPXDP@
5 33_0402_5%~DPXDP@RH5 33_0402_5%~DPXDP@
6 33_0402_5%~DPXDP@RH6 33_0402_5%~DPXDP@
7 33_0402_5%~DPXDP@
7 33_0402_5%~DPXDP@
8 33_0402_5%~DPXDP@
8 33_0402_5%~DPXDP@
9 33_0402_5%~DPXDP@
9 33_0402_5%~DPXDP@
10 33_0402_5%~DPXDP@
10 33_0402_5%~DPXDP@
12 33_0402_5%~DPXDP@
12 33_0402_5%~DPXDP@
13 33_0402_5%~DPXDP@
13 33_0402_5%~DPXDP@
14 33_0402_5%~DPXDP@RH14 33_0402_5%~DPXDP@
15 33_0402_5%~DPXDP@
15 33_0402_5%~DPXDP@
16 33_0402_5%~DPXDP@
16 33_0402_5%~DPXDP@
17 33_0402_5%~DPXDP@
17 33_0402_5%~DPXDP@
18 33_0402_5%~DPXDP@
18 33_0402_5%~DPXDP@
19 33_0402_5%~DPXDP@
19 33_0402_5%~DPXDP@
20 33_0402_5%~DPXDP@
20 33_0402_5%~DPXDP@
24 1K_0402_5%~DPXDP@
24 1K_0402_5%~DPXDP@
P
C
5
U
H_RTCX1
P
3
1 2
1 2
1 2
1 2
1
1 2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
1 2
1
1 2
1 2
C
12
H_AZ_SYNC_Q
PI_PCH_CS1#
S
P
I_PCH_DIN
S
I_WP#_SEL_R
P
S
3
X
D
P_FN0
XD
P_FN1
XD
P_FN2
X
P_FN3
D
X
P_FN4
2
2
2
2
R
R
R
H
H
2
2
10M_0402_5%~D
10M_0402_5%~D
P
P
S
I
N
P
P
P
P
P
P
U
P
P
P
P
P
P
P
P
P
R
R
R
R
D
X
P_FN5
D
X
D
P_FN6
X
D
P_FN7
X
P_FN8
D
X
DP_FN9
X
D
P_FN10
X
D
P_FN11
X
D
P_FN12
X
P_FN13
D
X
P_FN14
D
X
P_FN15
D
X
D
P_FN16
X
D
P_FN17
MRST#_XDP
S
R_XDP_WAN_SMBDAT<7,12,13,15,27,34>
D
D
R_XDP_WAN_SMBCLK<7,12,13,15,27,34>
D
D
U
U
C
H_RTCX2
H_RTCRST#
C
R
TCRST#
TRUDER#
C
H_INTVRMEN
C
H_AZ_BITCLK
H_AZ_RST#
C
H_AZ_CODEC_SDIN0
C
H_AZ_MDC_SDIN1
C
C
H_AZ_SDOUT
P
C
H_GPIO33
B30_SMI#
S
C
H_JTAG_TCK
H_JTAG_TMS
C
C
H_JTAG_TDI
C
H_JTAG_TDO
H_SPI_CLK
C
H_SPI_CS0#
C
C
H_SPI_CS1#
H_SPI_DO
C
C
H_SPI_DIN
1 2
36 47_0402_5%~D
36 47_0402_5%~D
9
9
1 2
8
8
95 33_0402_5%~D
95 33_0402_5%~D
A20
C20
D20
G22
K22
C17
N34
P
H_AZ_SYNC
C
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
PI_PCH_CS1#_R
S
P
I_DIN32
S
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
P
3
.3V_ALW_PCH
3
+
1
PXDP@
PXDP@
CH
CH
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
R
R
283 1K_0402_5%~DPXDP@
283 1K_0402_5%~DPXDP@
H
H
05V_0.8V_PWROK<40,51>
.
1
I
O_PWRBTN#_R<7,16>
S
H
H
4A
4A
R
CX1
T
R
CX2
T
R
CRST#
T
S
R
TCRST#
I
TRUDER#
N
I
TVRMEN
N
H
D
A_BCLK
H
D
A_SYNC
S
KR
P
H
A_RST#
D
H
D
A_SDIN0
H
D
A_SDIN1
H
A_SDIN2
D
H
A_SDIN3
D
H
D
A_SDO
H
A_DOCK_E N# / GPIO33
D
H
A_DOCK_R ST# / GPIO13
D
J
AG_TCK
T
J
T
AG_TMS
J
AG_TDI
T
J
T
AG_TDO
S
I_CLK
P
S
I_CS0#
P
S
I_CS1#
P
S
P
I_MOSI
S
P
I_MISO
BS_BIT0 - BIOS BOOT STRAP BIT 0
B
00 MIL SO8
2
2Mb Flash ROM
3
X76@
X76@
1
2
3
4
W25Q32BVSSIG_SO8~D
W25Q32BVSSIG_SO8~D
1 2
1 2
21 0_0402_5%~DPXDP@
21 0_0402_5%~DPXDP@
H
H
R
R
H
H
284 0_0402_5%~DPXDP@
284 0_0402_5%~DPXDP@
R
R
1 2
1 2
H285 0_0402_5%~DPXDP@RH285 0_0402_5%~DPXDP@
R
C
C
T
T
R
R
DA
DA
H
H
I
I
TAG
TAG
J
J
PI
PI
S
S
S
S
U
3
U5
5
3
8
C
V
#
S
C
C
7
H
D
LD#
O
O
6
C
W
K
P
L
#
5
D
G
N
I
D
1
.
05V_0.8V_PWROK_R
P
C
D
D
R_XDP_WAN_SMBDAT_R2
D
D
R_XDP_WAN_SMBCLK_R2
F
W
H0 / LAD0
F
W
H1 / LAD1
F
W
H2 / LAD2
F
H3 / LAD3
W
PC
PC
L
L
F
H4 / LFRAM E#
W
L
D
RQ0#
L
D
RQ1# / GP IO23
S
E
RIRQ
S
A
TA0RXN
S
A
TA0RXP
S
TA0TXN
A
S
TA0TXP
A
S
A
TA1RXN
ATA 6G
ATA 6G
S
A
TA1RXP
S
S
S
TA1TXN
A
S
TA1TXP
A
S
A
TA2RXN
S
A
TA2RXP
S
TA2TXN
A
S
TA2TXP
A
S
A
TA3RXN
S
A
TA3RXP
S
TA3TXN
A
S
TA3TXP
A
S
A
TA4RXN
S
A
TA4RXP
S
TA4TXN
A
S
TA4TXP
A
SATA
SATA
S
A
TA5RXN
S
A
TA5RXP
S
TA5TXN
A
S
A
TA5TXP
S
TAICOMPO
A
S
TAICOMPI
A
S
TA3RCOMPO
A
S
A
TA3COMPI
S
TA3RBIAS
A
S
ATALED#
TA0GP / GP IO21
A
A
TA1GP / GP IO19
3.3V_SPI
+
P
I_CLK32
S
P
I_DO32
S
X
D
X
D
X
D
X
D
X
DP_FN4
X
D
X
D
X
D
H_PWRBTN#_XDP
P
H_JTAG_TCK
C
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
1 2
8
8
R
R
1 2
9
9
R
R
2
.3V_ALW_PCH
+3
P_FN0
P_FN1
P_FN2
P_FN3
P_FN5
P_FN6
P_FN7
L
P
C_LAD0
L
P
C_LAD1
L
P
C_LAD2
L
C_LAD3
P
L
P
C_LFRAME#
L
P
C_LDRQ1#
I
R
Q_SERIRQ
S
TA_COMP
A
S
TA3_COMP
A
R
B
IAS_SATA3
S
A
TA_ACT#
H
D
D_DET#_R
B
B
S_BIT0_R
H_PLTRST#<7,17>
C
P
45
7
7
45
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
I_HOLD#
P
S
P
I_PCH_CLK
S
97 33_0402_5%~D
97 33_0402_5%~D
I_PCH_DO
P
S
00 33_0402_5%~D
00 33_0402_5%~D
2
J
J
X
X
DP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
DP2
GN
D0
O
SFN_A0
B
O
SFN_A1
B
G
N
D2
O
B
SDATA_A0
O
B
SDATA_A1
G
D4
N
O
SDATA_A2
B
O
SDATA_A3
B
D6
N
G
SFN_B0
B
O
SFN_B1
B
O
N
D8
G
B
SDATA_B0
O
B
SDATA_B1
O
ND10
G
SDATA_B2
B
O
SDATA_B3
B
O
D12
N
G
W
RGOOD/HOO K0
P
O
OK1
H
C
C_OBS_A B
V
O
OK2
H
O
OK3
H
N
D14
G
D
A
S
L
C
S
K1
C
T
K0
C
T
D16
N
G
SAMTE_BSH-030-01-L-D-A C ONN@
SAMTE_BSH-030-01-L-D-A C ONN@
C_LAD0 <32,34,39,40>
P
L
C_LAD1 <32,34,39,40>
P
L
PC_LAD2 <32,34,39,40>
L
C_LAD3 <32,34,39,40>
P
L
C_LFRAME# <32,34,39,40>
P
L
C_LDRQ1# <39>
P
L
R
Q_SERIRQ <32,39,40>
I
ATA_PRX_DTX_N0_C <27>
S
P
ATA_PRX_DTX_P0_C <27>
S
P
ATA_PTX_DRX_N0_C <27>
S
P
ATA_PTX_DRX_P0_C <27>
S
P
A
TA_ODD_PRX_DTX_N1_C <28>
S
A
TA_ODD_PRX_DTX_P1_C <28>
S
TA_ODD_PTX_DRX_N1_C <28>
A
S
TA_ODD_PTX_DRX_P1_C <28>
A
S
ATA_PRX_DTX_N4_C <37>
S
E
ATA_PRX_DTX_P4_C <37>
S
E
S
ATA_PTX_DRX_N4_C <37>
E
S
ATA_PTX_DRX_P4_C <37>
E
TA_PRX_DKTX_N5_C <38>
A
S
TA_PRX_DKTX_P5_C <38>
A
S
TA_PTX_DKRX_N5_C <38>
A
S
TA_PTX_DKRX_P5_C <38>
A
S
1 2
R
R
40 37.4_0402_1%~D
H
H
40 37.4_0402_1%~D
1 2
R
R
H
H
42 49.9_0402_1%~D
42 49.9_0402_1%~D
1 2
R
R
46 750_0402_1%~D
46 750_0402_1%~D
H
H
TA_ACT# <43>
A
S
1 2
290 0_0402_5%~D@
290 0_0402_5%~D@
H
H
R
R
D
S
D
S
1 3
Q
Q
1 BSS138W-7-F_SOT323-3~D
H
H
1 BSS138W-7-F_SOT323-3~D
G
G
2
J
J
PI1
S
S
PI1
1
1
1
1
1
1
1
G
G
HRS_FH12-16S-0P5SH(55)~D
HRS_FH12-16S-0P5SH(55)~D
CONN@
CONN@
1
2
D1
N
G
SFN_C0
OB
B
SFN_C1
O
G
B
SDATA_C0
O
SDATA_C1
B
O
G
SDATA_C2
B
O
B
SDATA_C3
O
G
B
SFN_D0
O
B
SFN_D1
O
G
SDATA_D0
B
O
SDATA_D1
B
O
G
SDATA_D2
B
O
B
SDATA_D3
O
G
T
PCLK/HOO K4
I
T
PCLK#/HO OK5
I
C
C_OBS_CD
V
E
SET#/HOOK 6
R
B
R#/HOOK7
D
G
T
G
1
.05V_RUN
+
.05V_RUN
1
+
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0
1
0
1
1
1
1
2
2
3
1
3
4
1
4
1
5
5
1
6
6
7
1
1
1
8
2
LL CONFIDENTIAL/PROPRIETARY
E
D
tle
Title
i
itle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
XDP_FN16
4
XD
6
8
N
D3
X
10
X
12
14
D5
N
X
16
X
18
20
N
D7
22
24
26
N
D9
X
28
X
30
32
D11
N
X
34
X
36
38
N
D13
40
42
44
R
46
X
48
50
N
D15
P
52
D
0
T
54
R
ST#
P
56
D
I
T
P
58
S
M
T
60
D17
N
HDD
D
D/ E Module Bay
O
-
SATA
E
O
CK
D
.3V_RUN
3
+
H_SATA_MOD_EN# <40>
C
P
S
I_PCH_CS1#
P
P
C
H_SPI_CS1#
R
R
S
P
I_PCH_DO
P
H_SPI_DO
C
R
R
S
P
I_PCH_DIN
P
H_SPI_DIN
C
R
R
S
I_PCH_CLK
P
P
R
R
CH_SPI_CLK
S
P
I_PCH_CS0#
P
H_SPI_CS0#
C
R
R
R
R
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
C
L
L
L
P_FN17
D
P_FN8
D
P_FN9
P_FN10
D
P_FN11
D
D
P_FN12
D
P_FN13
P_FN14
D
P_FN15
D
.3V_ALW_PCH
3
+
MRST#_XDP
S
P_DBRESET#
D
C
H_JTAG_TDO
C
H_JTAG_TDI
C
H_JTAG_TMS
P
B
12
345 0_0402_5%~D
345 0_0402_5%~D
H
H
346 0_0402_5%~D
346 0_0402_5%~D
H
H
347 0_0402_5%~D
347 0_0402_5%~D
H
H
348 0_0402_5%~D
H
H
348 0_0402_5%~D
H
H
349 0_0402_5%~D
349 0_0402_5%~D
.3V_M
3
+
H
H
350 0_0402_5%~D
350 0_0402_5%~D
C
C
C
P
P
P
-7781
A
A
A
-7781
-7781
CH_GPIO33
H
H
R
R
I
Q_SERIRQ
R
R
R
H
H
S_BIT0_R
B
NTEL feedback 0302
I
S
P
KR
o
N
SPKR
H
H
30
30
R
R
10K_0402_5%~D
10K_0402_5%~D
1 2
1 2
1 2
1 2
1
1 2
H (1/8)
H (1/8)
H (1/8)
1
P_DBRESET# <7,16>
D
X
355 100K_0402_5%~D
355 100K_0402_5%~D
28 8.2K_0402_5%~D
28 8.2K_0402_5%~D
R
R
H
H
52 4.7K_0402_5%~D
52 4.7K_0402_5%~D
H
H
35 10K_0402_5%~D@
35 10K_0402_5%~D@
R
R
Reboot Strap
w = Default
o
L
High = No Reboot
D_DET# <27>
D
H
2
1
1
1
12
12
12
3
+
12
3
.3V_SPI
+
4 6
4 6
4 6
f
f
f
o
o
o
+
3
.3V_RUN
.3V_RUN
.
.
.
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
0
0
0
5
D D
P
C
IE_PRX_WANTX_N1<34>
P
IE_PRX_WANTX_P1<34>
P
P
P
P
P
P
P
P
P
P
IE_PRX_WLANTX_N2<34>
C
C
IE_PRX_WLANTX_P2<34>
C
IE_PTX_WLANRX_N2<34>
IE_PTX_WLANRX_P2<34>
C
P
P
P
P
P
P
P
P
IE_PRX_WPANTX_N5<34>
C
IE_PRX_WPANTX_P5<34>
C
C
IE_PTX_WPANRX_N5<34>
C
IE_PTX_WPANRX_P5<34>
P
P
P
P
P
P
P
P
C
C
IE_PTX_WANRX_N1<34>
IE_PTX_WANRX_P1<34>
C
C
IE_PRX_EXPTX_N3<35>
C
IE_PRX_EXPTX_P3<35>
C
IE_PTX_EXPRX_N3<35>
IE_PTX_EXPRX_P3<35>
C
IE_PRX_EMBTX_N4<28>
C
IE_PRX_EMBTX_P4<28>
C
IE_PTX_EMBRX_N4<28>
C
C
IE_PTX_EMBRX_P4<28>
C
IE_PRX_MMITX_N6<33>
C
IE_PRX_MMITX_P6<33>
IE_PTX_MMIRX_N6<33>
C
IE_PTX_MMIRX_P6<33>
C
C
IE_PRX_GLANTX_N7<31>
IE_PRX_GLANTX_P7<31>
C
IE_PTX_GLANRX_N7<31>
C
IE_PTX_GLANRX_P7<31>
C
C
C
+
C
+
C
+
K_PCIE_MINI1#<34 >
L
K_PCIE_MINI1<34>
L
3
.3V_ALW_PCH
I
NI1CLK_REQ#<34>
M
K_PCIE_LAN#<31>
L
C
K_PCIE_LAN<31>
L
C
A
NCLK_REQ#<31>
L
K_PCIE_MMI#<33>
L
C
K_PCIE_MMI<33>
L
C
+
3
.3V_RUN
ICLK_REQ#<33>
M
M
K_PCIE_MINI3#<34>
L
L
K_PCIE_MINI3<34>
C
+
3.3V_ALW_PCH
NI3CLK_REQ#<34>
I
M
L
K_PCIE_EXP#<35>
C
K_PCIE_EXP<35>
L
C
+
.3V_ALW_PCH
3
PCLK_REQ#<35>
X
E
L
K_PCIE_MINI2#<34 >
C
K_PCIE_MINI2<34>
L
C
3
.3V_ALW_PCH
NI2CLK_REQ#<34>
I
M
+
.3V_ALW_PCH
3
L
K_PCIE_EMB#<28>
K_PCIE_EMB<28>
L
C
.3V_ALW_PCH
3
BCLK_REQ#<28>
M
E
L
K_CPU_ITP#<7>
C
K_CPU_ITP<7>
L
C
H
H
307 0_0402_5%~D@
307 0_0402_5%~D@
R
R
308 0_0402_5%~D@
H
H
308 0_0402_5%~D@
R
R
81 10K_0402_5%~D
H
H
81 10K_0402_5%~D
R
R
R
R
82 0_0402_5%~D@
H
H
82 0_0402_5%~D@
83 0_0402_5%~D@
83 0_0402_5%~D@
H
H
R
R
85 0_0402_5%~D@
H
H
85 0_0402_5%~D@
R
R
H
H
86 0_0402_5%~D@
86 0_0402_5%~D@
R
R
R
R
87 10K_0402_5%~D
87 10K_0402_5%~D
H
H
H88 0_0402_5%~D@RH88 0_0402_5%~D@
R
R
R
90 0_0402_5%~D@
90 0_0402_5%~D@
H
H
R
R
H
152 10K_0402_5%~D
152 10K_0402_5%~D
H
H
H
92 0_0402_5%~D@
92 0_0402_5%~D@
R
R
93 0_0402_5%~D@
93 0_0402_5%~D@
H
H
R
R
94 10K_0402_5%~D
94 10K_0402_5%~D
RH
RH
95 0_0402_5%~D@
95 0_0402_5%~D@
H
H
R
R
96 0_0402_5%~D@
96 0_0402_5%~D@
H
H
R
R
97 10K_0402_5%~D
97 10K_0402_5%~D
H
H
R
R
H
98 10K_0402_5%~D
98 10K_0402_5%~D
H
R
R
310 0_0402_5%~D@
310 0_0402_5%~D@
H
H
R
R
H
H
312 0_0402_5%~D@
312 0_0402_5%~D@
R
R
104 10K_0402_5%~D
H
H
104 10K_0402_5%~D
R
R
280 0_0402_5%~D@
H
H
280 0_0402_5%~D@
R
R
281 0_0402_5%~D@
H
H
281 0_0402_5%~D@
R
R
AN (Mini Card 1)--->
W
W
WLAN (Mini Card 2)--->
PRESS Card--->
X
E
3
Module Bay--->
E
2 MINI CARD-3 PCIE
/
1
(Mini Card 3)--->
M
I --->
C C
0
1
W
AN (Mini Card 1)--->
W
P
B B
P
M
/100/1G LAN --->
0
/100/1G LAN --->
1
M
I--->
M
(Mini Card 3)--->
press card--->
x
E
WLAN (Mini Card 2)--->
eModule Bay--->
A A
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
5
1 2
2
1 2
4
12
12
12
12
12
12
12
12
12
12
1
12
12
12
12
12
12
12
12
12
12
4
P
C
IE_PRX_WANTX_N1
P
C
IE_PRX_WANTX_P1
P
IE_PTX_WANRX_N1
C
P
IE_PTX_WANRX_P1
C
P
IE_PRX_WLANTX_N2
C
P
IE_PRX_WLANTX_P2
C
P
IE_PTX_WLANRX_N2
C
P
C
IE_PTX_WLANRX_P2
P
IE_PRX_EXPTX_N3
C
P
IE_PRX_EXPTX_P3
C
P
IE_PTX_EXPRX_N3
C
P
IE_PTX_EXPRX_P3
C
P
C
IE_PRX_EMBTX_N4
P
C
IE_PRX_EMBTX_P4
P
IE_PTX_EMBRX_N4
C
P
IE_PTX_EMBRX_P4
C
P
IE_PRX_WPANTX_N5
C
P
IE_PRX_WPANTX_P5
C
P
IE_PTX_WPANRX_N5
C
P
C
IE_PTX_WPANRX_P5
P
IE_PRX_MMITX_N6
C
P
C
IE_PRX_MMITX_P6
P
IE_PTX_MMIRX_N6
C
P
CIE_PTX_MMIRX_P6
P
IE_PRX_GLANTX_N7
C
P
C
IE_PRX_GLANTX_P7
P
C
IE_PTX_GLANRX_N7
P
IE_PTX_GLANRX_P7
C
P
C
IE_MINI1#
P
IE_MINI1
C
M
NI1CLK_REQ#
I
P
IE_LAN#
C
P
IE_LAN
C
L
A
NCLK_REQ#
P
C
IE_MMI#
P
IE_MMI
C
M
ICLK_REQ#
M
P
IE_MINI3#
C
P
IE_MINI3
C
M
NI3CLK_REQ#
I
P
IE_EXP#
C
P
C
IE_EXP
E
PCLK_REQ#
X
P
IE_MINI2#
C
P
IE_MINI2
C
M
NI2CLK_REQ#
I
P
E
G_B_CLKRQ#
P
IE_EMB#
C
P
C
IE_EMB
E
BCLK_REQ#
M
C
L
K_BCLK_ITP#
C
L
K_BCLK_ITP
U
U
H
H
4B
4B
BG34
P
E
RN1
BJ34
P
E
RP1
AV32
P
TN1
E
AU32
P
TP1
E
BE34
P
E
RN2
BF34
P
E
RP2
BB32
P
E
TN2
AY32
P
E
TP2
BG36
P
RN3
E
BJ36
P
RP3
E
AV34
P
E
TN3
AU34
P
E
TP3
BF36
P
RN4
E
BE36
P
E
RP4
AY34
P
TN4
E
BB34
P
E
TP4
BG37
P
E
RN5
BH37
P
RP5
E
AY36
P
TN5
E
BB36
P
TP5
E
BJ38
P
RN6
E
BG38
P
RP6
E
AU36
P
TN6
E
AV36
P
E
TP6
BG40
P
E
RN7
BJ40
P
E
RP7
AY40
P
TN7
E
BB40
P
TP7
E
BE38
P
RN8
E
BC38
P
RP8
E
AW38
P
E
TN8
AY38
P
E
TP8
Y40
C
KOUT_PCIE0N
L
Y39
C
L
KOUT_PCIE0P
J2
P
IECLKRQ0# / GPIO73
C
AB49
C
KOUT_PCIE1N
L
AB47
C
KOUT_PCIE1P
L
M1
P
IECLKRQ1# / GPIO18
C
AA48
C
L
KOUT_PCIE2N
AA47
C
L
KOUT_PCIE2P
V10
P
IECLKRQ2# / GPIO20
C
Y37
C
LKOUT_PCIE3N
Y36
C
L
KOUT_PCIE3P
A8
P
C
IECLKRQ3# / GPIO25
Y43
C
LKOUT_PCIE4N
Y45
C
L
KOUT_PCIE4P
L12
P
IECLKRQ4# / GPIO26
C
V45
C
L
KOUT_PCIE5N
V46
C
L
KOUT_PCIE5P
L14
P
C
IECLKRQ5# / GPIO44
AB42
C
L
KOUT_PEG_B_N
AB40
C
L
KOUT_PEG_B_P
E6
P
E
G_B_CLKRQ# / GPIO56
V40
C
KOUT_PCIE6N
L
V42
C
L
KOUT_PCIE6P
T13
P
C
IECLKRQ6# / GPIO45
V38
C
L
KOUT_PCIE7N
V37
C
KOUT_PCIE7P
L
K12
P
C
IECLKRQ7# / GPIO46
AK14
C
L
KOUT_ITPXDP_N
AK13
C
KOUT_ITPXDP_P
L
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
3
P
H_SMB_ALERT#
C
S
M
S
BDATA
M
S
L0CLK
M
S
M
L0DATA
C
L
_CLK1
C
_DATA1
L
C
L
_RST1#
KIN_DMI_N
KIN_DMI_P
L
FCLK14IN
E
X
T
AL25_IN
T
AL25_OUT
BCLK
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
M
E
M_SMBCLK
M
M_SMBDATA
E
D
D
R_HVREF_RST_PCH
L
A
N_SMBCLK
L
N_SMBDATA
A
P
C
H_GPIO74
S
L1_SMBCLK
M
S
L1_SMBDATA
M
P
CH_CL_CLK1
P
C
H_CL_DATA1
P
C
H_CL_RST1#
P
E
G_A_CLKRQ#
C
K_CPU_DMI#
L
C
K_CPU_DMI
L
C
L
K_BUF_DMI#
C
K_BUF_DMI
L
C
L
K_BUF_BCLK
C
L
K_BUF_BCLK
C
K_BUF_DOT96#
L
C
LK_BUF_DOT96
C
K_BUF_CKSSCD#
L
C
K_BUF_CKSSCD
L
C
L
K_PCH_14M
C
L
K_PCI_LOOPBACK
X
T
AL25_IN
X
T
AL25_OUT
X
C
LK_RCOMP
P
I_TPM_TCM
C
S
I
O_14M
C
LK_80H
J
TWAY_14M
E
S
BALERT# / GPIO11
M
S
M
L0ALERT# / GPIO60
MBUSController
MBUSController
S
S
S
L1ALERT# / PCHHOT# / GPIO74
M
S
M
L1CLK / GPIO58
S
L1DATA / GPIO75
M
CI-E*
CI-E*
P
P
Link
Link
P
E
G_A_CLKRQ# / GPIO47
C
L
KOUT_PEG_A_N
C
KOUT_PEG_A_P
L
C
L
KOUT_DMI_N
C
L
LOCKS
LOCKS
C
C
LEX CLOCKS
LEX CLOCKS
F
F
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
ARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P
3
KOUT_DMI_P
C
KOUT_DP_N
L
C
KOUT_DP_P
L
C
L
C
C
KIN_GND1_N
L
C
L
KIN_GND1_P
C
KIN_DOT_96N
L
C
L
KIN_DOT_96P
C
L
KIN_SATA_N
C
KIN_SATA_P
L
R
C
L
KIN_PCILOOPBACK
X
X
CLK_RCOMP
C
L
KOUTFLEX0 / GPIO64
C
L
KOUTFLEX1 / GPIO65
C
L
KOUTFLEX2 / GPIO66
C
KOUTFLEX3 / GPIO67
L
2
M
E
M_SMBCLK
ME
M_SMBDATA
R_HVREF_RST_PCH <7>
D
D
A
N_SMBCLK <31>
L
N_SMBDATA <31>
A
L
M
L1_SMBCLK <40>
S
S
ML1_SMBDATA <40>
P
C
H_CL_CLK1 <34>
P
H_CL_DATA1 <34>
C
P
C
H_CL_RST1# <34>
L
K_CPU_DMI# <7>
C
L
K_CPU_DMI <7>
C
K_PCI_LOOPBACK <17>
L
C
1 2
R
R
H
H
100 90.9_0402_1 %~D
100 90.9_0402_1 %~D
311 22_0402_5%~D1@
H
H
311 22_0402_5%~D1@
R
R
313 22_0402_5%~D
313 22_0402_5%~D
H
H
R
R
314 22_0402_5%~D
314 22_0402_5%~D
H
H
R
R
R
R
315 22_0402_5%~D@
315 22_0402_5%~D@
H
H
12
12
12
12
2
+
3
.3V_RUN
H
H
5A
5A
Q
Q
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
4
3
H
H
5B
5B
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
S
L1_SMBCLK
M
S
L1_SMBDATA
M
D
D
R_HVREF_RST_PCH
P
H_GPIO74
C
M
M_SMBCLK
E
M
E
M_SMBDATA
P
C
H_SMB_ALERT#
P
G_A_CLKRQ#
E
L
N_SMBCLK
A
L
N_SMBDATA
A
C
LK_BUF_DMI#
C
L
K_BUF_DMI
C
K_BUF_BCLK
L
C
K_BUF_DOT96#
L
C
L
K_BUF_DOT96
C
K_BUF_CKSSCD#
L
C
L
K_BUF_CKSSCD
C
L
K_PCH_14M
LOCK TERMINATION for FCIM and need close to PCH
C
+
.05V_RUN
1
K_PCI_TPM_TCM <32>
L
C
L
K_SIO_14M <39>
C
LK_80H <34>
C
P
E
TWAY_CLK14M <32>
J
LL CONFIDENTIAL/PROPRIETARY
E
D
tle
i
i
Title
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
D
D
RH
RH
H
H
R
R
H
R
R
H
H
H
R
R
R
R
H
H
H
H
R
R
H
H
R
R
R
R
H
H
H
H
R
R
H
H
R
R
H
H
R
R
H
H
R
R
H
H
R
R
RH
RH
H
H
R
R
H78 10K_0402_5%~D
H
R
R
H
H
R
R
R
R
H
H
12
99
99
H
H
R
R
1M_0402_5%~D
1M_0402_5%~D
25MHZ_10PF_Q22FA2380049900~D
25MHZ_10PF_Q22FA2380049900~D
2
18
18
H
H
C
C
1
8.2P_0402_50V8D~D
8.2P_0402_50V8D~D
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
P
P
P
L
L
L
1
R_XDP_WAN_SM BCLK <7,12,13,14,27,34>
D
R_XDP_WAN_SM BDAT <7,12,13,14,27,34>
D
+
3
.3V_ALW_PCH
1 2
298 2.2K_0402 _5%~D
298 2.2K_0402 _5%~D
1 2
299 2.2K_0402 _5%~D
299 2.2K_0402 _5%~D
300 1K_ 0402_5%~D
300 1K_ 0402_5%~D
301 10K _0402_5%~D
301 10K _0402_5%~D
302 2.2K_0402 _5%~D
302 2.2K_0402 _5%~D
303 2.2K_0402 _5%~D
303 2.2K_0402 _5%~D
304 10K _0402_5%~D
304 10K _0402_5%~D
80 10K_0402_5%~D
80 10K_0402_5%~D
305 2.2K_0402 _5%~D
305 2.2K_0402 _5%~D
306 2.2K_0402 _5%~D
306 2.2K_0402 _5%~D
1
74 10K_0402_5%~D
74 10K_0402_5%~D
1 2
75 10K_0402_5%~D
75 10K_0402_5%~D
1
91 10K_0402_5%~D
91 10K_0402_5%~D
1
76 10K_0402_5%~D
76 10K_0402_5%~D
1 2
77 10K_0402_5%~D
77 10K_0402_5%~D
1 2
78 10K_0402_5%~D
1 2
79 10K_0402_5%~D
79 10K_0402_5%~D
1 2
183 10K_0402_5%~D
183 10K_0402_5%~D
H
H
309 0_0402_5%~D@
309 0_0402_5%~D@
R
R
3
4
C
C
C
H (2/8)
H (2/8)
H (2/8)
-7781
-7781
A
A
A
-7781
+
.3V_ALW_PCH
3
12
12
12
12
12
12
+
3
.3V_LAN
12
12
2
2
2
2
1
H
H
2
2
Y
Y
1
N
U
T
I
O
2
D
D
N
N
G
G
1
2
1
5 6
5 6
5 6
1
1
1
f
f
f
o
o
o
19
19
H
H
C
C
8.2P_0402_50V8D~D
8.2P_0402_50V8D~D
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+
.3V_ALW_PCH
3
S
U
1 2
R
R
318 10K_0402_5%~D@
318 10K_0402_5%~D@
H
H
1 2
RH
RH
144 10K_0402_5%~D
144 10K_0402_5%~D
D D
+
3
.3V_RUN
C C
+
1
.05V_RUN
SACK#< 39>
U
S
B B
Y
S_PWROK<7, 39>
S
SET_OUT#<4 0>
E
R
_DRAM_PWRGD<7>
M
P
C
H_RSMRST#_Q<1 4,41>
P
_SUS_PWR_ACK<40>
E
M
IO_PWRBTN#_R<7,14>
S
I
O_PWRBTN#<40>
S
C
_PRESENT<40>
A
+
3
.3V_ALW_PCH
A A
1
R
R
142 10K_0402_5%~D
142 10K_0402_5%~D
H
H
1 2
R
R
319 10K_0402_5%~D@
319 10K_0402_5%~D@
H
H
1 2
H
H
140 10K_0402_5%~D
140 10K_0402_5%~D
R
R
1 2
H
H
137 8. 2K_0402_5%~D
137 8. 2K_0402_5%~D
R
R
1 2
R
R
H
H
138 8. 2K_0402_5%~D@
138 8. 2K_0402_5%~D@
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
1 2
R
R
H
H
111 49.9_0402_1%~D
111 49.9_0402_1%~D
1 2
R
R
H112 750_0402_1%~D
H112 750_0402_1%~D
1 2
114 0_0402_5%~D@
RH
RH
114 0_0402_5%~D@
1 2
116 0_0402_5%~D@
116 0_0402_5%~D@
H
H
R
R
1
R
R
H
H
117 0_0402_5%~D@
117 0_0402_5%~D@
1 2
R
R
320 0_0402_5%~D@
H
H
320 0_0402_5%~D@
1 2
H
H
120 0_0402_5%~D@
120 0_0402_5%~D@
R
R
1
H
H
121 0_0402_5%~D@
121 0_0402_5%~D@
R
R
1 2
R
R
122 0_0402_5%~D@
H
H
122 0_0402_5%~D@
1
R
R
H
H
139 8.2K_0402_5%~D
139 8.2K_0402_5%~D
S_STAT#/LPCPD#
_SUS_PWR_ACK
ME
P
H_PCIE_WAKE#
C
2
S
I
O_SLP_LAN#
P
H_RI#
C
C
KRUN#
L
M
_RESET#
E
D
I_CTX_PRX_N0
2
2
2
D
I_COMP_R
M
R
BIAS_CPY
M
D
I_CTX_PRX_N1
M
D
M
I_CTX_PRX_N2
D
I_CTX_PRX_N3
M
D
I_CTX_PRX_P0
M
D
M
I_CTX_PRX_P1
D
I_CTX_PRX_P2
M
D
M
I_CTX_PRX_P3
D
I_CRX_PTX_N0
M
D
I_CRX_PTX_N1
M
D
M
I_CRX_PTX_N2
D
M
I_CRX_PTX_N3
D
M
I_CRX_PTX_P0
D
I_CRX_PTX_P1
M
D
M
I_CRX_PTX_P2
D
I_CRX_PTX_P3
M
S
U
SACK#_R
S
Y
S_RESET#
S
S_PWROK_R
Y
P
H_PWROK
C
P
_APWROK_R
M
P
_DRAM_PWRGD_R
M
P
C
H_RSMRST#_R
M
_SUS_PWR_ACK_R
E
S
I
O_PWRBTN#_R
A
_PRESENT
C
P
C
H_BATLOW#
P
H_RI#
C
I_CTX_PRX_N0<6>
I_CTX_PRX_N1<6>
I_CTX_PRX_N2<6>
I_CTX_PRX_N3<6>
I_CTX_PRX_P0<6>
I_CTX_PRX_P1<6>
I_CTX_PRX_P2<6>
I_CTX_PRX_P3<6>
I_CRX_PTX_N0<6>
I_CRX_PTX_N1<6>
I_CRX_PTX_N2<6>
I_CRX_PTX_N3<6>
I_CRX_PTX_P0<6>
I_CRX_PTX_P1<6>
I_CRX_PTX_P2<6>
I_CRX_PTX_P3<6>
XD
P_DBRESET#<7 ,14>
M
E
_SUS_PWR_ACK_R
U
U
4C
H
H
4C
BC24
D
I0RXN
M
BE20
D
I1RXN
M
BG18
D
I2RXN
M
BG20
D
M
I3RXN
BE24
D
I0RXP
M
BC20
D
M
I1RXP
BJ18
D
M
I2RXP
BJ20
D
M
I3RXP
AW24
D
I0TXN
M
AW20
D
M
I1TXN
BB18
D
M
I2TXN
AV18
D
M
I3TXN
AY24
D
M
I0TXP
AY20
D
M
I1TXP
AY18
D
I2TXP
M
AU18
D
I3TXP
M
BJ24
D
M
I_ZCOMP
BG25
D
I_IRCOMP
M
BH21
M
I2RBIAS
D
C12
U
SACK#
S
K3
S
S_RESET#
Y
P12
S
Y
S_PWROK
L22
W
ROK
P
L10
P
WROK
A
B13
R
AMPWROK
D
C21
MRST#
S
R
K16
SWARN#/SUSPWRDNACK/GPIO30
U
S
E20
P
W
RBTN#
H20
PRESENT / GPIO31
C
A
E10
A
TLOW# / GPIO72
B
A10
I
#
R
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
P
R
E
SET_OUT#
R
R
C
H_DPWROK
4
357 0_0402_5%~D@RH357 0_0402_5%~D@
RH
1 2
+
3.3V_RUN
U
U
3
@
3
@
C
C
1
E
_RESET#
P
C
H_RSMRST#_R
S
Y
S
U
F
I_RXN0
D
F
I_RXN1
D
F
D
I_RXN2
F
I_RXN3
D
F
I_RXN4
D
F
D
I_RXN5
F
D
I_RXN6
F
I_RXN7
D
F
D
I_RXP0
F
D
I_RXP1
F
D
I_RXP2
F
I_RXP3
D
F
D
I_RXP4
F
D
I_RXP5
F
I_RXP6
D
F
I_RXP7
D
F
D
F
I_FSYNC0
D
F
I_FSYNC1
D
F
D
I_LSYNC0
F
I_LSYNC1
D
WVRMEN
S
D
WROK
P
D
W
U
SCLK / GPIO62
P_S5# / GPIO63
S
P_S4#
L
S
L
P_S3#
L
S
S
LP_SUS#
P
SYNCH
M
B
2
A
S_PWROK
SACK#_R
I_INT
KE#
A
P_A#
M
12
141 8.2K_0402_5%~D@
141 8.2K_0402_5%~D@
H
H
1 2
R
R
H
H
113 0_0402_5%~D@
113 0_0402_5%~D@
1 2
H
H
321 0_0402_5%~D@
321 0_0402_5%~D@
R
R
1 2
RH
323 0_0402_5%~D@RH323 0_0402_5%~D@
DI
DI
DMIF
DMIF
KRUN# / GPIO32
L
C
U
S_STAT# / GPIO61
S
S
S
L
ystem Power Management
ystem Power Management
S
S
P_LAN# / GPIO29
L
S
C
C
99
@
99
@
H
H
1 2
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
P
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
F
D
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
I_CTX_PRX_N0
F
I_CTX_PRX_N1
D
F
I_CTX_PRX_N2
D
F
I_CTX_PRX_N3
D
F
D
I_CTX_PRX_N4
F
D
I_CTX_PRX_N5
F
D
I_CTX_PRX_N6
F
I_CTX_PRX_N7
D
F
I_CTX_PRX_P0
D
F
I_CTX_PRX_P1
D
F
DI_CTX_PRX_P2
F
D
I_CTX_PRX_P3
F
D
I_CTX_PRX_P4
F
D
I_CTX_PRX_P5
F
I_CTX_PRX_P6
D
F
I_CTX_PRX_P7
D
F
D
I_INT
F
D
I_FSYNC0
F
I_FSYNC1
D
F
I_LSYNC0
D
F
DI_LSYNC1
D
WODVREN
S
P
H_DPWROK
C
P
H_PCIE_WAKE#
C
C
KRUN#
L
S
S_STAT#/LPCPD#
U
S
U
SCLK
S
I
O_SLP_S5#
S
O_SLP_S4#
I
S
IO_SLP_S3#
S
O_SLP_A#
I
S
I
O_SLP_SUS#
H
PM_SYNC
_
S
O_SLP_LAN#
I
RH
RH
H
H
R
R
H
H
R
R
R
R
H
S
Y
S_RESET#
H
SWODVREN - On Die DSW VR Enable
D
Enabled (DEFAULT)
Disabled
D
I_CTX_PRX_N0 <6>
F
D
I_CTX_PRX_N1 <6>
F
D
I_CTX_PRX_N2 <6>
F
I_CTX_PRX_N3 <6>
D
F
I_CTX_PRX_N4 <6>
D
F
I_CTX_PRX_N5 <6>
D
F
D
I_CTX_PRX_N6 <6>
F
I_CTX_PRX_N7 <6>
D
F
D
I_CTX_PRX_P0 <6>
F
I_CTX_PRX_P1 <6>
D
F
I_CTX_PRX_P2 <6>
D
F
I_CTX_PRX_P3 <6>
D
F
I_CTX_PRX_P4 <6>
D
F
I_CTX_PRX_P5 <6>
D
F
D
I_CTX_PRX_P6 <6>
F
D
I_CTX_PRX_P7 <6>
F
D
I_INT <6>
F
I_FSYNC0 <6>
D
F
D
I_FSYNC1 <6>
F
D
I_LSYNC0 <6 >
F
I_LSYNC1 <6 >
D
F
H
H
127 330K_0402_1%~D
127 330K_0402_1%~D
R
R
1 2
R
R
H
H
129 330K_0402_1%~D@
129 330K_0402_1%~D@
1 2
H_DPWROK <39>
C
P
C
H_PCIE_WAKE# <40>
P
LKRUN# <32,39,40>
C
6 PAD~D
5
5
6 PAD~D
T
T
7 PAD~D
5
5
7 PAD~D
T
T
5
5
8 PAD~D
8 PAD~D
T
T
IO_SLP_S5# <40>
S
9 PAD~D
5
5
9 PAD~D
T
T
O_SLP_S4# <39,42,4 6>
I
S
I
O_SLP_S3# <11,27,3 5,39,42,47>
S
I
O_SLP_A# <39,42,48>
S
62 PAD~D
62 PAD~D
T
T
I
O_SLP_SUS# <39>
S
T
T
3 PAD~D
6
6
3 PAD~D
_
PM_SYNC <7>
H
IO_SLP_LAN# <31,39>
S
3
P
H_CRT_BLU
1 2
131 150 _0402_1%~D
131 150 _0402_1%~D
1 2
132 150 _0402_1%~D
132 150 _0402_1%~D
1 2
133 150 _0402_1%~D
133 150 _0402_1%~D
1 2
134 100 K_0402_5%~D
134 100 K_0402_5%~D
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
LOW: RH129 STUFFED,
RH127 UNSTUFFED
C
P
CH_CRT_GRN
P
C
H_CRT_RED
E
VDD_PCH
N
L
L
inimum speacing of 20mils for LVD_IBG
M
+
R
TC_CELL
H_CRT_HSYNC<23>
C
P
CH_CRT_VSYNC<23>
P
2.2K_0402_5%~D
2.2K_0402_5%~D
A
NEL_BKEN_PCH<24>
P
N
VDD_PCH<24,39>
E
I
A_PWM_PCH<24 >
B
D
DC_CLK_PCH<24>
D
DC_DATA_PCH<24>
1 2
R
R
344 2.37 K_0402_1%~D
344 2.37 K_0402_1%~D
H
H
D_ACLK-_PCH<24>
C
L
D_ACLK+_PCH<24>
C
L
D_A0-_PCH<24>
C
L
D_A1-_PCH<24>
C
L
D_A2-_PCH<24>
C
L
D_A0+_PCH<24>
C
L
C
D_A1+_PCH<24>
L
C
D_A2+_PCH<24>
L
C
D_BCLK-_PCH<24>
L
C
D_BCLK+_PCH<24>
L
D_B0-_PCH<24>
C
L
D_B1-_PCH<24>
C
L
D_B2-_PCH<24>
C
L
D_B0+_PCH<24>
C
L
D_B1+_PCH<24>
C
L
D_B2+_PCH<24>
C
L
C
H_CRT_BLU<23>
P
C
H_CRT_GRN<23>
P
C
H_CRT_RED<23>
P
R
R
123 20_0402_1%~D
123 20_0402_1%~D
H
H
1 2
1 2
R
R
124 20_0402_1%~D
H
H
124 20_0402_1%~D
1K_0402_0.5%~D
1K_0402_0.5%~D
+
.3V_RUN
3
12
12
R
R
H
H
316
316
_APWROK<40>
M
P
P
NEL_BKEN_PCH
A
E
N
VDD_PCH
B
I
A_PWM_PCH
L
DC_CLK_PCH
D
L
DC_DATA_PCH
D
L
V
D_IBG
L
C
D_ACLK-_PCH
L
C
D_ACLK+_PCH
L
C
D_A0-_PCH
L
C
D_A1-_PCH
L
C
D_A2-_PCH
L
C
D_A0+_PCH
L
C
D_A1+_PCH
L
D_A2+_PCH
C
L
D_BCLK-_PCH
C
L
D_BCLK+_PCH
C
L
C
D_B0-_PCH
L
C
D_B1-_PCH
L
C
D_B2-_PCH
L
CD_B0+_PCH
L
D_B1+_PCH
C
L
D_B2+_PCH
C
P
CH_CRT_BLU
P
CH_CRT_GRN
P
C
H_CRT_RED
P
H_CRT_DDC_CLK
C
P
C
H_CRT_DDC_DAT
H
S
V
S
R
R
H
H
126
126
YNC
YNC
2
2.2K_0402_5%~D
2.2K_0402_5%~D
R
R
H
H
317
317
P
H_CRT_DDC_CLK
C
P
C
H_CRT_DDC_DAT
S
O_SLP_A#
I
P
M
_APWROK
J47
M45
P45
T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
C
T_IREF
R
T43
12
T42
+
3
.3V_ALW2
5
1
P
B
2
A
G
3
1 2
R
R
H
H
118 0_0402_5%~D@
118 0_0402_5%~D@
tel request DDPB can not support eDP
n
I
4D
H
H
4D
U
U
BKLTEN
_
L
_
VDD_EN
L
BKLTCTL
_
L
DDC_CLK
_
L
DDC_DATA
_
L
_
CTRL_CLK
L
_
CTRL_DATA
L
D_IBG
V
L
D_VBG
V
L
D_VREFH
V
L
D_VREFL
V
L
V
DSA_CLK#
L
DSA_CLK
V
L
V
DSA_DATA#0
L
V
DSA_DATA#1
L
V
DSA_DATA#2
L
V
DSA_DATA#3
L
V
DSA_DATA0
L
V
DSA_DATA1
L
V
DSA_DATA2
L
DSA_DATA3
V
L
V
DSB_CLK#
L
V
DSB_CLK
L
V
DSB_DATA#0
L
V
DSB_DATA#1
L
V
DSB_DATA#2
L
V
DSB_DATA#3
L
V
DSB_DATA0
L
DSB_DATA1
V
L
DSB_DATA2
V
L
V
DSB_DATA3
L
R
T_BLUE
C
T_GREEN
R
C
T_RED
R
C
R
T_DDC_CLK
C
RT_DDC_DATA
C
R
T_HSYNC
C
T_VSYNC
R
C
C_IREF
A
D
R
T_IRTN
C
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
C
H_CRT_DDC_CLK <23>
P
H_CRT_DDC_DAT <23>
C
P
1 2
CH
CH
108 0.1U_0402_25V6K~D
108 0.1U_0402_25V6K~D
5
5
H
H
U
U
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
P
M_APWROK_R
4
O
VO_STALLN
VO_STALLP
S
VO_INTN
D
SD
VO_INTP
D
PB_AUXN
D
PB_AUXP
DD
DD
PB_HPD
DPB_0N
D
D
PB_0P
D
D
PB_1N
D
D
PB_1P
D
D
PB_2N
D
D
PB_2P
D
D
PB_3N
D
PB_3P
D
D
D
PC_AUXN
D
PC_AUXP
DD
DDPC_HPD
PC_0N
D
D
PC_0P
D
D
D
PC_1N
D
PC_1P
D
D
PC_2N
D
D
PC_2P
D
D
PC_3N
D
D
PC_3P
D
D
D
PD_AUXN
D
PD_AUXP
DD
DD
PD_HPD
PD_0N
D
D
D
PD_0P
D
D
PD_1N
D
D
PD_1P
D
PD_2N
D
D
D
PD_2P
D
PD_3N
D
D
D
PD_3P
D
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
SD
VO_TVCLKINN
SD
VO_TVCLKINP
SD
SD
D
VO_CTRLCLK
S
D
VO_CTRLDATA
S
VDS
VDS
L
L
PC_CTRLCLK
D
D
DPC_CTRLDATA
D
Digital Display Interface
Digital Display Interface
PD_CTRLCLK
D
D
PD_CTRLDATA
D
D
RT
RT
C
C
P
C
H_SDVO_CTRLCLK
P
H_SDVO_CTRLDATA
C
P
C
H_SDVO_CTRLCLK
P
H_SDVO_CTRLDATA
C
H
M
T
M
T
M
T
M
T
M
T
M
T
M
T
M
T
P
P
D
D
P
D
P
D
P
D
P
D
P
D
P
D
D
P
D
D
P
PD_PCH_DOCK_AUX# <26>
D
P
D
PD_PCH_DOCK_HPD <38>
D
P
D
P
D
P
D
P
D
P
D
P
D
PD_PCH_LANE_N3 <38>
D
P
D
P
P
P
1
H
H
351 2. 2K_0402_5%~D
351 2. 2K_0402_5%~D
R
R
R
R
H
H
352 2. 2K_0402_5%~D
352 2. 2K_0402_5%~D
H_SDVO_CTRLCLK <25>
C
P
H_SDVO_CTRLDATA < 25>
C
P
MIB_PCH_HPD <25>
D
DSB_PCH_N2 <25>
DSB_PCH_P2 <25>
DSB_PCH_N1 <25>
DSB_PCH_P1 <25>
DSB_PCH_N0 <25>
DSB_PCH_P0 <25>
DSB_PCH_CLK# <25>
DSB_PCH_CLK <25>
H_DDPC_CTRLCLK <26>
C
C
H_DDPC_CTRLDATA <26>
P
C_PCH_DOCK_AUX# <26>
C_PCH_DOCK_AUX <26>
C_PCH_DOCK_HPD <38>
C_PCH_LANE_N0 <38>
C_PCH_LANE_P0 < 38>
C_PCH_LANE_N1 <38>
C_PCH_LANE_P1 < 38>
C_PCH_LANE_N2 <38>
C_PCH_LANE_P2 < 38>
C_PCH_LANE_N3 <38>
C_PCH_LANE_P3 < 38>
H_DDPD_CTRLCLK <26>
C
H_DDPD_CTRLDATA <26>
C
P
D_PCH_DOCK_AUX <26>
D_PCH_LANE_N0 <38>
D_PCH_LANE_P0 < 38>
D_PCH_LANE_N1 <38>
D_PCH_LANE_P1 < 38>
D_PCH_LANE_N2 <38>
D_PCH_LANE_P2 < 38>
D_PCH_LANE_P3 < 38>
+
.3V_RUN
3
12
12
LL CONFIDENTIAL/PROPRIETARY
E
D
pal Electronics, Inc.
om
om
om
pal Electronics, Inc.
pal Electronics, Inc.
C
C
Title
i
i
tle
tle
T
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P
5
4
3
2
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
H (3/8)
C
C
C
H (3/8)
H (3/8)
P
P
P
0
.
.
.
0
0
1
1
L
L
L
-7781
A
A
A
-7781
-7781
6 6
6 6
6 6
1
1
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
5
+
3
.3V_RUN
P
C
I_PIRQA#
2
1
H
324 8.2K_0402_5%~D
324 8.2K_0402_5%~D
H
R
D D
C C
R
1 2
325 8.2K_0402_5%~D
325 8.2K_0402_5%~D
H
H
R
R
1
R
R
H
326 8.2K_0402_5%~D
326 8.2K_0402_5%~D
H
1 2
R
R
329 8.2K_0402_5%~D
329 8.2K_0402_5%~D
H
H
1 2
327 10K_0402_5%~D
327 10K_0402_5%~D
H
H
R
R
1 2
R
R
H
H
330 10K_0402_5%~D
330 10K_0402_5%~D
1 2
H
H
328 10K_0402_5%~D
328 10K_0402_5%~D
R
R
1 2
R
R
332 10K_0402_5%~D
332 10K_0402_5%~D
H
H
1 2
H
H
331 10K_0402_5%~D
331 10K_0402_5%~D
R
R
1 2
359 10K_0402_5%~D
359 10K_0402_5%~D
H
H
R
R
P
C
I_GNT3#
12
H
H
333
@
333
@
R
R
1K_0402_5%~D
1K_0402_5%~D
1
6 swap override Strap/Top-Bloc k
A
P
I_PIRQB#
C
P
CI_PIRQC#
2
P
CI_PIRQD#
P
C
I_REQ1#
L
D_CBL_DET#
C
B
_DET#
T
P
H_GPIO3
C
C
M_MIC_CBL_DET#
A
P
C
IE_MCARD2_DET#
Swap Override jumper
P
C
IE_MCARD2_DET#<34>
C
1 2
334 0_0402_5%~D@
H
H
334 0_0402_5%~D@
R
R
H
H
160 22_0402_5%~D
160 22_0402_5%~D
R
R
H102 22_0402_5%~D
H102 22_0402_5%~D
R
R
R
R
H
H
103 22_0402_5%~D
103 22_0402_5%~D
R
R
H
H
105 22_0402_5%~D
105 22_0402_5%~D
C
K_PCI_5048
L
1
C
C
110
H
H
110
12P_0402_50V8J~D
12P_0402_50V8J~D
2
P
H_PLTRST#_EC <32,34,35,39,40>
C
H_PLTRST#<7,14>
Low = A16 swap
High = Default
P
L
TRST_USH#<32>
P
L
TRST_MMI#<33>
P
TRST_XDP#<7>
L
P
TRST_LAN#<31>
L
LTRST_EMB#<28>
P
P
C
H_PLTRST#
5
+
3.3V_RUN
1
2
5
P
B
A
G
3
H
D_FALL_INT<27>
D
1 2
R
R
H
H
335 0_0402_5%~D@
335 0_0402_5%~D@
1 2
R
R
336 0_0402_5%~D@
336 0_0402_5%~D@
H
H
1 2
H337 0_0402_5%~D@RH337 0_0402_5%~D@
R
1 2
R
R
338 0_0402_5%~D@
338 0_0402_5%~D@
H
H
1 2
340 0_0402_5%~D@
H
H
340 0_0402_5%~D@
R
R
C
LK_PCI_5048<39>
C
K_PCI_MEC<40>
L
C
L
K_PCI_DOCK<38>
C
K_PCI_LOOPBACK<15>
L
C
C
102
H
H
102
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
3
H
H
3
U
U
P
H_PLTRST#_EC
C
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
CI_GNT#3
P
B B
A A
C
P
4
H
H
4E
4E
U
U
BG26
T
1
P
BJ26
T
P
2
BH25
T
3
P
BJ16
T
4
P
BG16
T
P
5
AH38
T
P
6
AH37
T
P
7
AK43
T
P
8
AK45
T
9
P
C18
T
10
P
N30
T
P11
H3
T
P
12
AH12
T
P
13
AM4
T
P
14
AM5
T
P
15
Y13
T
P
16
K24
T
P
17
L24
T
P
18
AB46
T
P
19
AB45
T
20
P
SVD
21
22
23
24
B3Rn1
B3Rn2
B3Rn3
B3Rn4
B3Rp1
B3Rp2
B3Rp3
B3Rp4
B3Tn1
B3Tn2
B3Tn3
B3Tn4
B3TP1
B3Tp2
B3Tp3
B3Tp4
Q1# / GPIO50
Q2# / GPIO52
Q3# / GPIO54
T1# / GPIO51
T2# / GPIO53
T3# / GPIO55
E#
KOUT_PCI0
KOUT_PCI1
KOUT_PCI2
KOUT_PCI3
KOUT_PCI4
SVD
R
R
SB30
SB30
U
U
CI
CI
P
P
SATA_SLPD
(BBS_BIT0)
B21
T
P
M20
T
P
AY16
T
P
BG46
T
P
I_5048
I_MEC
I_DOCK
BE28
U
S
BC30
U
S
BE32
U
S
BJ32
U
S
BC28
U
S
BE30
U
S
BF32
U
S
BG32
U
S
AV26
U
S
BB26
U
S
AU28
U
S
AY30
U
S
AU26
U
S
AY26
U
S
AV28
U
S
AW30
U
S
K40
IRQA#
P
K38
I
RQB#
P
H38
RQC#
I
P
G38
I
RQD#
P
C46
E
R
C44
E
R
E40
RE
D47
GN
E42
GN
F46
GN
G42
RQE# / GPIO2
PI
G40
PIRQF# / GPIO3
C42
PI
RQG# / GPIO4
D44
PI
RQH# / GPIO5
K10
P
M
C6
P
TRST#
L
H49
C
L
H43
C
L
J48
C
L
K42
C
L
H40
C
L
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
oot BIOS Strap
B
S
B3RN1<36>
U
SB3RN2<36>
U
S
B3RN4<38>
U
S
B3RP1<36>
U
S
B3RP2<36>
U
S
B3RP4<38>
U
S
B3TN1<36>
U
B3TN2<36>
S
U
S
B3TN4<38>
U
B3TP1<36>
S
U
B3TP2<36>
S
U
B3TP4<38>
S
U
P
CI_PIRQA#
P
I_PIRQB#
C
P
I_PIRQC#
C
P
I_PIRQD#
C
P
I_REQ1#
C
B
T
B
_DET#<41>
T
L
D_CBL_DET#<24>
C
M_MIC_CBL_DET#<24>
A
12
12
12
12
_DET#
B
BS_BIT1
P
I_GNT3#
C
L
D_CBL_DET#
C
P
C
H_GPIO3
C
A
M_MIC_CBL_DET#
F
F
S_PCH_INT
1
1
04PAD~D @
04PAD~D @
T
T
P
C
H_PLTRST#
P
P
P
P
I_LOOPBACKOUT
C
C
K_PCI_MEC
L
1
109
109
H
H
C
C
12P_0402_50V8J~D
12P_0402_50V8J~D
2
C
C
C
BBS_BIT1 Boot BIOS Location
0 0
0
1
1
*
4
1
0
1
3
USB
USB
O
C
O
C
O
C
O
C
O
C
O
O
C
O
C
LPC
eserved (NAND)
R
PCI
SPI
3
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
SVD9
R
VD10
S
R
VD11
S
R
S
VD12
R
SVD13
R
VD14
S
R
S
VD15
R
S
VD16
R
S
VD17
R
S
VD18
R
S
VD19
R
S
VD20
R
S
VD21
R
S
VD22
R
S
VD23
R
VD24
S
R
VD25
S
R
VD26
S
R
S
VD27
R
S
VD28
R
S
VD29
R
US
BP0N
US
BP0P
U
BP1N
S
U
BP1P
S
U
BP2N
S
U
BP2P
S
U
BP3N
S
U
S
BP3P
U
S
BP4N
U
S
BP4P
U
BP5N
S
U
BP5P
S
U
BP6N
S
U
BP6P
S
U
BP7N
S
U
BP7P
S
U
S
BP8N
U
S
BP8P
U
S
BP9N
U
BP9P
S
U
BP10N
S
U
BP10P
S
U
S
BP11N
U
S
BP11P
U
S
BP12N
U
BP12P
S
U
BP13N
S
U
BP13P
S
U
BRBIAS#
S
U
S
BRBIAS
0# / GPIO59
1# / GPIO40
2# / GPIO41
3# / GPIO42
4# / GPIO43
C
5# / GPIO9
6# / GPIO10
7# / GPIO14
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
SBP8-
U
SBP8+
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
SBP13+
U
S
U
SB_OC0#_R
U
B_OC1#_R
S
U
S
B_OC2#
U
B_OC3#
S
U
B_OC4#_R
S
U
B_OC5#
S
U
B_OC6#
S
2
BP0ÂBP0+
BP1ÂBP1+
BP2ÂBP2+
BP3ÂBP3+
BP4ÂBP4+
BP5ÂBP5+
BP6ÂBP6+
BP7ÂBP7+
BP9ÂBP9+
BP10ÂBP10+
BP11ÂBP11+
BP12ÂBP12+
BP13-
BRBIAS
U
S
BP0- <36>
U
S
BP0+ <36>
U
BP1- <36>
S
U
S
BP1+ <36>
U
BP2- <37>
S
U
BP2+ <37>
S
U
BP3- <38>
S
U
BP3+ <38>
S
U
SBP4- <34>
U
BP4+ <34>
S
U
SBP5- <34>
U
S
BP5+ <34>
U
S
BP6- <38>
U
S
BP6+ <38>
U
BP7- <32>
S
U
S
BP7+ <32>
U
BP8- <34>
S
U
BP8+ <34>
S
U
SBP9- <30>
U
S
BP9+ <30>
U
S
BP10- <35>
U
S
BP10+ <35>
U
BP11- <41>
S
U
BP11+ <41>
S
U
S
BP12- <24>
U
BP12+ <24>
S
U
S
BP13- <24>
U
BP13+ <24>
S
1 2
151
H
H
151
R
R
22.6_0402_1%~D
22.6_0402_1%~D
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
1 2
R
R
H
H
339 0_0402_5%~D@
339 0_0402_5%~D@
1 2
H
H
341 0_0402_5%~D@
341 0_0402_5%~D@
R
R
1
R
R
H
H
356 0_0402_5%~D@
356 0_0402_5%~D@
S
I
O_EXT_SMI#
B
S_BIT1
B
----->Right Side Top
-
--->Right Side Bottom
-
----->Right side E-SATA
----->MLK DOCK
-
--->WLAN/WIMAX
-
---->WWAN/UWB
-
--->DOCK
-
-
----->USH
----->Flash
----->Left side
----->Express Card
----->Blue Tooth
--->Camera
-
-
----->LCD Touch
2
1
342
@
342
@
H
H
R
R
1K_0402_5%~D
1K_0402_5%~D
2
2
U
S
U
S
U
SB_OC2# <14>
U
S
U
S
U
S
U
S
I
O_EXT_SMI# <14,40>
S
U
S
U
S
S
U
B_OC0# <36>
B_OC1# <36>
B_OC3# <14>
B_OC4# <30>
B_OC5# <14>
B_OC6# <14>
B_OC0#_R <14>
B_OC1#_R <14>
B_OC4#_R <14>
1
+
3
NTEL feedback 0307
I
U
B_OC0#_R
S
U
B_OC1#_R
S
U
B_OC3#
S
U
B_OC4#_R
S
10K_1206_8P4R_5%~D
U
U
S
U
LL CONFIDENTIAL/PROPRIETARY
E
D
Title
tle
i
itle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
10K_1206_8P4R_5%~D
B_OC5#
S
S
B_OC6#
I
O_EXT_SMI#
SB_OC2#
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
C
C
C
C
P
P
P
-7781
-7781
A
A
A
-7781
L
L
L
R
R
4 5
3 6
2 7
1 8
R
R
4 5
3 6
2 7
1 8
H (4/8)
H (4/8)
H (4/8)
1
H1
H1
P
P
H2
H2
P
P
.3V_ALW_PCH
7 61Friday, February 24, 2012
7 6
7 6
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
0
0
.
.
.
0
1
1
1
5
+
.3V_ALW_PCH
3
H
H
53
53
R
R
4.7K_0402_5%~D
D D
C C
B B
A A
4.7K_0402_5%~D
1 2
S
L
P_ME_CSW_DEV#
1
R
R
353
353
H
H
1K_0402_5%~D
1K_0402_5%~D
@
@
2
o
te: PCH has internal pull up 20k ohm on
N
E3_PAID_TS_DET# (GPIO27)
LP_ME_CSW_DEV# PLL ON DIE VR ENABLE
S
ENABLED - HIGH DEFAULT
DISABLED - LOW
+
.3V_ALW_PCH
3
S
IO_EXT_WAKE#
12
177 10K_0402_5%~D
177 10K_0402_5%~D
H
H
1 2
354 1K_ 0402_5%~D
H
H
354 1K_ 0402_5%~D
NTEL feedback 0302
I
2
H
H
174 10K_0402_5%~D
174 10K_0402_5%~D
R
R
R
R
H
H
172 10K_0402_5%~D
172 10K_0402_5%~D
273 1K_0402_5%~D@
H
H
273 1K_0402_5%~D@
R
R
R
R
H
H
265 10K_0402_5%~D@
265 10K_0402_5%~D@
12
1
12
12
1
1
P
P
C
H_GPIO36
1
P
H_GPIO37
C
12
P
H_GPIO17
C
12
P
CH_GPIO16
12
K
_DET#
B
P
H_GPIO36
C
P
H_GPIO37
C
T
EMP_ALERT#
P
H_GPIO22
C
P
C
H_GPIO7
P
H_GPIO17
C
I
O
_LOOP#
P
C
H_GPIO16
5
C
H_GPIO15
+
3.3V_ALW_PCH
R
R
+
3
.3V_RUN
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
170 10K_0402_5%~D
170 10K_0402_5%~D
H
H
2
H
H
171 10K_0402_5%~D@
171 10K_0402_5%~D@
H
H
173 1K_0402_5%~D@
173 1K_0402_5%~D@
H
H
266 10K_0402_5%~D
266 10K_0402_5%~D
2
181 10K_0402_5%~D
181 10K_0402_5%~D
H
H
2
H
H
178 10K_0402_5%~D
178 10K_0402_5%~D
1 2
H
H
269 8.2K_0402_5%~D
269 8.2K_0402_5%~D
1 2
163 10K_0402_5%~D
H
H
163 10K_0402_5%~D
1 2
272 10K_0402_5%~D
H
H
272 10K_0402_5%~D
S
I
O_EXT_SCI#_R<14>
S
I
O_EXT_SCI#<40>
U
SH_DET#<32>
I
_LOOP#<30>
O
S
IO_EXT_WAKE#<39>
P
_LANPHY_ENABLE< 31>
M
P
CH_GPIO15<14>
P
H_GPIO16<14>
C_ENABLE for E4 12"
B
D
L
ayout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
C
P
IE_MCARD1_DET#<34>
C
E
_PAID_TS_DET#<24>
3
S
P_ME_CSW_DEV#<14,39>
L
U
B_MCARD1_DET#<14,34>
S
P
H_GPIO36<14>
C
P
C
H_GPIO37<14>
F
F
T
E
MP_ALERT#<14,39>
K
B_DET#<41>
+
3
.3V_RUN
T
M_ID0
P
S_INT2<27>
1@
1@
10K_0402_5%~D
10K_0402_5%~D
1 2
12
2@
2@
10K_0402_5%~D
10K_0402_5%~D
S
267
H
H
267
R
R
H
H
270
270
R
R
4
I
O_EXT_SCI#
4
1 2
259 0_0402_5%~D@
259 0_0402_5%~D@
H
H
R
R
U
H_DET#
S
I
_LOOP#
O
P
H_GPIO7
C
P
_LANPHY_ENABLE
M
P
H_GPIO15
C
P
H_GPIO16
C
P
C
H_GPIO17
P
C
H_GPIO22
E
_PAID_TS_DET#
3
S
LP_ME_CSW_DEV #
U
B_MCARD1_DET#
S
P
C
H_GPIO36
P
C
H_GPIO37
T
P
M_ID0
T
M_ID1
P
F
F
S_INT2
T
E
MP_ALERT#
K
_DET#
B
V
S
S_NCTF_1
V
S
S_NCTF_2
V
S_NCTF_3
S
V
S
S_NCTF_4
V
S_NCTF_5
S
V
S_NCTF_6
S
V
S_NCTF_7
S
V
S_NCTF_8
S
V
S
S_NCTF_9
V
S_NCTF_10
S
V
S_NCTF_11
S
V
S
S_NCTF_12
V
S_NCTF_13
S
V
S_NCTF_14
S
+
3
T
P
M_ID1
.3V_RUN
12
12
@
@
2.2K_0402_5%~D
2.2K_0402_5%~D
T7
A42
H36
E38
C10
C4
G2
U2
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
R
R
H
H
268
268
20K_0402_5%~D
20K_0402_5%~D
H
H
271
271
R
R
H
H
4F
4F
U
U
BM
BUSY# / GPIO0
CH1 / GPIO1
TA
CH2 / GPIO6
A
T
CH3 / GPIO7
A
T
P
IO8
G
A
N_PHY_PWR_CTRL / GPIO12
L
P
IO15
G
TA4GP / GPIO16
SA
A
CH0 / GPIO17
T
LOCK / GPIO22
C
S
P
IO24
G
IO27
P
G
IO28
P
G
T
P_PCI# / GPIO34
S
IO35
GP
A
TA2GP / GPIO36
S
TA3GP / GPIO37
A
S
L
OAD / GPIO38
S
D
ATAOUT0 / GPIO39
S
D
ATAOUT1 / GPIO48
S
TA5GP / GPIO49 / TEMP_ALERT#
A
S
IO57
P
G
S_NCTF_1
S
V
S_NCTF_2
S
V
S_NCTF_3
S
V
S_NCTF_4
S
V
S_NCTF_5
S
V
S_NCTF_6
S
V
S_NCTF_7
S
V
S_NCTF_8
S
V
S_NCTF_9
S
V
S
S_NCTF_10
V
S_NCTF_11
S
V
S_NCTF_12
S
V
V
S
S_NCTF_13
V
SS_NCTF_14
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
Non-TPM
PM
GPIO
GPIO
CTF
CTF
N
N
3
TA
CH4 / GPIO68
CH5 / GPIO69
TA
CH6 / GPIO70
TA
CH7 / GPIO71
TA
0GATE
A2
OCPWRGD
R
P
H
RMTRIP#
T
N
IT3_3V#
I
D
F
PU/MISC
PU/MISC
C
C
T
S
_VSS1
T
S
_VSS2
T
S
_VSS3
T
S
_VSS4
V
S
S_NCTF_15
V
S
S_NCTF_16
VS
S_NCTF_17
VS
S_NCTF_18
VS
S_NCTF_19
VS
S_NCTF_20
V
S_NCTF_21
S
V
S_NCTF_22
S
V
S_NCTF_23
S
V
S
S_NCTF_24
V
S
S_NCTF_25
V
S
S_NCTF_26
V
S_NCTF_27
S
V
S_NCTF_28
S
V
S_NCTF_29
S
V
SS_NCTF_30
V
S
S_NCTF_31
S
S_NCTF_32
V
1
3
R
P
C
_TVS
N
2
C
O
NTACTLESS_DET#
C
O
NTACTLESS_DET#
C40
P
C
H_GPIO69
B41
P
IE_MCARD3_DET#
C
C41
A40
S
I
O_A20GATE
P4
AU16
E
CI
IN#
_1
C
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
T
P
M_ID1TPM_ID0
S
I
O_RCIN#
H
CPUPWRGD
_
P
H_THRMTRIP#_R
C
I
N
IT3_3V#
D
_TVS
F
N
C
_1
V
S
S_NCTF_15
V
S_NCTF_16
S
V
S
S_NCTF_17
V
S
S_NCTF_18
V
S
S_NCTF_19
V
S
S_NCTF_20
V
S_NCTF_21
S
V
S
S_NCTF_22
V
S
S_NCTF_23
V
S_NCTF_24
S
V
S_NCTF_25
S
V
S_NCTF_26
S
V
S
S_NCTF_27
V
S
S_NCTF_28
V
S_NCTF_29
S
V
SS_NCTF_30
V
S_NCTF_31
S
V
S_NCTF_32
S
C
NTACTLESS_DET# <32>
O
P
C
IE_MCARD3_DET# <34>
U
B_MCARD2_DET# <34>
S
S
I
O_A20GATE <40>
S
I
O_RCIN# <40>
H
CPUPWRGD <7>
_
T
T
06PAD~D
06PAD~D
1
1
@
@
08PAD~D @
1
1
08PAD~D @
T
T
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
1
2
H
_
SNB_IVB#<7>
12
R
R
262 56_0402_5%~D
262 56_0402_5%~D
H
H
H
H
97
97
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
150 0_0402_5%~D@
150 0_0402_5%~D@
H
H
R
R
+
.05V_RUN_VTT
1
1 2
P
H_GPIO69
C
P
L
( TO CPU and NV RAM CONNECTOR)
+
CCDFTERM
V
2
256 10K_0402_5%~D
256 10K_0402_5%~D
H
H
R
R
1 2
R
R
H
H
260 1.5K_0402_1%~D
260 1.5K_0402_1%~D
S
I
O_A20GATE
S
I
O_RCIN#
S
O_EXT_SCI#
I
U
SH_DET#
ACE RH150 CLOSE TO THE BRANCHI NG POINT
1
H
H
149
149
R
R
2.2K_0402_5%~D
2.2K_0402_5%~D
2
D
_TVS_R
F
358 1K_0402_5%~D
H
H
358 1K_0402_5%~D
R
R
D
MI & FDI Termination Voltage
D
F_TVS
1
+
.3V_RUN
3
1
+
3
.3V_RUN
12
158 10K_0402_5%~D
158 10K_0402_5%~D
H
H
R
R
R
R
R
R
R
R
R
1 2
12
203 10K_0402_5%~D
203 10K_0402_5%~D
H
H
1 2
263 10K_0402_5%~D
263 10K_0402_5%~D
H
H
1 2
164 100K_0402_5%~D
164 100K_0402_5%~D
H
H
H
149 need to close to CPU
D
_TVS
F
S
et to Vss when LOW
Set to Vcc when HIGH
10
1T
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
ompal Electronics, Inc.
o
o
mpal Electronics, Inc.
T
T
tle
tle
Title
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
H (5/8)
C
C
C
H (5/8)
H (5/8)
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
8 6
8 61Friday, February 24, 2012
1
8 61Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
5
+
.05V_RUN
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
D D
+
.05V_RUN
1
+
.05V_RUN
1
C C
+
3
.3V_RUN
B B
1
2
@
@
R
R
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
H
H
51
51
1 2
247
247
H
H
2
+
1
.05V_RUN
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
H
H
44
44
2
+
C
C
H
H
30
30
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C
C
H
H
45
45
2
2
+
+
.05V_RUN
1
.05V_RUN_VTT
1
C
C
H
H
32
32
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
H
H
46
46
2
1
.05V_+1.5V_1.8V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
C
C
H
H
H
H
31
31
33
33
2
+
CCAPLLEXP
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
@
@
C
C
H
H
40
40
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
H
H
H
H
48
48
47
47
2
+
CCAPLL_FDI
V
4
U
U
H4G
4G
H
AA23
V
CCORE[1]
C
AC23
V
CCORE[2]
C
AD21
V
CCCORE[3]
AD23
V
C
CCORE[4]
AF21
V
C
CCORE[5]
AF23
V
CCORE[6]
C
AG21
V
CCORE[7]
C
AG23
V
CCORE[8]
C
AG24
V
C
CCORE[9]
AG26
V
C
CCORE[10]
AG27
V
C
CCORE[11]
AG29
V
C
CCORE[12]
AJ23
V
C
CCORE[13]
AJ26
V
CCORE[14]
C
AJ27
V
CCCORE[15]
AJ29
C
CCORE[16]
V
AJ31
C
CCORE[17]
V
AN19
V
C
CIO[28]
BJ22
V
CAPLLEXP
C
AN16
V
CIO[15]
C
AN17
V
C
CIO[16]
AN21
V
CIO[17]
C
AN26
V
CIO[18]
C
AN27
V
C
CIO[19]
AP21
V
CIO[20]
C
AP23
V
CIO[21]
C
AP24
V
C
CIO[22]
AP26
V
C
CIO[23]
AT24
V
C
CIO[24]
AN33
C
CIO[25]
V
AN34
CIO[26]
C
V
BH29
C3_3[3]
C
V
AP16
V
C
CVRM[2]
BG6
V
ccAFDIPLL
AP17
V
C
CIO[27]
AU20
CDMI[2]
C
V
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
P
P
WER
WER
O
O
CC CORE
CC CORE
V
V
VCCIO
VCCIO
FDI
FDI
V
C
V
SSADAC
RTLVDS
RTLVDS
C
C
V
CALVDS
C
V
S
SALVDS
V
C
CTX_LVDS[1]
V
CTX_LVDS[2]
C
V
CTX_LVDS[3]
C
V
CCTX_LVDS[4]
C
V
C
V
VCMOS
VCMOS
H
H
V
C
CVRM[3]
C
CDMI[1]
V
MI
MI
CCLKDMI
C
V
D
D
C
CDFTERM[1]
V
CDFTERM[2]
C
V
V
CCDFTERM[3]
V
CDFTERM[4]
C
DFT / SPI
DFT / SPI
V
CADAC
C3_3[6]
C3_3[7]
CSPI
C
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
3
1
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
C
C
H
H
103
103
2
1
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+
1
+
.05V_RUN_VCCCLKDMI
1
1
50
50
H
H
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
2
+
V
CCSPI
1
54
H
H
54
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1UH_GLFR1608T1R0M-LR_20%~D
CCADAC
V
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C
C
H
H
34
34
H52
H
52
1
2
+
CCDFTERM
V
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
H
H
35
35
1 2
1UH_GLFR1608T1R0M-LR_20%~D
1
2
+
43
43
.05V_+1.5V_1.8V_RUN
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
C
C
H
H
36
36
2
+
.8V_RUN_LVDS
1
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C
C
H
H
104
104
49
H
H49
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
H
H
R
R
@
@
1
C
C
H
H
106
106
2
@
H
H276
@
R
R
0_0805_5%~D
0_0805_5%~D
P
P
JP
JP
@
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
2
H
H
202 0_0603_5%~D@
202 0_0603_5%~D@
R
R
204 0_0603_5%~D@
204 0_0603_5%~D@
H
H
R
R
H
H
1
1
L
L
12
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
2
+
3
.3V_RUN
205 0_0603_5%~D@
205 0_0603_5%~D@
276
12
66
66
1
12
I
NTEL feedback 0307
+
.3V_RUN
3
8
8
H
H
L
100NH_HK1608R10J-T_5%_0603~D
100NH_HK1608R10J-T_5%_0603~D
C
C
H
H
105
105
+
12
L
0
.1uH inductor, 200mA
C
PN: SHI0110BJ0L
.05V_RUN_VTT
1
I
NTEL feedback 0302
+
3
.3V_RUN
+
.8V_RUN
1
+
.3V_M
3
+
.3V_RUN
3
+
1
12
.05V_RUN
2
.3V_RUN
+
1
+3
.8V_RUN
P
C
H Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
V
cADPLLB
c
V
c
cCore
V
cDMI
c
V
o
ltage
1.05
3.3
3
1.05
1.05
1.05
1.1
5
5
.
3
1
S
0 Iccmax
Current (A)
0.001
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
VccASW
V
c
cSPI
V
cDSW3_3 0.001
c
1.05
3
.
3.3
0.903
3
0.01
1.8 0.002VCCDFTERM
3.3VccR TC 2 (mA)
3.3VccS us3_3
3.3VccS usHDA
0.095
0.01
VccVRM 1.5 0.167
1.05VccClkDMI 0.07
1.05VccSSC
VccDIFFCLKN 0.055
1
05
.
VccALVDS 3.3
0.095
0.001
1.8VccT X_LVDS 0.04
+
1
.05V_RUN
+
V
1 2
195 0.022_0805_ 1%@
195 0.022_0805_ 1%@
H
H
R
R
A A
5
CCAPLL_FDI
+
.5V_RUN
1
R
R
4
12
197 0_0603_5%~D@
197 0_0603_5%~D@
H
H
+
1.05V_+1.5V_1.8V_RUN
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
3
2
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
itle
Title
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
H (6/8)
C
C
C
H (6/8)
H (6/8)
L
L
L
-7781
A
A
A
-7781
-7781
1
1
1
9 6
9 6
1
9 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
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