A
B
C
D
E
COMPAL CONFIDENTIAL
QA
1 1
PCB NO :
BOM P/N :
GPIO MAP: E4_VC_GPIO_map_rev_1.1
L
A-7781P (DA60000OP10)
4319EK31L01
MODEL NAME :
L80
2 2
Dalmore 14 UMA
I
y Bridge + Panther POINT
@
v
2012-02-24
REV : 1.0 (A00)
@ : Nopop Component
3 3
CONN@ : Connector Component
MB Type
ATG Non-TPM
BOM P/N
L52
L01TPM
L02Non-TPM
1@
2@
5@ATG TPM L51
5@
1@
2@
4 4
M
M
PCB
B
B
PCB
P
P
art Number
art Number
D
D
A60000OP10
A60000OP10
Description
Description
PCB 0LD LA-7781P REV1 M/B UMA
PCB 0LD LA-7781P REV1 M/B UMA
A
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
C
C
C
ver Sheet
o
o
o
ver Sheet
ver Sheet
L
L
L
-7781
-7781
-7781
A
A
A
E
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
0
.
.
.
A
B
ck Diagram
lo
1 1
On IO board
CRT CONN
VGA
VGA
For MB/DOCK
Video Switch
PI3V713-AZLEX
PAGE 23
HDMI CONN
PAGE 25
DOCKING PORT
PAGE 37
D
2 2
EXPRESS
Card
USB10
3 3
AI
U
SB2.0 [3,6]
S
ATA5
D
O
CK LAN
U
SB3.0 [4]
1/2 Mini Card
PP
PCIE5
1/2 Mini Card
PAGE 33
USB8
Smart Card
LVDS CONN
SDXC/MMC
PCIE2
WLAN
PAGE 33 PAGE 33PAGE 34
PAGE 32
Full Mini Card
WWAN
USB5USB4
TDA8034HN
CPU XDP Port
PCH XDP Port
W
Fi ON/OFF
i
RFID
Fingerprint
CONN
SMSC SIO
D
C
/DC Interface
L
E
4 4
D
Thermal
GUARDIAN III
EMC4021
PWM FAN
PAGE 22
PAGE 22
A
ECE5048
B
PAGE 22
Card Reader
OZ600FJ0
PCI Express BUS
F
B
O
P_USB
BC BUS
PCIE1PCIE3
PAGE 38
VGA
DPB
DPC
D
D
P
LVDS
PAGE 32
100MHz
tion
p
China TCM1.2
SSX44B
PAGE 31
USH
BCM5882
USB7
U
SH Module
SMSC KBC
MEC5055
TP CONN
PAGE 40 PAGE 40
PCIE x1
LPC BUS
33MHz
PAGE 39
KB CONN
Ivy Bridge
rPGA CPU
FDI
Lane x 8
I
TEL
N
P
nther Point-M
a
B
G
A
SPI
W25Q64CVSSIG
64M 4K sector
W25Q32BVSSIG
32M 4K sector
Discrete TPM
AT97SC3204
C
Memory BUS (DDR3)
1333/1600 MHz
PAGE 6-11
D
M
I2
L
a
ne x 4
U
SB
PAGE 14-21
PCI Express BUS
H
D Audio I/F
S
-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PAGE 14
PAGE 14
FFS LNG3DM
P
IE4
C
E-Module
PAGE 27
PAGE 31
C
S
ATA
PI5USB1457A USB
Power Share
100MHz
HDD
PAGE 26
PAGE 26
D
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Touch Screen
BT 4.0
PAGE 22
PAGE 40
Camera
SATA Repeater
PS8513B
PAGE 36
PAGE 35
HDA Codec
9
M
D
C
RJ11
on IO board
D
E
PAGE 12-13
T
ough Cable
r
E-SATA
U
SB3.0
U
SB3.0
on IO board
USB 2.0 Port
USB3.0/2.0
USB3.0/2.0+PS
USB Port
PAGE 36
PAGE 35
PAGE 35
Intel Lewisville
DOCK LAN
INT.Speaker
HD93
2
PAGE 28
Combo Jack
D
I
A
D
i
g.
PAGE 28
T
o
Docking side
MIC
T
ough LVDS Cable
r
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
U
U
U
MA Block Diagram
M
M
A Block Diagram
A Block Diagram
L
L
L
-7781
-7781
A
A
A
-7781
E
2
2
2
82579LM
LAN SWITCH
PAGE 30
PI3L720
RJ45
on IO board
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
PAGE 30
1
1
1
0
0
.
.
.0
5
4
3
2
1
POWER STATES
CH
S
H
USB PORT#
0
1
2
3
4
5
6
7
8
9
1
0
11
1
2
3
1
0
1
JUSB1 (Right side Top)
JUSB2 (Right side Bottom)
J
E
DOCKING
WLAN
WWAN
D
O
U
S
JMINI3(Flash)
J
U
E
x
Bluetooth
Camera
LCD Touch
S
L
P
SLP
S3#
S4#
H
IGH HIGH
HIGH
L
O
W HIGH HIGH ON ON ON OFF
LOW HIGH HIGH
LOW
LOW
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
+PWR_SRC_S
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
O
N
ower
p
plane
Signal
State
S
(Full ON) / M0
0
D D
S3 (Suspend to RAM) / M3
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S
3
(Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
P
TABLE
M
C C
State
S
0
S
3
S
L
SLP
S5#
H
+
3
+1.5V_MEM
P
A#
HIGH
HIGH
GH
I
.3V_SUS
ON ON
ON
ALWAYS
PLANE
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
ON
M
PLANE
ON
OFFON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
+
+
3.3V_M
1
.05V_M
ON
ON
+
3
+1.05V_M
(M-OFF)
ON
OFF
CLOCKS
OFF
OFF
O
FF
.3V_M
S
A
TA
SATA 0
ATA 1
S
SATA 2
SATA 3
S
A
TA 4
SATA 5
D
E
STINATION
HDD
O
DD/ E3 Module Bay
N
A
N
A
E
S
ATA
Dock
P
U
DESTINATION
SA1 (Right side ESATA)
CKING
H->BIO
SB (Left side)
press card
B
O
I
NA
S5 S4/AC
S
5
S4/AC don't exist
B B
A A
5
ON
OFF
OFFOFF
OFF
OFF
ON
OFF
OFFOFF
need to update Power Status and PM
Table
4
P
C
U
A DP/HDMI Port
M
Port B
Port C
P
o
rt D
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Connetion
MB HDMI Conn
Dock DP port 2
Dock DP port 1
2
I EXPRESS
Lane 1
L
ane 2
Lane 3
Lane 4
L
ne 5
a
Lane 6
L
ne 7
a
MINI CARD-1 WWAN
M
Express card
E
1
MMI
10/100/1G LOM
Lane 8 None
D
ELL CONFIDENTIAL/PROPRIETARY
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
D
STINATION
E
NI CARD-2 WLAN
I
3 Module Bay (USB3)
/2vMINI CARD-3 PCIE
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
I
I
I
ndex and Config.
n
n
dex and Config.
dex and Config.
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
1
0
0
.
.
3
3
3
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
E
N_INVPWR
D D
4
F
D
C654P
(
21)
Q
+
B
L_PWR_SRC
3
2
DC_EN
O
O_SLP_S3#
I
S
M
1
ADAPTER
S
I3456BDVSI3456BDV
+
V_MOD
5
(Q30)(Q27)
S
I
(Q42)
ARD_MISC_PWREN
C
M
3456
S
I
(Q40)
ARD_WWAN_PWREN
C
M
3456
B
A
TTERY
+PWR_SRC
1
.
05V_0.8V_PWROK
I
SL95836
(PU700)
+
CC_GFXCORE
V
+
5
V_HDD
A
LWON
IO_SLP_A#
S
S
I
3456
(
58)
Q
+3.3V_M
+
.3V_WWAN
3
+
O_SLP_S3#
I
S
+
5
3.3V_FLASH
V_RUN
C C
B B
A A
I
L95836
S
(
PU700)
05V_0.8V_PWROK
.
1
+
CC_CORE
V
C
H
ARGER
T
P
S51212
T
(PU500)
U_VTT_ON
P
C
+
1
.05V_RUN_VTT +1.05V_M
S
O_SLP_S3#
I
S
I
4164
(Q63)
S51212
P
(PU400)
O_SLP_A#
I
S
P
op option
S
O_SLP_S3#
I
A
O
4728
(QC3)
R
T
8207
(
P
U200)
R_ON
D
D
+
1
.5V_MEM
S
O_SLP_S3#
I
NTGS4141N
(
59)
Q
IO_SLP_S3#
S
S
8033
Y
(
P
U300)
+
1
0.75V_DDR_VTT_ON
.8V_RUN
T
P
(
P
+
V
05V_VTTPWRGD
.
1
S51461
U600)
CC_SA
S
I
(Q38)
+
3
.3V_WLAN
X_EN_WOWL
U
A
3456
H_ALW_ON
C
P
S
I
3456
(Q49)
+
.3V_ALW_PCH
3
RT8205
(
PU100)
+
3
.3V_ALW
S
1
3456
(Q54)
+
3
.3V_SUS
S_ON
U
S
+
3.3V_M
+
V_ALW
5
O_SLP_LAN#
I
S
S
I3456
(Q34) (U78)
+
3
.3V_LAN
P
p option
o
+
.3V_RUN
3
O_SLP_S3#
I
S
TPS22966
+
.05V_RUN
1
5
+
1.0V_LAN
+
1
.5V_RUN+1.5V_CPU_VDDQ
4
+
0
.75V_DDR_VTT
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
ower Rail
o
o
wer Rail
wer Rail
L
L
L
-7781
-7781
A
A
A
-7781
4
4
4
1
o
o
o
f
f
f
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
5
S
MBUS Address [0x9a]
B
4
A3
B5
A4
A56
MEM_SMBCLK
M
M_SMBDATA
E
L
N_SMBCLK
A
LAN_SMBDATA
2.2K
2
2K
.
D
O
CK_SMB_CLK
D
O
CK_SMB_DAT
L
CD_SMBCLK
LCD_SMDATA
P
B
AT_SMBCLK
PBAT_SMBDAT
+
3.3V_ALW_PCH
H14
C
9
P
H
D D
C C
C
C
8
G12
E
14M16
S
M
L1_SMBDATA
S
ML1_SMBCLK
B
6A5
3
A
3A
1A
1A
1B
1B
K
BC
1C1CB59
2.
2.2K
2
.
2.2K
2K
2K
2
2
2
2.2K
2
.
.2K
.
2
2
.
4
2K
2K
2K
.
2K
.
2K
+3.3V_ALW_PCH
+
3.3V_LAN
2
8
3
1
LOM
+
3.3V_ALW
+
3.3V_ALW
+
3.3V_ALW
1
0 ohm
0
1
0
0 ohm
2N7002
2
7002
N
S
BUS Address [C8]
M
127
1
29
7
6
D
OCKING
BATTERY
CONN
3
S
MBUS Address
A
R_EC: 0x48
P
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
S
MBUS Address [0x16]
2
2
202
2
2
02
00
0
0
5
3
5
1
5
3
5
1
30
3
2
D
IMMA
D
IMMB
XDP1
XDP2
1
0
K
1
K
0
4
G
6
SMBUS Address [A0]
SMBUS Address [A4]
S
MBUS Address [TBD]
SMBUS Address [TBD]
+
3.3V_RUN
Sensor
W
AN
W
S
M
BUS Address [3B]
SMBUS Address [TBD]
1
+
A
2.2K
50
U
B53
A
9
4
B52
B50
A47
B
7
A7
SH_SMBCLK
U
S
H_SMBDAT
CARD_SMBCLK
CARD_SMBDAT
C
HARGER_SMBCLK
CHARGER_SMBDAT
BAY_SMBDAT
BAY_SMBCLK
2
.
2K
2
2K
.
2
.2K
2
.
2K
2
.
2K
2
.
2K
4
1E
B B
M
E
C 5065
A A
1E
2B
2B
1G
1G
2
D
2
D
5
3.3V_ALW
+
3.3V_SUS
+
3.3V_ALW
+
3.3V_ALW
M
9
9
L
U
S
H
S
M
BUS Address [0xa4]
7
8
Express card
9
8
C
h
arger
SMBUS Address [0x12]
S
BUS Address [TBD]
M
2
9
E
3 Module Bay
3
0
3
S
M
BUS Address [0xd2]
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
mpal Electronics, Inc.
S
S
S
MBUS TOPOLOGY
M
M
BUS TOPOLOGY
BUS TOPOLOGY
L
L
L
-7781
-7781
A
A
A
-7781
5
5
5
1
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
4
3
2
1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
+
.05V_RUN_VTT
1
12
C
C
2
2
R
R
24.9_0402_1%~D
D D
DM
D
M
I_CRX_PTX_N0<16>
D
M
I_CRX_PTX_N1<16>
D
M
I_CRX_PTX_N2<16>
D
M
I_CRX_PTX_N3<16>
D
I_CRX_PTX_P0<16>
M
D
I_CRX_PTX_P1<16>
M
D
M
I_CRX_PTX_P2<16>
D
MI_CRX_PTX_P3<16>
D
M
I_CTX_PRX_N0<16>
D
I_CTX_PRX_N1<16>
M
D
I_CTX_PRX_N2<16>
M
D
I_CTX_PRX_N3<16>
M
D
M
I_CTX_PRX_P0<16>
D
M
I_CTX_PRX_P1<16>
D
M
I_CTX_PRX_P2<16>
D
I_CTX_PRX_P3<16>
M
F
D
I_CTX_PRX_N0<16>
F
D
I_CTX_PRX_N1<16>
F
I_CTX_PRX_N2<16>
D
F
I_CTX_PRX_N3<16>
D
F
D
C C
B B
I_CTX_PRX_N4<16>
F
D
I_CTX_PRX_N5<16>
F
I_CTX_PRX_N6<16>
D
F
I_CTX_PRX_N7<16>
D
F
D
I_CTX_PRX_P0<16>
F
D
I_CTX_PRX_P1<16>
F
I_CTX_PRX_P2<16>
D
F
D
I_CTX_PRX_P3<16>
F
DI_CTX_PRX_P4<16>
F
D
I_CTX_PRX_P5<16>
F
I_CTX_PRX_P6<16>
D
F
I_CTX_PRX_P7<16>
D
F
D
I_FSYNC0<16>
F
I_FSYNC1<16>
D
F
D
I_INT<16>
F
I_LSYNC0<16>
D
F
D
I_LSYNC1<16>
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
I_CRX_PTX_N0
D
M
I_CRX_PTX_N1
D
I_CRX_PTX_N2
M
D
MI_CRX_PTX_N3
D
M
I_CRX_PTX_P0
D
I_CRX_PTX_P1
M
D
I_CRX_PTX_P2
M
D
M
I_CRX_PTX_P3
D
MI_CTX_PRX_N0
D
I_CTX_PRX_N1
M
D
I_CTX_PRX_N2
M
D
I_CTX_PRX_N3
M
D
I_CTX_PRX_P0
M
D
M
I_CTX_PRX_P1
D
M
I_CTX_PRX_P2
D
I_CTX_PRX_P3
M
F
I_CTX_PRX_N0
D
F
I_CTX_PRX_N1
D
F
I_CTX_PRX_N2
D
F
I_CTX_PRX_N3
D
F
I_CTX_PRX_N4
D
F
D
I_CTX_PRX_N5
F
I_CTX_PRX_N6
D
F
D
I_CTX_PRX_N7
F
I_CTX_PRX_P0
D
F
I_CTX_PRX_P1
D
F
I_CTX_PRX_P2
D
F
I_CTX_PRX_P3
D
F
D
I_CTX_PRX_P4
F
D
I_CTX_PRX_P5
F
D
I_CTX_PRX_P6
F
I_CTX_PRX_P7
D
F
I_FSYNC0
D
F
DI_FSYNC1
F
I_INT
D
F
I_LSYNC0
D
F
I_LSYNC1
D
E
P_COMP
D
PU1A
PU1A
C
C
J
J
B27
M
I_RX#[0]
D
B25
M
I_RX#[1]
D
A25
M
I_RX#[2]
D
B24
M
I_RX#[3]
D
B28
I_RX[0]
M
D
B26
I_RX[1]
M
D
A24
I_RX[2]
M
D
B23
I_RX[3]
M
D
G21
I_TX#[0]
M
D
E22
I_TX#[1]
M
D
F21
I_TX#[2]
M
D
D21
I_TX#[3]
M
D
G22
I_TX[0]
M
D
D22
I_TX[1]
M
D
F20
I_TX[2]
M
D
C21
I_TX[3]
M
D
A21
D
I0_TX#[0]
F
H19
D
I0_TX#[1]
F
E19
D
I0_TX#[2]
F
F18
D
I0_TX#[3]
F
B21
I1_TX#[0]
D
F
C20
I1_TX#[1]
D
F
D18
D
I1_TX#[2]
F
E17
I1_TX#[3]
D
F
A22
D
I0_TX[0]
F
G19
D
I0_TX[1]
F
E20
I0_TX[2]
D
F
G18
I0_TX[3]
D
F
B20
I1_TX[0]
D
F
C19
I1_TX[1]
D
F
D19
I1_TX[2]
D
F
F17
I1_TX[3]
D
F
J18
DI0_FSYNC
F
J17
I1_FSYNC
D
F
H20
I_INT
D
F
J19
D
I0_LSYNC
F
H17
D
I1_LSYNC
F
A18
e
D
P_COMPIO
A17
e
D
P_ICOMPO
B16
e
D
P_HPD#
C15
e
D
P_AUX
D15
e
P_AUX#
D
C17
e
P_TX[0]
D
F16
e
P_TX[1]
D
C16
e
P_TX[2]
D
G15
e
P_TX[3]
D
C18
e
P_TX#[0]
D
E16
e
D
P_TX#[1]
D16
e
D
P_TX#[2]
F15
e
D
P_TX#[3]
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
G_ICOMPI
G_ICOMPO
G_RCOMPO
G_RX#[0]
PE
G_RX#[1]
PE
E
G_RX#[2]
P
G_RX#[3]
PE
G_RX#[4]
PE
G_RX#[5]
PE
G_RX#[6]
PE
G_RX#[7]
PE
G_RX#[8]
PE
G_RX#[9]
PE
G_RX#[10]
G_RX#[11]
G_RX#[12]
G_RX#[13]
G_RX#[14]
G_RX#[15]
PE
G_RX[0]
PE
G_RX[1]
PE
G_RX[2]
PE
G_RX[3]
PE
G_RX[4]
P
G_RX[5]
E
P
G_RX[6]
E
P
G_RX[7]
E
P
G_RX[8]
E
P
G_RX[9]
E
P
G_RX[10]
E
P
E
G_RX[11]
P
E
G_RX[12]
P
E
G_RX[13]
P
G_RX[14]
E
P
G_RX[15]
E
P
G_TX#[0]
E
P
G_TX#[1]
E
P
G_TX#[2]
E
P
G_TX#[3]
E
P
E
G_TX#[4]
P
E
G_TX#[5]
P
E
G_TX#[6]
P
G_TX#[7]
E
P
G_TX#[8]
E
P
G_TX#[9]
E
P
E
G_TX#[10]
P
E
G_TX#[11]
P
E
G_TX#[12]
P
G_TX#[13]
E
P
G_TX#[14]
E
P
G_TX#[15]
E
P
E
G_TX[0]
P
E
G_TX[1]
P
G_TX[2]
E
P
G_TX[3]
E
P
G_TX[4]
E
P
G_TX[5]
E
P
E
G_TX[6]
P
E
G_TX[7]
P
E
G_TX[8]
P
G_TX[9]
E
P
G_TX[10]
E
P
E
G_TX[11]
P
E
G_TX[12]
P
E
G_TX[13]
P
G_TX[14]
E
P
E
G_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PE
PE
PE
DMI
DMI
ntel(R) FDI
ntel(R) FDI
I
I
DP
DP
e
e
PE
PE
PE
PE
PE
PE
CI EXPRESS* - GRAPHICS
CI EXPRESS* - GRAPHICS
P
P
24.9_0402_1%~D
P
E
G_COMP
P
G Compensation
E
P
EG_ICOMPI and R COMPO signals s hould be shorte d and routed
with - max leng th = 500 mils - typical impeda nce = 43 mohms
PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils
- typical imped ance = 14.5 moh ms
J
J
PU1I
PU1I
C
C
T35
V
S
S161
T34
V
S
S162
T33
V
S163
S
T32
V
S164
S
T31
V
SS165
T30
V
S
S166
T29
V
S
S167
T28
V
S168
S
T27
V
S169
S
T26
V
S
S170
P9
V
S
S171
P8
V
S
S172
P6
V
S
S173
P5
V
S
S174
P3
V
S175
S
P2
V
S176
S
N35
V
SS177
N34
V
S
S178
N33
V
S179
S
N32
V
S180
S
N31
V
S
S181
N30
V
S
S182
N29
V
S183
S
N28
V
S184
S
N27
V
S185
S
N26
V
S
S186
M34
V
S187
S
L33
V
S188
S
L30
V
SS189
L27
V
S
S190
L9
V
S191
S
L8
V
S192
S
L6
V
S
S193
L5
V
S194
S
L4
V
S195
S
L3
V
S
S196
L2
V
S
S197
L1
V
S198
S
K35
V
SS199
K32
V
S
S200
K29
V
S
S201
K26
S202
S
V
J34
S
S203
V
J31
S
S204
V
H33
S
S205
V
H30
S206
S
V
H27
SS207
V
H24
S208
S
V
H21
S
S209
V
H18
S
S210
V
H15
S
S211
V
H13
S
S212
V
H10
S
S213
V
H9
S
S214
V
H8
S215
S
V
H7
S216
S
V
H6
S217
S
V
H5
S218
S
V
H4
S219
S
V
H3
S
S220
V
H2
S
S221
V
H1
S
S222
V
G35
S
S223
V
G32
S224
S
V
G29
S
S225
V
G26
SS226
V
G23
S227
S
V
G20
S228
S
V
G17
S229
S
V
G11
S230
S
V
F34
S231
S
V
F31
S232
S
V
F29
S
S233
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
F22
S234
S
V
F19
S235
S
V
E30
S
S236
V
E27
S
S237
V
E24
S
S238
V
E21
S239
S
V
E18
S240
S
V
E15
S241
S
V
E13
S242
S
V
E10
S
S243
V
E9
S
S244
V
E8
S
S245
V
E7
S246
S
V
E6
S
S247
V
E5
S
S248
V
E4
S
S249
V
E3
SS250
V
E2
S251
S
V
E1
S252
S
V
D35
S253
S
V
D32
S254
S
V
D29
S255
S
V
D26
S
S256
V
D20
S
S257
V
D17
S
S258
V
C34
S
S259
V
C31
S
S260
V
C28
S
S261
V
C27
S262
S
V
C25
S263
S
V
C23
S264
S
V
C10
S265
S
V
C1
S266
S
V
B22
S267
S
V
B19
S268
S
V
V
V
SS
S
S
B17
S269
S
V
B15
S270
S
V
B13
S
S271
V
B11
S272
S
V
B9
S
S273
V
B8
S
S274
V
B7
S
S275
V
B5
S
S276
V
B3
S
S277
V
B2
S
S278
V
A35
S
S279
V
A32
S
S280
V
A29
S
S281
V
A26
S
S282
V
A23
S
S283
V
A20
S
S284
V
A3
S
S285
V
D
Compensation
P
+
.05V_RUN_VTT
1
12
R
R
C1
C1
24.9_0402_1%~D
A A
e
D
P_COMPIO and IC OMPO signals sh ould be shorted near
balls and route d with typical impedance <25 m ohms
5
24.9_0402_1%~D
E
DP_COMP
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
tle
i
i
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
I
I
I
y Bridge (1/6)
v
v
v
y Bridge (1/6)
y Bridge (1/6)
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
1
.
0
0
0
.
6
6
6
.
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
llow DG Rev0.71 SM_DRAMPWROK topology
Fo
+
3
.3V_ALW_PCH
C
C
156 0.1U_0402_25V6K~D
156 0.1U_0402_25V6K~D
C
C
1 2
5
U
U
C
C
2
2
1
U
NPWROK<39,40>
R
+
.3V_ALW_PCH
3
D D
+
.05V_RUN_VTT
1
C C
B B
ffered reset to CPU
u
B
A A
P
1 2
R
R
18 200_0402_1%~D
18 200_0402_1%~D
C
C
M
P
2
1
C
C
126 56_0402_5%~D@
126 56_0402_5%~D@
R
R
1 2
R
R
128 49.9_0402_1%~D@
128 49.9_0402_1%~D@
C
C
1 2
44 62_0402_5%~D
44 62_0402_5%~D
C
C
R
R
ollow check list 0.5
F
PROCHOT#<40,51,52>
_
H
_
THERMTRIP#<22>
H
_
CPUPWRGD<18>
H
C
H_PLTRST#<14,17>
_DRAM_PWRGD<16>
H
_THERMTRIP#
H
_
CATERR#
H
PROCHOT#
_
SNB_IVB#<18>
_
H
P
U_DETECT#<39>
C
CI_EC<40>
E
P
R1 TOPOLOGY
V
1 2
R
R
C
C
57 56_0402_5%~D
57 56_0402_5%~D
1 2
R
R
129 0_0402_5%~D@
129 0_0402_5%~D@
C
C
_
PM_SYNC<16>
H
1 2
R
R
C
C
25 0_0402_5%~D@
25 0_0402_5%~D@
5
1
2
3
P
B
2
A
N_ON_CPU1.5VS3#<11,42>
U
R
H
_CATERR#
H
_PROCHOT#_R
C
H
_THERMTRIP#_R
H
PM_SYNC
_
V
C
P
M
P
C
H_PLTRST#_R
U
U
1
C
C
1
V
N
C
C
C
A
G
Y
D
N
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
pen drain buffer
O
R
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
ose to JCBU1
l
CPWRGOOD_0_R
_DRAM_PWRGD_CP U
+
3
.3V_RUN
1
2
5
P
H_PLTRST#_BUF
C
4
NPWROK_AND
U
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+
.5V_CPU_VDDQ
1
RC
64
39_0402_5%~D
39_0402_5%~D
1 2
13
D
D
Q
Q
C
2
G
G
NTEL suggest RC64 and QC1 NO stuff by default
I
J
J
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
+
1
.05V_RUN_VTT
C
C
C
C
140
140
C
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
C
C
PU1B
PU1B
R
OC_SELECT#
P
K
TOCC#
S
TERR#
A
C
E
CI
P
OCHOT#
R
P
ERMTRIP#
H
T
_SYNC
M
P
COREPWRGOOD
N
U
M
_DRAMPWROK
S
SET#
E
R
75_0402_1%~D
75_0402_1%~D
R
R
12
C
C
4
4
1 2
R
R
C10 43_0402_5%~D
C10 43_0402_5%~D
4
12
RC
RC
12
12
200_0402_1%~D
200_0402_1%~D
1 2
28 130_0402_1%~D
28 130_0402_1%~D
C
C
R
R
@RC64
@
1
@
1
@
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
P
C
H_PLTRST#_R
4
P
_DRAM_PWRGD_CP U
M
P
D
P
LL_REF_CLK#
D
LOCKS
LOCKS
C
C
M
S
S
S
S
DR3
DR3
D
D
MISC
MISC
TAG & BPM
TAG & BPM
J
J
C
B
C
B
LL_REF_CLK
_DRAMRST#
M
_RCOMP[0]
_RCOMP[1]
M
_RCOMP[2]
M
DY#
R
P
EQ#
R
P
T
T
R
ST#
T
T
B
D
P
M#[0]
B
P
M#[1]
B
M#[2]
P
B
M#[3]
P
B
M#[4]
P
B
M#[5]
P
B
M#[6]
P
B
P
M#[7]
B
3
+
.3V_ALW_PCH
3
1
124
@RC124
@
RC
1K_0402_5%~D
1K_0402_5%~D
2
S
S_PWROK_XDP
Y
e resistor for HOOK2 should be placed
h
T
such that the s tub is very sma ll on CFG0 net
H
_
CPUPWRGD
S
O_PWRBTN#_R<14,16>
I
C
FG0_R
S_PWROK<16,39>
Y
S
R_XDP_WAN_SM BDAT<12,13,14,15,27,34>
D
D
R_XDP_WAN_SM BCLK<12,13,14,15,27,34>
D
D
C
P
LK
LK#
C
M
D
T
D
R#
C
U_DMI#
P
A27
C
P
U_DPLL
A16
C
P
U_DPLL#
A15
emove DPLL Ref clock (for eDP only)
R
D
R3_DRAMRST#_CPU
D
R8
S
M_RCOMP0
AK1
S
_RCOMP1
M
A5
S
_RCOMP2
M
A4
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
X
P_PRDY#
D
AP29
X
D
P_PREQ#
AP27
X
P_TCLK
D
AR26
K
X
D
P_TMS
AR27
S
X
P_TRST#
D
AP30
X
P_TDI_R
D
AR28
I
X
P_TDO_R
D
AP26
O
X
P_DBRESET#_R
D
AL35
X
D
P_OBS0_R
AT28
X
D
P_OBS1_R
AR29
X
D
P_OBS2_R
AR30
X
DP_OBS3_R
AT30
X
P_OBS4_R
D
AP32
X
P_OBS5_R
D
AR31
X
P_OBS6_R
D
AT31
X
D
P_OBS7_R
AR32
or ESD concern, please put near CPU
F
V
void stub in th e PWRGD path
A
while placing r esistors RC25 & RC130
U_DMI
A28
1 2
13 0_0402_5%~D@
13 0_0402_5%~D@
C
C
R
R
1 2
C
C
15 0_0402_5%~D@
15 0_0402_5%~D@
R
R
1 2
R
R
16 1K_0402_5%~D
16 1K_0402_5%~D
C
C
1 2
C
C
17 1K_0402_5%~D
17 1K_0402_5%~D
R
R
a
x 500mils
M
1 2
R
R
27 0_0402_5%~D@
E
E27 0_0402_5%~D@
1 2
28 0_0402_5%~D@
28 0_0402_5%~D@
E
E
R
R
1 2
R
R
29 0_0402_5%~D@
E
E
29 0_0402_5%~D@
1 2
30 0_0402_5%~D@
E
E
30 0_0402_5%~D@
R
R
1 2
E31 0_0402_5%~D@RE31 0_0402_5%~D@
R
1 2
32 0_0402_5%~D@
32 0_0402_5%~D@
E
E
R
R
2
26 0_0402_5%~D@
26 0_0402_5%~D@
1 2
30 0_0402_5%~D@
30 0_0402_5%~D@
1 2
31 0_0402_5%~D@
31 0_0402_5%~D@
1 2
33 0_0402_5%~D@
33 0_0402_5%~D@
1 2
34 0_0402_5%~D@
34 0_0402_5%~D@
1 2
36 0_0402_5%~D@
36 0_0402_5%~D@
1 2
37 0_0402_5%~D@
37 0_0402_5%~D@
1 2
38 0_0402_5%~D@
38 0_0402_5%~D@
1 2
39 0_0402_5%~D@
39 0_0402_5%~D@
12
3
1
C
C
130
130
R
R
10K_0402_5%~D
10K_0402_5%~D
R
R
C
C
C
C
R
R
R
R
C
C
R
R
C
C
R
R
C
C
C
C
R
R
C
C
R
R
C
C
R
R
R
R
C
C
CPWRGOOD_0_R
C
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
R
R
C
C
R
R
C
C
R
R
C
C
C
C
R
R
R
R
125 0_0402_5%~D@
125 0_0402_5%~D@
C
C
127 0_0402_5%~D@
127 0_0402_5%~D@
C
C
R
R
L
K_CPU_DMI <15>
C
K_CPU_DMI# <15>
L
C
C
C
R
R
4.99K_0402_1%~D
4.99K_0402_1%~D
X
P_PREQ#_R
D
X
P_TCLK_R
D
X
D
P_TMS_R
X
D
P_TRST#_R
X
P_TDI
D
X
D
P_TDO
X
P_DBRESET#
D
X
D
P_OBS0
X
P_OBS1
D
X
P_OBS2
D
X
DP_OBS3
X
P_OBS4
D
X
D
P_OBS5
X
P_OBS6
D
X
P_OBS7
D
+1
.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
ace near JXDP1
l
P
1 2
5 1K_0402_5%~D@
5 1K_0402_5%~D@
1 2
6 0_0402_5%~D@
6 0_0402_5%~D@
1 2
7 1K_0402_5%~D@
7 1K_0402_5%~D@
1 2
9 0_0402_5%~D@
9 0_0402_5%~D@
1 2
1 2
+
1
.05V_RUN_VTT
1
50
50
2
S
_RCOMP2
M
S
_RCOMP1
M
S
M
_RCOMP0
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
C
C
C
C
C
C
66
66
65
65
2
F
G10<9>
C
G11<9>
F
C
1 2
48 0_0402_5%~D@
C
RC
48 0_0402_5%~D@
R
S
S
G
G
2
1
2
D
R_HVREF_RST_PCH<15>
D
R_HVREF_RST_GATE<40>
D
D
X
D
P_DBRESET# <14,16>
2
X
D
P_PREQ#_R
X
D
P_PRDY#
X
P_OBS0
D
X
P_OBS1
D
X
DP_OBS2
X
D
P_OBS3
C
F
G10
C
F
G11
X
D
P_OBS4
X
D
P_OBS5
X
P_OBS6
D
X
P_OBS7
D
H
CPUPWRGD_XDP
_
C
D_PWRBTN#_XDP
F
X
D
P_HOOK2
S
Y
S_PWROK_XDP
D
D
R_XDP_SMBDAT_R1
D
R_XDP_SMBCLK_R1
D
X
D
P_TCLK_R
D
D
13
Q
Q
C
C
2
2
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
D
R_HVREF_RST
D
C
C
177
C
C
177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
46 0_0402_5%~D@RC46 0_0402_5%~D@
RC
47 0_0402_5%~D@
C
C
47 0_0402_5%~D@
R
R
12
12
42
43
45
42
C
C
R
R
140_0402_1%~D
140_0402_1%~D
45
43
C
C
RC
RC
R
R
25.5_0402_1%~D
25.5_0402_1%~D
2
+
.05V_RUN_VTT
1
R3_DRAMRST# <12>
D
D
1 2
1 2
12
200_0402_1%~D
200_0402_1%~D
J
J
DP1
DP1
X
X
1
G
D0
N
3
O
B
SFN_A0
5
O
B
SFN_A1
7
G
D2
N
9
O
SDATA_A0
B
11
O
B
SDATA_A1
13
G
N
D4
15
O
SDATA_A2
B
17
O
SDATA_A3
B
19
G
N
D6
21
O
B
SFN_B0
23
O
B
SFN_B1
25
D8
N
G
27
SDATA_B0
B
O
29
B
SDATA_B1
O
31
N
D10
G
33
B
SDATA_B2
O
35
SDATA_B3
B
O
37
D12
N
G
39
W
RGOOD/HOOK0
P
41
O
OK1
H
43
C
C_OBS_AB
V
45
O
OK2
H
47
OK3
O
H
49
D14
N
G
51
A
D
S
53
C
L
S
55
C
K1
T
57
C
K0
T
59
D16
N
G
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
X
P_RST#_R
D
C
K_XDP
L
H
H
107 0_0402_5%~D@
107 0_0402_5%~D@
R
R
C
L
K_XDP#
106 0_0402_5%~D@
106 0_0402_5%~D@
H
H
R
R
L
K_XDP_ITP<9>
C
K_XDP_ITP#<9>
L
C
D
tle
Title
i
i
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
+
.05V_RUN_VTT
1
2
N
D1
G
B
SFN_C0
O
SFN_C1
B
O
D3
N
G
SDATA_C0
B
O
B
SDATA_C1
O
N
D5
G
B
SDATA_C2
O
SDATA_C3
B
O
D7
N
G
SFN_D0
B
O
B
SFN_D1
O
D9
N
G
SDATA_D0
B
O
SDATA_D1
B
O
N
D11
G
B
SDATA_D2
O
B
SDATA_D3
O
N
D13
G
PCLK/HOOK4
T
I
PCLK#/HOOK5
T
I
C_OBS_CD
C
V
SET#/HOOK6
E
R
R#/HOOK7
B
D
N
D15
G
D
0
T
R
ST#
T
D
I
T
S
M
T
D17
N
G
1 2
R
R
8 1K_0402_5%~DPXDP@
8 1K_0402_5%~DPXDP@
C
C
1 2
1 2
R
R
R
R
D
R_HVREF_RST <12>
D
3 control
M
/PD for JTAG signals
U
P
X
P_DBRESET#
D
X
P_TMS
D
X
D
P_TDI_R
X
P_PREQ#
D
X
D
P_TDO_R
X
D
P_TCLK
X
D
P_TRST#
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
C
G16
F
4
C
G17
F
6
8
CF
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1 2
109 0_0402_5%~D@
109 0_0402_5%~D@
H
H
1 2
H
H
108 0_0402_5%~D@
108 0_0402_5%~D@
o
o
o
v
v
v
I
I
I
L
L
L
G0_R
C
G1_R
F
C
G2
F
C
G3
F
C
F
G8
C
F
G9
C
G4
F
C
G5_R
F
C
G6
F
C
G7
F
C
K_XDP
L
C
K_XDP#
L
X
DP_RST#_R
X
P_DBRESET#
D
X
P_TDO
D
X
P_TRST#_R
D
X
P_TDI
D
X
P_TMS_R
D
19 1K_0402_5%~D
19 1K_0402_5%~D
C
C
R
R
C
C
R
R
C
C
R
R
C
C
R
R
C
C
R
R
R
R
C
C
R
R
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
y Bridge (1/6)
y Bridge (1/6)
y Bridge (1/6)
-7781
A
A
A
-7781
-7781
12
27 51_0402_1%~D
27 51_0402_1%~D
12
29 51_0402_1%~D
29 51_0402_1%~D
12
32 51_0402_1%~D@
32 51_0402_1%~D@
12
35 51_0402_1%~D
35 51_0402_1%~D
12
40
40
12
51_0402_1%~D
1
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
41
41
F
G16 <9>
C
F
G17 <9>
C
C
G0_R <9>
F
G1_R <9>
F
C
C
F
G2 <9>
C
G3 <9>
F
F
G8 <9>
C
G9 <9>
F
C
C
G4 <9>
F
C
G5_R <9>
F
C
F
G6 <9>
G7 <9>
F
C
TRST_XDP# <17>
L
P
K_CPU_ITP <15>
L
C
K_CPU_ITP# <15>
L
C
+
3
+
.05V_RUN_VTT
1
7
7
7
o
o
o
.3V_RUN
f
f
f
0
.
.
.
0
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
5
JC
JC
PU1C
PU1C
D D
C C
B B
R_A_D[0..63]<12>
D
D
D
R_A_BS0<12>
D
D
R_A_BS1<12>
D
DR_A_BS2<12>
D
D
R_A_CAS#<12>
D
D
R_A_RAS#<12>
D
DR_A_WE#<12>
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DR_A_D6
D
D
D
D
D
D
D
D
D
D
D
DR_A_D12
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DR_A_D38
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
R_A_BS0
D
D
R_A_BS1
D
D
D
R_A_BS2
D
D
R_A_CAS#
D
R_A_RAS#
D
D
R_A_WE#
D
R_A_D0
R_A_D1
R_A_D2
R_A_D3
R_A_D4
R_A_D5
R_A_D7
R_A_D8
R_A_D9
R_A_D10
R_A_D11
R_A_D13
R_A_D14
R_A_D15
R_A_D16
R_A_D17
R_A_D18
R_A_D19
R_A_D20
R_A_D21
R_A_D22
R_A_D23
R_A_D24
R_A_D25
R_A_D26
R_A_D27
R_A_D28
R_A_D29
R_A_D30
R_A_D31
R_A_D32
R_A_D33
R_A_D34
R_A_D35
R_A_D36
R_A_D37
R_A_D39
R_A_D40
R_A_D41
R_A_D42
R_A_D43
R_A_D44
R_A_D45
R_A_D46
R_A_D47
R_A_D48
R_A_D49
R_A_D50
R_A_D51
R_A_D52
R_A_D53
R_A_D54
R_A_D55
R_A_D56
R_A_D57
R_A_D58
R_A_D59
R_A_D60
R_A_D61
R_A_D62
R_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AE8
AD9
AF9
C5
S
_DQ[0]
A
D5
S
A
_DQ[1]
D3
S
_DQ[2]
A
D2
S
_DQ[3]
A
D6
S
_DQ[4]
A
C6
S
_DQ[5]
A
C2
S
A
_DQ[6]
C3
S
A
_DQ[7]
F10
S
A
_DQ[8]
F8
S
_DQ[9]
A
S
_DQ[10]
A
G9
S
_DQ[11]
A
F9
S
_DQ[12]
A
F7
S
A
_DQ[13]
G8
S
A
_DQ[14]
G7
S
A
_DQ[15]
K4
S
A
_DQ[16]
K5
S
_DQ[17]
A
K1
S
_DQ[18]
A
J1
S
_DQ[19]
A
J5
S
A
_DQ[20]
J4
S
A
_DQ[21]
J2
S
A
_DQ[22]
K2
S
A
_DQ[23]
M8
S
_DQ[24]
A
S
_DQ[25]
A
N8
S
A
_DQ[26]
N7
S
A
_DQ[27]
S
_DQ[28]
A
M9
S
_DQ[29]
A
N9
S
_DQ[30]
A
M7
S
A
_DQ[31]
S
A
_DQ[32]
S
_DQ[33]
A
S
_DQ[34]
A
S
_DQ[35]
A
S
A
_DQ[36]
S
A
_DQ[37]
AJ5
S
A
_DQ[38]
AJ6
S
_DQ[39]
A
AJ8
S
A_DQ[40]
S
A
_DQ[41]
AJ9
S
A
_DQ[42]
S
_DQ[43]
A
S
_DQ[44]
A
S
A
_DQ[45]
AL9
S
A
_DQ[46]
AL8
S
_DQ[47]
A
S
_DQ[48]
A
S
A
_DQ[49]
S
A
_DQ[50]
S
_DQ[51]
A
S
_DQ[52]
A
S
_DQ[53]
A
S
A
_DQ[54]
S
_DQ[55]
A
S
_DQ[56]
A
S
A
_DQ[57]
S
A
_DQ[58]
S
_DQ[59]
A
S
A
_DQ[60]
S
A
_DQ[61]
S
_DQ[62]
A
S
A
_DQ[63]
_BS[0]
SA
SA
_BS[1]
V6
SA_BS[2]
_CAS#
SA
SA
_RAS#
SA
_WE#
4
CLK_DDR0
_
M
AB6
S
_CK[0]
A
_CLK#[0]
SA
S
_CKE[0]
A
SA
_CK[1]
SA
_CLK#[1]
SA
_CKE[1]
S
A
_CK[2]
S
A
_CLK#[2]
S
_CKE[2]
A
S
A
_CK[3]
S
A
_CLK#[3]
S
_CKE[3]
A
S
_CS#[0]
A
S
_CS#[1]
A
S
_CS#[2]
A
S
A
_CS#[3]
S
_ODT[0]
A
S
_ODT[1]
A
S
A
_ODT[2]
S
_ODT[3]
A
S
A
_DQS#[0]
S
_DQS#[1]
A
S
_DQS#[2]
A
S
_DQS#[3]
A
S
A
_DQS#[4]
S
A
_DQS#[5]
S
_DQS#[6]
A
S
_DQS#[7]
A
S
_DQS[0]
A
S
_DQS[1]
A
S
_DQS[2]
A
S
A
_DQS[3]
S
A
_DQS[4]
S
_DQS[5]
A
S
A
_DQS[6]
S
A
_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
S
_MA[0]
A
S
_MA[1]
A
S
A
_MA[2]
S
A
_MA[3]
S
A
_MA[4]
S
_MA[5]
A
S
_MA[6]
A
S
A
_MA[7]
S
A
_MA[8]
S
A
_MA[9]
S
A
_MA[10]
S
_MA[11]
A
S
_MA[12]
A
S
_MA[13]
A
S
_MA[14]
A
S
_MA[15]
A
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
CLK_DDR#0
_
M
D
R_CKE0_DIMMA
D
_
CLK_DDR1
M
CLK_DDR#1
_
M
D
R_CKE1_DIMMA
D
R_CS0_DIMMA#
D
D
D
R_CS1_DIMMA#
D
ODT0
_
M
ODT1
_
M
D
R_A_DQS#0
D
D
R_A_DQS#1
D
R_A_DQS#2
D
D
R_A_DQS#3
D
D
R_A_DQS#4
D
D
R_A_DQS#5
D
D
R_A_DQS#6
D
D
R_A_DQS#7
D
D
R_A_DQS0
D
D
R_A_DQS1
D
D
R_A_DQS2
D
D
D
R_A_DQS3
D
R_A_DQS4
D
D
D
R_A_DQS5
D
R_A_DQS6
D
D
R_A_DQS7
D
D
D
R_A_MA0
D
D
R_A_MA1
D
R_A_MA2
D
D
D
R_A_MA3
D
D
R_A_MA4
D
R_A_MA5
D
D
D
R_A_MA6
D
D
R_A_MA7
D
R_A_MA8
D
D
D
R_A_MA9
D
R_A_MA10
D
D
R_A_MA11
D
D
D
R_A_MA12
D
R_A_MA13
D
D
D
R_A_MA14
D
D
R_A_MA15
D
CLK_DDR0 <12>
M_
CLK_DDR#0 <12>
M_
D
R_CKE0_DIMMA <12>
D
CLK_DDR1 <12>
_
M
_CLK_DDR#1 <12>
M
R_CKE1_DIMMA <12>
D
D
R_CS0_DIMMA# <12>
D
D
R_CS1_DIMMA# <12>
D
D
ODT0 <12>
_
M
ODT1 <12>
_
M
R_A_DQS#[0..7] <12>
D
D
R_A_DQS[0..7] <12>
D
D
R_A_MA[0..15] <12>
D
D
3
D
R_B_D[0..63]<13>
D
R_B_BS0<13>
D
D
DR_B_BS1<13>
D
R_B_BS2<13>
D
D
D
R_B_CAS#<13>
D
DR_B_RAS#<13>
D
R_B_WE#<13>
D
D
D
R_B_D0
D
D
R_B_D1
D
D
R_B_D2
D
D
R_B_D3
D
D
D
R_B_D4
D
R_B_D5
D
R_B_D6
D
D
D
D
R_B_D7
D
D
R_B_D8
D
D
R_B_D9
D
D
R_B_D10
D
D
R_B_D11
D
D
R_B_D12
D
R_B_D13
D
D
R_B_D14
D
D
R_B_D15
D
R_B_D16
D
D
D
R_B_D17
D
D
R_B_D18
D
D
R_B_D19
D
D
R_B_D20
D
D
R_B_D21
D
D
R_B_D22
D
R_B_D23
D
D
R_B_D24
D
D
D
R_B_D25
D
D
R_B_D26
D
D
R_B_D27
D
R_B_D28
D
D
D
R_B_D29
D
D
R_B_D30
D
D
R_B_D31
D
D
D
R_B_D32
D
R_B_D33
D
D
R_B_D34
D
D
D
R_B_D35
D
D
R_B_D36
D
R_B_D37
D
D
R_B_D38
D
D
R_B_D39
D
D
D
R_B_D40
D
R_B_D41
D
D
D
R_B_D42
D
R_B_D43
D
D
DR_B_D44
D
R_B_D45
D
D
R_B_D46
D
D
D
R_B_D47
D
D
R_B_D48
D
R_B_D49
D
D
R_B_D50
D
D
DR_B_D51
D
D
R_B_D52
D
R_B_D53
D
D
R_B_D54
D
D
D
R_B_D55
D
R_B_D56
D
D
D
R_B_D57
D
D
R_B_D58
D
R_B_D59
D
D
R_B_D60
D
D
R_B_D61
D
D
D
R_B_D62
D
R_B_D63
D
R_B_BS0
D
D
D
D
R_B_BS1
D
D
R_B_BS2
D
R_B_CAS#
D
D
D
R_B_RAS#
D
R_B_WE#
D
AM5
AM6
AJ11
AH11
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AT8
AT9
AR8
AA9
AA7
AB8
AB9
2
J
J
PU1D
PU1D
C
C
CLK_DDR2
_
M
AE2
S
_CK[0]
B
S
B
C9
_DQ[0]
B
S
A7
B
_DQ[1]
S
B
_DQ[2]
S
C8
_DQ[3]
B
S
A9
_DQ[4]
B
S
A8
B
_DQ[5]
S
D9
B
_DQ[6]
S
D8
B
_DQ[7]
S
G4
B
_DQ[8]
S
F4
_DQ[9]
B
S
F1
_DQ[10]
B
S
G1
_DQ[11]
B
S
G5
B
_DQ[12]
S
F5
B
_DQ[13]
S
F2
B
_DQ[14]
S
G2
B
_DQ[15]
S
J7
_DQ[16]
B
S
J8
_DQ[17]
B
S
_DQ[18]
B
S
K9
_DQ[19]
B
S
J9
_DQ[20]
B
S
J10
B
_DQ[21]
S
K8
B
_DQ[22]
S
K7
B
_DQ[23]
S
M5
B
_DQ[24]
S
N4
_DQ[25]
B
S
N2
B_DQ[26]
S
N1
_DQ[27]
B
S
M4
_DQ[28]
B
S
N5
_DQ[29]
B
S
M2
_DQ[30]
B
S
M1
B
_DQ[31]
S
_DQ[32]
B
S
B
_DQ[33]
S
B
_DQ[34]
S
B
_DQ[35]
S
B
_DQ[36]
S
B
_DQ[37]
S
B
_DQ[38]
S
B
_DQ[39]
S
_DQ[40]
B
S
B
_DQ[41]
S
_DQ[42]
B
S
_DQ[43]
B
S
_DQ[44]
B
S
_DQ[45]
B
S
_DQ[46]
B
S
_DQ[47]
B
S
_DQ[48]
B
S
_DQ[49]
B
S
_DQ[50]
B
S
_DQ[51]
B
S
_DQ[52]
B
S
_DQ[53]
B
S
_DQ[54]
B
S
_DQ[55]
B
S
_DQ[56]
B
S
_DQ[57]
B
S
_DQ[58]
B
S
_DQ[59]
B
S
_DQ[60]
B
S
_DQ[61]
B
S
_DQ[62]
B
S
_DQ[63]
B
S
S
B
_BS[0]
S
_BS[1]
B
R6
S
B
_BS[2]
S
_CAS#
B
S
B
_RAS#
S
_WE#
B
_CLK#[0]
S
B
_CKE[0]
S
_CK[1]
B
S
_CLK#[1]
B
S
B
_CKE[1]
B
_CK[2]
S
B
_CLK#[2]
S
B_CKE[2]
S
_CK[3]
B
S
_CLK#[3]
B
S
_CKE[3]
B
S
B
_CS#[0]
S
B
_CS#[1]
S
B
_CS#[2]
S
B
_CS#[3]
S
S
_ODT[0]
B
S
B
_ODT[1]
_ODT[2]
B
S
_ODT[3]
B
S
S
_DQS#[0]
B
S
B
_DQS#[1]
S
B
_DQS#[2]
_DQS#[3]
B
S
S
_DQS#[4]
B
S
B
_DQS#[5]
S
_DQS#[6]
B
S
_DQS#[7]
B
S
B
_DQS[0]
S
B
_DQS[1]
S
_DQS[2]
B
B
_DQS[3]
S
S
B
_DQS[4]
S
_DQS[5]
B
S
_DQS[6]
B
DR SYSTEM MEMORY B
DR SYSTEM MEMORY B
S
B
_DQS[7]
D
D
B
_MA[0]
S
B
_MA[1]
S
B
_MA[2]
S
_MA[3]
B
S
B
_MA[4]
S
_MA[5]
B
S
_MA[6]
B
S
_MA[7]
B
S
_MA[8]
B
S
B
_MA[9]
S
_MA[10]
B
S
B
_MA[11]
S
B
_MA[12]
S
B
_MA[13]
S
B
_MA[14]
S
_MA[15]
B
S
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
CLK_DDR#2
_
M
R_CKE2_DIMMB
D
D
CLK_DDR3
_
M
CLK_DDR#3
_
M
R_CKE3_DIMMB
D
D
R_CS2_DIMMB#
D
D
R_CS3_DIMMB#
D
D
ODT2
_
M
ODT3
_
M
R_B_DQS#0
D
D
D
R_B_DQS#1
D
D
R_B_DQS#2
D
R_B_DQS#3
D
D
R_B_DQS#4
D
D
D
R_B_DQS#5
D
R_B_DQS#6
D
D
DR_B_DQS#7
D
R_B_DQS0
D
D
D
R_B_DQS1
D
D
R_B_DQS2
D
R_B_DQS3
D
D
R_B_DQS4
D
D
D
R_B_DQS5
D
R_B_DQS6
D
D
D
R_B_DQS7
D
R_B_MA0
D
D
D
R_B_MA1
D
D
R_B_MA2
D
D
R_B_MA3
D
R_B_MA4
D
D
D
R_B_MA5
D
D
R_B_MA6
D
R_B_MA7
D
D
R_B_MA8
D
D
R_B_MA9
D
D
D
R_B_MA10
D
DR_B_MA11
D
R_B_MA12
D
D
D
R_B_MA13
D
D
R_B_MA14
D
R_B_MA15
D
D
1
_
CLK_DDR2 <13>
M
M_
CLK_DDR#2 <13>
DD
R_CKE2_DIMMB <13>
CLK_DDR3 <13>
M_
_
CLK_DDR#3 <13>
M
D
R_CKE3_DIMMB <13>
D
R_CS2_DIMMB# <13>
D
D
D
R_CS3_DIMMB# <13>
D
ODT2 <13>
_
M
_
ODT3 <13>
M
R_B_DQS#[0..7] <13>
D
D
R_B_DQS[0..7] <13>
D
D
R_B_MA[0..15] <13>
D
D
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
A A
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
TYCO_2013620-3_IVYBRIDGE
2
LL CONFIDENTIAL/PROPRIETARY
E
D
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
tle
i
i
i
tle
tle
T
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
y Bridge (1/6)
v
v
v
y Bridge (1/6)
y Bridge (1/6)
I
I
I
-7781
A
A
A
-7781
-7781
L
L
L
1Friday, February 24, 2012
6
6
6
1Friday, February 24, 2012
8
8
8
1
1Friday, February 24, 2012
f
f
f
o
o
o
0
.
.
.
0
0
1
1
1
5
D D
C
F
G0_R<7>
C
F
G1_R<7>
C
G5_R<7>
F
+
CC_GFXCORE
V
V
XG_VAL_SENSE
1 2
R
R
C
C
122 49.9_0402_ 1%~D@
122 49.9_0402_ 1%~D@
CC_CORE
V
C
C
R
R
R
R
C
C
R
R
C
C
1 2
123 49.9_0402_ 1%~D@
123 49.9_0402_ 1%~D@
1 2
120 49.9_0402_ 1%~D@
120 49.9_0402_ 1%~D@
1 2
121 49.9_0402_ 1%~D@
121 49.9_0402_ 1%~D@
C C
+
B B
A
12
@
@
C
C
R
R
100_0402_1%~D
100_0402_1%~D
V
S
SAXG_VAL_SENSE
V
C_VAL_SNESE
C
12
C
C
@
@
R
R
100_0402_1%~D
100_0402_1%~D
V
S_VAL_SNESE
S
69
69
71
71
1 2
36 0_0402_5%~D@
36 0_0402_5%~D@
E
E
R
R
1 2
34 0_0402_5%~D@
34 0_0402_5%~D@
E
E
R
R
1 2
35 0_0402_5%~D@
35 0_0402_5%~D@
E
E
R
R
C
F
G2<7>
C
F
G3<7>
C
F
G4<7>
C
G6<7>
F
C
G7<7>
F
C
G8<7>
F
C
G9<7>
F
C
FG10<7>
C
F
G11<7>
9
9
PAD~D@
PAD~D@
T
T
0 PAD~D@
0 PAD~D@
1
1
T
T
T
T
1
1
2 PAD~D@
2 PAD~D@
4 PAD~D@
4 PAD~D@
1
1
T
T
C
G16<7>
F
C
G17<7>
F
2PAD~D @
2PAD~D @
2
2
T
T
2
2
8PAD~D @
8PAD~D @
T
T
T
T
2
2
9PAD~D @
9PAD~D @
0PAD~D @
0PAD~D @
3
3
T
T
3
3
1PAD~D @
1PAD~D @
T
T
T
T
3PAD~D @
3
3
3PAD~D @
T
T
5PAD~D @
3
35PAD~D @
T
T
3
3
6PAD~D @
6PAD~D @
T
T
3
7PAD~D @
7PAD~D @
3
T
T
8PAD~D @
3
3
8PAD~D @
T
T
4
4
0PAD~D @
0PAD~D @
4
4
1PAD~D @
1PAD~D @
T
T
T
T
2PAD~D @
2PAD~D @
4
4
T
T
4
4
3PAD~D @
3PAD~D @
T
T
4PAD~D @
4PAD~D @
4
4
5PAD~D @
4
4
5PAD~D @
T
T
T
T
6PAD~D @
4
4
6PAD~D @
7PAD~D @
7PAD~D @
4
4
T
T
8PAD~D @
4
4
8PAD~D @
T
T
T
T
2PAD~D @
2PAD~D @
5
5
4
C
FG0
C
G1
F
C
FG2
C
F
G3
C
F
G4
C
F
G5
C
F
G6
C
G7
F
C
G8
F
C
G9
F
C
G10
F
C
F
G11
C
F
G12
C
F
G13
C
F
G14
C
F
G15
C
F
G16
C
F
G17
V
XG_VAL_SENSE
A
V
SAXG_VAL_SENSE
S
V
C_VAL_SNESE
C
V
S_VAL_SNESE
S
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
AJ31
AH31
AJ33
AH33
AJ26
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
J15
CPU1E
CPU1E
J
J
F
G[0]
C
F
G[1]
C
F
G[2]
C
FG[3]
C
G[4]
F
C
G[5]
F
C
G[6]
F
C
G[7]
F
C
G[8]
F
C
G[9]
F
C
G[10]
F
C
G[11]
F
C
G[12]
F
C
G[13]
F
C
G[14]
F
C
G[15]
F
C
G[16]
F
C
G[17]
F
C
VA
XG_VAL_SENSE
VS
SAXG_VAL_SENSE
V
C_VAL_SENSE
C
V
S_VAL_SENSE
S
RS
VD5
S
VD8
R
VD9
RS
RS
VD10
VD11
RS
VD12
RS
RS
VD13
VD14
RS
VD15
S
R
S
VD16
R
VD17
S
R
VD18
S
R
S
VD19
R
VD20
S
R
SVD21
R
S
VD22
R
S
VD23
R
R
SVD24
R
S
VD25
S
VD27
R
FG
FG
C
C
ESERVED
ESERVED
R
R
VC
C_DIE_SENSE
V
S_DIE_SENSE
S
VD_NCTF1
S
R
S
VD_NCTF2
R
VD_NCTF3
S
R
RS
VD_NCTF4
VD_NCTF5
S
R
VD_NCTF6
S
R
VD_NCTF7
S
R
S
VD_NCTF8
R
SVD_NCTF9
R
VD_NCTF10
S
R
B
B
C
VD_NCTF11
S
R
VD_NCTF12
S
R
VD_NCTF13
S
R
R
VD28
S
R
VD29
S
R
VD30
S
R
VD31
S
VD32
RS
RS
VD33
VD34
S
R
VD35
S
R
VD37
RS
VD38
S
R
VD39
S
R
VD40
S
R
S
VD51
R
S
VD52
R
C
LK_ITP
LK_ITP#
3
T
T
9 PAD~D@
9 PAD~D@
3
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
K
E
Y
3
T
T
PAD~D@
PAD~D@
1
1
2
2
PAD~D@
PAD~D@
T
T
PAD~D@
PAD~D@
3
3
T
T
4
4
PAD~D@
PAD~D@
T
T
T
T
PAD~D@
PAD~D@
5
5
T
T
PAD~D@
PAD~D@
6
6
T
T
PAD~D@
PAD~D@
7
7
8
8
PAD~D@
PAD~D@
T
T
1 PAD~D@
1 PAD~D@
1
1
T
T
13 PAD~D@T1
3 PAD~D@
T
T
T
5 PAD~D@
5 PAD~D@
1
1
T
T
6 PAD~D@
6 PAD~D@
1
1
T
T
7 PAD~D@
7 PAD~D@
1
1
8 PAD~D@
8 PAD~D@
1
1
T
T
9 PAD~D@
1
1
9 PAD~D@
T
T
T
T
0 PAD~D@
0 PAD~D@
2
2
T
T
1 PAD~D@
1 PAD~D@
2
2
2
2
3 PAD~D@
3 PAD~D@
T
T
2
2
4 PAD~D@
4 PAD~D@
T
T
25 PAD~D@T2
5 PAD~D@
T
T
26 PAD~D@T26 PAD~D@
2
2
7 PAD~D@
7 PAD~D@
T
T
T
T
3
3
2 PAD~D@
2 PAD~D@
4 PAD~D@
4 PAD~D@
3
3
T
T
C
L
K_XDP_ITP <7>
C
K_XDP_ITP# <7>
L
T
T
9 PAD~D@
9 PAD~D@
4
4
5
5
0 PAD~D@
0 PAD~D@
T
T
1 PAD~D@
1 PAD~D@
5
5
T
T
T
T
3 PAD~D@
5
3 PAD~D@
5
2
CF
G Straps for Processor
C
F
G2
12
C
C
51
@
51
@
R
R
1K_0402_5%~D
1K_0402_5%~D
P
EG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
C
G2
F
definition matches socket pin map definition
0:Lane Reversed
C
FG4
12
R
R
C
C
52
@
52
@
1K_0402_5%~D
1K_0402_5%~D
D
isplay Port Presence Strap
1 : Disabled; No Physical Display Port
C
F
G4
attached to Embedded Display Port
0
: Enabled; An external Display Port device is
connected to the Embedded Display Port
C
G6
F
C
G5
F
1
12
54
@
54
@
C
C
R
R
1K_0402_5%~D
1K_0402_5%~D
P
CIE Port Bifurcation Straps
1
1
C
F
G[6:5]
: (Default) x16 - Device 1 functions 1 and 2 disabled
1
0: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
0
1: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2
R
R
C
C
53
@
53
@
1K_0402_5%~D
1K_0402_5%~D
1
C
F
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
P
EG DEFER TRAINING
C
FG7
A A
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
G7
12
C
C
56
@
56
@
R
R
1K_0402_5%~D
1K_0402_5%~D
1: (Default) PEG Train immediately
following xxRESETB de assertion
0
:
PEG Wait for BIOS for training
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
i
i
Title
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
I
I
I
y Bridge (1/6)
v
v
vy Bridge (1/6)
y Bridge (1/6)
L
L
L
-7781
A
A
-7781
-7781
A
1
1
1
1
0
.
.
.
0
9
9
9
0
1Friday, February 24, 2012
61Friday, February 24, 2012
6
6
1Friday, February 24, 2012
o
o
o
f
f
f
5
+
CC_CORE
V
53A
D D
C C
B B
A A
5
4
JC
JC
PU1F
PU1F
AG35
V
C
C1
AG34
V
C
C2
AG33
V
C3
C
AG32
V
C4
C
AG31
V
C5
C
AG30
V
CC6
AG29
V
C
C7
AG28
V
C
C8
AG27
V
CC9
AG26
V
C
C10
AF35
V
C
C11
AF34
V
C12
C
AF33
V
C13
C
AF32
V
C14
C
AF31
V
CC15
AF30
V
C
C16
AF29
V
C
C17
AF28
V
C18
C
AF27
V
C19
C
AF26
V
C20
C
AD35
V
C
C21
AD34
V
C22
C
AD33
V
C23
C
AD32
V
C24
C
AD31
V
C
C25
AD30
V
C
C26
AD29
V
C27
C
AD28
V
C28
C
AD27
V
C29
C
AD26
V
C
C30
AC35
V
C31
C
AC34
V
C32
C
AC33
V
C
C33
AC32
V
C
C34
AC31
V
C
C35
AC30
V
C36
C
AC29
V
C37
C
AC28
V
C
C38
AC27
V
C39
C
AC26
V
C40
C
AA35
V
C41
C
AA34
V
C
C42
AA33
V
C43
C
AA32
V
C44
C
AA31
V
C
C45
AA30
V
C
C46
AA29
V
C
C47
AA28
V
C
C48
AA27
V
C
C49
AA26
V
C
C50
Y35
V
C51
C
Y34
V
C
C52
Y33
V
C
C53
Y32
V
C54
C
Y31
V
CC55
Y30
V
C
C56
Y29
V
C57
C
Y28
V
C58
C
Y27
V
C
C59
Y26
V
C60
C
V35
V
C61
C
V34
V
C
C62
V33
V
C63
C
V32
V
C64
C
V31
V
C
C65
V30
V
C66
C
V29
V
C67
C
V28
V
C
C68
V27
V
C69
C
V26
V
C70
C
U35
V
C
C71
U34
C
C72
V
U33
C73
C
V
U32
C74
C
V
U31
C75
C
V
U30
C76
C
V
U29
C77
C
V
U28
C78
C
V
U27
C
C79
V
U26
C
C80
V
R35
C
C81
V
R34
C
C82
V
R33
C
C83
V
R32
C
C84
V
R31
C85
C
V
R30
C
C86
V
R29
C87
C
V
R28
C88
C
V
R27
C
C89
V
R26
C90
C
V
P35
C91
C
V
P34
C92
C
V
P33
C93
C
V
P32
C94
C
V
P31
C95
C
V
P30
C96
C
V
P29
C97
C
V
P28
C98
C
V
P27
C99
C
V
P26
C
C100
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
4
POWER
POWER
PEG AND DDR
PEG AND DDR
ORE SUPPLY
ORE SUPPLY
C
C
V
S
SENSE LINES SVID
SENSE LINES SVID
CIO1
C
V
CIO2
C
V
CIO3
C
V
CIO4
C
V
C
CIO5
V
C
CIO6
V
C
CIO7
V
CIO8
C
V
C
CIO9
V
C
CIO10
V
C
CIO11
V
C
CIO12
V
CIO13
C
V
CIO14
C
V
CIO15
C
V
CIO16
C
V
C
CIO17
V
C
CIO18
V
C
CIO19
V
C
CIO20
V
CIO21
C
V
CIO22
C
V
CIO23
C
V
CIO24
C
V
C
CIO25
V
CIO26
C
V
CIO27
C
V
CIO28
C
V
CIO29
C
V
C
CIO30
V
CIO31
C
V
C
CIO32
V
C
CIO33
V
C
CIO34
V
C
CIO35
V
CIO36
C
V
C
CIO37
V
CIO38
C
V
CIO39
C
V
C
CIO40
V
V
DALERT#
I
V
IDSCLK
V
I
DSOUT
V
C_SENSE
C
V
S_SENSE
S
C
CIO_SENSE
V
S_SENSE_VCCIO
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
3
+
.05V_RUN_VTT
1
8
5A
.
Note: Place the PU resistors c lose to CPU
RC61 close to C PU 300 - 1500mi ls
H
_CPU_SVIDALRT#
H
CPU_SVIDALRT#
_
V
DSCLK
I
V
I
DSOUT
V
CSENSE_R
C
V
S
SSENSE_R
V
T
T_SENSE
V
SIO_SENSE_R
S
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
V
I
DSCLK <51>
P
lace RC66, RC70, RC75 near CPU
1 2
67 0_0402_5%~D@
67 0_0402_5%~D@
C
C
R
R
1 2
68 0_0402_5%~D@
68 0_0402_5%~D@
C
C
R
R
3
R
R
C98 10_0402_1%~D
C98 10_0402_1%~D
10_0402_1%~D
10_0402_1%~D
12
R
R
C
C
133
133
1 2
R
R
61 43_0402_5%~D
61 43_0402_5%~D
C
C
+
1
.05V_RUN_VTT
C
D Note: Place t he PU
12
63
C
C
63
R
R
130_0402_1%~D
130_0402_1%~D
H
CPU_SVIDALRT# must be routed between the
_
VIDSOUT and VIDSCLK lines to reduce cross
talk. 18 mils spacing to others.
12
A
resistors close to CPU
RC63 close to C PU 300 - 1500mi ls
V
DSOUT <51>
I
75
@
C
C75
@
R
R
100_0402_1%~D
100_0402_1%~D
1 2
+
1
.05V_RUN_VTT
V
T
T_SENSE <49>
V
S
SIO_SENSE_R <49>
2
+
1
.05V_RUN_VTT
12
+
V
CC_CORE
12
12
2
C
C
60
60
R
R
75_0402_1%~D
75_0402_1%~D
R
R
C
C
66
66
100_0402_1%~D
100_0402_1%~D
V
CSENSE <51>
C
V
S
SSENSE <5 1>
70
70
C
C
R
R
100_0402_1%~D
100_0402_1%~D
1
V
I
DALERT_N <51>
Iccmax current changed for PDD G Rev0.7
C
U Power Rail Table
P
V
ltage Rail
o
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+
1
.5V_MEM 1.5
D
escription
*
5
A
to Mem control ler(+1.5V_CPU_V DDQ)
5-6A to 2 DIMMs /channel
2-5A to +1.5V_R UN & +0.75V_DDR _VTT
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
L
L
L
A
A
A
Voltage
0
.
1.05
0
.
1.8
1
0.65-0.9
I
I
I
y Bridge (1/6)
v
y Bridge (1/6)
y Bridge (1/6)
v
v
-7781
-7781
-7781
1
65-1.3
0-1.1
.5
S
0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16
1
1
1
0 6
0 6
0 6
o
o
o
f
f
f
*
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+
1.5V_CPU_VDDQ Source
+
.3V_ALW2
3
12
C
C
74
74
R
R
100K_0402_5%~D
1
+
+
2
2
+
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
C
C
C
C
176
176
61
V
CC_GFXCORE
100K_0402_5%~D
R
N_ON_CPU1.5VS3#
U
C
C
4A
4A
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
A
3
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.5A
B6
A6
A2
D D
S
I
O_SLP_S3#<16,27,35,39,42,47>
C
P
U1.5V_S3_GATE<40>
C C
B B
1 2
R
R
96 1K_0402_5%~D@
96 1K_0402_5%~D@
C
C
1 2
C
97 1K_0402_5%~D@
97 1K_0402_5%~D@
C
R
R
A A
+
1
.8V_RUN
R
R
R
R
+
DIMM0_1_VREF_CPU
+
D
IMM0_1_CA_CPU
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
173
173
2
5
1 2
82 0_0402_5%~D@
82 0_0402_5%~D@
C
C
1 2
79 0_0402_5%~D@
79 0_0402_5%~D@
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
174
174
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
175
175
2
4
+
P
WR_SRC_S
12
3
5
4
R
U
N_ON_CPU1.5VS3# <7,42>
P
P
OWER
J
J
C
PU1G
PU1G
C
V
A
XG1
V
XG2
A
V
XG3
A
V
A
XG4
V
XG5
A
V
XG6
A
V
XG7
A
V
A
XG8
V
A
XG9
V
XG10
A
V
A
XG11
V
A
XG12
V
A
XG13
V
XG14
A
V
A
XG15
V
A
XG16
V
XG17
A
V
XG18
A
V
A
XG19
V
XG20
A
V
XG21
A
V
AXG22
V
XG23
A
V
XG24
A
V
XG25
A
V
XG26
A
V
XG27
A
V
XG28
A
V
A
XG29
V
XG30
A
V
XG31
A
V
A
XG32
V
XG33
A
V
XG34
A
V
A
XG35
V
XG36
A
V
XG37
A
V
XG38
A
V
XG39
A
V
XG40
A
V
XG41
A
V
XG42
A
V
AXG43
V
XG44
A
V
XG45
A
V
A
XG46
A
XG47
V
XG48
A
V
A
XG49
V
XG50
A
V
XG51
A
V
XG52
A
V
XG53
A
V
A
XG54
V
CPLL1
C
V
C
CPLL2
V
C
CPLL3
V
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
OWER
RAPHICS
RAPHICS
G
G
.8V RAIL
.8V RAIL
1
1
4
Q
+
.5V_MEM
1
R
R
72
72
C
C
330K_0402_5%~D
330K_0402_5%~D
R
U
N_ON_CPU1.5VS3
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
C
C
4B
4B
ENSE
ENSE
S
S
Q
3
3
C
C
AO4304L_SO8
AO4304L_SO8
8
7
6
5
4
1M_0402_5%~D
1M_0402_5%~D
12
R
R
C
C
143
143
V
LINES
LINES
_DIMM_VREFDQ
A
S
REFMISC
REFMISC
_DIMM_VREFDQ
B
S
V
V
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
A RAIL
A RAIL
S
S
V
A
XG_SENSE
SAXG_SENSE
S
S
M
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CSA_SENSE
C
V
C
CSA_VID[0]
V
CSA_VID[1]
C
V
C
CIO_SEL
V
_VREF
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
D
V
DQ10
D
DQ11
D
DQ12
D
DQ13
D
DQ14
D
DQ15
D
C
CSA1
CSA2
C
CSA3
C
C
CSA4
CSA5
C
CSA6
C
C
CSA7
CSA8
C
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
1
2
0.022U_0402_25V7K~D
0.022U_0402_25V7K~D
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
1
2
3
C
C
C
C
136
136
5A
6A
+
.5V_CPU_VDDQ
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
C
C
135
135
2
+
CC_GFXCORE
V
12
R
R
100_0402_1%~D
100_0402_1%~D
12
R
R
100_0402_1%~D
100_0402_1%~D
+
IMM0_1_VREF_CPU
D
+
D
IMM0_1_CA_CPU
1 2
140 0_0402_5%~D@
140 0_0402_5%~D@
C
C
R
R
20K_0402_5%~D
20K_0402_5%~D
12
@
@
R
R
C
C
73
73
99
C
C
99
100
C
C
100
+
_SM_VREF_CNT
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
3
+
1
.5V_MEM
1K_0402_1%~D
1K_0402_1%~D
12
@
@
R
R
C
C
80
80
1K_0402_1%~D
1K_0402_1%~D
12
@
@
R
R
C
C
81
81
76
@
76
@
C
C
R
R
100_0402_1%~D
100_0402_1%~D
1
+
V_SM_VREF should
have 10 mil trace width
+
IMM0_1_VREF_CPU
D
+
IMM0_1_CA_CPU
D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C
C
161
161
C
C
C
C
C
C
C162
C162
163
163
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
1
1
C
C
C
C
C
C
C
C
168
169
169
168
2
2
a
dded VCCSA_VID_0 to Power page
V
V
3
+
V
_DDR_SMREF
R
U
N_ON_CPU1.5VS3
2
V
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C164
C164
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
C
C
C
C
170
170
2
2
CCSA_VID_0 <50>
CSA_VID_1 <50>
C
1
R
R
134 0_0402_5%~D@
134 0_0402_5%~D@
C
C
@
@
NTR4503NT1G_SOT23-3~D
NTR4503NT1G_SOT23-3~D
1
C_AXG_SENSE <51>
C
S_AXG_SENSE <51>
S
+
.5V_CPU_VDDQ
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
C
C
C
C
166
166
165
165
2
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0603_6.3V6M~D
1
C
C
C
C
+
+
C
C
C
C
171
172
172
171
2
V
C
CP_PWRCTRL <49>
2
+
1
.5V_CPU_VDDQ
1K_0402_1%~D
2
5
5
C
C
Q
Q
3
2
C
C
C
C
C
C
C
C
C
C
C
C
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
C
C
C
1
2
C
C
C
+
+
C
C
167
167
1K_0402_1%~D
12
R
R
C
C
+
_SM_VREF_CNT
V
84
84
1K_0402_1%~D
1K_0402_1%~D
12
R
R
C
C
78
78
178 0.1U_04 02_10V7K~D
178 0.1U_04 02_10V7K~D
2
1
179 0.1U_04 02_10V7K~D
179 0.1U_04 02_10V7K~D
12
149 0.1U_04 02_10V7K~D
149 0.1U_04 02_10V7K~D
12
150 0.1U_04 02_10V7K~D
150 0.1U_04 02_10V7K~D
1
2
+
VCC_SA
V
C
CSA_SENSE <50>
2
6
A
+
.5V_MEM
1
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
C
PU1H
PU1H
J
J
AT35
S1
S
V
AT32
S2
S
V
AT29
S3
S
V
AT27
S4
S
V
AT25
S5
S
V
AT22
S6
S
V
AT19
S
S7
V
AT16
S8
S
V
AT13
S
S9
V
AT10
S10
S
V
AT7
S11
S
V
AT4
S12
S
V
AT3
S13
S
V
AR25
S14
S
V
AR22
S15
S
V
AR19
S16
S
V
AR16
S17
S
V
AR13
S18
S
V
AR10
S19
S
V
AR7
S20
S
V
AR4
S21
S
V
AR2
S22
S
V
AP34
S23
S
V
AP31
S24
S
V
AP28
S25
S
V
AP25
S26
S
V
AP22
S27
S
V
AP19
S28
S
V
AP16
S29
S
V
AP13
S30
S
V
AP10
S31
S
V
AP7
S32
S
V
AP4
S33
S
V
AP1
S34
S
V
AN30
S35
S
V
AN27
S36
S
V
AN25
S37
S
V
AN22
S38
S
V
AN19
SS39
V
AN16
S40
S
V
AN13
S41
S
V
AN10
S
S42
V
AN7
S
S43
V
AN4
S
S44
V
AM29
S
S45
V
AM25
S
S46
V
AM22
S47
S
V
AM19
S48
S
V
AM16
S49
S
V
AM13
S50
S
V
AM10
S51
S
V
AM7
S52
S
V
AM4
S
S53
V
AM3
S
S54
V
AM2
S
S55
V
AM1
S
S56
V
AL34
S
S57
V
AL31
S
S58
V
AL28
S59
VS
AL25
S60
VS
AL22
S61
VS
AL19
S62
VS
AL16
VSS63
AL13
S64
VS
AL10
VS
S65
AL7
VS
S66
AL4
VS
S67
AL2
V
S68
S
AK33
V
S69
S
AK30
V
S70
S
AK27
V
S
S71
AK25
V
S
S72
AK22
V
S
S73
AK19
V
S74
S
AK16
V
S75
S
AK13
V
S76
S
AK10
V
S
S77
AK7
V
S
S78
AK4
V
S
S79
AJ25
V
S80
S
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
mpal Electronics, Inc.
mpal Electronics, Inc.
o
T
T
tle
i
itle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
1
SS
SS
V
V
I
I
I
y Bridge (1/6)
y Bridge (1/6)
v
v
v
y Bridge (1/6)
L
L
L
A-7781
A-7781
A
-7781
1
S81
VS
S82
VS
V
S
S83
VS
S84
V
S
S85
V
S
S86
V
S87
S
V
S88
S
V
S
S89
V
S
S90
V
S
S91
V
S
S92
V
S
S93
V
S
S94
V
S95
S
V
S96
S
V
S98
S
V
S99
S
V
S100
S
V
S
S101
V
S
S102
V
S
S103
V
S
S104
V
S105
S
V
S106
S
V
S107
S
V
S108
S
V
S109
S
V
S
S110
V
S
S111
V
S
S112
V
S
S113
V
S114
S
V
S115
S
V
S
S116
V
S
S117
V
S
S118
V
S119
S
V
S120
S
V
S121
S
V
S
S122
V
S
S123
V
S
S124
V
S125
S
V
S126
S
V
S127
S
V
S
S128
V
S
S129
V
S
S130
V
S131
S
V
S132
S
V
S
S133
V
S
S134
V
S135
S
V
S136
S
V
S
S137
V
S
S138
V
S
S139
V
S140
S
V
S141
S
V
S
S142
V
S
S143
V
S144
S
V
S145
S
V
S
S146
V
S
S147
V
S148
S
V
S149
S
V
S
S150
V
S
S151
V
S152
S
V
S153
S
V
S
S154
V
S155
S
V
S156
S
V
S157
S
V
S
S158
V
S159
S
V
S160
S
1
1
1
1 6
1 6
1 6
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
o
o
o
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
5
_DDR_REFA_M3
+V
+
V
_DDR_REF
D D
o
pulate RD1, De-Populate RD7 for Intel DDR3
P
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
ll VREF traces should
A
have 10 mil trace width
D
R_A_DQS#[0..7]<8>
D
R_A_D[0..63]<8>
D
D
D
R_A_DQS[0..7]<8>
D
D
R_A_MA[0..15]<8>
D
C C
a
yout Note:
L
Place near JDIMM1
+
.5V_MEM
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
3
3
2
+
1
.5V_MEM
B B
A A
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
1
D
D
7
7
2
2
a
yout Note:
L
Place near JDIMM1.203,204
+
.75V_DDR_VTT
0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
17
17
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
4
4
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
C
C
1
D
D
9
9
8
8
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
18
18
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
5
C
C
C
C
D
D
D
D
6
5
6
5
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
D
D
10
10
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
19
19
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
C
C
1
1
D
D
11
51
51
11
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
D
D
20
20
330U_SX_2VY~D
330U_SX_2VY~D
@
@
1
C
C
C
C
1
+
+
D
D
D
D
14
13
13
14
2
2
2 10K_0402_5%~D
D
D
2 10K_0402_5%~D
R
R
1 2
1 2
D
D
3 10K_0402_5%~D
3 10K_0402_5%~D
R
R
1 2
D
D
R
R
1 2
RD
+
3
.3V_RUN
4
IMM1 H=5.2
+
IMM1_VREF_DQ
7 0_0402_5%~D@
7 0_0402_5%~D@
1 0_0402_5%~D@RD1 0_0402_5%~D@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
D
D
D
D
4
D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
D
R_A_D0
D
D
R_A_D1
D
C
C
C
C
1
D
D
D
D
2
2
1
1
R_CKE0_DIMMA<8>
D
R_A_BS2<8>
D
_
CLK_DDR0<8>
M
CLK_DDR#0<8>
_
M
R_A_BS0<8>
D
D
R_A_WE#<8>
D
D
D
R_A_CAS#<8>
D
R_CS1_DIMMA#<8>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
D
DR_A_D2
2
D
DR_A_D3
D
D
R_A_D8
D
R_A_D9
D
D
D
R_A_DQS#1
D
R_A_DQS1
D
D
D
R_A_D10
D
D
R_A_D11
D
R_A_D16
D
D
DR_A_D17
D
D
R_A_DQS#2
D
R_A_DQS2
D
D
R_A_D18
D
D
R_A_D19
D
D
R_A_D24
D
D
R_A_D25
D
D
D
R_A_D26
D
D
R_A_D27
D
D
R_CKE0_DIMMA
D
D
R_A_BS2
D
R_A_MA12
D
D
R_A_MA9
D
D
R_A_MA8
D
D
R_A_MA5
D
D
R_A_MA3
D
D
R_A_MA1
D
M
_
CLK_DDR0
M
_
CLK_DDR#0
D
R_A_MA10
D
D
D
R_A_BS0
D
R_A_WE#
D
D
R_A_CAS#
D
D
R_A_MA13
D
D
D
R_CS1_DIMMA#
D
D
R_A_D32
D
R_A_D33
D
D
R_A_DQS#4
D
D
R_A_DQS4
D
D
R_A_D34
D
D
R_A_D35
D
D
D
R_A_D40
D
R_A_D41
D
D
DR_A_D42
D
D
R_A_D43
D
D
R_A_D48
D
R_A_D49
D
D
D
R_A_DQS#6
D
D
R_A_DQS6
D
R_A_D50
D
D
R_A_D51
D
D
D
R_A_D56
D
R_A_D57
D
D
D
R_A_D58
D
D
R_A_D59
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
+
.75V_DDR_VTT
C
C
D
D
21
21
0
C
C
D
D
22
22
2
+
.5V_MEM
1
JD
J
J
IMM1
IMM1
D
D
1
EF_DQ
VR
3
V
S
S
5
D
0
Q
7
D
1
Q
9
V
S
S
11
D
0
M
13
V
SS
15
DQ
2
17
DQ
3
19
V
S
S
21
DQ
8
23
D
Q
9
25
V
S
S
27
D
S1#
Q
29
D
Q
S1
31
V
S
S
33
D
Q
10
35
D
Q
11
37
V
S
S
39
D
Q
16
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
18
Q
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
25
Q
61
V
S
S
63
D
3
M
65
V
SS
67
D
Q
26
69
D
Q
27
71
V
S
S
73
C
E0
K
75
V
D
D
7
7
N
C
79
B
A
2
81
V
D
D
83
A
2/BC#
1
5
8
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
7
9
A
1
99
V
D
D
101
C
K
0
103
C
K
0#
105
V
D
D
107
A
0/AP
1
109
B
0
A
111
V
D
D
113
W
E
#
115
C
A
S#
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
Q
32
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
Q
S4
139
V
S
S
141
D
34
Q
143
D
35
Q
145
S
S
V
147
Q
40
D
149
Q
41
D
151
S
S
V
153
M
5
D
155
S
S
V
157
Q
42
D
159
43
Q
D
161
S
S
V
163
48
Q
D
165
49
Q
D
167
S
S
V
169
S6#
Q
D
171
S6
Q
D
173
S
S
V
175
50
Q
D
177
Q
51
D
179
S
S
V
181
56
Q
D
183
Q
57
D
185
S
S
V
187
7
M
D
189
S
S
V
191
58
Q
D
193
Q
59
D
195
S
S
V
197
0
A
S
199
D
DSPD
V
201
A
1
S
203
T
T
V
205
N
D1
G
TYCO_2-2013289-2~D
TYCO_2-2013289-2~D
CONN@
CONN@
3
-
3A to 1 DIMMs/channel
.5V_MEM
1
2
D
R_A_D4
D
D
R_A_D5
D
D
D
R_A_DQS#0
D
D
R_A_DQS0
D
D
R_A_D6
D
D
R_A_D7
D
DR_A_D12
D
D
R_A_D13
D
R3_DRAMRST#_R
D
D
R_A_D14
D
D
R_A_D15
D
D
R_A_D20
D
D
D
R_A_D21
D
D
R_A_D22
D
R_A_D23
D
D
R_A_D28
D
D
DR_A_D29
D
D
R_A_DQS#3
D
R_A_DQS3
D
D
R_A_D30
D
D
D
R_A_D31
D
D
R_CKE1_DIMMA
D
D
R_A_MA15
D
R_A_MA14
D
D
R_A_MA11
D
D
R_A_MA7
D
D
R_A_MA6
D
D
R_A_MA4
D
D
R_A_MA2
D
D
R_A_MA0
D
M
_
CLK_DDR1
M
CLK_DDR#1
_
D
DR_A_BS1
D
D
R_A_RAS#
D
DR_CS0_DIMMA#
M
_
ODT0
M
_
ODT1
D
R_A_D36
D
D
R_A_D37
D
D
R_A_D38
D
D
D
R_A_D39
D
R_A_D44
D
D
D
R_A_D45
D
R_A_DQS#5
D
D
R_A_DQS5
D
D
D
R_A_D46
D
R_A_D47
D
D
D
R_A_D52
D
R_A_D53
D
D
D
R_A_D54
D
D
R_A_D55
D
D
R_A_D60
D
D
R_A_D61
D
R_A_DQS#7
D
D
D
R_A_DQS7
D
R_A_D62
D
D
R_A_D63
D
+
.75V_DDR_VTT
0
D
R_CKE1_DIMMA <8>
D
CLK_DDR1 <8>
_
M
CLK_DDR#1 <8>
_
M
R_A_BS1 <8>
D
D
R_A_RAS# <8>
D
D
D
R_CS0_DIMMA# <8>
D
_
ODT0 <8>
M
ODT1 <8>
_
M
+
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
C
C
1
D
D
15
15
2
R_XDP_WAN_SM BDAT <7,13,14,15,27,34>
D
D
D
R_XDP_WAN_SM BCLK <7,13,14,15,27,34>
D
+
2
V
S
S
4
D
4
Q
6
D
Q
5
8
V
S
S
10
D
Q
S0#
12
D
S0
Q
14
V
S
S
16
D
6
Q
18
D
7
Q
20
V
S
S
22
D
Q
12
24
D
13
Q
26
V
S
S
28
D
M
1
30
R
SET#
E
32
V
S
S
34
D
Q
14
36
D
Q
15
38
V
S
S
40
D
20
Q
42
D
21
Q
44
V
S
S
46
D
M
2
48
V
S
S
50
D
22
Q
52
D
23
Q
54
V
S
S
56
D
Q
28
58
D
29
Q
60
V
S
S
62
D
Q
S3#
64
D
Q
S3
66
V
S
S
68
D
30
Q
70
D
Q
31
72
V
S
S
74
C
K
E1
76
V
D
D
78
A
1
5
80
A
4
1
82
V
D
D
84
A
1
1
6
8
A
7
88
V
D
D
9
0
A
6
2
9
A
4
94
V
D
D
6
9
A
2
9
8
A
0
100
V
D
D
102
C
1
K
104
C
K
1#
106
V
D
D
108
B
1
A
110
R
A
S#
112
V
D
D
114
S
#
0
116
O
D
T0
118
V
D
D
120
O
T1
D
1
22
N
C
124
V
D
D
126
V
EF_CA
R
128
S
S
V
130
Q
36
D
132
37
Q
D
134
S
S
V
136
4
M
D
138
S
S
V
140
38
Q
D
142
39
Q
D
144
S
S
V
146
Q
44
D
148
Q
45
D
150
S
S
V
152
S5#
Q
D
154
Q
S5
D
156
S
S
V
158
46
Q
D
160
Q
47
D
162
S
S
V
164
52
Q
D
166
Q
53
D
168
S
S
V
170
6
M
D
172
S
S
V
174
54
Q
D
176
55
Q
D
178
S
S
V
180
60
Q
D
182
61
Q
D
184
S
S
V
186
S7#
Q
D
188
S7
Q
D
190
S
S
V
192
Q
62
D
194
63
Q
D
196
S
S
V
198
V
ENT#
E
200
D
A
S
202
C
L
S
204
T
T
V
206
N
D2
G
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
P
3
D
IMM1_VREF_CA
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
2
R3_DRAMRST#_R<13>
D
D
+
D
IMM0_1_VREF_CPU
R_HVREF_RST<7>
D
D
+
D
IMM0_1_CA_CPU
3 Circuit (Processor Generated SO-DIMM VREF_DQ)
M
12
11 0_0402_5%~D@
D
D
11 0_0402_5%~D@
R
R
C
C
D
D
16
16
2
1
+
1
.5V_MEM
1
27
27
D
D
R
R
1K_0402_5%~D
1K_0402_5%~D
D
R3_DRAMRST#_R
D
D
D
R_HVREF_RST
D
D
R_HVREF_RST
1
D
D
28 1K_ 0402_5%~D
28 1K_ 0402_5%~D
R
R
29 0_0402_5%~D@
29 0_0402_5%~D@
D
D
R
R
D30 0_0402_5%~D@RD
30 0_0402_5%~D@
R
V
_DDR_REF
+
E
LL CONFIDENTIAL/PROPRIETARY
D
Title
i
i
tle
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
2
1 2
1
1
QD
QD
D
S
D
S
BSS138_G_SOT23-3
BSS138_G_SOT23-3
13
G
G
2
1 2
D
D
2
2
Q
Q
D
S
D
S
BSS138_G_SOT23-3
BSS138_G_SOT23-3
13
G
G
2
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
RIII-SODIMM SLOT1
RIII-SODIMM SLOT1
D
D
D
RIII-SODIMM SLOT1
D
D
D
A
A
A-7781
-7781
-7781
L
L
L
R3_DRAMRST# <7>
D
D
1
+
V
_DDR_REFA_M3
_DDR_REFB_M3
V
+
2 6
2 6
2 6
1
1
1
.
0
0
0
.
.
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
5
D D
o
pulate RD4, De-Populate RD8 for Intel DDR3
P
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
D
D
R_B_DQS#[0..7]<8>
D
R_B_D[0..63]<8>
D
D
D
R_B_DQS[0..7]<8>
D
R_B_MA[0..15]<8>
D
C C
+
1
.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD
CD
25
25
2
+
.5V_MEM
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
B B
A A
10U_0603_6.3V6M~D
C
C
C
C
1
1
D
D
D
D
29
29
30
30
2
2
yout Note:
a
L
Place near JDIMM2.203,204
+
.75V_DDR_VTT
0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
D
D
39
39
2
a
L
Place near JDIMM2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD
CD26
26
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD
CD
1
1
31
31
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C
C
D
D
40
40
2
2
5
yout Note:
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
D
D
D
D
27
27
28
28
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
C
C
1
1
D
D
D
D
33
33
32
32
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
D
D
D
D
42
41
41
42
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
D
D
34
34
ll VREF traces should
A
have 10 mil trace width
10U_0603_6.3V6M~D
330U_SX_2VY~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
@
@
1
C
C
C
C
1
+
+
D
D
D
D
35
36
35
36
2
2
+
V
_DDR_REFB_M3
+
_DDR_REF
V
4
+
IMM2_VREF_DQ
D
1 2
8 0_0402_5%~D@RD8 0_0402_5%~D@
RD
1 2
4 0_0402_5%~D@
4 0_0402_5%~D@
D
D
R
R
+
.3V_RUN
3
5 10K_0402_5%~D
D
D
5 10K_0402_5%~D
R
R
4
1
2
12
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+
3
C
C
D
D
23
23
D
D
D
D
.3V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
R_CKE2_DIMMB<8>
R_B_BS2<8>
D
D
_
CLK_DDR2<8>
M
CLK_DDR#2<8>
_
M
D
R_B_BS0<8>
D
R_B_WE#<8>
D
D
D
R_B_CAS#<8>
D
R_CS3_DIMMB#<8>
12
3
+
.5V_MEM
1
D
R_B_D0
D
D
R_B_D1
D
C
C
D
D
24
24
D
D
R_B_D2
D
D
R_B_D3
D
D
R_B_D8
D
DR_B_D9
D
R_B_DQS#1
D
D
D
R_B_DQS1
D
R_B_D10
D
D
D
R_B_D11
D
D
R_B_D16
D
D
R_B_D17
D
R_B_DQS#2
D
D
R_B_DQS2
D
D
R_B_D18
D
D
DR_B_D19
D
R_B_D24
D
D
DR_B_D25
D
D
R_B_D26
D
R_B_D27
D
D
R_CKE2_DIMMB
D
D
R_B_BS2
D
D
R_B_MA12
D
D
R_B_MA9
D
D
D
R_B_MA8
D
D
R_B_MA5
D
R_B_MA3
D
D
R_B_MA1
D
M
CLK_DDR2
_
M
CLK_DDR#2
_
D
D
R_B_MA10
D
R_B_BS0
D
D
R_B_WE#
D
D
DR_B_CAS#
D
D
R_B_MA13
D
R_CS3_DIMMB#
D
D
R_B_D32
D
D
DR_B_D33
D
D
R_B_DQS#4
D
D
R_B_DQS4
D
D
R_B_D34
D
DR_B_D35
D
D
R_B_D40
D
R_B_D41
D
D
R_B_D42
D
D
R_B_D43
D
D
D
R_B_D48
D
R_B_D49
D
D
DR_B_DQS#6
D
R_B_DQS6
D
D
R_B_D50
D
D
D
R_B_D51
D
R_B_D56
D
D
DR_B_D57
D
D
R_B_D58
D
R_B_D59
D
10K_0402_5%~D
10K_0402_5%~D
+
0.75V_DDR_VTT
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
R
R
D
D
6
6
C
C
C
1
2
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
P
C
1
D
D
D
D
44
44
43
43
2
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
D
D
IMM2
IMM2
J
J
1
R
EF_DQ
V
3
VS
S
5
0
DQ
7
DQ
1
9
V
S
S
11
D
0
M
13
V
S
S
15
D
2
Q
17
D
3
Q
19
S
VS
21
8
DQ
23
D
9
Q
25
S
VS
27
D
S1#
Q
29
D
S1
Q
31
VS
S
33
D
10
Q
35
D
11
Q
37
V
S
S
39
D
16
Q
41
D
17
Q
43
V
S
S
45
D
S2#
Q
47
D
S2
Q
49
V
S
S
51
D
Q
18
53
D
Q
19
55
V
S
S
57
D
Q
24
59
D
Q
25
61
V
S
S
63
D
3
M
65
V
S
S
67
D
26
Q
69
D
Q
27
71
V
S
S
73
C
K
E0
75
V
D
D
7
7
N
C
79
B
2
A
81
V
D
D
83
A
2/BC#
1
8
5
A
9
87
V
D
D
8
9
A
8
9
1
A
5
93
V
D
D
5
9
A
3
9
7
A
1
99
V
D
D
101
C
K
0
103
C
K
0#
105
V
D
D
107
A
0/AP
1
109
B
A
0
111
V
D
D
113
W
E
#
115
C
S#
A
117
V
D
D
119
A
3
1
121
S
1
#
123
V
D
D
125
T
ST
E
127
V
S
S
129
D
32
Q
131
D
Q
33
133
V
S
S
135
D
S4#
Q
137
D
S4
Q
139
V
S
S
141
D
Q
34
143
D
Q
35
145
V
S
S
147
D
40
Q
149
D
41
Q
151
V
S
S
153
D
5
M
155
V
S
S
157
D
42
Q
159
D
Q
43
161
S
S
V
163
48
Q
D
165
49
Q
D
167
S
S
V
169
S6#
Q
D
171
Q
S6
D
173
S
S
V
175
Q
50
D
177
Q
51
D
179
S
S
V
181
Q
56
D
183
Q
57
D
185
S
S
V
187
M
7
D
189
S
S
V
191
Q
58
D
193
59
Q
D
195
S
S
V
197
A
0
S
199
DSPD
D
V
201
1
A
S
203
T
T
V
205
N
D1
G
TYCO_2-2013310-2~D
TYCO_2-2013310-2~D
CONN@
CONN@
2
VS
S
4
D
Q
4
6
D
5
Q
8
V
S
S
10
D
S0#
Q
12
D
S0
Q
14
V
S
S
16
D
Q
6
18
D
Q
7
20
V
S
S
22
D
12
Q
24
D
13
Q
26
V
S
S
28
D
M
1
30
R
E
SET#
32
V
S
S
34
D
Q
14
36
D
Q
15
38
V
S
S
40
D
20
Q
42
D
21
Q
44
V
SS
46
D
M
2
48
V
S
S
50
D
22
Q
52
D
23
Q
54
V
S
S
56
D
Q
28
58
D
Q
29
60
V
S
S
62
D
S3#
Q
64
D
S3
Q
66
V
S
S
68
D
Q
30
70
D
31
Q
72
V
S
S
74
C
K
E1
76
V
D
D
78
A
15
80
A
1
4
82
V
D
D
84
A
1
1
8
A
7
88
V
DD
9
A
6
9
A
4
94
V
D
D
9
A
2
9
A
0
100
V
D
D
102
C
K
1
104
C
K
1#
106
V
D
D
108
B
1
A
110
R
A
S#
112
V
D
D
114
S
#
0
116
O
T0
D
118
V
D
D
120
O
T1
D
1
N
C
124
V
D
D
126
V
EF_CA
R
128
V
S
S
130
D
Q36
132
D
37
Q
134
V
S
S
136
D
4
M
138
V
S
S
140
D
38
Q
142
D
39
Q
144
V
S
S
146
44
Q
D
148
Q
45
D
150
S
S
V
152
Q
S5#
D
154
Q
S5
D
156
S
S
V
158
Q
46
D
160
47
Q
D
162
S
S
V
164
52
Q
D
166
53
Q
D
168
S
S
V
170
6
M
D
172
S
S
V
174
54
Q
D
176
55
Q
D
178
S
S
V
180
Q
60
D
182
61
Q
D
184
S
S
V
186
Q
S7#
D
188
S7
Q
D
190
S
S
V
192
Q
62
D
194
63
Q
D
196
S
S
V
198
V
ENT#
E
200
A
D
S
202
L
C
S
204
T
T
V
206
N
D2
G
2
3A to 1 DIMMs/channel
2-
+
.5V_MEM
1
D
R_B_D4
D
D
D
R_B_D5
D
D
R_B_DQS#0
D
R_B_DQS0
D
D
DR_B_D6
D
D
R_B_D7
D
D
R_B_D12
D
D
R_B_D13
D
R3_DRAMRST#_R
D
D
D
R_B_D14
D
R_B_D15
D
D
R_B_D20
D
D
R_B_D21
D
D
R_B_D22
D
D
DR_B_D23
D
D
R_B_D28
D
D
R_B_D29
D
R_B_DQS#3
D
D
R_B_DQS3
D
D
D
R_B_D30
D
R_B_D31
D
D
D
R_CKE3_DIMMB
D
D
R_B_MA15
D
D
R_B_MA14
D
R_B_MA11
D
D
D
R_B_MA7
6
D
D
R_B_MA6
0
D
D
R_B_MA4
2
D
D
R_B_MA2
6
D
DR_B_MA0
8
M
CLK_DDR3
_
M
CLK_DDR#3
_
D
D
R_B_BS1
D
D
R_B_RAS#
D
DR_CS2_DIMMB#
M
_ODT2
M
_ODT3
22
D
R_B_D36
D
D
D
R_B_D37
D
R_B_D38
D
D
R_B_D39
D
D
R_B_D44
D
D
D
R_B_D45
D
R_B_DQS#5
D
D
R_B_DQS5
D
D
R_B_D46
D
D
DR_B_D47
D
D
R_B_D52
D
R_B_D53
D
D
D
R_B_D54
D
R_B_D55
D
D
R_B_D60
D
D
D
R_B_D61
D
D
R_B_DQS#7
D
R_B_DQS7
D
D
R_B_D62
D
D
R_B_D63
D
+
0
.75V_DDR_VTT
2
D
J
D
R3_DRAMRST#_R <12>
D
R_CKE3_DIMMB <8>
D
D
CLK_DDR3 <8>
_
M
CLK_DDR#3 <8>
_
M
R_B_BS1 <8>
D
D
R_B_RAS# <8>
D
D
D
R_CS2_DIMMB# <8>
D
ODT2 <8>
_
M
_
ODT3 <8>
M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
D
D
D
D
1
IMMB H=9.2
+
D
IMM2_VREF_CA
12
15 0_0402_5%~D@
D
D
15 0_0402_5%~D@
R
R
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
C
D
D
37
37
R_XDP_WAN_SM BDAT <7,12,14,15,27,34>
R_XDP_WAN_SM BCLK <7,12,14,15,27,34>
C
1
D
D
38
38
2
LL CONFIDENTIAL/PROPRIETARY
E
D
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
tle
tle
Title
i
i
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
RIII-SODIMM SLOT2
D
D
D
RIII-SODIMM SLOT2
RIII-SODIMM SLOT2
D
D
D
-7781
-7781
A
A
A
-7781
L
L
L
+
_DDR_REF
V
3 6
3 6
3 6
1
1
1
f
f
f
o
o
1
o
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
2
2
1
101
H
H
101
2
R
R
R
R
R
R
R
TC_CELL
+
1 2
H
H
29 33_0402_5%~D
29 33_0402_5%~D
R
R
1
R
R
H
H
26 33_0402_5%~D
26 33_0402_5%~D
1 2
27 33_0402_5%~D
27 33_0402_5%~D
H
H
R
R
1 2
H
H
25 33_0402_5%~D
25 33_0402_5%~D
R
R
R
R
H
H
1
35 47_0402_5%~D
35 47_0402_5%~D
9
9
1 2
94 33_0402_5%~D
8
8
94 33_0402_5%~D
1 2
98 0_0402_5%~D@
8
8
98 0_0402_5%~D@
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
o signal should be PU to the ALWAYS rail.
S
3
.3V_ALW_PCH
+
12
R
R
66
66
H
H
1K_0402_5%~D
1K_0402_5%~D
P
H_AZ_SYNC
C
12
282
@
282
@
H
H
R
R
100K_0402_5%~D
100K_0402_5%~D
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
1 2
H
H
22 20K_0402_5%~D
22 20K_0402_5%~D
R
R
1 2
R
R
23 20K_0402_5%~D
23 20K_0402_5%~D
H
H
1 2
R
R
11 1M_0402_5%~D
11 1M_0402_5%~D
H
H
1
1
@
@
C
C
C
C
OS place near DIMM
M
C
P
C
H_AZ_SDOUT
P
H_AZ_SYNC_Q
C
2
P
H_AZ_RST#
C
P
C
H_AZ_BITCLK
3
.3V_ALW_PCH
+
12
288
@
288
@
H
H
R
R
0_0603_5%~D
0_0603_5%~D
+
3
.3V_ALW_PCH_JTAG
C
H_AZ_SYNC_Q
P
1 2
31 1M_0402_5%~D
31 1M_0402_5%~D
TEL HDA_SYNC
N
I
isolation circuit
8
8
90
90
R
R
3.3K_0402_5%~D
3.3K_0402_5%~D
P
I_PCH_CS0#_R
S
2
S
PI_DIN64
S
I_WP#_SEL_R
P
2
M
M
OS1 SHORT PADS~D
OS1 SHORT PADS~D
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4
4
H
H
R
R
RH
RH
llow INTEL CRB 0.7
o
F
V_RUN
5
+
1
0 MIL SO8
0
2
4Mb Flash ROM
6
X76@
X76@
2
1
/
C
S
2
D
O
3
/
W
P
4
G
D
N
W25Q64CVSSIG_SO8~D
W25Q64CVSSIG_SO8~D
2
R
R
59 51_0402_1%~D
59 51_0402_1%~D
H
H
44 200_0402_1%~D
H
H
44 200_0402_1%~D
45 200_0402_1%~D
45 200_0402_1%~D
43 200_0402_1%~D
43 200_0402_1%~D
H
H
R
R
U
U
5
5
e
V
WINBOND
2
2
ndor
C
H_AZ_MDC_SDOUT<30>
P
S
S
G
G
2
V
/
H
OLD
C
D
M
OS_CLR1
C
h
S
p
O
ME_CLR1
Sh
Open
TC_CELL
R
+
D D
INTVRMEN- Integrated SUS
1.1V VRM Enable
i
gh - Enable Internal VRs
*
H
Low - Enable External VRs
C C
P
P
B B
P
S
A A
C
Clear CMOS
unt
en
K
TPM setting
Cl
unt
ear ME RTC Registers
Keep ME RTC Registers
12
38
38
RH
RH
330K_0402_1%~D
330K_0402_1%~D
P
H_INTVRMEN
C
1
R
R
H
H
39
@
39
@
330K_0402_1%~D
330K_0402_1%~D
2
1
1
@
@
M
M
E
E
1 SHORT PADS~D
1 SHORT PADS~D
1 2
5 1U_0402_6.3V6K~D
5 1U_0402_6.3V6K~D
H
H
C
C
C
H_AZ_CODEC_SDOUT<29>
C
H_AZ_CODEC_SYNC<29>
P
C
H_AZ_CODEC_RST#<29>
P
C
H_AZ_CODEC_BITCLK<29>
27P_0402_50V8J~D
27P_0402_50V8J~D
S
P
I_PCH_CS0#
S
I_PCH_DIN
P
S
I_WP#_SEL
P
I_WP#_SEL<39>
M
OS setting
e
ep CMOS
C
C
@
@
WINBOND
EON
MXIC
5
4
U
B_OC2#<17>
B_OC3#<17>
B_OC5#<17>
B_OC6#<17>
2
2
H
H
C
C
15P_0402_50V8J~D
15P_0402_50V8J~D
12
C
C
H
H
3
3
15P_0402_50V8J~D
15P_0402_50V8J~D
12
@
@
H_AZ_MDC_BITCLK<30>
C
P
C
H_AZ_MDC_SYNC<30>
P
H_AZ_MDC_RST#<30>
C
P
H_AZ_CODEC_SDIN0< 29>
C
H_AZ_MDC_SDIN1<30>
P
_FWP<39>
P
CH_AZ_SYNC
P
I_CLK64
1 2
99 33_0402_5%~D
99 33_0402_5%~D
8
8
R
R
I_DO64
P
1 2
01 33_0402_5%~D
9
9
01 33_0402_5%~D
R
R
o
.
N
SB_OC0#_R
US
B_OC1#_R
US
B_OC2#
US
B_OC3#
U
S
B_OC4#_R
U
B_OC5#
S
U
B_OC6#
S
S
O_EXT_SMI#
I
S
L
P_ME_CSW_DEV#
U
S
B_MCARD1_DET#
H_GPIO36
C
P
C
H_GPIO37
P
P
H_GPIO16
C
T
EMP_ALERT#
P
C
H_GPIO15
S
I
O_EXT_SCI#_R
12
P
2
C
C
H
H
100
100
27P_0402_50V8J~D
27P_0402_50V8J~D
KR<29>
P
S
3
.3V_ALW_PCH
+
12
48
48
H
H
R
R
@
@
1
91
91
8
8
R
R
3.3K_0402_5%~D
3.3K_0402_5%~D
2
A
000039A2L
S
B_OC0#_R<17>
S
U
B_OC1#_R<17>
S
U
S
U
S
U
B_OC4#_R<17>
US
S
U
S
U
I
O_EXT_SMI#<17,40>
S
P_ME_CSW_DEV#<18,39>
L
S
B_MCARD1_DET#<18,34>
S
U
C
H_GPIO36<18>
P
C
H_GPIO37<18>
P
C
H_GPIO16<18>
P
E
MP_ALERT#<18,39>
T
C
H_GPIO15<18>
P
I
O_EXT_SCI#_R<18>
S
H_RSMRST#_Q<16,41>
C
P
C
P
E
M
12
12
12
12
D
D
13
Q
7
QH
H
7
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
3
.3V_SPI
+
8
C
C
7
S
6
K
L
S
5
O
I
76@ configuration for ROM part
X
7
640631L01 SA000039A1L
X
X7640631L02
X7640631L03 SA000046400
X7640631L04 SA00004G600
4
RH
H
H
R
R
H
H
R
R
RH
RH
R
R
H
H
R
R
H
H
H
H
R
R
R
R
H
H
D
D_DET#_R
B
S_BIT0_R
B
Y
Y
H
H
1
1
32.768KHZ_12.5PF_Q13FC1350000~D
32.768KHZ_12.5PF_Q13FC1350000~D
H_RTCX2_R
C
1
12
49
49
H
H
R
R
@
@
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
46
46
7
7
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
P
I_HOLD#
S
S
P
I_PCH_CLK
S
I_PCH_DO
P
2
5
U
H
RH
RH
H
H
R
R
RH
R
R
H
H
H
H
R
R
R
R
H
H
R
R
H
H
R
R
H
H
R
R
H
H
H
H
R
R
1 2
R
R
H
H
286 0_0402_5%~D@
286 0_0402_5%~D@
1 2
R
R
32 33_0402_5%~D
32 33_0402_5%~D
H
H
1 2
33 33_0402_5%~D
33 33_0402_5%~D
H
H
R
R
1 2
R
R
34 33_0402_5%~D
34 33_0402_5%~D
H
H
1 2
R
R
H
H
287 1K_0402_5%~D@
287 1K_0402_5%~D@
1 2
H
H
36 33_0402_5%~D
36 33_0402_5%~D
R
R
1 2
H
H
50 1K_0402_5%~D
50 1K_0402_5%~D
R
R
S
B30_SMI#<28>
U
12
47
47
H
H
R
R
@
@
100_0402_1%~D
100_0402_1%~D
SA00003K80L
00003K80L
A
S
SA00004LI00
SA000041P00
1 33_0402_5%~DPXDP@RH1 33_0402_5%~DPXDP@
3 33_0402_5%~DPXDP@
3 33_0402_5%~DPXDP@
4 33_0402_5%~DPXDP@
4 33_0402_5%~DPXDP@
5 33_0402_5%~DPXDP@RH5 33_0402_5%~DPXDP@
6 33_0402_5%~DPXDP@RH6 33_0402_5%~DPXDP@
7 33_0402_5%~DPXDP@
7 33_0402_5%~DPXDP@
8 33_0402_5%~DPXDP@
8 33_0402_5%~DPXDP@
9 33_0402_5%~DPXDP@
9 33_0402_5%~DPXDP@
10 33_0402_5%~DPXDP@
10 33_0402_5%~DPXDP@
12 33_0402_5%~DPXDP@
12 33_0402_5%~DPXDP@
13 33_0402_5%~DPXDP@
13 33_0402_5%~DPXDP@
14 33_0402_5%~DPXDP@RH14 33_0402_5%~DPXDP@
15 33_0402_5%~DPXDP@
15 33_0402_5%~DPXDP@
16 33_0402_5%~DPXDP@
16 33_0402_5%~DPXDP@
17 33_0402_5%~DPXDP@
17 33_0402_5%~DPXDP@
18 33_0402_5%~DPXDP@
18 33_0402_5%~DPXDP@
19 33_0402_5%~DPXDP@
19 33_0402_5%~DPXDP@
20 33_0402_5%~DPXDP@
20 33_0402_5%~DPXDP@
24 1K_0402_5%~DPXDP@
24 1K_0402_5%~DPXDP@
P
C
5
U
H_RTCX1
P
3
1 2
1 2
1 2
1 2
1
1 2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
1 2
1
1 2
1 2
C
12
H_AZ_SYNC_Q
PI_PCH_CS1#
S
P
I_PCH_DIN
S
I_WP#_SEL_R
P
S
3
X
D
P_FN0
XD
P_FN1
XD
P_FN2
X
P_FN3
D
X
P_FN4
2
2
2
2
R
R
R
H
H
2
2
10M_0402_5%~D
10M_0402_5%~D
P
P
S
I
N
P
P
P
P
P
P
U
P
P
P
P
P
P
P
P
P
R
R
R
R
D
X
P_FN5
D
X
D
P_FN6
X
D
P_FN7
X
P_FN8
D
X
DP_FN9
X
D
P_FN10
X
D
P_FN11
X
D
P_FN12
X
P_FN13
D
X
P_FN14
D
X
P_FN15
D
X
D
P_FN16
X
D
P_FN17
MRST#_XDP
S
R_XDP_WAN_SMBDAT<7,12,13,15,27,34>
D
D
R_XDP_WAN_SMBCLK<7,12,13,15,27,34>
D
D
U
U
C
H_RTCX2
H_RTCRST#
C
R
TCRST#
TRUDER#
C
H_INTVRMEN
C
H_AZ_BITCLK
H_AZ_RST#
C
H_AZ_CODEC_SDIN0
C
H_AZ_MDC_SDIN1
C
C
H_AZ_SDOUT
P
C
H_GPIO33
B30_SMI#
S
C
H_JTAG_TCK
H_JTAG_TMS
C
C
H_JTAG_TDI
C
H_JTAG_TDO
H_SPI_CLK
C
H_SPI_CS0#
C
C
H_SPI_CS1#
H_SPI_DO
C
C
H_SPI_DIN
1 2
36 47_0402_5%~D
36 47_0402_5%~D
9
9
1 2
8
8
95 33_0402_5%~D
95 33_0402_5%~D
A20
C20
D20
G22
K22
C17
N34
P
H_AZ_SYNC
C
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
PI_PCH_CS1#_R
S
P
I_DIN32
S
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
P
3
.3V_ALW_PCH
3
+
1
PXDP@
PXDP@
CH
CH
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
R
R
283 1K_0402_5%~DPXDP@
283 1K_0402_5%~DPXDP@
H
H
05V_0.8V_PWROK<40,51>
.
1
I
O_PWRBTN#_R<7,16>
S
H
H
4A
4A
R
CX1
T
R
CX2
T
R
CRST#
T
S
R
TCRST#
I
TRUDER#
N
I
TVRMEN
N
H
D
A_BCLK
H
D
A_SYNC
S
KR
P
H
A_RST#
D
H
D
A_SDIN0
H
D
A_SDIN1
H
A_SDIN2
D
H
A_SDIN3
D
H
D
A_SDO
H
A_DOCK_E N# / GPIO33
D
H
A_DOCK_R ST# / GPIO13
D
J
AG_TCK
T
J
T
AG_TMS
J
AG_TDI
T
J
T
AG_TDO
S
I_CLK
P
S
I_CS0#
P
S
I_CS1#
P
S
P
I_MOSI
S
P
I_MISO
BS_BIT0 - BIOS BOOT STRAP BIT 0
B
00 MIL SO8
2
2Mb Flash ROM
3
X76@
X76@
1
2
3
4
W25Q32BVSSIG_SO8~D
W25Q32BVSSIG_SO8~D
1 2
1 2
21 0_0402_5%~DPXDP@
21 0_0402_5%~DPXDP@
H
H
R
R
H
H
284 0_0402_5%~DPXDP@
284 0_0402_5%~DPXDP@
R
R
1 2
1 2
H285 0_0402_5%~DPXDP@RH285 0_0402_5%~DPXDP@
R
C
C
T
T
R
R
DA
DA
H
H
I
I
TAG
TAG
J
J
PI
PI
S
S
S
S
U
3
U5
5
3
8
C
V
#
S
C
C
7
H
D
LD#
O
O
6
C
W
K
P
L
#
5
D
G
N
I
D
1
.
05V_0.8V_PWROK_R
P
C
D
D
R_XDP_WAN_SMBDAT_R2
D
D
R_XDP_WAN_SMBCLK_R2
F
W
H0 / LAD0
F
W
H1 / LAD1
F
W
H2 / LAD2
F
H3 / LAD3
W
PC
PC
L
L
F
H4 / LFRAM E#
W
L
D
RQ0#
L
D
RQ1# / GP IO23
S
E
RIRQ
S
A
TA0RXN
S
A
TA0RXP
S
TA0TXN
A
S
TA0TXP
A
S
A
TA1RXN
ATA 6G
ATA 6G
S
A
TA1RXP
S
S
S
TA1TXN
A
S
TA1TXP
A
S
A
TA2RXN
S
A
TA2RXP
S
TA2TXN
A
S
TA2TXP
A
S
A
TA3RXN
S
A
TA3RXP
S
TA3TXN
A
S
TA3TXP
A
S
A
TA4RXN
S
A
TA4RXP
S
TA4TXN
A
S
TA4TXP
A
SATA
SATA
S
A
TA5RXN
S
A
TA5RXP
S
TA5TXN
A
S
A
TA5TXP
S
TAICOMPO
A
S
TAICOMPI
A
S
TA3RCOMPO
A
S
A
TA3COMPI
S
TA3RBIAS
A
S
ATALED#
TA0GP / GP IO21
A
A
TA1GP / GP IO19
3.3V_SPI
+
P
I_CLK32
S
P
I_DO32
S
X
D
X
D
X
D
X
D
X
DP_FN4
X
D
X
D
X
D
H_PWRBTN#_XDP
P
H_JTAG_TCK
C
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
1 2
8
8
R
R
1 2
9
9
R
R
2
.3V_ALW_PCH
+3
P_FN0
P_FN1
P_FN2
P_FN3
P_FN5
P_FN6
P_FN7
L
P
C_LAD0
L
P
C_LAD1
L
P
C_LAD2
L
C_LAD3
P
L
P
C_LFRAME#
L
P
C_LDRQ1#
I
R
Q_SERIRQ
S
TA_COMP
A
S
TA3_COMP
A
R
B
IAS_SATA3
S
A
TA_ACT#
H
D
D_DET#_R
B
B
S_BIT0_R
H_PLTRST#<7,17>
C
P
45
7
7
45
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
I_HOLD#
P
S
P
I_PCH_CLK
S
97 33_0402_5%~D
97 33_0402_5%~D
I_PCH_DO
P
S
00 33_0402_5%~D
00 33_0402_5%~D
2
J
J
X
X
DP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
DP2
GN
D0
O
SFN_A0
B
O
SFN_A1
B
G
N
D2
O
B
SDATA_A0
O
B
SDATA_A1
G
D4
N
O
SDATA_A2
B
O
SDATA_A3
B
D6
N
G
SFN_B0
B
O
SFN_B1
B
O
N
D8
G
B
SDATA_B0
O
B
SDATA_B1
O
ND10
G
SDATA_B2
B
O
SDATA_B3
B
O
D12
N
G
W
RGOOD/HOO K0
P
O
OK1
H
C
C_OBS_A B
V
O
OK2
H
O
OK3
H
N
D14
G
D
A
S
L
C
S
K1
C
T
K0
C
T
D16
N
G
SAMTE_BSH-030-01-L-D-A C ONN@
SAMTE_BSH-030-01-L-D-A C ONN@
C_LAD0 <32,34,39,40>
P
L
C_LAD1 <32,34,39,40>
P
L
PC_LAD2 <32,34,39,40>
L
C_LAD3 <32,34,39,40>
P
L
C_LFRAME# <32,34,39,40>
P
L
C_LDRQ1# <39>
P
L
R
Q_SERIRQ <32,39,40>
I
ATA_PRX_DTX_N0_C <27>
S
P
ATA_PRX_DTX_P0_C <27>
S
P
ATA_PTX_DRX_N0_C <27>
S
P
ATA_PTX_DRX_P0_C <27>
S
P
A
TA_ODD_PRX_DTX_N1_C <28>
S
A
TA_ODD_PRX_DTX_P1_C <28>
S
TA_ODD_PTX_DRX_N1_C <28>
A
S
TA_ODD_PTX_DRX_P1_C <28>
A
S
ATA_PRX_DTX_N4_C <37>
S
E
ATA_PRX_DTX_P4_C <37>
S
E
S
ATA_PTX_DRX_N4_C <37>
E
S
ATA_PTX_DRX_P4_C <37>
E
TA_PRX_DKTX_N5_C <38>
A
S
TA_PRX_DKTX_P5_C <38>
A
S
TA_PTX_DKRX_N5_C <38>
A
S
TA_PTX_DKRX_P5_C <38>
A
S
1 2
R
R
40 37.4_0402_1%~D
H
H
40 37.4_0402_1%~D
1 2
R
R
H
H
42 49.9_0402_1%~D
42 49.9_0402_1%~D
1 2
R
R
46 750_0402_1%~D
46 750_0402_1%~D
H
H
TA_ACT# <43>
A
S
1 2
290 0_0402_5%~D@
290 0_0402_5%~D@
H
H
R
R
D
S
D
S
1 3
Q
Q
1 BSS138W-7-F_SOT323-3~D
H
H
1 BSS138W-7-F_SOT323-3~D
G
G
2
J
J
PI1
S
S
PI1
1
1
1
1
1
1
1
G
G
HRS_FH12-16S-0P5SH(55)~D
HRS_FH12-16S-0P5SH(55)~D
CONN@
CONN@
1
2
D1
N
G
SFN_C0
OB
B
SFN_C1
O
G
B
SDATA_C0
O
SDATA_C1
B
O
G
SDATA_C2
B
O
B
SDATA_C3
O
G
B
SFN_D0
O
B
SFN_D1
O
G
SDATA_D0
B
O
SDATA_D1
B
O
G
SDATA_D2
B
O
B
SDATA_D3
O
G
T
PCLK/HOO K4
I
T
PCLK#/HO OK5
I
C
C_OBS_CD
V
E
SET#/HOOK 6
R
B
R#/HOOK7
D
G
T
G
1
.05V_RUN
+
.05V_RUN
1
+
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0
1
0
1
1
1
1
2
2
3
1
3
4
1
4
1
5
5
1
6
6
7
1
1
1
8
2
LL CONFIDENTIAL/PROPRIETARY
E
D
tle
Title
i
itle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
XDP_FN16
4
XD
6
8
N
D3
X
10
X
12
14
D5
N
X
16
X
18
20
N
D7
22
24
26
N
D9
X
28
X
30
32
D11
N
X
34
X
36
38
N
D13
40
42
44
R
46
X
48
50
N
D15
P
52
D
0
T
54
R
ST#
P
56
D
I
T
P
58
S
M
T
60
D17
N
HDD
D
D/ E Module Bay
O
-
SATA
E
O
CK
D
.3V_RUN
3
+
H_SATA_MOD_EN# <40>
C
P
S
I_PCH_CS1#
P
P
C
H_SPI_CS1#
R
R
S
P
I_PCH_DO
P
H_SPI_DO
C
R
R
S
P
I_PCH_DIN
P
H_SPI_DIN
C
R
R
S
I_PCH_CLK
P
P
R
R
CH_SPI_CLK
S
P
I_PCH_CS0#
P
H_SPI_CS0#
C
R
R
R
R
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
C
L
L
L
P_FN17
D
P_FN8
D
P_FN9
P_FN10
D
P_FN11
D
D
P_FN12
D
P_FN13
P_FN14
D
P_FN15
D
.3V_ALW_PCH
3
+
MRST#_XDP
S
P_DBRESET#
D
C
H_JTAG_TDO
C
H_JTAG_TDI
C
H_JTAG_TMS
P
B
12
345 0_0402_5%~D
345 0_0402_5%~D
H
H
346 0_0402_5%~D
346 0_0402_5%~D
H
H
347 0_0402_5%~D
347 0_0402_5%~D
H
H
348 0_0402_5%~D
H
H
348 0_0402_5%~D
H
H
349 0_0402_5%~D
349 0_0402_5%~D
.3V_M
3
+
H
H
350 0_0402_5%~D
350 0_0402_5%~D
C
C
C
P
P
P
-7781
A
A
A
-7781
-7781
CH_GPIO33
H
H
R
R
I
Q_SERIRQ
R
R
R
H
H
S_BIT0_R
B
NTEL feedback 0302
I
S
P
KR
o
N
SPKR
H
H
30
30
R
R
10K_0402_5%~D
10K_0402_5%~D
1 2
1 2
1 2
1 2
1
1 2
H (1/8)
H (1/8)
H (1/8)
1
P_DBRESET# <7,16>
D
X
355 100K_0402_5%~D
355 100K_0402_5%~D
28 8.2K_0402_5%~D
28 8.2K_0402_5%~D
R
R
H
H
52 4.7K_0402_5%~D
52 4.7K_0402_5%~D
H
H
35 10K_0402_5%~D@
35 10K_0402_5%~D@
R
R
Reboot Strap
w = Default
o
L
High = No Reboot
D_DET# <27>
D
H
2
1
1
1
12
12
12
3
+
12
3
.3V_SPI
+
4 6
4 6
4 6
f
f
f
o
o
o
+
3
.3V_RUN
.3V_RUN
.
.
.
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
0
0
0
5
D D
P
C
IE_PRX_WANTX_N1<34>
P
IE_PRX_WANTX_P1<34>
P
P
P
P
P
P
P
P
P
P
IE_PRX_WLANTX_N2<34>
C
C
IE_PRX_WLANTX_P2<34>
C
IE_PTX_WLANRX_N2<34>
IE_PTX_WLANRX_P2<34>
C
P
P
P
P
P
P
P
P
IE_PRX_WPANTX_N5<34>
C
IE_PRX_WPANTX_P5<34>
C
C
IE_PTX_WPANRX_N5<34>
C
IE_PTX_WPANRX_P5<34>
P
P
P
P
P
P
P
P
C
C
IE_PTX_WANRX_N1<34>
IE_PTX_WANRX_P1<34>
C
C
IE_PRX_EXPTX_N3<35>
C
IE_PRX_EXPTX_P3<35>
C
IE_PTX_EXPRX_N3<35>
IE_PTX_EXPRX_P3<35>
C
IE_PRX_EMBTX_N4<28>
C
IE_PRX_EMBTX_P4<28>
C
IE_PTX_EMBRX_N4<28>
C
C
IE_PTX_EMBRX_P4<28>
C
IE_PRX_MMITX_N6<33>
C
IE_PRX_MMITX_P6<33>
IE_PTX_MMIRX_N6<33>
C
IE_PTX_MMIRX_P6<33>
C
C
IE_PRX_GLANTX_N7<31>
IE_PRX_GLANTX_P7<31>
C
IE_PTX_GLANRX_N7<31>
C
IE_PTX_GLANRX_P7<31>
C
C
C
+
C
+
C
+
K_PCIE_MINI1#<34 >
L
K_PCIE_MINI1<34>
L
3
.3V_ALW_PCH
I
NI1CLK_REQ#<34>
M
K_PCIE_LAN#<31>
L
C
K_PCIE_LAN<31>
L
C
A
NCLK_REQ#<31>
L
K_PCIE_MMI#<33>
L
C
K_PCIE_MMI<33>
L
C
+
3
.3V_RUN
ICLK_REQ#<33>
M
M
K_PCIE_MINI3#<34>
L
L
K_PCIE_MINI3<34>
C
+
3.3V_ALW_PCH
NI3CLK_REQ#<34>
I
M
L
K_PCIE_EXP#<35>
C
K_PCIE_EXP<35>
L
C
+
.3V_ALW_PCH
3
PCLK_REQ#<35>
X
E
L
K_PCIE_MINI2#<34 >
C
K_PCIE_MINI2<34>
L
C
3
.3V_ALW_PCH
NI2CLK_REQ#<34>
I
M
+
.3V_ALW_PCH
3
L
K_PCIE_EMB#<28>
K_PCIE_EMB<28>
L
C
.3V_ALW_PCH
3
BCLK_REQ#<28>
M
E
L
K_CPU_ITP#<7>
C
K_CPU_ITP<7>
L
C
H
H
307 0_0402_5%~D@
307 0_0402_5%~D@
R
R
308 0_0402_5%~D@
H
H
308 0_0402_5%~D@
R
R
81 10K_0402_5%~D
H
H
81 10K_0402_5%~D
R
R
R
R
82 0_0402_5%~D@
H
H
82 0_0402_5%~D@
83 0_0402_5%~D@
83 0_0402_5%~D@
H
H
R
R
85 0_0402_5%~D@
H
H
85 0_0402_5%~D@
R
R
H
H
86 0_0402_5%~D@
86 0_0402_5%~D@
R
R
R
R
87 10K_0402_5%~D
87 10K_0402_5%~D
H
H
H88 0_0402_5%~D@RH88 0_0402_5%~D@
R
R
R
90 0_0402_5%~D@
90 0_0402_5%~D@
H
H
R
R
H
152 10K_0402_5%~D
152 10K_0402_5%~D
H
H
H
92 0_0402_5%~D@
92 0_0402_5%~D@
R
R
93 0_0402_5%~D@
93 0_0402_5%~D@
H
H
R
R
94 10K_0402_5%~D
94 10K_0402_5%~D
RH
RH
95 0_0402_5%~D@
95 0_0402_5%~D@
H
H
R
R
96 0_0402_5%~D@
96 0_0402_5%~D@
H
H
R
R
97 10K_0402_5%~D
97 10K_0402_5%~D
H
H
R
R
H
98 10K_0402_5%~D
98 10K_0402_5%~D
H
R
R
310 0_0402_5%~D@
310 0_0402_5%~D@
H
H
R
R
H
H
312 0_0402_5%~D@
312 0_0402_5%~D@
R
R
104 10K_0402_5%~D
H
H
104 10K_0402_5%~D
R
R
280 0_0402_5%~D@
H
H
280 0_0402_5%~D@
R
R
281 0_0402_5%~D@
H
H
281 0_0402_5%~D@
R
R
AN (Mini Card 1)--->
W
W
WLAN (Mini Card 2)--->
PRESS Card--->
X
E
3
Module Bay--->
E
2 MINI CARD-3 PCIE
/
1
(Mini Card 3)--->
M
I --->
C C
0
1
W
AN (Mini Card 1)--->
W
P
B B
P
M
/100/1G LAN --->
0
/100/1G LAN --->
1
M
I--->
M
(Mini Card 3)--->
press card--->
x
E
WLAN (Mini Card 2)--->
eModule Bay--->
A A
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
5
1 2
2
1 2
4
12
12
12
12
12
12
12
12
12
12
1
12
12
12
12
12
12
12
12
12
12
4
P
C
IE_PRX_WANTX_N1
P
C
IE_PRX_WANTX_P1
P
IE_PTX_WANRX_N1
C
P
IE_PTX_WANRX_P1
C
P
IE_PRX_WLANTX_N2
C
P
IE_PRX_WLANTX_P2
C
P
IE_PTX_WLANRX_N2
C
P
C
IE_PTX_WLANRX_P2
P
IE_PRX_EXPTX_N3
C
P
IE_PRX_EXPTX_P3
C
P
IE_PTX_EXPRX_N3
C
P
IE_PTX_EXPRX_P3
C
P
C
IE_PRX_EMBTX_N4
P
C
IE_PRX_EMBTX_P4
P
IE_PTX_EMBRX_N4
C
P
IE_PTX_EMBRX_P4
C
P
IE_PRX_WPANTX_N5
C
P
IE_PRX_WPANTX_P5
C
P
IE_PTX_WPANRX_N5
C
P
C
IE_PTX_WPANRX_P5
P
IE_PRX_MMITX_N6
C
P
C
IE_PRX_MMITX_P6
P
IE_PTX_MMIRX_N6
C
P
CIE_PTX_MMIRX_P6
P
IE_PRX_GLANTX_N7
C
P
C
IE_PRX_GLANTX_P7
P
C
IE_PTX_GLANRX_N7
P
IE_PTX_GLANRX_P7
C
P
C
IE_MINI1#
P
IE_MINI1
C
M
NI1CLK_REQ#
I
P
IE_LAN#
C
P
IE_LAN
C
L
A
NCLK_REQ#
P
C
IE_MMI#
P
IE_MMI
C
M
ICLK_REQ#
M
P
IE_MINI3#
C
P
IE_MINI3
C
M
NI3CLK_REQ#
I
P
IE_EXP#
C
P
C
IE_EXP
E
PCLK_REQ#
X
P
IE_MINI2#
C
P
IE_MINI2
C
M
NI2CLK_REQ#
I
P
E
G_B_CLKRQ#
P
IE_EMB#
C
P
C
IE_EMB
E
BCLK_REQ#
M
C
L
K_BCLK_ITP#
C
L
K_BCLK_ITP
U
U
H
H
4B
4B
BG34
P
E
RN1
BJ34
P
E
RP1
AV32
P
TN1
E
AU32
P
TP1
E
BE34
P
E
RN2
BF34
P
E
RP2
BB32
P
E
TN2
AY32
P
E
TP2
BG36
P
RN3
E
BJ36
P
RP3
E
AV34
P
E
TN3
AU34
P
E
TP3
BF36
P
RN4
E
BE36
P
E
RP4
AY34
P
TN4
E
BB34
P
E
TP4
BG37
P
E
RN5
BH37
P
RP5
E
AY36
P
TN5
E
BB36
P
TP5
E
BJ38
P
RN6
E
BG38
P
RP6
E
AU36
P
TN6
E
AV36
P
E
TP6
BG40
P
E
RN7
BJ40
P
E
RP7
AY40
P
TN7
E
BB40
P
TP7
E
BE38
P
RN8
E
BC38
P
RP8
E
AW38
P
E
TN8
AY38
P
E
TP8
Y40
C
KOUT_PCIE0N
L
Y39
C
L
KOUT_PCIE0P
J2
P
IECLKRQ0# / GPIO73
C
AB49
C
KOUT_PCIE1N
L
AB47
C
KOUT_PCIE1P
L
M1
P
IECLKRQ1# / GPIO18
C
AA48
C
L
KOUT_PCIE2N
AA47
C
L
KOUT_PCIE2P
V10
P
IECLKRQ2# / GPIO20
C
Y37
C
LKOUT_PCIE3N
Y36
C
L
KOUT_PCIE3P
A8
P
C
IECLKRQ3# / GPIO25
Y43
C
LKOUT_PCIE4N
Y45
C
L
KOUT_PCIE4P
L12
P
IECLKRQ4# / GPIO26
C
V45
C
L
KOUT_PCIE5N
V46
C
L
KOUT_PCIE5P
L14
P
C
IECLKRQ5# / GPIO44
AB42
C
L
KOUT_PEG_B_N
AB40
C
L
KOUT_PEG_B_P
E6
P
E
G_B_CLKRQ# / GPIO56
V40
C
KOUT_PCIE6N
L
V42
C
L
KOUT_PCIE6P
T13
P
C
IECLKRQ6# / GPIO45
V38
C
L
KOUT_PCIE7N
V37
C
KOUT_PCIE7P
L
K12
P
C
IECLKRQ7# / GPIO46
AK14
C
L
KOUT_ITPXDP_N
AK13
C
KOUT_ITPXDP_P
L
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
3
P
H_SMB_ALERT#
C
S
M
S
BDATA
M
S
L0CLK
M
S
M
L0DATA
C
L
_CLK1
C
_DATA1
L
C
L
_RST1#
KIN_DMI_N
KIN_DMI_P
L
FCLK14IN
E
X
T
AL25_IN
T
AL25_OUT
BCLK
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
M
E
M_SMBCLK
M
M_SMBDATA
E
D
D
R_HVREF_RST_PCH
L
A
N_SMBCLK
L
N_SMBDATA
A
P
C
H_GPIO74
S
L1_SMBCLK
M
S
L1_SMBDATA
M
P
CH_CL_CLK1
P
C
H_CL_DATA1
P
C
H_CL_RST1#
P
E
G_A_CLKRQ#
C
K_CPU_DMI#
L
C
K_CPU_DMI
L
C
L
K_BUF_DMI#
C
K_BUF_DMI
L
C
L
K_BUF_BCLK
C
L
K_BUF_BCLK
C
K_BUF_DOT96#
L
C
LK_BUF_DOT96
C
K_BUF_CKSSCD#
L
C
K_BUF_CKSSCD
L
C
L
K_PCH_14M
C
L
K_PCI_LOOPBACK
X
T
AL25_IN
X
T
AL25_OUT
X
C
LK_RCOMP
P
I_TPM_TCM
C
S
I
O_14M
C
LK_80H
J
TWAY_14M
E
S
BALERT# / GPIO11
M
S
M
L0ALERT# / GPIO60
MBUSController
MBUSController
S
S
S
L1ALERT# / PCHHOT# / GPIO74
M
S
M
L1CLK / GPIO58
S
L1DATA / GPIO75
M
CI-E*
CI-E*
P
P
Link
Link
P
E
G_A_CLKRQ# / GPIO47
C
L
KOUT_PEG_A_N
C
KOUT_PEG_A_P
L
C
L
KOUT_DMI_N
C
L
LOCKS
LOCKS
C
C
LEX CLOCKS
LEX CLOCKS
F
F
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
ARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P
3
KOUT_DMI_P
C
KOUT_DP_N
L
C
KOUT_DP_P
L
C
L
C
C
KIN_GND1_N
L
C
L
KIN_GND1_P
C
KIN_DOT_96N
L
C
L
KIN_DOT_96P
C
L
KIN_SATA_N
C
KIN_SATA_P
L
R
C
L
KIN_PCILOOPBACK
X
X
CLK_RCOMP
C
L
KOUTFLEX0 / GPIO64
C
L
KOUTFLEX1 / GPIO65
C
L
KOUTFLEX2 / GPIO66
C
KOUTFLEX3 / GPIO67
L
2
M
E
M_SMBCLK
ME
M_SMBDATA
R_HVREF_RST_PCH <7>
D
D
A
N_SMBCLK <31>
L
N_SMBDATA <31>
A
L
M
L1_SMBCLK <40>
S
S
ML1_SMBDATA <40>
P
C
H_CL_CLK1 <34>
P
H_CL_DATA1 <34>
C
P
C
H_CL_RST1# <34>
L
K_CPU_DMI# <7>
C
L
K_CPU_DMI <7>
C
K_PCI_LOOPBACK <17>
L
C
1 2
R
R
H
H
100 90.9_0402_1 %~D
100 90.9_0402_1 %~D
311 22_0402_5%~D1@
H
H
311 22_0402_5%~D1@
R
R
313 22_0402_5%~D
313 22_0402_5%~D
H
H
R
R
314 22_0402_5%~D
314 22_0402_5%~D
H
H
R
R
R
R
315 22_0402_5%~D@
315 22_0402_5%~D@
H
H
12
12
12
12
2
+
3
.3V_RUN
H
H
5A
5A
Q
Q
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
4
3
H
H
5B
5B
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
S
L1_SMBCLK
M
S
L1_SMBDATA
M
D
D
R_HVREF_RST_PCH
P
H_GPIO74
C
M
M_SMBCLK
E
M
E
M_SMBDATA
P
C
H_SMB_ALERT#
P
G_A_CLKRQ#
E
L
N_SMBCLK
A
L
N_SMBDATA
A
C
LK_BUF_DMI#
C
L
K_BUF_DMI
C
K_BUF_BCLK
L
C
K_BUF_DOT96#
L
C
L
K_BUF_DOT96
C
K_BUF_CKSSCD#
L
C
L
K_BUF_CKSSCD
C
L
K_PCH_14M
LOCK TERMINATION for FCIM and need close to PCH
C
+
.05V_RUN
1
K_PCI_TPM_TCM <32>
L
C
L
K_SIO_14M <39>
C
LK_80H <34>
C
P
E
TWAY_CLK14M <32>
J
LL CONFIDENTIAL/PROPRIETARY
E
D
tle
i
i
Title
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
D
D
RH
RH
H
H
R
R
H
R
R
H
H
H
R
R
R
R
H
H
H
H
R
R
H
H
R
R
R
R
H
H
H
H
R
R
H
H
R
R
H
H
R
R
H
H
R
R
H
H
R
R
RH
RH
H
H
R
R
H78 10K_0402_5%~D
H
R
R
H
H
R
R
R
R
H
H
12
99
99
H
H
R
R
1M_0402_5%~D
1M_0402_5%~D
25MHZ_10PF_Q22FA2380049900~D
25MHZ_10PF_Q22FA2380049900~D
2
18
18
H
H
C
C
1
8.2P_0402_50V8D~D
8.2P_0402_50V8D~D
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
P
P
P
L
L
L
1
R_XDP_WAN_SM BCLK <7,12,13,14,27,34>
D
R_XDP_WAN_SM BDAT <7,12,13,14,27,34>
D
+
3
.3V_ALW_PCH
1 2
298 2.2K_0402 _5%~D
298 2.2K_0402 _5%~D
1 2
299 2.2K_0402 _5%~D
299 2.2K_0402 _5%~D
300 1K_ 0402_5%~D
300 1K_ 0402_5%~D
301 10K _0402_5%~D
301 10K _0402_5%~D
302 2.2K_0402 _5%~D
302 2.2K_0402 _5%~D
303 2.2K_0402 _5%~D
303 2.2K_0402 _5%~D
304 10K _0402_5%~D
304 10K _0402_5%~D
80 10K_0402_5%~D
80 10K_0402_5%~D
305 2.2K_0402 _5%~D
305 2.2K_0402 _5%~D
306 2.2K_0402 _5%~D
306 2.2K_0402 _5%~D
1
74 10K_0402_5%~D
74 10K_0402_5%~D
1 2
75 10K_0402_5%~D
75 10K_0402_5%~D
1
91 10K_0402_5%~D
91 10K_0402_5%~D
1
76 10K_0402_5%~D
76 10K_0402_5%~D
1 2
77 10K_0402_5%~D
77 10K_0402_5%~D
1 2
78 10K_0402_5%~D
1 2
79 10K_0402_5%~D
79 10K_0402_5%~D
1 2
183 10K_0402_5%~D
183 10K_0402_5%~D
H
H
309 0_0402_5%~D@
309 0_0402_5%~D@
R
R
3
4
C
C
C
H (2/8)
H (2/8)
H (2/8)
-7781
-7781
A
A
A
-7781
+
.3V_ALW_PCH
3
12
12
12
12
12
12
+
3
.3V_LAN
12
12
2
2
2
2
1
H
H
2
2
Y
Y
1
N
U
T
I
O
2
D
D
N
N
G
G
1
2
1
5 6
5 6
5 6
1
1
1
f
f
f
o
o
o
19
19
H
H
C
C
8.2P_0402_50V8D~D
8.2P_0402_50V8D~D
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+
.3V_ALW_PCH
3
S
U
1 2
R
R
318 10K_0402_5%~D@
318 10K_0402_5%~D@
H
H
1 2
RH
RH
144 10K_0402_5%~D
144 10K_0402_5%~D
D D
+
3
.3V_RUN
C C
+
1
.05V_RUN
SACK#< 39>
U
S
B B
Y
S_PWROK<7, 39>
S
SET_OUT#<4 0>
E
R
_DRAM_PWRGD<7>
M
P
C
H_RSMRST#_Q<1 4,41>
P
_SUS_PWR_ACK<40>
E
M
IO_PWRBTN#_R<7,14>
S
I
O_PWRBTN#<40>
S
C
_PRESENT<40>
A
+
3
.3V_ALW_PCH
A A
1
R
R
142 10K_0402_5%~D
142 10K_0402_5%~D
H
H
1 2
R
R
319 10K_0402_5%~D@
319 10K_0402_5%~D@
H
H
1 2
H
H
140 10K_0402_5%~D
140 10K_0402_5%~D
R
R
1 2
H
H
137 8. 2K_0402_5%~D
137 8. 2K_0402_5%~D
R
R
1 2
R
R
H
H
138 8. 2K_0402_5%~D@
138 8. 2K_0402_5%~D@
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
M
D
1 2
R
R
H
H
111 49.9_0402_1%~D
111 49.9_0402_1%~D
1 2
R
R
H112 750_0402_1%~D
H112 750_0402_1%~D
1 2
114 0_0402_5%~D@
RH
RH
114 0_0402_5%~D@
1 2
116 0_0402_5%~D@
116 0_0402_5%~D@
H
H
R
R
1
R
R
H
H
117 0_0402_5%~D@
117 0_0402_5%~D@
1 2
R
R
320 0_0402_5%~D@
H
H
320 0_0402_5%~D@
1 2
H
H
120 0_0402_5%~D@
120 0_0402_5%~D@
R
R
1
H
H
121 0_0402_5%~D@
121 0_0402_5%~D@
R
R
1 2
R
R
122 0_0402_5%~D@
H
H
122 0_0402_5%~D@
1
R
R
H
H
139 8.2K_0402_5%~D
139 8.2K_0402_5%~D
S_STAT#/LPCPD#
_SUS_PWR_ACK
ME
P
H_PCIE_WAKE#
C
2
S
I
O_SLP_LAN#
P
H_RI#
C
C
KRUN#
L
M
_RESET#
E
D
I_CTX_PRX_N0
2
2
2
D
I_COMP_R
M
R
BIAS_CPY
M
D
I_CTX_PRX_N1
M
D
M
I_CTX_PRX_N2
D
I_CTX_PRX_N3
M
D
I_CTX_PRX_P0
M
D
M
I_CTX_PRX_P1
D
I_CTX_PRX_P2
M
D
M
I_CTX_PRX_P3
D
I_CRX_PTX_N0
M
D
I_CRX_PTX_N1
M
D
M
I_CRX_PTX_N2
D
M
I_CRX_PTX_N3
D
M
I_CRX_PTX_P0
D
I_CRX_PTX_P1
M
D
M
I_CRX_PTX_P2
D
I_CRX_PTX_P3
M
S
U
SACK#_R
S
Y
S_RESET#
S
S_PWROK_R
Y
P
H_PWROK
C
P
_APWROK_R
M
P
_DRAM_PWRGD_R
M
P
C
H_RSMRST#_R
M
_SUS_PWR_ACK_R
E
S
I
O_PWRBTN#_R
A
_PRESENT
C
P
C
H_BATLOW#
P
H_RI#
C
I_CTX_PRX_N0<6>
I_CTX_PRX_N1<6>
I_CTX_PRX_N2<6>
I_CTX_PRX_N3<6>
I_CTX_PRX_P0<6>
I_CTX_PRX_P1<6>
I_CTX_PRX_P2<6>
I_CTX_PRX_P3<6>
I_CRX_PTX_N0<6>
I_CRX_PTX_N1<6>
I_CRX_PTX_N2<6>
I_CRX_PTX_N3<6>
I_CRX_PTX_P0<6>
I_CRX_PTX_P1<6>
I_CRX_PTX_P2<6>
I_CRX_PTX_P3<6>
XD
P_DBRESET#<7 ,14>
M
E
_SUS_PWR_ACK_R
U
U
4C
H
H
4C
BC24
D
I0RXN
M
BE20
D
I1RXN
M
BG18
D
I2RXN
M
BG20
D
M
I3RXN
BE24
D
I0RXP
M
BC20
D
M
I1RXP
BJ18
D
M
I2RXP
BJ20
D
M
I3RXP
AW24
D
I0TXN
M
AW20
D
M
I1TXN
BB18
D
M
I2TXN
AV18
D
M
I3TXN
AY24
D
M
I0TXP
AY20
D
M
I1TXP
AY18
D
I2TXP
M
AU18
D
I3TXP
M
BJ24
D
M
I_ZCOMP
BG25
D
I_IRCOMP
M
BH21
M
I2RBIAS
D
C12
U
SACK#
S
K3
S
S_RESET#
Y
P12
S
Y
S_PWROK
L22
W
ROK
P
L10
P
WROK
A
B13
R
AMPWROK
D
C21
MRST#
S
R
K16
SWARN#/SUSPWRDNACK/GPIO30
U
S
E20
P
W
RBTN#
H20
PRESENT / GPIO31
C
A
E10
A
TLOW# / GPIO72
B
A10
I
#
R
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
P
R
E
SET_OUT#
R
R
C
H_DPWROK
4
357 0_0402_5%~D@RH357 0_0402_5%~D@
RH
1 2
+
3.3V_RUN
U
U
3
@
3
@
C
C
1
E
_RESET#
P
C
H_RSMRST#_R
S
Y
S
U
F
I_RXN0
D
F
I_RXN1
D
F
D
I_RXN2
F
I_RXN3
D
F
I_RXN4
D
F
D
I_RXN5
F
D
I_RXN6
F
I_RXN7
D
F
D
I_RXP0
F
D
I_RXP1
F
D
I_RXP2
F
I_RXP3
D
F
D
I_RXP4
F
D
I_RXP5
F
I_RXP6
D
F
I_RXP7
D
F
D
F
I_FSYNC0
D
F
I_FSYNC1
D
F
D
I_LSYNC0
F
I_LSYNC1
D
WVRMEN
S
D
WROK
P
D
W
U
SCLK / GPIO62
P_S5# / GPIO63
S
P_S4#
L
S
L
P_S3#
L
S
S
LP_SUS#
P
SYNCH
M
B
2
A
S_PWROK
SACK#_R
I_INT
KE#
A
P_A#
M
12
141 8.2K_0402_5%~D@
141 8.2K_0402_5%~D@
H
H
1 2
R
R
H
H
113 0_0402_5%~D@
113 0_0402_5%~D@
1 2
H
H
321 0_0402_5%~D@
321 0_0402_5%~D@
R
R
1 2
RH
323 0_0402_5%~D@RH323 0_0402_5%~D@
DI
DI
DMIF
DMIF
KRUN# / GPIO32
L
C
U
S_STAT# / GPIO61
S
S
S
L
ystem Power Management
ystem Power Management
S
S
P_LAN# / GPIO29
L
S
C
C
99
@
99
@
H
H
1 2
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
P
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
F
D
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
I_CTX_PRX_N0
F
I_CTX_PRX_N1
D
F
I_CTX_PRX_N2
D
F
I_CTX_PRX_N3
D
F
D
I_CTX_PRX_N4
F
D
I_CTX_PRX_N5
F
D
I_CTX_PRX_N6
F
I_CTX_PRX_N7
D
F
I_CTX_PRX_P0
D
F
I_CTX_PRX_P1
D
F
DI_CTX_PRX_P2
F
D
I_CTX_PRX_P3
F
D
I_CTX_PRX_P4
F
D
I_CTX_PRX_P5
F
I_CTX_PRX_P6
D
F
I_CTX_PRX_P7
D
F
D
I_INT
F
D
I_FSYNC0
F
I_FSYNC1
D
F
I_LSYNC0
D
F
DI_LSYNC1
D
WODVREN
S
P
H_DPWROK
C
P
H_PCIE_WAKE#
C
C
KRUN#
L
S
S_STAT#/LPCPD#
U
S
U
SCLK
S
I
O_SLP_S5#
S
O_SLP_S4#
I
S
IO_SLP_S3#
S
O_SLP_A#
I
S
I
O_SLP_SUS#
H
PM_SYNC
_
S
O_SLP_LAN#
I
RH
RH
H
H
R
R
H
H
R
R
R
R
H
S
Y
S_RESET#
H
SWODVREN - On Die DSW VR Enable
D
Enabled (DEFAULT)
Disabled
D
I_CTX_PRX_N0 <6>
F
D
I_CTX_PRX_N1 <6>
F
D
I_CTX_PRX_N2 <6>
F
I_CTX_PRX_N3 <6>
D
F
I_CTX_PRX_N4 <6>
D
F
I_CTX_PRX_N5 <6>
D
F
D
I_CTX_PRX_N6 <6>
F
I_CTX_PRX_N7 <6>
D
F
D
I_CTX_PRX_P0 <6>
F
I_CTX_PRX_P1 <6>
D
F
I_CTX_PRX_P2 <6>
D
F
I_CTX_PRX_P3 <6>
D
F
I_CTX_PRX_P4 <6>
D
F
I_CTX_PRX_P5 <6>
D
F
D
I_CTX_PRX_P6 <6>
F
D
I_CTX_PRX_P7 <6>
F
D
I_INT <6>
F
I_FSYNC0 <6>
D
F
D
I_FSYNC1 <6>
F
D
I_LSYNC0 <6 >
F
I_LSYNC1 <6 >
D
F
H
H
127 330K_0402_1%~D
127 330K_0402_1%~D
R
R
1 2
R
R
H
H
129 330K_0402_1%~D@
129 330K_0402_1%~D@
1 2
H_DPWROK <39>
C
P
C
H_PCIE_WAKE# <40>
P
LKRUN# <32,39,40>
C
6 PAD~D
5
5
6 PAD~D
T
T
7 PAD~D
5
5
7 PAD~D
T
T
5
5
8 PAD~D
8 PAD~D
T
T
IO_SLP_S5# <40>
S
9 PAD~D
5
5
9 PAD~D
T
T
O_SLP_S4# <39,42,4 6>
I
S
I
O_SLP_S3# <11,27,3 5,39,42,47>
S
I
O_SLP_A# <39,42,48>
S
62 PAD~D
62 PAD~D
T
T
I
O_SLP_SUS# <39>
S
T
T
3 PAD~D
6
6
3 PAD~D
_
PM_SYNC <7>
H
IO_SLP_LAN# <31,39>
S
3
P
H_CRT_BLU
1 2
131 150 _0402_1%~D
131 150 _0402_1%~D
1 2
132 150 _0402_1%~D
132 150 _0402_1%~D
1 2
133 150 _0402_1%~D
133 150 _0402_1%~D
1 2
134 100 K_0402_5%~D
134 100 K_0402_5%~D
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
LOW: RH129 STUFFED,
RH127 UNSTUFFED
C
P
CH_CRT_GRN
P
C
H_CRT_RED
E
VDD_PCH
N
L
L
inimum speacing of 20mils for LVD_IBG
M
+
R
TC_CELL
H_CRT_HSYNC<23>
C
P
CH_CRT_VSYNC<23>
P
2.2K_0402_5%~D
2.2K_0402_5%~D
A
NEL_BKEN_PCH<24>
P
N
VDD_PCH<24,39>
E
I
A_PWM_PCH<24 >
B
D
DC_CLK_PCH<24>
D
DC_DATA_PCH<24>
1 2
R
R
344 2.37 K_0402_1%~D
344 2.37 K_0402_1%~D
H
H
D_ACLK-_PCH<24>
C
L
D_ACLK+_PCH<24>
C
L
D_A0-_PCH<24>
C
L
D_A1-_PCH<24>
C
L
D_A2-_PCH<24>
C
L
D_A0+_PCH<24>
C
L
C
D_A1+_PCH<24>
L
C
D_A2+_PCH<24>
L
C
D_BCLK-_PCH<24>
L
C
D_BCLK+_PCH<24>
L
D_B0-_PCH<24>
C
L
D_B1-_PCH<24>
C
L
D_B2-_PCH<24>
C
L
D_B0+_PCH<24>
C
L
D_B1+_PCH<24>
C
L
D_B2+_PCH<24>
C
L
C
H_CRT_BLU<23>
P
C
H_CRT_GRN<23>
P
C
H_CRT_RED<23>
P
R
R
123 20_0402_1%~D
123 20_0402_1%~D
H
H
1 2
1 2
R
R
124 20_0402_1%~D
H
H
124 20_0402_1%~D
1K_0402_0.5%~D
1K_0402_0.5%~D
+
.3V_RUN
3
12
12
R
R
H
H
316
316
_APWROK<40>
M
P
P
NEL_BKEN_PCH
A
E
N
VDD_PCH
B
I
A_PWM_PCH
L
DC_CLK_PCH
D
L
DC_DATA_PCH
D
L
V
D_IBG
L
C
D_ACLK-_PCH
L
C
D_ACLK+_PCH
L
C
D_A0-_PCH
L
C
D_A1-_PCH
L
C
D_A2-_PCH
L
C
D_A0+_PCH
L
C
D_A1+_PCH
L
D_A2+_PCH
C
L
D_BCLK-_PCH
C
L
D_BCLK+_PCH
C
L
C
D_B0-_PCH
L
C
D_B1-_PCH
L
C
D_B2-_PCH
L
CD_B0+_PCH
L
D_B1+_PCH
C
L
D_B2+_PCH
C
P
CH_CRT_BLU
P
CH_CRT_GRN
P
C
H_CRT_RED
P
H_CRT_DDC_CLK
C
P
C
H_CRT_DDC_DAT
H
S
V
S
R
R
H
H
126
126
YNC
YNC
2
2.2K_0402_5%~D
2.2K_0402_5%~D
R
R
H
H
317
317
P
H_CRT_DDC_CLK
C
P
C
H_CRT_DDC_DAT
S
O_SLP_A#
I
P
M
_APWROK
J47
M45
P45
T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
C
T_IREF
R
T43
12
T42
+
3
.3V_ALW2
5
1
P
B
2
A
G
3
1 2
R
R
H
H
118 0_0402_5%~D@
118 0_0402_5%~D@
tel request DDPB can not support eDP
n
I
4D
H
H
4D
U
U
BKLTEN
_
L
_
VDD_EN
L
BKLTCTL
_
L
DDC_CLK
_
L
DDC_DATA
_
L
_
CTRL_CLK
L
_
CTRL_DATA
L
D_IBG
V
L
D_VBG
V
L
D_VREFH
V
L
D_VREFL
V
L
V
DSA_CLK#
L
DSA_CLK
V
L
V
DSA_DATA#0
L
V
DSA_DATA#1
L
V
DSA_DATA#2
L
V
DSA_DATA#3
L
V
DSA_DATA0
L
V
DSA_DATA1
L
V
DSA_DATA2
L
DSA_DATA3
V
L
V
DSB_CLK#
L
V
DSB_CLK
L
V
DSB_DATA#0
L
V
DSB_DATA#1
L
V
DSB_DATA#2
L
V
DSB_DATA#3
L
V
DSB_DATA0
L
DSB_DATA1
V
L
DSB_DATA2
V
L
V
DSB_DATA3
L
R
T_BLUE
C
T_GREEN
R
C
T_RED
R
C
R
T_DDC_CLK
C
RT_DDC_DATA
C
R
T_HSYNC
C
T_VSYNC
R
C
C_IREF
A
D
R
T_IRTN
C
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
C
H_CRT_DDC_CLK <23>
P
H_CRT_DDC_DAT <23>
C
P
1 2
CH
CH
108 0.1U_0402_25V6K~D
108 0.1U_0402_25V6K~D
5
5
H
H
U
U
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
P
M_APWROK_R
4
O
VO_STALLN
VO_STALLP
S
VO_INTN
D
SD
VO_INTP
D
PB_AUXN
D
PB_AUXP
DD
DD
PB_HPD
DPB_0N
D
D
PB_0P
D
D
PB_1N
D
D
PB_1P
D
D
PB_2N
D
D
PB_2P
D
D
PB_3N
D
PB_3P
D
D
D
PC_AUXN
D
PC_AUXP
DD
DDPC_HPD
PC_0N
D
D
PC_0P
D
D
D
PC_1N
D
PC_1P
D
D
PC_2N
D
D
PC_2P
D
D
PC_3N
D
D
PC_3P
D
D
D
PD_AUXN
D
PD_AUXP
DD
DD
PD_HPD
PD_0N
D
D
D
PD_0P
D
D
PD_1N
D
D
PD_1P
D
PD_2N
D
D
D
PD_2P
D
PD_3N
D
D
D
PD_3P
D
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
SD
VO_TVCLKINN
SD
VO_TVCLKINP
SD
SD
D
VO_CTRLCLK
S
D
VO_CTRLDATA
S
VDS
VDS
L
L
PC_CTRLCLK
D
D
DPC_CTRLDATA
D
Digital Display Interface
Digital Display Interface
PD_CTRLCLK
D
D
PD_CTRLDATA
D
D
RT
RT
C
C
P
C
H_SDVO_CTRLCLK
P
H_SDVO_CTRLDATA
C
P
C
H_SDVO_CTRLCLK
P
H_SDVO_CTRLDATA
C
H
M
T
M
T
M
T
M
T
M
T
M
T
M
T
M
T
P
P
D
D
P
D
P
D
P
D
P
D
P
D
P
D
D
P
D
D
P
PD_PCH_DOCK_AUX# <26>
D
P
D
PD_PCH_DOCK_HPD <38>
D
P
D
P
D
P
D
P
D
P
D
P
D
PD_PCH_LANE_N3 <38>
D
P
D
P
P
P
1
H
H
351 2. 2K_0402_5%~D
351 2. 2K_0402_5%~D
R
R
R
R
H
H
352 2. 2K_0402_5%~D
352 2. 2K_0402_5%~D
H_SDVO_CTRLCLK <25>
C
P
H_SDVO_CTRLDATA < 25>
C
P
MIB_PCH_HPD <25>
D
DSB_PCH_N2 <25>
DSB_PCH_P2 <25>
DSB_PCH_N1 <25>
DSB_PCH_P1 <25>
DSB_PCH_N0 <25>
DSB_PCH_P0 <25>
DSB_PCH_CLK# <25>
DSB_PCH_CLK <25>
H_DDPC_CTRLCLK <26>
C
C
H_DDPC_CTRLDATA <26>
P
C_PCH_DOCK_AUX# <26>
C_PCH_DOCK_AUX <26>
C_PCH_DOCK_HPD <38>
C_PCH_LANE_N0 <38>
C_PCH_LANE_P0 < 38>
C_PCH_LANE_N1 <38>
C_PCH_LANE_P1 < 38>
C_PCH_LANE_N2 <38>
C_PCH_LANE_P2 < 38>
C_PCH_LANE_N3 <38>
C_PCH_LANE_P3 < 38>
H_DDPD_CTRLCLK <26>
C
H_DDPD_CTRLDATA <26>
C
P
D_PCH_DOCK_AUX <26>
D_PCH_LANE_N0 <38>
D_PCH_LANE_P0 < 38>
D_PCH_LANE_N1 <38>
D_PCH_LANE_P1 < 38>
D_PCH_LANE_N2 <38>
D_PCH_LANE_P2 < 38>
D_PCH_LANE_P3 < 38>
+
.3V_RUN
3
12
12
LL CONFIDENTIAL/PROPRIETARY
E
D
pal Electronics, Inc.
om
om
om
pal Electronics, Inc.
pal Electronics, Inc.
C
C
Title
i
i
tle
tle
T
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P
5
4
3
2
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
H (3/8)
C
C
C
H (3/8)
H (3/8)
P
P
P
0
.
.
.
0
0
1
1
L
L
L
-7781
A
A
A
-7781
-7781
6 6
6 6
6 6
1
1
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
5
+
3
.3V_RUN
P
C
I_PIRQA#
2
1
H
324 8.2K_0402_5%~D
324 8.2K_0402_5%~D
H
R
D D
C C
R
1 2
325 8.2K_0402_5%~D
325 8.2K_0402_5%~D
H
H
R
R
1
R
R
H
326 8.2K_0402_5%~D
326 8.2K_0402_5%~D
H
1 2
R
R
329 8.2K_0402_5%~D
329 8.2K_0402_5%~D
H
H
1 2
327 10K_0402_5%~D
327 10K_0402_5%~D
H
H
R
R
1 2
R
R
H
H
330 10K_0402_5%~D
330 10K_0402_5%~D
1 2
H
H
328 10K_0402_5%~D
328 10K_0402_5%~D
R
R
1 2
R
R
332 10K_0402_5%~D
332 10K_0402_5%~D
H
H
1 2
H
H
331 10K_0402_5%~D
331 10K_0402_5%~D
R
R
1 2
359 10K_0402_5%~D
359 10K_0402_5%~D
H
H
R
R
P
C
I_GNT3#
12
H
H
333
@
333
@
R
R
1K_0402_5%~D
1K_0402_5%~D
1
6 swap override Strap/Top-Bloc k
A
P
I_PIRQB#
C
P
CI_PIRQC#
2
P
CI_PIRQD#
P
C
I_REQ1#
L
D_CBL_DET#
C
B
_DET#
T
P
H_GPIO3
C
C
M_MIC_CBL_DET#
A
P
C
IE_MCARD2_DET#
Swap Override jumper
P
C
IE_MCARD2_DET#<34>
C
1 2
334 0_0402_5%~D@
H
H
334 0_0402_5%~D@
R
R
H
H
160 22_0402_5%~D
160 22_0402_5%~D
R
R
H102 22_0402_5%~D
H102 22_0402_5%~D
R
R
R
R
H
H
103 22_0402_5%~D
103 22_0402_5%~D
R
R
H
H
105 22_0402_5%~D
105 22_0402_5%~D
C
K_PCI_5048
L
1
C
C
110
H
H
110
12P_0402_50V8J~D
12P_0402_50V8J~D
2
P
H_PLTRST#_EC <32,34,35,39,40>
C
H_PLTRST#<7,14>
Low = A16 swap
High = Default
P
L
TRST_USH#<32>
P
L
TRST_MMI#<33>
P
TRST_XDP#<7>
L
P
TRST_LAN#<31>
L
LTRST_EMB#<28>
P
P
C
H_PLTRST#
5
+
3.3V_RUN
1
2
5
P
B
A
G
3
H
D_FALL_INT<27>
D
1 2
R
R
H
H
335 0_0402_5%~D@
335 0_0402_5%~D@
1 2
R
R
336 0_0402_5%~D@
336 0_0402_5%~D@
H
H
1 2
H337 0_0402_5%~D@RH337 0_0402_5%~D@
R
1 2
R
R
338 0_0402_5%~D@
338 0_0402_5%~D@
H
H
1 2
340 0_0402_5%~D@
H
H
340 0_0402_5%~D@
R
R
C
LK_PCI_5048<39>
C
K_PCI_MEC<40>
L
C
L
K_PCI_DOCK<38>
C
K_PCI_LOOPBACK<15>
L
C
C
102
H
H
102
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
3
H
H
3
U
U
P
H_PLTRST#_EC
C
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
CI_GNT#3
P
B B
A A
C
P
4
H
H
4E
4E
U
U
BG26
T
1
P
BJ26
T
P
2
BH25
T
3
P
BJ16
T
4
P
BG16
T
P
5
AH38
T
P
6
AH37
T
P
7
AK43
T
P
8
AK45
T
9
P
C18
T
10
P
N30
T
P11
H3
T
P
12
AH12
T
P
13
AM4
T
P
14
AM5
T
P
15
Y13
T
P
16
K24
T
P
17
L24
T
P
18
AB46
T
P
19
AB45
T
20
P
SVD
21
22
23
24
B3Rn1
B3Rn2
B3Rn3
B3Rn4
B3Rp1
B3Rp2
B3Rp3
B3Rp4
B3Tn1
B3Tn2
B3Tn3
B3Tn4
B3TP1
B3Tp2
B3Tp3
B3Tp4
Q1# / GPIO50
Q2# / GPIO52
Q3# / GPIO54
T1# / GPIO51
T2# / GPIO53
T3# / GPIO55
E#
KOUT_PCI0
KOUT_PCI1
KOUT_PCI2
KOUT_PCI3
KOUT_PCI4
SVD
R
R
SB30
SB30
U
U
CI
CI
P
P
SATA_SLPD
(BBS_BIT0)
B21
T
P
M20
T
P
AY16
T
P
BG46
T
P
I_5048
I_MEC
I_DOCK
BE28
U
S
BC30
U
S
BE32
U
S
BJ32
U
S
BC28
U
S
BE30
U
S
BF32
U
S
BG32
U
S
AV26
U
S
BB26
U
S
AU28
U
S
AY30
U
S
AU26
U
S
AY26
U
S
AV28
U
S
AW30
U
S
K40
IRQA#
P
K38
I
RQB#
P
H38
RQC#
I
P
G38
I
RQD#
P
C46
E
R
C44
E
R
E40
RE
D47
GN
E42
GN
F46
GN
G42
RQE# / GPIO2
PI
G40
PIRQF# / GPIO3
C42
PI
RQG# / GPIO4
D44
PI
RQH# / GPIO5
K10
P
M
C6
P
TRST#
L
H49
C
L
H43
C
L
J48
C
L
K42
C
L
H40
C
L
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
oot BIOS Strap
B
S
B3RN1<36>
U
SB3RN2<36>
U
S
B3RN4<38>
U
S
B3RP1<36>
U
S
B3RP2<36>
U
S
B3RP4<38>
U
S
B3TN1<36>
U
B3TN2<36>
S
U
S
B3TN4<38>
U
B3TP1<36>
S
U
B3TP2<36>
S
U
B3TP4<38>
S
U
P
CI_PIRQA#
P
I_PIRQB#
C
P
I_PIRQC#
C
P
I_PIRQD#
C
P
I_REQ1#
C
B
T
B
_DET#<41>
T
L
D_CBL_DET#<24>
C
M_MIC_CBL_DET#<24>
A
12
12
12
12
_DET#
B
BS_BIT1
P
I_GNT3#
C
L
D_CBL_DET#
C
P
C
H_GPIO3
C
A
M_MIC_CBL_DET#
F
F
S_PCH_INT
1
1
04PAD~D @
04PAD~D @
T
T
P
C
H_PLTRST#
P
P
P
P
I_LOOPBACKOUT
C
C
K_PCI_MEC
L
1
109
109
H
H
C
C
12P_0402_50V8J~D
12P_0402_50V8J~D
2
C
C
C
BBS_BIT1 Boot BIOS Location
0 0
0
1
1
*
4
1
0
1
3
USB
USB
O
C
O
C
O
C
O
C
O
C
O
O
C
O
C
LPC
eserved (NAND)
R
PCI
SPI
3
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
SVD9
R
VD10
S
R
VD11
S
R
S
VD12
R
SVD13
R
VD14
S
R
S
VD15
R
S
VD16
R
S
VD17
R
S
VD18
R
S
VD19
R
S
VD20
R
S
VD21
R
S
VD22
R
S
VD23
R
VD24
S
R
VD25
S
R
VD26
S
R
S
VD27
R
S
VD28
R
S
VD29
R
US
BP0N
US
BP0P
U
BP1N
S
U
BP1P
S
U
BP2N
S
U
BP2P
S
U
BP3N
S
U
S
BP3P
U
S
BP4N
U
S
BP4P
U
BP5N
S
U
BP5P
S
U
BP6N
S
U
BP6P
S
U
BP7N
S
U
BP7P
S
U
S
BP8N
U
S
BP8P
U
S
BP9N
U
BP9P
S
U
BP10N
S
U
BP10P
S
U
S
BP11N
U
S
BP11P
U
S
BP12N
U
BP12P
S
U
BP13N
S
U
BP13P
S
U
BRBIAS#
S
U
S
BRBIAS
0# / GPIO59
1# / GPIO40
2# / GPIO41
3# / GPIO42
4# / GPIO43
C
5# / GPIO9
6# / GPIO10
7# / GPIO14
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
SBP8-
U
SBP8+
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
S
U
SBP13+
U
S
U
SB_OC0#_R
U
B_OC1#_R
S
U
S
B_OC2#
U
B_OC3#
S
U
B_OC4#_R
S
U
B_OC5#
S
U
B_OC6#
S
2
BP0BP0+
BP1BP1+
BP2BP2+
BP3BP3+
BP4BP4+
BP5BP5+
BP6BP6+
BP7BP7+
BP9BP9+
BP10BP10+
BP11BP11+
BP12BP12+
BP13-
BRBIAS
U
S
BP0- <36>
U
S
BP0+ <36>
U
BP1- <36>
S
U
S
BP1+ <36>
U
BP2- <37>
S
U
BP2+ <37>
S
U
BP3- <38>
S
U
BP3+ <38>
S
U
SBP4- <34>
U
BP4+ <34>
S
U
SBP5- <34>
U
S
BP5+ <34>
U
S
BP6- <38>
U
S
BP6+ <38>
U
BP7- <32>
S
U
S
BP7+ <32>
U
BP8- <34>
S
U
BP8+ <34>
S
U
SBP9- <30>
U
S
BP9+ <30>
U
S
BP10- <35>
U
S
BP10+ <35>
U
BP11- <41>
S
U
BP11+ <41>
S
U
S
BP12- <24>
U
BP12+ <24>
S
U
S
BP13- <24>
U
BP13+ <24>
S
1 2
151
H
H
151
R
R
22.6_0402_1%~D
22.6_0402_1%~D
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
1 2
R
R
H
H
339 0_0402_5%~D@
339 0_0402_5%~D@
1 2
H
H
341 0_0402_5%~D@
341 0_0402_5%~D@
R
R
1
R
R
H
H
356 0_0402_5%~D@
356 0_0402_5%~D@
S
I
O_EXT_SMI#
B
S_BIT1
B
----->Right Side Top
-
--->Right Side Bottom
-
----->Right side E-SATA
----->MLK DOCK
-
--->WLAN/WIMAX
-
---->WWAN/UWB
-
--->DOCK
-
-
----->USH
----->Flash
----->Left side
----->Express Card
----->Blue Tooth
--->Camera
-
-
----->LCD Touch
2
1
342
@
342
@
H
H
R
R
1K_0402_5%~D
1K_0402_5%~D
2
2
U
S
U
S
U
SB_OC2# <14>
U
S
U
S
U
S
U
S
I
O_EXT_SMI# <14,40>
S
U
S
U
S
S
U
B_OC0# <36>
B_OC1# <36>
B_OC3# <14>
B_OC4# <30>
B_OC5# <14>
B_OC6# <14>
B_OC0#_R <14>
B_OC1#_R <14>
B_OC4#_R <14>
1
+
3
NTEL feedback 0307
I
U
B_OC0#_R
S
U
B_OC1#_R
S
U
B_OC3#
S
U
B_OC4#_R
S
10K_1206_8P4R_5%~D
U
U
S
U
LL CONFIDENTIAL/PROPRIETARY
E
D
Title
tle
i
itle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
10K_1206_8P4R_5%~D
B_OC5#
S
S
B_OC6#
I
O_EXT_SMI#
SB_OC2#
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
C
C
C
C
P
P
P
-7781
-7781
A
A
A
-7781
L
L
L
R
R
4 5
3 6
2 7
1 8
R
R
4 5
3 6
2 7
1 8
H (4/8)
H (4/8)
H (4/8)
1
H1
H1
P
P
H2
H2
P
P
.3V_ALW_PCH
7 61Friday, February 24, 2012
7 6
7 6
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
0
0
.
.
.
0
1
1
1
5
+
.3V_ALW_PCH
3
H
H
53
53
R
R
4.7K_0402_5%~D
D D
C C
B B
A A
4.7K_0402_5%~D
1 2
S
L
P_ME_CSW_DEV#
1
R
R
353
353
H
H
1K_0402_5%~D
1K_0402_5%~D
@
@
2
o
te: PCH has internal pull up 20k ohm on
N
E3_PAID_TS_DET# (GPIO27)
LP_ME_CSW_DEV# PLL ON DIE VR ENABLE
S
ENABLED - HIGH DEFAULT
DISABLED - LOW
+
.3V_ALW_PCH
3
S
IO_EXT_WAKE#
12
177 10K_0402_5%~D
177 10K_0402_5%~D
H
H
1 2
354 1K_ 0402_5%~D
H
H
354 1K_ 0402_5%~D
NTEL feedback 0302
I
2
H
H
174 10K_0402_5%~D
174 10K_0402_5%~D
R
R
R
R
H
H
172 10K_0402_5%~D
172 10K_0402_5%~D
273 1K_0402_5%~D@
H
H
273 1K_0402_5%~D@
R
R
R
R
H
H
265 10K_0402_5%~D@
265 10K_0402_5%~D@
12
1
12
12
1
1
P
P
C
H_GPIO36
1
P
H_GPIO37
C
12
P
H_GPIO17
C
12
P
CH_GPIO16
12
K
_DET#
B
P
H_GPIO36
C
P
H_GPIO37
C
T
EMP_ALERT#
P
H_GPIO22
C
P
C
H_GPIO7
P
H_GPIO17
C
I
O
_LOOP#
P
C
H_GPIO16
5
C
H_GPIO15
+
3.3V_ALW_PCH
R
R
+
3
.3V_RUN
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
170 10K_0402_5%~D
170 10K_0402_5%~D
H
H
2
H
H
171 10K_0402_5%~D@
171 10K_0402_5%~D@
H
H
173 1K_0402_5%~D@
173 1K_0402_5%~D@
H
H
266 10K_0402_5%~D
266 10K_0402_5%~D
2
181 10K_0402_5%~D
181 10K_0402_5%~D
H
H
2
H
H
178 10K_0402_5%~D
178 10K_0402_5%~D
1 2
H
H
269 8.2K_0402_5%~D
269 8.2K_0402_5%~D
1 2
163 10K_0402_5%~D
H
H
163 10K_0402_5%~D
1 2
272 10K_0402_5%~D
H
H
272 10K_0402_5%~D
S
I
O_EXT_SCI#_R<14>
S
I
O_EXT_SCI#<40>
U
SH_DET#<32>
I
_LOOP#<30>
O
S
IO_EXT_WAKE#<39>
P
_LANPHY_ENABLE< 31>
M
P
CH_GPIO15<14>
P
H_GPIO16<14>
C_ENABLE for E4 12"
B
D
L
ayout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
C
P
IE_MCARD1_DET#<34>
C
E
_PAID_TS_DET#<24>
3
S
P_ME_CSW_DEV#<14,39>
L
U
B_MCARD1_DET#<14,34>
S
P
H_GPIO36<14>
C
P
C
H_GPIO37<14>
F
F
T
E
MP_ALERT#<14,39>
K
B_DET#<41>
+
3
.3V_RUN
T
M_ID0
P
S_INT2<27>
1@
1@
10K_0402_5%~D
10K_0402_5%~D
1 2
12
2@
2@
10K_0402_5%~D
10K_0402_5%~D
S
267
H
H
267
R
R
H
H
270
270
R
R
4
I
O_EXT_SCI#
4
1 2
259 0_0402_5%~D@
259 0_0402_5%~D@
H
H
R
R
U
H_DET#
S
I
_LOOP#
O
P
H_GPIO7
C
P
_LANPHY_ENABLE
M
P
H_GPIO15
C
P
H_GPIO16
C
P
C
H_GPIO17
P
C
H_GPIO22
E
_PAID_TS_DET#
3
S
LP_ME_CSW_DEV #
U
B_MCARD1_DET#
S
P
C
H_GPIO36
P
C
H_GPIO37
T
P
M_ID0
T
M_ID1
P
F
F
S_INT2
T
E
MP_ALERT#
K
_DET#
B
V
S
S_NCTF_1
V
S
S_NCTF_2
V
S_NCTF_3
S
V
S
S_NCTF_4
V
S_NCTF_5
S
V
S_NCTF_6
S
V
S_NCTF_7
S
V
S_NCTF_8
S
V
S
S_NCTF_9
V
S_NCTF_10
S
V
S_NCTF_11
S
V
S
S_NCTF_12
V
S_NCTF_13
S
V
S_NCTF_14
S
+
3
T
P
M_ID1
.3V_RUN
12
12
@
@
2.2K_0402_5%~D
2.2K_0402_5%~D
T7
A42
H36
E38
C10
C4
G2
U2
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
R
R
H
H
268
268
20K_0402_5%~D
20K_0402_5%~D
H
H
271
271
R
R
H
H
4F
4F
U
U
BM
BUSY# / GPIO0
CH1 / GPIO1
TA
CH2 / GPIO6
A
T
CH3 / GPIO7
A
T
P
IO8
G
A
N_PHY_PWR_CTRL / GPIO12
L
P
IO15
G
TA4GP / GPIO16
SA
A
CH0 / GPIO17
T
LOCK / GPIO22
C
S
P
IO24
G
IO27
P
G
IO28
P
G
T
P_PCI# / GPIO34
S
IO35
GP
A
TA2GP / GPIO36
S
TA3GP / GPIO37
A
S
L
OAD / GPIO38
S
D
ATAOUT0 / GPIO39
S
D
ATAOUT1 / GPIO48
S
TA5GP / GPIO49 / TEMP_ALERT#
A
S
IO57
P
G
S_NCTF_1
S
V
S_NCTF_2
S
V
S_NCTF_3
S
V
S_NCTF_4
S
V
S_NCTF_5
S
V
S_NCTF_6
S
V
S_NCTF_7
S
V
S_NCTF_8
S
V
S_NCTF_9
S
V
S
S_NCTF_10
V
S_NCTF_11
S
V
S_NCTF_12
S
V
V
S
S_NCTF_13
V
SS_NCTF_14
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
Non-TPM
PM
GPIO
GPIO
CTF
CTF
N
N
3
TA
CH4 / GPIO68
CH5 / GPIO69
TA
CH6 / GPIO70
TA
CH7 / GPIO71
TA
0GATE
A2
OCPWRGD
R
P
H
RMTRIP#
T
N
IT3_3V#
I
D
F
PU/MISC
PU/MISC
C
C
T
S
_VSS1
T
S
_VSS2
T
S
_VSS3
T
S
_VSS4
V
S
S_NCTF_15
V
S
S_NCTF_16
VS
S_NCTF_17
VS
S_NCTF_18
VS
S_NCTF_19
VS
S_NCTF_20
V
S_NCTF_21
S
V
S_NCTF_22
S
V
S_NCTF_23
S
V
S
S_NCTF_24
V
S
S_NCTF_25
V
S
S_NCTF_26
V
S_NCTF_27
S
V
S_NCTF_28
S
V
S_NCTF_29
S
V
SS_NCTF_30
V
S
S_NCTF_31
S
S_NCTF_32
V
1
3
R
P
C
_TVS
N
2
C
O
NTACTLESS_DET#
C
O
NTACTLESS_DET#
C40
P
C
H_GPIO69
B41
P
IE_MCARD3_DET#
C
C41
A40
S
I
O_A20GATE
P4
AU16
E
CI
IN#
_1
C
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
T
P
M_ID1TPM_ID0
S
I
O_RCIN#
H
CPUPWRGD
_
P
H_THRMTRIP#_R
C
I
N
IT3_3V#
D
_TVS
F
N
C
_1
V
S
S_NCTF_15
V
S_NCTF_16
S
V
S
S_NCTF_17
V
S
S_NCTF_18
V
S
S_NCTF_19
V
S
S_NCTF_20
V
S_NCTF_21
S
V
S
S_NCTF_22
V
S
S_NCTF_23
V
S_NCTF_24
S
V
S_NCTF_25
S
V
S_NCTF_26
S
V
S
S_NCTF_27
V
S
S_NCTF_28
V
S_NCTF_29
S
V
SS_NCTF_30
V
S_NCTF_31
S
V
S_NCTF_32
S
C
NTACTLESS_DET# <32>
O
P
C
IE_MCARD3_DET# <34>
U
B_MCARD2_DET# <34>
S
S
I
O_A20GATE <40>
S
I
O_RCIN# <40>
H
CPUPWRGD <7>
_
T
T
06PAD~D
06PAD~D
1
1
@
@
08PAD~D @
1
1
08PAD~D @
T
T
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
1
2
H
_
SNB_IVB#<7>
12
R
R
262 56_0402_5%~D
262 56_0402_5%~D
H
H
H
H
97
97
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
150 0_0402_5%~D@
150 0_0402_5%~D@
H
H
R
R
+
.05V_RUN_VTT
1
1 2
P
H_GPIO69
C
P
L
( TO CPU and NV RAM CONNECTOR)
+
CCDFTERM
V
2
256 10K_0402_5%~D
256 10K_0402_5%~D
H
H
R
R
1 2
R
R
H
H
260 1.5K_0402_1%~D
260 1.5K_0402_1%~D
S
I
O_A20GATE
S
I
O_RCIN#
S
O_EXT_SCI#
I
U
SH_DET#
ACE RH150 CLOSE TO THE BRANCHI NG POINT
1
H
H
149
149
R
R
2.2K_0402_5%~D
2.2K_0402_5%~D
2
D
_TVS_R
F
358 1K_0402_5%~D
H
H
358 1K_0402_5%~D
R
R
D
MI & FDI Termination Voltage
D
F_TVS
1
+
.3V_RUN
3
1
+
3
.3V_RUN
12
158 10K_0402_5%~D
158 10K_0402_5%~D
H
H
R
R
R
R
R
R
R
R
R
1 2
12
203 10K_0402_5%~D
203 10K_0402_5%~D
H
H
1 2
263 10K_0402_5%~D
263 10K_0402_5%~D
H
H
1 2
164 100K_0402_5%~D
164 100K_0402_5%~D
H
H
H
149 need to close to CPU
D
_TVS
F
S
et to Vss when LOW
Set to Vcc when HIGH
10
1T
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
ompal Electronics, Inc.
o
o
mpal Electronics, Inc.
T
T
tle
tle
Title
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
H (5/8)
C
C
C
H (5/8)
H (5/8)
L
L
L
-7781
-7781
A
A
A
-7781
1
1
1
8 6
8 61Friday, February 24, 2012
1
8 61Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
5
+
.05V_RUN
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
D D
+
.05V_RUN
1
+
.05V_RUN
1
C C
+
3
.3V_RUN
B B
1
2
@
@
R
R
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
H
H
51
51
1 2
247
247
H
H
2
+
1
.05V_RUN
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
H
H
44
44
2
+
C
C
H
H
30
30
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C
C
H
H
45
45
2
2
+
+
.05V_RUN
1
.05V_RUN_VTT
1
C
C
H
H
32
32
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
H
H
46
46
2
1
.05V_+1.5V_1.8V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
C
C
H
H
H
H
31
31
33
33
2
+
CCAPLLEXP
V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
@
@
C
C
H
H
40
40
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
H
H
H
H
48
48
47
47
2
+
CCAPLL_FDI
V
4
U
U
H4G
4G
H
AA23
V
CCORE[1]
C
AC23
V
CCORE[2]
C
AD21
V
CCCORE[3]
AD23
V
C
CCORE[4]
AF21
V
C
CCORE[5]
AF23
V
CCORE[6]
C
AG21
V
CCORE[7]
C
AG23
V
CCORE[8]
C
AG24
V
C
CCORE[9]
AG26
V
C
CCORE[10]
AG27
V
C
CCORE[11]
AG29
V
C
CCORE[12]
AJ23
V
C
CCORE[13]
AJ26
V
CCORE[14]
C
AJ27
V
CCCORE[15]
AJ29
C
CCORE[16]
V
AJ31
C
CCORE[17]
V
AN19
V
C
CIO[28]
BJ22
V
CAPLLEXP
C
AN16
V
CIO[15]
C
AN17
V
C
CIO[16]
AN21
V
CIO[17]
C
AN26
V
CIO[18]
C
AN27
V
C
CIO[19]
AP21
V
CIO[20]
C
AP23
V
CIO[21]
C
AP24
V
C
CIO[22]
AP26
V
C
CIO[23]
AT24
V
C
CIO[24]
AN33
C
CIO[25]
V
AN34
CIO[26]
C
V
BH29
C3_3[3]
C
V
AP16
V
C
CVRM[2]
BG6
V
ccAFDIPLL
AP17
V
C
CIO[27]
AU20
CDMI[2]
C
V
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
P
P
WER
WER
O
O
CC CORE
CC CORE
V
V
VCCIO
VCCIO
FDI
FDI
V
C
V
SSADAC
RTLVDS
RTLVDS
C
C
V
CALVDS
C
V
S
SALVDS
V
C
CTX_LVDS[1]
V
CTX_LVDS[2]
C
V
CTX_LVDS[3]
C
V
CCTX_LVDS[4]
C
V
C
V
VCMOS
VCMOS
H
H
V
C
CVRM[3]
C
CDMI[1]
V
MI
MI
CCLKDMI
C
V
D
D
C
CDFTERM[1]
V
CDFTERM[2]
C
V
V
CCDFTERM[3]
V
CDFTERM[4]
C
DFT / SPI
DFT / SPI
V
CADAC
C3_3[6]
C3_3[7]
CSPI
C
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
3
1
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
C
C
H
H
103
103
2
1
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+
1
+
.05V_RUN_VCCCLKDMI
1
1
50
50
H
H
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
2
+
V
CCSPI
1
54
H
H
54
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1UH_GLFR1608T1R0M-LR_20%~D
CCADAC
V
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C
C
H
H
34
34
H52
H
52
1
2
+
CCDFTERM
V
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
H
H
35
35
1 2
1UH_GLFR1608T1R0M-LR_20%~D
1
2
+
43
43
.05V_+1.5V_1.8V_RUN
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
C
C
H
H
36
36
2
+
.8V_RUN_LVDS
1
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C
C
H
H
104
104
49
H
H49
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
H
H
R
R
@
@
1
C
C
H
H
106
106
2
@
H
H276
@
R
R
0_0805_5%~D
0_0805_5%~D
P
P
JP
JP
@
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
2
H
H
202 0_0603_5%~D@
202 0_0603_5%~D@
R
R
204 0_0603_5%~D@
204 0_0603_5%~D@
H
H
R
R
H
H
1
1
L
L
12
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
2
+
3
.3V_RUN
205 0_0603_5%~D@
205 0_0603_5%~D@
276
12
66
66
1
12
I
NTEL feedback 0307
+
.3V_RUN
3
8
8
H
H
L
100NH_HK1608R10J-T_5%_0603~D
100NH_HK1608R10J-T_5%_0603~D
C
C
H
H
105
105
+
12
L
0
.1uH inductor, 200mA
C
PN: SHI0110BJ0L
.05V_RUN_VTT
1
I
NTEL feedback 0302
+
3
.3V_RUN
+
.8V_RUN
1
+
.3V_M
3
+
.3V_RUN
3
+
1
12
.05V_RUN
2
.3V_RUN
+
1
+3
.8V_RUN
P
C
H Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
V
cADPLLB
c
V
c
cCore
V
cDMI
c
V
o
ltage
1.05
3.3
3
1.05
1.05
1.05
1.1
5
5
.
3
1
S
0 Iccmax
Current (A)
0.001
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
VccASW
V
c
cSPI
V
cDSW3_3 0.001
c
1.05
3
.
3.3
0.903
3
0.01
1.8 0.002VCCDFTERM
3.3VccR TC 2 (mA)
3.3VccS us3_3
3.3VccS usHDA
0.095
0.01
VccVRM 1.5 0.167
1.05VccClkDMI 0.07
1.05VccSSC
VccDIFFCLKN 0.055
1
05
.
VccALVDS 3.3
0.095
0.001
1.8VccT X_LVDS 0.04
+
1
.05V_RUN
+
V
1 2
195 0.022_0805_ 1%@
195 0.022_0805_ 1%@
H
H
R
R
A A
5
CCAPLL_FDI
+
.5V_RUN
1
R
R
4
12
197 0_0603_5%~D@
197 0_0603_5%~D@
H
H
+
1.05V_+1.5V_1.8V_RUN
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
3
2
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
itle
Title
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
H (6/8)
C
C
C
H (6/8)
H (6/8)
L
L
L
-7781
A
A
A
-7781
-7781
1
1
1
9 6
9 6
1
9 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
5
+1
.05V_RUN
+
.3V_ALW_PCH
3
+
.3V_ALW2
3
D D
+
.05V_RUN
1
C C
+
.3V_RUN
3
1 2
215 0.022_0805_1%
H
H
215 0.022_0805_1%
R
R
N
ote: If EMI concern, pop
R
R
R
R
@
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
with SHI00008S0L, 10UH +-20%
N
ote: Place VCCDIFFCLKN with a trace
2
1
H
H
201 0_0402_5%~D@
201 0_0402_5%~D@
2
1
253 0_0402_5%~D@
253 0_0402_5%~D@
H
H
L
L
H
H
3
3
+
1
.05V_M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
+
1
@
@
C
C
2
H
H
58
58
1
2
.05V_RUN
+
.3V_RUN_VCC_CLKF33
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@
@
C
C
H73
H
73
specially for XCLK_RCOMP (RH100.2)
B B
+
1
.05V_M
H
H
248 0.022_0805_1%@
248 0.022_0805_1%@
R
R
A A
+
1
1 2
.05V_RUN
+
1
+
.05V_RUN_VTT
1
.05V_M_VCCSUS
5
+
.05V_RUN
1
1
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
L
L
H
H
6
6
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
1 2
7
7
H
H
L
L
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
C
C
85
85
H
H
220U_D2_2VY_R15M
220U_D2_2VY_R15M
1
+
+
2
C
C
C
C
H
H
94
94
1
C
C
55
55
H
H
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
H
H
74
74
2
1
79
H
H
79
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
H96
96
H
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
86
86
H
H
C
C
2
+
.05V_RUN_VCCA_A_DPL
1
+
.05V_RUN_VCCA_B_DPL
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
1
+
+
H
H
92
92
2
2
R
R
H
H
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
220U_D2_2VY_R15M
220U_D2_2VY_R15M
1 2
200 0.022_0805_1%@
200 0.022_0805_1%@
@
@
H
H
57
57
C
C
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C
C
1
1
H
H
64
64
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
C
C
H
H
67
67
2
2
78
H
H
78
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
H84
H84
2
1
87
87
CH
CH
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
C
C
1
H
H
H
H
95
95
93
93
2
4
+
1
2
1
@
@
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C
C
H
H
65
65
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
H
H
68
68
2
+
.05V_+1.5V_1.8V_RUN
1
+
.05V_RUN_VCCA_A_DPL
1
+
1.05V_RUN_VCCA_B_DPL
H
H
81
81
+
+
1
C
C
83
83
H
H
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+
R
TC_CELL
1
2
4
V
CCACLK
+
V
CCDSW3_3
+
P
CH_VCCDSW
+
3
.3V_RUN_VCC_CLKF33
+
V
CCAPLL_CPY_PCH
+
CCSUS1
V
61
H
H
61
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C
C
H
H
69
69
+
V
CCRTCEXT
V
CCSST
.05V_M_VCCSUS
1
@
@
1
88
88
89
89
H
H
H
H
C
C
C
C
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
U
U
4J
4J
H
H
AD49
V
CACLK
C
T16
V
CDSW3_3
C
V12
D
C
PSUSBYP
T38
V
C
C3_3[5]
BH23
V
CAPLLDMI2
C
AL29
V
CIO[14]
C
AL24
D
C
PSUS[3]
AA19
V
C
CASW[1]
AA21
V
C
CASW[2]
AA24
V
C
CASW[3]
AA26
V
C
CASW[4]
AA27
V
CASW[5]
C
AA29
V
CASW[6]
C
AA31
V
C
CASW[7]
AC26
V
C
CASW[8]
AC27
V
C
CASW[9]
AC29
V
CASW[10]
C
AC31
V
CASW[11]
C
AD29
V
CASW[12]
C
AD31
V
CASW[13]
C
W21
V
CASW[14]
C
W23
V
CASW[15]
C
W24
V
CASW[16]
C
W26
V
CASW[17]
C
W29
V
CASW[18]
C
W31
V
CASW[19]
C
W33
V
CASW[20]
C
N16
D
C
PRTC
Y49
V
C
CVRM[4]
BD47
V
C
CADPLLA
BF47
V
C
CADPLLB
AF17
V
CIO[7]
C
AF33
V
C
CDIFFCLKN[1]
AF34
V
C
CDIFFCLKN[2]
AG34
V
C
CDIFFCLKN[3]
AG33
V
CSSC
C
V16
D
C
PSST
T17
D
C
PSUS[1]
V19
D
C
PSUS[2]
BJ8
V
_
PROC_IO
A22
V
CRTC
C
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
C
C
90
H
H
90
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
3
P
P
WER
WER
O
O
N26
V
CIO[29]
C
P26
V
C
CIO[30]
P28
V
C
CIO[31]
T27
V
CIO[32]
C
T29
V
C
CIO[33]
CSUS3_3[7]
CSUS3_3[8]
CSUS3_3[9]
CSUS3_3[6]
V
C
CIO[34]
V
REF_SUS
5
D
PSUS[4]
C
CSUS3_3[1]
V
REF
5
CSUS3_3[3]
CSUS3_3[4]
CSUS3_3[5]
V
C3_3[1]
C
V
C
C3_3[8]
V
C3_3[4]
C
V
C
C3_3[2]
V
C
CIO[5]
V
CIO[12]
C
V
C
CIO[13]
V
CIO[6]
C
CAPLLSATA
V
C
CVRM[1]
V
CIO[2]
C
V
CIO[3]
C
V
CIO[4]
C
C
CASW[22]
C
CASW[23]
CASW[21]
C
CCSUSHDA
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
V
C
V
C
V
C
V
CSUS3_3[10]
C
V
C
V
C
V
CCSUS3_3[2]
V
C
V
C
V
C
lock and Miscellaneous
lock and Miscellaneous
C
C
CI/GPIO/LPC
CI/GPIO/LPC
P
P
V
C
ATA USB
ATA USB
S
S
V
V
ISC
ISC
M
M
DA
DA
H
H
V
V
3
CPURTC
CPURTC
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+
P
CH_V5REF_SUS
+
CCA_USBSUS
V
+
CH_V5REF_RUN
P
1
2
1
C
C
56
56
H
H
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
59
59
H
H
C
C
2
1
70
70
H
H
C
C
1U_0603_10V7K~D
1U_0603_10V7K~D
2
1
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+
V
+
1
.05V_+1.5V_1.8V_RUN
91
91
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+
3
H76
H
76
CCSATAPLL
+
1
60
60
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
66
66
H
H
C
C
2
1
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
.3V_RUN
1
H
H
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
.05V_RUN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
72
72
1
2
82
82
2
A
L
W_ON_3.3V#<42>
+
1
.05V_RUN
+
3
.3V_ALW_PCH
+
.3V_ALW_PCH
3
+
75
75
H
H
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
77
H
H
77
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
@
@
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
+
.05V_M
1
+
.3V_ALW_PCH
3
+
.3V_ALW_PCH
3
C
RB 0.7 RH208,RH213 trace width 20mil.
3
.3V_RUN
+
.3V_RUN
3
+
1
.05V_RUN
5
5
H
H
L
L
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1
C
C
80
H
H
80
+
.05V_RUN
1
+
.3V_ALW_PCH
3
1
V_ALW
1
279
279
RH
RH
100K_0402_5%~D
100K_0402_5%~D
2
5
V
_ALW_PCH_ENABLE
13
D
D
6
6
H
H
Q
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
2
+5
+
V_ALW_PCH
5
H
H
R
R
10_0402_1%~D
10_0402_1%~D
R
R
H
H
10_0402_1%~D
10_0402_1%~D
H
H
4
4
Q
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
D
1 3
G
G
2
1
2
+
.3V_ALW_PCH
3
1
+
5
V_RUN
2
12
+
+
1
.05V_RUN
V
21
1
2
+
.3V_RUN
3
21
1
2
CCA_USBSUS
208
208
213
213
D
D
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
CH
CH
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DH
DH
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+
P
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
P
P
P
H (7/8)
C
C
C
H (7/8)
H (7/8)
L
L
L
-7781
-7781
A
A
A
-7781
1
WR_SRC_S
+P
2
G
G
@
@
D
E
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+5
S
S
1
98
98
H
H
C
C
2
107
107
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
H
H
C
C
3300P_0402_50V7K~D
3300P_0402_50V7K~D
2
2
H
H
+
P
CH_V5REF_SUS
63
63
3
3
CH_V5REF_RUN
C
C
71
H
H
71
1U_0603_10V7K~D
1U_0603_10V7K~D
1
@
@
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
2
2
0 6
0 6
0 6
V_ALW_PCH
12
278
278
H
H
R
R
H
H
62
62
o
o
o
f
f
f
20K_0402_5%~D
20K_0402_5%~D
1
1
1
.
0
0
0
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
D D
C C
B B
A A
5
U
U
H
H
4H
4H
H5
S[0]
S
V
AA17
V
SS[1]
AA2
V
S
S[2]
AA3
V
S
S[3]
AA33
S
S[4]
V
AA34
V
S
S[5]
AB11
V
S
S[6]
AB14
V
S[7]
S
AB39
V
S[8]
S
AB4
V
S[9]
S
AB43
V
S[10]
S
AB5
V
S[11]
S
AB7
V
SS[12]
AC19
V
S
S[13]
AC2
V
S
S[14]
AC21
V
S
S[15]
AC24
V
S[16]
S
AC33
V
S[17]
S
AC34
V
S[18]
S
AC48
V
S[19]
S
AD10
V
S[20]
S
AD11
V
S
S[21]
AD12
V
S
S[22]
AD13
V
S
S[23]
AD19
V
S[24]
S
AD24
V
S[25]
S
AD26
V
S[26]
S
AD27
V
SS[27]
AD33
V
S
S[28]
AD34
V
S
S[29]
AD36
V
S
S[30]
AD37
V
S[31]
S
AD38
S
S[32]
V
AD39
V
S[33]
S
AD4
V
S[34]
S
AD40
V
S
S[35]
AD42
V
S[36]
S
AD43
V
S[37]
S
AD45
V
S[38]
S
AD46
V
S[39]
S
AD8
S
S[40]
V
AE2
S
S[41]
V
AE3
S
S[42]
V
AF10
V
S
S[43]
AF12
V
S[44]
S
AD14
S[45]
S
V
AD16
V
S
S[46]
AF16
V
S
S[47]
AF19
V
S[48]
S
AF24
V
S[49]
S
AF26
V
S[50]
S
AF27
V
S
S[51]
AF29
V
S
S[52]
AF31
V
S
S[53]
AF38
V
S[54]
S
AF4
V
SS[55]
AF42
V
S
S[56]
AF46
V
S[57]
S
AF5
S[58]
S
V
AF7
V
S[59]
S
AF8
V
S[60]
S
AG19
V
S[61]
S
AG2
V
S[62]
S
AG31
V
S[63]
S
AG48
V
S
S[64]
AH11
V
S
S[65]
AH3
V
S
S[66]
AH36
V
SS[67]
AH39
V
S
S[68]
AH40
V
S[69]
S
AH42
V
S[70]
S
AH46
V
SS[71]
AH7
V
S
S[72]
AJ19
V
S[73]
S
AJ21
S
S[74]
V
AJ24
S[75]
S
V
AJ33
V
S
S[76]
AJ34
V
S[77]
S
AK12
V
S[78]
S
AK3
V
S[79]
S
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
4
AK38
V
S[80]
S
AK4
V
S[81]
S
AK42
V
S[82]
S
AK46
V
SS[83]
AK8
V
S
S[84]
AL16
V
S
S[85]
AL17
V
S[86]
S
AL19
V
S[87]
S
AL2
V
SS[88]
AL21
V
S
S[89]
AL23
V
S
S[90]
AL26
V
S[91]
S
AL27
V
S[92]
S
AL31
V
S
S[93]
AL33
S[94]
S
V
AL34
S[95]
S
V
AL48
V
S[96]
S
AM11
V
SS[97]
AM14
V
S
S[98]
AM36
V
S
S[99]
AM39
V
S[100]
S
AM43
S[101]
S
V
AM45
V
S
S[102]
AM46
V
S
S[103]
AM7
V
S[104]
S
AN2
V
S[105]
S
AN29
V
SS[106]
AN3
V
S
S[107]
AN31
V
S[108]
S
AP12
V
S[109]
S
AP19
V
S
S[110]
AP28
V
S
S[111]
AP30
V
S[112]
S
AP32
V
S
S[113]
AP38
V
S
S[114]
AP4
S
S[115]
V
AP42
V
S[116]
S
AP46
V
S
S[117]
AP8
V
S
S[118]
AR2
V
S[119]
S
AR48
V
SS[120]
AT11
V
S
S[121]
AT13
V
S
S[122]
AT18
V
S[123]
S
AT22
V
S
S[124]
AT26
V
S
S[125]
AT28
V
S[126]
S
AT30
V
S
S[127]
AT32
V
S
S[128]
AT34
S[129]
S
V
AT39
S[130]
S
V
AT42
V
S
S[131]
AT46
V
S[132]
S
AT7
V
S[133]
S
AU24
V
S
S[134]
AU30
V
S[135]
S
AV16
V
S[136]
S
AV20
S
S[137]
V
AV24
S
S[138]
V
AV30
S
S[139]
V
AV38
S
S[140]
V
AV4
S[141]
S
V
AV43
S
S[142]
V
AV8
S[143]
S
V
AW14
S[144]
S
V
AW18
S
S[145]
V
AW2
S[146]
S
V
AW22
S
S[147]
V
AW26
S[148]
S
V
AW28
S
S[149]
V
AW32
S
S[150]
V
AW34
S
S[151]
V
AW36
S
S[152]
V
AW40
S[153]
S
V
AW48
S
S[154]
V
AV11
SS[155]
V
AY12
S[156]
S
V
AY22
S
S[157]
V
AY28
S[158]
S
V
4
3
4I
4I
H
H
U
U
AY4
S
S[159]
V
AY42
SS[160]
V
AY46
S[161]
S
V
AY8
S[162]
S
V
B11
S[163]
S
V
B15
S
S[164]
V
B19
S
S[165]
V
B23
S
S[166]
V
B27
S[167]
S
V
B31
S
S[168]
V
B35
S
S[169]
V
B39
S
S[170]
V
B7
S
S[171]
V
F45
V
S
S[172]
BB12
S[173]
S
V
BB16
S[174]
S
V
BB20
S[175]
S
V
BB22
S[176]
S
V
BB24
S[177]
S
V
BB28
S
S[178]
V
BB30
S
S[179]
V
BB38
S
S[180]
V
BB4
S
S[181]
V
BB46
S
S[182]
V
BC14
S
S[183]
V
BC18
S
S[184]
V
BC2
S
S[185]
V
BC22
S[186]
S
V
BC26
S[187]
S
V
BC32
S[188]
S
V
BC34
S[189]
S
V
BC36
S[190]
S
V
BC40
S[191]
S
V
BC42
S[192]
S
V
BC48
S[193]
S
V
BD46
S[194]
S
V
BD5
S[195]
S
V
BE22
S[196]
S
V
BE26
S[197]
S
V
BE40
S
S[198]
V
BF10
S[199]
S
V
BF12
S
S[200]
V
BF16
S
S[201]
V
BF20
S[202]
S
V
BF22
S
S[203]
V
BF24
S
S[204]
V
BF26
S
S[205]
V
BF28
S
S[206]
V
BD3
S
S[207]
V
BF30
S[208]
S
V
BF38
S
S[209]
V
BF40
S
S[210]
V
BF8
S[211]
S
V
BG17
S[212]
S
V
BG21
S
S[213]
V
BG33
S[214]
S
V
BG44
S[215]
S
V
BG8
S
S[216]
V
BH11
S[217]
S
V
BH15
S[218]
S
V
BH17
S[219]
S
V
BH19
S[220]
S
V
H10
V
S[221]
S
BH27
S[222]
S
V
BH31
S[223]
S
V
BH33
S[224]
S
V
BH35
S[225]
S
V
BH39
S[226]
S
V
BH43
S
S[227]
V
BH7
S
S[228]
V
D3
S
S[229]
V
D12
S
S[230]
V
D16
S
S[231]
V
D18
S
S[232]
V
D22
S[233]
S
V
D24
S[234]
S
V
D26
S
S[235]
V
D30
S[236]
S
V
D32
S[237]
S
V
D34
V
S
S[238]
D38
V
S
S[239]
D42
V
S[240]
S
D8
V
S[241]
S
E18
V
SS[242]
E26
V
S
S[243]
G18
V
S
S[244]
G20
V
S[245]
S
G26
V
S
S[246]
G28
V
S
S[247]
G36
V
S
S[248]
G48
V
S[249]
S
H12
V
S[250]
S
H18
V
S
S[251]
H22
V
S
S[252]
H24
V
S[253]
S
H26
V
S[254]
S
H30
V
SS[255]
H32
V
S[256]
S
H34
V
S[257]
S
F3
V
S[258]
S
BD82QM77 QPRE C1_BGA989~D
BD82QM77 QPRE C1_BGA989~D
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
H46
V
S[259]
S
K18
V
S
S[260]
K26
V
S
S[261]
K39
V
S
S[262]
K46
V
S
S[263]
K7
S[264]
S
V
L18
S[265]
VS
L2
S[266]
VS
L20
S
S[267]
V
L26
S
S[268]
V
L28
S
S[269]
V
L36
S
S[270]
V
L48
S
S[271]
V
M12
S
S[272]
V
P16
S
S[273]
V
M18
S
S[274]
V
M22
S
S[275]
V
M24
S
S[276]
V
M30
S
S[277]
V
M32
S
S[278]
V
M34
S
S[279]
V
M38
S
S[280]
V
M4
S
S[281]
V
M42
S[282]
VS
M46
S
S[283]
V
M8
S
S[284]
V
N18
S[285]
VS
P30
S[286]
VS
N47
V
S
S[287]
P11
S[288]
VS
P18
S[289]
VS
T33
S[290]
VS
P40
S[291]
VS
P43
S[292]
VS
P47
VS
S[293]
P7
S[294]
VS
R2
VS
S[295]
R48
VS
S[296]
T12
VS
S[297]
T31
VS
S[298]
T37
V
S[299]
S
T4
VS
S[300]
W34
V
S[301]
S
T46
V
S[302]
S
T47
V
S[303]
S
T8
V
S
S[304]
V11
V
S
S[305]
V17
V
S
S[306]
V26
V
S
S[307]
V27
V
S
S[308]
V29
V
S
S[309]
V31
V
S[310]
S
V36
V
S[311]
S
V39
V
S[312]
S
V43
V
S
S[313]
V7
V
S
S[314]
W17
V
S
S[315]
W19
V
S[316]
S
W2
V
S
S[317]
W27
V
S
S[318]
W48
V
S
S[319]
Y12
V
S[320]
S
Y38
V
S[321]
S
Y4
V
S[322]
S
Y42
V
S
S[323]
Y46
V
S
S[324]
Y8
V
S[325]
S
BG29
V
S[328]
S
N24
V
S
S[329]
AJ3
V
S
S[330]
AD47
V
S
S[331]
B43
V
S[333]
S
BE10
V
S[334]
S
BG41
V
S[335]
S
G14
V
S
S[337]
H16
V
S
S[338]
T36
V
S
S[340]
BG22
V
S[342]
S
BG24
V
S
S[343]
C22
V
S
S[344]
AP13
V
S[345]
S
M14
V
S
S[346]
AP3
V
S
S[347]
AP1
V
S[348]
S
BE16
V
S
S[349]
BC16
V
S
S[350]
BG28
V
S
S[351]
BJ28
V
S[352]
S
2
1
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
H (8/8)
C
C
C
H (8/8)
H (8/8)
L
L
L
-7781
-7781
A
A
A
-7781
2
2
2
1 6
1 6
1
1 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
0
.
.
.
5
Place under CPU
Place C266 close to the Q12 as possible
C
@
@
D D
100P_0402_50V8J~D
100P_0402_50V8J~D
C C
100P_0402_50V8J~D
100P_0402_50V8J~D
B B
2
2
2
66
66
C
C
1
(1) DP2/DN2 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14
(2) DP4/DN4 for Skin on Q13, place Q13 close to Vcore VR choke.
1
2
2
72
@
72
@
C
C
2
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
C
2
B
B
E
E
Q
Q
1
1
2
2
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
100P_0402_50V8J~D
100P_0402_50V8J~D
1
E
E
31
@
H
_
2
+
THERMTRIP#<7>
@
C
C
2
2
77
77
1
.05V_RUN_VTT
B
B
2
3
1
1
3
Q
Q
C
C
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
R
R
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
PMST3904_SOT323-3~D
PMST3904_SOT323-3~D
C
C
2
B
B
E
E
3 1
4
4
1
1
Q
Q
99
99
3
3
M_DIODE1_P_4022
RE
R
E
M_DIODE1_N_4022
R
M_DIODE2_P_4022
E
R
M_DIODE2_N_4022
E
+
.3V_M
3
1
2
C
C
2
B
B
E
E
1
1
6
6
Q
Q
3 1
3
3
R
R
8.2K_0402_5%~D
8.2K_0402_5%~D
95
95
T
H
ERMATRIP2#
1
2
4
+
F
AN1_VOUT
+
5
V_RUN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
0
0
C
C
U_0805_10V6K~D
U_0805_10V6K~D
C276
C276
1
1
2
2
75
75
+
.3V_RUN
3
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
2
2
78
78
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
1
3
3
05
05
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
639 0_0603_5%~D@
639 0_0603_5%~D@
1
1
R
R
C
C
7
7
38
38
+
C
C
70 2200P_0402_50 V7K~D
70 2200P_0402_50 V7K~D
2
2
2
2
71 2200P_0402_50 V7K~D
71 2200P_0402_50 V7K~D
C
C
M
X8731_IINP<52>
A
12
04
04
4
4
R
R
10K_0402_5%~D
10K_0402_5%~D
SMSC request
1 2
3.3V_M
1 2
1
3
R
R
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
D
D
1
2
2
2
2 1
+
3
1 2
89 10K _0402_5%~D
3
3
89 10K _0402_5%~D
R
R
2
P
C
H_PWRGD#<4 0>
F
N1_DET#
A
F
A
N1_TACH_FB
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C
C
2
2
19
19
.3V_RUN_EMC_VDDL
V
DD_PWRGD
R
R
R
R
V
1 2
R
R
91 1K_0402_5%~D
91 1K_0402_5%~D
3
3
+
R
TC_CELL
MOLEX_53398-0471~D
MOLEX_53398-0471~D
EM_DIODE1_N_4022
M_DIODE1_P_4022
E
E
M_DIODE2_N_4022
E
M_DIODE2_P_4022
V
C
12
3
3
874.7K_0402_5%~D
874.7K_0402_5%~D
R
R
ET_4021
S
F
A
N1_TACH_FB
F
A
N1_DET#
3
V
_PWROK#
F
F
AN1
AN1
J
J
1
1
2
2
5
3
1
3
G
6
4
2
G
4
CONN@
CONN@
U
U
9
9
2
V
D
D_H
3
V
D_H
D
6
D
D_L
V
13
D
D_PWRGD
V
23
1/THERM
N
D
24
D
P
1/VREF_T
26
D
2/DP4
N
27
2/DN4
P
D
30
C
/
N
29
C
/
N
P2
31
C
P
V
25
N
I
V
28
ET
S
V
10
A
CH/GPIO1
T
11
ST3
E
T
15
P
IO3/PWM/THERMTRIP_SIO
G
12
V
_PWROK#
3
16
T
C_PWR3V
R
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
MC4021-1-EZK-TR_QFN32_5X5~D
MC4021-1-EZK-TR_QFN32_5X5~D
E
E
1
C
C
2
2
74
74
2
T
H
ERMTRIP2#
Y
S_SHDN#
S
WER_SW#
O
P
C
AVAIL_CLR
A
T
F_INT#/BC_IRQ#
A
F
F
CLK/BC_CLK
M
S
M
DATA/BC_DATA
S
D
DR_MODE/XEN
A
2
N_OUT
A
AN_OUT
E
T
E
T
1
+
.3V_M
3
B
C
_INT#_EMC4022
F
N1_TACH_FB
A
F
N1_DET#
A
T
HERMATRIP2#
17
18
/
C
N
19
P
WER_SW#
O
20
21
B
_INT#_EMC4022
C
9
5
4
8
7
1
D
D
V
32
14
ST1
22
ST2
33
S
S
V
+
V
+
CC_4022
A
DDR_XEN
+
AN1_VOUT
F
1 2
12
R
R
10K_0402_5%~D
10K_0402_5%~D
S
M
A
CAV_IN <40,52,53>
B
C
_INT#_EMC4022 <40>
3
3
R
R
4
4
03
03
SC request
1 2
R
R
3
3
90 47K_0402_1%~D@
90 47K_0402_1%~D@
B
_CLK_EMC4022 <40>
C
B
_DAT_EMC4022 <40>
C
+
CC_4022
V
934.7K_0402_5%~D
934.7K_0402_5%~D
2
1
85 10K_0402 _5%~D
85 10K_0402 _5%~D
3
3
R
R
2
R
R
R
R
1
26 10K_0402 _5%~D
26 10K_0402 _5%~D
4
4
12
02 10K_0402 _5%~D
4
4
02 10K_0402 _5%~D
T
ERM_STP# <45>
H
+
TC_CELL
R
+
3
.3V_M
88
88
3
3
R
R
22_0402_5%~D
22_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C
C
C
C
2
2
1
1
73
73
179
179
2
12
1
2
+
R
V
ET_4021
12
R
R
406
4
06
1.24K_0402_1%~D
1.24K_0402_1%~D
S
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
P
WER_SW#
O
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
2
2
82
82
2
TC_CELL
5
U
U
0
1
1
0
4
O
3
2
1
C
C
81 0.1U_0402_25V6K ~D
81 0.1U_0402_25V6K ~D
2
2
1
P
B
2
A
G
D
O
CK_PWR_SW # <40>
P
WER_SW_IN# <40>
O
Tp=93degree
A A
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
5
4
3
2
T
T
Title
tle
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
F
F
F
N & Thermal Sensor
A
A
A
N & Thermal Sensor
N & Thermal Sensor
L
L
L
-7781
A
-7781
-7781
A
A
1
2
2
2
2 61Friday, February 24, 2012
2 6
2 6
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
2
1
B B
P
H_CRT_RED
S
E
L1/SEL2
C
P
H_CRT_GRN
C
P
H_CRT_BLU
C
P
CH_CRT_HSYNC
P
CH_CRT_VSYNC
P
H_CRT_DDC_DAT
C
P
H_CRT_DDC_CLK
C
C
RT_SWITCH
+
.3V_RUN
3
12
R
R
56
56
5
5
4.7K_0402_5%~D
4.7K_0402_5%~D
+
3
.3V_RUN
P
H_CRT_RED<16>
C
P
H_CRT_GRN<16>
C
P
H_CRT_BLU<16>
C
P
H_CRT_HSYNC<16>
C
P
H_CRT_VSYNC<16>
C
P
H_CRT_DDC_DAT<16>
C
P
H_CRT_DDC_CLK<16>
C
C
R
T_SWITCH<39>
0
1
S
W
U
U
1
R
2
G
5
B
6
H
_
7
V
_HOURCE
9
S
D
10
S
C
30
S
E
29
T
E
8
R
e
3
G
ND
11
G
N
28
G
N
31
G
N
33
G
P
TS3V713ELRTGR _TQFN32_6X3~D
TS3V713ELRTGR _TQFN32_6X3~D
S
Chanel
o
MBA=B1
APR/SPR
A=B2
for MB/DOCK
+
V_RUN
5
8
8
1
1
SOURCE
A_SOURCE
L_SOURCE
L
ST
served
D
D
D
AD
urce
5
H
1
V
1
H
2_OUT
V
2
V VDD
V
V
V
_OUT
_OUT
S
D
S
_OUT
S
D
S
16
4
D
D
23
D
D
32
D
D
R
G
B
A1
L1
C
R
G
B
A2
C
L2
RED_CRT
7
2
1
GREEN_CRT
5
2
1
B
L
2
2
1
HSYNC_BUF
20
VSYNC_BUF
18
DAT_DDC2_CRT
12
CLK_DDC2_CRT
14
R
E
6
2
2
G
R
4
2
2
B
L
2
1
2
H
S
19
V
S
17
D
A
13
C
L
15
UE_CRT
D_DOCK
EEN_DOCK
UE_DOCK
YNC_DOCK
YNC_DOCK
T_DDC2_DOCK
K_DDC2_DOCK
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
@
@
C
C
3
3
32
32
2
+
.3V_RUN
3
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
@
@
C
C
3
3
33
33
2
R
E
D_CRT <30>
G
R
EEN_CRT <30>
B
UE_CRT <30>
L
H
YNC_BUF <30>
S
V
S
YNC_BUF <30>
D
A
T_DDC2_CRT <30>
C
K_DDC2_CRT <30>
L
R
E
D_DOCK <38>
G
R
EEN_DOCK <38>
B
UE_DOCK <38>
L
H
SYNC_DOCK <38>
V
S
YNC_DOCK <38>
D
T_DDC2_DOCK <38>
A
C
K_DDC2_DOCK <38>
L
+
.3V_RUN
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
3
3
34
34
2
2
+
V_RUN
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
C
C
3
3
3
3
36
35
35
36
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
3
3
39
39
2
A A
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
ompal Electronics, Inc.
o
o
T
T
tle
Title
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
1
Date: Sheet
mpal Electronics, Inc.
C
C
C
T/Video switch
R
R
R
T/Video switch
T/Video switch
L
L
L
-7781
-7781
A
A
A
-7781
2
2
2
3 6
3 6
3 6
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
J
J
LVDS1
LVDS1
B
ATT_WHITE_LED
B
TT_YELLOW_LED
A
B
R
EATH_WHITE_LED
D D
C C
SP_ON/OFF#
I
D
NNTST_GND
O
C
L
L
L
V
V
L
46
ND6
G
M
45
ND5
G
M
44
ND4
G
M
43
G
ND3
M
42
ND2
G
M
41
G
ND1
M
ACES_59003-0400C-001
ACES_59003-0400C-001
CONN@
CONN@
B
A_PWM_LVDS
I
G
V
R
_SRC
V
_SRC
R
V
_SRC
R
P
V
R
_GND
V
R
_GND
V
R
_GND
C
D_B_CLK+
D_B_CLK-
C
G
L
DS_B2+
V
L
DS_B2-
V
L
DS_B1+
V
L
DS_B1-
V
L
VDS_B0+
L
V
DS_B0-
G
DS_A_CLK+
DS_A_CLK-
G
DS_A2+
V
L
L
DS_A2-
V
L
V
DS_A1+
V
DS_A1-
L
VDS_A0+
L
L
VDS_A0-
ID_DATA
D
E
E
D
ID_CLK
B
V
EDID
_
L
D_VDD
C
C
D_VDD
L
O
NNTST
C
12
1
D
N
2
3
4
5
6
7
8
C
N
9
10
M
W
11
12
13
14
15
16
17
ND
18
19
20
21
22
23
24
D
N
25
26
27
N
D
28
29
30
31
32
33
34
35
36
I
ST
37
38
39
40
137
137
1
1
R
R
10K_0402_5%~D
10K_0402_5%~D
1 2
46 0.1U_0603_50V7K~D
46 0.1U_0603_50V7K~D
C2
C2
1 2
92 BLM 18BB221SN1D_2P~D
92 BLM 18BB221SN1D_2P~D
E
E
L
L
L
D
DC_DATA_PCH
L
D
DC_CLK_PCH
L
C
D_TST
6
6
6
6
D
D
21
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
6
6
8
8
D
D
21
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
+
5
+
5
+
3
+
L
V_ALW for panel side LED power
V_ALW
B
TT_WHITE_LED <43>
A
B
TT_YELLOW_LED <43>
A
B
REATH_WHITE_LED <43>
+
L_PWR_SRC
B
D
SP_ON
I
B
A_PWM_LVDS
I
L
D_B2+_PCH < 16>
C
L
D_B2-_PCH <16>
C
L
CD_B1+_PCH <16>
L
C
D_B1-_PCH <16>
L
C
D_B0+_PCH < 16>
L
C
D_B0-_PCH <16>
L
D_A2+_PCH < 16>
C
L
C
D_A2-_PCH <16>
L
D_A1+_PCH < 16>
C
L
C
D_A1-_PCH <16>
L
C
D_A0+_PCH < 16>
L
C
D_A0-_PCH <16>
L
DC_DATA_PCH <16>
D
L
D
DC_CLK_PCH <16>
L
C
D_TST <39>
.3V_RUN
CDVDD
L
C
D_CBL_DET# <17>
B
I
A_PWM_PCH <16>
B
I
A_PWM_EC <40>
4
P
A
NEL_HDD_LED <43>
5P_0402_50V8C~D
5P_0402_50V8C~D
5P_0402_50V8C~D
5P_0402_50V8C~D
1
1
@
@
C
C
4
4
0
0
2
2
5P_0402_50V8C~D
5P_0402_50V8C~D
5P_0402_50V8C~D
5P_0402_50V8C~D
1
1
@
@
C
C
4
4
2
2
2
2
L
C
D_BCLK+_PCH <16>
L
C
D_BCLK-_PCH <16>
@
@
C
C
4
4
1
1
L
C
D_ACLK+_PCH <16>
L
CD_ACLK-_PCH <16>
@
@
C
C
4
4
3
3
D
I
SP_ON
12
R
R
138
1
1
138
100K_0402_5%~D
100K_0402_5%~D
+
3
.3V_RUN
1
R
R
59 2.2K_0402_5%~D
59 2.2K_0402_5%~D
1
1
1 2
60 2.2K_0402_5%~D
1
1
60 2.2K_0402_5%~D
R
R
P
lace near to JLVDS1
+
L
CDVDD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
1
2
2
98
98
2
C
ose to JLVDS1.42,43
l
D
D
7
7
6
6
21
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
D
D
6
6
9
9
1
2
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
2
L
DC_CLK_PCH
D
L
DC_DATA_PCH
D
3
+
3
.3V_RUN
1
2
C
ose to JLVD1.41
l
P
NEL_BKEN_PCH <16>
A
P
NEL_BKEN_EC <3 9>
A
2
LCD Power
WR_SRC_S
+3.3V_ALW
+LCDVDD
130_0402_1%~D
130_0402_1%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1
R
R
413
413
2
61
Q
Q
1
1
9A
9A
2
D
D
6
6
L
C
D_VCC_TEST_EN<39>
E
VDD_PCH<16,39>
N
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
2
2
43
43
2
1
3
B
B
AT54CW_SOT323-3~D
AT54CW_SOT323-3~D
E
_LCDPWR
N
2
Q
Q
PDTC124EU_SC70-3~D
PDTC124EU_SC70-3~D
40mil
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
C
C
2
2
97
97
2
E
0
0
2
2
_INVPWR<40>
N
+P
10K_0402_5%~D
10K_0402_5%~D
12
R
R
4
4
14
14
5
13
+
PWR_SRC
12
4
4
22
22
R
R
100K_0402_5%~D
100K_0402_5%~D
P
1 2
R
R
23 4 7K_0402_5%~D
4
4
23 4 7K_0402_5%~D
P
anel backlight power control by EC
1
4
4
12
12
R
R
470K_0402_5%~D
470K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
1
1
9B
9B
4
FDC654P-G_SSOT-6~D
FDC654P-G_SSOT-6~D
4 5
R_SRC_ON
W
E
N
_INVPWR
CDVDD
+L
4 5
4.7M_0402_5%~D
4.7M_0402_5%~D
12
R
R
1
1
632
632
1
2
2
1
Q
Q
D
D
S
S
G
G
3
Q
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
D
1
1
1
1
8
8
Q
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
S
S
6
2
1
G
G
3
0.022U_0402_25V7K~D
0.022U_0402_25V7K~D
1
C
C
2
2
93
93
2
4
0
1
2
S
S
3
F
D
C654P: P CHANNAL
mil
C
C
96
2
2
96
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
6
2
1
2
2
2
2
G
G
2
+3
.3V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
+
B
L_PWR_SRC
C
C
2
2
92
92
+
C
F
or Webcam
B B
3
3
2
2
Q
+
C
AMERA_VDD
10
10
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
U_0805_10V6K~D
U_0805_10V6K~D
C300
C300
C
C
1
1
299
299
2
2
C
C
C
W
ebcam PWR CTRL
A A
5
C
D_OFF<39>
PMV65XP_SOT23-3~D
PMV65XP_SOT23-3~D
D_OFF
Q
D
D
1 3
2
S
S
G
G
+
.3V_RUN
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
1
3
3
01
01
2
J
J
JST_BM08B-SRSS-TB1-LF-SN~D
JST_BM08B-SRSS-TB1-LF-SN~D
CONN@
CONN@
U
BP12+<17>
S
U
S
BP12-<17>
4
AMERA_VDD
C
C
AM1
AM1
C
A
0
U
S
U
S
BP12+
BP12-
M_MIC_CBL_DET#
U
S
BP12_D+
U
BP12_D-
S
D
IC_CLK
M
D
IC0
M
0
1
1
0
L
L
1
1
4
4
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
1
4
4
27 0 _0402_5%~D@
27 0 _0402_5%~D@
R
R
1
R
R
28 0 _0402_5%~D@
28 0 _0402_5%~D@
4
4
C
A
M_MIC_CBL_DET# <17>
+
V_RUN
5
10K_0402_5%~D
D
M
IC_CLK <29>
D
MIC0 <29>
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
2
3
P
P
D
D
ESD5V0U2BT_SOT23-3~D
ESD5V0U2BT_SOT23-3~D
8
8
1
1
@
@
@
@
C
C
C
C
1
1
1
1
207
206
206
207
2
2
1
T
O
UCH_SCREEN_PD#<39>
U
BP12_D+
2
2
3
3
2
2
S
U
BP12_D-
S
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
10K_0402_5%~D
12
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
2
3
5
4
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
G
1
1
G
2
w
a
it CIS symbol
+
V_TSP
5@
5@
R
R
4
4
31
31
5@
5@
Q
Q
1
1
25A
25A
5@
5@
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
U
U
25B
1
1
25B
Q
Q
2
3
3
2
5@
2
5@
Q
Q
PMV65XP_SOT23-3~D
PMV65XP_SOT23-3~D
D
S
D
S
1 3
G
G
2
S
BP13-<17>
BP13+<17>
S
+
D
V_RUN
5
E
1
2
E
T
ouch Screen Connector
E
3_PAID_TS_DET# (touch screen d etect pin)
is not function al because remo ve trace
inside cable.
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
5@
5@
P
lace close JTCH1
C
C
3
3
06
06
_PAID_TS_DET#<18>
3
2
3
D
D
6
@
6
@
8
8
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
1
+
5
V_TSP
T
T
CH1
CH1
J
J
1
2
3
4
5
6
+
V_TSP
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
5@
5@
1
C
C
3
3
02
8
2
1
G
2
3
4
5
1
6
G
TYCO_1734595-6CONN@
TYCO_1734595-6CONN@
7
02
2
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
tle
Title
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
e
e
e
P & CAM &TS Conn
D
D
D
P & CAM &TS Conn
P & CAM &TS Conn
L
L
L
-7781
-7781
A
A
A
-7781
2
2
2
4 6
4 61Friday, February 24, 2012
1
4 61Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
2
L
L
1
1
00
00
1 2
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
L
L
1
1
9
@
9
T
DSB_PCH_CLK_C
M
T
M
DSB_PCH_CLK<16>
T
M
DSB_PCH_CLK#<16>
B B
T
DSB_PCH_P0< 16>
M
T
DSB_PCH_N0<16>
M
+
3
.3V_RUN
H
MI_CEC
D
1
1
R
R
T
DSB_PCH_P2_C
M
T
M
DSB_PCH_N2_C
T
DSB_PCH_P1_C
M
T
MDSB_PCH_N1_C
T
M
DSB_PCH_P0_C
T
M
DSB_PCH_N0_C
T
M
DSB_PCH_CLK_C
T
DSB_PCH_CLK#_C
M
P
CH_SDVO_CTRLCLK<16>
A A
P
H_SDVO_CTRLDATA<16>
C
H
MIB_PCH_HPD<16>
D
4
4
R
R
4
4
R
R
R
R
4
4
4
4
R
R
4
4
R
R
4
4
R
R
4
4
R
R
4
4
R
R
+
3
.3V_RUN
+
3
.3V_RUN
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
12
165 10K_ 0402_5%~D
165 10K_ 0402_5%~D
52 604_0402_1%
52 604_0402_1%
1 2
50 604_0402_1%
50 604_0402_1%
1 2
48 604_0402_1%
48 604_0402_1%
1 2
49 604_0402_1%
49 604_0402_1%
2
1
54 604_0402_1%
54 604_0402_1%
2
1
53 604_0402_1%
53 604_0402_1%
1 2
56 604_0402_1%
56 604_0402_1%
1 2
55 604_0402_1%
55 604_0402_1%
2
1
R
R
4
4
58 10K_0402_5%~D
58 10K_0402_5%~D
1 2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Q
Q
20A
1
1
20A
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
P
C
61
5
P
3
Q
Q
20B
20B
1
1
1M_0402_5%~D
1M_0402_5%~D
R
R
1
1
168
168
1 2
C
+
.3V_RUN
3
G
G
2
S
S
Q
Q
1
1
21
21
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
H
MI_OB
D
2
G
G
Q
Q
6
2
6
2
H_SDVO_CTRLCLK_R
H_SDVO_CTRLDATA_R
H
MI_HPD_SINK
D
13
D
D
2
T
M
DSB_PCH_P1< 16>
T
MDSB_PCH_N1<16>
13
T
DSB_PCH_P2< 16>
M
D
D
T
DSB_PCH_N2<16>
M
S
S
+
V_HDMI_DDC
1 2
1153 2.2K_0402 _5%~D
1153 2.2K_0402 _5%~D
R
R
1 2
152 2.2K_0402_ 5%~D
152 2.2K_0402_ 5%~D
1
1
R
R
1 2
R
R
1
1
128 20K_0402_5%~D
128 20K_0402_5%~D
5
12
C
C
3
3
53 0 .1U_0402_10V7K~D
53 0 .1U_0402_10V7K~D
52 0 .1U_0402_10V7K~D
52 0 .1U_0402_10V7K~D
3
3
C
C
51 0 .1U_0402_10V7K~D
51 0 .1U_0402_10V7K~D
3
3
C
C
50 0 .1U_0402_10V7K~D
3
3
50 0 .1U_0402_10V7K~D
C
C
47 0 .1U_0402_10V7K~D
47 0 .1U_0402_10V7K~D
3
3
C
C
3
3
46 0 .1U_0402_10V7K~D
46 0 .1U_0402_10V7K~D
C
C
49 0 .1U_0402_10V7K~D
3
3
49 0 .1U_0402_10V7K~D
C
C
48 0 .1U_0402_10V7K~D
3
3
48 0 .1U_0402_10V7K~D
C
C
+
5
V_RUN
T
M
DSB_PCH_CLK#_C
12
T
M
DSB_PCH_P0_C
12
T
M
DSB_PCH_N0_C
12
T
M
DSB_PCH_P1_C
12
T
M
DSB_PCH_N1_C
12
T
DSB_PCH_P2_C
M
12
T
DSB_PCH_N2_C
M
12
RB751VM-40TE-17_SOD323-2~D
RB751VM-40TE-17_SOD323-2~D
12
21
@
@
D
D
6
6
1
1
163
163
R
R
5
5
0_0402_5%~D
0_0402_5%~D
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
@
1
1
2
4
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
@
@
1
4
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
@
@
1
4
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
@
@
1
4
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
9NH_0402HS-9N0EJTS_5%~D
9NH_0402HS-9N0EJTS_5%~D
4
L
L
1
1
01
01
1 2
02
02
L1
L1
1 2
0
0
2
2
L
L
1
4
03
03
1
1
L
L
1 2
05
1
1
05
L
L
1 2
L
L
2
2
2
2
1
4
1
1
04
04
L
L
1 2
07
1
107
L
L
1 2
L
L
2
2
1
1
1
4
1
1
06
06
L
L
1 2
3
2
3
2
3
2
3
T
DSB_CON_CLK
M
2
T
DSB_CON_CLK#
M
3
2
3
2
3
2
3
1
2
T
M
DSB_CON_P0
T
DSB_CON_N0
M
1
2
T
DSB_CON_P1
M
T
DSB_CON_N1
M
1
2
T
M
DSB_CON_P2
T
M
DSB_CON_N2
1
2
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1
C
C
C
C
1
1
1
1
209
209
210
210
2
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1
C
C
C
C
1
1
1
1
211
212
212
211
2
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1
C
C
C
C
1
1
1
1
213
213
214
214
2
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1
C
C
C
C
1
1
1
1
215
215
216
216
2
+5
V_RUN
21
+
21
5
1
B
B
AT1000-7-F_SOT23-3~D
AT1000-7-F_SOT23-3~D
3
C
C
D
D
N
N
4
4
V_RUN_HDMI
0
0
.5A_15V_SMD1812P050TF
.5A_15V_SMD1812P050TF
F
F
2
2
1
+
VDISPLAY_VCC
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C338
C338
1
1
C
0
0
_1206_5%~D
_1206_5%~D
@
@
R
R
5
5
1 2
PCH_SDVO_CTRLDATA_R
PCH_SDVO_CTRLCLK_R
HDMI_CEC
T
DSB_CON_CLK#
M
T
M
DSB_CON_CLK
T
MDSB_CON_N0
T
M
DSB_CON_P0
T
M
DSB_CON_N1
TMDSB_CON_P1
T
DSB_CON_N2
M
T
M
DSB_CON_P2
C
3
3
37
37
2
2
J
J
H
H
DMI1
HDMI_HPD_SINK
D
LL CONFIDENTIAL/PROPRIETARY
E
T
T
Title
tle
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
DMI1
19
H
P
_DET
18
+
5
V
17
D
D
C/CEC_GND
16
S
D
A
15
S
L
C
14
R
served
e
13
C
C
E
12
C
-
K
11
C
_shield
K
10
C
+
K
9
D
0-
8
D
0
_shield
7
D
0+
6
D
1
-
5
D
1
_shield
C
C
C
H
H
H
4
3
2
1
o
o
o
MI port
D
D
D
MI port
MI port
L
L
L
G
D
1
+
D
N
G
D
D
N
2
G
D
N
2
D
_shield
G
D
N
2
D
+
TYCO_2041270-1
TYCO_2041270-1
CONN@
CONN@
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
-7781
A
-7781
-7781
A
A
20
21
22
23
2
2
2
5 61Friday, February 24, 2012
5 6
5 6
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
5
A
X/DDC SW for DPC to E-DOCK
U
U
C
C
57
57
3
D D
D
C_PCH_DOCK_AUX<16>
P
D
P
C C
T
here is a new die for PI3C3125. Sample availabe on May.
D
P
D
D_PCH_DOCK_AUX#<16>
P
B B
D
P
C_PCH_DOCK_AUX#<16>
D
C_DOCK_AUX#<38>
P
D
C_CA_DET<38>
P
A
U
X/DDC SW for DPD to E-DOCK
D_PCH_DOCK_AUX<16>
D
P
D_DOCK_AUX<38>
D
P
D_DOCK_AUX#<38>
3
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
C_DOCK_AUX<38>
12
C
C
3
3
60 0.1U_0402_10V7K ~D
60 0.1U_0402_10V7K ~D
C
C
3
3
67
67
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
12
12
C
C
68 0.1U_0402_10V7K ~D
3
3
68 0.1U_0402_10V7K ~D
D
PC_AUX_C
1
D
P
C_DOCK_AUX
D
C_AUX#_C
P
D
C_DOCK_AUX#
P
D
C_CA_DET
P
D
D_AUX_C
P
D
D_DOCK_AUX
P
D
P
D_AUX#_C
D
D_DOCK_AUX#
P
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
U
0
0
2
2
1
B
0
E
2
A
0
3
B
0
4
B
1
E
5
A
1
6
B
1
7
G
N
D
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+
5
V_RUN
12
C
C
65
65
3
3
5
1
U
U
P
C
N
A2Y
G
TC7SET04FU_SC70-5~D
TC7SET04FU_SC70-5~D
3
U
U
2
2
3
3
1
E
C
0
B
2
3
4
5
6
7
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
V
0
A
B
0
B
1
E
B
1
B
A
1
B
N
D
G
V
C
C
B
E
A
B
B
E
A
B
1
1
2
2
4
C
E
3
3
A
3
B
2
E
2
A
2
B
4
+
3
.3V_RUN
1 2
C
C
3
3
56
56
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
14
1
3
3
2
1
3
1
1
3
1
0
2
9
2
8
2
D
P
C_CA_DET#
14
3
1
2
1
1
1
0
1
9
8
+
.3V_RUN
3
1 2
P
C
P
CH_DDPC_CTRLCLK <16>
P
H_DDPC_CTRLDATA <16>
C
C
C
3
3
66
66
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
H_DDPD_CTRLCLK <16>
P
C
H_DDPD_CTRLDATA <16>
3
2
1
+
5
V_RUN
12
C
C
69
3
3
69
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
D
P
D
P
D_CA_DET<38>
+
.3V_RUN
3
R
R
487 2.2K_0402_5%~D
487 2.2K_0402_5%~D
R
R
4
A A
4
R
R
4
4
R
R
4
4
D_CA_DET
1 2
2
1
88 2 .2K_0402_5%~D
88 2 .2K_0402_5%~D
1 2
89 2 .2K_0402_5%~D
89 2 .2K_0402_5%~D
1 2
90 2 .2K_0402_5%~D
90 2 .2K_0402_5%~D
1 2
R
R
4
4
91 1M_0 402_5%~D
91 1M_0 402_5%~D
1 2
R
R
4
4
92 1M_0 402_5%~D
92 1M_0 402_5%~D
5
P
H_DDPC_CTRLCLK
C
P
CH_DDPC_CTRLDATA
P
H_DDPD_CTRLCLK
C
P
C
H_DDPD_CTRLDATA
D
PD_CA_DET
D
P
C_CA_DET
1
U
U
2
2
4
4
P
C
D
P
D_CA_DET#
N
4
A2Y
G
TC7SET04FU_SC70-5~D
TC7SET04FU_SC70-5~D
3
I
ntel WW18 Strapping option
Intel WW18 Strapping option
4
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
ompal Electronics, Inc.
o
mpal Electronics, Inc.
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
D
D
D
AUX SW
AUX SW
P
P
P
AUX SW
L
L
L
-7781
A-7781
A
A
-7781
2
2
2
6 6
6 6
1
6 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
5
D D
+
3
.3V_RUN
12
53
53
JP
JP
P
P
PAD-OPEN1x1m
PAD-OPEN1x1m
4
3
2
1
Free Fall Sensor
+
3.3V_RUN_FFS
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
1
1
C C
+
3
.3V_RUN
1 2
01 1 0K_0402_5%~D
5
5
01 1 0K_0402_5%~D
R
R
1 2
R
R
02 1 0K_0402_5%~D
02 1 0K_0402_5%~D
5
5
1 2
R
R
5
5
03 1 00K_0402_5%~D
03 1 00K_0402_5%~D
B B
F
F
S_INT2<18>
D
DR_XDP_WAN_SM BDAT
D
D
R_XDP_WAN_SM BCLK
H
D_FALL_INT
D
F
F
S_INT2
2
2
+
3
C
C
3
3
87
87
D
D
D
D
.3V_RUN
12
61
C
C
3
3
88
88
2
H
D
D_FALL_INT<17>
R_XDP_WAN_SM BDAT<7,12,13,14,15,34>
R_XDP_WAN_SM BCLK<7,12,13,14,15,34>
5
5
08
08
R
R
100K_0402_5%~D
100K_0402_5%~D
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
2
2
9A
9A
+
5
V_HDD
12
5
5
06
@
06
@
R
R
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
2
29B
9B
4
H
D
D_FALL_INT
F
FS_INT2
F
S_INT2_Q
F
P
S
ATA_PTX_DRX_P0_C<14>
P
ATA_PTX_DRX_N0_C<14>
S
P
S
ATA_PRX_DTX_N0_C<14>
P
S
ATA_PRX_DTX_P0_C<14>
8
8
8
8
U
U
NG3DM
NG3DM
L
L
E
1
14
11
9
7
6
4
8
LNG3DMTR_LGA16_3X3~D
LNG3DMTR_LGA16_3X3~D
+
.3V_RUN
3
R
E
D
D_IO
R
V
D
D
E
R
V
I
I
S
S
S
C
+
E
R
T 1
N
N
N
T 2
G
N
G
D
O/SA0
D
A / SDI / SDO
C
L/SPC
N
S
N
V_HDD
5
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
1
C
C
3
3
95
95
2
2
P
eace near HDD CONN
l
10
S
13
S
15
S
16
S
5
D
12
D
2
C
3
C
12
3
3
83 0.01U_0402_16V7K~D
83 0.01U_0402_16V7K~D
C
C
12
C
C
3
3
84 0.01U_0402_16V7K~D
84 0.01U_0402_16V7K~D
12
3
3
85 0.01U_0402_16V7K~D
85 0.01U_0402_16V7K~D
C
C
12
86 0.01U_0402_16V7K~D
86 0.01U_0402_16V7K~D
3
3
C
C
P
P
64
JP
JP
64
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
H
D
D_DET#<14>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
3
3
96
96
+
3
.3V_RUN_HDD
S
A
TA_PTX_DRX_P0
S
A
TA_PTX_DRX_N0
S
A
TA_PRX_DTX_N0
S
TA_PRX_DTX_P0
A
H
D
D_DET#
+
V_HDD
5
F
F
S_INT2_Q
For HDD Temp.
S
S
ATA1
ATA1
J
J
1
D
N
G
2
+
X
R
3
X-
R
4
D
N
G
5
-
X
T
6
+
X
T
7
D
N
G
8
.
3V
3
9
.
3V
3
10
.
3V
3
11
N
D
G
12
N
D
G
13
N
D
G
4
1
V
5
1
5
V
5
1
6
V
5
17
D
N
G
18
19
20
21
22
JAE_SP100421-HDD
JAE_SP100421-HDD
CONN@
CONN@
M
ain SATA +5V Default
R
G
2
1
2
1
2
1
eserved
D
N
V
V
V
N
G
N
G
H
DD PWR
+
V_ALW
+
P
WR_SRC_S
+
3
.3V_ALW2
12
R
R
5
5
00
@
00
@
100K_0402_5%~D
100K_0402_5%~D
6
R
U
N_ON<35,39,42,47>
S
I
O_SLP_S3#<11,16,35,39,42,47>
23
D1
24
D2
1 2
R
R
1
1
621 0_0402_5%~D@
621 0_0402_5%~D@
1 2
1
1
624 0_0402_5%~D@
624 0_0402_5%~D@
R
R
100K_0402_5%~D
100K_0402_5%~D
2
1
12
R
R
05
@
05
@
5
5
12
@R4
@
100K_0402_5%~D
100K_0402_5%~D
H
DD_EN_5V
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
@
@
Q
Q
2
2
8A
8A
5
499
99
R
@
@
Q
Q
1M_0402_5%~D
1M_0402_5%~D
2
2
8B
8B
12
@
@
R
R
5
5
16
16
245
1
G
G
3
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
@
@
C
C
1
3
3
93
93
2
+
6
D
D
7
@
2
2
7
@
Q
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
S
S
+
5
V_HDD
@
C394
C394
@
12
SHORT DEFAULT
R
R
04
04
5
5
100K_0402_5%~D
100K_0402_5%~D
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
1
2
V_HDD Source
5
3
JP
JP
3
P
P
112
JUMP_43X79
JUMP_43X79
+
5
V_RUN
2
+
3
.3V_RUN_HDD
A A
5
4
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
2
C
C
C
C
3
3
4
4
99
99
02
02
2
P
leace near HDD CONN
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
ompal Electronics, Inc.
o
o
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
H
H
H
D CONNECTOR
D
D
D
D CONNECTOR
D CONNECTOR
L
L
L
-7781
-7781
A
A
A
-7781
1
2
2
2
7 6
7 6
7 6
o
o
o
f
f
f
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
1
1
1
0
.
.
.
0
0
5
.3V_ALW
+3
Z
DD_WAKE#
1 2
5
5
R
R
1 2
5
5
R
.3V_ALW_PCH
+
V_MOD
5
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
2
C
C
3
3
97
97
R
1 2
R
R
5
5
1
2
+
3
D D
C C
P
l
eace near ODD CONN
O
10 10K_0402_5%~D
10 10K_0402_5%~D
M
O
13 10K_0402_5%~D
13 10K_0402_5%~D
14 100K_0402_5%~D
14 100K_0402_5%~D
D_MD
U
B30_SMI#
S
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
3
3
98
98
S
TA_ODD_PTX_DRX_P1_C<14>
A
S
TA_ODD_PTX_DRX_N1_C<14>
A
S
TA_ODD_PRX_DTX_N1_C<14>
A
S
A
TA_ODD_PRX_DTX_P1_C<14>
D
E
VICE_DET#<40>
C
K_PCIE_EMB<15>
L
C
K_PCIE_EMB#<15>
L
P
C
IE_PRX_EMBTX_P4<15>
P
C
IE_PRX_EMBTX_N4<15>
P
IE_PTX_EMBRX_P4<15>
C
P
C
IE_PTX_EMBRX_N4<15>
E
BCLK_REQ#<15>
M
P
IE_WAKE#<34,35,40>
C
P
L
TRST_EMB#<17>
B
AY_SMBDAT<40,44>
B
A
Y_SMBCLK<40,44>
M
D_SATA_PCIE#_DET<39>
O
4
12
C
C
4
4
07 0.01U_0402_16V7K~D
07 0.01U_0402_16V7K~D
12
06 0.01U_0402_16V7K~D
4
4
06 0.01U_0402_16V7K~D
C
C
12
C
C
4
4
05 0.01U_0402_16V7K~D
05 0.01U_0402_16V7K~D
12
C
C
04 0.01U_0402_16V7K~D
04 0.01U_0402_16V7K~D
4
4
E
M
BCLK_REQ#
P
C
IE_WAKE#
P
TRST_EMB#
L
B
A
Y_SMBDAT
B
Y_SMBCLK
A
+
.3V_ALW
3
1 2
183 10K_0402 _5%~D
183 10K_0402 _5%~D
1
1
R
R
+
V_MOD
5
12
12
S
TA_ODD_PTX_DRX_P1
A
S
TA_ODD_PTX_DRX_N1
A
S
ATA_ODD_PRX_DTX_N1
S
A
TA_ODD_PRX_DTX_P1
P
C
IE_PTX_EMBRX_P4_C
090.1U_0402_10V7K ~D
4
4
090.1U_0402_10V7K ~D
C
C
P
C
IE_PTX_EMBRX_N4_C
C
C
080.1U_0402_10V7K ~D
4
4
080.1U_0402_10V7K ~D
+
5
V_MOD
3
2
1
For ODD
+
5
M
O
DC_EN<39>
100K_0402_5%~D
100K_0402_5%~D
VMOD Source
2
12
R
R
12
12
5
5
+
3
.3V_ALW2
1
2
6
1
09
09
5
5
R
R
100K_0402_5%~D
100K_0402_5%~D
M
O
DC_EN#
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
3
3
1A
1A
+
P
WR_SRC_S
5
12
R
R
5
5
07
07
470K_0402_5%~D
470K_0402_5%~D
2
M
O
D_EN
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
3
3
1B
1B
4
+
V_ALW
5
6
2
1
D
D
G
G
Q
Q
0
3
3
0
SI3456DDV-T1-GE3_TSOP6~D
0.022U_0402_25V7K~D
0.022U_0402_25V7K~D
4 5
C
C
1
4
4
00
00
2
SI3456DDV-T1-GE3_TSOP6~D
S
S
+
V_MOD
5
P
JP4
@PJP4
C401
C401
@
12
R
R
11
11
5
5
100K_0402_5%~D
100K_0402_5%~D
112
JUMP_43X79
JUMP_43X79
1
1
0U_0805_10V6K~D
0U_0805_10V6K~D
2
+
V_RUN
5
3
4.7M_0402_5%~D
4.7M_0402_5%~D
12
R
R
1
5
5
17
17
2
S
S
ATA2
ATA2
J
J
1
D
N
G
2
+
A
3
-
A
4
D
N
G
5
-
B
6
+
B
7
N
D
G
8
P
D
9
V
5
+
10
V
5
M
D_MD
O
+
1
1
M
12
G
13
G
14
G
15
R
16
R
17
G
18
P
19
P
20
G
21
G
22
P
23
P
24
G
25
+
26
C
27
W
28
P
29
S
30
S
31
H
D
N
D
N
D
N
D
FCLK+
E
E
FCLKD
N
E
TX+
E
TX-
N
D
N
D
RX+
E
RX-
E
D
N
5
V
KREQ#
L
A
KE#
E
RST#
M
B_DATA
B_CLK
M
P
D
TYCO_2-2129116-3
TYCO_2-2129116-3
CONN@
CONN@
32
N
D1
G
33
N
D2
G
+
.3V_ALW
Q
Q
6
7
7
B B
M
D_MD
O
A A
5
6
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
S
D
S
13
G
G
2
M
O
DC_EN#
23B
23B
1
1
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
5
U
S
B30_EN
Z
O
DD_WAKE#
U
S
B30_SMI#
4
Z
O
DD_WAKE# <39>
U
S
B30_SMI# <14>
M
D_SATA_PCIE#_DET
O
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3
12
R
R
5
5
100K_0402_5%~D
100K_0402_5%~D
U
61
1
1
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
2
15
15
S
B30_EN
23A
23A
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
Title
tle
tle
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
mpal Electronics, Inc.
O
O
O
D CONNECTOR
D CONNECTOR
D
D
D
D CONNECTOR
L
L
L
-7781
A
A-7781
A-7781
1
2
2
2
8 6
8 6
8 6
o
o
o
f
f
f
1
1
1
0
0
.
.
0
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
2
Internal Speakers Header
15 mils trace
I
N
T_SPK_L+
I
N
T_SPK_L-
I
T_SPK_R+
N
I
T_SPK_R-
N
C
C
C
C
C
C
9
9
9
9
9
9
75 2200 P_0402_50V7K~D
75 2200 P_0402_50V7K~D
73 2200 P_0402_50V7K~D
73 2200 P_0402_50V7K~D
74 2200 P_0402_50V7K~D
74 2200 P_0402_50V7K~D
1
1
1
1
2
2
2
2
R
R
R1
R1
R
R
1
1
1
1
658 3.3_0402_5%~D
658 3.3_0402_5%~D
659 3.3_0402_5%~D
659 3.3_0402_5%~D
660 3.3_0402_5%~D
B B
A A
12
C
lose to U72 pin5
P
C
12
@
@
1
@
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
P
ace closely to Pin 13.
l
P
l
ace closely to Pin 14
D
CK_HP_DET<39>
O
660 3.3_0402_5%~D
12
1
2
C
l
ose to U72
H_AZ_CODEC_SDOUT
R
R
077
1
1
077
47_0402_5%~D
47_0402_5%~D
C
C
9
9
78
78
DMN66D0LDW-7_ SOT363-6~D
DMN66D0LDW-7_ SOT363-6~D
A
+
3
.3V_RUN
12
DMN66D0LDW-7_ SOT363-6~D
DMN66D0LDW-7_ SOT363-6~D
12
dd for solve pop noise and detect issue
39.2K_0402_1%~D
39.2K_0402_1%~D
R
R
100K_0402_5%~D
100K_0402_5%~D
DVDD_IO should match
with HDA Bus level
9
9
1 BLM18PG121SN1D_0603
1 BLM18PG121SN1D_0603
L
L
1 2
L
L
9
9
2 BLM18PG121SN1D_0603
2 BLM18PG121SN1D_0603
1 2
3 BLM18PG121SN1D_0603
3 BLM18PG121SN1D_0603
9
9
L
L
9
9
L
L
C9
76 2200 P_0402_50V7K~DC976 2200 P_0402_50V7K~D
R
R
1
1
661 3.3_0402_5%~D
661 3.3_0402_5%~D
081
081
1
1
2
1
4 BLM18PG121SN1D_0603
4 BLM18PG121SN1D_0603
1 2
C
ose to U72 pin6
l
P
H_AZ_CODEC_BITCLK
C
12
R1076
R1076
3
3
_0402_5%~D
_0402_5%~D
3
3
1
9
9
77
77
C
C
10P_0402_50V8J~D
10P_0402_50V8J~D
2
A
D_SENSE_A
U
2
07A
07A
1
1
Q
Q
A
U
D_SENSE_B
1079
1
R
R
2
Q
Q
1
1
06A
06A
079
61
12
61
12
086
086
1
1
R
R
20K_0402_1%~D
20K_0402_1%~D
3
07B
1
1
07B
Q
Q
4
DMN66D0LDW-7_ SOT363-6~D
DMN66D0LDW-7_ SOT363-6~D
12
080
080
1
1
R
R
20K_0402_1%~D
20K_0402_1%~D
3
Q
Q
4
DMN66D0LDW-7_ SOT363-6~D
DMN66D0LDW-7_ SOT363-6~D
I
N
T_SPKL_L+
I
T_SPKR_L-
N
I
T_SPKR_R+
N
I
T_SPKR_R-
N
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
3
2
3
@
@
D
D
E
E
2
2
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
5
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
2
5
1
1
06B
06B
1
2
3
4
MOLEX_53398-0471~ D
MOLEX_53398-0471~ D
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
2
@
@
D
D
E
E
1
1
1
B
C
LK: Audio serial data bus bit clock input/output
L
RCK: Audio serial data bus word clock input/output
A
D_NB_MUTE#<39>
U
+
.3V_RUN
3
+
083
083
1
1
R
R
2.49K_0402_1%~D
2.49K_0402_1%~D
12
+
3
.3V_RUN
C
C
9
9
80
80
12
R
R
100K_0402_5%~D
100K_0402_5%~D
1
@
@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
+
078
078
1
1
R
R
2.49K_0402_1%~D
2.49K_0402_1%~D
2
1
C
C
9
9
79
79
+
3.3V_RUN
12
R
R
100K_0402_5%~D
100K_0402_5%~D
2
+3
.3V_RUN
J
J
PK1
CONN@
PK1
CONN@
S
S
1
2
5
G1
3
6
G
4
2
P
C
H_AZ_CODEC_BITCLK<14>
P
H_AZ_CODEC_SDOUT<14>
C
P
CH_AZ_CODEC_SYNC<14>
P
CH_AZ_CODEC_SDIN0<14>
P
C
H_AZ_CODEC_RST#<14>
1 2
0
0
K_0402_5%~DR1099
K_0402_5%~DR1099
1
1
V
DDA_AVDD
087
1
1
087
A
D_HP_NB_SENSE <30,39>
U
67
9
9
67
C
C
DDA_AVDD
V
1
1
082
082
D
O
CK_MIC_DET <39>
+3
.3V_RUN_DVDD+3.3V_RUN_DVDD
PJ
P60
@PJP60
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
1U_0603_10V7K~D
1U_0603_10V7K~D
1
2
Place R1096 close to codec
1
R1096
R1096
I
2
S_MCLK
I
2
S_BCLK
I2S_DO
I2S_LRCLK
I2S_DI#
p
lace at AGND and DGND plane
Resistor
39.2K
20K
10K
5.11K
2.49K
PORT B
PORT C
PORT D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
9
994
9
9
52
52
94
2
2
P
C
P
C
P
_0402_5%~D
_0402_5%~D
3
3
3
3
C
P
C
_0402_5%~DR1097
_0402_5%~DR1097
2
3
3
3
3
1 2
Place R1097 close to codec
1 2
C
C
81
81
9
9
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
1
C
C
9
9
82
82
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
C
C
83
83
9
9
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
SENSE_A SENSE_B
PORT A
PORT B
NA
SPDIFOUT0
External MICPORT A
HeadPhone Out
Dock Audio
Internal SPK
+
VDD_CORE
D
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
1
C9
C
C954
C954
9
53
53
2
H_AZ_CODEC_BITCLK
H_AZ_CODEC_SDOUT
H_AZ_SDIN0_R
H_AZ_CODEC_RST#
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
Place C994, C952~C957 close to Codec
U
U
2
2
7
7
1
D
DD_CORE
V
3
D
V
DD_IO
9
D
V
DD
6
B
I
TCLK
5
S
ATA_OUT
D
10
S
Y
NC
8
S
D
ATA_IN
11
R
E
SET#
15
I
S_MCLK
2
16
I
2
S_SCLK
17
I
S_DOUT
2
18
I
S_LRCLK
2
24
I
2
S_DIN
19
N
Connect
o
20
N
Connect
o
47
E
A
PD
7
D
V
SS
42
P
SS
V
49
G
D
N
92HD93B2X5NLGXWBX8_Q FN48_7X7~D
92HD93B2X5NLGXWBX8_Q FN48_7X7~D
p
lace at Codec bottom side
P62
@
P62
@
J
J
P
P
1
PAD-OPEN1x1m
PAD-OPEN1x1m
R
162, R163, R164, R165,R166 CO-lay with U73
2
D
IC1/GPIO0/SPDIFOUT1
M
S
P
DIFOUT0//GPIO3/Aux_Out
D
I_BCLK#
A
D
I_LRCK#
A
D
I_DO#
A
D
A
I_12MHZ#
D
PORT E
PORT F
E
N
_I2S_NB_CODEC#<39>
DMIC0
SPDIFOUT1 (DMIC1)
Pull-up to AVDD
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
ARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
DD1
V
A
VDD2
P
V
DD
P
V
DD
S
E
NSE_A
S
E
NSE_B
P
O
RTA_L
P
O
RTA_R
V
r
efOut_A
P
RTB_L
O
P
RTB_R
O
P
RTD_+L
O
P
RTD_-L
O
P
O
RTD_+R
P
O
RTD_-R
M
NO_OUT
O
P
_BEEP
C
IC_CLK/GPIO 1
M
D
IC_0/GPIO 2
M
C
A
P+
C
A
P-
V
R
EFFILT
C
P2
A
V
-
V
r
eg
A
V
SS1
A
SS
V
A
V
SS
1 2
R162 22_ 0402_5%~DR162 2 2_0402_5%~D
1 2
63 0_040 2_5%~D@
1
163 0_04 02_5%~D@
R
R
1 2
64 0_040 2_5%~D@
1
1
64 0_040 2_5%~D@
R
R
1 2
65 22_04 02_5%~D
1
1
65 22_04 02_5%~D
R
R
E
27
38
45
39
13
14
28
29
23
31
32
40
41
44
43
25
12
2
4
46
48
36
35
21
22
4
3
37
26
30
33
_I2S_NB_CODEC#
N
place close to pin27
DDA_AVDD
+V
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
957
957
2
+
DDA_PVDD
V
AUD_SENSE_A
AUD_SENSE_B
M
I
C_IN_L
M
C_IN_R
I
+
V
REFOUT
A
D_HP_OUT_L
U
A
D_HP_OUT_R
U
I
N
T_SPK_L+
I
N
T_SPK_L-
I
N
T_SPK_R+
I
N
T_SPK_R-
A
U
D_PC_BEEP
D
IC_CLK_L
M
1 2
3 BLM18BB22 1SN1D_2P~D
3 BLM18BB22 1SN1D_2P~D
E
E
L
L
1
1
1
69 0 _0402_5%~D@
69 0 _0402_5%~D@
R
R
1 2
R
R
641 0_040 2_5%~D@
641 0_040 2_5%~D@
1
1
1
62
62
9
9
C
C
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
Place C962 close to Codec
2
+
3
.3V_RUN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
2
1
1
103
103
1
S_BCLK
S_LRCLK
S_DO
S_MCLK
540
1
1
540
16
2
4
6
1
0
2
1
1
4
1
12
15
I
2
I
2
I
2
I
2
R
R
@
@
1K_0402_5%~D
1K_0402_5%~D
1U_0603_10V7K~D
1U_0603_10V7K~D
1
2
C
C
163 2.2U_0402_6.3V6M
163 2.2U_0402_6.3V6M
1
1
1
1
105 0.1 U_0402_25V6K~D
105 0.1 U_0402_25V6K~D
C
C
1
1
106 0.1 U_0402_25V6K~D
106 0.1 U_0402_25V6K~D
C
C
Place LE3 close to codec
2
Place C963~C966 close to Codec
7
7
3
@
3
@
U
U
C
C
V
A
1
A
2
A
3
A
4
A
5
A
6
1#
E
O
E
2#
O
CD74HC366M96_SO16~D
CD74HC366M96_SO16~D
1
C
C
9
9
56
56
2
1 2
+
V
REFOUT
12
12
E
N
_I2S_NB_CODEC#
Y
#
1
#
Y
2
#
Y
3
Y
#
4
Y
#
5
Y
#
6
N
D
G
1
1
0U_0805_10V6K~D
0
U_0805_10V6K~D
R
R
+
1
place close to pin38
C955
C955
1 2
143 2.2K_0402_5%~D
143 2.2K_0402_5%~D
1
1
D
M
IC_CLK <24>
D
IC0 <24>
M
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C
C
9
9
63
63
2
2
3
.3V_RUN
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
3
3
@
@
D
D
5
5
4
4
1
3
5
7
9
11
I
2S_DI#
13
8
1 2
66 0_040 2_5%~D@
66 0_040 2_5%~D@
1
1
R
R
1
V_RUN
L7
L7
7
7
BLM21PG600SN1D_0805~ D
BLM21PG600SN1D_0805~ D
1 2
1
C
C
9
9
64
64
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
1
D
T
T
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+5
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
1
C958
C958
2
M
C_IN_R <30>
I
A
UD_HP_OUT_L <30>
A
U
D_HP_OUT_R <30>
1 2
R
R
119 100K_0402_5%~D
119 100K_0402_5%~D
1
1
1 2
R
R
1
1
120 100K_0402_5%~D
120 100K_0402_5%~D
1 2
R
R
141 10K_04 02_5%~D@
141 10K_04 02_5%~D@
1
1
1 2
R
1142 10K_0 402_5%~D@R1142 10K_0 402_5%~D@
1U_0603_10V7K~D
1U_0603_10V7K~D
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
1
C966
C966
C
C
9
9
65
65
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
3
@
@
@
@
D
D
D
D
5
5
5
5
6
6
5
5
1
D
I_DI
A
LL CONFIDENTIAL/PROPRIETARY
E
tle
tle
i
i
+5
V_RUN
1
2
3
C
C
C
A
A
A
1
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
1
1
C960
C960
C
C
9
9
59
59
2
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
@
@
D
D
5
5
7
7
1
D
A
I_BCLK#
D
A
I_LRCK#
D
I_DO#
A
D
A
I_12MHZ#
+
.3V_RUN
3
2
3
@
@
D
D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
1
pal Electronics, Inc.
pal Electronics, Inc.
om
om
om
pal Electronics, Inc.
alia (HD) Codec
z
z
z
alia (HD) Codec
alia (HD) Codec
L
L
L
-7781
-7781
A
A
A
-7781
0_0805_5%~D
0_0805_5%~D
@
@
R
R
1
1
095
095
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
9
9
61
61
S
PKR <14>
B
E
EP <40>
8
5
5
8
D
AI_DI
+
REFOUT
V
D
I_BCLK# <38>
A
D
A
I_LRCK# <3 8>
D
AI_12MHZ# < 38>
D
2
2
2
9 6
9 6
9 6
1
2
D
A
I_DO# <3 8>
A
I_DI <38>
o
o
o
f
f
f
1U_0603_10V7K~D
1U_0603_10V7K~D
C
C
1
1
180
180
1
1
1
.0
0
0
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
4
3
I
/O board CONN.
2
1
Change to TYCO_2041300-2_60P-T and Horizonal reverse to SSI
O1
O1
I
I
J
J
2
2
S
W
_LAN_TX0+<31>
S
W
D D
S
S
1
W
W
1
NTC033-XJ1J-X260CM_4P
V
L_MUTE<40>
O
OL_DOWN<40>
V
L_UP<40>
O
L
I
D_CL#<39,43>
NTC033-XJ1J-X260CM_4P
3
4
J
J
L
L
ED1
ED1
1
1
2
2
3
3
4
4
5
7
5
G
1
6
8
6
G
2
TYCO_2041084-6~D
TYCO_2041084-6~D
CONN@
CONN@
1
2
M
dia Board
e
J
J
M
M
DIA1
DIA1
1
1
2
2
3
3
4
4
5
5
6
1
6
G
7
2
G
7
8
8
TYCO_2041070-8~D
TYCO_2041070-8~D
CONN@
CONN@
ED Board
L
+
5
V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
5
5
0
0
2
9
0
1
P
WER_SW#_M B
P
O
WER_SW#_M B<40,41>
P
WER & INSTANT ON SWITCH
O
D
efult on,
WIRELESS_ON/OFF#:
LOW: ON
HIGH: OFF
C C
+
V_ALW
5
B B
1
C
C
002
002
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
+
3
.3V_ALW
S
A
B
A
B
A
W
L
TA_LED<43>
TT_WHITE<43>
TT_YELLOW<43>
AN_LED< 43>
O
D
D
2
2
3
@
3
@
1
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
1
C
C
001
001
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
3
2
V
W
I
RELESS_ON#/OFF<39>
S
W
S
W
S
W_LAN_TX2+<31>
S
W
S
W
S
W
+
3
L
E
D_100_ORG#<31>
L
E
D_10_GRN#<31>
L
A
N_ACTLED_YEL#<31>
U
U
SBP9+<17>
U
S
U
S
B_SIDE_EN#<36,39>
A
D_HP_NB_SENSE<29,39>
U
+
3
.3V_LAN
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
9
9
97
97
2
P
l
ace close
to JIO1.13
_LAN_TX0-<31>
_LAN_TX1-<31>
_LAN_TX1+<31>
_LAN_TX2-<31>
_LAN_TX3-<31>
_LAN_TX3+<31>
+
5
.3V_LAN
S
B_OC4#<17>
BP9-<17>
V_RUN
DETECT_GND
4
4
6
6
8
8
0
1
0
1
2
1
2
1
1
4
4
1
6
1
6
1
8
1
8
1
0
2
0
2
2
2
2
2
2
4
4
2
2
6
6
2
2
8
8
2
3
0
0
3
3
2
2
3
3
4
4
3
6
3
6
3
8
3
8
3
0
4
0
4
2
4
2
4
4
4
4
4
6
4
6
4
8
4
8
4
0
5
0
5
5
2
2
5
5
4
4
5
6
5
6
5
8
5
8
5
0
6
0
6
62
D
N
G
64
D
N
G
66
D
N
G
TYCO_2041300-2
TYCO_2041300-2
CONN@
CONN@
1
1
3
3
5
5
7
7
9
9
1
1
1
1
1
3
3
1
5
1
5
1
7
1
7
1
9
1
9
1
2
1
1
2
2
3
3
2
2
5
5
2
2
7
7
2
2
9
9
2
3
1
1
3
3
3
3
3
5
3
5
3
7
3
7
3
9
3
9
3
1
4
1
4
3
4
3
4
5
4
5
4
7
4
7
4
9
4
9
4
1
5
1
5
3
5
3
5
5
5
5
5
5
7
7
5
5
9
9
5
61
D
N
G
63
D
N
G
65
D
N
G
M
P
C
H_AZ_MDC_RST1#
A
I
nalog_GND
C_IN_R
I
_LOOP# <18>
O
V
YNC_BUF <23>
S
H
YNC_BUF <23>
S
R
ED_CRT <23>
G
R
EEN_CRT <2 3>
B
L
UE_CRT <23>
D
T_DDC2_CRT <23>
A
C
L
K_DDC2_CRT <23>
A
U
D_HP_OUT_R <29>
M
I
C_IN_R <29>
A
D_HP_OUT_L <29>
U
+
3
.3V_ALW_PCH
P
C
H_AZ_MDC_SDIN1 <14>
P
C
H_AZ_MDC_SYNC <14>
P
C
H_AZ_MDC_SDOUT <14>
P
H_AZ_MDC_BITCLK <14>
C
+
3
.3V_ALW_PCH
1
C
C
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
P
lace close
to JIO1.35
+
5
V_ALW
1
C
C
003
003
1
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
000
000
Q
Q
4
4
4
4
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
P
S
S
CH_AZ_MDC_RST1#
12
R
R
51
51
7
7
100K_0402_5%~D
100K_0402_5%~D
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
Title
itle
tle
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
R SW/Sub-board Connector
W
W
W
R SW/Sub-board Connector
R SW/Sub-board Connector
L
L
L
-7781
-7781
A
A
A-7781
1
3
3
3
0 6
0 6
0 6
o
o
o
f
f
f
1
1
1
0
.
0
0
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
D
D
R
R
52
7
7
52
10K_0402_5%~D
10K_0402_5%~D
1 3
2
G
G
P
CH_AZ_MDC_RST#<14>
+
5
A A
M
C_RST_DIS#<39>
D
V_ALW
12
5
5
+3
.3V_LAN
T
P
1 2
R
R
45 10K_0402 _5%~D@
45 10K_0402 _5%~D@
5
5
1 2
R5
R5
46 10K_0402 _5%~D@
46 10K_0402 _5%~D@
D D
P
M
_LANPHY_ENABLE< 18>
C C
B B
D
O
CKED<39>
A A
yout Notice : Place bead as
a
L
close PI3L500 as possible
_LAN_JTAG_TMS
T
P
_LAN_JTAG_TCK
+
3.3V_LAN
12
49
5
5
49
R
R
10K_0402_5%~D
10K_0402_5%~D
1 2
55 0_0402_5%~D@
55 0_0402_5%~D@
5
5
R
R
12
57
@
57
@
5
5
R
R
10K_0402_5%~D
10K_0402_5%~D
3
3
Y
Y
2
2
5MHZ_18PF_X3G025000DI1H-H~D
5MHZ_18PF_X3G025000DI1H-H~D
1
33P_0402_50V8J~D
33P_0402_50V8J~D
2
2
C
C
4
4
70
70
1
ed to verify A3 silicon drive
e
N
power before removing C427
KDS crystal vender verify
driving level in A3
+
L
A
N_TX0+
1 2
0 12NH_0603CS-120EJTS_5 %~D
0 12NH_0603CS-120EJTS_5 %~D
3
3
L
L
L
N_TX0-
A
1 2
L
L
1 12NH_0603CS-120EJTS_5 %~D
3
3
1 12NH_0603CS-120EJTS_5 %~D
L
N_TX1+
A
1 2
3
3
3 12NH_0603CS-120EJTS_5 %~D
3 12NH_0603CS-120EJTS_5 %~D
L
L
L
A
N_TX1-
1 2
L
L
2 12NH_0603CS-120EJTS_5 %~D
2 12NH_0603CS-120EJTS_5 %~D
3
3
L
A
N_TX2+
1 2
L
L
4 12NH_0603CS-120EJTS_5 %~D
4 12NH_0603CS-120EJTS_5 %~D
3
3
L
N_TX2-
A
1 2
L
L
5 12NH_0603CS-120EJTS_5 %~D
5 12NH_0603CS-120EJTS_5 %~D
3
3
L
A
N_TX3+
1 2
L
L
6 12NH_0603CS-120EJTS_5 %~D
3
36 12NH_0603CS-120EJTS_ 5%~D
L
N_TX3-
A
1 2
7 12NH_0603CS-120EJTS_5 %~D
3
3
7 12NH_0603CS-120EJTS_5 %~D
L
L
D
O
CKED
OM NIC DOCKED
R
F
5
N
I
N
D
G
3.3V_LAN
U
O
N
G
3
T
4
D
L
L
L
1
0: TO RJ45
O
O
O
:
L
A
P
L
C
LK_PCIE_LAN<15>
C
L
K_PCIE_LAN#<15>
P
C
IE_PRX_GLANTX_P7<15>
P
C
IE_PRX_GLANTX_N7<15>
C
IE_PTX_GLANRX_P7<15>
P
P
C
IE_PTX_GLANRX_N7<15>
L
N_SMBCLK<15>
A
L
A
N_SMBDATA<15>
1 2
1
1
144 0_0402_5%~D@
144 0_0402_5%~D@
R
R
33P_0402_50V8J~D
33P_0402_50V8J~D
2
C4
C4
71
71
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
4
4
4
4
72
72
73
73
2
2
M_ACTLED_YEL#
M_SPD100LED_ORG#
M_SPD10LED_GRN#
TO DOCK
NCLK_REQ#<15>
TRST_LAN#<17>
1
2
L
A
N_TX0+R
L
N_TX0-R
A
L
A
N_TX1+R
L
A
N_TX1-R
L
N_TX2+R
A
L
A
N_TX2-R
L
A
N_TX3+R
L
A
N_TX3-R
1 2
187 0_0402_5%~D@
187 0_0402_5%~D@
1
1
R
R
2
1
C
C
4
4
58 0.1U_0402_10V7K~D
58 0.1U_0402_10V7K~D
12
C
C
59 0.1U_0402_10V7K~D
59 0.1U_0402_10V7K~D
4
4
1 2
60 0.1U_0402_10V7K~D
60 0.1U_0402_10V7K~D
4
4
C
C
1 2
61 0.1U_0402_10V7K~D
61 0.1U_0402_10V7K~D
4
4
C
C
1 2
R
R
51 0_0402_5%~D@
51 0_0402_5%~D@
5
5
1 2
R
R
52 0_0402_5%~D@
52 0_0402_5%~D@
5
5
MBus Device Address 0xC8
S
A
N_DISABLE#_R<39>
L
42 PAD~D
42 PAD~D
1
1
T
T
T
T
43 PAD~D
1
1
43 PAD~D
1K_0402_5%~D
1K_0402_5%~D
12
R
R
5
5
61
61
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
4
4
74
74
U
U
3
3
2
2
2
A
0
+
3
A
-
0
6
A
+
1
7
A
-
1
9
A
2
+
10
A
-
2
11
A
3
+
12
A
3
-
13
S
E
L
15
L
DA0
E
16
L
E
DA1
42
L
DA2
E
5
P
D
43
P
AD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
PI3L720ZHEX_TQFN42_9X3P5~D
+3
.3V_RUN
12
L
C
L
K_PCIE_LAN
C
K_PCIE_LAN#
L
P
IE_PRX_GLANTX_P7_C
C
P
C
IE_PRX_GLANTX_N7_C
P
IE_PTX_GLANRX_P7_C
C
P
IE_PTX_GLANRX_N7_C
C
L
A
N_SMBCLK_R
L
A
N_SMBDATA_R
L
A
N_DISABLE#_R
L
O
M_ACTLED_YEL#
L
M_SPD100LED_ORG#
O
L
M_SPD10LED_GRN#
O
T
P
_LAN_JTAG_TDI
T
P
_LAN_JTAG_TDO
T
_LAN_JTAG_TMS
P
T
_LAN_JTAG_TCK
P
X
ALO
T
X
ALI
T
L
A
N_TEST_EN
R
S_BIAS
E
3.01K_0402_1%~D
3.01K_0402_1%~D
12
R
R
5
5
62
62
39
4
8
14
21
30
D
D
D
D
D
D
D
D
D
D
V
V
V
V
V
4
5
5
47
47
R
R
10K_0402_5%~D
10K_0402_5%~D
A
NCLK_REQ#_R
1
D
D
D
D
V
V
B
B
B
B
B
B
B
B
L
DB0
E
L
E
DB1
L
DB2
E
C
C
C
C
C
C
C
C
L
EDC0
L
E
DC1
L
DC2
E
4
U
U
48
36
44
45
38
39
41
42
28
31
3
26
27
25
32
34
33
35
9
10
30
12
AN ANALOG
L
SWITCH
38
0
+
37
0
-
34
+
1
33
1
-
29
+
2
28
-
2
25
+
3
24
-
3
17
18
41
36
0
+
35
0
-
32
1
+
31
-
1
27
2
+
26
-
2
23
3
+
22
-
3
19
20
40
3
1
1
3
K_REQ_N
L
C
E
_RST_N
P
E
_CLKP
P
E
_CLKN
P
E
Tp
P
Tn
E
P
Rp
E
P
Rn
E
P
B_CLK
M
S
M
B_DATA
S
L
N_DISABLE_N
A
D0
E
L
D1
E
L
E
L
T
J
T
J
T
J
T
J
T
X
T
X
E
T
R
D
D
E
E
D2
L
L
AG_TDI
AG_TDO
AG
AG
AG_TMS
T
T
AG_TCK
J
J
AL_OUT
AL_IN
ST_EN
B
IAS
S
W
_LAN_TX0+
S
W
_LAN_TX0-
S
_LAN_TX1+
W
S
_LAN_TX1-
W
S
W
_LAN_TX2+
S
W
_LAN_TX2-
S
_LAN_TX3+
W
S
W_LAN_TX3-
L
N_ACTLED_YEL#
A
L
E
D_100_ORG#
L
E
D_10_GRN#
D
O
CK_LOM_TRD0+
D
CK_LOM_TRD0-
O
D
CK_LOM_TRD1+
O
D
CK_LOM_TRD1-
O
D
O
CK_LOM_TRD2+
D
O
CK_LOM_TRD2-
D
O
CK_LOM_TRD3+
D
CK_LOM_TRD3-
O
D
CK_LOM_ACTLED_YEL#
O
D
CK_LOM_SPD100LED_ORG#
O
D
OCK_LOM_SPD10LED_GRN#
I_PLUS0
D
M
I_MINUS0
D
M
I_PLUS1
D
M
D
I_MINUS1
M
I
I
IE
IE
D
D
C
C
M
M
I_PLUS2
D
M
P
P
D
I_MINUS2
M
D
I_PLUS3
M
I_MINUS3
D
M
S
VD_NC
R
BUS
BUS
R
VD_VCC3P3_1
S
M
M
R
S
VD_VCC3P3_2
S
S
D3P3_IN
D
V
V
D
D3P3_OUT
D
D3P3_15
V
D
D3P3_19
V
D3P3_29
D
V
D
D1P0_47
V
D
D1P0_46
V
D
D1P0_37
V
D
D1P0_43
V
D1P0_11
D
V
D1P0_40
D
V
D1P0_22
D
V
D
D1P0_16
V
D
D1P0_8
V
T
RL_1P0
C
S_EPAD
S
V
82579_QFN48_6X6~D
82579_QFN48_6X6~D
3
L
A
N_TX0+
13
L
AN_TX0-
14
L
A
N_TX1+
17
L
AN_TX1-
18
LA
N_TX2+
20
L
AN_TX2-
21
L
A
N_TX3+
23
L
N_TX3-
A
24
6
+
R
SVD_VCC3P3_1
1
+
R
SVD_VCC3P3_2
2
5
4
15
19
29
47
46
37
43
11
40
22
16
8
7
49
S
W
S
W
S
W
S
W
S
W
S
W
S
W
S
W
L
A
L
E
L
E
D
O
D
O
D
O
D
O
D
O
D
OCK_LOM_TRD2- <38>
D
O
D
O
D
O
D
O
D
O
+
3
.3V_LAN_OUT
+
1
.0V_LAN
R
EGCTL_PNP10
_LAN_TX0+ <30>
_LAN_TX0- <30>
_LAN_TX1+ <30>
_LAN_TX1- <30>
_LAN_TX2+ <30>
_LAN_TX2- <30>
_LAN_TX3+ <30>
_LAN_TX3- <30>
N_ACTLED_YEL# <30>
D_100_ORG# <30>
D_10_GRN# < 30>
CK_LOM_TRD0+ <38>
CK_LOM_TRD0- <38>
CK_LOM_TRD1+ <38>
CK_LOM_TRD1- <38>
CK_LOM_TRD2+ <38>
CK_LOM_TRD3+ <38>
CK_LOM_TRD3- <38>
CK_LOM_ACTLED_YEL# <38>
CK_LOM_SPD100LED_ORG# <38>
CK_LOM_SPD10LED_GRN# <38>
3
R
R
R
12
5
5
54 4.7K_0402 _5%~D
54 4.7K_0402 _5%~D
1
64
64
4
4
C
C
1U_0603_10V7K~D
1U_0603_10V7K~D
2
S
1.05V SVR
S
NO STUFF: L29
O
T
DOCK
12
53 4.7K_0402 _5%~D
53 4.7K_0402 _5%~D
5
5
R
2
R
GCTL_PNP10
E
+
.3V_LAN
3
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
C
C
4
4
66
66
2
2
o
te:
N
+1.0V_LAN will work at 0.95V t o 1.15V
1
.0V_LAN POWER OPTIONS
+
h
ared with PCH
UFF: R548
T
ternal SRV
n
I
*
STUFF: L29
NO STUFF: R548
S
I
O_SLP_LAN#<16,39>
L
O
M_SPD100LED_ORG#
L
M_SPD10LED_GRN#
O
+
2
2
1 2
4.7UH_CBC2012T4R7M_20%~D
4.7UH_CBC2012T4R7M_20%~D
d
I
+
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C
C
C
C
4
4
468
468
67
67
2
3
.3V_ALW2
12
65
5
5
65
R
R
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q
Q
3
3
5A
5A
+
3.3V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
5
1
P
B
O
2
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
5
5
1
1
U
U
1
+
.0V_LAN
+
3
1
2
.3V_LAN
1
2
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C4
C4
1
62
62
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C
C
1
1
178
178
2
2
9
9
L
L
c max=330mA
l
ace R548, C462, C463 and L29 c lose to U31
P
.0V_LAN
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
C
1
1
1
1
C
C
177
177
469
469
2
2
C
C
4
4
63
63
48
@
48
@
5
5
R
R
0_0805_5%~D
0_0805_5%~D
1 2
Place C1178 clo se to pin5
4
4
3
3
Q
+
3
.3V_ALW
1
64
64
5
5
R
R
100K_0402_5%~D
100K_0402_5%~D
2
3
4
W
D
tle
i
i
Title
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
E
AB_3VLAN
N
1M_0402_5%~D
1M_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1
Q
Q
R
R
1
1
3
3
638
638
5B
5B
2
AN_LAN_DISB# <39>
L
LL CONFIDENTIAL/PROPRIETARY
E
o
o
o
C
C
C
tel 82579 (Hanksville) / LAN SW
n
n
n
tel 82579 (Hanksville) / LAN SW
tel 82579 (Hanksville) / LAN SW
I
I
I
78
4
4
78
C
C
1 2
4
+
WR_SRC_S
P
5
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
C
C
4
4
77
77
2
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
-7781
-7781
A
A
A
-7781
L
L
L
1
+
.05V_M
1
+
3
.3V_M
@
@
0_1206_5%~D
0_1206_5%~D
1 2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
1 6
1 6
1 6
3
3
3
f
f
f
o
o
o
+
C
C
4
4
75
75
R
63
R5
5
63
3
.3V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
C
C
4
4
76
76
2
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
D D
4
3
2
1
+
.3V_RUN
3
1 2
PAD-OPEN1x1m
_TPM_LPC_EN<39>
C
1
2
1
2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
PAD-OPEN1x1m
1 2
73 0_0402_5%~D@
73 0_0402_5%~D@
8
8
R
R
K_PCI_TPM_TCM
L
RE51@
RE51@
_0402_5%~D
_0402_5%~D
3
3
3
3
3
1@
3
1@
E
E
C
C
33P_0402_50V8J~D
33P_0402_50V8J~D
+
57
@
6
6
57
@
R
R
R
R
6
6
59
1@
59
1@
+
.3V_RUN_TPM
3
S
P
C C
B B
A A
61
61
JP
JP
P
P
+
.3V_RUN_TPM
3
C
K_PCI_TPM_TCM< 15>
L
L
P
P
C
H_PLTRST#_EC<17,34,35,39,40>
I
R
Q_SERIRQ<14,39,40>
3
.3V_RUN_TPM
12
1
2
+
3
+
3
1 2
663 10K_0402_5%~D@
1
1
663 10K_0402_5%~D@
R
R
1 2
1
1
662 0_0402_ 5%~D@
662 0_0402_ 5%~D@
R
R
D
D
8
8
7 R B751S40T1_SOD523-2~D@
7 R B751S40T1_SOD523-2~D@
L
C_LAD0<14,34,39,40>
P
L
P
C_LAD1<14,34,39,40>
L
P
C_LAD2<14,34,39,40>
L
C_LAD3<14,34,39,40>
P
C_LFRAME#<14,34,39,40>
C
KRUN#<16,39,40>
L
1
@
@
R
R
10K_0402_5%~D
10K_0402_5%~D
2
12
1@
1@
10K_0402_5%~D
10K_0402_5%~D
.3V_RUN_TPM
.3V_SB3V
21
58
58
6
6
R
R
60
6
6
60
+
3
.3V_SB3V
+
3
E
TWAY_CLK14M
C
_P
5
5
C
C
M_BA0
C
P
.3V_RUN_TPM
1 2
54 1U_0402_6.3V6K ~D@
54 1U_0402_6.3V6K ~D@
1 2
56 4 .7K_0402_5%~D@
56 4 .7K_0402_5%~D@
6
6
R
R
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
1
@
@
1
1
C
C
5
5
50
50
2
2
J
TWAY_CLK14M <15>
E
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
1
@
@
C
C
5
5
51
51
1
2
+
.3V_RUN_TPM
3
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
0.1U_0402_25V6K~D
1
1
@
@
1
1
C
C
4
4
4
4
2
2
S
_TPM_LPC_EN_R
P
L
P
C_LAD0
L
P
C_LAD1
L
P
C_LAD2
L
P
C_LAD3
C
L
K_PCI_TPM_TCM
L
C_LFRAME#
P
P
C
H_PLTRST#_EC
I
Q_SERIRQ
R
C
KRUN#
L
T
M_BA1
C
C
o-lay U37 and U38
L
PC layout: Place TCM first and then end LPC with TPM.
A
MEL TPM for E4
@
@
1
1
C
C
4
4
5
5
T
3
3
9
1@
9
1@
U
U
5
3V
B
S
28
P
CPD#
L
26
D0
A
L
23
D1
A
L
20
D2
A
L
17
A
D3
L
21
C
LK
L
22
F
RAME#
L
16
R
ESET#
L
27
RIRQ
E
S
15
L
KRUN#
C
1
EST_1
T
A
2
T
EST_2
A
3
T
EST_3
A
AT97SC3204-X2A18-AB_TSSOP28
AT97SC3204-X2A18-AB_TSSOP28
10
C_0
C
V
19
C
C_1
V
24
C
C_2
V
12
_
BAT
V
B
O_13
N
B
O_14
N
P
G
E
STBI
T
E
T
N
N
G
N
D_11
G
N
D_18
G
N
D_25
G
J
13
N
14
6
IO6
T
9
8
STI
P
7
C
_7
4
D_4
11
18
25
China TCM: NationZ & Jetway co-lay
+
.3V_RUN_TPM
N
D
D
D
D_11
D_18
D_25
N
N
C
C
N
N
N
N
C
3
10
D_0
19
D_1
24
D_2
11
18
25
4
D_4
5
C
_5
12
_12
J
E
TWAY_CLK14M
13
_13
1
C
_1
2
_2
C
6
_6
C
8
_8
C
N
C
_P
14
_P
L
OW:Power Down Mode
High:Working Mode
S
P
_TPM_LPC_EN_R
L
C_LAD0
P
L
C_LAD1
P
L
C_LAD2
P
L
P
C_LAD3
C
K_PCI_TPM_TCM
L
L
P
C_LFRAME#
P
H_PLTRST#_EC
T
M_BA0
C
T
M_BA1
C
C
I
R
Q_SERIRQ
C
KRUN#
L
P
P
T
M_BA1
C
T
M_BA0
C
U
U
7
@
7
@
3
3
28
P
CPD#
L
26
L
D0
A
23
L
D1
A
20
L
A
D2
17
L
D3
A
21
L
LK
C
22
L
RAME#
F
16
L
R
ESET#
27
S
RIRQ
E
15
C
LKRUN#
7
P
P
3
A
_1
B
9
B
_0
A
SSX44-B-D-T1_TSSOP28~D
SSX44-B-D-T1_TSSOP28~D
V
V
V
G
N
G
N
G
N
G
N
N
+
.3V_SUS
3
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
@
@
1
1
1
1
@
@
C
C
C
C
5
5
5
5
52
52
53
53
2
+
3
+
3
+
3
.3V_SB3V
J
TWAY_CLK14M
E
.3V_SUS
1
2
.3V_RUN
1
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
5
5
3
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
5
5
1
1
12
@
@
E
E
R
R
33_0402_5%~D
33_0402_5%~D
1
@
@
C
C
E
E
27P_0402_50V8J~D
27P_0402_50V8J~D
2
1 2
89 2 .2K_0402_5%~D
89 2 .2K_0402_5%~D
5
5
R
R
1
5
5
85 2 .2K_0402_5%~D
85 2 .2K_0402_5%~D
R
R
+
V_RUN
5
1
2
6
6
4
4
U
H_SMBCLK
S
U
H_SMBDAT
S
2
U
B
B
T
B
U
S
C
O
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
5
5
2
2
U
SH board conn
U
U
SH1
SH1
J
J
1
1
U
S
BP7-<17>
U
S
BP7+<17>
U
S
H_SMBCLK<40>
H_SMBDAT<40>
S
M5882_ALERT#<39>
C
_COEX_STATUS2<41>
_PRI_STATUS<41>
T
P
TRST_USH#<17>
L
H_PWR_STATE#<39>
NTACTLESS_DET#<18>
U
S
H_DET#<18>
1M_0402_5%~D
1M_0402_5%~D
12
R
R
1
1640
640
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1
0
0
1
1
1
1
1
1
2
2
1
1
3
3
1
4
1
4
1
5
1
5
1
6
1
6
1
7
1
7
1
1
8
8
1
9
1
9
1
2
0
0
2
21
N
D1
G
22
N
D2
G
TYCO_2-2041070-0
TYCO_2-2041070-0
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
T
T
tle
i
i
Title
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
T
T
T
M/TCM
P
P
M/TCM
M/TCM
P
L
L
L
-7781
A
A
-7781
-7781
A
1
3
3
3
2 6
2 6
2 6
o
o
o
f
f
f
1
1
1
0
.0
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
A
1 1
+
.3V_RUN
3
+
.5V_RUN
1
+
P
E_VDDH
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1
C5
C5
C
C
5
5
73
73
74
2
2 2
p
lace close to pin U38.32
74
2
7
7
4
4
L
L
1 2
BLM18BD601SN1D_0603~D
BLM18BD601SN1D_0603~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
1
C
C
C
C
5
5
5
5
62
62
61
61
2
2
C
K_PCIE_MMI<15>
L
C
K_PCIE_MMI#<15>
L
P
C
IE_PRX_MMITX_P6<15>
P
IE_PRX_MMITX_N6<15>
C
P
IE_PTX_MMIRX_P6<15>
C
P
IE_PTX_MMIRX_N6<15>
C
P
L
TRST_MMI#<17>
M
ICLK_REQ#<15>
M
B
4
4
5
5
L
L
BLM18PG471SN1D_2P~D
BLM18PG471SN1D_2P~D
1 2
5
5
69 0.1U_0402_10V7K~D
69 0.1U_0402_10V7K~D
C
C
1 2
71 0.1U_0402_10V7K~D
5
5
71 0.1U_0402_10V7K~D
C
C
1 2
5
5
67 0.1U_0402_10V7K~D
67 0.1U_0402_10V7K~D
C
C
1 2
C
C
568 0.1U_0402_10V7K~D
568 0.1U_0402_10V7K~D
1 2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
C
C
5
5
77
77
2
1 2
4 BLM18BD601S N1D_0603~D
4 BLM18BD601S N1D_0603~D
4
4
L
L
5
5
C
C
R
R
6
6
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
5
5
5
5
75
75
76
76
2
2
+
3
.3VDDH
+
V
DDH_SD
+
+
E_VDDH
P
P
E_VDDH
12
78 4.7U_0603_6.3V6K~ D
78 4.7U_0603_6.3V6K~ D
P
C
IE_PRX_MMITX_P6_C
P
C
IE_PRX_MMITX_N6_C
P
C
IE_PTX_MMIRX_P6_C
P
C
IE_PTX_MMIRX_N6_C
1 2
77 191_0402_1%~D
77 191_0402_1%~D
P
L
TRST_MMI#
U
U
8
8
3
3
16
3VDDH
.
3
9
D
V
32
E
P
2
E
P
1
E
P
6
P
E
7
P
E
5
E
P
4
E
P
3
P
E
33
P
G
13
P
E
14
U
M
31
U
M
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C
C
E
E
13
13
2
DH
_VDDH
_REFCLKP
_REFCLKM
_TXP
_TXM
_RXP
_RXM
_REXT
AD
_RST#
LTI-IO1
LTI-IO2
OZ600FJ0LN_QFN32_5X5~D
OZ600FJ0LN_QFN32_5X5~D
M
I_VCC_OUT
M
D
_CMD/MS_BS
S
S
M
C
K
M
M
M
M
M
M
M
M
S
S
D
VDD
A
V
T_VCC
D
S
D
S
I_D0
M
S
M
S
M
I_D3
M
I_D4
M
M
I_D5
M
I_D6
I_D7
M
S
_CD#
I_CLK
_CD#
D
D
_WPI
D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
C
C
5
5
64
64
2
S
/MMCDAT1
D
S
D
/MMCDAT2
S
D
/MMCDAT0
S
/MMCDAT3
D
S
/MMCDAT4
D
S
/MMCDAT5
D
S
/MMCDAT6
D
S
D
/MMCDAT7
S
/MMCCMD
D
S
/MMCCLK
D
1
C
C
C
C
5
5
5
5
59
59
60
60
2
+
3.3V_RUN_CARD
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C563
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
+
O
Z_DVDD
10
+
O
Z_AVDD
8
DD
+
S
KT_VCC
17
15
S
D
/MMCDAT1_R
28
_D1
S
D
/MMCDAT2_R
26
_D2
S
D
/MMCDAT0_R
29
27
_D1
25
_D2
S
D
/MMCDAT3_R
24
S
D
/MMCDAT4_R
23
S
D
/MMCDAT5_R
22
S
D
/MMCDAT6_R
21
S
D
/MMCDAT7_R
20
11
S
/MMCCMD_R
D
19
S
D/MMCCLK_R
18
S
D
/MMCCD#
12
S
D
WP
30
1
C
C
565
565
2
2
R
R
63 33_0402_5%~D
63 33_0402_5%~D
6
6
1 2
R
64 33_0402_5%~D
R6
6
64 33_0402_5%~D
1 2
65 33_0402_5%~D
65 33_0402_5%~D
6
6
R
R
1 2
6
6
68 33_0402_5%~D
68 33_0402_5%~D
R
R
1 2
69 33_0402_5%~D
69 33_0402_5%~D
6
6
R
R
1 2
R
R
670 33_0402_5%~D
6
70 33_0402_5%~D
1 2
6
6
72 33_0402_5%~D
72 33_0402_5%~D
R
R
1 2
R
R
73 33_0402_5%~D
73 33_0402_5%~D
6
6
1 2
74 33_0402_5%~D
6
6
74 33_0402_5%~D
R
R
1 2
76 10_0402_1%~D
6
6
76 10_0402_1%~D
R
R
1 2
C563
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
C
C
5
5
66
66
2
E
N
te: The trace need to route as
o
daisy-chain and the trace of SD signals
need to route as short as possible
3 3
E
MI request
S
D
12
E
E
@
@
R
R
22_0402_5%~D
22_0402_5%~D
1
@
E
CE
@
C
33P_0402_50V8J~D
33P_0402_50V8J~D
2
4 4
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
/MMCCLK
678
678
757
757
+
.3V_RUN_CARD
3
S
S
D1
CONN@
D1
CONN@
J
S
D
/MMCCLK
S
/MMCCMD
D
33P_0402_50V8J~D
10K_0402_5%~D
10K_0402_5%~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
5
5
5
5
72
72
70
70
2
2
D
33P_0402_50V8J~D
12
@
@
C
C
1
E
E
S
D
R
R
8
8
26
26
/MMCDAT0
758
758
S
D
/MMCDAT1
S
/MMCDAT2
D
2
S
/MMCDAT3
D
S
D
/MMCDAT4
S
/MMCDAT5
D
S
/MMCDAT6
D
S
D
/MMCDAT7
S
WP
D
S
/MMCCD#
D
S
/MMCCD#
D
S
DWP
D
E
T
T
tle
tle
Title
i
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
J
8
L
K/SD-5
C
9
C
C/VDD/SD-4
V
10
S
S1/SD-3
V
12
D/SD-2
M
C
4
A
T0/SD-7
D
3
T1/SD-8
A
D
15
A
T2/SD-9
D
14
AT3/SD-1
D
13
T4/MMC-10
A
D
11
T5/MMC-11
A
D
7
T6/MMC-12
A
D
5
T7/MMC-13
A
D
1
SW/SD
P
W
2
D
SW/SD
C
16
N
D SW
G
17
SW
D
C
18
SW
P
W
19
D
&WP/SW/GND
C
20
D
&WP/SW/GND
C
6
N
D/VSS2/SD6
G
T-SOL_156-3000000901~D
T-SOL_156-3000000901~D
o
ly for MMC/SD
n
21
N
D1
G
22
N
D2
G
LL CONFIDENTIAL/PROPRIETARY
C
C
C
ompal Electronics, Inc.
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
rd Reader OZ600FJ0
rd Reader OZ600FJ0
a
a
a
rd Reader OZ600FJ0
L
L
L
-7781
A
A
A
-7781
-7781
3
3
3
3 6
3 6
E
3 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
5
+3
US
B_MCARD2_DET#
D D
94 100K_0402_5%~D
94 100K_0402_5%~D
R6
R6
.3V_RUN
12
R_XDP_WAN_SM BCLK<7,12,13,14,15,27>
D
D
D
R_XDP_WAN_SM BDAT<7,12,13,14,15,27>
D
Mini WWAN/GPS/LTE H=5.2
CONN@
@
@
C
C
1
1
176
176
1
2
+
S
33P_0402_50V8J~D
33P_0402_50V8J~D
IM_PWR
@
@
C
C
6
6
31
31
CONN@
J
J
M
M
1
1
3
3
5
5
7
7
9
9
1
1
1
1
3
1
1
3
5
1
1
5
1
7
1
7
1
9
1
9
2
1
2
1
2
3
2
3
5
2
2
5
7
2
2
7
9
2
2
9
3
1
3
1
3
3
3
3
3
5
3
5
3
7
3
7
9
3
3
9
1
4
4
1
4
3
4
3
4
5
4
5
7
4
4
7
9
4
4
9
1
5
5
1
53
G
TYCO_1775861-1~D
TYCO_1775861-1~D
U
I
M_VPP
U
M_DATA
I
INI1
INI1
N
+
.3V_PCIE_WWAN
P
IE_WAKE#<28,35,40>
C
P
M
NI1CLK_REQ#<15>
I
C
L
K_PCIE_MINI1#<15>
C
L
K_PCIE_MINI1<15>
P
C
IE_PRX_WANTX_N1<15>
P
IE_PRX_WANTX_P1<15>
C
C
IE_PTX_WANRX_N1<15>
P
C
IE_PTX_WANRX_P1<15 >
P
P
C
IE_MCARD2_DET#<17>
+
.5V_RUN
1
C C
33P_0402_50V8J~D
33P_0402_50V8J~D
1
C
C
5
5
93
93
2
+
.3V_PCIE_WWAN
3
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C
C
6
6
10
10
2
B B
+
IM_PWR
S
1
2
U
M_RESET
I
A A
U
M_CLK
I
33P_0402_50V8J~D
33P_0402_50V8J~D
@
@
1
C
C
6
6
28
28
2
C
C
C
C
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C5
C5
94
94
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
33P_0402_50V8J~D
1
1
C
C
6
6
11
11
2
2
IM
Card Push-Push
S
U
M_RESET
I
U
M_CLK
I
16
16
6
6
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
3
33P_0402_50V8J~D
33P_0402_50V8J~D
@
@
1
C6
C6
29
29
2
C
M
I
NI1CLK_REQ#
C
L
K_PCIE_MINI1#
C
L
K_PCIE_MINI1
P
IE_PRX_WANTX_N1
C
P
IE_PRX_WANTX_P1
C
97 0 .1U_0402_10V7K~D
97 0 .1U_0402_10V7K~D
5
5
P
C
1 2
P
C
1 2
5
5
99 0 .1U_0402_10V7K~D
99 0 .1U_0402_10V7K~D
1 2
R
R
7
7
25 0_0402_5%~D@
25 0_0402_5%~D@
W
_GPS_DISABLE2#<39>
H
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
1
C
C
C
C
6
6
6
6
13
13
12
12
2
2
IM1
IM1
S
S
J
J
1
C
C
V
2
T
S
R
3
L
K
C
4
C
N
MOLEX_475531001
MOLEX_475531001
CONN@
CONN@
0
@
4
4
0
@
U
U
SRV05-4.TCT_SOT23-6~D
SRV05-4.TCT_SOT23-6~D
5
3
IE_WAKE#
IE_PTX_WANRX_N1_C
IE_PTX_WANRX_P1_C
P
C
IE_MCARD2_DET#_R
330U_D2E_6.3VM_R25~D
33P_0402_50V8J~D
330U_D2E_6.3VM_R25~D
33P_0402_50V8J~D
1
1
+
+
+
+
C
C
C
C
6
6
6
6
15
14
15
14
2
2
5
D
N
G
6
P
P
V
7
O
/
I
8
C
N
9
N
D
G
10
N
D
G
U
IM_VPP
6
5
U
M_DATA
I
4
33P_0402_50V8J~D
33P_0402_50V8J~D
1
2
330U_D2E_6.3VM_R25~D
330U_D2E_6.3VM_R25~D
@
@
C
C
6
6
30
30
G
N
D1
L
D_WWAN_OUT #
E
+
+
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
4
2
4
4
4
6
4
8
5
0
5
2
D2
PWR
Rail
+3.3V
.3Vaux
3
1
.5V
+
.3V_PCIE_WWAN
3
2
4
6
8
0
1
2
1
4
1
1
6
1
8
2
0
2
2
4
2
2
6
2
8
0
3
2
3
3
4
3
6
3
8
0
4
2
4
4
4
4
6
4
8
0
5
5
2
54
4
157 0_0402_5%~D@
157 0_0402_5%~D@
1
1
R
R
158 0_0402_5%~D@R1158 0_0402_5%~D@
R1
U
M_DATA
I
U
IM_CLK
U
I
M_RESET
U
I
M_VPP
7
7
R
R
W
AN_SMBCLK
W
W
AN_SMBDAT
W
U
BP5-
S
U
BP5+
S
U
B_MCARD2_DET#
S
L
D_WWAN_OUT #LED_W WAN_OUT#
E
U
B_MCARD2_DET#
S
+
3
19
19
7
7
R
R
1 2
100K_0402_5%~D
100K_0402_5%~D
S
S
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
ltage
o
V
Tolerance
9%
-
+
+-9%
+-5%
4
+
3
.3V_PCIE_WWAN
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
@
@
12
12
R
R
1
1
159
159
12
12
+
1
.5V_RUN
+
SIM_PWR
1 2
04 0_0402_5%~D@
04 0_0402_5%~D@
.3V_PCIE_WWAN
G
G
2
13
D
D
Q
Q
7
7
7
7
P
P
W
P
BP5- <17>
S
U
S
BP5+ <17>
U
B_MCARD2_DET# <18>
S
U
1 2
R6
97 0_0402_5%~D@R697 0_0402_5%~D@
W
r
imary Power Aux Power
ak Normal Normal
e
1000 750
330
500
@
@
R
R
1
1
160
160
W
W
AN_SMBCLK
W
W
AN_SMBDAT
W
AN_RADIO_DIS# <39>
C
H_PLTRST#_EC <17,32,35,39,40>
P
C
IE_MCARD2_DET#
RELESS_LED# <39,43>
I
250 (Wake enable)
250
5 (Not wake enable)
375
NA
3
1 2
6
6
93 0_0402_5%~D@
93 0_0402_5%~D@
R
W
L
AN_RADIO_DIS#<39>
O
C
O
C
C
EX2_WLAN_ACTIVE
O
C
C
@
@
33P_0402_50V8J~D
33P_0402_50V8J~D
R
1
D
D
3
3
1
1
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
P
C
EX2_WLAN_ACTIVE
EX2_WLAN_ACTIVE<41>
EX1_BT_ACTIVE<41>
1
00
00
6
6
2
O
C
O
EX1_BT_ACTIVE
M
NI2CLK_REQ#<15>
I
L
K_PCIE_MINI2#<15 >
C
L
K_PCIE_MINI2<15>
C
H
O
ST_DEBUG_RX<40>
P
IE_PRX_WLANTX_N2<15>
C
P
IE_PRX_WLANTX_P2<15>
C
IE_PTX_WLANRX_N2<15>
C
P
C
IE_PTX_WLANRX_P2<15>
P
P
CIE_MCARD1_DET#<18>
H_CL_CLK1<15>
C
P
P
C
H_CL_DATA1<15>
P
C
H_CL_RST1#<15>
AN_RADIO_DIS#_R
WL
2
IE_WAKE#<28,35,40>
C
R
R
R
R
M
CLK<40>
S
C
C
5
5
96 0.1U_0402_10V7K~D
96 0.1U_0402_10V7K~D
1 2
1 2
C
C
98 0.1U_0402_10V7K~D
98 0.1U_0402_10V7K~D
5
5
1 2
R
R
07 0_0402_5%~D@
7
7
07 0_0402_5%~D@
P
IE_WAKE#
C
1 2
7
7
00 0_0402_5%~D@
00 0_0402_5%~D@
1 2
02 0_0402_5%~D@
02 0_0402_5%~D@
7
7
P
IE_PRX_WLANTX_N2
C
P
IE_PRX_WLANTX_P2
C
P
IE_PTX_WLANRX_N2_C
C
P
IE_PTX_WLANRX_P2_C
C
P
IE_MCARD1_DET#
C
c
+
.5V_RUN
1
+
1
.5V_RUN
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
P
+
.3V_WLAN
3
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@
1
1
C
C
6
6
01
01
2
2
IE_PTX_WPANRX_N5<15>
C
P
C
IE_PTX_WPANRX_P5<15>
P
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C
C
6
6
19
19
2
2
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
C
C
6
6
02
02
2
C
IE_PRX_WPANTX_N5<15>
P
C
IE_PRX_WPANTX_P5<15>
P
+
3
.3V_RUN
+
.3V_PCIE_FLASH
3
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C6
C6
20
20
2
@
C
C
6
6
03
03
C
M
K_PCIE_MINI3#<15 >
L
C
L
K_PCIE_MINI3<15>
C
P
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
@
@
C
C
6
6
21
21
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C
C
6
6
04
04
2
2
EX2_WLAN_ACTIVE
O
I
NI3CLK_REQ#<15>
LK_80H<15>
C
P
C
C
6
6
17 0.1U_0402_10V7K ~D
17 0.1U_0402_10V7K ~D
1 2
1
6
6
18 0.1U_0402_10V7K ~D
18 0.1U_0402_10V7K ~D
C
C
IE_MCARD3_DET#<18>
1 2
11 1 00K_0402_5%~D
7
7
11 1 00K_0402_5%~D
R
R
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C
C
6
6
22
22
2
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C
C
6
6
05
05
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C
C
6
6
23
23
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
2
1
C
C
6
6
07
07
1
2
C
IE_WAKE#
1 2
7
7
09 0_0402 _5%~D@
09 0_0402 _5%~D@
C
IE_MCARD3_DET#
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
1
C
C
6
6
25
25
1
2
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
C
C
6
6
06
06
1
/2 Minicard Pink Pather/60GHz Card H=4
1
P
R
R
M
NI3CLK_REQ#
I
C
K_PCIE_MINI3#
L
C
K_PCIE_MINI3
L
P
H_PLTRST#_EC
C
P
C
LK_80H
P
IE_PRX_WPANTX_N5
C
P
IE_PRX_WPANTX_P5
C
P
C
IE_PTX_WPANRX_N5 _C
P
IE_PTX_WPANRX_P5_C
C
2
P
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
C
C
6
6
24
24
1
2
Mini WLAN/WIMAX H=4
+
3
.3V_WLAN
heck
C
C
608
6
08
+
3
.3V_PCIE_FLASH
C
C
626
626
CONN@
CONN@
J
J
1
3
5
7
9
1
1
3
1
1
5
1
7
1
9
21
3
2
2
5
7
2
9
2
1
3
3
3
3
5
3
7
9
3
1
4
3
4
4
5
4
7
9
4
5
1
53
TYCO_1775861-1~D
TYCO_1775861-1~D
2
CONN@
CONN@
MINI2
MINI2
J
J
1
1
3
3
5
5
7
7
9
9
1
1
1
1
1
3
3
1
1
5
5
1
1
7
7
1
1
9
9
1
1
2
1
2
2
3
3
2
2
5
5
2
7
2
7
2
2
9
9
2
1
3
1
3
3
3
3
3
5
3
5
3
7
3
7
3
9
3
9
3
41
1
4
3
4
3
4
5
4
5
4
4
7
7
4
49
9
4
1
5
1
5
53
N
G
TYCO_1775861-1~D
TYCO_1775861-1~D
W
IMAX_LED#
W
AN_LED#
L
INI3
INI3
M
M
1
3
5
7
9
1
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
4
1
4
3
4
5
4
7
4
9
5
1
G
G
N
D1
D1
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
4
2
4
4
4
6
4
8
5
0
5
2
D2
N
2
4
6
8
0
1
2
1
4
1
6
1
8
1
0
2
2
2
4
2
6
2
8
2
0
3
2
3
34
6
3
38
40
42
44
46
48
50
52
GN
D2
18
718
7
R
R
+
.3V_PCIE_FLASH
3
2
4
6
8
1
0
1
2
1
4
16
1
8
2
0
2
2
4
2
2
6
2
8
3
0
2
3
3
4
3
6
8
3
0
4
2
4
4
4
6
4
8
4
5
0
5
2
54
1
IE_MCARD1_DET#
PC
U
SB_MCARD1_DET#
+
3
.3V_WLAN
+
.5V_RUN
1
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
4
3
3
6
8
3
0
4
2
4
4
4
6
4
8
4
0
5
2
5
54
1 2
M
05
7
R705
R
1 2
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
U
L
P
C_LFRAME#
L
C_LAD3
P
L
P
C_LAD2
L
C_LAD1
P
L
P
C_LAD0
1 2
10 0_0402 _5%~D@
10 0_0402 _5%~D@
7
7
R
R
U
BP8-
S
U
S
BP8+
U
B_MCARD3_DET#
S
ELL CONFIDENTIAL/PROPRIETARY
D
tle
Title
i
i
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
R6
P
IE_MCARD1_DET#
C
U
B_MCARD1_DET#
S
S
DATA
W
AN_RADIO_DIS#_R
L
03 0_0402_5%~D@
03 0_0402_5%~D@
7
7
R
R
U
BP4-
S
U
BP4+
S
U
S
B_MCARD1_DET#
W
MAX_LED#
I
W
LAN_LED#
1 2
06 0_0402_5%~D@R706 0_0402_5%~D@
R7
IMAX_LED# STUDY FOR DEBUG
W
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q
Q
24A
24A
1
1
B_MCARD3_DET#
S
+
P
H_PLTRST#_EC
C
R
R
12 1 00K_0402_5%~D@
12 1 00K_0402_5%~D@
7
7
W
U
S
1
@
@
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
o
o
o
C
C
C
ni Card
i
i
i
ni Card
ni Card
M
M
M
A
A
A
L
L
L
1 2
6
6
92 1 00K_0402_5%~D
92 1 00K_0402_5%~D
R
R
P
IE_MCARD1_DET#
C
2
98 0_0402_5%~D@R698 0_0402_5%~D@
1 2
R
R
99 1 00K_0402_5%~D@
99 1 00K_0402_5%~D@
6
6
1 2
7
7
01 1 00K_0402_5%~D
01 1 00K_0402_5%~D
R
R
1 2
C5
C5
95 4700P_0402_25V7K~D
95 4700P_0402_25V7K~D
H
ST_DEBUG_TX <40>
O
P
H_PLTRST#_EC
C
12
S
BP4- <17>
U
S
BP4+ <17>
U
B_MCARD1_DET# <14,18>
S
U
M
DATA
S
M
DATA <40>
S
+
.3V_WLAN
3
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
W
W
IRELESS_LED#
I
RELESS_LED#
3
4
1
1
24B
24B
Q
Q
P
IE_MCARD3_DET#
ust reserve
j
1
C
+
.3V_ALW_PCH
3
4 6
4 6
4 6
3
3
3
1 2
08 0_0402_5%~D@
08 0_0402_5%~D@
7
7
R
R
1
.5V_RUN
P
C_LFRAME# <14,32,39,40>
L
P
C_LAD3 <14,32,39,40>
L
P
C_LAD2 <14,32,39,40>
L
C_LAD1 <14,32,39,40>
P
L
C_LAD0 <14,32,39,40>
P
L
BP8- <17>
S
U
S
BP8+ <17>
U
12
AN Noise
P
B_MCARD3_DET#
27
27
6
6
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
-7781
-7781
-7781
+3
.3V_ALW_PCH
+
3.3V_RUN
f
f
f
o
o
o
0
0
.
.
.
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
4
3
2
1
Power Control for Mini card2
+
3
.3V_ALW
12
6
1
16
16
+
3
1A
1A
R
R
7
7
100K_0402_5%~D
100K_0402_5%~D
R
R
7
7
13
13
.3V_ALW
12
M
61
26
26
P
100K_0402_5%~D
100K_0402_5%~D
12
R
R
7
7
14
14
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
3
3
9B
9B
5
4
100K_0402_5%~D
100K_0402_5%~D
R
R
7
721
21
C
ARD_WWA N_PWREN#
6
2
1
+
D D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
A
U
X_EN_WOWL<39>
C C
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
M
C
ARD_WWA N_PWREN<39>
B B
3
3
3
9A
9A
Q
Q
2
1
R
R
7
7
100K_0402_5%~D
100K_0402_5%~D
2
Power Control for Mini card1
4
4
Q
Q
2
12
100K_0402_5%~D
100K_0402_5%~D
.3V_ALW
+
WR_SRC_S
Q
Q
8
8
3
3
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
S
S
45
G
G
3
1M_0402_5%~D
1M_0402_5%~D
12
R
R
1
1
620
620
+
PWR_SRC_S
5
1
2
+
3
.3V_ALW
470K_0402_5%~D
470K_0402_5%~D
12
R
R
7
7
22
22
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
4
4
1B
1B
4
+3
.3V_WLAN
12
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C
C
6
6
32
32
+
0
0
4
4
Q
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
220P_0402_50V8J~D
4.7M_0402_5%~D
4.7M_0402_5%~D
12
220P_0402_50V8J~D
12
C
R
R
1
1
625
625
C
6
6
44
44
Q
Q
7
7
3
3
15
15
7
7
R
R
20K_0402_5%~D
20K_0402_5%~D
.3V_PCIE_WWAN
3
1
2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
S
S
R
R
23
23
7
7
1K_0402_5%~D
1K_0402_5%~D
M
ARD_WWA N_PWREN#
C
2
G
G
+
+
S
O_SLP_S3#<11,16,27,39,42,47>
I
R
N_ON<27,39,42,47>
U
P
C
H_PLTRST#_EC<17,32,34,39,40>
1 2
34 0_0402 _5%~D@
34 0_0402 _5%~D@
7
7
R
R
1 2
17 0_0402 _5%~D@
7
7
17 0_0402 _5%~D@
R
R
.5V_RUN
1
1
2
.3V_RUN
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
6
6
35
35
+
.3V_RUN
3
+
3
.3V_CARD
+
1
.5V_CARD
+
1
.5V_RUN
U
BP10-<17>
S
U
BP10+<17>
S
+
.3V_SUS
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
1
C
C
6
6
34
34
2
E
PRCRD_STBY_R#
X
N
ote: Add connection on pin4, pin5, pin 13
and pin14 to support GMT 2nd source part
Power Control for Mini card3
+
.3V_ALW
3
+
P
+
.3V_ALW
3
4
3A
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
M
ARD_MISC_PWRE N<39>
C
A A
43A
2
12
33
33
7
7
R
R
100K_0402_5%~D
100K_0402_5%~D
WR_SRC_S
470K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
12
R
R
7
7
28
28
61
470K_0402_5%~D
12
R
R
7
7
29
29
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
4
4
3B
3B
5
4
2
4
4
2
Q
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
4.7M_0402_5%~D
4.7M_0402_5%~D
12
R
R
1
1
628
628
+
.3V_PCIE_FLASH
3
12
R
R
30
30
7
7
20K_0402_5%~D
220P_0402_50V8J~D
220P_0402_50V8J~D
12
C
C
6
6
50
50
20K_0402_5%~D
+
.3V_CARDAUX
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+
1
C
C
6
6
46
46
2
Express Card PWR S/W
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
6
6
33
33
U
U
1
1
4
4
17
2
12
20
1
6
19
4
5
1
3
1
4
6
1
TPS2231MRGPR-2_QFN20_4X4~D
TPS2231MRGPR-2_QFN20_4X4~D
A
A
U
3
.
3VIN
1
5VIN
.
S
H
S
T
S
Y
O
C
N
C
N
C
N
C
N
C
N
C
XIN
DN#
BY#
SRST#
#
3
1
P
C
R
XOUT
U
.
3VOUT
5VOUT
.
E
C
P
C
Express Card Conn.
1 2
7
7
24 0_0402_5%~D@
24 0_0402_5%~D@
R
R
1 2
R
R
27 0_0402_5%~D@
7
7
27 0_0402_5%~D@
1
1
4
4
L
L
49 DLW 21SN900SQ2L_0805_4P~D
49 DLW 21SN900SQ2L_0805_4P~D
3
.3V_CARD
2
2
3
3
C
RD_SMBDAT<40>
A
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
6
6
49
49
P
IE_PRX_EXPTX_N3<15>
C
P
IE_PRX_EXPTX_P3<15>
2
C
P
IE_PTX_EXPRX_N3<15>
C
P
C
IE_PTX_EXPRX_P3<15>
RST#
P
USB#
LKEN
G
P
C
C
C
+
.3V_CARDAUX
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
6
6
6
6
43
43
42
42
2
2
15
3
11
C
RD_RESET#
A
8
E
PRCRD_CPPE#
X
10
PE#
N
A
A
P
E
L
L
C
USB#
P
9
18
7
D
21
D
U
BP10_D-
S
U
BP10_D+
S
C
P
USB#
C
A
RD_SMBCLK<40>
C
IE_WAKE#<28,34,40>
PCLK_REQ#<15>
X
K_PCIE_EXP#<15>
K_PCIE_EXP<15>
RD_SMBCLK
C
A
RD_SMBDAT
C
A
RD_RESET#
E
PRCRD_CPPE#
X
6
6
C
C
6
6
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
C
C
1
1
E
E
E
E
11
11
10
10
2
2
+
3
.3V_SUS
2.2K_0402_5%~D
2.2K_0402_5%~D
12
47 0.1U_0402_10V7K ~D
47 0.1U_0402_10V7K ~D
P
IE_PTX_EXPRX_N3_C
C
1 2
P
IE_PTX_EXPRX_P3_C
C
1 2
48 0.1U_0402_10V7K ~D
48 0.1U_0402_10V7K ~D
+
.3V_CARD
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
6
6
6
6
41
41
40
40
2
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
1
E
E
12
12
2
+
1
.5V_CARD
0.1U_0402_25V6K~D
2.2K_0402_5%~D
2.2K_0402_5%~D
12
R
R
7
7
31
31
0.1U_0402_25V6K~D
1
C
R
R
7
7
32
32
C
6
6
45
45
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+
.5V_CARD
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
6
6
37
37
2
CONN@
CONN@
E
E
XP1
XP1
J
J
1
G
D1
N
2
U
B_D-
S
3
US
B_D+
4
CP
USB#
5
RE
SERVED
6
RESERVED
7
B_CLK
SM
8
SMB_DAT
9
.5V
+1
.5V
+1
KE#
WA
3
.3VAUX
+
E
RST#
P
3
.3V
+
.3V
3
+
KREQ#
L
C
PE#
P
C
E
FCLK-
R
E
FCLK+
R
N
D
G
R_N0
E
P
R_P0
E
P
D
N
G
E
T_N0
P
E
T_P0
P
D
N
G
G
D
N
G
N
D
G
D
N
G
N
D
T-SOL_5421005002000-9_NR
T-SOL_5421005002000-9_NR
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
C
C
6
6
38
38
2
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
T
T
Title
itle
itle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
IE-SATA SW / PCIE PWR
C
C
C
IE-SATA SW / PCIE PWR
IE-SATA SW / PCIE PWR
L
L
L
-7781
-7781
A
A
A
-7781
1
3
3
3
5 6
5 6
5 6
o
o
o
f
f
f
1
1
1
.
0
0
0
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
D D
L
L
7
7
9
U
B3RN2
U
SB3RN2<17>
U
S
B3RP2<17>
U
B3TN2<17>
S
U
S
C C
B B
C
C
4
4
10 0 .1U_0402_10V7K~D
10 0 .1U_0402_10V7K~D
B3TP2<17>
U
S
B_PWR_SHR_EN#<39>
11 0 .1U_0402_10V7K~D
4
4
11 0 .1U_0402_10V7K~D
C
C
S
U
SB3RP2
U
S
B3TN2_C
12
U
S
B3TP2_C
12
1 2
626 0_0402_5%~D@
626 0_0402_5%~D@
1
1
R
R
9
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
1 2
616 0_0402_5%~D@
616 0_0402_5%~D@
1
1
R
R
1 2
R
R
609 0_0402_5%~D@
609 0_0402_5%~D@
1
1
L
L
4
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R
R
R
R
8
8
9
9
4
1
1 2
612 0_0402_5%~D@
612 0_0402_5%~D@
1
1
1 2
615 0_0402_5%~D@
615 0_0402_5%~D@
1
1
S
B
#
3
3
2
2
3
2
U
BP0-<17>
S
U
BP0+<17>
S
+
3
2
V_ALW
5
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
7
7
15
15
2
4
U
S
B3RN2_D-
U
S
B3RP2_D+
U
S
B3TN2_D-
U
S
B3TP2_D+
U
S
B_PWR_SHR_VBU S_EN<39>
U
U
2
2
8
S
B
7
Y
-
6
Y
+
5
V
D
D
LG55584AVTR_TDFN8_2X2
S
S
LG55584AVTR_TDFN8_2X2
U
S
B3RN2_D-
U
S
B3RP2_D+
U
B3TN2_D-
S
U
B3TP2_D+
S
U
BP1+<17>
S
U
S
BP1-<17>
1
I
N
T
2
D
-
3
D
+
4
S
L
E
9
G
N
D
S
B
#
@
@
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Q
D
D
9
9
7
7
1
2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
IP4292CZ10-TBR_XSON10_2.5X1~D
1 2
84 0_0402_5%~D@
84 0_0402_5%~D@
7
7
R
R
P
RSHARE_EN
W
U
S
BP0_D-
U
BP0_D+
S
S
L
E
+
V_ALW
5
10K_0402_5%~D
10K_0402_5%~D
1 2
2
13
D
D
@
S
S
@
10K_0402_5%~D
10K_0402_5%~D
1
2
G
G
26
1
1
26
1
0
9
7
6
4
1
614
614
1
1
R
R
R
R
613
613
1
1
3
U
S
B3RN2_D-
U
S
B3RP2_D+
U
B3TN2_D-
S
U
B3TP2_D+
S
2
2
L5
L5
4
1
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
1 2
37 0_0402_5%~D@
7
7
37 0_0402_5%~D@
R
R
1 2
R
R
7
7
39 0_0402_5%~D@
39 0_0402_5%~D@
2
G
G
3
2
+
V_ALW
5
R
R
16
8
8
16
100K_0402_5%~D
100K_0402_5%~D
1 2
P
W
RSHARE_EN#
13
D
D
8
4
4
8
Q
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
3
2
U
U
S
BP1_D+
S
BP1_D-
+
SB_SIDE_PWR
U
+
5
+
5
1
+
+
2
V_ALW
1
2
V_ALW
1
2
2
JU
JU
SB2
U
S
B3TP2_D+
U
B3TN2_D-
2
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
U
B_SIDE_EN#<30,39>
S
E
S
ATA_USB_PWR_EN #<39>
W
RSHARE_EN#
S
U
BP1_D-
S
U
BP1_D+
S
U
B3RP2_D+
S
D
D
7
7
U
SB3RN2_D-
3
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
150U_D2_6.3VY_R15M~D
150U_D2_6.3VY_R15M~D
1
C655
C655
C
C
6
6
52
52
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
C678
C678
1
1
0
0
U_0805_10V6K~D
U_0805_10V6K~D
C676
C676
3
2
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
6
6
77
77
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
P
C
C
6
6
75
75
SB2
9
SS
TX+
1
V
US
B
8
SS
TX-
2
D
-
7
G
D
N
3
D
+
6
S
RX+
S
4
G
D
N
5
S
RX-
S
SANTA_370300-1
SANTA_370300-1
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5
U
U
1
D
N
O
G
V
2
O
I
N
V
V
3
O
I
N
V
V
4
N
E
F
G
G
547I2P81U_MSOP8
547I2P81U_MSOP8
8
4
4
8
U
U
1
N
D
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2
N
I
3
N
I
4
N
1#
E
5
2#
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E
TPS2560DRCR-PG1.1_SON10_3X3~D
TPS2560DRCR-PG1.1_SON10_3X3~D
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GN
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D
N
12
GN
D
13
G
D
N
+
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SB_SIDE_PWR
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UT
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L
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10
ULT1#
A
F
9
T1
U
O
8
U
T2
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7
IM
L
I
6
ULT#2
A
F
11
-
PAD
T
U
ATA_SIDE_PWR
B_OC0# <17>
S
U
B_OC1# <17>
S
U
S
B_OC0# <17>
1
+
V_USB_CHG_PWR
5
12
48
48
7
7
R
R
24.9K_0402_1%~D
24.9K_0402_1%~D
8
8
7
7
D
L
L
5
5
9
U
S
U
SB3RN1<17>
U
B3RP1<17>
S
U
SB3TN1<17>
U
B3TP1<17>
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S
B3RN1
U
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B3RP1
U
B3TN1_C
S
12
C
C
12 0 .1U_0402_10V7K~D
4
4
12 0 .1U_0402_10V7K~D
U
S
B3TP1_C
12
13 0 .1U_0402_10V7K~D
13 0 .1U_0402_10V7K~D
4
4
C
C
5
9
4
4
1
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
1 2
R
R
605 0_0402_5%~D@
605 0_0402_5%~D@
1
1
1 2
1
1
604 0_0402_5%~D@
604 0_0402_5%~D@
R
R
L
L
4
1
DLW21SN900HQ2L_0805_4P~D
DLW21SN900HQ2L_0805_4P~D
R
R
R
R
96
96
4
1
1 2
606 0_0402_5%~D@
1
1
606 0_0402_5%~D@
1 2
603 0_0402_5%~D@
603 0_0402_5%~D@
1
1
3
3
2
2
3
2
U
B3RN1_D-
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U
S
B3RP1_D+
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3
2
SB3TN1_D-
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2
4
5
3
8
IP4292CZ10-TBR_XSON10_2.5X1~D
IP4292CZ10-TBR_XSON10_2.5X1~D
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BP0_D+
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BP0_D-
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U
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0
1
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S
9
U
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7
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SB3TP1_D+
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1
DLW21SN900SQ2L_0805_4P~D
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R
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B3RP1_D+
B3TN1_D-
5
5
1
1
4
1
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7
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36 0_0402 _5%~D@
36 0_0402 _5%~D@
1 2
40 0_040 2_5%~D@
40 0_040 2_5%~D@
7
7
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
U
SBP0_R_D+
3
3
U
S
BP0_R_D-
2
2
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+
5
V_USB_CHG_PWR
150U_D2_6.3VY_R15M~D
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6
6
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54
51
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BP0_R_D-
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D
LL CONFIDENTIAL/PROPRIETARY
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C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
Title
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
U
U
U
B x2
S
S
S
B x2
B x2
L
L
L
-7781
A
A
A
-7781
-7781
1
3
3
3
6 6
6 6
6 61Friday, February 24, 2012
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o
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1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
5
4
3
2
1
ESATA Repeater
+
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ATA_PRX_DTX_N4_C<14>
S
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ATA_PRX_DTX_P4_C<14>
S
C C
S
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S
ATA_PTX_DRX_N4_C
E
ATA_PRX_DTX_N4_C
S
E
SATA_PRX_DTX_P4_C
3
1 2
R
R
41 0_040 2_5%~D@
41 0_040 2_5%~D@
7
7
E
ATA_PTX_DRX_P4
S
12
C
C
63 0.01U_0 402_16V7K~D
63 0.01U_0 402_16V7K~D
6
6
C
C
6
6
C
C
6
6
C
C
6
6
E
ATA_PTX_DRX_N4
S
12
64 0.01U_0 402_16V7K~D
64 0.01U_0 402_16V7K~D
E
SATA_PRX_DTX_N4
12
65 0.01U_0 402_16V7K~D
65 0.01U_0 402_16V7K~D
E
SATA_PRX_DTX_P4
12
66 0.01U_0 402_16V7K~D
66 0.01U_0 402_16V7K~D
.3V_RUN
+3
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
U
U
4
4
4
4
7
E
N
17
N
C_GND_VDD
19
18
1
2
4
5
3
13
21
PS8513BTQFN20GTR-A0_TQFN20_4X4
PS8513BTQFN20GTR-A0_TQFN20_4X4
N
_GND_VDD
C
N
C
_GND_VDD
A
_
INp
A
_
INn
B
OUTn
_
B
_OUTp
G
D
N
G
D
N
G
N
D
P
EXT/NC/VDD
R
N
C
/GND/VDD
A
A
A
B
_
_
P
P
_
_
OUTp
OUTn
B
B
.3V_RUN_U44
+3
JP
JP
9
9
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
V
V
PRE
PRE
_
_
0.01U_0402_16V7K~D
1
1
C
C
C
C
6
6
661
661
62
62
2
2
6
C
C
16
C
C
20
10
9
8
15
14
11
INp
12
INn
R
XT
E
E
S
ATA_PE1
E
ATA_PE2
S
E
ATA_PTX_DRX_P4_RP
S
E
ATA_PTX_DRX_N4_RP
S
E
ATA_PRX_DTX_P4_RP
S
E
ATA_PRX_DTX_N4_RP
S
+
S
ATA_SIDE_PWR
1
+
+
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
150U_D2_6.3VY_R15M~D
150U_D2_6.3VY_R15M~D
C
C
C
C
1
6
6
6
6
68
68
67
67
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
@
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
1
@
@
R
R
1
1
595
595
2
@
0_0402_5%~D
0_0402_5%~D
12
12
12
@
@
R
R
R
R
R
1
1
594
594
R
7
7
7
7
42
42
43
43
J
J
SA1
E
E
SA1
1
V
US
U
BP2_D-
S
U
S
BP2_D+
B B
0
0
9
9
L
L
U
BP2+<17>
S
U
BP2-<17>
S
A A
5
1
1
4
4
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
1 2
150 0_0402_5%~D@
1
1
150 0_0402_5%~D@
R
R
1 2
R
1151 0_0402_5%~D@R1151 0_0402_5%~D@
4
U
BP2_D+
S
2
2
U
SBP2_D-
3
3
2
3
4
4
7
7
D
D
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
1
P
lace D74 close to JESATA1
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
E
S
ATA_PTX_DRX_P4_RP
E
ATA_PTX_DRX_N4_RP
S
E
ATA_PRX_DTX_N4_RP
S
E
ATA_PRX_DTX_P4_RP
S
S
A
TA_PTX_DRX_P4
1 2
C
C
6
6
71 0.01U_0402_16V7 K~D
71 0.01U_0402_16V7 K~D
S
TA_PTX_DRX_N4
A
1 2
C
C
72 0.01U_0402_16V7 K~D
6
6
72 0.01U_0402_16V7 K~D
S
A
TA_PRX_DTX_N4
1 2
6
6
73 0.01U_0402_16V7 K~D
73 0.01U_0402_16V7 K~D
C
C
S
A
TA_PRX_DTX_P4
1 2
74 0.01U_0402_16V7 K~D
74 0.01U_0402_16V7 K~D
6
6
C
C
2
B
2
D
-
3
D
+
4
G
N
D
5
G
N
D
6
A
+
7
A
-
8
G
N
D
9
B
-
0
1
B
+
11
G
D
N
12
G
N
D
13
G
N
D
14
G
ND
15
G
N
D
TYCO_2129156-3
TYCO_2129156-3
CONN@
CONN@
U
U
SB
SB
ESATA
ESATA
D
E
LL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
ompal Electronics, Inc.
o
mpal Electronics, Inc.
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
U
U
U
B/ESATA/IO/MDC
B/ESATA/IO/MDC
S
S
S
B/ESATA/IO/MDC
L
L
L
-7781
A-7781
A
A
-7781
1
3
3
3
7 6
7 6
7 6
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
5
D D
C C
B B
P
D_PCH_LANE_P0<16>
D
P
D_PCH_LANE_N0<16>
D
D_PCH_LANE_P1<16>
P
D
P
D_PCH_LANE_N1<16>
D
D_PCH_LANE_P2<16>
P
D
D_PCH_LANE_N2<16>
P
D
P
D_PCH_LANE_P3<16>
D
D_PCH_LANE_N3<16>
P
D
D
PD_PCH_DOCK_HPD
C
C
6
6
90 0.1U_0402_10V7K~D
90 0.1U_0402_10V7K~D
12
79 0.1U_0402_10V7K~D
79 0.1U_0402_10V7K~D
C6
C6
2
1
6
6
81 0.1U_0402_10V7K~D
81 0.1U_0402_10V7K~D
C
C
2
1
83 0.1U_0402_10V7K~D
83 0.1U_0402_10V7K~D
6
6
C
C
12
92 0.1U_0402_10V7K~D
92 0.1U_0402_10V7K~D
6
6
C
C
12
85 0.1U_0402_10V7K~D
85 0.1U_0402_10V7K~D
6
6
C
C
12
6
6
87 0.1U_0402_10V7K~D
87 0.1U_0402_10V7K~D
C
C
12
6
6
89 0.1U_0402_10V7K~D
89 0.1U_0402_10V7K~D
C
C
12
D
P
D_PCH_DOCK_HPD<16>
lo
se to DOCK
C
Its for Enhance ESD on dock issue.
12
57
57
7
7
R
R
100K_0402_5%~D
100K_0402_5%~D
D
D_PCH_LANE_P0_C
P
D
P
D_PCH_LANE_N0_C
D
P
D_PCH_LANE_P1_C
D
P
D_PCH_LANE_N1_C
D
D_PCH_LANE_P2_C
P
D
P
D_PCH_LANE_N2_C
D
P
D_PCH_LANE_P3_C
D
P
D_PCH_LANE_N3_C
4
D
O
CK_LOM_SPD10LED_GRN#<31>
7 33_0402_5%~D
7 33_0402_5%~D
RE
RE
2
E
E
8 33_0402_5%~D
8 33_0402_5%~D
R
R
9 33_0402_5%~D
9 33_0402_5%~D
E
E
R
R
E
E
10 33_0402_5%~D
10 33_0402_5%~D
R
R
2
13 33_0402_5%~D
13 33_0402_5%~D
E
E
R
R
14 33_0402_5%~D
14 33_0402_5%~D
E
E
R
R
15 33_0402_5%~D
15 33_0402_5%~D
E
E
R
R
16 33_0402_5%~D
16 33_0402_5%~D
E
E
R
R
D
D
D
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1
C
C
6
6
95
95
2
S
ICE_BAT_PRES#<39,53>
L
+
D
OCK_PWR_BAR
D
P
D_CA_DET<26>
1
12
12
1
12
12
12
12
P
D_DOCK_AUX<26>
D_DOCK_AUX<26>
P
D_DOCK_AUX#<26>
P
D
PD_PCH_DOCK_HPD
+
N
BDOCK_DC_IN_SS
B
UE_DOCK<23>
L
R
E
G
EEN_DOCK<23>
R
H
YNC_DOCK<23>
S
V
S
YNC_DOCK<23>
C
K_MSE<40>
L
D
T_MSE<40>
A
D
A
I_BCLK#<29>
D
I_LRCK#<29>
A
D
I_DI<29>
A
D
I_DO#<29>
A
D
I_12MHZ#<29>
A
D
_
D
_
D
_
D
_
D
LFRAME#<39>
_
D
CLKRUN#<39>
_
D
D
_
C
K_PCI_DOCK<17>
L
D
O
CK_SMB_CLK<40>
D
CK_SMB_DAT< 40>
O
D
O
CK_SMB_ALERT#<39,53>
D
O
D
OCK_PWR_BTN#<40>
1
2
D_DOCK<23>
LAD0<39>
LAD1<39>
LAD2<39>
LAD3<39>
_
SERIRQ<39>
DLDRQ1#<39>
CK_PSID<44>
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
S
L
ICE_BAT_PRES#
@
@
1
C
C
E
E
6
6
2
OCK_DET_1
D
D
P
D_CA_DET
D
D_DOCK_LANE_P0
P
D
D_DOCK_LANE_N0
P
D
D_DOCK_LANE_P1
P
D
P
D_DOCK_LANE_N1
D
D_DOCK_LANE_P2
P
D
D_DOCK_LANE_N2
P
D
D_DOCK_LANE_P3
P
D
D_DOCK_LANE_N3
P
D
D_DOCK_AUX
P
D
D_DOCK_AUX#
P
B
L
UE_DOCK
R
D_DOCK
E
G
EEN_DOCK
R
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
C
C
7
7
02
02
3
CONN@
CONN@
JD
JD
OCK1
OCK1
1
1
3
3
5
5
7
7
9
9
1
1
1
1
1
3
13
1
5
15
7
1
17
9
1
19
1
2
21
3
2
23
5
2
25
7
2
27
9
2
29
1
3
31
3
3
33
5
3
35
7
3
37
3
9
39
1
4
41
4
3
43
4
5
45
4
7
47
4
9
49
5
1
51
5
3
53
5
5
55
7
5
5
7
9
5
5
9
1
6
6
1
3
6
6
3
5
6
6
5
7
6
6
7
6
9
6
9
7
1
7
1
7
3
7
3
7
5
7
5
7
7
7
7
7
9
7
9
1
8
8
1
3
8
8
3
5
8
8
5
8
7
8
7
8
9
8
9
9
1
9
1
9
3
9
3
5
9
9
5
7
9
9
7
9
9
9
9
101
1
1
0
103
1
3
0
105
1
0
5
107
1
0
7
109
1
0
9
111
1
1
1
113
1
3
1
115
1
1
5
117
1
1
7
119
1
1
9
121
1
2
1
123
1
3
2
125
1
5
2
127
1
7
2
129
1
2
9
131
1
3
1
133
1
3
3
135
1
5
3
137
1
3
7
139
1
3
9
141
1
1
4
143
1
4
3
145
G
D1
N
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
2
3
@
@
D
D
3
3
3
3
1
146
P
147
P
148
P
153
S
154
S
155
S
156
S
157
S
158
S
W
R1
W
R1
R1
W
h
ield_G
ield_G
h
ield_G
h
h
ield_G
ield_G
h
hield_G
JAE_WD2F144W B1
JAE_WD2F144W B1
2
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
3
8
4
0
4
2
4
4
4
6
4
8
5
0
5
2
5
4
5
6
5
8
6
0
6
2
6
4
6
6
6
8
7
0
7
2
7
4
7
6
7
8
8
0
8
2
8
4
8
6
8
8
9
0
9
2
9
4
9
6
9
8
1
0
0
1
2
0
1
0
4
1
0
6
1
0
8
1
0
1
1
1
2
1
1
4
1
6
1
1
8
1
1
2
0
1
2
2
1
4
2
1
2
6
1
2
8
1
0
3
1
2
3
1
3
4
1
3
6
1
8
3
1
0
4
1
2
4
1
4
4
P
W
R2
P
W
R2
P
R2
W
G
D2
N
S
ield_G
h
S
ield_G
h
S
h
ield_G
S
ield_G
h
S
ield_G
h
S
h
ield_G
D
OCK_AC_OFF
2
4
D
P
0
2
4
6
8
0
2
4
6
8
0
2
6
8
0
2
4
6
8
0
2
4
6
8
0
2
4
6
8
0
2
4
6
8
0
2
4
6
8
0
2
4
6
8
C_CA_DET
D
C_DOCK_LANE_P0
P
D
C_DOCK_LANE_N0
P
D
C_DOCK_LANE_P1
P
D
C_DOCK_LANE_N1
P
D
C_DOCK_LANE_P2
P
D
C_DOCK_LANE_N2
P
D
C_DOCK_LANE_P3
P
D
C_DOCK_LANE_N3
P
D
C_DOCK_AUX
P
D
C_DOCK_AUX#
P
D
P
C_PCH_DOCK_HPD
S
TA_PRX_DKTX_P5
A
S
TA_PRX_DKTX_N5
A
S
A
TA_PTX_DKRX_P5
S
A
TA_PTX_DKRX_N5
U
S
BP6_D+
U
BP6_D-
S
D
O
CK_DET_R#
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
C
C
1
7
7
03
03
2
6
8
1
1
1
1
1
2
2
2
2
2
3
3
34
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
9
9
9
9
9
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
149
150
151
152
159
160
161
162
163
164
D
O
CK_AC_OFF <39,53>
D
O
CK_LOM_SPD100LED_ORG# <31>
D
PC_CA_DET <26>
17 33_0402_5%~D
17 33_0402_5%~D
E
E
R
R
1 2
18 33_0402_5%~D
18 33_0402_5%~D
E
E
R
R
1
19 33_0402_5%~D
19 33_0402_5%~D
E
E
R
R
1
E
E
20 33_0402_5%~D
20 33_0402_5%~D
R
R
1 2
21 33_0402_5%~D
21 33_0402_5%~D
E
E
R
R
1 2
22 33_0402_5%~D
22 33_0402_5%~D
E
E
R
R
1 2
R
R
23 33_0402_5%~D
23 33_0402_5%~D
E
E
1 2
24 33_0402_5%~D
24 33_0402_5%~D
E
E
R
R
1 2
D
C_DOCK_AUX <26>
P
D
C_DOCK_AUX# <26>
P
A
C
AV_DOCK_SRC# <53>
D
T_DDC2_DOCK <23>
A
C
K_DDC2_DOCK <23>
L
6
6
97 0.01U_0402_16V7K~D
97 0.01U_0402_16V7K~D
C
C
6
6
98 0.01U_0402_16V7K~D
98 0.01U_0402_16V7K~D
C
C
1 2
6
6
99 0.01U_0402_16V7K~D
99 0.01U_0402_16V7K~D
C
C
1 2
7
7
00 0.01U_0402_16V7K~D
00 0.01U_0402_16V7K~D
C
C
U
S
U
S
C
LK_KBD <40>
D
A
T_KBD <40>
U
S
B3RN4 <17>
U
B3RP4 <17>
S
U
S
B3TN4 <17>
U
B3TP4 <17>
S
B
EATH_LED# <39,43>
R
D
O
CK_LOM_ACTLED_YEL# <31>
D
CK_LOM_TRD0+ <31>
O
D
CK_LOM_TRD0- <31>
O
D
O
CK_LOM_TRD1+ <31>
D
CK_LOM_TRD1- <31>
O
+
OM_VCT
L
D
CK_LOM_TRD2+ <31>
O
D
O
CK_LOM_TRD2- <31>
D
O
CK_LOM_TRD3+ <31>
D
O
CK_LOM_TRD3- <31>
D
OCK_DCIN_IS+ <52>
D
O
CK_DCIN_IS- <52>
D
OCK_POR_RST# <40>
+
D
OCK_PWR_BAR
D
A
I_12MHZ#
12
11
@
11
@
E
E
R
R
10_0402_1%~D
10_0402_1%~D
1
8
@
8
@
E
E
C
C
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
2
12
12
BP3+ <17>
BP3- <17>
2
2
2
2
3
1
1
672 0_0402_ 5%~D
672 0_0402_ 5%~D
R
R
1
1
673 0_0402_ 5%~D
673 0_0402_ 5%~D
R
R
I solution for E-Docking USB
M
E
+
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
D
I_BCLK#
A
12
@
E
E
@
R
R
10_0402_1%~D
10_0402_1%~D
1
E
E
@
@
C
C
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
2
D
P
C_PCH_LANE_P0_C
D
P
C_PCH_LANE_N0_C
D
C_PCH_LANE_P1_C
P
D
C_PCH_LANE_N1_C
P
D
P
C_PCH_LANE_P2_C
D
C_PCH_LANE_N2_C
P
D
P
C_PCH_LANE_P3_C
D
C_PCH_LANE_N3_C
P
S
TA_PRX_DKTX_P5_C <14>
A
S
A
TA_PRX_DKTX_N5_C <14>
S
A
TA_PTX_DKRX_P5_C <14>
S
A
TA_PTX_DKRX_N5_C <14>
3
@
5
5
3
@
L
L
2
3
DLW21SN900SQ2L_0805_4P~D
DLW21SN900SQ2L_0805_4P~D
OM_VCT
L
12
12
9
9
12
12
1
@
@
01
01
7
7
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
3
3
2
2
D
D
21
1
1
4
4
6
6
91 0.1U_0402_10V7K~D
91 0.1U_0402_10V7K~D
C
C
12
80 0.1U_0402_10V7K~D
80 0.1U_0402_10V7K~D
6
6
C
C
12
6
6
82 0.1U_0402_10V7K~D
82 0.1U_0402_10V7K~D
C
C
12
6
6
84 0.1U_0402_10V7K~D
84 0.1U_0402_10V7K~D
C
C
2
1
93 0.1U_0402_10V7K~D
6
6
93 0.1U_0402_10V7K~D
C
C
12
6
6
86 0.1U_0402_10V7K~D
86 0.1U_0402_10V7K~D
C
C
12
88 0.1U_0402_10V7K~D
88 0.1U_0402_10V7K~D
6
6
C
C
12
94 0.1U_0402_10V7K~D
94 0.1U_0402_10V7K~D
6
6
C
C
12
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1
C
C
6
6
96
96
lo
C
2
Its for Enhance ESD on dock issue.
S
U
S
U
D
CK_DET#
O
D
O
7
7
55 1 0K_0402_5%~D
55 1 0K_0402_5%~D
R
R
CK_DET# <39>
C
L
K_PCI_DOCK
12
56
7
7
56
R
R
33_0402_5%~D
33_0402_5%~D
1
04
04
7
7
C
C
12P_0402_50V8J~D
12P_0402_50V8J~D
2
1 2
D
P
C_PCH_DOCK_HPD <16>
se to DOCK
BP6+ <17>
BP6- <17>
1
C_PCH_LANE_P0 <16>
P
D
C_PCH_LANE_N0 <16>
P
D
P
C_PCH_LANE_P1 <16>
D
C_PCH_LANE_N1 <16>
P
D
C_PCH_LANE_P2 <16>
P
D
C_PCH_LANE_N2 <16>
P
D
P
C_PCH_LANE_P3 <16>
D
P
C_PCH_LANE_N3 <16>
D
D
C_PCH_DOCK_HPD
P
+
3
.3V_ALW
12
58
58
7
7
R
R
100K_0402_5%~D
100K_0402_5%~D
A A
LL CONFIDENTIAL/PROPRIETARY
E
D
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
C
C
tle
tle
Title
i
i
T
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
CKING CONN
O
O
O
CKING CONN
CKING CONN
D
D
D
-7781
-7781
A
A
A
-7781
L
L
L
0
0
.
.
.
0
1
1
8 6
8 6
8 6
3
3
3
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
o
o
o
.3V_ALW
+3
1 2
96 10K_0402 _5%~D
96 10K_0402 _5%~D
7
7
R
R
1 2
R7
R7
98 100K_040 2_5%~D
98 100K_040 2_5%~D
1 2
R
R
7
7
61 100K_040 2_5%~D
61 100K_040 2_5%~D
1 2
7
7
63 100K_040 2_5%~D
63 100K_040 2_5%~D
R
.3V_RUN
3
+
.3V_ALW
3
+
V
A_ID
G
R
1 2
60 100K_040 2_5%~D
60 100K_040 2_5%~D
7
7
R
R
1 2
7
7
74 100K_040 2_5%~D
74 100K_040 2_5%~D
R
R
1 2
R7
R7
76 100K_040 2_5%~D
76 100K_040 2_5%~D
1 2
68 10K_0402 _5%~D
68 10K_0402 _5%~D
R7
R7
1 2
7
7
69 100K_040 2_5%~D
69 100K_040 2_5%~D
R
R
1
7
7
78 100K_040 2_5%~D
78 100K_040 2_5%~D
R
R
1 2
62 10K_0402 _5%~D
62 10K_0402 _5%~D
7
7
R
R
1
7
7
71 100K_040 2_5%~D
71 100K_040 2_5%~D
R
R
1 2
R
R
4
4
57 100K_040 2_5%~D
57 100K_040 2_5%~D
1
7
7
66 100K_040 2_5%~D@
66 100K_040 2_5%~D@
R
R
1
7
7
72 10K_0402 _5%~D@
72 10K_0402 _5%~D@
R
R
1 2
7
7
67 100K_040 2_5%~D
67 100K_040 2_5%~D
R
R
1 2
7
7
75 10K_0402 _5%~D
75 10K_0402 _5%~D
R
R
1 2
1
1
582 100K_040 2_5%~D
582 100K_040 2_5%~D
R
R
1 2
R
R
1
1
583 100K_040 2_5%~D
583 100K_040 2_5%~D
1
R
R
3 1
3 1
1 2
8
8
R
R
D D
C C
B B
Discrete
5
DY
N_TURB_PWR_ALR T#
H
W
_GPS_DISABLE2#
P
OCHOT_GATE
R
C
U_DETECT#
P
S
ICE_BAT_PRES#
L
W
WAN_RADIO_DIS#
U
S
B_PWR_SHR_EN#
U
SB_SIDE_EN#
E
ATA_USB_PWR_EN #
S
U
S
B_PWR_SHR_VBU S_EN
2
O
CK_SMB_ALERT#
D
RELESS_ON#/OFF
I
W
2
C
ARD_PCIE_SATA#
M
W
I
RELESS_ON#/OFF
2
S
P
_TPM_LPC_EN
2
L
C
D_TST
S
S_LED_MASK#
Y
D
PU_PWR_EN
G
G
X_MEM_VTT_ON
F
ARGE_EN
H
C
2
00K_0402_5%~D
00K_0402_5%~D
V
G
1 2
R
R
8
03 1 00K_0402_5%~D@
03 1 00K_0402_5%~D@
8
V
G
A_ID
A_ID0
00 100K_0402_5%~D
00 100K_0402_5%~D
R
T_SWITCH<23>
C
D
C_RST_DIS#<30>
M
C
ARD_MISC_PWRE N<35>
M
OCHOT_GATE<52>
R
P
CK_SMB_ALERT#<38,53>
O
D
UCH_SCREEN_PD#<24>
O
T
S
B_SIDE_EN#<30,36>
U
_I2S_NB_CODEC#<29>
N
E
H_PWR_STATE#<32>
S
U
N
_DOCK_PWR_BAR<53>
E
NEL_BKEN_EC<24>
A
P
N
VDD_PCH<16,24>
E
D_TST<24>
C
L
ID_DISABLE#<44>
S
P
AT_PRES#<44,53>
B
P
CKED<31>
O
D
CK_DET#<38>
O
D
D_NB_MUTE#<29>
U
A
ARD_WWA N_PWREN<35>
C
M
C
D_VCC_TEST_EN<24>
L
D_OFF<24>
C
C
U
D_HP_NB_SENSE<29,30>
A
S
ATA_USB_PWR_EN #<36>
E
DULE_ON<53>
O
M
ICE_BAT_ON<53>
L
S
L
ICE_BAT_PRES#<38,53>
S
DULE_BATT_PRES#<44,53>
O
M
ARGE_MODULE_BATT<53>
H
C
ARGE_PBATT<53>
H
C
E
FAULT_OVRDE<53>
D
S
B_PWR_SHR_EN#<36>
U
P
U_DETECT#<7>
C
D_SATA_PCIE#_DET<28>
O
M
1
1
16 PAD~D@
16 PAD~D@
T
T
DD_WAKE#<28>
O
Z
C
M5882_ALERT#<32>
B
SACK#<16>
U
S
T
T
1
1
11 PAD~D@
11 PAD~D@
10 PAD~D@
10 PAD~D@
1
1
T
T
09 PAD~D@
09 PAD~D@
1
1
T
T
P_ME_CSW_DEV#<14,18>
L
S
A
N_DISABLE#_R<31>
L
Y
S_LED_MASK#<43>
S
I
O_EXT_WAKE#<18>
S
RELESS_LED#<34,43>
I
W
B_PWR_SHR_VBU S_EN<36>
S
U
L
AN_RADIO_DIS#<34>
W
I
RELESS_ON#/OFF<30>
W
_RADIO_DIS#<41>
T
B
W
AN_RADIO_DIS#<34>
W
S_PWROK<7,16>
Y
S
T
T
1
1
14 PAD~D@
14 PAD~D@
U_VTT_ON<49>
P
C
C
H_DPWROK<16>
P
7
7
R
R
97 0_0402_5%~D@
97 0_0402_5%~D@
1 2
0
UMA 1
A A
ME_FWP PCH has internal 20K PD.
(suspend power rail)
M
_FWP
E
12
R
R
93
@
7
7
93
@
1K_0402_5%~D
1K_0402_5%~D
5
4
C
R
T_SWITCH
M
C_RST_DIS#
D
M
ARD_MISC_PWRE N
C
P
OCHOT_GATE
R
L
I
D_CL_SIO#
CK_SMB_ALERT#
O
D
U
S
B_SIDE_EN#
E
_I2S_NB_CODEC#
N
U
H_PWR_STATE#
S
E
_DOCK_PWR_BAR
N
P
ANEL_BKEN_EC
E
VDD_PCH
N
L
C
D_TST
P
S
ID_DISABLE#
P
AT_PRES#
B
D
CKED
O
D
CK_DET#
O
A
UD_NB_MUTE#
M
ARD_WWA N_PWREN
C
L
C
D_VCC_TEST_EN
C
D_OFF
C
A
D_HP_NB_SENSE
U
E
SATA_USB_PWR_E N#
M
O
DULE_ON
S
ICE_BAT_ON
L
S
ICE_BAT_PRES#
L
M
DULE_BATT_PRES#
O
C
ARGE_MODULE_BATT
H
C
ARGE_PBATT
H
D
E
FAULT_OVRDE
U
S
B_PWR_SHR_EN#
G
F
X_MEM_VTT_ON
M
ARD_PCIE_SATA#
C
C
P
U_DETECT#
D
PU_PWR_EN
G
M
O
D_SATA_PCIE#_DET
D
_HDMI_HPD
P
Z
O
DD_WAKE#
B
C
M5882_ALERT#
E
ID_SELECT#
D
D
PU_PWROK
G
V
A_ID
G
3
.
3V_RUN_GFX_ON
S
L
P_ME_CSW_DEV#
L
N_DISABLE#_R
A
C
ARGE_EN
H
S
Y
S_LED_MASK#
D
Y
N_TURB_PWR_ALR T#
W
RELESS_LED#
I
U
B_PWR_SHR_VBU S_EN
S
W
AN_RADIO_DIS#
L
W
RELESS_ON#/OFF
I
B
_RADIO_DIS#
T
W
WAN_RADIO_DIS#
S
Y
S_PWROK
D
G
PU_SELECT#
C
U_VTT_ON
P
1 2
R802 0_0402_5%~D@
02 0_0402_5%~D@
R8
4
B52
A49
B53
A50
B54
A51
B55
A52
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
B32
A31
B33
B15
A15
B16
A16
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
U
U
4
4
6
6
G
P
IOA0
G
P
IOA1
G
P
IOA2
G
P
IOA3
G
IOA4
P
G
IOA5
P
G
IOA6
P
G
IOA7
P
G
IOB0
P
G
P
IOB1
G
P
OC2
G
OC3
P
G
OC4
P
G
P
OC5
G
P
OC6/TACH4
G
IOC7
P
G
IOD0
P
G
P
IOC1
G
IOC0
P
G
IOB7
P
G
IOB6
P
G
P
IOB5
G
P
IOB4
G
IOB3
P
G
P
IOB2
G
PIOD1
G
P
IOD2
G
P
IOD3
G
IOD4
P
G
IOD5
P
G
IOD6
P
G
P
IOD7
G
P
IOE0/RXD
G
IOE1/TXD
P
G
IOE2/RTS#
P
G
P
IOE3/DSR#
G
IOE4/CTS#
P
G
IOE5/DTR#
P
G
P
IOE6/RI#
G
IOE7/DCD#
P
G
IOF0
P
G
IOF1
P
G
IOF2
P
G
IOF3/TACH8
P
G
IOF4/TACH7
P
G
P
IOF5
G
P
IOF6
G
IOF7
P
G
P
IOG0/TACH5
IOG1
P
G
P
IOG2
G
P
IOG3
G
P
IOG4
G
P
IOG5
G
IOG6
P
G
P
IOG7/TACH6
G
G
IOH0
P
G
IOH1
P
S
SOPT1/GPIOH2
Y
S
SOPT0/GPIOH3
Y
G
IOH4
P
G
IOH5
P
G
IOH6
P
G
IOH7
P
.3V_ALW
3
+
1
2
B5
A17
B30
A43
A54
C1
C1
C1
C1
C1
C
C
C
C
C
V
V
V
V
V
1
4.318MHZ/GPIOM0
ECE5048-LZY_DQFN132_11X11~D
ECE5048-LZY_DQFN132_11X11~D
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
P
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
T
E
B
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
N
A
P
3
1
2
DC_EN
CK_HP_DET
CK_MIC_DET
_FWP
SK_SATA_LED#
N_ON
S_ON
H_PWR_ON
_GPS_DISABLE2#
EATH_LED#
H_PLTRST#_EC
_INT#_ECE5048
_CLK_ECE5048
NPWROK
2
1
8
8
04 1K_0402_5%~D
04 1K_0402_5%~D
1
C
C
7
7
14
14
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
C7
C7
07
07
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
O_SLP_A# <16,42,48>
I
S
.
75V_DDR_VTT_ON <46>
0
O_SLP_S4# <16,42,46>
I
S
I
O_SLP_S3# <11,16,27,35,42,47>
S
VP_PWRGD < 51>
M
I
M
VP_VR_ON <51>
I
D
CK_AC_OFF_EC
O
X_EN_WOWL <35>
U
A
AN_LAN_DISB# <31>
L
W
O_SLP_LAN# <16,31>
I
S
O_SLP_SUS# <16>
I
S
IO_PSID_SELECT <44>
P
G
O
DC_EN <28>
M
O
CK_HP_DET <29>
D
O
CK_MIC_DET <29>
D
E
_FWP <14>
M
SK_SATA_LED# <43>
A
M
.
8V_RUN_PWRGD <47>
1
D_SATA_DIAG_OUT# <43>
E
L
N_ON <27,35,42,47>
U
R
I_WP#_SEL <14>
P
S
S_ON <42 >
U
S
T1_LED# <43>
A
B
T2_LED# <43>
A
B
T
T
1
1
W
_GPS_DISABLE2# <34>
H
R
EATH_LED# <38,43>
B
C_LAD0 <14,32,34,40>
P
L
P
C_LAD1 <14,32,34,40>
L
P
C_LAD2 <14,32,34,40>
L
P
C_LAD3 <14,32,34,40>
L
P
C_LFRAME# <14,32,34,40>
L
C
H_PLTRST#_EC <17,32,34,35,40>
P
K_PCI_5048 <17 >
L
C
KRUN# <16,32,40>
L
C
C_LDRQ1# <1 4>
P
L
Q_SERIRQ <14,32,40>
R
I
K_SIO_14M <15>
L
C
_32KHZ_ECE5048 <40>
C
E
_
LAD0 <38>
D
_LAD1 <38>
D
_
LAD2 <38>
D
LAD3 <38>
_
D
_
LFRAME# <38>
D
_
CLKRUN# <38>
D
DLDRQ1# <38>
_
D
SERIRQ <38>
_
D
_INT#_ECE5048 <40>
C
B
_DAT_ECE5048 <40>
C
B
C
_CLK_ECE5048 <40>
B
NPWROK <7,40>
U
R
_TPM_LPC_EN <32>
P
S
CAP_LDO trace width 20 mils
+
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
P
P
P
P
P
P
P
IOJ0
P
P
IOJ3
P
IOJ4
P
IOJ5
P
IOJ6
P
IOJ7
P
IOK0
IOK2
P
IOK3
P
P
IOK4
P
IOK5
P
IOK6
P
IOK7
IOL6
P
P
IOM1
L
L
L
L
ESET#
ICLK
C
RQ1#
R_IRQ
D
L
D
LAD1
D
L
D
L
_INT#
_DAT
C
_CLK
RGD
W
O
U
V
IOI0
IOI1
IOI3
IOI4
IOI5
IOI6
IOI7
A
A
A
A
AD0
AD2
AD3
T65
1
C
C
7
7
06
06
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
A23
S
I
O_SLP_A#
B63
0
.75V_DDR_VTT_ON
A60
A61
B65
A62
1 2
B66
65 0_0402_5%~D@R765 0_0402_5%~D@
R7
A63
B67
A64
S
I
O_SLP_LAN#
A5
S
O_SLP_SUS#
I
B6
A6
M
O
B7
D
O
A7
D
O
B8
M
E
A8
M
A
B9
B10
L
D_SATA_DIAG_OUT#
E
A10
T
E
MP_ALERT#_R
B11
R
U
A11
B12
A12
S
U
B60
A57
B
AT1_LED#
B64
B68
B
A
T2_LED#
A9
B1
U
S
A18
A44
H
W
B34
B
R
B39
B51
L
P
C_LAD0
A27
D0
D1
D2
D3
S
S
P
E
L
C_LAD1
P
A26
L
C_LAD2
P
B26
L
P
C_LAD3
B25
L
C_LFRAME#
P
A21
P
C
B22
C
L
K_PCI_5048
A28
C
KRUN#
L
B20
L
PC_LDRQ1#
A22
I
Q_SERIRQ
R
B21
C
L
K_SIO_14M
A32
B35
D
_
LAD0
B29
D
_
LAD1
B28
D
_
LAD2
A25
D
LAD3
_
A24
D
_LFRAME#
B23
D
CLKRUN#
_
A19
D
_
DLDRQ1#
B24
D
_SERIRQ
A20
B
C
A29
B
C_DAT_ECE5048
B31
B
C
A30
R
U
A4
S
_TPM_LPC_EN
P
B56
B19
R
R
+
C
AP_LDO
B46
B27
C1
C
C
7
05
05
7
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
G
G
IOI2/TACH0
P
G
G
G
G
G
G
G
IOJ1/TACH1
P
G
IOJ2/TACH2
P
G
G
G
G
G
G
G
IOK1/TACH3
P
G
G
G
G
G
G
G
G
IOL0/PWM7
P
G
IOL1/PWM8
P
G
IOL2/PWM0
P
IOL3/PWM1
P
G
IOL4/PWM3
P
G
IOL5/PWM2
P
G
G
P
IOL7/PWM5
G
G
G
IOM3/PWM4
P
G
IOM4/PWM6
P
L
RAME#
F
L
R
P
C
KRUN#
L
L
D
S
E
L
K32/GPIOM2
C
D
FRAME#
L
D
CLKRUN#
D
L
DRQ1#
D
ER_IRQ
S
B
C
B
C
B
P
T
ST_PIN
E
C
A
P_LDO
DB Version 0.4
DB Version 0.4
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
7
7
08
08
C
C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
race width 20 mils
t
trace width 20 mils
17PAD~D @
17PAD~D @
C
L
K_SIO_14M
@
7
7
@
R
R
10_0402_1%~D
10_0402_1%~D
712
@
12
@
7
C
C
2
AV_IN_NB <40,52,53>
C
A
CK_AC_OFF_EC <53>
O
D
1 2
R
R
7
7
38 0_0402 _5%~D@
38 0_0402 _5%~D@
12
94
94
1
33P_0402_50V8J~D
33P_0402_50V8J~D
2
2
1
2
C
3
3
C
C
7
7
09
09
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
T
E
MP_ALERT#
K_PCI_5048
L
R795@
R795@
_0402_5%~D
3
3
_0402_5%~D
13
@
7
7
13
@
C
C
1
1
C7
C7
10
10
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
3
.3V_ALW
+
7
7
11 0.1U_0402_25V6K~D@
11 0.1U_0402_25V6K~D@
C
C
1 2
5
1
P
B
2
A
12
1
2
2 1
4
O
D3
4
@D34
@
G
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
U4
U4
7
@
7
@
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
MP_ALERT# <14,18>
E
T
3
.3V_ALW
+
12
R
R
05
05
8
8
100K_0402_5%~D
100K_0402_5%~D
L
D_CL_SIO#
I
1
16
16
7
7
C
C
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
LL CONFIDENTIAL/PROPRIETARY
E
D
C
C
Title
itle
i
tle
T
T
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
E
E
E
O
CK_AC_OFF <38,53>
D
12
R
R
70
@
7
770
@
33K_0402_5%~D
33K_0402_5%~D
D
CLKRUN#
_
D
SERIRQ
_
D
DLDRQ1#
_
R
U
C
P
0
.
75V_DDR_VTT_ON
S
L
ICE_BAT_ON
S
U
07 10_040 2_1%~D
8
8
07 10_040 2_1%~D
R
R
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
E5048
C
C
E5048
E5048
C
-7781
A
A
A
-7781
-7781
L
L
L
N_ON
U_VTT_ON
S_ON
R
R
77 100K_040 2_5%~D
77 100K_040 2_5%~D
7
7
80 100K_040 2_5%~D
80 100K_040 2_5%~D
R7
R7
R
R
7
7
82 100K_040 2_5%~D
82 100K_040 2_5%~D
2
7
7
86 100K_040 2_5%~D
86 100K_040 2_5%~D
R
R
R
R
7
7
89 100K_040 2_5%~D
89 100K_040 2_5%~D
2
R
R
7
7
90 100K_040 2_5%~D
90 100K_040 2_5%~D
R
R
91 100K_040 2_5%~D
7
7
91 100K_040 2_5%~D
R
R
78 100K_040 2_5%~D
8
8
78 100K_040 2_5%~D
12
1
3
.3V_RUN
+
12
12
12
1
12
1
12
12
D_CL# <30,43>
I
L
9 6
9 6
9 6
3
3
3
f
f
f
o
o
o
0
.
.
.
0
0
1
1
1
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+3
.3V_ALW
20
20
7
7
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
5
0
0
5
5
U
1
APWROK<50>
dify name net
1 2
R7
R7
59 10K_0402_5%~D
59 10K_0402_5%~D
12
R
R
21 100K_0402_5%~D
21 100K_0402_5%~D
8
8
1 2
R
R
8
8
14 100K_0402_5%~D
14 100K_0402_5%~D
1 2
17 100K_0402_5%~D
17 100K_0402_5%~D
8
8
R
R
1 2
8
8
18 2.2K_0402_5%~D
18 2.2K_0402_5%~D
R
R
1
2
R
R
20 2.2K_0402_5%~D
20 2.2K_0402_5%~D
8
8
1 2
R8
23 100K_0402_5%~D@R823 100K_0402_5%~D@
1 2
R
R
27 2.2K_0402_5%~D
8
827 2.2K_0402_5%~D
1 2
8
8
28 2.2K_0402_5%~D
28 2.2K_0402_5%~D
R
R
1 2
8
8
29 2.2K_0402_5%~D
29 2.2K_0402_5%~D
R
R
1 2
8
8
22 2.2K_0402_5%~D
22 2.2K_0402_5%~D
R
R
.3V_ALW
3
+
10K_0402_5%~D
10K_0402_5%~D
12
R8
R8
24
24
100_0402_1%~D
100_0402_1%~D
12
@
@
R
R
8
8
36
36
7
7
41
41
C
C
2
1
22P_0402_50V8J~D
22P_0402_50V8J~D
2
1
7
7
43
43
C
C
1 2
22P_0402_50V8J~D
22P_0402_50V8J~D
CONN@
CONN@
J
J
G2
DE
DE
G2
1
2
2
3
4
4
5
6
6
7
8
8
9
1
0
10
1
1
G
1
1
2
G
2
3
1
G
3
4
1
G
4
ACES_87153-10411
ACES_87153-10411
12
8
8
85
@
85
@
R
R
1
7
7
47
@
47
@
C
C
2
.05V_VTTPWRGD
V
CCS
APWROK
P
CIE_WAKE#
C_
DAT_EMC4022
B
B
C_
DAT_ECE5048
B
C_
DAT_ECE1117
P
AT_SMBDAT
B
P
AT_SMBCLK
B
C_LDRQ#_MEC
P
L
C
HA
RGER_SMBDAT
C
HA
RGER_SMBCLK
P
U_SMBDAT
G
U_SMBCLK
P
G
J
TAG_RST# citcui t
close to U51.B5 7
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
Y
Y
6
6
3
3
2.768KHZ_12.5PF_Q13FC1350000~D
2.768KHZ_12.5PF_Q13FC1350000~D
.3V_ALW
3
+
49.9_0402_1%~D
49.9_0402_1%~D
12
R
R
8
8
64
64
1
2
3
4
5
M
CLK
S
6
M
DATA
S
7
H
O
ST_DEB_TX
8
H
OST_DEB_RX
9
10
.
05V_VTTPWRGD<49,50>
1
CCS
V
Mo
.3V_ALW
3
+
D D
EC firmware can configure those un-used SMBUS pins as GPO (Output),
then it's OK to leave these un-used pins No-Connect.
C C
J
AG_RST#
T
3
2 KHz Clock
M
E
C_XTAL2
M
C_XTAL1
E
B B
A A
P
l
ace closely pin A29
C
K_PCI_MEC
L
10_0402_5%~D
10_0402_5%~D
8.2P_0402_50V8D~D
8.2P_0402_50V8D~D
U
1
P
B
2
A
G
3
1
C
C
1
7
7
35
35
2
2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
12
R
R
R
R
R
R
8
8
8
8
8
8
58
58
60
60
59
59
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
@SHORT PADS~D
@SHORT PADS~D
J
J
T
T
AG1
AG1
CONN@
CONN@
10K_0402_5%~D
10K_0402_5%~D
12
R
R
8
8
61
61
J
T
AG_TDI
J
AG_TMS
T
J
TAG_CLK
J
T
AG_TDO
53 0_0402_5%~D@
8
8
53 0_0402_5%~D@
R
R
55 0_0402_5%~D@
8
8
55 0_0402_5%~D@
R
R
1
.
05V_0.8V_PWROK
36 0.1U_0402_25V6K~ D
36 0.1U_0402_25V6K~ D
7
7
C
C
CK_POR_RST#<38>
DO
C_
32KHZ_ECE5048<39>
E
3
.3V_ALW
+
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
R8
R8
R
R
8
8
48
48
47
47
1 2
1 2
12
10K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
10K_0402_5%~D
12
12
R
R
8
8
49
49
*
.
05V_0.8V_PWROK <14,51>
1
M
L1_SMBDATA<15>
S
M
L1_SMBCLK<15>
S
L
K_TP_SIO<41>
C
A
T_TP_SIO<41>
D
K_KBD<38>
L
C
A
T_KBD<38>
D
K_MSE<38>
L
C
T_MSE<38>
A
D
BAT_SMBDAT<44>
P
B
AT_SMBCLK<44>
P
CK_POR_RST#
O
D
CH_
P
I
A_PWM_EC<24>
B
CLK_ECE5048< 39>
C_
B
DAT_ECE5048<39>
C_
B
C_
INT#_ECE5048<39>
B
CLK_EMC4022<22>
C_
B
C_
DAT_EMC4022<22>
B
INT#_EMC4022<22>
C_
B
CH_
PCIE_WAKE#<16>
P
CI
P
C_
CLK_ECE1117< 41>
B
C_
DAT_ECE1117<41>
B
C_
INT#_ECE1117<41>
B
O_SLP_S5#<16>
SI
CA
A
S
I
O_RCIN#<18>
S
_SERIRQ<14,32,39>
RQ
I
CH_
PLTRST#_EC<17,32,34,35,39>
P
K_PCI_MEC<17>
L
C
C_LFRAME#<14,32,34,39>
P
L
P
C_LAD0< 14,32,34,39>
L
C_LAD1< 14,32,34,39>
P
L
C_LAD2< 14,32,34,39>
P
L
C_LAD3< 14,32,34,39>
P
L
L
KRUN#<16,32,39>
C
I
O_EXT_SCI#<18>
S
E
C_XTAL2
M
068 0_0402_5%~D@
1
1
068 0_0402_5%~D@
R
R
1 2
8
8
67 0_0402_5%~D@
67 0_0402_5%~D@
R
R
@
@
R
R
8
8
50
50
H
O
ST_DEBUG_TX
H
ST_DEBUG_RX
O
R
875 C744
2
0K 4700p
4
1
30K 4700p
62K
4700p
33K
4700p
8.2K
4700p
4.3K
4700p
2K
4700p
1
K
4700p
B
O_EXT_SMI#<14,17>
I
BOARD_ID rise time is measured from 5%~68%.
5
4
3
.3V_ALW
C_CELL_VBAT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
S
B66
Y
C
C
7
7
23
23
ND
G
A
STEM_ID
B64
+
AT
B
V
A11
A22
R[1]
R[2]
T
T
V
V
D
D
B
B
Version 0.12
Version 0.12
S[4]
S[1]
S
S
V
V
B60
B11
l
east
15mil
3
.3V_ALW
+
12
1
2
B35
A41
R[3]
R[4]
T
T
V
V
R
R
1K_0402_5%~D
1K_0402_5%~D
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C
C
7
7
42
42
A58
A52
B3
A26
R[5]
R[6]
R[7]
R[8]
T
T
T
T
V
V
V
V
P
G
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
G
P
IO040/GPTP-OUT3/HSPI_CS2
G
SMBUS INTERFACE
SMBUS INTERFACE
G
P
IO012/I2C1H_DATA/I2C2D_DATA
G
P
IO013/I2C1H_CLK/I2C2D_CLK
G
P
IO141/I2C1F_DATA/I2C2B_DATA
G
P
IO142/I2C1F_CLK/I2C2B_CLK
DELL PWR SW INF
DELL PWR SW INF
_CAP
S_RO
R
S
V
V
B12
B54
R_CAP
V
+
1
C
C
7
7
40
40
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
71
71
8
8
C
function
R8
RT
15
@R815
@
C_CELL
+
0_0402_5%~D
0_0402_5%~D
RT
+
1 2
U
U
5
5
1
1
P
P
/2 INTERFACE
/2 INTERFACE
S
S
M
L1_SMBDATA
S
M
L1_SMBCLK
C
K_TP_SIO
L
D
T_TP_SIO
A
C
K_KBD
L
D
AT_KBD
C
L
K_MSE
D
A
T_MSE
P
AT_SMBDAT
B
P
AT_SMBCLK
B
J
AG_TDI
T
J
T
AG_TDO
J
T
AG_CLK
J
T
AG_TMS
J
T
AG_RST#
P
CH_
ALW_ON<42,44>
E_WAKE#<28,34,35>
E
EP<29>
V_IN_NB<39,52 ,53>
ALW_ON
B
A_PWM_EC
I
B
CLK_ECE5048
C_
B
DAT_ECE5048
C_
B
INT#_ECE5048
C_
C_
CLK_EMC4022
B
C_
DAT_EMC4022
B
C_
INT#_EMC4022
B
CH_PCIE_WAKE#
P
E_WAKE#
CI
P
B
C_
CLK_ECE1117
B
C_
DAT_ECE1117
B
INT#_ECE1117
C_
EP
E
B
I
O_SLP_S5#
S
V_IN_NB
CA
A
S
I
O_EXT_SMI#
S
O_RCIN#
I
C_LDRQ#_MEC
P
L
I
RQ
_SERIRQ
P
CH_
PLTRST#_EC
C
L
K_PCI_MEC
L
P
C_LFRAME#
L
C_LAD0
P
L
PC_LAD1
L
P
C_LAD2
L
C_LAD3
P
C
KRUN#
L
S
O_EXT_SCI#
I
C_XTAL1
E
M
E
C_XTAL2_R
M
12
S
A5
G
PIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
G
P
IO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
A37
G
P
IO110/PS2_CLK2/GPTP-IN6
B40
G
P
IO111/PS2_DAT2/GPTP-OUT6
A38
G
IO112/PS2_CLK1A
P
B41
G
IO113/PS2_DAT1A
P
A39
G
IO114/PS2_CLK0A
P
B42
G
IO115/PS2_DAT0A
P
B59
G
PIO154/I2C1C_DATA/PS2_CLK1B
A56
G
P
IO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
JTAG INTERFACE
A51
G
IO145/I2C1K_DATA/JTAG_TDI
P
B55
G
IO146/I2C1K_CLK/JTAG_TDO
P
B56
G
IO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
P
A53
G
P
IO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
B57
J
T
AG_RST#
FAN PWM & TACH
FAN PWM & TACH
B22
G
IO050/FAN_TACH1
P
A21
G
IO051/FAN_TACH2
P
B23
G
IO052/FAN_TACH3
P
B24
G
P
IO053/PWM0
A23
G
P
IO054/PWM1
B25
G
P
IO055/PWM2
A24
G
IO056/PWM3
P
BC-LINK
BC-LINK
A43
G
IO123/BCM_A_CLK
P
B45
G
P
IO122/BCM_A_DAT
A42
G
P
IO121/BCM_A_INT#
A12
G
IO022/BCM_B_CLK
P
B13
G
P
IO023/BCM_B_DAT
A13
G
P
IO024/BCM_B_INT#
B20
G
IO044/BCM_C_CLK
P
A18
G
P
IO043/BCM_C_DAT
B19
G
IO042/BCM_C_INT#
P
A20
G
IO047/LSBCM_D_CLK
P
B21
G
IO046/LSBCM_D_DAT
P
A19
G
IO045/LSBCM_D_INT#
P
A16
P
IO032/GPTP-IN3/BCM_E_CLK
G
B16
IO31/GPTP-OUT2/BCM_E_DAT
P
G
A15
IO30/GPTP-IN2/BCM_E_INT#
P
G
HOST INTERFACE
HOST INTERFACE
A6
P
IO011/nSMI
G
A27
P
IO061/LPCPD#
G
B29
D
RQ#
L
A28
E
R_IRQ
S
B30
R
ESET#
L
A29
I_CLK
C
P
B31
F
RAME#
L
A30
D0
A
L
B32
A
D1
L
A31
A
D2
L
B33
D3
A
L
A32
KRUN#
L
C
A33
P
IO100/nEC_SCI
G
MASTER CLOCK
MASTER CLOCK
A61
X
AL1
T
A62
X
AL2
T
B62
G
IO160/32KHZ_OUT
P
B34
C
1
N
A64
2
C
N
B68
3
C
N
15mil
C
39 close to U51.B12
7
3
.3V_ALW
R
X00
X
X
A
EV
1
0
0
2
0
0
+
12
75
8
8
75
R
R
33K_0402_5%~D
33K_0402_5%~D
B
ARD_ID
O
1
C
C
44
7
7
44
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
4
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
1
C
C
C
C
7
7
7
7
25
25
27
27
2
2
2
MISC INTERFACE
MISC INTERFACE
G
IO021/RC_ID1
P
IO020/RC_ID2
P
G
G
P
IO025/UART_CLK
IO120/UART_TX
P
G
IO124/GPTP-OUT5/UART_RX
V
C_PRWGD
C
G
IO060/KBRST
P
G
IO101/ECGP_SCLK
P
G
IO103/ECGP_MISO
P
G
P
IO105/ECGP_MOSI
G
P
IO102/HSPI_SCLK
G
IO104/HSPI_MISO
P
G
IO106/HSPI_MOSI
P
G
P
IO116/MSDATA
G
IO117/MSCLK
P
G
P
IO127/A20M
G
P
IO153/LED3
G
IO156/LED1
P
G
IO157/LED2
P
n
OCHOT#/PWM4
R
P
IO001/ECSPI_CS1
P
G
P
IO002/ECSPI_CS2
G
P
IO014/GPTP-IN7/HSPI_CS1
P
IO015/GPTP-OUT7
G
P
IO016/GPTP-IN8
G
IO017/GPTP-OUT8
P
G
P
IO026/GPTP-IN1
G
IO027/GPTP-OUT1
P
G
P
IO041
G
IO107/nRESET_OUT
P
G
P
IO125/GPTP-IN5
G
P
IO126
G
P
IO151/GPTP-IN4
G
IO152/GPTP-OUT4
P
G
G
PIO003/I2C1A_DATA
G
IO004/I2C1A_CLK
P
G
IO005/I2C1B_DATA
P
G
P
IO006/I2C1B_CLK
G
IO130/I2C2A_DATA
P
G
IO131/I2C2A_CLK
P
G
P
IO132/I2C1G_DATA
G
P
IO140/I2C1G_CLK
G
P
IO143/I2C1E_DATA
G
IO144/I2C1E_CLK
P
B
G
V
C
I_IN2#
V
C
I_OUT
V
C
I_IN1#
I_IN0#
C
V
I_OVRD_IN
C
V
I_IN3#
C
V
PECI
PECI
E
CI_VREF
P
P
I2S
I2S
2
S_DAT
I
I
2
S_CLK
I
S_WS
2
P
E
MEC5055-LZY_DQFN132_11X11~D
MEC5055-LZY_DQFN132_11X11~D
1
C
R
SET_OUT#
E
IPSET_ID for BID
H
3
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
C
C
7
7
29
29
WP
F
PO0
E
CI
3
+
2
G
G
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
7
7
7
7
26
26
31
31
2
2
S
Y
STEM_ID
A10
B
ARD_ID
O
B10
DR_
D
B14
H
O
ST_DEBUG_TX
B44
H
O
ST_DEBUG_RX
B46
R
UNP
B26
INVPWR
N_
E
A25
B36
B37
B38
D
DR_
A34
D
N_TUR_CURRNT_SET#
Y
A35
C
U1.5V_S3_GATE
P
A36
M
DATA
S
A40
M
CLK
S
B43
S
I
O_A20GATE
A45
P
_ID
S
A55
A57
B61
F
W
P#
B65
P
RO
A46
B2
A2
B8
B18
M
_SUS_PWR_ACK
E
A8
1
.
5V_SUS_PWRGD
B9
_APWROK
M
P
A9
05V_A_PWRGD
.
1
A14
W_PWRGD_3V _5V
L
A
B15
VICE_DET#
E
D
A17
R
SET_OUT#
E
B39
A44
P
CH_
B47
A
PRESENT
C_
A54
S
O_PWRBTN#
I
B58
D
CK_SMB_DAT
O
A3
D
CK_SMB_CLK
O
B4
L
CD_
A4
L
CD_SMBCLK
B5
B
Y_SMBDAT
A
B7
B
Y_SMBCLK
A
A7
U_SMBDAT
P
G
B48
U_SMBCLK
P
G
B49
C
HA
A47
C
HA
B50
C
RD_SMBDAT
A
B52
C
A
RD_SMBCLK
A49
U
S
H_SMBDAT
B53
U
S
H_SMBCLK
A50
A59
L
T_ON_SW#
A
B63
A
WON
L
A60
CI
_IN1#
V
A63
P
WER_SW _IN#
O
B67
CA
A
B1
CK_PWR_SW #
O
D
A1
+
P
ECI_VREF
B51
CI_EC_R
E
P
A48
B17
656 100K_0402_5%~D
1
1
656 100K_0402_5%~D
R
R
B27
1
1
657 100K_0402_5%~D
657 100K_0402_5%~D
R
R
B28
.3V_M
12
R
R
93
8
8
93
100K_0402_5%~D
100K_0402_5%~D
CH_
P
13
D
D
0
5
5
0
Q
Q
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
C
C
7
7
28
28
2
ON
WROK
HVREF_RST_GATE
CHOT#_EC
RSMRST#
SMBDAT
RGER_SMBDAT
RGER_SMBCLK
V_IN
1 2
1 2
PWRGD# <22>
1
2
R
R8
8
8
8
R
R
R
R
8
8
R
R
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
C
C
C
C
C
C
7
7
7
7
7
7
32
32
39
39
30
30
2
2
DR_
ON <46>
D
O
ST_DEBUG_TX <34>
H
O
ST_DEBUG_RX < 34>
H
UNP
WROK <7,39>
R
INVPWR <24>
EN_
CH_
SATA_MOD_EN# <14>
P
HVREF_RST_GATE <7>
DR_
D
N_TUR_CURRNT_SET# <52>
Y
D
U1.5V_S3_GATE <11>
P
C
DATA <34>
S
M
S
CLK <34>
M
O_A20GATE <18>
I
S
S
_ID <44>
P
84 1K_0402_5%~D
84 1K_0402_5%~D
1 2
86 1K_0402_5%~D
86 1K_0402_5%~D
1 2
87 1K_0402_5%~D
87 1K_0402_5%~D
1 2
_SUS_PWR_ACK <16>
E
M
.
5V_SUS_PWRGD <46>
1
M
_APWROK <16>
P
05V_A_PWRGD <48>
.
1
W_PWRGD_3V _5V <45>
L
A
VICE_DET# <28>
DE
ESET_OUT# <16>
R
CH_
RSMRST# <41 >
P
PRESENT <16>
C_
A
O_PWRBTN# <16>
I
S
CK_SMB_DAT <38>
O
D
CK_SMB_CLK <38>
O
D
Y_SMBDAT <28,44>
A
B
AY_SMBCLK <28,44>
B
HA
RGER_SMBDAT <52>
C
RGER_SMBCLK <52>
HA
C
RD_SMBDAT <35>
A
C
A
RD_SMBCLK <35>
C
S
H_SMBDAT <32>
U
S
H_SMBCLK <32>
U
L
WON <45>
A
V_IN <22,52,53>
CA
A
1 2
63 43_0402_5%~D
8
8
63 43_0402_5%~D
3
.3V_ALW
+
F
WP#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
ARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
V
OL_MUTE
O
L_MUTE <30>
V
O
L_UP
V
O
V
GPIO024/THSEL_STRAP note
i.
THSEL_STRAP =1 (selects thermistor on diode channel 1)
ii.
THSEL_STRAP = 0 (selects remote diode on diode channel 1)
12
72
8
8
72
R
R
10K_0402_5%~D
10K_0402_5%~D
79
@
79
@
8
8
R
R
10K_0402_5%~D
10K_0402_5%~D
1 2
L_DOWN
E
P
A
CI_EC <7>
V
_IN1#
CI
VO
VO
L
WON
R
863 close to
U51& least 250mils
L_UP <30>
L_DOWN <30>
1
2
R
R
8
8
1
C
C
2
1 2
69 10K_0402_5%~D
8
8
69 10K_0402_5%~D
R
R
1 2
R
R
76 100K_0402_5%~D
8
8
76 100K_0402_5%~D
1 2
R
R
80 100K_0402_5%~D
8
8
80 100K_0402_5%~D
1 2
81 100K_0402_5%~D
81 100K_0402_5%~D
8
8
R
R
1 2
82 100K_0402_5%~D
8
8
82 100K_0402_5%~D
R
R
1
R
R
83 10K_0402_5%~D
83 10K_0402_5%~D
8
8
1 2
43 8.2K_0402_5%~D@
43 8.2K_0402_5%~D@
8
8
R
R
1 2
R
R
8
8
89 100K_0402_5%~D
89 100K_0402_5%~D
1 2
92 10K_0402_5%~D
8
8
92 10K_0402_5%~D
R
R
2
208
208
1
1
C
C
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
.05V_RUN_VTT
1
+
1 2
62 0_0402_5%~D@
62 0_0402_5%~D@
7
7
37
37
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
R
R
1
1
156 100K_0402_5%~D
156 100K_0402_5%~D
M
S
DATA
D
DR_
P
CH_
D
CK_POR_RST#
O
E
N_
INVPWR
1
05V_0.8V_PWROK
.
2
R
E
SET_OUT#
C
P
U1.5V_S3_GATE
RSMRST#
CH_
P
+
ON
ALW_ON
1
C_CELL
+RT
12
R
R
10
10
8
8
100K_0402_5%~D
100K_0402_5%~D
P
WER_SW _IN#
1 2
1
1
179 10K_0402_5 %~D@
179 10K_0402_5 %~D@
CHOT#_EC
1 2
12 100K_0402_5%~D@
12 100K_0402_5%~D@
8
8
D
L
A
T_ON_SW#
O
CK_PWR_SW #
O
D
Y
O
WER_SW _IN#< 22>
P
O
CK_PWR_SW #<2 2>
D
1
.05V_RUN_VTT
+
R
R
P
RO
R
R
RT
C_CELL
1 2
R
R
8
8
11 10K_0402_5%~D
11 10K_0402_5%~D
1
7
7
22
22
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
C_CELL
RT
+
12
19
19
8
8
R
R
100K_0402_5%~D
100K_0402_5%~D
1 2
R8
R8
25 10K_0402_5%~D
25 10K_0402_5%~D
1
7
7
34
34
C
C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
RT
C_CELL
+
12
8
8
70
70
R
R
100K_0402_5%~D
100K_0402_5%~D
1
D
D
@
@
2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
G
G
S
S
3
1 2
R
R
180 0_0402_5%~D@
180 0_0402_5%~D@
1
1
R
WROK
UNP
ON_ENABLE#<42>
UN_
R
A
C_
PRESENT
L
CD_
SMBCLK
L
CD_
SMBDAT
D
CK_SMB_DAT
O
D
O
CK_SMB_CLK
B
A
Y_SMBDAT
B
A
Y_SMBCLK
N_TUR_CURRNT_SET#
D
E
VICE_DET#
C
L
K_KBD
D
A
T_KBD
C
K_MSE
L
D
AT_MSE
V
L_MUTE
O
2
1
1
169 100K_0402_5%~D@
169 100K_0402_5%~D@
R
R
V
OL_DOWN
R
R
197 100K_0402_5%~D@
197 100K_0402_5%~D@
1
1
V
O
L_UP
2
R
R
1
1
118 100K_0402_5%~D@
118 100K_0402_5%~D@
D
E
LL CONFIDENTIAL/PROPRIETARY
Title
Title
T
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet o
Date: Sheet
21
@C721
@
C7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2
O
WER_SW #_MB <30,41>
P
C7
33
@C733
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CK_PWR_BTN# <38>
O
D
_
PROCHOT# < 7,51,52>
H
Q
Q
7
4
4
7
.3V_RUN
3
+
12
R
R
99
7
7
99
10K_0402_5%~D
10K_0402_5%~D
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
2
Q
Q
4
4
G
G
5
5
S
S
.3V_ALW_PCH
3
+
12
35 10K_0402_5%~D
8
8
35 10K_0402_5%~D
R
R
18 2.2K_0402_5%~D
18 2.2K_0402_5%~D
4
4
R
R
4
4
20 2.2K_0402_5%~D
20 2.2K_0402_5%~D
R
R
R
R
38 2.2K_0402_5%~D
38 2.2K_0402_5%~D
8
8
R
R
41 2.2K_0402_5%~D
41 2.2K_0402_5%~D
8
8
54 2.2K_0402_5%~D
R8
R8
54 2.2K_0402_5%~D
56 2.2K_0402_5%~D
56 2.2K_0402_5%~D
8
8
R
R
1171 100K_0402 _5%~D
1171 100K_0402 _5%~D
R
R
R
R
125 100K_0402_ 5%~D
125 100K_0402_ 5%~D
1
1
R
R
8
8
45 4.7K_0402_5%~D
45 4.7K_0402_5%~D
8
8
46 4.7K_0402_5%~D
46 4.7K_0402_5%~D
R
R
R
R
8
8
51 4.7K_0402_5%~D
51 4.7K_0402_5%~D
52 4.7K_0402_5%~D
52 4.7K_0402_5%~D
8
8
R
R
1
12
1
C
C
mpal Electronics, Inc.
o
o
Compal Electronics, Inc.
mpal Electronics, Inc.
M
M
C5055
E
E
MEC5055
C5055
L
A
LA-7781
L
-7781
-7781
A
1
.3V_ALW
3
+
12
12
12
12
12
12
12
12
V_RUN
5
+
12
12
12
12
3
.3V_RUN
+
4
4
0 6
0 6
40 6
1
1
0
.
.
1.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
of
o
f
f
5
.3V_TP
+3
1
C7
C7
55
55
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
D D
TP
T
P
_CLK
_DATA
2
3
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
D
D
3
3
7
7
D
T_TP_SIO<40>
A
C
L
1
K_TP_SIO<40>
Place close to JTP1
RSMRST circuit
C C
+
3
+
5
V_ALW_PCH
12
629
629
1
1
R
R
33_0402_5%~D
33_0402_5%~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
C
C
2
2
89
89
2
4
4
U
U
1
C
C
V
E
SET#
R
2
ND
G
T9818A-44GU3_SC70-3~D
R
R
T9818A-44GU3_SC70-3~D
.3V_ALW_PCH
R
R
622
622
1
1
100K_0402_5%~D
100K_0402_5%~D
1 2
R
MRST#
S
3
P
1
C
C
14
14
E
E
100P_0402_50V8J~D
100P_0402_50V8J~D
2
4
.3V_TP
+3
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
12
1
Touch Pad
R
R
R
R
9
9
9
9
02
02
03
03
2
L5
L5
4 BLM18AG601SN1D_0603~D
4 BLM18AG601SN1D_0603~D
2
5
5
5 BLM18AG601SN1D_0603~D
5 BLM18AG601SN1D_0603~D
L
L
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
C
C
1
1
7
7
C
C
52
52
7
7
51
2
0_0402_5%~D
0_0402_5%~D
51
1
1
@
@
R
R
1 2
2
E
C SIDE
P
C
H_RSMRST#<40>
C
H_RSMRST#
1
12
C
C
7
7
50
50
+
3
.3V_ALW
623
623
P
C
H_RSMRST#_Q
1
B
2
A
3
Touch Pad Conn. Pitch=0.5mm
_DATA
TP
T
P_CLK
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1
1
C
C
7
7
49
49
2
2
1 2
88 0.1U_0402_25V6K ~D
88 0.1U_0402_25V6K ~D
2
2
C
C
5
3
U
U
7
7
0_0402_5%~D
0_0402_5%~D
P
4
O
G
T
C7SH08FU_SSOP5~D
C7SH08FU_SSOP5~D
T
@
@
1
1
R
R
1 2
P
in reverse for PT
T
P
_CLK
T
P
_DATA
+
.3V_TP
3
655
655
P
2_DAT_TS
S
P
S
2_CLK_TS
+
.3V_ALW
3
P
H_RSMRST#_Q <14,16>
C
+
.3V_RUN
3
1 2
R
R
1
1
161 0_0603_ 5%~D@
161 0_0603_ 5%~D@
1 2
1
1
162 0_0603_5%~D@
162 0_0603_5%~D@
R
R
P1
P1
T
T
J
J
1
1
2
2
3
3
4
4
5
5
6
1
6
G
7
2
7
G
8
8
TYCO_2041070-8
TYCO_2041070-8
CONN@
CONN@
2
BlueTooth
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
2
B
T
_DET#<17>
C
O
EX1_BT_ACTIVE<34>
B
_COEX_STATUS2<32>
9
1
0
+
.3V_TP
3
T
B
T
_PRI_STATUS<32>
B
T_ACTIVE<43 >
B
T
_RADIO_DIS#<39>
C
O
EX2_WLAN_ACTIVE<34>
U
BP11-<17>
S
U
BP11+<17>
S
+
.3V_RUN
3
B
T
_COEX_STATUS2
BT
_PRI_STATUS
10K_0402_5%~D
10K_0402_5%~D
33P_0402_50V8J~D
33P_0402_50V8J~D
1
C
C7
R
R
1
9
9
7
04
04
53
53
2
2
1 2
1133 1K_ 0402_5%~D
1133 1K_ 0402_5%~D
R
R
1 2
134 1K_0 402_5%~D
134 1K_0 402_5%~D
1
1
R
R
C
C
7
7
48
48
1
2
.3V_RUN
+3
100P_0402_50V8J~D
100P_0402_50V8J~D
@
@
C
C
7
7
54
54
B
_COEX_STATUS2
T
B
_PRI_STATUS
T
1
CONN@
CONN@
J
J
B
B
T1
T1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1
0
0
1
1
1
1
1
2
1
2
1
3
1
1
G
1
4
2
G
E&T_3703-E12N-03R
E&T_3703-E12N-03R
Power Switch for debug
2
P
O
WER_SW#_M B<30,40>
100P_0402_50V8J~D
100P_0402_50V8J~D
7
7
59
@
59
@
C
C
1
2
112
P
P
RSW1
@
RSW1
@
W
W
@SHORT PADS~D
@SHORT PADS~D
Place on Bottom
DS cable@
V
V
DS cable@
L
L
art Number
art Number
P
P
C02001DV00
C02001DV00
D
B B
Change KB connector to same as JSC1
KB Conn. Pitch=1.0mm
K
K
B1
B1
J
K
K
B
+
3
.3V_ALW
+
V_RUN
5
B
C
_INT#_ECE1117<40>
B
C
_DAT_ECE1117<40>
B
_CLK_ECE1117<40>
C
+
3
.3V_ALW
1
C
C
56
56
7
7
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
A A
5
Place close to JKB1
+
5
V_RUN
1
2
4
C
C
58
58
7
7
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
B_DET#
_DET#<18>
P
S2_CLK_TS
P
S
2_DAT_TS
J
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
0
1
0
1
11
N
D
G
12
D
N
G
FCI_10089709-010010LF~D
FCI_10089709-010010LF~D
CONN@
CONN@
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
A
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
D
R
R
P
P
art Number
art Number
G
G
C20323MX00
C20323MX00
F
F
art Number
art Number
P
P
C28A000800
C28A000800
D
D
S
S
art Number
art Number
P
P
K230003Q0L
K230003Q0L
P
P
Description
Description
H-CONN SET 0LD MB-LCD-CAM-LED 1CH TEFLON
H-CONN SET 0LD MB-LCD-CAM-LED 1CH TEFLON
C BATT@
T
TC BATT@
Description
Description
BATT CR2032 3V
BATT CR2032 3V
220MAH MAXELL
220MAH MAXELL
N@
A
A
N@
Description
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
p
p
eak@
eak@
Description
Description
SPK PACK ZJX 2.0W 4 OHM FG
SPK PACK ZJX 2.0W 4 OHM FG
2
ED Board FFC
ED Board FFC
L
L
@
@
art Number
art Number
P
P
BX00010100
BX00010100
N
N
@
@
MEDIA Board FFC
M
EDIA Board FFC
P
P
art Number
art Number
N
N
BX00010200
BX00010200
V
V
DS cable@
DS cable@
L
L
art Number
art Number
P
P
C02XXXXXXX
C02XXXXXXX
D
D
A DC_IN wire cable@
A DC_IN wire cable@
M
M
U
U
art Number
art Number
P
P
C30100BN0
C30100BN0
D
D
B
B
ttery bridge cable@
a
a
ttery bridge cable@
P
P
art Number
art Number
D
D
C020014Z10
C020014Z10
M
M
C wire set cable@
C wire set cable@
D
D
P
P
art Number Description
Description
FFC 6P H P1.0 PAD=0.65 63MM MB-LED/B 0LD
FFC 6P H P1.0 PAD=0.65 63MM MB-LED/B 0LD
Description
Description
Description
FFC 8P G P0.5 PAD.3 67MM MB-VOLUME/B 0LD
FFC 8P G P0.5 PAD.3 67MM MB-VOLUME/B 0LD
Description
Description
H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL
H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL
Description
Description
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
Description
Description
H-CONN SET 0FD M/B-BATTERY 9PIN
H-CONN SET 0FD M/B-BATTERY 9PIN
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
T
T
Title
tle
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
T
T
T
art Number Description
D
D
C30100BL0L
C30100BL0L
T
P FFC@
T/
/
P FFC@
Part Number
Part Number
N
NBX0000RR0L
BX0000RR0L
B FFC
K
K
B FFC
@
@
art Number
art Number
P
P
BX0000RQ0L
BX0000RQ0L
N
N
@
@
T wire cable
B
B
T wire cable
P
P
art Number
art Number
D
D
C02001510L
C02001510L
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
/KB/BT/FAN/RESET
P
P
P
/KB/BT/FAN/RESET
/KB/BT/FAN/RESET
L
L
L
-7781
A
-7781
-7781
A
A
1
CONN SET 0FD
CONN SET 0FD
MDC-RJ11
MDC-RJ11
Description
Description
F
FFC 8P F P0.5
FC 8P F P0.5
PAD=0.3 136MM
PAD=0.3 136MM
MB-TP/B 0FD
MB-TP/B 0FD
Description
Description
FFC 8P G P1.0 PAD=0.65 134MM MB-KB 0FD
FFC 8P G P1.0 PAD=0.65 134MM MB-KB 0FD
Description
Description
H-CONN SET 0FH MB-BT
H-CONN SET 0FH MB-BT
1
1
1
0
.
.
.
0
4
4
4
1 61Friday, February 24, 2012
1 6
1 6
o
o
o
0
1Friday, February 24, 2012
1Friday, February 24, 2012
f
f
f
5
+3.3V_ALW_PCH Source
+
3.3V_ALW2
12
07
07
9
9
R
R
100K_0402_5%~D
100K_0402_5%~D
D D
A
L
A
L
W_ON_3.3V#<20>
5
5
1A
1A
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
P
C
H_ALW_ON<40,44>
Q
W_ON_3.3V#
61
2
+P
WR_SRC_S
5
12
9
9
05
05
R
R
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
5
5
1B
1B
4
+3.3V_SUS Source
+
3.3V_ALW2
12
15
15
9
9
R
R
100K_0402_5%~D
100K_0402_5%~D
S
U
C C
S
S_ON<39>
U
S
I
O_SLP_S4#<16,39,46>
1 2
R
R
1
1
607 0_0402_5%~D@
607 0_0402_5%~D@
1
1
1
608 0_0402_5%~D@
608 0_0402_5%~D@
R
R
2
S_ON_3.3V#
61
Q
Q
3A
3A
5
5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
2
4
4
9
9
Q4
+3.3V_ALW +3.3V_ALW _PCH
A
W_ENABLE
L
1M_0402_5%~D
1M_0402_5%~D
12
R
R
1
1
619
619
+
PWR_SRC_S
12
3
5
4
Q
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45
2
1
G
G
3
1
C
C
3300P_0402_50V7K~D
3300P_0402_50V7K~D
2
+
.3V_ALW
3
R
R
11
9
9
11
470K_0402_5%~D
470K_0402_5%~D
S
S_ENABLE
U
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
5
5
3B
3B
4.7M_0402_5%~D
4.7M_0402_5%~D
12
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
C
C
1
7
7
60
60
2
7
7
62
62
Q
Q
4
4
5
5
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
2
1
G
G
3
R
R
1
1
618
618
12
12
S
S
45
7
7
C
C
220P_0402_50V8J~D
220P_0402_50V8J~D
R
R
9
9
08
08
20K_0402_5%~D
20K_0402_5%~D
1
2
67
67
3
DC/DC Interface
+
R
N_ON_ENABLE#<40>
U
S
I
O_SLP_S3#<11,16,27,35,39,47>
R
N_ON<27,35,39,47>
U
+
.3V_SUS
3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
C
C
7
7
14
14
9
9
R
R
65
65
20K_0402_5%~D
20K_0402_5%~D
1 2
35 0_0402_5%~D@R735 0_0402_5%~D@
R7
1 2
44 0_0402_5%~D@
44 0_0402_5%~D@
7
7
R
R
2
3
.3V_ALW2
12
6
1
2
R
R
09
09
9
9
100K_0402_5%~D
100K_0402_5%~D
R
N_ON_ENABLE#
U
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q
Q
5
5
2A
2A
+P
WR_SRC_S
5
+
WR_SRC_S
P
2
G
G
1
R
R
9
9
20
20
470K_0402_5%~D
470K_0402_5%~D
2
1
.
5V_RUN_ENABLE
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
5
5
2B
2B
4
12
R
R
30
30
9
9
330K_0402_5%~D
330K_0402_5%~D
1
05V_RUN_ENABLE
.
13
D
D
Q
Q
6
6
4
4
S
S
M3K7002FU_SC70-3~D
M3K7002FU_SC70-3~D
S
S
S
S
+1.5V_RUN Source
+1
.5V_MEM
8
7
6
5
2.2M_0402_5%
2.2M_0402_5%
1
R
R
1
1
610
610
2
+1.05V_RUN Source
Q
Q
+
6
6
1
.05V_M
3
3
SI4164DY-T1-GE3_SO8~D
SI4164DY-T1-GE3_SO8~D
8
7
5
1M_0402_5%~D
1M_0402_5%~D
12
R
R
1
1611
611
9
9
Q5
Q5
AO4304L_SO8
AO4304L_SO8
4
1
2
4
100P_0402_50V8J~D
100P_0402_50V8J~D
1
C
C
7
7
73
73
2
1
+
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
3
1
2
7
7
71
71
C
C
470P_0402_50V7K~D
470P_0402_50V7K~D
+
1
.05V_RUN
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
36
C
C
1
7
7
72
72
2
1
.5V_RUN
12
C
C
7
7
69
69
12
R
R
20K_0402_5%~D
20K_0402_5%~D
R
R
9
9
21
21
20K_0402_5%~D
20K_0402_5%~D
9
9
31
31
+3.3V_M Source
+
WR_SRC_S
18
9
9
18
R
R
100K_0402_5%~D
100K_0402_5%~D
A
ON_3.3V#
_
P
5
12
17
17
9
9
R
R
470K_0402_5%~D
470K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q
Q
5
5
7B
7B
4
+
3
.3V_ALW2
12
61
5
5
7A
7A
Q
B B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
S
O_SLP_A#<16,39,48>
I
S
O_SLP_A#
I
Q
2
A
_
ENABLE
+
.3V_ALW
3
4.7M_0402_5%~D
4.7M_0402_5%~D
12
R
R
1
1
617
617
Discharg Circuit
+
.3V_SUS
3
12
R
R
22
@
9
9
22
@
1K_0402_5%~D
1K_0402_5%~D
+
3
.3V_SUS_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q
Q
6
6
S
U
S_ON_3.3V#
2
G
A A
G
A
5
5
S
S
W_ON_3.3V#
L
+
3
.3V_ALW_PCH
2
G
G
12
R
R
9
9
28
@
28
@
1K_0402_5%~D
1K_0402_5%~D
+
3
.3V_ALWPCH_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q
Q
6
6
6
6
S
S
R
UN_ON_ENABLE#
2
G
G
+
5
V_RUN
12
@
@
1K_0402_5%~D
1K_0402_5%~D
+
5
V_RUN_CHG
13
D
D
S
S
R
R
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Q
Q
8
8
5
5
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
2
1
G
G
3
12
+
1
.5V_RUN
1
R
R
@
2
G
G
@
1K_0402_5%~D
1K_0402_5%~D
2
+
1
.5V_RUN_CHG
13
D
D
S
S
9
9
23
23
@
@
Q
Q
6
6
7
7
+
.3V_M
+
3
.3V_M
45
220P_0402_50V8J~D
220P_0402_50V8J~D
9
9
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
12
C
C
1
7
7
R
R
19
@
19
@
9
9
68
68
20K_0402_5%~D
20K_0402_5%~D
2
C
C
7
7
70
70
+
3
.3V_RUN
12
@
2
G
G
@
R
R
9
9
29
29
39_0603_5%~D
39_0603_5%~D
+
3
.3V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q
Q
6
6
9
9
S
S
24
24
@
@
Q
Q
6
6
8
8
2
G
G
+
.05V_RUN
1
A
_ON_3.3V#
1
@
@
9
9
R
R
39_0402_5%~D
39_0402_5%~D
2
+
1
.05V_RUN_CHG
SSM3K7002FU_SC70-3~D
@
SSM3K7002FU_SC70-3~D
@
13
D
D
Q
Q
7
7
0
0
S
S
3
12
R
R
16
16
9
9
39_0603_5%~D
39_0603_5%~D
+
3
.3V_M_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
1
D
D
Q
Q
6
6
2
0
0
G
G
S
S
3
+
1
.5V_CPU_VDDQ
12
R
2
G
G
R
26
9
9
26
220_0402_5%~D
220_0402_5%~D
+
1
.5V_CPU_VDDQ_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
S
S
25
25
R
U
N_ON_CPU1.5VS3#<7,11>
+
.75V_DDR_VTT
0
12
9
9
27
27
R
R
22_0603_5%~D
22_0603_5%~D
+
D
DR_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
Q
Q
7
7
2
2
2
G
G
Q
Q
7
7
1
1
S
S
+
WR_SRC_S
P
2
G
G
+
WR_SRC_S
P
2
G
G
12
R
R
06
06
9
9
470K_0402_5%~D
470K_0402_5%~D
5
V_RUN_ENABLE
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
Q
Q
6
6
2
2
S
S
12
12
9
9
12
R
R
470K_0402_5%~D
470K_0402_5%~D
3
.
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
1
D
D
Q
Q
5
5
6
6
S
S
3
3V_RUN_ENABLE
D
T
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
T
RADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
5
4
3
2
T
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+5V_RUN Source
Q
Q
5
5
5
5
+
5
V_ALW
DMN3030LSS
DMN3030LSS
8
7
5
4
220P_0402_25V8J
220P_0402_25V8J
1
C
C
7
7
63
63
2
+3.3V_RUN Source
1
1
6
6
Q
.3V_ALW
12
Q
DMN3030LSS
DMN3030LSS
8
7
5
4
1M_0402_5%~D
1M_0402_5%~D
@
@
R
R
1
1
627
627
1
2
C
C
C
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
P
P
P
WER CONTROL
O
WER CONTROL
WER CONTROL
O
O
L
L
L
-7781
-7781
A
A
A
-7781
+
3
LL CONFIDENTIAL/PROPRIETARY
E
tle
i
i
tle
+
V_RUN
5
1
2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
36
220P_0402_25V8J
220P_0402_25V8J
C
C
7
7
66
66
1
1
R
R
9
9
10
10
C
C
7
7
20K_0402_5%~D
20K_0402_5%~D
61
61
2
2
+
.3V_RUN
3
1
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
2
36
1
C
C
1
7
7
64
64
2
4
4
4
12
R
R
13
9
9
13
20K_0402_5%~D
20K_0402_5%~D
2 6
2 6
2 6
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
4
3
2
1
+
.3V_ALW
3
1
R
R
32
32
9
9
10K_0402_5%~D
Q
Q
4B
4B
7
5
12
50
50
9
9
R
R
100K_0402_5%~D
100K_0402_5%~D
7
4
3
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
5
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
3
7
7
8B
8B
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
D
D
9
9
5
5
1
2
2
6
6
D
D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
S
TA_ACT#<14>
D D
C C
A
M
A
SK_SATA_LED#<39>
L
D_SATA_DIAG_OUT#<39>
E
W
IRELESS_LED#<34,39>
B
_ACTIVE<41>
T
2
2
21
10K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
M
SK_BASE_LEDS#
A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
S
S_LED_MASK#
Y
+
.3V_ALW
3
12
R
R
9
37
37
9
100K_0402_5%~D
100K_0402_5%~D
7
7
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
M
A
SK_BASE_LEDS#
4A
4A
7
7
Q
Q
1
2
Q
Q
8
8
4B
4B
4
5
8A
8A
2
HDD LED solution for White LED Battery LED
+
5V_ALW
6
2
2
3
7
7
5
5
Q
Q
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1 3
1 2
R
R
34 2.2K_0402_5%~D
34 2.2K_0402_5%~D
9
9
P
A
NEL_HDD_LED
3
1
1
8
8
Q
Q
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1
1 2
38 2.2K_0402_5%~D
38 2.2K_0402_5%~D
9
9
R
R
S
TA_LED <30>
A
P
NEL_HDD_LED <24>
A
B
A
T2_LED#<39>
B
A
T1_LED#<39>
WLAN LED solution for White LED
B
R
+
V_ALW
5
61
2
Q
Q
79
7
9
PDTA114EU_SC70-3~D
PDTA114EU_SC70-3~D
1 3
1 2
39 1.8K_0402_5%~D
9
9
39 1.8K_0402_5%~D
R
R
W
L
AN_LED <30>
EATH_LED#<38,39>
3B
3B
Q8
Q8
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
3
5
M
A
SK_BASE_LEDS#
Q
Q
83A
83A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
2
M
SK_BASE_LEDS#
A
8
8
Q
Q
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1
4A
4A
2
M
SK_BASE_LEDS#
A
6
B
AT2_LED#_Q
B
A
T1_LED#_Q
B
EATH_LED#_Q
R
1 2
49 1K_0402_5%~D
49 1K_0402_5%~D
9
9
R
R
1 2
R
R
58 620_0402_5%
58 620_0402_5%
9
9
R
R
51
51
9
9
330_0402_5%~D
330_0402_5%~D
1
2
R
R
9
9
53
53
330_0402_5%~D
330_0402_5%~D
2
1
LTW-193ZDS5_WHITE~D
LTW-193ZDS5_WHITE~D
D1
E
E
D1
L
L
B
R
EATH_WHITE_LED_SNIFF
21
Place LED1 close to SW1
B
A
TT_WHITE <30>
B
TT_YELLOW <30>
A
B
A
TT_WHITE_LED <24>
B
A
TT_YELLOW_LED <24>
R
R
1 2
57 220_0402_5%~D
57 220_0402_5%~D
9
9
1 2
55 2.2K_0402_5%~D
9
9
55 2.2K_0402_5%~D
R
R
+
5
V_ALW
B
EATH_WHITE_LED <24>
R
Breath LED
B B
+
.3V_ALW
3
7
7
78 0.1U_0402_25V6K~D
78 0.1U_0402_25V6K~D
C
C
1 2
5
8
5
5
8
U
L
E
F
i
ducial Mark
1
@
D1
@
D
F
F
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
A A
2
@
D
D
2
@
F
F
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
D
D
3
@
3
@
F
F
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
F
D4
@FD4
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
D
not Mask LEDs (Lid Opened)
o
@
@
@
2
2
1
1
@
H
H
H
H
H
H
@
3
3
@
_3P3
_3P3
_3P3
H
H
H
H
_3P3
5
_3P0
H
H
_3P0
1
1
1
D Circuit Control Table
@
@
@
5
4
4
5
@
H
H
H
H
@H6
@
_3P0
_3P3
_3P3
H
H
H
H
_3P0
H_3P0
H_3P0
1
1
S
S_LED_MASK# LID_CL#
Y
0
1 0
@
8
8
9
9
@
@
@
@
H
6
H
H
1
@
H
H
H
H
H_3P3
H
H
_3P0
_3P0
_3P2
_3P2
H_3P3
1
1
+
P
WR_SRC
X
1 2
C
C
217 0.1U_0402_25V6K~D
1
1
217 0.1U_0402_25V6K~D
11
5
0
1
1
H
H
12
@H12
@
0
H
@
@
H_3P0
H_3P0
H_3P0
H_3P0
1
1
4
@
1
1
5
@
H
H
H
H
H
H
@
@
1
1
3
3
H_3P0
H_3P0
1
H
H
6
@
4
4
1
1
1
1
6
@
H_3P0
H_3P0
H_3P0
H_3P0
1
1
1
19
@H19
@
H
H_3P0x2P0
H_3P0x2P0
1
@
@
H
H
H_2P0N
H_2P0N
1
2
2
S
Y
S_LED_MASK#<39>
+
V_ALW
5
4
@
7
@
7
@
0
0
1
1
2
2
4
@
H
H
H
H
@
@
H_2P8
H_3P0
H_3P0
H_2P8
H_2P8
H_2P8
1
1
3
S
S_LED_MASK#
Y
L
ID_CL#
L
D_CL#<30,39>
I
H
H
2
2
5
5
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
B
TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
E
N
EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1
P
RTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
1
B
2
A
U
P
M
A
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
SK_BASE_LEDS#
2
EMI CLIP
L
L
IP1
IP1
C
C
EMI_CLIP
EMI_CLIP
D
N
G
IP2
L
L
IP2
C
C
EMI_CLIP
EMI_CLIP
N
D
G
1
1
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
tle
i
i
tle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
A
AD and Standoff
D and Standoff
D and Standoff
A
L
L
L
-7781
-7781
A
A
A
-7781
1
4
4
4
3 6
3 6
3 6
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
ESD Diodes
1
@
@
P
P
D1
D1
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
Media Bay Battery Connector
ATT1
ATT1
MB
12
12
5
5
C
C
P
P
2200P_0402_50V7K~D
2200P_0402_50V7K~D
MB
1
1
Z5
304
2
2
Z
305
5
3
3
Z5
306
4
4
5
5
6
6
7
N
D
G
8
N
D
G
SUYIN_150010GR006M500ZR
SUYIN_150010GR006M500ZR
P
rimary Battery Connector
11
D
N
G
10
D
N
G
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ATT1
ATT1
B
B
P
P
SUYIN_200275MR009G50PZR
SUYIN_200275MR009G50PZR
D D
2
2
PC
PC
2200P_0402_50V7K~D
2200P_0402_50V7K~D
C C
B B
2
3
P
P
R
R
3
3
R
100_0402_5%~D
100_0402_5%~D
1
G
N
D
1
2
100_0402_5%~D
_PSID
100_0402_5%~D
G
D
N
Z
304
4
Z
305
4
Z
306
4
N
B
P
P
100_0402_5%~D
100_0402_5%~D
2
1
@
@
P
P
D
5
5
D
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
3
R
R
7
7
P
P
100_0402_5%~D
100_0402_5%~D
1 2
BLM18BD102SN1D_0603~D
BLM18BD102SN1D_0603~D
R
4
4
2
E
SD Diodes
9
9
R
R
P
P
1 2
P
P
4
L
L
4
1
@
@
D
2
2
D
P
P
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
2
3
P
P
5
5
R
R
100_0402_5%~D
100_0402_5%~D
1 2
1
@
@
2
3
P
P
100_0402_5%~D
100_0402_5%~D
1 2
12
4
P
P
6
6
D
D
PESD24VS2UT_SOT23-3~D
PESD24VS2UT_SOT23-3~D
8
8
R
R
3
2
OINCELL
+C
1
COIN RTC Battery
12
1
1
R
R
P
P
1K_0402_5%~D
012
4
Z
2
3
P
P
4
4
D
D
1
P
P
U
U
1
1
1
N
O
2
G
N
3
N
C
TS5A63157DCKR_SC70-6~D
TS5A63157DCKR_SC70-6~D
1K_0402_5%~D
1
2
D
C
+
TC_CELL
R
P
P
C
C
3
3
1U_0603_10V4Z~D
1U_0603_10V4Z~D
6
I
N
5
V
+
4
O
M
+
OINCELL
C
G
IO_PSID_SELECT <40>
P
+
5V_ALW
P
S
_ID <41>
J
J
R
TC1
TC1
R
3
1
G
1
4
22G
TYCO_2-1775293-2~D
TYCO_2-1775293-2~D
1
1
PL
PL
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
MB
ATT+_C
B
A
B
A
14
14
R
R
P
P
1 2
100K_0402_1%~D
100K_0402_1%~D
16
16
R
R
P
P
1 2
15K_0402_1%~D
15K_0402_1%~D
Y_SMBCLK <29,41>
Y_SMBDAT <29,41>
P
P
B
AT_SMBCLK <41>
P
B
AT_SMBDAT <41>
@
@
B
ATT+_C
R
R
P
P
1 2
0_0402_5%~D
0_0402_5%~D
D
D
1 3
2
B
B
E
E
11
11
2
C
C
3 1
1
1
1
C
C
P
P
2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
4
4
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
S
S
2
2
Q
Q
P
P
FDV301N_G_NL_SOT23-3~D
FDV301N_G_NL_SOT23-3~D
G
G
3
3
Q
Q
P
P
MMST3904-7-F_SOT323~D
MMST3904-7-F_SOT323~D
1
@
@
2 1
PAD-OPEN 1x2m
PAD-OPEN 1x2m
12
33_0402_5%~D
33_0402_5%~D
1 2
2
J
J
P1
P1
P
P
L
L
2
2
P
P
1 2
3
PL
PL
3
1 2
J
J
P2
@
P2
@
P
P
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
R13
R13
+
V_ALW
5
7
7
D
D
P
P
@
@
DA204U_SOT323~D
DA204U_SOT323~D
+
V_ALW
5
+
3
.3V_ALW
P
15
15
R
R
P
P
BATT+
2
P
10K_0402_1%~D
10K_0402_1%~D
2
2
R
R
P
P
B
ATT+
G
D
N
17
17
R
R
P
P
1 2
10K_0402_5%~D@
10K_0402_5%~D@
12
M
DULE_BATT_PRES# <40,57>
+
6
6
R
R
P
P
+
12
12
R
R
P
P
3
.3V_ALW
100K_0402_5%~D
100K_0402_5%~D
.3V_ALW
3
2.2K_0402_5%~D
2.2K_0402_5%~D
O
12
1 2
N
_PSID_TS5A63157
B
P
S
100K_0402_5%~D
100K_0402_5%~D
M
3
1
12
P
D
O
CK_PSID<39>
ID_DISABLE# <40>
+
3
.3V_RTC_LDO
RB715FGT106_UMD3
RB715FGT106_UMD3
BAT_PRES# <40,57>
D
_IN+ Source
C
+
D
C_IN
P
P
L
L
5
5
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
1
13
13
D
D
12
P
2
P
P
L
L
6
6
1 2
P
@
@
12
VZ0603M260APT_0603
VZ0603M260APT_0603
16
16
PC
PC
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PS_HPW15003-05M101R
PS_HPW15003-05M101R
5
5
-
DCIN_JACK
4
4
3
3
+
D
2
A A
2
1
1
P
P
PDC1
PDC1
J
J
CIN_JACK
12
18
18
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
5
13
13
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
+
D
C_IN
10
C
C10
P
P
12
23
23
R
R
P
P
@
@
4.7K_0805_5%~D
4.7K_0805_5%~D
12
20
20
R
R
1 2
P
P
1M_0402_5%~D
1M_0402_5%~D
0.022U_0805_50V7K~D
0.022U_0805_50V7K~D
12
26
26
R
R
P
P
4
P
P
Q5
Q
5
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
1
S
2
S
3
S
4
G
P
P
24
24
R
R
1 2
10K_0402_5%~D
10K_0402_5%~D
1M_0402_5%~D
1M_0402_5%~D
8
D
7
D
6
D
5
D
S
O
FT_START_GC <57>
12
12
12
12
11
11
C
C
C
C
P
P
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+
C_IN_SS
D
12
12
14
14
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
P
C
15
15
22
22
C
C
R
R
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
100K_0402_5%~D
100K_0402_5%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A
ND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
E
PARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_ALW_ON<39>
+
3
.3V_ALW
+
P
WR_SRC
P
P
R
R
27
@
27
@
0_0402_5%~D
0_0402_5%~D
1 2
P
P
25
@
25
@
R
R
0_0402_5%
0_0402_5%
1
12
12
8
8
19
19
C
C
R
R
P
P
P
P
100K_0402_1%
P
P
22K_0402_1%
22K_0402_1%
1
B_N_003
S
V
13
D
D
P
V
B_N_002
S
2
12
P
2
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
G
G
S
S
17
17
C
C
P
P
.1U_0402_16V7K
.1U_0402_16V7K
100K_0402_1%
21
21
R
R
6
6
Q
Q
2
V
2
TP0610K-T1-GE3_SOT23-3
TP0610K-T1-GE3_SOT23-3
0.22U_0603_25V7K
0.22U_0603_25V7K
B_N_001
S
2
+
WR_SRC_S
P
13
12
9
9
C
C
P
P
4
4
Q
Q
P
P
0.1U_0603_25V7K
0.1U_0603_25V7K
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
i
Title
tle
i
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
+
+
+
CIN
D
D
D
CIN
CIN
L
L
L
-7781
A
A
-7781
-7781
A
1
4
4
4
4 6
4 6
4 6
o
o
o
f
f
f
1
1
1
0
.
.
0
0
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
A
1 1
@
@
P
P
JP
JP
100
100
1 2
PAD-OPEN 1x3m
+
P
2 2
PAD-OPEN 1x3m
WR_SRC
P
P
L
L
100
100
1UH_PCMB053T-1R0MS_7A_ 20%
1UH_PCMB053T-1R0MS_7A_ 20%
3
.3VALWP
12
+
3
12
100
100
102
102
C
C
C
C
P
P
P
P
0.1U_0402_25V6
0.1U_0402_25V6
.3V_ALWP
P
P
123
C
C
123
0.1U_0603_25V7K
0.1U_0603_25V7K
+
C1_PWR_SRC
D
12
12
103
103
C
C
P
P
@
@
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
2200P_0402_50V7K
12
12
119
119
C
C
P
P
10U_0805_25V6K
10U_0805_25V6K
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
101
101
L
L
P
P
2.2UH_ETQP3W2R2W FN_8.5A_20%
2.2UH_ETQP3W2R2W FN_8.5A_20%
1
+
+
110
110
220U_6.3V_M
220U_6.3V_M
PC
PC
2
12
109
109
R
R
P
P
4.7_1206_5%
4.7_1206_5%
TDC 5.72A
3 3
Peak Current 8.17A
OCP current 9.8A
+
FSW:375KHz
TRIP2
N
E
3
Q
Q
104B
104B
P
115
R
R
115
P
P
2K_0402_1%~D
2K_0402_1%~D
1 2
P
P
116
R
116
R
P
5
4
2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
A
WON<41>
L
@
4 4
T
ERM_STP#23
H
@
0_0402_5%~D
0_0402_5%~D
1 2
TRIP1
N
E
61
2
13
P
P
Q
Q
PDTC115EU_SOT323-3
PDTC115EU_SOT323-3
B
+
.3V_RTC_LDO
3
100
100
Q
Q
P
P
4
1
3 5
2
12
UB_3V
N
S
12
112
112
C
C
P
P
680P_0603_50V7K
680P_0603_50V7K
WR_SRC
P
104A
104A
Q
Q
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
114
114
R
R
P
P
100K_0402_1%
100K_0402_1%
1
105
105
Q
Q
P
P
FDMC8878_POWER33-8-5
FDMC8878_POWER33-8-5
3 5
241
MMSZ5229BS_SOD323~D
MMSZ5229BS_SOD323~D
2
102
102
@
@
1 2
+
5
P
R100
@PR100
@
0_0402_5%~D
0_0402_5%~D
1 2
10U_0805_6.3V6M
10U_0805_6.3V6M
0.22U_0603_16V7K
0.22U_0603_16V7K
D
D
100
100
P
P
V_ALW2
+
3
P
P
107
C
C
107
P
P
108
108
C
C
1 2
L
_3V
X
@
@
P
P
499K_0402_1%~D
499K_0402_1%~D
.3V_ALW2
12
B
T1_3V
S
113
113
R
R
12
107
107
R
R
P
P
1
2.2_0603_5%
2.2_0603_5%
L
_3V
G
111
111
R
R
P
P
@
@
300K_0402_1%
300K_0402_1%
2
V
REF_6182
22P_0402_50V8J~D
22P_0402_50V8J~D
13K_0402_1%
13K_0402_1%
20K_0402_1%
20K_0402_1%
169K_0402_1%~N
169K_0402_1%~N
B
T_3V
S
2
U
G
12
115
115
C
C
P
P
@
@
1U_0603_10V6K
1U_0603_10V6K
1U_0603_16V6K
1U_0603_16V6K
PC
@PC120
@
2
R
R
P
P
1 2
PR
PR
1 2
R
R
105
105
P
P
1 2
25
7
8
9
_3V
10
11
12
12
2
V
REF_6182
C
C
C
P
P
120
1
101
101
103
103
E
N
100
100
U
U
P
P
PAD
P
O
2
V
EG3
R
V
O
OT2
B
G
ATE2
U
ASE2
H
P
ATE2
G
L
+
D
12
101
101
F
B
_3V
TRIP2
6
5
4
3
2
F
B
E
F
R
NSEL
TRIP2
O
N
T
E
D
IPSEL
N
N
N
K
I
G
E
S
V
3
15
1
14
16
C1_PWR_SRC
12
P
P
121
@
121
@
C
C
12
22P_0402_50V8J~D
22P_0402_50V8J~D
R
R
102
102
P
P
30.9K_0402_1%
30.9K_0402_1%
1 2
P
P
R104
R104
20K_0402_1%
20K_0402_1%
F
_5V
B
1 2
P
P
R
R
106
106
90.9K_0402_1%
90.9K_0402_1%
E
TRIP1
N
1 2
1
2
1
B
F
TRIP1
N
E
24
1
O
V
23
G
OOD
P
22
OT1
O
B
21
G
ATE1
U
20
H
ASE1
P
19
G
ATE1
L
EG5
C
R
N
V
8
17
1
RT8205LZQW(2) WQFN 24P PW M
RT8205LZQW(2) WQFN 24P PW M
+
5
V_ALW2
12
P
P
C
C
114
114
4.7U_0805_10V6K
4.7U_0805_10V6K
116
116
C
C
P
P
0.1U_0603_25V7K
0.1U_0603_25V7K
B
S
T_5V
U
L
X
L
G
+
1 2
2.2_0603_5%
2.2_0603_5%
G_5V
_5V
_5V
+
V_ALWP
5
3
.3V_ALWP
C104
C104
P
P
R
R
108
108
P
P
R
R
P
P
100K_0402_1%
100K_0402_1%
D
+
D
C1_PWR_SRC
1
12
105
C
C105
P
P
2
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
P
P
0.22U_0603_16V7K
0.22U_0603_16V7K
B
T1_5V
S
1 2
+
3
.3V_ALW
2
112
112
1
P
P
JP
JP
101
101
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
JP
JP
102
102
P
P
1
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
JP
JP
103
103
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
104
JP
JP
104
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
12
12
106
106
118
118
C
C
C
C
P
P
P
P
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
C
C
109
109
P
FDMC7692S_POWER33 -8-5
FDMC7692S_POWER33 -8-5
2
P
A
L
W_PWRGD_3V_5V <41>
+
5
V_ALW
+
.3V_ALW
3
E
P
P
101
101
Q
Q
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
5
110
110
R
R
P
P
103
103
Q
Q
241
3
P
P
102
102
L
12
UB_5V
N
S
1
2
1 2
113
113
PC
PC
680P_0603_50V7K
680P_0603_50V7K
5
VALWP
L
111
111
C
C
P
P
220U_6.3V_M
220U_6.3V_M
3.3UH_ETQP3W3R3W FN_7A_20%
3.3UH_ETQP3W3R3W FN_7A_20%
4.7_1206_5%
4.7_1206_5%
1
+
+
2
+
5
V_ALWP
1
122
C
C
122
P
P
2
0.1U_0603_25V7K
0.1U_0603_25V7K
TDC 4.88A
Peak Current 6.98A
OCP current 8.38A
FSW:300KHz
12
117
117
PC
PC
@
@
1U_0603_10V6K
1U_0603_10V6K
A
B
T
H
IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
A
D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
N
D
PARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NE ITHER THIS SHEET NOR TH E INFORMATION IT CONTAINS
E
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
T
T
tle
Title
i
i
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
+
+
+
V_ALW/3.3V_ALW
V_ALW/3.3V_ALW
5
5
5
V_ALW/3.3V_ALW
L
L
L
-7781
A
A
A
-7781
-7781
E
4
4
4
5 6
5 6
5 6
o
o
o
f
f
f
1
1
1
.
.
.
0
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
4
3
2
1
1.5Volt +/- 5%
TDC 7.17A
Peak Current 10.25A
OCP current 12.3A
0.
75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
P200
P200
J
J
P
+
WR_SRC
P
D D
+
.5V_MEN_P
1
C C
B B
M
ode S3 S5 +1.5V_MEN +V_DDR_REF +0.75V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on
+
.5V_MEN_P
1
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
1
+
+
214
214
C
C
P
P
330U_SX_2VY~D
330U_SX_2VY~D
2
@
@
P
1UH 20% F DUE1040D-H-1R0 M=P3_21.3A_20% ~D
1UH 20% F DUE1040D-H-1R0 M=P3_21.3A_20% ~D
1 2
1
+
+
208
208
390U_2.5V_M
390U_2.5V_M
C
C
P
P
2
P
P
L200
L
200
P201
J
P
P
P201
J
2
2
JUMP_1x3m
JUMP_1x3m
P
P
P202
P202
J
J
2
2
JUMP_1x3m
JUMP_1x3m
1
.
5V_B+
1
12
200
200
2
C
C
P
P
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
209
209
C
C
12
P
P
680P_0603_50V7K
680P_0603_50V7K
UB_1.5V
N
S
12
R203
R203
P
P
4.7_1206_5%
4.7_1206_5%
S
O_SLP_S 4#<41>
I
1
1
1
1
12
201
201
C
C
P
P
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
D
R_ON<41>
D
+
.5V_MEM
1
P
P
J
J
P204
P
P
R
R
200
200
1 2
2.2_0603 _5%~D
2.2_0603 _5%~D
12
203
203
202
202
C
C
C
C
P
P
P
P
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
.
5V_SUS_ PWRGD<41>
@
@
R
R
P
P
0_0402_ 5%~D
0_0402_ 5%~D
1
210
@
210
@
R
R
P
P
0_0402_ 5%~D
0_0402_ 5%~D
1 2
+
.75V_P
0
5
200
200
Q
Q
P
P
123
SIR472DP-T1-GE3_POWERPAK8-5~D
SIR472DP-T1-GE3_POWERPAK8-5~D
5
201
201
Q
Q
P
P
213
SIR466DP-T1-GE3_POWERPAK8-5
SIR466DP-T1-GE3_POWERPAK8-5
206
206
2
12
2
1
4
+
5
V_ALW
4
+
3.3V_ALW
P
P
R
R
204
204
100K_04 02_1%~D
100K_04 02_1%~D
P
P
C
C
212
@
212
@
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
P203
P203
J
J
P
P
12
PAD-OPEN 1x1m
PAD-OPEN 1x1m
204
204
C
C
P
P
0.22U_0603_16V7K~D
0.22U_0603_16V7K~D
12
202
202
R
R
P
P
5.1_0603 _5%~D
5.1_0603 _5%~D
1 2
210
210
C
C
P
P
1U_0603 _10V6K~D
1U_0603 _10V6K~D
S
5
_1.5V
+
.75V_DDR_VTT
0
B
O
R
R
201
201
P
P
5.62K_04 02_1%
5.62K_04 02_1%
1 2
1U_0603 _10V6K~D
1U_0603 _10V6K~D
OT_1.5V
D
H
S
W
D
L
_1.5V
P
P
C
C
207
207
V
0
75V_DDR _VTT_ON<41>
.
_1.5V
_1.5V
D
C
S
_1.5V
D_1.5V
+
V_ALW
5
1
.
5V_SUS_ PWRGD
1
5V_B+
.
17
16
ATE
ASE
H
G
P
15
G
L
14
G
P
3
1
S
C
12
D
V
11
DD
V
1M_0402 _1%~D
1M_0402 _1%~D
1 2
@
@
F
sense trace
B
U
ATE
ND
RT8207M ZQW_W QFN20_3X3
RT8207M ZQW_W QFN20_3X3
DP
OOD
G
ON
P
T
9
10
205
205
R
R
P
P
P
P
R
R
208
208
0_0402_ 5%~D
0_0402_ 5%~D
2
1
+
.5V_MEN_ P
1
V
L
DOIN_1.5V
20
19
18
OT
O
B
5
S
8
U
U
P
P
T
T
V
P
DOIN
L
V
T
TGND
V
T
TSNS
V
G
TREF
T
V
D
V
3
B
F
S
6
7
1
.
5V_FB
P204
2
PAD-OPEN 1x1m
PAD-OPEN 1x1m
200
200
21
A
D
1
2
3
N
D
+
4
V
5
DQ
F
B sense trace
V
DDQ_1.5V
1
_DDR_RE F
+
.5V_MEN_P
1
+
1
when FB pull down to GND
P
P
207
@
207
@
R
R
0_0402_ 5%~D
0_0402_ 5%~D
12
C
C
215
@
215
@
P
P
22P_040 2_50V8J~D
22P_040 2_50V8J~D
12
P
P
R209
R209
0_0402_ 5%~D
0_0402_ 5%~D
1 2
.5V_MEN_P
12
@
@
OCP Current 0.9A
1
12
206
206
205
205
C
C
C
C
P
P
P
2
P
P
C
C
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
P
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
213
213
+
.75V_P
0
+
_DDR_REF
V
P
P
C
C
211
211
0.033U_0 402_16V7~D
0.033U_0 402_16V7~D
A A
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
Title
itle
tle
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
A
D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
N
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
5
4
3
2
i
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
+
+
+
.5V_MEN/+0.75V_DDR_VTT
.5V_MEN/+0.75V_DDR_VTT
1
1
1
.5V_MEN/+0.75V_DDR_VTT
L
L
L
A-7781
A-7781
A
-7781
1
4
4
4
6 6
6 6
6 6
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
A
1 1
P
P
P301
P301
J
+
3.3V_ALW
R
N_ON<11,28,38,40,43>
U
2 2
S
I
O_SLP_S3#<11,28,38,40,43>
J
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
P
P
R
R
1 2
12
1 2
303 0_0402_5%@
303 0_0402_5%@
P
P
306
@
306
@
R
R
0_0402_5%~D
0_0402_5%~D
P
P
C
C
22U_0805_6.3VAM
22U_0805_6.3VAM
300
300
E
E
N
N
_1.8VSP
_1.8VSP
1
8VSP_VIN
.
12
P
P
C
C
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
P
P
304
@
304
@
R
R
47K_0402_5%
47K_0402_5%
307
307
12
12
B
P
P
300
300
R
R
12
.3V_RUN
+3
10K_0402_5%~D
10K_0402_5%~D
1.
8V_RUN_PWRGD <40>
P
P
U
U
300
300
4
10
G
L
P
V
IN
P
9
P
L
IN
V
8
S
IN
V
5
304
304
C
C
P
P
@
@
0.1U_0402_10V7K
0.1U_0402_10V7K
F
E
N
C
P
T
N
1
7
1
SYN470DBC_DFN10_3X3
SYN470DBC_DFN10_3X3
1
8VSP_LX
.
2
X
3
X
1
8VSP_FB
.
6
B
C
N
1
1UH_NRS4018T1R 0NDGJ_3.2A_20%
1UH_NRS4018T1R 0NDGJ_3.2A_20%
12
UB_1.8VSP
N
S
12
1 2
301
301
R
R
P
P
4.7_0805_5%~D
4.7_0805_5%~D
305
305
C
C
P
P
680P_0603_50V7K
680P_0603_50V7K
P
P
301
301
L
L
P
P
302
302
R
R
20K_0402_1%
20K_0402_1%
P
P
305
305
R
R
10K_0402_1%
10K_0402_1%
C
12
12
<
V
12
301
301
C
C
P
P
22P_0402_50V8J
22P_0402_50V8J
o=1.8V> VFB=0.6V
D
1
.8Volt +/-5%
TDC 0.65A
Peak Current 0.93A
OCP current 1.12A
+
.8V_RUNP
1
1
12
302
302
C
C
P
P
22U_0805_6.3VAM
22U_0805_6.3VAM
12
306
306
C
C
303
303
P
P
C
C
2
P
P
22U_0805_6.3VAM
22U_0805_6.3VAM
47P_0402_50V8J~D
47P_0402_50V8J~D
Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V
P
P
P300
J
J
P300
+
.8V_RUNP
3 3
4 4
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
A
B
1
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
C
+
.8V_RUN
1
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
pal Electronics, Inc.
pal Electronics, Inc.
om
om
om
T
T
tle
i
i
Title
tle
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
+
+
+
.8V_RUN
.8V_RUN
1
1
.8V_RUN
1
L
L
L
-7781
A
A
A
-7781
-7781
D
4
4
4
7 6
7 6
7 6
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
5
D D
1
05V_A_PWRGD<41>
R
402
P
P
R
402
110K_0402_1%
110K_0402_1%
1
P
P
R
R
403
@
403
@
0_0402_5%~D
S
I
O_SLP_A#<16,40 ,43>
S
0 mode be high level
C C
0_0402_5%~D
1 2
P
P
0.1U_0402_16V7K
0.1U_0402_16V7K
.
2
12
@
@
C
C
407
407
+3
.3V_ALW
400
400
R
R
P
P
100K_0402_1%~D
100K_0402_1%~D
T
R
IP_+V1.05SP
E
N
_+V1.05SP
F
B
_+V1.05SP
R
_+V1.05SP
F
12
P
P
405
405
R
R
470K_0402_1%
470K_0402_1%
12
4
P
P
400
400
U
U
1
2
3
4
5
4.99K_0402_1%
4.99K_0402_1%
V
P
B
ST
OOD
G
D
T
E
V
R
TPS51212DSCR_SON10_ 3X3
TPS51212DSCR_SON10_ 3X3
P
P
R
R
VH
R
R
IP
S
N
F
F
406
406
W
V
B
5
IN
D
VL
R
T
P
12
3
P
P
401
401
R
R
2.2_0603_5%
2.2_0603_5%
1 2
B
T_+V1.05SP
S
10
U
G
9
8
7
6
1
_+V1.05SP
S
W
_+V1.05SP
+
V_ALW
L
G
_+V1.05SP
1
12
P
P
C
C
405
405
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
5
P
P
C
C
404
404
0.1U_0603_25V7K
0.1U_0603_25V7K
2
1
P
P
Q
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
Q
401
401
3 5
241
4
1
3 5
2
2
+
1.05SP_B+
V
401
401
C
C
P
P
P
P
400
400
Q
Q
FDMC8884_POWER33-8- 5
FDMC8884_POWER33-8- 5
1UH_FDSD0630-H-1 R0M=P3 11A_20%
1UH_FDSD0630-H-1 R0M=P3 11A_20%
1
P
P
404
404
R
R
4.7_1206_5%
4.7_1206_5%
2
12
C408
C408
P
P
680P_0603_50V7K
680P_0603_50V7K
12
402
402
C
C
P
P
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
P
P
400
L
L
400
1 2
1
P
P
J
J
P400
P400
2
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
1
12
12
400
400
403
C403
C
C
2
C
P
P
P
P
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
1
1
+
+
406
406
C
C
P
P
2
220U_D2_4VM
220U_D2_4VM
+
WR_SRC
P
+
.05V_MP
1
+
1
P
P
J
P401
P401
P
P
407
407
R
B B
A A
5
R
10K_0402_1%
10K_0402_1%
1 2
+
1.05V_MP
T
HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
4
3
J
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
P
P
JP402
JP402
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
+
2
1.05V_M
D
LL CONFIDENTIAL/PROPRIETARY
E
T
T
Title
i
i
tle
tle
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet
Date: Sheet
Date: Sheet
.05Volt +/- 5%
TDC 4.75A
Peak Current 6.69A
OCP current 8.03A
C
C
C
pal Electronics, Inc.
om
om
om
pal Electronics, Inc.
pal Electronics, Inc.
+
+
+
.05V_M
1
1
1
.05V_M
.05V_M
L
L
L
-7781
-7781
A
A
A
-7781
1
4
4
4
8 6
8 6
8 6
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
+
3
.3V_RUN
D D
1 2
1
05V_VTTPWRGD<41,53>
.
501
501
R
R
P
P
110K_0402_1%
110K_0402_1%
1 2
P
P
503
@
503
@
R
R
0_0402_5%~D
0_0402_5%~D
C
P
U_VTT_ON<40>
C C
1 2
@
@
P
P
C
0.1U_0402_16V7K
0.1U_0402_16V7K
C
506
506
12
T
R
IP_+V1.05S_VCCPP
E
N
_+V1.05S_VCCPP
F
B
_+V1.05S_VCCPP
R
_+V1.05S_VCCPP
F
12
P
P
505
505
R
R
470K_0402_1%
470K_0402_1%
P
P
4.32K_0402_1%
4.32K_0402_1%
2
4
500
500
R
R
P
P
100K_0402_5%
100K_0402_5%
P
P
500
U
U
500
1
2
3
4
5
507
507
R
R
V
P
B
G
OOD
T
D
R
IP
VH
R
E
V
R
TPS51212DSCR_SON10_ 3X3
TPS51212DSCR_SON10_ 3X3
S
N
V
B
5
F
D
R
F
1
3
+V
P
P
Q
Q
500
500
FDMC8884_POWER33-8- 5
FDMC8884_POWER33-8- 5
R
R
502
502
P
P
2.2_0603_5%
2.2_0603_5%
1 2
B
T_+V1.05S_VCCPP
S
10
ST
W
IN
VL
T
P
9
8
7
6
1
1
U
G_+V1.05S_VCCPP
S
W
_+V1.05S_VCCPP
L
G
_+V1.05S_VCCPP
P
P
C
C
504
504
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
+
12
P
P
C
C
505
505
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
V_ALW
5
241
3 5
Q
Q
501
501
P
P
3 5
241
2
1.05S_VCCPP_B+
1
1
C502
C502
501
501
P
P
C
C
2
P
P
1UH_FDSD0630-H-1 R0M=P3 11A_20%~D
1UH_FDSD0630-H-1 R0M=P3 11A_20%~D
1 2
12
P
P
504
R
R
504
4.7_1206_5%
4.7_1206_5%
12
P
P
C508
C508
680P_0603_50V7K
680P_0603_50V7K
V
S
2
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
500
500
L
L
P
P
V
T_SENSE_FB
T
SIO_SENSE_R_FB
1
503
503
C
C
2
P
P
12
@
@
C
C
510
510
P
P
.1U_0402_16V7K
.1U_0402_16V7K
1
P500
P500
PJ
PJ
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
12
500
500
C
C
P
P
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
4.7U_0805_25V6K
+
1
1
+
+
507
C
C507
P
P
2
220U_D2_4VM
220U_D2_4VM
L
ocal sense put on HW site
508
@
R
R
508
@
P
P
0_0402_5%~D
0_0402_5%~D
12
P
P
513
@
513
@
R
R
0_0402_5%~D
0_0402_5%~D
12
V
T_SENSE <10>
T
V
S
SIO_SENSE_R <10>
WR_SRC
+P
.05VTTP
12
P
P
R
R
509
509
71.5K_0402_1%
B B
71.5K_0402_1%
+
.3V_RUN
3
V
CP_PWRCTRL = "High" , Vo = 1.05V (SNB)
C
VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)
R
R
511
511
P
P
P
R510
R
510
10K_0402_1%
10K_0402_1%
1 2
12
P
R514
@PR514
@
10_0402_1%~D
10_0402_1%~D
A A
5
13
D
D
502
502
Q
Q
P
P
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
2
G
G
S
S
509
509
C
C
12
P
P
@
@
.01U_0402_16V7K~D
.01U_0402_16V7K~D
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
4
P
10K_0402_5%
10K_0402_5%
1 2
F
V
C
CP_PWRCTRL <11>
J
J
P501
P501
P
P
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
J
J
P502
P502
P
+
1
.05VTTP
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
P
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
3
rom GPIO
+
1
.05V_RUN_VTT
D
E
2
+
1
.05Volt +/- 5%
TDC 5.98A
Peak Current 8.55A
OCP current 10.26A
LL CONFIDENTIAL/PROPRIETARY
C
C
C
pal Electronics, Inc.
om
om
om
pal Electronics, Inc.
T
T
i
i
Title
tle
tle
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
+
+
+
1.05V_RUN_VTT
.05V_RUN_VTT
.05V_RUN_VTT
1
1
L
L
L
-7781
-7781
A
A
A
-7781
1
4
4
4
9 6
9 6
9 6
o
o
o
f
f
f
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
1
1
1
0
0
.
.
.
0
5
4
3
2
1
VID [0] VID[1] VCCSA Vout
T
h
e 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
R
R
601
601
P
P
1K_0402_5%
D D
P
P
R
R
600
@
600
@
0_0402_5%~D
0_0402_5%~D
+
5
V_ALW
10_0402_1%
10_0402_1%
19
20
21
22
23
24
P
P
C
C
617
617
12
R
R
606
606
P
P
U
U
P
P
P
P
P
V
V
V
12
V
CSAPWROK<41>
C
P
P
602
602
C
C
2.2U_0603_10V7K
2.2U_0603_10V7K
1 2
C C
1
613
613
C
C
600
P
P
C600
C
P
P
1 2
2
0.1U_0603_25V7K
0.1U_0603_25V7K
2200P_0402_50V7K
+
3
.3V_ALW
B B
P
P
P600
P600
J
J
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
2200P_0402_50V7K
+
CCSA_PWR_SRC
V
G
N
2
615
615
614
614
C
C
C
C
P
P
P
P
1
10U_0805_25V6M
10U_0805_25V6M
10U_0805_25V6M
10U_0805_25V6M
DA_VCCSA
2
1
+
CCSA_PWR_SRC
V
P
P
C616
C616
0.22U_0402_10V6K
0.22U_0402_10V6K
12
3300P_0402_50V7K
3300P_0402_50V7K
2
1
12
18
17
600
600
FILT
DRV
5
5
V
V
G
ND
GND
ND
G
TPS51461RGER_QFN24_4X4~D
TPS51461RGER_QFN24_4X4~D
N
I
IN
I
N
D
EF
N
R
G
V
2
1
P
P
R
613
613
R
5.1K_0402_1%~D
5.1K_0402_1%~D
+
3
603
603
R
R
P
P
100K_0402_5%
100K_0402_5%
601
601
C
C
P
P
1U_0603_10V6K
1U_0603_10V6K
12
.3V_RUN
1
+
2
V
CCSA_PWRGD
16
OOD
G
P
MP
O
C
3
618
618
C
C
P
P
0.01U_0402_25V7K
0.01U_0402_25V7K
1K_0402_5%
12
P
P
602
@
602
@
R
R
1 2
0_0402_5%~D
0_0402_5%~D
P
P
604
@
604
@
R
R
1 2
0_0402_5%~D
0_0402_5%~D
605
605
R
R
P
P
1K_0402_5%
1K_0402_5%
+
V
CCSA_EN
3
14
15
1
N
D0
D1
E
I
I
V
V
12
S
T
B
1
1
W
S
1
0
W
S
9
W
S
8
W
S
7
W
S
2
5
P
T
DE
UT
EW
O
L
O
S
V
M
4
5
6
1 2
12
+
CCSA_BT
V
+
CCSA_PHASE
V
@
@
33K_0402_5%
33K_0402_5%
P
P
610
610
R
R
V
CSA_VID_1 <11>
C
V
CSA_VID_0 <11>
C
@
@
R
R
P
P
0_0402_5%~D
0_0402_5%~D
1 2
P
P
R
R
608
608
2.2_0603_1%
2.2_0603_1%
1
12
607
607
+
2
12
12
V
CCSA_BT_1
P
P
C
C
604
@
604
@
680P_0603_50V7K
680P_0603_50V7K
609
609
R
R
P
P
@
@
4.7_0805_5%~D
4.7_0805_5%~D
1
.
05V_VTTPWRGD <41,52>
603
603
C
C
P
P
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
600
600
L
L
P
P
1 2
606
606
605
605
C
C
C
C
P
P
P
P
1 2
@
@
@
@
22U_0805_6.3V6M
22U_0805_6.3V6M
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V
o
tput voltage ad justable network
u
V
CSA
C
TDC 4.2A
Peak Current 6 A
OCP current 7.2 A
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
12
607
607
C
C
P
P
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
P
P
R
R
100_0402_5%
100_0402_5%
2
P
P
612
@
R
R612
@
0_0402_5%~D
0_0402_5%~D
609
609
608
608
C
C
C
C
P
P
P
P
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
611
611
1
12
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2
1
610
610
2
C
C
P
P
2200P_0402_50V7K
2200P_0402_50V7K
V
C
CSA_SENSE <11>
611
611
612
612
C
C
C
C
P
P
P
P
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
+
V
CCSA_P
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
J
J
P601
P601
P
P
DA_VCCSA
N
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
P602
P602
J
J
PAD-OPEN1x1m
PAD-OPEN1x1m
+
V
CC_SA
12
D
LL CONFIDENTIAL/PROPRIETARY
E
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
T
T
tle
tle
i
i
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
+
+
+
VCC_SA
VCC_SA
CC_SA
V
L
L
L
-7781
A
A
A
-7781
-7781
1
5
5
5
0 6
0 6
0 6
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
+
CCSA_P
V
G
A A
T
HI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
A
5
4
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
5
L
o
cal sense put on HW site
V
C
C_AXG_SENSE<11>
V
S_AXG_SENSE<11>
S
D D
V
UMG+
S
12
707
707
R
R
12
P
P
2.61K_0402_1%
2.61K_0402_1%
12
700
700
H
H
P
P
V
UMG-
S
12
711
711
C
C
P
P
.1U_0402_16V7K
.1U_0402_16V7K
R
R
712
712
P
P
1 2
3.83K_0402_1%
3.83K_0402_1%
C C
+
.05V_RUN_VTT
1
B B
A A
470K_0402_5%_ TSM0B474J4702RE
470K_0402_5%_ TSM0B474J4702RE
H
PROCHOT#<7,41,56>
_
P
P
730 54.9_0402_1%
730 54.9_0402_1%
R
R
12
735 75_0402_5%@
735 75_0402_5%@
R
R
P
P
A
2
1
P
P
R
R
737 130_0402_1%
737 130_0402_1%
12
27.4K_0402_1%
27.4K_0402_1%
S
C
LK
L
ERT#
S
A
D
R
R
P
P
1 2
10KB_0402_5%_ERTJ0ER103J
10KB_0402_5%_ERTJ0ER103J
12
H
H
P
P
715
715
12
P
P
724
@
724
@
R
R
0_0402_5%
0_0402_5%
12
12
12
707
709
709
R
R
P
P
11K_0402_1%
11K_0402_1%
701
701
V
I
DSCLK<10>
V
I
DALERT_N<10>
V
I
DSOUT<10>
5
708
708
707
C
C
P
P
12
719
719
C
C
P
P
.1U_0402_16V7K~D
.1U_0402_16V7K~D
V
S
+
43P_0402_50V8J~D
43P_0402_50V8J~D
C
C
P
P
.1U_0603_16V7K~D
.1U_0603_16V7K~D
UMG-
V_RUN
5
1
05V_0.8V_PWROK<14,41>
.
709
709
C
C
P
P
0.068U_0402_16V7K
0.068U_0402_16V7K
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
0.22U_0402_16V7K~D
1 2
0_0402_5%~D
0_0402_5%~D
716 0_0402_5%
716 0_0402_5%
R
R
P
P
1 2
P
P
718 0_0402_5%
718 0_0402_5%
R
R
1 2
719 0_0402_5%
R
R
719 0_0402_5%
P
P
1 2
721
@
721
@
R
R
P
P
1 2
0_0402_5%~D
0_0402_5%~D
I
VP_VR_ON
M
<40>
R
R
725
725
P
P
1 2
3.83K_0402_1%
3.83K_0402_1%
+
5
V_RUN
V
UM+
S
V
S
UM-
@
@
@
@
@
@
P
P
712
712
C
C
713
713
C
C
P
P
713
713
R
R
P
P
746
746
R
R
P
P
703
703
H
H
P
P
743
743
C
C
P
P
1 2
2.61K_0402_1%
2.61K_0402_1%
.1U_0402_16V7K
.1U_0402_16V7K
330P_0402_50V7K~D
330P_0402_50V7K~D
0.01U_0402_50V7K
0.01U_0402_50V7K
P
P
710
@
710
@
R
R
649_0402_1%~D
649_0402_1%~D
1 2
R
R
711
711
P
P
412_0402_1%
412_0402_1%
1 2
12
12
A
ERT#
L
S
A
D
V
_HOT#
R
P
P
722 0_0402_5%@
722 0_0402_5%@
R
R
1 2
723
@
R
R
723
@
P
P
0_0402_5%~D
0_0402_5%~D
12
P
P
H702
H702
470K_0402_5%_ TSM0B474J4702RE
470K_0402_5%_ TSM0B474J4702RE
727
R
R
727
P
P
27.4K_0402_1%
27.4K_0402_1%
12
P
P
C
O
MP
P
P
1 2
C
C
724
@
724
@
P
P
726
C
C
726
P
P
V
UM-
S
P
P
728
C
C
728
12
12
1
747 11K_0402_1%
747 11K_0402_1%
R
R
P
P
2
10KB_0402_5%_ERTJ0ER103J
10KB_0402_5%_ERTJ0ER103J
12
703
703
PC
PC
@
@
12
706
706
C
C
P
P
1 2
12
I
EN1G
S
I
EN2G
S
N
CG
T
S
LK
C
V
_EN
R
N
T
C
720 10P_0402_50V8J
C
C
720 10P_0402_50V8J
12
732 0_0402_5%@
R
R
732 0_0402_5%@
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
12
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
738
738
739
739
C
C
C
C
P
P
P
P
1 2
649_0402_1%~D
649_0402_1%~D
4
C
C
710
@
710
@
P
P
3300P_0402_50V7K~D
3300P_0402_50V7K~D
P
P
700
U
U
700
1
I
UMPG
S
2
I
EN1G
S
3
I
EN2G
S
4
N
CG
T
5
S
LK
C
6
A
L
ERT#
7
S
D
A
8
V
R
_HOT#
9
V
_ON
R
10
N
T
C
4
1
T
P
12
0.22U_0603_10V7K
0.22U_0603_10V7K
0.082U_0402_16V7K
0.082U_0402_16V7K
740
740
C
C
PR
PR
P
P
365_0402_1%~D
365_0402_1%~D
@
@
P
P
R
R
754
@
754
@
1 2
2200P_0402_25V7K~D
2200P_0402_25V7K~D
4
499_0402_1%~D
499_0402_1%~D
40
39
38
NG
T
R
UMNG
S
I
EN3/FB2
EN2
S
S
I
I
11
12
13
EN2
EN1
EN3
S
S
S
I
I
I
750
750
12
C
C
744
744
P
P
3.32K_0402_1%~N
3.32K_0402_1%~N
P
P
2
OODG
G
P
37
35
36
G
B
F
M2G
MPG
O
OODG
W
P
C
G
P
N
UMP
UMN
EN1
T
S
S
S
I
I
R
I
14
15
16
P
P
702
702
R
R
12
R
R
704
704
P
P
1
470P_0402_50V7K~D
470P_0402_50V7K~D
708
@
708
@
R
R
P
P
I
MVP_PWRGD
1 2
0_0402_5%
0_0402_5%
31
34
33
32
OT1G
ATE1G
ATE1G
ASE1G
O
G
H
G
B
L
P
U
B
O
OT2
U
G
ATE2
P
H
ASE2
L
G
ATE2
V
C
CP
V
D
D
P
W
M3
L
G
ATE1
P
ASE1
H
U
G
ATE1
MP
OT1
OOD
O
G
O
B
B
C
P
F
7
18
20
19
1
ISL95836HRTZ-T_TQFN40_5X5~D
ISL95836HRTZ-T_TQFN40_5X5~D
OOD
R
R
726
@
726
@
P
P
OMP
G
0_0402_5%~D
0_0402_5%~D
P
C
1 2
P
P
2
499_0402_1%~D
499_0402_1%~D
@
@
1
330P_0402_50V7K
330P_0402_50V7K
P
P
C
C
1
0.01U_0402_50V7K
0.01U_0402_50V7K
L
o
cal sense put on HW site
3
R
R
701
701
P
P
2K_0402_1%
2K_0402_1%
R
R
P
P
267K_0402_1%
267K_0402_1%
704
704
C
C
12
30
29
28
27
26
25
24
23
22
21
B
OT1
O
P
P
728 1.91K_0402_1%
728 1.91K_0402_1%
R
R
722
C
C
722
P
P
R
R
736
736
470P_0402_50V7K~D
470P_0402_50V7K~D
1
12
P
P
740
R
R
740
12
2.1K_0402_1%~D
2.1K_0402_1%~D
737
737
C
C
P
P
2
741
741
2
T
HI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A
N
D TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
M
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
330P_0402_50V7K~D
330P_0402_50V7K~D
12
12
703
703
P
P
1 2
68P_0402_50V8J~D
68P_0402_50V8J~D
L
G
P
H
U
G
B
O
B
O
OT2
U
G
ATE2
P
ASE2
H
L
ATE2
G
L
ATE1
G
P
ASE1
H
U
ATE1
G
I
M
VP_PWRGD
12
P
P
R
R
267K_0402_1%
267K_0402_1%
P
P
744
R
R
744
1 2
2K_0402_1%
2K_0402_1%
PC701
PC701
2
1
P
P
702
702
C
C
12
150P_0402_50V8F~D
150P_0402_50V8F~D
C
C
705
705
ATE1G
ASE1G
ATE1G
OT1G
V
CP
C
P
W
M3
+
3.3V_RUN
723
C
PC
723
P
12
47P_0402_50V8J~D
47P_0402_50V8J~D
741
741
12
150P_0402_50V8F~D
150P_0402_50V8F~D
P
P
729
729
C
C
1
680P_0402_50V7K~D
680P_0402_50V7K~D
V
C
CSENSE
V
SSENSE
S
3
12
705
705
R
R
P
P
150K_0402_1%~D
150K_0402_1%~D
P
P
750
750
C
C
0.22U_0603_16V7K
0.22U_0603_16V7K
P
763
PR
R
763
2.2_0603_5%
2.2_0603_5%
714
@
714
@
R
R
P
P
0_0402_5%~D
0_0402_5%~D
1 2
1 2
0_0603_5%
0_0603_5%
1_0603_5%
1_0603_5%
715
715
714
714
C
C
12
12
P
P
PC
PC
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
U
G
ATE2
P
HASE2
B
O
OT2
L
G
ATE2
P
P
742
R
R
742
21K_0402_1%~D
21K_0402_1%~D
727
C
C
727
P
P
1 2
12
2
B
OT1
O
2.2_0603_5%
2.2_0603_5%
L
ATE1
G
D
LL CONFIDENTIAL/PROPRIETARY
E
1 2
12
717
717
R
R
P
P
P
P
720
720
R
R
2
2.2_0603_5%
2.2_0603_5%
U
G
P
HASE1
P
P
749
749
R
R
@
@
P
P
Q
Q
P
P
+
V_ALW
5
12
P
P
R
R
729
729
1 2
1
P
P
0.22U_0603_16V7K
0.22U_0603_16V7K
ATE1
12
1 2
742
742
C
C
P
P
0.22U_0603_16V7K
0.22U_0603_16V7K
5
708
708
4
5
711
Q
711
Q
4
Q
Q
P
P
721
C
C
721
P
P
Q
Q
704
704
4
P
P
706
706
Q
Q
4
2
VCC_GFXCORE
TDC 21.5A Base on PDDG rev 0.95
Peak Current 33A
OCP current 39.6A
Load line -3.9mV/A
5
709
709
PQ
PQ
4
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
123
213
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
700
700
4
P
P
703
703
Q
Q
4
5
5
3
2
123
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
5
710
710
Q
Q
P
P
4
760
760
R
R
213
P
P
4.7_1206_5%
4.7_1206_5%
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
V
CC_core
TDC 32A Base on PDDG rev 0.95
Peak Current 53A
Load line -1.9mV/A
Icc_Dyn_VID1 43A
OCP current 63.6A
5
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
123
5
213
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
@
@
P
P
705
Q
705
Q
4
123
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
P
P
1
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
2
+
5
@
@
701
Q
Q
701
P
P
4
3
5
P
P
702
702
Q
Q
4
213
5
123
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
5
Q
Q
707
707
4
213
+
G
FX_PWR_SRC
12
12
746
746
747
747
C
C
C
C
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
G
1_SW
P
1
751
751
C
C
P
P
2
761
761
680P_0603_50V7K
680P_0603_50V7K
R
R
12
P
P
10K_0603_1%
10K_0603_1%
1 2
@
@
I
V
CC_PWR_SRC
12
716
C716
C
P
P
10U_0805_25V6K
10U_0805_25V6K
R472DP-T1-GE3_POWERPAK8-5~D
R472DP-T1-GE3_POWERPAK8-5~D
I
I
S
S
2
1
12
725
725
C
C
P
P
1
731
731
R
R
P
P
2
4.7_1206_5%
4.7_1206_5%
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
+
V
CC_PWR_SRC
12
12
734
734
C733
C733
C
C
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
12
745
745
C
C
P
P
1
680P_0603_50V7K
680P_0603_50V7K
751
751
R
R
P
P
2
4.7_1206_5%
4.7_1206_5%
R818DP-T1-GE3_POWERPAK8-5
R818DP-T1-GE3_POWERPAK8-5
I
I
S
S
T
T
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
HCB4532KF-800T90_1812
HCB4532KF-800T90_1812
12
1
748
748
C
C
P
P
10U_0805_25V6K
10U_0805_25V6K
758
758
R
R
P
P
1 2
EN1G
S
717
717
C
C
P
P
10U_0805_25V6K
10U_0805_25V6K
680P_0603_50V7K
680P_0603_50V7K
735
735
C
C
P
P
tle
i
i
tle
4
3
3.65K_0603_1%
3.65K_0603_1%
V
S
UMG+
12
I
EN2
S
10K_0603_1%
10K_0603_1%
V
SUM+
3.65K_0603_1%
3.65K_0603_1%
1
2
10U_0805_25V6K
10U_0805_25V6K
I
SEN1
10K_0603_1%
10K_0603_1%
V
S
UM+
3.65K_0603_1%
3.65K_0603_1%
12
749
749
C
C
C752
C752
P
P
P
P
2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
704
704
L
L
P
P
1
G
P
2
12
FBMA-L11-453215-800LMA90T_1812
FBMA-L11-453215-800LMA90T_1812
12
12
718
718
700
700
C
C
C
C
P
P
P
P
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
733
R
R
733
P
P
1 2
R
R
738
738
P
P
1 2
V
UM-
S
1_0402_5%
1_0402_5%
12
754
754
736
736
C
C
C
C
P
P
P
P
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
P
1
752
752
R
R
P
P
1 2
P
P
R
R
755
755
1 2
V
S
UM-
1_0402_5%
1_0402_5%
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
+
+
+
VC
VC
VC
L
L
L
P702
P702
PJ
PJ
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
L
L
@
@
1 2
1_Vo
762
762
759
759
R
R
R
R
P
P
P
P
@
@
1 2
1_0402_5%
1_0402_5%
@
@
1 2
1 2
1
753
753
C
C
P
P
2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
4
3
P
_SW
2
R
R
743
743
P
P
12
12
P
P
L
L
4
3
_SW
P
P
R
R
757
757
12
C_CORE
C_CORE
C_CORE
-7781
-7781
A
A
A
-7781
1
703
703
+
V
CC_GFXCORE
I
EN2G
S
10K_0402_1%
10K_0402_1%
V
S
UMG-
P700
P700
J
J
P
P
PAD-OPEN 1x3m
PAD-OPEN 1x3m
P
P
L700
L
700
P
P
701
701
L
L
1
2
P
2
1
+
+
730
730
C
C
P
P
2
100U_25V_M
100U_25V_M
702
702
1
2
P
1
_Vo
10K_0402_1%
10K_0402_1%
1
+
P
WR_SRC
+
WR_SRC
P
+
V
CC_CORE
_Vo
734
@
734
@
R
R
P
P
10K_0402_1%
10K_0402_1%
1
+
+
731
731
C
C
P
P
2
100U_25V_M
100U_25V_M
+
V
CC_CORE
R
R
753
@
753
@
P
P
12
5
5
5
1 6
1 6
1 61Friday, February 24, 2012
o
o
o
f
f
f
I
EN1
S
12
1
+
+
732
732
C
C
P
P
2
100U_25V_M
100U_25V_M
I
SEN2
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
A
PD1300@
PD1300@
2 1
2AA-13-F
2AA-13-F
ES
ES
Q
Q
1300
1300
P
P
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
8
+
D
C_IN_SS
1 1
E
AC_OK=17.7 Volt
2
PR1313
TI bq24745 = 316K
Intersil ISL88731 = 226K
Maxim = 383K
R
R
P
P
49.9K_0402_1%~D
49.9K_0402_1%~D
P
P
C
C
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
G
N
2 2
Vref
TI bq24747 = 3.3V
Intersil ISL88731C = 3.2V
VDDP
TI bq24747 = 6V
Intersil ISL88731C = 5.1V
3 3
65W
90W
D
Y
N_TUR_CURRNT_SET#
4 4
DA_CHG
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C
ARGER_SMBCLK<41>
H
C
ARGER_SMBDAT<41>
H
DYN_TUR_CURRENT_SET#
High
Low
2
G
G
P
P
Q
Q
1309
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
1309
A
7
5
+
DC_IN
S
M
A
1313
1313
R
R
P
P
1317
1317
1 2
226K_0402_1%~D
226K_0402_1%~D
12
1307
1307
12
1349
1349
R
R
P
P
A
C
+
V_ALW
5
12
P
P
1316
1316
C
C
G
N
DA_CHG
M
A
+
12
1341
1341
R
R
P
P
150K_0402_1%~D
150K_0402_1%~D
12
12
1350
1350
1341
1341
R
R
C
C
P
P
P
P
150K_0402_1%~D
150K_0402_1%~D
66.5K_0402_1%~D
66.5K_0402_1%~D
13
D
D
100P_0402_50V8J~D
100P_0402_50V8J~D
S
S
X8731A_LDO
1310
1310
R
R
P
P
AV_IN<22,41,63>
X8731_IINP<22>
.3V_ALW2
3
12
4
10K_0402_1%~D
10K_0402_1%~D
12
M
1
2
36
PR
1300
@PR1300
@
0_0402_5%~D
0_0402_5%~D
1 2
M
A
@
@
12
1316
1316
R
R
P
P
15.8K_0402_1%~D
15.8K_0402_1%~D
1329
1329
R
R
P
P
@
@
8.45K_0402_1%~D
8.45K_0402_1%~D
AX8731_IINP
X8731_REF
12
1311
1311
R
R
P
P
10K_0402_5%~D
10K_0402_5%~D
1
2
@
@
20K_0402_1%~D
20K_0402_1%~D
12
1323
1323
C
C
P
P
220P_0402_50V8J~D
220P_0402_50V8J~D
1343
1343
R
R
P
P
1 2
D
C
_BLOCK_GC <63>
+
HGR_DC_IN<63>
C
1320
@
1320
@
R
R
P
P
1 2
0_0402_5%~D
0_0402_5%~D
1 2
P
P
@
@
200K_0402_5%~D
200K_0402_5%~D
12
1325
1325
R
R
P
P
@
@
P
P
4.7K_0402_5%~D
4.7K_0402_5%~D
120P_0402_50VNPO~D
120P_0402_50VNPO~D
1 2
12
1324
1324
C
C
P
P
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12
A
apter Protection Circuit for Turbo Mode
d
R
R
C
C
1323
1323
1321
1321
+
5
1340
1340
C
C
P
P
V_ALW
220P_0402_50V8J~D
220P_0402_50V8J~D
@
@
+
D
OCK_PWR_BAR
+
D
12
1325
1325
C
C
P
P
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
1336
1336
C
C
P
P
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C
C_IN_SS
1320
1320
C
C
P
P
@
@
1326
1326
C
C
P
P
1
2
S
S_GC<63>
PD
PD
2
3
BAT54CW_SOT323~D
BAT54CW_SOT323~D
P
P
1309
@
R
R
1309
@
1 2
1_0805_5%~D
1_0805_5%~D
G
DA_CHG
N
1318
@
C
P
P
1318
@
C
12
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2
1
56P_0402_50V8~D
56P_0402_50V8~D
12
1327
1327
C
C
P
P
@
@
1U_0603_10V6K~D
1U_0603_10V6K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12
1337
1337
C
C
P
P
@
@
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
3
+
2
-
B
+S
DC_IN
R
R
1302
@
1302
@
P
P
0_0402_5%~D
0_0402_5%~D
1 2
1302
1302
1
P
P
C
C
1306
1306
0.1U_0805_50V7M~D
0.1U_0805_50V7M~D
@
@
1 2
7.5K_0402_5%~D
7.5K_0402_5%~D
M
X8731_REF
A
@
@
R
R
P
P
1 2
10K_0402_5%~D
10K_0402_5%~D
12
G
1340
R
R
1340
P
P
1.8M_0402_1%
1.8M_0402_1%
1 2
8
U
U
1303A
1303A
P
P
P
1
O
G
LM393DR_SO8~D
LM393DR_SO8~D
4
B
12
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
G
N
DA_CHG
12
M
X8731_IINP
A
1324
1324
R
R
P
P
1327
1327
12
1328
1328
C
C
P
P
@
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DA_CHG
N
+
@
@
+
5
1334
1334
R
R
P
P
1300
1300
C
C
P
P
P
P
1 2
D
V_ALW
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
P
P
C
C
1303
1303
CIN
13
D
D
2
G
G
Q
Q
1302
1302
S
S
SP_1
S
C
12
1304
1304
R
R
P
P
10_0402_5%~D
10_0402_5%~D
0.047U_0603_25V7M~D
0.047U_0603_25V7M~D
P
P
1300
1300
U
U
22
D
C
IN
2
A
C
IN
13
A
OK
C
11
V
DSMB
D
10
S
L
C
9
S
A
D
1
4
N
C
8
V
CM
I
6
F
B
O
5
E
I
A
4
E
A
O
3
V
R
EF
7
C
E
12
G
D
N
2
9
T
P
ISL88731C_QFN28_5X5~D
ISL88731C_QFN28_5X5~D
@
@
1 2
221K_0402_1%~D
221K_0402_1%~D
61
2
C
1300
1300
L
L
P
P
1UH_PCMB053T-1R0MS_7A_20%
S
S
DA_CHG
1310
1310
C
C
P
P
12
1328
R
R1328
P1301
P1301
J
J
+PWR_SRC
Q
Q
P
P
G
G
1
4.7_0603_5%~D
4.7_0603_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1UH_PCMB053T-1R0MS_7A_20%
1303A
1303A
D
D
65
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
S
S
12
1307
1307
R
R
P
P
100K_0402_1%~D
100K_0402_1%~D
1319
1319
R
R
P
P
B
OT_D
O
12
12
1301
1301
D
D
P
P
@
@
BAT54HT1G_SOD323-2~D
BAT54HT1G_SOD323-2~D
C
H
G_UGATE
+
CHGR_B
V
C
G_LGATE
H
+
V
CHGR
12
1338
1338
C
C
P
P
100P_0402_50V8J~D
100P_0402_50V8J~D
R
R
1301
1301
P
P
0.01_1206_1%~D
0.01_1206_1%~D
1
4
3
2
1
D
D
PQ
PQ
1301
1301
2
G
G
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
S
S
3
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
SN_1
S
R1303
R1303
P
P
10K_0402_5%~D
10K_0402_5%~D
1
P
P
0_0402_5%~D
0_0402_5%~D
1307A
1307A
Q
Q
P
P
C
12
1
1305
1305
R
R
P
P
P
P
1304
1304
C
C
2
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
27
28
SP
SN
REF
S
S
I
OUT
C
C
C
C
I
B
OT
O
V
D
DP
U
G
ATE
P
ASE
H
L
ATE
G
P
ND
G
C
S
OP
C
ON
S
V
FB
N
C
G
DA_CHG
N
H
1339
1339
R
R
1307B
1307B
Q
Q
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A
ND
D
E
PARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
1306
1306
R
R
P
P
10_0402_5%~D
10_0402_5%~D
P
P
C
C
1305
1305
100K_0402_1%~D
100K_0402_1%~D
2
1
G
N
I
COUT
26
1318
1318
R
R
P
P
2.2_0603_1%~D
2.2_0603_1%~D
B
O
OT
1 2
25
M
X8731A_LDO
A
21
24
1322
R
R
1322
P
P
23
0_0603_5%~D
0_0603_5%~D
12
P
P
1317
@
C
C
1317
@
220P_0402_50V7K~D
220P_0402_50V7K~D
20
19
18
17
P
P
V
B
F
1 2
1
5
100_0402_5%~D
100_0402_5%~D
6
1
P
P
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
PROCHOT#
_
3
5
4
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PJ
P1300
@PJP1300
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1303B
1303B
Q
Q
P
P
D
D
G
G
3
P
P
@
@
0_0402_5%~D
0_0402_5%~D
1 2
1 2
PC
PC
1311
1311
1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
M
X8731_REF
A
+
DC_IN
12
1335
1335
R
R
P
P
232K_0402_1%~D
232K_0402_1%~D
12
1346
1346
R
R
P
P
22.6K_0402_1%~D
22.6K_0402_1%~D
P
P
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
C
42
R
R
1312
1312
1302
U
U
1302
4
12
12
1301
1301
C
C
P
P
47P_0402_50V8J~D
47P_0402_50V8J~D
D
O
D
O
D
_CSS_GC <63>
K
12
1309
1309
C
C
P
P
1U_0603_10V6K~D
1U_0603_10V6K~D
G
DA_CHG
N
4
12
1319
1319
C
C
P
P
@
@
3300P_0402_50V7K~D
3300P_0402_50V7K~D
P
P
Q
Q
1305
1305
5
4
12
1336
1336
R
R
P
P
47K_0402_1%~D
47K_0402_1%~D
1
1347
1347
R
R
P
P
12
1339
1339
C
C
P
P
2
42.2K_0402_1%~D
42.2K_0402_1%~D
100P_0402_50V8J~D
100P_0402_50V8J~D
+
3
.3V_ALW
1342
1342
C
C
P
P
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
12
5
1
P
B
O
2
A
G
3
T
o
switching from AC to DC.
1302
1302
C
C
P
P
@
@
CK_DCIN_IS+ <39>
CK_DCIN_IS- <39>
5
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
123
123
1M_0402_1%~D
1M_0402_1%~D
1 2
5
6
P
OCHOT_GATE <40>
R
prevent system throtlle when it
CHAGER_SRC
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
M
aximum charging current is 7.2A
1304
1304
Q
Q
P
P
L
L
P
C1322
C
1322
P
P
R
R
1332
1332
P
P
G
NDA_CHG
7
P
P
P
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+
.3V_ALW
3
12
1351
R
R
1351
13
D
D
S
S
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
1 2
P
P
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
12
1000P_0603_50V7K~D
1000P_0603_50V7K~D
4.7_1206_5%~D
4.7_1206_5%~D
1 2
7716ADN-T1-GE3_POWERPAK8-5
7716ADN-T1-GE3_POWERPAK8-5
I
I
S
S
1333
R
R
1333
P
P
+
5
V_ALW
8
U
U
1303B
1303B
P
P
P
+
O
-
G
LM393DR_SO8~D
LM393DR_SO8~D
4
100K_0402_5%~D
100K_0402_5%~D
1301
1301
P
P
C
C
2
G
G
1306
1306
Q
Q
+
V
12
1333
1333
@
@
12
C1312
C1312
P
P
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.01_1206_1%~D
0.01_1206_1%~D
CHGR_L
4
3
1
1330
1330
R
R
2
P
P
10_0402_5%~D
10_0402_5%~D
1
0.22U_0603_25V7K~D
0.22U_0603_25V7K~D
M
A
X8731_REF
12
1338
1338
R
R
P
P
10K_0402_1%~D
10K_0402_1%~D
1
1348
1348
R
R
P
P
2
41.2K_0402_1%~D
41.2K_0402_1%~D
A
AV_IN <41,63>
C
D
12
12
1313
1313
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
R
R
1326
1326
P
P
1
2
1331
1331
R
R
P
P
P
P
C
C
1334
1334
2
P
P
1342
@
R
R
1342
@
0_0402_5%~D
0_0402_5%~D
1 2
D
E
LL CONFIDENTIAL/PROPRIETARY
T
T
Title
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1314
1314
C
C
P
P
10U_0805_25V6K
10U_0805_25V6K
12
1329
1329
C
C
0_0402_5%~D
0_0402_5%~D
P
P
P
P
1335
@
1335
@
C
C
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
C1315
C1315
P
P
10U_0805_25V6K
10U_0805_25V6K
12
1330
1330
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
G
DA_CHG
N
C
C
C
o
o
o
12
+
CHGR
V
12
10U_0805_25V6K
10U_0805_25V6K
A
C
AV_IN_NB <40,41,63>
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
C
C
C
harger
h
h
arger
arger
L
L
L
D
1331
1331
C
C
P
P
-7781
-7781
A
A
A
-7781
1
12
2
PC1332
PC1332
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
5
5
5
2 6
2 6
2 6
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
o
o
f
f
f
1
1
1
0
0
.
.
.
0
5
.3V_ALW2
+3
915
915
C
C
P
P
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
A
AV_IN<41,56>
C
C
HARGE_MODULE_BATT
<40>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
D D
P
P
909
909
Q
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
<40>
M
O
DULE_BATT_PRES#
C
H
ARGE_PBATT
<40>
C C
P
B B
916
D
D
916
P
P
A A
S
ICE_BAT_PRES#
L
Q
+
.3V_ALW2
3
916
916
C
C
P
P
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
P
P
U
U
901
901
1
A
C
AV_IN<41,56>
2
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
P
P
916
916
Q
Q
2
B
AT_PRES#<40>
G
G
D
E
FAULT_OVRDE<40>
12
12
MK0340L-7-F_SOD323-2~D
MK0340L-7-F_SOD323-2~D
SD
SD
2
S
1 2
1
B
2
A
1
D
D
G
G
S
S
3
5
P
B
A
G
3
13
D
D
S
S
L
ICE_BAT_ON<40>
917
917
D
D
P
P
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
961
@
961
@
R
R
P
P
0_0402_5%~D
0_0402_5%~D
O
+VCHGR
5
P
P
902
902
U
U
P
4
O
G
3
12
908
908
PR
PR
10K_0402_5%~D
10K_0402_5%~D
+
V
CHGR
915
915
904
12
@
@
P
P
0_0402_5%~D
0_0402_5%~D
1 2
P
P
915
915
Q
Q
1
1
2
2
2
1
2
5
904
R
R
C
C
P
P
P
P
@
@
1 2
100K_0402_5%~D
100K_0402_5%~D
919
919
R
R
P
P
2
935
935
R
R
+
3
.3V_ALW2
3
3
914
C
C
914
P
P
1500P_0402_7K~D
1500P_0402_7K~D
4
920
920
R
R
P
P
10K_0402_5%~D
10K_0402_5%~D
FDN338P_G_NL_SOT23-3~D
FDN338P_G_NL_SOT23-3~D
1 3
12
900
900
900
900
R
R
C
C
P
P
P
P
@
@
1 2
100K_0402_5%~D
100K_0402_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
906
906
R
R
P
P
10K_0402_5%~D
10K_0402_5%~D
61
904A
904A
Q
Q
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
P
P
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
1
2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
10K_0402_5%~D
10K_0402_5%~D
61
910A
910A
Q
Q
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
@
@
R
R
926
926
P
P
0_0402_5%~D
0_0402_5%~D
1 2
P
B
ATT+
931
931
R
R
P
P
200K_0402_1%~D
200K_0402_1%~D
2
12
938
938
R
R
P
P
@
@
499K_0402_1%~D
499K_0402_1%~D
+
C_IN
D
1
946 100K_0402_5%~D
R
R
946 100K_0402_5%~D
P
P
A
C
AV_DOCK_SRC#< 39>
+
DC_IN
S
A
C
AV_IN<41,56>
+
.3V_ALW2
3
D
CK_SMB_ALERT# <39, 41,47>
O
4
12
61
0_0402_5%~D
0_0402_5%~D
PQ
PQ
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
4
913
913
Q
Q
8
7
5
3
908B
908B
Q
Q
5
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
910
910
D
D
P
P
1 2
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
907A
907A
Q
Q
@
@
P
P
P
P
0_0402_5%~D
0_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
P
P
944 47_0805_5%~D
944 47_0805_5%~D
R
R
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
S
O
FT_START_GC<47>
2
P
P
R
R
951
@
951
@
2
1
D
_BLOCK_GC<56>
C
955
@
955
@
R
R
P
P
1 2
0_0402_5%~D
0_0402_5%~D
R
R
957
@
957
@
P
P
1 2
0_0402_5%~D
0_0402_5%~D
900
900
908A
908A
Q
Q
P
P
911
911
D
D
P
P
5
R
R
936
936
P
B
AT_PRES#<40,47>
910
C
C
910
P
P
@
@
1
0_0402_5%~D
0_0402_5%~D
C
1 2
61
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
3
4
1 2
P
P
R
R
948
948
3301_SDC_IN
D
8
7
5
R
R
916
916
P
P
20K_0402_1%~D
20K_0402_1%~D
20K_0402_1%~D
20K_0402_1%~D
2
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
0_0402_5%~D
0_0402_5%~D
907B
907B
Q
Q
P
P
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
+
12
2
911
911
C
C
P
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
R
R
921
921
P
P
2
@
@
P
P
R
R
932
932
S
L
ICE_BAT_PRES#
<39,40,47>
OCK_PWR_BAR
D
+
C_IN_SS
D
+
HGR_DC_IN<56>
C
C
D
3301_DCIN
A
AVDK_SRC
C
E
C1
R
12
4
M
BATT+
P
12
12
904
904
903
903
R
R
R
R
P
P
P
P
390K_0402_5%~D
390K_0402_5%~D
12
909
909
R
R
P
P
390K_0402_5%~D
390K_0402_5%~D
P
BATT+
12
R913
R913
P
P
390K_0402_5%~D
390K_0402_5%~D
5
12
922
922
R
R
P
@
@
0_0402_5%~D
0_0402_5%~D
1 2
5
915
915
D
D
P
P
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
5
P
P
937
@
937
@
R
R
0_0402_5%~D
0_0402_5%~D
_IN_SS
_PWRBAR
K
C
HGVR_DCIN
D
D
C
33
34
35
C
N
_IN_SS
C
D
ARGERVR_DCIN
H
C
S_GC
_CSS_GC
C3
S
K
R
C
D
E
11
12
13
C2
R
E
C3
12
913
913
C
C
P
P
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
925
925
R
R
P
P
M
P
933
933
R
R
P
P
510K_0402_5%~D
510K_0402_5%~D
1
30
3
32
C
D
N
N
G
_PWRBAR
K
D
K_MOSFET_GC
L
B
L
KNG_MOSFET_GC
B
R_SRC
D
C2
_DCBLK_GC
N
S
R
W
S
E
G
P
16
14
15
S
3
01_PWRSRC
3
BATT+
T
P
390K_0402_5%~D
390K_0402_5%~D
M
12
P
P
R
R
934 100K_0402_5%~D@
934 100K_0402_5%~D@
1 2
M
O
P
2
@
@
R
R
941
941
P
P
0_0402_5%~D
0_0402_5%~D
1
29
28
att+
B
P
0ALW
5
P
ATT_OFF
B
P
_AC_OFF_EN
K
D
CHRG_MOSFET_GC
C
AV_IN_NB
A
S
D
_AC_OFF_EN
K
D
L
_BAT_PRES#
S
B
DK_DCINSS
N
_DK_PWRBAR
3ALW
N
3
E
P
17
18
P
3
3ALW
E
_DK_PWRBAR
N
START_DCBLOCK_GC
0_0402_5%~D
0_0402_5%~D
1 2
61
906A
906A
PQ
PQ
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
912
912
D
D
P
P
1 2
12
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
@
@
0_0402_5%~D
0_0402_5%~D
1 2
@
@
0_0402_5%~D
0_0402_5%~D
1
2
3
4
5
6
7
A
AVIN
C
8
P
3
3ALW2
9
7
3
D
K
4
Q
Q
906B
906B
P
P
913
913
D
D
P
P
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
939
R
R
939
P
P
1 2
1 2
P
P
940 0_0402_5%~D@
R
R
940 0_0402_5%~D@
P
P
943
R
R
943
900
U
U
900
P
P
_IN
C
D
_GC
S
S
R
C1
E
AVDK_SRC
C
A
D
N
G
D
C_IN
S
C_BLK_GC
D
AV_IN
C
A
3ALW2
3
P
P
T
C
S
S_GC<56>
_CSS_GC<56>
912
912
C
C
P
P
3
4
N66D0LDW-7 2N_SOT363-6~D
N66D0LDW-7 2N_SOT363-6~D
M
M
D
D
1 2
1 2
3
905B
905B
Q
Q
P
P
4
1 2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
6
3
10
E
R
12
@
@
0.047U_0603_25V7K~D
0.047U_0603_25V7K~D
P
P
905
905
R
R
820_0603_1%~D
820_0603_1%~D
620K_0402_5%~D
620K_0402_5%~D
1
3
5
PQ
PQ
904B
904B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
12
914
914
R
R
P
P
R
R
917
917
P
P
820_0603_1%~D
820_0603_1%~D
620K_0402_5%~D
620K_0402_5%~D
1 2
3
910B
910B
Q
Q
P
P
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
61
<40>
DULE_ON
O
P
P
905A
905A
Q
Q
N66D0LDW-7 2N_SOT363-6~D
N66D0LDW-7 2N_SOT363-6~D
M
M
D
D
DULE_BATT_PRES# <40,47>
ATT+
B
P
0ALW
5
C
D
_PBATT_OFF
27
26
D
_AC_OFF
K
25
24
23
N
D
G
CD3301ARHHR_QFN36_6X6~D
CD3301ARHHR_QFN36_6X6~D
@
@
1 2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
@
@
P
P
1 2
22
21
20
19
P
P
R
R
959
959
P
P
960
@
R
R
960
@
1 2
R
R
963
963
D
S
1
S
2
S
3
S
4
G
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
PQ
PQ
901
901
2
12
P
P
903
903
C
C
0.01U_0603_25V7K~D
0.01U_0603_25V7K~D
912
Q
P
P
Q
912
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
1
S
D
2
S
D
3
S
D
4
G
D
12
907
907
C
C
P
P
0.01U_0603_25V7K~D
0.01U_0603_25V7K~D
2
12
928
928
R
R
P
P
@
@
499K_0402_1%~D
499K_0402_1%~D
945
@
R
R
945
@
P
P
0_0402_5%~D
0_0402_5%~D
1 2
P
P
947 0_0402_5%~D@
947 0_0402_5%~D@
R
R
1 2
R
R
949 0_0402_5%~D@
949 0_0402_5%~D@
P
P
1 2
3
01_ACAV_IN_NB
3
K
_AC_OFF_EN
L
_BAT_PRES#
+
.3V_ALW
3
E
N
_DOCK_PWR_BAR <40>
1 2
1M_0402_5%~D
1M_0402_5%~D
R
R
962
962
P
P
@
@
+
P
WR_SRC
3
901
901
PR
PR
330K_0402_5%~D
911
911
A
C
V_ALW
S
LICE_BAT_ON <40>
D
CK_AC_OFF <39,41,47>
O
953
953
0_0402_5%~D
0_0402_5%~D
330K_0402_5%~D
1 2
R
R
912
912
P
P
330K_0402_5%~D
330K_0402_5%~D
1 2
AV_IN <41,56>
P
P
954
@
R
R
954
@
1 2
S
ICE_BAT_PRES# <39,40,47>
L
+
BDOCK_DC_IN_SS
N
A
AV_IN_NB <40,41,56>
C
D
8
D
7
D
6
D
5
D
M
P
BATT_IN_SS
8
7
P
BATT_IN_SS
6
5
D
FAULT_OVRDE
E
<40>
12
923
923
R
R
P
P
10K_0402_5%~D
10K_0402_5%~D
P
P
Q
Q
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
13
D
D
2
G
G
S
S
+
5
P
P
@
@
R
R
1 2
0_0402_5%~D
0_0402_5%~D
B
KNG_MOSFET_GC
L
956
@
956
@
R
R
P
P
1 2
0_0402_5%~D
0_0402_5%~D
1 2
958 0_0402_5%~D@
R
R
958 0_0402_5%~D@
P
P
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
2
3
8
D
7
D
6
D
5
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
903
903
D
D
P
P
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
P
P
904
904
D
D
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
2
3
Q
Q
P
P
8
D
7
D
6
D
5
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
D
D
907
907
P
P
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
908
908
PD
PD
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
O
CK_AC_OFF_EC <40>
2
901
901
PD
PD
1
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
P
P
902
902
Q
Q
1
S
2
S
3
S
4
G
12
12
12
910
910
R
R
P
P
499K_0402_1%~D
499K_0402_1%~D
905
905
D
D
P
P
1
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
914
914
1
S
2
S
3
S
4
G
12
12
12
924
924
R
R
P
P
499K_0402_1%~D
499K_0402_1%~D
1 2
1M_0402_5%~D
1M_0402_5%~D
P
P
R
R
952
952
@
@
P
P
0_0402_5%~D
0_0402_5%~D
1 2
+
OCK_PWR_BAR
D
942
942
R
R
1
S2
S2
AA-13-F SMA
AA-13-F SMA
PD902
PD902
2 1
903
903
Q
Q
P
P
8
1
D
S
7
2
D
S
6
3
4
lector
e
e
e
lector
lector
L
L
L
-7781
-7781
A
A
A
-7781
12
902
902
C
C
P
P
0.47U_0805_25V7K~D
0.47U_0805_25V7K~D
@
@
P
P
911
911
R
R
0_0402_5%~D
0_0402_5%~D
S
1 2
T
START_DCBLOCK_GC
+
WR_SRC
P
12
12
905
C906
C906
C
P
P
PC905
P
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
5
5
1
5
3 6
3 6
3 6
o
o
o
f
f
f
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
D
S
5
G
D
FDS6679AZ_G_SO8~D
FDS6679AZ_G_SO8~D
R
R
907
907
P
P
330K_0402_5%~D
330K_0402_5%~D
1 2
D
ELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
ompal Electronics, Inc.
o
o
T
T
tle
i
itle
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
S
S
S
1
1
1
0
.
.
0
0
.
5
CC_CORE
+V
1
P
P
C1000
C1000
10U_080 5_4VAM
10U_080 5_4VAM
2
D D
1
P
P
C
C
1005
1005
10U_080 5_4VAM
10U_080 5_4VAM
2
+
CC_CORE
V
1
C
C
1019
1019
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1043
1043
C
C
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
C C
1
P
P
1060
C
1060
C
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
C
C
1001
1001
P
P
10U_080 5_4VAM
10U_080 5_4VAM
2
1
P
P
C1006
C1006
10U_080 5_4VAM
10U_080 5_4VAM
2
1
P
P
C
C
1020
1020
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
P
P
C1044
C1044
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
C
C
1061
1061
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
P
P
C
C
1002
1002
10U_080 5_4VAM
10U_080 5_4VAM
2
1
C
C
1007
1007
P
P
10U_080 5_4VAM
10U_080 5_4VAM
2
1
C
C
1021
1021
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
P
P
1045
1045
C
C
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1062
1062
C
C
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1003
1003
C
C
P
P
10U_080 5_4VAM
10U_080 5_4VAM
2
1
1008
1008
PC
PC
10U_080 5_4VAM
10U_080 5_4VAM
2
1
P
P
C
C
1022
1022
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
P
P
C1046
C
1046
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1063
C
C
1063
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
4
+V
1
P
P
1004
1004
C
C
10U_080 5_4VAM
10U_080 5_4VAM
2
1
PC
PC
1009
1009
10U_080 5_4VAM
10U_080 5_4VAM
2
1
P
P
1023
1023
C
C
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1053
1053
PC
PC
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
1
1064
1064
C
C
P
P
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
3
CC_CORE +VCC_GFXCORE
+
VCC_GFXCORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
1
C
C
1011
1011
2
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
1
C
C
1035
1035
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
P
P
C
C
+
+
1056
1056
2
22U_0805_6.3V6M
P
P
P
1
2
1
2
P
1
C
C
C
C
1012
1012
1013
1013
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
P
P
1
C
C
C
C
1036
1037
1037
1036
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
P
P
C
C
+
+
1057
1057
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
P
P
1
1
2
1
2
C
C
C
C
1015
1015
1014
1014
2
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
C
C
1038
1038
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
1
1
C
C
1016
1016
2
2
2
1
Below is 458544_CRV_PDDG_0.5 Table 5-8.
5
x 22 µF (0805)
S
o
cket Bottom
5 x (0805) no-stuff
sites
7 x 22 µF (0805)
2 x (0805) no-stuff
sites
+
.05V_RUN _VTT
1
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
@
@
P
P
C
C
1027
1027
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
P
P
C
C
1047
1047
2
1
P
P
P
P
C
C
C
C
1028
1028
1029
1029
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
P
P
P
P
C
C
C
C
1049
1049
1048
1048
2
2
+
.05V_RUN_VTT
1
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
P
P
P
P
C1030
C
C
C
1031
1031
1030
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
P
P
P
P
C
C
C
C1050
1051
1051
1050
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
P
P
C
C
1032
1032
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
@
@
P
P
C
C
1052
1052
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
P
P
C
C
+
+
1065
1065
2
22U_0805_6.3VAM
1
1
@
@
P
P
P
P
C
C
C
C
1033
1033
1034
1034
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
P
P
P
P
C
C
C
C
1054
1054
1055
2
1
+
+
2
1055
2
330U_X_2VM_R6M
330U_X_2VM_R6M
P
P
C
C
1066
1066
22U_0805_6.3VAM
22U_0805_6.3VAM
1
P
P
C
C
1024
1024
2
Socket Top
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
@
@
P
P
P
P
C
C
C
C
1026
1026
1025
1025
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
2
22U_0805_6.3VAM
22U_0805_6.3VAM
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
P
P
1
C
C
P
P
1018
1018
C
C
1017
1017
2
1
P
P
C1068
C1068
22U_080 5_6.3VAM
22U_080 5_6.3VAM
2
+
V
CC_CORE
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
@
@
1
P
P
C
C
+
+
1072
1072
B B
A A
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
PC
PC
+
+
1076
1076
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
P
P
C
C
+
+
1073
1073
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
P
P
C
C
+
+
1077
1077
2
5
470U_D2_2VM_R4.5M
1
P
P
C
C
+
+
1074
1074
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
@
@
1
P
P
C
C
+
+
1075
1075
2
D
E
LL CONFIDENTIAL/PROPRIETARY
T
T
T
itle
i
tle
tle
T
IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H
A
D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
N
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M
Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
4
3
2
i
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
F
r sandy bridge depop PC1267
o
For ivy bridge pop PC1267
C
C
C
mpal Electronics, Inc.
o
o
mpal Electronics, Inc.
mpal Electronics, Inc.
o
PR
PR
PR
CESSOR DECOUPLING
O
O
O
CESSOR DECOUPLING
CESSOR DECOUPLING
L
L
L
-7781
A
A
A
-7781
-7781
1
5
5
5
4 6
4 6
4 6
o
o
o
f
f
f
1
1
1
0
.
.
.
0
0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
Request
Request
Page#
Item
Item Issue Description
ItemItem
Page#
Page#Page#
Title
Title
Title
Title
Date
DateDate
RequestRequest
Owner
Owner
OwnerOwner
4
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Issue DescriptionDate
Issue DescriptionIssue Description
3
Page 1
Page 1
Page 1Page 1
2
Solution Description
Solution Description
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.
Rev.
1
D D
2
3
4
5 45 +5V/3.3V 8/4 Compal DFX concern, choke change from 10*10 to 7*7
6
C C
7
8 51 Vcore/GFX core 8/4
9
1
0 4546+5V/3.3V
1
1
B B
1
2
46 +1.5V_MEN 7/5 Dell Follow VC , enable use SIO_SLP_S4#. Add PR210 for net "SIO_SLP_S4#" X01
4 DCIN 8/4 Dell ME design change. PJPDC1 change from 7pin to 5pin X01
4
4
5 +5V/3.3V 8/4 Compal Main and 2nd IC common setting. De-pop PD100,PR113,PR111 X01
C
1 Vcore/GFX core 8/4
5
4
5
46
46
+5V/3.3V
+1.5V_MEN
5V/3.3V
+
+1.5V_MEN
51,5245Vcore, Charger
+5V/3.3V
+1.5V_MEN
47,4849+1.8V/+1.05VM
+1.05V_VTT
45 +5V/3.3V 8/10
ompal
JimmyCC_Kuo
8/4 Compal
8/4 Compal
C
o
mpal
C
8/8
8/8
8/8
ompal
Justin_Hsu
C
ompal
JimmyCC_Kuo
C
ompal
JimmyCC_Kuo
C
ompal
JimmyCC_Kuo
S
uppress WWAN BB noise.
C
OS concern, change from D2 Polymer cap to OScon cap PC110,PC111 change from 220u polymer cap
P
revent Jitter issue. Add PC120,PC121,PC215 parallel with
P
revent output voltage glitch when power up.
E
MI solution.
S
uppress WWAN BB noise.
S
uppress WWAN BB noise.
S
uppress WWAN BB noise.
P
op PC751,PR760,PC725,PR731,
P
C745,PR751(680pF 0603, 4.7 ohm 1206)
P
L101 change from 3.3u 10*10 to 2.2u 7*7
PL102 change from 3.3u 10*10 to 3.3u 7*7
to 220u OScon cap
PC208 change from 330u polymer cap
to 390u OScon cap
PR101,PR102,PR207
P
U700 VCCP and VDD change form +5V_RUN
t
o +5V_ALW
P
op PL700.PL1300,PL100
P
op PR109,PC112,PR110,PC113,PC209,PR203
(
6
80pF 0603, 4.7 ohm 1206)
P
op PR301(0805),PC305,PR404,PC408,PR504,
P
C
508(680pF 0603, 4.7 ohm 1206)
A
dd PC122,PC123 on +5V_ALWP
a
n
d +3.3V_ALWP
X
1
0
X
01
X
01
X
0145
X
01
X
1
0
X
01
X
01
X
01
F
1
3
45-53 11/16 For cost saving, change the 0ohm resistors to
layout short PAD.
14 44 DCIN 11/30 Compal Reduce power consumption in S5. Add PCH_ALW_ON for +PWR_SRC_S
ootprint change PR100,PR116,PR208,PR210,
PR306,PR403,PR503,PR508,PR513,PR600,PR607,
PR612,PR602,PR604,PR714,PR726,PR713,PR721,
PR723,PR1300,PR1302,PR1312,PR1320,PR1339,
PR1342,PR911,PR925,PR937,PR941,PR932,PR936,
PR926,PR935,PR945,PR947,PR949,PR939,PR940,
PR943,PR948,PR951,PR955,PR957,PR961,PR953,
PR954,PR956,PR958,PR959,PR960,PR963
X
02Compal
X02
enable signal.
A A
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IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
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D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
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Date: Sheet
mpal Electronics, Inc.
P
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P
WR_PIR 1
W
W
R_PIR 1
R_PIR 1
L
L
L
-7781
-7781
A
A
A
-7781
5
5
5
5 6
5 6
5 6
1
1
1
1
0
0
.
.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
o
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Request
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Page#Page#
1
51 VCORE/GFXcore 12/09 Compal Fine tune load line,OCP,transient response.
Title
Title
TitleTitle
Date
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4
Version Change List ( P. I. R. List )
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Issue DescriptionDate
Issue DescriptionIssue Description
3
Page 1
Page 1
Page 1Page 1
2
Solution Description
Solution Description
Solution DescriptionSolution Description
PR740 change from 2K to 2.1K ohm.
P
C740 change from 0.033uF to 0.082uF.
P
R
750 change from 348 to 365 ohm.
1
Rev.
Rev.
Rev.Rev.
X
0
2
PC707 change from 0.022uF to 0.1uF.
PR711 change from 357 to 412 ohm.
P
R702 change from 2.55k to 3.32K ohm.
C C
B B
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IS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
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A
D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
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DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
M
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Y BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
3
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
P
P
P
WR_PIR 2
W
W
R_PIR 2
R_PIR 2
L
L
L
-7781
-7781
A
A
A
-7781
5
5
5
6 6
6 6
6 6
1
1
1
1
0
0
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.
.0
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
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Page#
Page#
Page#Page#
1
Title
Title
TitleTitle
H
W
Date
DateDate
07/11/2011
RequestRequest
Owner
Owner
OwnerOwner
COMPAL42
4
Issue DescriptionDate
Issue DescriptionIssue Description
3
DDR_ON and SUS_ON are replaced by SIO_SLP_S4#E4 uses SIO_SLP_S4# for power control
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.
X
0
1
2
14,39
3
4
24 COMPAL
6 42 HW 07/14/2011 COMPAL Change back to E3 +3.3V/5V_RUN discrete solution X01
H
HW
H
H
07/11/2011
W
07/11/201111
COMPAL
COMPAL Follow INTEL DG
W Add “5@” for touch screen circuit of Dalmore 14” ATG X01
07/11/2011 Change thermal sensor to EMC4021 for UMA5 22 COMPAL X01UMA uses EMC4021 for cost concern
W
SMSC request to delete LPC_LDRQ0#
ATG needs touch screen circuit07/11/2011
Leave LDRQ0# no connection on both of 5048 and PCH side
Change RC99, RC100 from SD034100A8L (S RES 1/16W 10 +-1% 0402) to
SD03410008L (S RES 1/16W 100 +-1% 0402)
Load SW sources output rising time
mismatch and COS. cost concern
7 20 HW 07/14/2011 COMPAL CH94 and CH95 to D2 size for cost concern Change CH94 and CH95 from SGA0000170L to SGA00004L0L
C C
H
W
07/21/2011 COMPAL Vgs less than cut-in voltage in battery mode X01
27,28,42
1
1 H
1
2 R
32 HW 07/25/2011 COMPAL
H
07/25/2011 COMPAL Vgs of 5V MOS maybe large than max rating 10 X01Add R516, R517. Change Q55 from SB00000KQ0L to SB00000GV00
W
W 07/25/2011 COMPAL11 Follow INTEL PDDG 0.8 X01De-pop RC140
ESET_OUT# power sequence issue X01Add R1640, 1M ohms pull down for USH_PWR_STATE# at M/B side
P
p R162~R166 and de-pop U738 29 HW 07/19/2011
o
Add control circuit for +5V_ALW_PCH9 20,42
15 HW 07/25/201113 COMPAL Follow crystal measurement report
B B
4014 HW 07/27/2011 COMPAL Change board ID to X01
C
h
ange R875 to 130Kohms X01
X
0
X01
X
0
X
0
X
0
1
1
1Codec is change to 92HD93COMPAL
1Change CH18 and CH19 to 8.2pF
C
MPAL PCH GPIO52 need 8.2~10K pull up +3.3VS Change R695 from 100K to 10Kohms X01
15 34 HW 07/27/2011
16 23 HW
17 16 HW
0
7
/28/2011 COMPAL Connect pin29 to +3.3V_RUN X01CRT SW 2nd source TI, TS3V713 pin29 is VDD
0
7
/28/2011 COMPAL +1.05V_M turn off before APWROK de-assert Add UH5 circuit for HW solution X01
O
Pop option for 92HD93/ALC290=>R1646/C1164; R1644/R1643; C965/R1642; Q107/R171
18 29
H
W
08/01/2011 COMPAL Co-lay 92HD93 with ALC290
Reserve for ALC290 only: C1204, C1205, R1647, C1165, R1648
X01
Reserve for 92HD93 only: R1645, C963
1
9
20
21 26
A A
2
2
41 Change U4 to RT9801A (threshold adjustable)HW 08/02/2011 COMPAL Reset IC threshold voltage issue X01
2
9 H
W 08/02/2011 COMPAL EMI request to add solution for BITCLK Pop R1076 (33ohms) and C977 (10pF) for PCH_AZ_CODEC_BITCLK X01
H
08/03/2011 COMPAL DPX_CA_DET voltage too low through dongle Change U21 and U24 to SA000055G0L X01
W
17 HW 08/03/2011 X01Pop RH332 for PCH_GPIO3COMPAL Request from INTEL review feedback
D
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ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
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Size Document Number Rev
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Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
E
E
E
P.I.R (1/4)
E
E
E
P.I.R (1/4)
P.I.R (1/4)
L
L
L
-7781
-7781
A
A
A-7781
1
5
5
5
7 6
7 6
7 6
o
o
o
f
f
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1
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0
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0
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.
1Friday, February 24, 2012
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Request
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Page#
Page#
Page#Page#
Title
Title
TitleTitle
Date
DateDate
RequestRequest
Owner
Owner
OwnerOwner
23 42,43 HW 08/04/2011 COMPAL For cost saving
2
4
24, 29, 33 HW
0
8
/08/2011 COMPAL EMI request to add solution
25
26 39
27 43
H
H
08/08/2011 COMPAL RF request to add solution X01
W
08/08/2011 COMPAL White light LED brightness is abnormal Change R934, R938, R939, R949, R958, R957 and R955 to 2.2 Kohms X01
W
4
Issue DescriptionDate
Issue DescriptionIssue Description
3
C
h
ange Q61 to SB00000GV00; HDD and breath LED control share Q84;
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Power team request Q59 change to SB00000L80L
Pop RE678 (22ohms), CE757 (33pF) and C981~3 (0.1uF). Add CE758 (33pF).
Reserve C1206 and C1207.
F
o
r RSMRST# debugCOMPAL08/08/2011HW41 Reserve R1655 and pop R1623 X01
Pop R795 (33ohms), C713 (32pF), RE5 (33ohms), CE3 (32pF), R885 (10ohms)
and C747 (8.2pF)
Rev.
Rev.
Rev.
X01
X01
28
29 17
3
0
C C
31 11 S3 can't resume issue
3
2
3
3
34
35
36
3
7
38
B B
39
40
41
42 40
43 29 HW
4
4
45
4
0 H
W 08/09/2011 COMPAL ESD request add 0.1uF on ALWON Reserve C1208 for ESD backup plan X01
H
W
08/10/2011 COMPAL RF request 10pF on MEC and 5048 PCI CLK Reserve 10pF bypass cap. at CH109 and CH110 X01
18 HW X01De-pop RH270 and RH271. Always pop RH267 and RH26808/11/2011 COMPAL Delete TCM and Non-TPM configuration
H
W 08/12/2011 COMPAL Control 1.5V_VDDQ by EC. Pop RC79 and de-pop RC82 X01
0
8
0 HW
4
14~21 HW Change UH4 to SA00004NQ2L
4
2 HW 08/18/2011 Rated Vgs of Q61 is 25V De-pop R1627 COMPAL
3
6 H
1
9 Change LH1 from 180ohms bead to 1uH inductorHW 08/19/2011 COMPAL CRT ripple garbage display issue
W 08/19/2011 X02COMPAL Follow INTEL DG Change C410~C413 from 0.01uF to 0.1uF
/15/2011 COMPAL X02Change board ID to X02 Change R875 to 62Kohms
0
/15/2011 COMPAL Change PCH to B0 version
8
Change C1163 from 1uF to 2.2uF and codec from WA to WB versionIDT request and codec version change
4
3 H
42 HW 09/02/2011
39 HW
W 08/29/2011 Change R949, R958, R957, R955, R939, R938, R934 from 2.2K to 1.2KohmsCOMPAL To meet current limit resistor of LED spec
C
O
MPAL DMN3030LSS-13 poor soldering issue Change Q55 and Q61 to AO4478L X02
0
9
/02/2011 COMPAL SMSC change 5048 pin A23 to GPIOI0 Re-link ECE 5048 symbol X02
25 HW 09/14/2011 X02De-pop L19~L22. Add L100~107 (9nH) and C1209~C1216 (3.3pF)COMPAL HDMI EMI low cost solution
H
W
09/14/2011 COMPAL Add R1656 and R1657 100Kohms to GND for I2S disabled X02SMSC review feedback
Remove R1648, R1647, R1646, R1645, C1165, C1164, R1643, R1644, R1642,
R171, C1204, C1205
Add snubber on speaker trace with C: 2200pF and R: 3.3ohms.
Change bead rated current from 200mA to 2A.
29
3
3 H
0
/16/2011 COMPAL Remove ALC290 co-lay circuit
9
HW 09/16/2011 COMPAL 15" UMA speaker no sound issue X02
W 09/26/2011 COMPAL EMI request to change SD CLK series R R676 is changed from 33ohms to 10ohms X02
X02
X02
X02
X
0
X02
X02
229 HW 08/29/2011 COMPAL
46 42
A A
47 40
H
W
09/26/2011 COMPAL 1V leakage on +3.3V_RUN during system boot X02Pop Q69 and R929 discharge circuit
H
W
09/26/2011 COMPAL EC has internal pull up for volume signals De-pop R1169, R1197 and R1118 X02
D
ELL CONFIDENTIAL/PROPRIETARY
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ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
E
E
E
P.I.R (2/4)
E
E
E
P.I.R (2/4)
P.I.R (2/4)
L
L
L
-7781
-7781
A
A
A-7781
1
5
5
5
8 6
8 6
8 6
o
o
o
f
f
f
1
1
1
0
0
0
.
.
.
1Friday, February 24, 2012
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1Friday, February 24, 2012
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Request
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Item
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ItemItem
D D
4
Page#
Page#
Page#Page#
8
42
Title
Title
TitleTitle
H
W
Date
DateDate
09/28/2011 COMPAL INTEL timing spec, V2 fail Change C763 to 470pF as that of +3.3V_RUN X02
RequestRequest
Owner
Owner
OwnerOwner
49 41 HW 10/05/2011 COMPAL
50 39 HW 10/05/2011 COMPAL X02Add R771 pulling up to +3.3V_ALW for WIRELESS_ON#/OFF and de-pop R766
51 X02
C
MPAL10/11/2011HW19 Change CH36 from 10uF to 22uFCRT ripple garbage display issue
O
4
Issue DescriptionDate
Issue DescriptionIssue Description
C
hane reset IC to RT9818A-44GU3 X02
3
U
date U4 symbol and add R1629 for backup of inrush prevention.
p
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.
Change RSMRST# pull up with 100Koms. Pop R1655 and de-pop R1623.
When suspend/resume cycles, wireless SW
GPIO IRQs keeps giving
52 X027~42
H
53 HW29
5
4
C C
56 43 HW 10/20/2011
42 X02Change C767 to 470pF, the same as that of +3.3V_RUNHW 10/18/2011 COMPAL +3.3V_SUS sequence timing probelm
57 32 HW 10/24/2011 COMPALTP
5
8
5
9 33 HW COMPAL EMI change to reserve solution for SD/MMCCLK De-pop RE678 and CE757 X0210/25/2011
6
0
42 HW
34 HW 11/04/2011 X02COMPAL PCH GPIO52 changed to be free
61 17,39,40 HW 11/07/2011
62 43 HW 11/07/2011 COMPAL
6
7
B B
69 32
14~21 HW Change UH4 to SA00005BU0L11/07/2011 COMPAL Change PCH to C0 version
H
71 38 HW COMPAL X02
10/11/2011 COMPAL For cost saving Change 0 ohm resistor to short pad
W
Change C973~C976 P/N to SE074222K8L.
Change R1658~R1661 size to 0402.
C
ange R406 from 953ohms to 1.24KohmsCOMPAL Thermal requests to change OTP from 88 to 93
h
C
OMPAL BREATH LED flash issue when AC plugin Add Q126 to control BREATH LED X02
M is changed to AT97SC3204-X2A18-AB U39(TPM) is changed to SA00004WQ10(AT97SC3204-X2A18-AB) for WIN8 support X02
1
/25/2011 COMPAL +3.3/5V_RUN inrush curren issue with 470pF Change C763 and C766 form 470pF to 2200pF X02
0
De-pop R725, remove R695 and add RH359
C
MPAL RF final solution for PCI clock noise X02De-pop R795, C713, R885 and C747. Pop CH109 and CH110 with 12pF
O
C
h
ange current limit resistors of LED X02
W X
1
1
/11/2011
R949 from 2.2K to 1K, R939 from 2.2K to 1.8K, R957 from 2.2K to 220,
R951 from 475 to 330, R953 from 475 to 330 and R958 from 2.2K to 620
C
hange QC3 and Q59 to AO4304L (SB00000RV00)11/07/2011 COMPAL AO4728L leakage issue
Add R1662 0ohm resistor. Reserve D87 and R1663 (pull high to
+3.3V_RUN_TPM) for HW solution backup.
C
ange 1Kohms +-1% to +-5% except RC78, RC80, RC81 and RC84Change 1Kohms tolerance for cost saving11/07/2011HW COMPAL
h
Add RE7~RE24 for DP portD and portCEMI request to add 33ohms for DP port
X
0
X0255 22 HW 10/18/2011
X02
X0268 11,42 HW
0211/07/2011 COMPAL +3.3V_RUN Giltch when AC plugin
X0270
210/11/2011 COMPAL Change C973~C976 P/N and R1658~R1661 size
RC72 from 100K to 330K; RC143 from 330K to 1M; CC136 from 0.1u to 0.022u
X02
R412 from 100K to 470K; R1632 from 1M to 4.7M; C293 from 0.1u to 0.022u
R507 from 100K to 470K; R517 from 1M to 4.7M; C400 from 0.1u to 0.022u
72 HW 11/16/2011 COMPAL
C
h
ange RC value at Gate of MOS Load SW to
modify power rail soft start timing
R722 from 100K to 470K; R1625 from 1M to 4.7M; C644 from 4700p to 220p
R729 from 100K to 470K; R1628 from 1M to 4.7M; C650 from 4700p to 220p
R917 from 100K to 470K; R1617 from 1M to 4.7M; C770 from 4700p to 220p
R920 from 100K to 470K; R1610 from 470K to 2.2M; C771 from 4700p to 470p
A A
R930 from 100K to 470K; R1611 from 470K to 2.2M; C773 from 2200p to 100p
R906 from 100K to 470K; C763 from 2200p to 220p
R912 from 100K to 470K; C766 from 470p to 220p
D
ELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
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o
o
mpal Electronics, Inc.
T
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i
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P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
E
E
E
P.I.R (3/4)
E
E
E
P.I.R (3/4)
P.I.R (3/4)
L
L
L
-7781
-7781
A
A
A-7781
1
5
5
5
9 6
9 6
9 6
o
o
o
f
f
f
1
1
1
0
0
0
.
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
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Item
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ItemItem
D D
7
7
Page#
Page#
Page#Page#
42 COMPAL
Title
Title
TitleTitle
H
W
H
W 11/21/2011
5
6
38 11/29/2011 X02Add bypass resistors, R1672 and R1673; choke L99 for backupHW COMPAL EMI solution for E-Docking USB (port8)
Date
DateDate
11/21/2011 ESD team modify USB3.0 ESD diode package36 COMPAL
RequestRequest
Owner
Owner
OwnerOwner
4
Issue DescriptionDate
Issue DescriptionIssue Description
3
Change RC value at Gate of MOS Load SW to
modify power rail soft start timing
Add USB PWR SW circuit with G547 for JUSB2COMPAL11/23/2011HW36
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
A
dd single channel USB PWR SW U5, G547. Add decoupling cap. C677 and
1
C678 for SW IC input. Add decoupling cap. C652 and C655 at conn. side.
Rev.
Rev.
Rev.
X
X0274 R930 from 470K to 330K; R1611 form 2.2M to 1M
X02
0
273 Change D78 and D79 to NXP IP4292CZ10-TBR(SC300002F0L, Package: XSON10)
Pop C1208 for UMA trace, ALWON
A
d CE10~CE12 for EXP PWR SW signals, CPUSB#, EXPRCRD_CPPE#
d
77 COMPAL11/30/2011HW35 From ESD team request X02
and CARD_RESET#
Add 0ohm resistors, RE27~RE32 and RE34~RE36 to block ESD from XDP
Swap USB Port6 and Port8; reserve a 90ohms choke at E-Docking conn.:
78 Port6 from Mini3 Pink Panther card to E-docking
1
,34,38
7
HW 12/02/2011 COMPAL EMI solution for E-Docking USB port X02
Port8 from E-Docking to Mini3 Pink Panther card
C C
C
ange UH4 to SA00005BU1L14~21 HW 12/05/2011 COMPAL Change PCH to C1 version (QS)
h
X
279
0
80 X02
1 HW 12/07/2011 COMPAL +3.3V_SUS sequence timing R911 from 100K to 470K; R1618 from 1M to 4.7M; C767 from 470p to 220p
8
2 H
83 25 HW
84 41 HW
85
B B
87 14
88 40
89 38
90 14~21,32 HW 02/01/2012 COMPAL A00
91 31 HW 02/01/2012 COMPAL A00
92 15,18,32 HW 02/03/2012
93 14
9
4
A A
9
5
2
4
4
28
43 X02
33 HW 02/20/2012 COMPAL A00
36
HW 12/06/2011 COMPAL EMI solution for USB port12 of camera Pop 90ohms choke, L10; De-pop R427 and R428
W 12/07/2011 COMPAL Add EMI solution Add C1217 with 0.1uF
Pop L100~L107 with 9nH. Change C1209~C1216 from 3.3pF to 1.8pF.
Change R450, R452~R456 and R458~R459 from 680ohms to 604ohms.
SMT request to change F2 footprint
H
H
01/13/2012 COMPAL Change U51 P/N to SA00003TZ2L A00Change MEC5055 P/N for MP
W
01/13/2012 COMPAL System hangs after hot dock (DF531758) A00Change R755 from 100Kohms to 10Kohms
W
Chnage PCH, LAN chip P/N for X-build
C
O
MPAL A00Add 1@ for TPM and 2@ for Non-TPM configAdd BOM config for Non-TPM
H
W
02/16/2012 COMPAL De-pop RH288, RH47, RH48 and RH49 A00De-pop resistor on PCH JTAG for power saving
For SD card reader and KB ESD issue
H
5
02/24/2012 COMPAL Samsung cell phone can't support CDP A00
W
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
For DFX conern of F2 2nd source, SP040003H0L, change F2 footprint to
F_MF-MSMF050-2
C
h
ange R875 to 33KohmsChange board ID to A00COMPAL01/13/2012
A
d X76@ for U52 and U53 A00HW 01/13/2012 COMPAL Add X76@ for ROM part
d
U
4 is changed to SA00005BU3L
H
U31 is changed to SA00003SI5L
c
h
ange SW1 back to E3 solution, ALPS SKRBAAE010Change PWR button, SW1 back to E3 solution
Add 47nF CE13 close to reset input of SD card reader IC
Add 100pF CE14 close to U4.3
Change charging mode to SDP only in S0 Add Q126 and change
R1614 to 100Kohms (reserve this solution and R1614 10kohms)
2
X02
X
0
X
0
X
0
A00HW4086
D
ELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
E
E
E
P.I.R (3/4)
E
E
E
P.I.R (3/4)
P.I.R (3/4)
L
L
L
-7781
-7781
A
A
A-7781
1
6
6
6
0 6
0 6
0 6
o
o
o
f
f
f
212/08/2011 COMPAL EMI final solution for HDMI port
212/08/2011 COMPAL To prevent inrush current at reset IC input Change R1629 from 0ohms to 33ohms resistor
225 HW 12/28/2011 COMPAL
1
1
1
0
0
0
.
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
5
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Title
Item
ItemItem
96 A
D D
9
C C
Page# Rev.
Page#Page#
7 A
TitlePage#
TitleTitle
HW
Date
Date
DateDate
RequestRequest
Owner
Owner
OwnerOwner
C
O
MPAL
4
Issue Description
Issue DescriptionItem
Issue DescriptionIssue Description
3
Ch
ange U2 to Seligo SA00004VH00Samsung cell phone can't support CDP
2
Solution Description
Solution DescriptionSolution Description
Pericom IC fail Change U4 to Richtek SA00005A60L
1
Rev.Solution Description
Rev.Rev.
00COMPAL36 02/24/2012
0041 02/24/2012HW
B B
A A
D
ELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
o
o
o
mpal Electronics, Inc.
P
ROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
T
T
T
tle
i
i
i
tle
tle
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
E
E
E
P.I.R (5/5)
E
E
E
P.I.R (5/5)
P.I.R (5/5)
L
L
L
-7781P
-7781P
A
A
A-7781P
1
6
6
6
1 6
1 6
1 6
o
o
o
f
f
f
0
0
0
3
3
3
.
.
.
1Friday, February 24, 2012
1Friday, February 24, 2012
1Friday, February 24, 2012
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