Compal LA-7731P QAM00 Dalmore 12 UMA, Latitude E6230 Schematic
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-7731P
4319ET31L01
MODEL NAME :
QAM00
GPIO MAP:
2 2
Dalmore 12 UMA
Ivy Bridge + Panther POINT
@
2011-8-30
REV : 0.3 (X01)
@ : Nopop Component
3 3
CONN@ : Connector Component
MB Type BOM P/N
M/B SPI ROM
TAA SPI ROM
SATA re-driver with CD
function
Normal E-SATA re-driver
4 4
MB PCB
MB PCB
Part Number Description
Part Number Description
DA60000P700
DA60000P700
HDMI Royalty@
HDMI Royalty@
Part Number
Part Number
RO0000002HM
RO0000002HM
A
PCB 0FH LA-7731P REV0 M/B UMA
PCB 0FH LA-7731P REV0 M/B UMA
Description
Description
HDMI Royalty
HDMI Royalty
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
5@
6@
7@
8@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-7731P
LA-7731P
LA-7731P
1 59Thursday, September 01, 2011
1 59Thursday, September 01, 2011
1 59Thursday, September 01, 2011
E
0.3
0.3
0.3
Block Diagram
A
B
C
D
E
Memory BUS (DDR3)
1333/1600MHz
1 1
Ivy Bridge
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
LVDS CONN
PAGE 24
CRT CONN
PAGE 45
VGA
2 2
DOCKING
PORT
PAGE 38
DAI
USB
SATA
DOCK LAN
USB30
PCIE5
EXPRESS
Card
PAGE 35 PAGE 34 PAGE 34 PAGE 34 PAGE 32
3 3
USB
CPU ITP Port
PCH ITP Port
1/2 Mini Card
PP
USB
PAGE 7
PAGE 14
WiFi ON/OFF
IO/B
DC/DC Interface
4 4
PAGE 42
Power On/Off
SW & LED
PAGE 30.43
A
For MB/Dock
Video Switch
PI3V713-AZLE
PAGE 23
HDMI CONN
PAGE 25
SDXC/MMC
PAGE 33 PAGE 33
Card reader
O2 Micro OZ600FJ0
PCI Express BUS
PCIE2
WLAN/60GHz
USB
Smart Card
RFID
TDA8034HN
Fingerprint
CONN
PCIE1PCIE3
Full Mini Card
WWAN
USB
Thermal Sensor
FAN
PAGE 22 PAGE 40
EMC4021
Option
SSX44B
BCM5882
FP_USB
USH Module
PAGE 22
B
LVDS
VGA
DPB
DPC
DPD
PCIE x1
LPC BUSChina TPM1.2
USH
USB
BC BUS
BGA CPU
FDI
Lane x 8
INTEL
Panther POINT-M
BGA
SPI
W25Q64CVSSIG
64M 4K sector
W25Q32BVSSIG
32M 4K sector
Discrete TPM
AT97SC3204
SMSC KBC
MEC5055
KB CONNTP CONN
PAGE 41PAGE 41
C
PAGE 6~11
DMI
Lane x 4
USB
PAGE 14~21
SATA
USB POWER SHARE
PCI Express BUS
HD Audio I/F
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PAGE 14
PAGE 14
ST LNG3DM
PAGE 32
SMSC SIO
ECE5048
PAGE 39
BC BUS
BT 4.0
Camera
SATA Repeater
PS8513B
SLG55584A
PAGE 36
HDD
PAGE 28
FFS
PAGE 28
D
PAGE 41
PAGE 24
PAGE 37
USB30
USB30
HDA Codec
92HD93B2
Trough LVDS Cable
E-SATA
USB2.0
USB3.0/2.0
USB3.0/2.0+PS
PAGE 37
PAGE 37
PAGE 36
PAGE 36
Intel Lewisville
82579LM
PAGE 29
DOCK LAN
INT.Speaker
PAGE 29
Combo Jack
DAI
To Docking side
PAGE 45 PAGE 44
LAN SWITCH
PI3L720
Transformer
RJ45
PAGE 44
Dig.
MIC
Trough LVDS Cable
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
UMA Block Diagram
UMA Block Diagram
UMA Block Diagram
LA-7731P
LA-7731P
LA-7731P
E
PAGE 31
PAGE 31
2 59Thursday, September 01, 2011
2 59Thursday, September 01, 2011
2 59Thursday, September 01, 2011
0.3
0.3
0.3
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
USB PORT#
0
1
2
3
4
5
6
7
JUSB1 (Right side )
JUSB2 (Bot side)
NA
MLK DOCK
WLAN
WWAN
JMINI3(PP)
USH->BIO
DESTINATION
DOCKING8
PM TABLE
C C
power
plane
State
S0
S3
+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
+3.3V_M +3.3V_M
+1.05V_M
ON
ON
+1.05V_M
(M-OFF)
ON
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
DESTINATION
HDD
NA
NA
NA
ESATA
Dock
USH
9
10 Express card
11
12
13
0
1
JESATA1 ( Left)
Bluetooth
Camera
NA
BIO
NA
S5 S4/AC
S5 S4/AC don't exist
B B
ON
OFF
OFFOFF
OFF
OFF
ON
need to update Power Status and PM
Table
A A
OFF
OFFOFF
UMA DP/HDMI Port
Port B
Port C
Port D
Connetion
MB HDMI Conn
Dock DP port 2
Dock DP port 1
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 None
DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
Express card
None
1/2vMINI CARD-3 PCIE
MMI
10/100/1G LOM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-7731P
LA-7731P
LA-7731P
3 59Thursday, September 01, 2011
3 59Thursday, September 01, 2011
3 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
4
3
2
1
EN_INVPWR
D D
ADAPTER
1.05V_0.8V_PWROK
+PWR_SRC
BATTERY
C C
CHARGER
FDC654P
(Q21)
ISL95836
(PU700)
+BL_PWR_SRC
+VCC_GFXCORE
HDDC_EN
SI3456BDV
(Q27)
+5V_HDD
ALWON
RT8205
(PU100)
+5V_ALW
MCARD_MISC_PWREN
SI3456
(Q42)
+3.3V_FLASH
MCARD_WWAN_PWREN
SI3456
(Q40)
+3.3V_WWAN
+3.3V_ALW
SIO_SLP_S3#
ISL95836
(PU700)
B B
TPS51212
(PU500)
TPS51212
(PU400)
RT8207
(PU200)
DDR_ON
SY8033
(PU300)
1.05V_VTTPWRGD
TPS51461
(PU600)
AUX_EN_WOWL
SI3456
(Q38)
PCH_ALW_ON
SI3456
(Q49)
SUS_ON
S13456
(Q54)
SIO_SLP_LAN#
SI3456
SIO_SLP_S3#
TPS22966
(Q34) (U78)
SIO_SLP_S3#
SIO_SLP_A#
SI3456
(Q58)
(QC3)
+1.5V_MEM
NTGS4141NAO4728
(Q59)
SIO_SLP_S3#
0.75V_DDR_VTT_ON
+1.8V_RUN
+VCC_SA
+3.3V_WLAN
+3.3V_ALW_PCH
+3.3V_LAN+3.3V_SUS
+3.3V_RUN
+5V_RUN
+3.3V_M
1.05V_0.8V_PWROK
+VCC_CORE
CPU_VTT_ON
SIO_SLP_A#
+1.05V_RUN_VTT +1.05V_M
SIO_SLP_S3#
CPU1.5V_S3_GATE
SI4164
(Q63)
A A
+1.5V_CPU_VDDQ
+1.5V_RUN +0.75V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
+1.05V_RUN
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-7731P
LA-7731P
LA-7731P
4 59Thursday, September 01, 2011
4 59Thursday, September 01, 2011
4 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
B4
A3
B5
A4
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
C8
G12
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
@
@
2.2K
2.2K
2.2K
2.2K
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
SMBUS Address [C8]
127
129
DOCKING
3
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
202
200
202
200
2
DIMMA
DIMMB
53
51
53
51
XDP1
XDP2
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
SMBUS Address [TBD]
1
2.2K
G Sensor
WWAN
+3.3V_RUN
SMBUS Address [3B]
SMBUS Address [TBD]
2.2K
14
13
30
32
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_SUS
+3.3V_ALW
10
9
7
6
M9
L9
7
8
Charger
BATTERY
CONN
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
Express card
SMBUS Address [0x12]
SMBUS Address [TBD]
3
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SMBUS TOPOLOGY
SMBUS TOPOLOGY
SMBUS TOPOLOGY
LA-7731P
LA-7731P
LA-7731P
5 59Thursday, September 01, 2011
5 59Thursday, September 01, 2011
5 59Thursday, September 01, 2011
1
0.3
0.3
0.3
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5065
2B
2B
2.2K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
A A
5
2.2K
5
D D
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
C C
B B
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0< 16>
FDI_FSYNC1< 16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
W11
AC9
W10
AC8
AA11
AC12
AA10
AG8
AD2
AG11
AG4
AC3
AC4
AE11
AC1
AE10
P10
P11
AA6
AA7
AA3
U11
AF3
AF4
AE7
AA4
AE6
4
U1A
U1A
M2
DMI_RX#[0]
P6
DMI_RX#[1]
P1
DMI_RX#[2]
DMI_RX#[3]
N3
DMI_RX[0]
P7
DMI_RX[1]
P3
DMI_RX[2]
DMI_RX[3]
K1
DMI_TX#[0]
M8
DMI_TX#[1]
N4
DMI_TX#[2]
R2
DMI_TX#[3]
K3
DMI_TX[0]
M7
DMI_TX[1]
P4
DMI_TX[2]
T3
DMI_TX[3]
U7
FDI0_TX#[0]
FDI0_TX#[1]
W1
FDI0_TX#[2]
FDI0_TX#[3]
W6
FDI1_TX#[0]
V4
FDI1_TX#[1]
Y2
FDI1_TX#[2]
FDI1_TX#[3]
U6
FDI0_TX[0]
FDI0_TX[1]
W3
FDI0_TX[2]
FDI0_TX[3]
W7
FDI1_TX[0]
T4
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
3
(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
+1.05V_RUN_VTT
12
RC2
RC2
24.9_0402_1%~D
24.9_0402_1%~D
PEG_COMP
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G3
G1
G4
H22
J21
B22
PEG_ICOMPI and RCOMPO signals should be shor ted and routed
D21
A19
with - max leng th = 500 mils - typical imped ance = 43 mohm s
D17
PEG_ICOMPO sign als should be routed with - m ax length = 50 0 mils
B14
- typical imped ance = 14.5 mo hms
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG Compensation
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI Intel(R) FDI
DMI Intel(R) FDI
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
eDP
eDP
2
U1I
U1I
BG17
VSS[181]
BG21
VSS[182]
BG24
VSS[183]
BG28
VSS[184]
BG37
VSS[185]
BG41
VSS[186]
BG45
VSS[187]
BG49
VSS[188]
BG53
VSS[189]
BG9
VSS[190]
C29
VSS[191]
C35
VSS[192]
C40
VSS[193]
D10
VSS[194]
D14
VSS[195]
D18
VSS[196]
D22
VSS[197]
D26
VSS[198]
D29
VSS[199]
D35
VSS[200]
D4
VSS[201]
D40
VSS[202]
D43
VSS[203]
D46
VSS[204]
D50
VSS[205]
D54
VSS[206]
D58
VSS[207]
D6
VSS[208]
E25
VSS[209]
E29
VSS[210]
E3
VSS[211]
E35
VSS[212]
E40
VSS[213]
F13
VSS[214]
F15
VSS[215]
F19
VSS[216]
F29
VSS[217]
F35
VSS[218]
F40
VSS[219]
F55
VSS[220]
G51
VSS[221]
G6
VSS[222]
G61
VSS[223]
H10
VSS[224]
H14
VSS[225]
H17
VSS[226]
H21
VSS[227]
H4
VSS[228]
H53
VSS[229]
H58
VSS[230]
J1
VSS[231]
J49
VSS[232]
J55
VSS[233]
K11
VSS[234]
K21
VSS[235]
K51
VSS[236]
K8
VSS[237]
L16
VSS[238]
L20
VSS[239]
L22
VSS[240]
L26
VSS[241]
L30
VSS[242]
L34
VSS[243]
L38
VSS[244]
L43
VSS[245]
L48
VSS[246]
L61
VSS[247]
M11
VSS[248]
M15
VSS[249]
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
VSS
VSS
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
NCTF
NCTF
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
1
T128 PAD~D@ T128 PA D~D@
eDP Compensation
+1.05V_RUN_VTT
12
RC1
RC1
24.9_0402_1%~D
A A
eDP_COMPIO and ICOMPO signals should be shor ted near
balls and route d with typical impedance <25 mohms
5
24.9_0402_1%~D
EDP_COMP
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (1/6)
Sandy Bridge (1/6)
Sandy Bridge (1/6)
LA-7731P
LA-7731P
LA-7731P
6 59Thursday, September 01, 2011
6 59Thursday, September 01, 2011
6 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
+3.3V_ALW_PCH
CC156 0.1U_0402_25V6K~DCC156 0.1U_0402_25V6K~D
1 2
5
UC2
UC2
1
RUNPWROK<39,40>
+3.3V_ALW_PCH
D D
+1.05V_RUN_VTT
C C
1 2
RC18 200_0402_1%~DRC18 200_0402_1%~D
PM_DRAM_PWR GD<16>
1 2
RC126 56_0402_5%~D@RC126 56_0402_5%~D@
1 2
RC128 49.9_0402_1%~D@RC 128 49.9_0402_1%~D@
1 2
RC44 62_0402_5%~DRC44 62_0402_5%~D
Follow check list 0.5
H_PROCHOT#<40,53,54>
H_THERMTRIP#<22>
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
H_SNB_IVB#<18>
CPU_DETECT#<39>
PECI_EC<40>
1 2
place RC57 near CPU 300mils ~1530mils
RC57 56_0402_5%~DRC57 56_0402_5%~D
1 2
RC129 0_0402_5%~DRC129 0_0402_5%~D
P
B
O
2
A
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
RUN_ON_CPU1.5VS3#<11,42>
H_CATERR#
VR1 TOPOLOGY
H_PROCHOT#_R
H_THERMTRIP#_R
RUNPWROK_AND PM_DRAM_PWR GD_CPU
4
+1.5V_CPU_VDDQ
RC64
39_0402_5%~D
39_0402_5%~D
1 2
13
D
D
QC1
QC1
2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
G
G
S
S
INTEL suggest RC64 and QC1 NO stuff by default
U1B
U1B
F49
PROC_SELECT#
C57
PROC_DETECT#
C49
CATERR#
A48
PECI
C45
PROCHOT#
D45
THERMTRIP#
place RC129 nea r CPU 250mils ~2530 mils
1 2
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWR GD_CPU
PCH_PLTRST#_R
H_PM_SYNC< 16>
H_CPUPWRGD<18>
B B
RC25 1K_0402_5%~DRC25 1K_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
CC141
CC141
2
C48
PM_SYNC
B46
UNCOREPWRGOOD
BE45
SM_DRAMPWR OK
D44
RESET#
EMI request to reserve CC141
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
Buffered reset to CPU
A A
PCH_PLTRST#<17,31,32,33>
1
2
5
+3.3V_RUN
1
5
PCH_PLTRST#_BUF
4
2
UC1
UC1
NC
VCC
A
GND3Y
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
+1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CC140
CC140
RC4
75_0402_1%~D
RC4
75_0402_1%~D
12
1 2
RC10 43_0402_5%~DRC10 43_0402_5%~D
4
12
RC12
RC12
200_0402_1%~D
200_0402_1%~D
1 2
RC28 130_0402_1%~DRC28 130_0402_1%~D
@RC64
@
@
@
MISC THERMAL PWR MANAGEMENT
MISC THERMAL PWR MANAGEMENT
PCH_PLTRST#_R
4
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
3
+3.3V_ALW_PCH
12
RC124
@RC124
@
1K_0402_1%~D
1K_0402_1%~D
SYS_PWROK_XDP
J3
H2
AG3
AG1
N59
N58
AT30
BF44
BE43
BG43
N53
N55
L56
L55
J58
M60
TDI
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
CPU_DMI
CPU_DMI#
CPU_DPLL
CPU_DPLL#
CLK_XDP_ITP
CLK_XDP_ITP#
DDR3_DRAMRST#_CP U
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
BPM#6
BPM#7
1 2
RC13 0_0402_5%~DRC13 0_0402_5%~D
1 2
RC15 0_0402_5%~DRC15 0_0402_5%~D
1 2
RC16 1K_0402_5%~DRC16 1K_0402_5%~D
1 2
RC17 1K_0402_5%~DRC17 1K_0402_5%~D
+1.05V_RUN_VTT
Max 500mils
12
RC26 0_0402_5%~DRC26 0_0402_5%~D
Place T108 close to T107, T109
close to T127 for iFDIM request
T107 PAD~D@ T107 PAD~D@
T127 PAD~D@ T127 PAD~D@
4.99K_0402_1%~D
4.99K_0402_1%~D
For ESD concern, please put near CPU
VCCPWRGOOD_0_R
12
RC130
RC130
10K_0402_5%~D
10K_0402_5%~D
Avoid stub in t he PWRGD path
while placing r esistors RC25 & RC130
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.05V_RUN_VTT
Place near JXDP1
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
12
RC50
RC50
DDR_HVREF_RST_PCH<15>
DDR_HVREF_RST_GATE<40>
XDP_DBRESET#XDP_DBRESET#_R
T108 PAD~D@ T108 PAD~D@
T109 PAD~D@ T109 PAD~D@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
CC65
CC65
2
XDP_DBRESET# <1 4,16>
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
2
SIO_PWRBTN#<14,16,40>
CFG0<9>
SYS_PWROK<16,39>
PCH_PLTRST#<17,31,32,33>
1 2
RC48 0_0402_5%~D@RC48 0_0402_5%~D@
D
S
D
S
13
QC2
QC2
G
G
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
2
1
CC177
CC177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
1 2
RC46 0_0402_5%~DR C46 0_0402_5%~D
1 2
RC47 0_0402_5%~D@RC47 0_0 402_5%~D@
XDP_TDO_R XDP_TDO
12
RC42
RC42
140_0402_1%~D
140_0402_1%~D
RC8 1K_0402_5%~DRC8 1K_0402_5%~D
DDR_HVREF_RST
1 2
RC23 0_0402_5%~DRC23 0_0402_5%~D
1 2
RC24 0_0402_5%~DRC24 0_0402_5%~D
12
RC45
RC45
RC43
RC43
200_0402_1%~D
200_0402_1%~D
25.5_0402_1%~D
25.5_0402_1%~D
2
1 2
RC5 1K_0402_1%~DRC5 1K_0402_1%~D
1 2
RC6 0_0402_5%~DRC6 0_0402_5%~D
1 2
RC7 1K_0402_1%~DRC7 1K_0402_1%~D
1 2
RC9 0_0402_5%~D@RC9 0_0402_5%~D@
1 2
CLK_XDP
CLK_XDP#
DDR3_DRAMRST# <12>
XDP_TDIXDP_TDI_R
12
1
+1.05V_RUN_VTT
JXDP1
@JXDP1
XDP_PREQ#
XDP_PRDY#
H_CPUPWRGD_XDPH_CPUPWRGD
CFD_PWRBTN#_X DP
XDP_HOOK2
SYS_PWROK_XDP
CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCLK
1 2
RH107 0_0402 _5%~DRH107 0_0402_5%~D
1 2
RH106 0_0402 _5%~DRH106 0_0402_5%~D
CLK_XDP_ITP
CLK_XDP_ITP#
DDR_HVREF_RST <12>
M3 control
RH109 0_0402_5%~D@RH109 0_0402_5%~D@
RH108 0_0402_5%~D@RH108 0_0402_5%~D@
1 2
1 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
26
MOLEX_52435-2671
MOLEX_52435-2671
OBSFN_A0
OBSFN_A1
GND
OBSDATA_A[0]
OBSDATA_A[1]
GND
OBSDATA_A[2]
OBSDATA_A[3]
GND
HOOK0
HOOK1
HOOK2
HOOK3
HOOK4
HOOK5
VCCOBS_AB
HOOK6
HOOK7
GND
TDO
TRSTn
TDI
TMS
TCK124GND
GND
GND
TCK0
CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>
@
27
28
PU/PD for JTAG signals
+3.3V_RUN
XDP_DBRESET#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
RC19 1K_0402_1%~DRC19 1K_0402_1%~D
RC27 51_0402_1%~DRC27 51_0402_1%~D
RC29 51_0402_1%~DRC29 51_0402_1%~D
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
RC35 51_0402_1%~DRC35 51_0402_1%~D
RC40
RC40
RC41
RC41
12
12
12
12
12
12
51_0402_1%~D
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
+1.05V_RUN_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (2/6)
Sandy Bridge (2/6)
Sandy Bridge (2/6)
LA-7731P
LA-7731P
LA-7731P
7 59Thursday, September 01, 2011
7 59Thursday, September 01, 2011
7 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
U1C
D D
C C
B B
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#< 12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
U1C
AG6
SA_DQ[0]
AJ6
SA_DQ[1]
AP11
SA_DQ[2]
AL6
SA_DQ[3]
AJ10
SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7]
AR11
SA_DQ[8]
AP6
SA_DQ[9]
AU6
SA_DQ[10]
AV9
SA_DQ[11]
AR6
SA_DQ[12]
AP8
SA_DQ[13]
AT13
SA_DQ[14]
AU13
SA_DQ[15]
BC7
SA_DQ[16]
BB7
SA_DQ[17]
BA13
SA_DQ[18]
BB11
SA_DQ[19]
BA7
SA_DQ[20]
BA9
SA_DQ[21]
BB9
SA_DQ[22]
AY13
SA_DQ[23]
AV14
SA_DQ[24]
AR14
SA_DQ[25]
AY17
SA_DQ[26]
AR19
SA_DQ[27]
BA14
SA_DQ[28]
AU14
SA_DQ[29]
BB14
SA_DQ[30]
BB17
SA_DQ[31]
BA45
SA_DQ[32]
AR43
SA_DQ[33]
AW48
SA_DQ[34]
BC48
SA_DQ[35]
BC45
SA_DQ[36]
AR45
SA_DQ[37]
AT48
SA_DQ[38]
AY48
SA_DQ[39]
BA49
SA_DQ[40]
AV49
SA_DQ[41]
BB51
SA_DQ[42]
AY53
SA_DQ[43]
BB49
SA_DQ[44]
AU49
SA_DQ[45]
BA53
SA_DQ[46]
BB55
SA_DQ[47]
BA55
SA_DQ[48]
AV56
SA_DQ[49]
AP50
SA_DQ[50]
AP53
SA_DQ[51]
AV54
SA_DQ[52]
AT54
SA_DQ[53]
AP56
SA_DQ[54]
AP52
SA_DQ[55]
AN57
SA_DQ[56]
AN53
SA_DQ[57]
AG56
SA_DQ[58]
AG53
SA_DQ[59]
AN55
SA_DQ[60]
AN52
SA_DQ[61]
AG55
SA_DQ[62]
AK56
SA_DQ[63]
BD37
SA_BS[0]
BF36
SA_BS[1]
BA28
SA_BS[2]
BE39
SA_CAS#
BD39
SA_RAS#
AT41
SA_WE#
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
4
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AU36
AV36
AY26
AT40
AU40
BB26
BB40
BC41
AY40
BA41
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12>
3
DDR_B_D[0..63]<13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#< 13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
2
U1D
U1D
AL4
SB_DQ[0]
AL1
SB_DQ[1]
AN3
SB_DQ[2]
AR4
SB_DQ[3]
AK4
SB_DQ[4]
AK3
SB_DQ[5]
AN4
SB_DQ[6]
AR1
SB_DQ[7]
AU4
SB_DQ[8]
AT2
SB_DQ[9]
AV4
SB_DQ[10]
BA4
SB_DQ[11]
AU3
SB_DQ[12]
AR3
SB_DQ[13]
AY2
SB_DQ[14]
BA3
SB_DQ[15]
BE9
SB_DQ[16]
BD9
SB_DQ[17]
BD13
SB_DQ[18]
BF12
SB_DQ[19]
BF8
SB_DQ[20]
BD10
SB_DQ[21]
BD14
SB_DQ[22]
BE13
SB_DQ[23]
BF16
SB_DQ[24]
BE17
SB_DQ[25]
BE18
SB_DQ[26]
BE21
SB_DQ[27]
BE14
SB_DQ[28]
BG14
SB_DQ[29]
BG18
SB_DQ[30]
BF19
SB_DQ[31]
BD50
SB_DQ[32]
BF48
SB_DQ[33]
BD53
SB_DQ[34]
BF52
SB_DQ[35]
BD49
SB_DQ[36]
BE49
SB_DQ[37]
BD54
SB_DQ[38]
BE53
SB_DQ[39]
BF56
SB_DQ[40]
BE57
SB_DQ[41]
BC59
SB_DQ[42]
AY60
SB_DQ[43]
BE54
SB_DQ[44]
BG54
SB_DQ[45]
BA58
SB_DQ[46]
AW59
SB_DQ[47]
AW58
SB_DQ[48]
AU58
SB_DQ[49]
AN61
SB_DQ[50]
AN59
SB_DQ[51]
AU59
SB_DQ[52]
AU61
SB_DQ[53]
AN58
SB_DQ[54]
AR58
SB_DQ[55]
AK58
SB_DQ[56]
AL58
SB_DQ[57]
AG58
SB_DQ[58]
AG59
SB_DQ[59]
AM60
SB_DQ[60]
AL59
SB_DQ[61]
AF61
SB_DQ[62]
AH60
SB_DQ[63]
BG39
SB_BS[0]
BD42
SB_BS[1]
AT22
SB_BS[2]
AV43
SB_CAS#
BF40
SB_RAS#
BD45
SB_WE#
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
1
M_CLK_DDR2
BA34
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AY34
AR22
BA36
BB36
BF27
BE41
BE47
AT43
BG47
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_B_MA[0..15] <13>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (3/6)
Sandy Bridge (3/6)
Sandy Bridge (3/6)
LA-7731P
LA-7731P
LA-7731P
8 59Thursday, September 01, 2011
8 59Thursday, September 01, 2011
8 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
4
3
2
1
CFG Straps for Processor
CFG2
D D
CFG0<7>
+VCC_GFXCORE
1 2
RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
1 2
RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
C C
+VCC_CORE
1 2
RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
1 2
RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
B B
1 2
RC96 1K_0402_1%~D@RC96 1K_0402_1%~D@
1 2
RC97 1K_0402_1%~D@RC97 1K_0402_1%~D@
VAXG_VAL_SENSE
12
RC69
@RC69
@
100_0402_1%~D
100_0402_1%~D
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
12
RC71
@RC71
@
100_0402_1%~D
100_0402_1%~D
VSS_VAL_SENSE
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
EDS 1.0 RSVD_12 -> VCC_DIE_SENSE
T22PAD~D @T22PAD~D @
CFG0
CFG2
CFG4
CFG5
CFG6
CFG7
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
TP_VCC_DIESENSE
U1E
U1E
B50
CFG[0]
C51
CFG[1]
B54
CFG[2]
D53
CFG[3]
A51
CFG[4]
C53
CFG[5]
C55
CFG[6]
H49
CFG[7]
A55
CFG[8]
H51
CFG[9]
K49
CFG[10]
K53
CFG[11]
F53
CFG[12]
G53
CFG[13]
L51
CFG[14]
F51
CFG[15]
D52
CFG[16]
L53
CFG[17]
H43
VCC_VAL_SENSE
K43
VSS_VAL_SENSE
H45
VAXG_VAL_SENSE
K45
VSSAXG_VAL_SENSE
F48
VCC_DIE_SENSE
H48
RSVD6
K48
RSVD7
BA19
RSVD8
AV19
RSVD9
AT21
RSVD10
BB21
RSVD11
BB19
RSVD12
AY21
RSVD13
BA22
RSVD14
AY22
RSVD15
AU19
RSVD16
AU21
RSVD17
BD21
RSVD18
BD22
RSVD19
BD25
RSVD20
BD26
RSVD21
BG22
RSVD22
BE22
RSVD23
BG26
RSVD24
BE26
RSVD25
BF23
RSVD26
BE24
RSVD27
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
RESERVED
RESERVED
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
+DIMM0_1_VREF_CPU
BE7
+DIMM0_1_CA_CPU
BG7
N42
L42
L45
L47
M13
M14
U14
W14
P13
AT49
K24
AH2
AG13
AM14
AM15
N50
TP_DC_TEST_A4
A4
C4
DC_TEST_C4_D3
D3
TP_DC_TEST_D1
D1
TP_DC_TEST_A58
A58
A59
DC_TEST_A59_C59
C59
A61
DC_TEST_A61_C61
C61
TP_DC_TEST_D61
D61
TP_DC_TEST_BD61
BD61
BE61
DC_TEST_BE59_BE61
BE59
BG61
DC_TEST_BG59_BG61
BG59
TP_DC_TEST_BG58
BG58
TP_DC_TEST_BG4
BG4
BG3
DC_TEST_BE3_BG3
BE3
BG1
DC_TEST_BE1_BG1
BE1
TP_DC_TEST_BD1
BD1
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
T121 PAD~D@ T121 PA D~D@
T118 PAD~D@ T118 PA D~D@
T119 PAD~D@ T119 PA D~D@
T120 PAD~D@ T120 PA D~D@ RC53
T122 PAD~D@ T122 PA D~D@
T132 PAD~D@ T132 PA D~D@
T123 PAD~D@ T123 PA D~D@
T124 PAD~D@ T124 PA D~D@
PCIE Port Bifurcation Straps
connected to the Embedded Display Port
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG4
CFG6
CFG5
RC54
@ RC54
@
1K_0402_1%~D
1K_0402_1%~D
12
@ RC51
@
1K_0402_1%~D
1K_0402_1%~D
12
@ RC52
@
1K_0402_1%~D
1K_0402_1%~D
12
12
RC51
RC52
@ RC53
@
1K_0402_1%~D
1K_0402_1%~D
CFG7
12
@ RC56
@
1K_0402_1%~D
1K_0402_1%~D
RC56
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (4/6)
Sandy Bridge (4/6)
Sandy Bridge (4/6)
LA-7731P
LA-7731P
LA-7731P
9 59Thursday, September 01, 2011
9 59Thursday, September 01, 2011
9 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
4
3
2
1
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
W16
W17
BC22
AM25
AN22
A44
B43
C44
F43
G43
AN16
AN17
8.5A
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
Note: Place the PU resistors close to CPU
RC61 close to C PU 300 - 1500m ils
1 2
RC140 0_0402_5%~D@RC140 0_0402_5%~D@
+1.05V_RUN_VTT
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCSENSE_R
VSSSENSE_R
H_CPU_SVIDALRT#
+3.3V_RUN
@ RC141
@
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC573
CC573
2
VIDSCLK <53>
Place RC66, RC70 ,RC133near CPU
1 2
RC67 0_0402_5%~DRC67 0_0402_5%~D
1 2
RC68 0_0402_5%~DRC68 0_0402_5%~D
RC133 10_0402_1%~DRC133 10_0402_1%~D
1 2
1 2
RC61 43_0402_5%~DRC61 43_0402_5%~D
VCCP_PWRCTRL Pull high on power side
CAD Note: Place the PU
RC141
10K_0402_5%~D
10K_0402_5%~D
VCCP_PWRCTR L <51>
+1.05V_RUN_VTT
12
RC63
RC63
130_0402_1%~D
130_0402_1%~D
resistors close to CPU
RC63 close to C PU 300 - 1500m ils
VIDSOUT <53>
RC75
@RC75
@
100_0402_1%~D
100_0402_1%~D
1 2
RC98
RC98
12
10_0402_1%~D
10_0402_1%~D
+1.05V_RUN_VTT
VTT_SENSE <51>
VSSIO_SENSE_R <5 1>
Place RC98 close to CPU
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
RC60
RC60
75_0402_1%~D
75_0402_1%~D
+VCC_CORE
12
12
2
RC66
RC66
100_0402_1%~D
100_0402_1%~D
VCCSENSE <53>
VSSSENSE <53>
RC70
RC70
100_0402_1%~D
100_0402_1%~D
VIDALERT_N <53>
Iccmax current changed for PD DG Rev0.7
CPU Power Rail Table
Voltage Rail
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM 1.5
Description
*
5A to Mem contr oller(+1.5V_CP U_VDDQ)
5-6A to 2 DIMMs /channel
2-5A to +1.5V_R UN & +0.75V_DD R_VTT
Voltage
0.65-1.3
1.05/1
0.0-1.1
1.8
1.5
0.65-0.9
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (5/6)
Sandy Bridge (5/6)
Sandy Bridge (5/6)
LA-7731P
LA-7731P
LA-7731P
1
S0 Iccmax
Current (A)
10 59Thursday, September 01, 2011
10 59Thursday, September 01, 2011
10 59Thursday, September 01, 2011
53
8.5
33
1.2
5
6
12-16
*
0.3
0.3
0.3
POWER
U1F
53A
U1F
A26
VCC[1]
A29
VCC[2]
A31
VCC[3]
A34
VCC[4]
A35
VCC[5]
A38
VCC[6]
A39
VCC[7]
A42
VCC[8]
C26
VCC[9]
C27
VCC[10]
C32
VCC[11]
C34
VCC[12]
C37
VCC[13]
C39
VCC[14]
C42
VCC[15]
D27
VCC[16]
D32
VCC[17]
D34
VCC[18]
D37
VCC[19]
D39
VCC[20]
D42
VCC[21]
E26
VCC[22]
E28
VCC[23]
E32
VCC[24]
E34
VCC[25]
E37
VCC[26]
E38
VCC[27]
F25
VCC[28]
F26
VCC[29]
F28
VCC[30]
F32
VCC[31]
F34
VCC[32]
F37
VCC[33]
F38
VCC[34]
F42
VCC[35]
G42
VCC[36]
H25
VCC[37]
H26
VCC[38]
H28
VCC[39]
H29
VCC[40]
H32
VCC[41]
H34
VCC[42]
H35
VCC[43]
H37
VCC[44]
H38
VCC[45]
H40
VCC[46]
J25
VCC[47]
J26
VCC[48]
J28
VCC[49]
J29
VCC[50]
J32
VCC[51]
J34
VCC[52]
J35
VCC[53]
J37
VCC[54]
J38
VCC[55]
J40
VCC[56]
J42
VCC[57]
K26
VCC[58]
K27
VCC[59]
K29
VCC[60]
K32
VCC[61]
K34
VCC[62]
K35
VCC[63]
K37
VCC[64]
K39
VCC[66]
K42
VCC[67]
L25
VCC[68]
L28
VCC[69]
L33
VCC[70]
L36
VCC[71]
L40
VCC[72]
N26
VCC[73]
N30
VCC[74]
N34
VCC[75]
N38
VCC[76]
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
4
+VCC_CORE
D D
C C
B B
A A
5
POWER
CORE SUPPLY
CORE SUPPLY
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
PEG IO AND DDR IO
PEG IO AND DDR IO
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO50
VCCIO51
VCCIO_SEL
VCCPQE[1]
VCCPQE[2]
RAILS
RAILS
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID QUIET
SENSE LINES SVID QUIET
5
12
RC74
RC74
100K_0402_5%~D
QC4A
QC4A
2
12
RC99
RC99
100_0402_1%~D
100_0402_1%~D
12
RC100
RC100
100_0402_1%~D
100_0402_1%~D
1
1
2
2
100K_0402_5%~D
61
+1.8V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC264
CC264
1
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
1
CC176
CC176
+
+
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC262
CC262
CC263
CC263
1
2
5
RUN_ON_CPU1.5VS3# <7,42>
RC76
100_0402_1%~D
100_0402_1%~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC174
CC174
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
+1.5V_CPU_VDDQ Source
VCC_AXG_SENSE<53>
VSS_AXG_SENSE<53>
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC170
CC170
2
2
5
1 2
RC82 0_0402_5%~D@RC82 0_0402_5%~D@
1 2
RC79 0_0402_5%~DRC79 0_0402_5%~D
+VCC_GFXCORE
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC183
CC183
CC168
CC168
CC169
CC169
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CPU1.5V_S3_GATE<40>
SIO_SLP_S3#<16,35,39,42,49>
+VCC_SA
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
CC172
CC172
+
+
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC171
CC171
2
D D
C C
B B
A A
12
RC72
RC72
100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3
3
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
QC4B
QC4B
4
@RC76
@
12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC175
CC175
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC260
CC260
CC261
CC261
1
2
4
+1.5V_MEM +1.5V_CPU_VDDQ+3.3V_ALW2 +PWR_SRC_S
8
7
6
5
330K_0402_1%~D
330K_0402_1%~D
12
RC143
RC143
+VCC_GFXCORE
1.2A
6A
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4
QC3
QC3
AO4728L_SO8~D
AO4728L_SO8~D
U1G
U1G
33A
AA46
VAXG[1]
AB47
VAXG[2]
AB50
VAXG[3]
AB51
VAXG[4]
AB52
VAXG[5]
AB53
VAXG[6]
AB55
VAXG[7]
AB56
VAXG[8]
AB58
VAXG[9]
AB59
VAXG[10]
AC61
VAXG[11]
AD47
VAXG[12]
AD48
VAXG[13]
AD50
VAXG[14]
AD51
VAXG[15]
AD52
VAXG[16]
AD53
VAXG[17]
AD55
VAXG[18]
AD56
VAXG[19]
AD58
VAXG[20]
AD59
VAXG[21]
AE46
VAXG[22]
N45
VAXG[23]
P47
VAXG[24]
P48
VAXG[25]
P50
VAXG[26]
P51
VAXG[27]
P52
VAXG[28]
P53
VAXG[29]
P55
VAXG[30]
P56
VAXG[31]
P61
VAXG[32]
T48
VAXG[33]
T58
VAXG[34]
T59
VAXG[35]
T61
VAXG[36]
U46
VAXG[37]
V47
VAXG[38]
V48
VAXG[39]
V50
VAXG[40]
V51
VAXG[41]
V52
VAXG[42]
V53
VAXG[43]
V55
VAXG[44]
V56
VAXG[45]
V58
VAXG[46]
V59
VAXG[47]
W50
VAXG[48]
W51
VAXG[49]
W52
VAXG[50]
W53
VAXG[51]
W55
VAXG[52]
W56
VAXG[53]
W61
VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]
F45
VAXG_SENSE
G45
VSSAXG_SENSE
BB3
VCCPLL[1]
BC1
VCCPLL[2]
BC4
VCCPLL[3]
L17
VCCSA[1]
L21
VCCSA[2]
N16
VCCSA[3]
N20
VCCSA[4]
N22
VCCSA[5]
P17
VCCSA[6]
P20
VCCSA[7]
R16
VCCSA[8]
R18
VCCSA[9]
R21
VCCSA[10]
U15
VCCSA[11]
V16
VCCSA[12]
V17
VCCSA[13]
V18
VCCSA[14]
V21
VCCSA[15]
W20
VCCSA[16]
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
3
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2
3
4
0.1U_0603_50V7K~D
0.1U_0603_50V7K~D
1
CC136
CC136
2
20K_0402_5%~D
20K_0402_5%~D
12
@
@
RC73
RC73
CC135
CC135
1
2
POWER
POWER
VREF
VREF
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
VCCSA VID
VCCSA VID
SM_VREF
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
VCCDQ[1]
VCCDQ[2]
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
SENSE LINES
SENSE LINES
VCCSA_VID[0]
VCCSA_VID[1]
lines
lines
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
+V_SM_VREF_CNT
+V_SM_VREF_CNT
AY43
+V_SM_VREF should
have 10 mil trace width
5A
+1.5V_CPU_VDDQ
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
3
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
AM28
AN26
BC43
BA43
U10
D48
D49
1
2
1
2
+1.5V_CPU_VDDQ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D
12
CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D
12
CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D
12
CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D
12
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC180
CC180
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC251
CC251
10U_0603_6.3V6M~D
1
CC161
CC161
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC252
CC252
1
2
VCCSA_VID_0 <52>
VCCSA_VID_1 <52>
CC162
CC162
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC181
CC181
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC250
CC250
1
2
CC574
CC574
VCCSA_SENSE <52>
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC253
CC253
+1.5V_CPU_VDDQ
RC84
RC84
RC78
RC78
1
CC163
CC163
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC254
CC254
1
2
2
U1H
U1H
1K_0402_1%~D
1K_0402_1%~D
12
1K_0402_1%~D
1K_0402_1%~D
12
6A
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC165
CC165
CC164
CC164
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC255
CC255
1
1
2
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC256
CC256
CC167
CC167
CC166
CC166
+
+
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC257
CC257
1
2
CC259
CC259
CC258
CC258
1
1
2
2
A13
VSS[1]
A17
VSS[2]
A21
VSS[3]
A25
VSS[4]
A28
VSS[5]
A33
VSS[6]
A37
VSS[7]
A40
VSS[8]
A45
VSS[9]
A49
VSS[10]
A53
VSS[11]
A9
VSS[12]
AA1
VSS[13]
AA13
VSS[14]
AA50
VSS[15]
AA51
VSS[16]
AA52
VSS[17]
AA53
VSS[18]
AA55
VSS[19]
AA56
VSS[20]
AA8
VSS[21]
AB16
VSS[22]
AB18
VSS[23]
AB21
VSS[24]
AB48
VSS[25]
AB61
VSS[26]
AC10
VSS[27]
AC14
VSS[28]
AC46
VSS[29]
AC6
VSS[30]
AD17
VSS[31]
AD20
VSS[32]
AD4
VSS[33]
AD61
VSS[34]
AE13
VSS[35]
AE8
VSS[36]
AF1
VSS[37]
AF17
VSS[38]
AF21
VSS[39]
AF47
VSS[40]
AF48
VSS[41]
AF50
VSS[42]
AF51
VSS[43]
AF52
VSS[44]
AF53
VSS[45]
AF55
VSS[46]
AF56
VSS[47]
AF58
VSS[48]
AF59
VSS[49]
AG10
VSS[50]
AG14
VSS[51]
AG18
VSS[52]
AG47
VSS[53]
AG52
VSS[54]
AG61
VSS[55]
AG7
VSS[56]
AH4
VSS[57]
AH58
VSS[58]
AJ13
VSS[59]
AJ16
VSS[60]
AJ20
VSS[61]
AJ22
VSS[62]
AJ26
VSS[63]
AJ30
VSS[64]
AJ34
VSS[65]
AJ38
VSS[66]
AJ42
VSS[67]
AJ45
VSS[68]
AJ48
VSS[69]
AJ7
VSS[70]
AK1
VSS[71]
AK52
VSS[72]
AL10
VSS[73]
AL13
VSS[74]
AL17
VSS[75]
AL21
VSS[76]
AL25
VSS[77]
AL28
VSS[78]
AL33
VSS[79]
AL36
VSS[80]
AL40
VSS[81]
AL43
VSS[82]
AL47
VSS[83]
AL61
VSS[84]
AM13
VSS[85]
AM20
VSS[86]
AM22
VSS[87]
AM26
VSS[88]
AM30
VSS[89]
AM34
VSS[90]
IVY-BRIDGE_BGA1023~D
IVY-BRIDGE_BGA1023~D
VSS
VSS
1
AM38
VSS[91]
AM4
VSS[92]
AM42
VSS[93]
AM45
VSS[94]
AM48
VSS[95]
AM58
VSS[96]
AN1
VSS[97]
AN21
VSS[98]
AN25
VSS[99]
AN28
VSS[100]
AN33
VSS[101]
AN36
VSS[102]
AN40
VSS[103]
AN43
VSS[104]
AN47
VSS[105]
AN50
VSS[106]
AN54
VSS[107]
AP10
VSS[108]
AP51
VSS[109]
AP55
VSS[110]
AP7
VSS[111]
AR13
VSS[112]
AR17
VSS[113]
AR21
VSS[114]
AR41
VSS[115]
AR48
VSS[116]
AR61
VSS[117]
AR7
VSS[118]
AT14
VSS[119]
AT19
VSS[120]
AT36
VSS[121]
AT4
VSS[122]
AT45
VSS[123]
AT52
VSS[124]
AT58
VSS[125]
AU1
VSS[126]
AU11
VSS[127]
AU28
VSS[128]
AU32
VSS[129]
AU51
VSS[130]
AU7
VSS[131]
AV17
VSS[132]
AV21
VSS[133]
AV22
VSS[134]
AV34
VSS[135]
AV40
VSS[136]
AV48
VSS[137]
AV55
VSS[138]
AW13
VSS[139]
AW43
VSS[140]
AW61
VSS[141]
AW7
VSS[142]
AY14
VSS[143]
AY19
VSS[144]
AY30
VSS[145]
AY36
VSS[146]
AY4
VSS[147]
AY41
VSS[148]
AY45
VSS[149]
AY49
VSS[150]
AY55
VSS[151]
AY58
VSS[152]
AY9
VSS[153]
BA1
VSS[154]
BA11
VSS[155]
BA17
VSS[156]
BA21
VSS[157]
BA26
VSS[158]
BA32
VSS[159]
BA48
VSS[160]
BA51
VSS[161]
BB53
VSS[162]
BC13
VSS[163]
BC5
VSS[164]
BC57
VSS[165]
BD12
VSS[166]
BD16
VSS[167]
BD19
VSS[168]
BD23
VSS[169]
BD27
VSS[170]
BD32
VSS[171]
BD36
VSS[172]
BD40
VSS[173]
BD44
VSS[174]
BD48
VSS[175]
BD52
VSS[176]
BD56
VSS[177]
BD8
VSS[178]
BE5
VSS[179]
BG13
VSS[180]
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (6/6)
Sandy Bridge (6/6)
Sandy Bridge (6/6)
LA-7731P
LA-7731P
LA-7731P
11 59Thursday, September 01, 2011
11 59Thursday, September 01, 2011
11 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
+V_DDR_REFA_M3
+V_DDR_REF
D D
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
All VREF traces should
have 10 mil trace width
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
C C
Layout Note:
Place near JDIMM1
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD3
CD3
2
+1.5V_MEM
B B
A A
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD7
CD7
1
1
2
2
Layout Note:
Place near JDIMM1.203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD17
CD17
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD4
CD4
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD8
CD8
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD18
CD18
2
1
CD5
CD5
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD9
CD9
CD10
CD10
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD19
CD19
2
2
5
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD6
CD6
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@CD13
@
CD11
CD11
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD20
CD20
1
CD51
CD51
CD13
1
+
+
2
2
330U_SX_2VY~D
330U_SX_2VY~D
CD14
CD14
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
1 2
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
4
1 2
RD7 0_0402_5%~DRD7 0_0402_5 %~D
1 2
RD1 0_0402_5%~DRD1 0_0402_5 %~D
+3.3V_RUN
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
DDR_CKE0_DIMMA<8>
DDR_CS1_DIMMA#<8>
4
3
JDIMM1
JDIMM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
TYCO_2-2013022-1
TYCO_2-2013022-1
CONN@
CONN@
H=4mm
2-3A to 1 DIMMs/channel
+1.5V_MEM+1.5V_MEM
2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR3_DRAMRST#_R
DDR_A_D14
DDR_A_D15
DDR_A_D20DDR_A_D16
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.75V_DDR_VTT
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 < 8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
M_ODT0 <8>
M_ODT1 <8>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
+DIMM1_VREF_DQ
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
DDR_A_D0
DDR_A_D1
CD2
CD2
1
CD1
CD1
2
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
CD21
CD21
2
2
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD22
CD22
+0.75V_DDR_VTT
2
+DIMM0_1_VREF_CPU
DDR_HVREF_RST<7>
+DIMM0_1_CA_CPU
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
+DIMM1_VREF_CA
RD11 0_0402_5%~DR D11 0_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CD16
CD15
CD15
1
2
DDR_XDP_WAN_ SMBDAT <13,15,27,34>
DDR_XDP_WAN_ SMBCLK <13,15,27,34>
CD16
1
2
2
1
+1.5V_MEM
12
RD27
RD27
1K_0402_1%~D
1K_0402_1%~D
DDR3_DRAMRST#_R
DDR_HVREF_RST
DDR_HVREF_RST
12
1 2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
RD29 0_0402_5%~D@RD29 0_0402_5%~D@
1 2
QD1
QD1
D
S
D
S
BSS138-G_SOT23-3
BSS138-G_SOT23-3
13
G
G
2
RD30 0_0402_5%~D@RD30 0_0402_5%~D@
1 2
QD2
QD2
D
S
D
S
BSS138-G_SOT23-3
BSS138-G_SOT23-3
13
G
G
2
+V_DDR_REF
DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-7731P
LA-7731P
LA-7731P
1
+V_DDR_REFA_M3
+V_DDR_REFB_M3
12 59Thursday, September 01, 2011
12 59Thursday, September 01, 2011
12 59Thursday, September 01, 2011
0.3
0.3
0.3
5
D D
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
C C
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD25
CD25
2
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
B B
A A
10U_0603_6.3V6M~D
CD29
CD29
CD30
CD30
1
1
2
2
Layout Note:
Place near JDIMM2.203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD39
CD39
2
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD26
CD26
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD31
CD31
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD40
CD40
2
2
5
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD28
CD28
CD27
CD27
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD34
CD32
CD32
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD41
CD41
CD34
CD33
CD33
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD42
CD42
2
All VREF traces should
have 10 mil trace width
330U_SX_2VY~D
330U_SX_2VY~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@CD35
@
1
CD36
CD36
CD35
1
+
+
2
2
4
+V_DDR_REFB_M3
+V_DDR_REF
4
+DIMM2_VREF_DQ
1 2
RD8 0_0402_5%~DRD8 0_0402_5 %~D
1 2
RD4 0_0402_5%~DRD4 0_0402_5 %~D
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
+3.3V_RUN
RD5 10K_04 02_5%~DRD5 10K_0402_5%~D
12
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CD23
CD23
2
+3.3V_RUN
3
+1.5V_MEM +1.5V_MEM
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CD24
CD24
1
2
DDR_CKE2_DIMMB<8>
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
DDR_CS3_DIMMB#<8>
10K_0402_5%~D
10K_0402_5%~D
12
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+0.75V_DDR_VTT +0.75V_DDR_VTT
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
RD6
RD6
CD43
CD43
1
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
CD44
CD44
2
H=4mm
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013287-1
TYCO_2-2013287-1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
2
2-3A to 1 DIMMs/channel
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
2
DDR3_DRAMRST#_R <12>
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 < 8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <8>
M_ODT3 <8>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CD37
CD37
2
DDR_XDP_WAN_ SMBDAT <12,15,27,34>
DDR_XDP_WAN_ SMBCLK <12,15,27,34>
1
JDIMMB Reverse Type
+DIMM2_VREF_CA
12
RD15 0_0402_5%~DR D15 0_0402_5%~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CD38
CD38
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-7731P
LA-7731P
LA-7731P
+V_DDR_REF
13 59Thursday, September 01, 2011
13 59Thursday, September 01, 2011
13 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
CMOS settingCMOS_CLR1
Open
ME_CLR1
Shunt
Open
+RTC_CELL
D D
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
Low - Enable External VRs
Clear CMOSShunt
Keep CMOS
TPM setting
Clear ME RTC Registers
Keep ME RTC Registers
12
RH38
RH38
330K_0402_1%~D
330K_0402_1%~D
PCH_INTVRMEN
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
+3.3V_ALW_PCH
12
RH66
RH66
1K_0402_1%~D
1K_0402_1%~D
PCH_AZ_SYNC
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
*
+RTC_CELL
1
@
@
ME1 SHORT PADS~D
ME1 SHORT PADS~D
PCH_AZ_CODEC_SDOUT<29>
PCH_AZ_CODEC_SYNC<29>
PCH_AZ_CODEC_RST#<29>
PCH_AZ_CODEC_BITCLK<29>
+3.3V_ALW_PCH
CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D
27P_0402_50V8J~D
27P_0402_50V8J~D
RH357 100K_0402_5%~DRH357 100K_0402_5%~D
C C
B B
1
1 2
CH101
@CH101
@
2
12
2
1 2
RH29 33_0402_5%~DRH29 33_0402_5%~D
1 2
RH26 33_0402_5%~DRH26 33_0402_5%~D
1 2
RH27 33_0402_5%~DRH27 33_0402_5%~D
1 2
RH25 33_0402_5%~DRH25 33_0402_5%~D
1
2
USB30_SMI#
1 2
RH22 20K_0402_5%~DRH22 20K_0402_5%~D
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
1
1
@
@
CMOS1 SHORT PADS~D
CMOS1 SHORT PADS~D
CH4
CH4
CMOS place near DIMM
PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK
+3.3V_ALW_PCH
12
RH288
RH288
0_0603_5%~D
0_0603_5%~D
+3.3V_ALW_PCH_JTAG
2
2
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RH59 51_0402_1%~DRH59 51_0402_1%~D
RH44 200_0402_1%~DRH44 200_0402_1%~D
RH45 200_0402_1%~DRH45 200_0402_1%~D
RH43 200_0402_1%~DRH43 200_0402_1%~D
ME_FWP<39>
12
12
12
12
18P_0402_50V8J~D
18P_0402_50V8J~D
18P_0402_50V8J~D
18P_0402_50V8J~D
4
PCH_AZ_SYNC_Q
1 2
RH31 1M_0402_5%~DRH31 1M_0402_5%~D
INTEL HDA_SYNC
isolation circuit
CH2
CH2
12
12
YH1
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
CH3
CH3
32.768KHZ_12.5PF_Q13FC1350000~D
PCH_RTCX2_R
12
+3.3V_ALW_PCH
12
12
RH48
RH48
100_0402_1%~D
100_0402_1%~D
+5V_RUN
1 2
RH286 0_0402_5%~DRH286 0_0402_5%~D
PCH_AZ_CODEC_SDIN0<29>
1 2
RH287 1K_0402_1%~D@RH287 1K_0402_1%~D@
1 2
RH50 1K_0402_1%~DRH50 1K_0402_1%~D
12
RH47
RH47
RH49
RH49
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
S
S
G
G
PCH_RTCX1
SPKR<29>
D
D
13
QH7
QH7
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
2
12
RH2
RH2
10M_0402_5%~D
10M_0402_5%~D
PCH_RTCX2
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_GPIO33
USB30_SMI#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
3
PCH_AZ_SYNC
SIO_PWRBTN#
PCH_RSMRST#_Q<16,41>
UH4A
UH4A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_ EN# / GPIO3 3
N32
HDA_DOCK_ RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
2
+3.3V_ALW_PCH
12
1 2
RH24 1K_0402_1%~D@ RH24 1K_0402_1%~D@
FWH0 / L AD0
FWH1 / L AD1
FWH2 / L AD2
FWH3 / L AD3
LPC
LPC
FWH4 / L FRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA
SATA
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMP O
SATA3COMPI
SATA3RBIA S
SATALED#
+3.3V_ALW_PCH+1.05V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
@
CH1
CH1
1
CH1 clsoe to JXDP2CH6 clsoe to JXDP2
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LDRQ1#
IRQ_SERIRQ
SATA_COMP
SATA3_COMP
RBIAS_SATA3
SATA_ACT#
HDD_DET#_R
BBS_BIT0_R
1.05V_0.8V_PWROK<40,53>
SIO_PWRBTN#<7,16,40>
+3.3V_ALW_PCH
XDP_DBRESET#<7,16>
RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D
RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D
RH46 750_0402_1%~DRH46 750_0402_1%~D
RH284 0_0402_5%~D@RH284 0_0402_5%~D@
RSMRST#_XDP
1 2
RH283 1K_0402_5%~D@R H283 1K_0402_5%~D@
1 2
1 2
RH21 0_0402_5%~D@RH21 0_0402_5%~D@
RSMRST#_XDP
XDP_DBRESET#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMSRSMRST#_XDP
PCH_JTAG_TCK
LPC_LAD0 <32, 34,39,40>
LPC_LAD1 <32, 34,39,40>
LPC_LAD2 <32, 34,39,40>
LPC_LAD3 <32, 34,39,40>
LPC_LFRAME# <32,34,39,40>
LPC_LDRQ1# <39>
IRQ_SERIRQ <32,39,40>
PSATA_PRX_DTX_N0_C <27>
PSATA_PRX_DTX_P0_C <27>
PSATA_PTX_DRX_N0_C <27>
PSATA_PTX_DRX_P0_C <27>
ESATA_PRX_DTX_N4_C <37>
ESATA_PRX_DTX_P4_C <37>
ESATA_PTX_DRX_N4_C <37>
ESATA_PTX_DRX_P4_C <37>
SATA_PRX_DKTX_N5_C <38>
SATA_PRX_DKTX_P5_C <38>
SATA_PTX_DKRX_N5_C <38>
SATA_PTX_DKRX_P5_C <38>
1 2
1 2
1 2
SATA_ACT# <43>
1 2
RH290 0_0402_5%~DRH290 0_0402_5%~D
1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP
+1.05V_RUN
+1.05V_RUN
HDD
E-SATA
DOCK
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
@
CH6
CH6
1
2
RH41 10K_0402_5%~D@ RH41 10K_0402_5%~D@
RTCIHDA
RTCIHDA
JTAG
JTAG
SATA0GP / GPIO21
SPI
SPI
SATA1GP / GPIO19
+1.05V_RUN
+3.3V_RUN
12
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
26
PCH_GPIO33
RH355 100K_0402_5%~DRH355 100K_0402_5%~D
IRQ_SERIRQ
RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D
BBS_BIT0_R
RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D
INTEL feedback 0302
SPKR
RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@
No Reboot Strap
SPKR
RH30
RH30
10K_0402_5%~D
10K_0402_5%~D
HDD_DET# <27>
JXDP2
@JXDP2
@
OBSFN_A0
OBSFN_A1
GND
OBSDATA_A [0]
OBSDATA_A [1]
GND
OBSDATA_A [2]
OBSDATA_A [3]
GND
HOOK0
HOOK1
HOOK2
HOOK3
HOOK4
HOOK5
VCCOBS_A B
HOOK6
HOOK7
GND
TDO
TRSTn
TDI
TMS
TCK124GND
GND
GND
TCK0
MOLEX_52435-2671
MOLEX_52435-2671
12
12
1 2
+3.3V_RUN
12
Low = Default
High = No Reboot
27
28
+3.3V_RUN
BBS_BIT0 - BIOS BOOT STRAP BIT 0
+3.3V_M
12
200 MIL SO8
R890
5@ R890
5@
3.3K_0402_5%~D
3.3K_0402_5%~D
PCH_SPI_CS0# PCH_SPI_CS0_R#
1 2
R935 0_0402_5%~DR935 0_0402_5%~D
PCH_SPI_DIN SPI_DIN64
1 2
R894 33_0402_5%~D5@ R894 33_0402_5%~D5@
SPI_WP#_SEL
SPI_WP#_SEL<39>
A A
R898 0_0402_5%~D@R 898 0_0402_5%~D@
1 2
5
SPI_WP#_SEL_R
64Mb Flash ROM
U52
5@ U52
5@
1
VCC
/CS
2
DO
/HOLD
3
CLK
/WP
GND4DIO
W25Q64CVSSIG_SO8~D
W25Q64CVSSIG_SO8~D
PCH_SPI_DO SPI_DO_TAA
12
R912 0_0402_5%~D6@ R912 0_0402_5%~D6@
SPI_CLK_TAAPCH_SPI_CLK
12
R906 0_0402_5%~D6@ R906 0_0402_5%~D6@
8
7
6
5
12
5@ R891
5@
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_CLK64
SPI_DO64
2
4
6
8
10
12
14
ACES_50169-01441-002
ACES_50169-01441-002
CONN@
CONN@
4
C746
5@ C746
5@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
R891
SPI_HOLD#
1 2
R899 33_0402_5%~D5@ R899 33_0402_5%~D5@
1 2
R901 33_0402_5%~D5@ R901 33_0402_5%~D5@
JTAA1
JTAA1
112
334
556
778
9910
111112
131314
PCH_SPI_CLK
PCH_SPI_DO
PCH_SPI_CS1_R#
SPI_DIN_TAA
PCH_SPI_CS0_R#
PCH_SPI_CS1# PCH_SPI_CS1_R#
1 2
R936 0_0402_5%~DR936 0_0402_5%~D
PCH_SPI_DIN
1 2
R895 33_0402_5%~D5@ R895 33_0402_5%~D5@
+3.3V_M
PCH_SPI_DIN
12
R896 0_0402_5%~D
R896 0_0402_5%~D
6@
6@
+3.3V_M
C745
5@ C745
5@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
SPI_HOLD#
SPI_CLK32
SPI_DO32
1 2
1 2
R897 33_0402_5%~D5@ R897 33_0402_5%~D5@
1 2
R900 33_0402_5%~D5@ R900 33_0402_5%~D5@
PCH_SPI_CLK
PCH_SPI_DO
2
200 MIL SO8
32Mb Flash ROM
U53
5@ U53
5@
1
SPI_DIN32
SPI_WP#_SEL_R
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
/CS
2
DO
3
/WP
GND4DIO
W25Q32BVSSIG_SO8~D
W25Q32BVSSIG_SO8~D
VCC
/HOLD
8
7
6
CLK
5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/8)
PCH (1/8)
PCH (1/8)
LA-7731P
LA-7731P
LA-7731P
14 59Thursday, September 01, 2011
14 59Thursday, September 01, 2011
14 59Thursday, September 01, 2011
1
0.3
0.3
0.3
5
Follow DG0.9 Device
D D
down & Express/Mini
card topology
PCIE_PRX_WANTX_N 1<3 4>
WWAN (Mini Card 1)--->
WLAN (Mini Card 2)--->
EXPRESS Card--->
1/2vMINI CARD-3 PCIE
(Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
WWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI Card--->
B B
PP (Mini Card 3)--->
Express card--->
WLAN (Mini Card 2)--->
A A
PCIE_PRX_WANTX_P 1<34>
PCIE_PTX_WANRX_N 1<3 4>
PCIE_PTX_WANRX_P 1<34>
PCIE_PRX_WLANTX_ N2<34>
PCIE_PRX_WLANTX_ P2<34>
PCIE_PTX_WLANRX_ N2<34>
PCIE_PTX_WLANRX_ P2<34>
PCIE_PRX_EXPTX_N3<35>
PCIE_PRX_EXPTX_P3<35>
PCIE_PTX_EXPRX_N3<35>
PCIE_PTX_EXPRX_P3<35>
PCIE_PRX_WPANTX _N5<34>
PCIE_PRX_WPANTX _P5<34>
PCIE_PTX_WPANRX _N5<34>
PCIE_PTX_WPANRX _P5<34>
PCIE_PRX_MMITX_N6<33>
PCIE_PRX_MMITX_P6<33>
PCIE_PTX_MMIRX_N6<33>
PCIE_PTX_MMIRX_P6<33>
PCIE_PRX_GLANTX_N7<31>
PCIE_PRX_GLANTX_P7<31>
PCIE_PTX_GLANRX_N7<31>
PCIE_PTX_GLANRX_P7<31>
CLK_PCIE_MINI1#<34>
CLK_PCIE_MINI1<34>
+3.3V_ALW_PCH
MINI1CLK_REQ#<34>
CLK_PCIE_LAN#<31>
CLK_PCIE_LAN<31>
LANCLK_REQ#<31>
CLK_PCIE_MMI#<33>
CLK_PCIE_MMI<33>
+3.3V_RUN
MMICLK_REQ#<33>
CLK_PCIE_MINI3#<34>
CLK_PCIE_MINI3<34>
+3.3V_ALW_PCH
MINI3CLK_REQ#<34>
CLK_PCIE_EXP#< 35>
CLK_PCIE_EXP<35>
+3.3V_ALW_PCH
EXPCLK_REQ#<35>
CLK_PCIE_MINI2#<34>
CLK_PCIE_MINI2<34>
+3.3V_ALW_PCH
MINI2CLK_REQ#<34>
+3.3V_ALW_PCH
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
RH87 10K_0402_5%~DRH87 10K_0402_ 5%~D
RH152 10K_0402_5%~DRH 152 10K_0402_5%~D
RH94 10K_0402_5%~DRH94 10K_0402_ 5%~D
RH97 10K_0402_5%~DRH97 10K_0402_ 5%~D
RH98 10K_0402_5%~DRH98 10K_0402_5%~D
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
5
1 2
1 2
4
12
12
12
12
4
PCIE_PRX_WANTX_N 1
PCIE_PRX_WANTX_P 1
PCIE_PTX_WANRX_N 1
PCIE_PTX_WANRX_P 1
PCIE_PRX_WLANTX_ N2
PCIE_PRX_WLANTX_ P2
PCIE_PTX_WLANRX_ N2
PCIE_PTX_WLANRX_ P2
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_WPANTX _N5
PCIE_PRX_WPANTX _P5
PCIE_PTX_WPANRX _N5
PCIE_PTX_WPANRX _P5
PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
MINI1CLK_REQ#
LANCLK_REQ#
MMICLK_REQ#
MINI3CLK_REQ#
EXPCLK_REQ#
MINI2CLK_REQ#
PEG_B_CLKRQ#
UH4B
UH4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
3
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
PCI_TPM_TCM
JETWAY_14M
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
PCH_GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
PEG_A_CLKRQ#
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
+XCLK_RCOMP
SIO_14M
CLK_80H
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
2
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <31>
LAN_SMBDATA <31 >
SML1_SMBCLK <40>
SML1_SMBDATA <40>
PCH_CL_CLK1 <34>
PCH_CL_DATA1 <34 >
PCH_CL_RST1# <34>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_PCI_LOOPBACK <17>
1 2
RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D
RH311 22_0402_5%~DRH311 22_0402_5%~D
RH313 22_0402_5%~DRH313 22_0402_5%~D
RH314 22_0402_5%~DRH314 22_0402_5%~D
RH315 22_0402_5%~D@ RH315 22_0402_5%~D@
12
12
12
12
2
+3.3V_RUN
5
3
QH5B
QH5B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
CLOCK TERMINATION for FCIM and need close to PCH
+1.05V_RUN
CLK_PCI_TPM_TCM <32>
CLK_SIO_14M <39>
1 2
C717 12P_0402_50V8J~DC717 12P_0402_50V8J~D
PCLK_80H <34>
JETWAY_CLK14M <32>
1
QH5A
QH5A
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
4
SML1_SMBCLK
SML1_SMBDATA
DDR_HVREF_RST_PCH
PCH_GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
PEG_A_CLKRQ#
LAN_SMBCLK
LAN_SMBDATA
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
DDR_XDP_WAN_ SMBCLK <12,13,27,34>
DDR_XDP_WAN_ SMBDAT <12,13,27,34>
1 2
RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
1 2
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D
RH300 1K_0402_1%~DRH300 1K_0402_1%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
RH304 10K_0402_5%~DRH304 10K_0402_5%~D
RH80 10K_0402_5%~DRH80 10K_0402_5%~D
RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D
1 2
RH74 10K_0402_5%~DRH74 10K_0402_ 5%~D
1 2
RH75 10K_0402_5%~DRH75 10K_0402_ 5%~D
1 2
RH91 10K_0402_5%~DRH91 10K_0402_ 5%~D
1 2
RH76 10K_0402_5%~DRH76 10K_0402_ 5%~D
1 2
RH77 10K_0402_5%~DRH77 10K_0402_ 5%~D
1 2
RH78 10K_0402_5%~DRH78 10K_0402_ 5%~D
1 2
RH79 10K_0402_5%~DRH79 10K_0402_ 5%~D
1 2
RH183 10K_0402_5%~DRH 183 10K_0402_5%~D
12
RH309 0_0402_5%~DRH309 0_0402_5%~D
12
RH99
RH99
1M_0402_5%~D
1M_0402_5%~D
2
25MHZ_10PF_Q22FA2380049900~D
25MHZ_10PF_Q22FA2380049900~D
CH18
CH18
1
10P_0402_50V8J~D
10P_0402_50V8J~D
3
4
12
12
12
12
12
12
12
12
YH2
YH2
OUT
GND
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_LAN
1
IN
2
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8)
PCH (2/8)
PCH (2/8)
LA-7731P
LA-7731P
LA-7731P
15 59Thursday, September 01, 2011
15 59Thursday, September 01, 2011
15 59Thursday, September 01, 2011
1
2
CH19
CH19
1
10P_0402_50V8J~D
10P_0402_50V8J~D
0.3
0.3
0.3
5
+3.3V_ALW_PCH
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_COMP_R
RBIAS_CPY
SUSACK#_R
XDP_DBRESET#
PM_APWROK_R
AC_PRESENT
PCH_BATLOW#
PCH_RI#
ME_SUS_PWR_ACK
PCH_PCIE_WAKE#
PCH_RI#
CLKRUN#
PCH_DPWROK PCH_RSMRST#_Q
ME_SUS_PWR_ACK SUSACK#_R
UH4C
UH4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
1 2
RH144 10K_0402_5 %~DRH1 44 10K_0402_5%~D
D D
+3.3V_RUN
C C
+1.05V_RUN
1 2
RH111 49.9_0402 _1%~DRH111 49.9_0402_ 1%~D
1 2
RH112 750_0402_ 1%~DRH112 750_0 402_1%~D
SUSACK#<39> PCH_DPWROK <39>
B B
ME_SUS_PWR_ACK<40 >
AC_PRESENT<40>
+3.3V_ALW_PCH
A A
Remove RH116, RH117,
RH118, RH320, RH120,
RH121, RH122 to save room
for D4 12" only
1 2
RH142 10K_0402_5 %~DRH1 42 10K_0402_5%~D
1 2
RH140 10K_0402_5 %~DRH1 40 10K_0402_5%~D
1 2
RH137 8 .2K_0402_5%~DRH137 8 .2K_0402_5%~D
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
1 2
RH114 0_0402_5%~D@ RH114 0_0402_5%~D@
XDP_DBRESET#<7,14>
SYS_PWROK<7,3 9>
RESET_OUT#<40>
PM_DRAM_PWRGD<7>
PCH_RSMRST#_Q<14, 41>
SIO_PWRBTN#<7 ,14,40>
1 2
RH139 8.2K_0402_5%~DRH1 39 8.2K_0402_5%~D
5
4
1 2
RH113 0_0402_5%~DRH113 0_0402_5%~D
SYS_PWROKRESET_OUT#
1 2
RH321 0_0402_5%~D@ RH321 0_0402_5%~D@
1 2
RH323 0_0402_5%~DRH323 0_0402_5%~D
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
DMI
DMI
System Power Management
System Power Management
FDI_RXP7
FDI
FDI
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
4
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
RH131 150 _0402_1%~DRH131 150_0402_ 1%~D
RH132 150 _0402_1%~DRH132 150_0402_ 1%~D
RH133 150 _0402_1%~DRH133 150_0402_ 1%~D
RH134 100 K_0402_5%~DRH134 100K_0402_5%~D
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
Disabled
LOW: RH129 STUFFED,
RH127 UNSTUFFED
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
H_PM_SYNC
RH127 3 30K_0402_1%~DRH127 330K_ 0402_1%~D
1 2
PCH_PCIE_WAKE# <40>
CLKRUN# <32,39,40>
T56 PAD~DT56 PAD~D
T57 PAD~DT57 PAD~D
T58 PAD~DT58 PAD~D
SIO_SLP_S5# <40>
T59 PAD~DT59 PAD~D
SIO_SLP_S4# <39,42,48>
T60 PAD~DT60 PAD~D
SIO_SLP_S3# <11,35,39,4 2,49>
T61 PAD~DT61 PAD~D
SIO_SLP_A# <39,42,50>
T62 PAD~DT62 PAD~D
SIO_SLP_SUS# <39>
T63 PAD~DT63 PAD~D
SIO_SLP_LAN# < 31,39>
1 2
1 2
1 2
1 2
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
FDI_INT <6 >
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 < 6>
FDI_LSYNC1 < 6>
H_PM_SYNC <7>
3
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
PANEL_BKEN_PCH< 24>
ENVDD_PCH<24,39>
BIA_PWM_PCH<24>
LDDC_CLK_PCH<24>
LDDC_DATA_PCH<24>
Minimum speacing of 20mils for LVD_IBG
+RTC_CELL
PCH_CRT_HSYNC<23 >
PCH_CRT_VSYNC<23>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
RH344 2.3 7K_0402_1%~DRH344 2.3 7K_0402_1%~D
LCD_ACLK-_PCH<24 >
LCD_ACLK+_PCH<24>
LCD_A0-_PCH<24>
LCD_A1-_PCH<24>
LCD_A2-_PCH<24>
LCD_A0+_PCH<24>
LCD_A1+_PCH<24>
LCD_A2+_PCH<24>
PCH_CRT_BLU< 23>
PCH_CRT_GRN<23>
PCH_CRT_RED<23>
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
RH316
RH316
PM_APWROK<40>
PANEL_BKEN_PCH
ENVDD_PCH
BIA_PWM_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
LVD_IBG
1 2
LCD_ACLK-_PCH
LCD_ACLK+_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
RH123 20_0402_1%~DRH123 20_ 0402_1%~D
RH124 20_0402_1%~DRH124 20_ 0402_1%~D
1 2
1 2
RH126
RH126
1K_0402_0.5%~D
1K_0402_0.5%~D
HSYNC
VSYNC
12
2.2K_0402_5%~D
2.2K_0402_5%~D
CRT_IREF
RH317
RH317
SIO_SLP_A#
PM_APWROK
UH4D
UH4D
J47
M45
P45
T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
T43
T42
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
2
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
RH118 0_0402_5%~ D@RH118 0_0402_5%~D@
+3.3V_ALW2
1
B
2
A
1 2
5
P
G
3
PCH_CRT_DDC_CLK <23>
PCH_CRT_DDC_DAT <23>
UH5
UH5
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PM_APWROK_R
4
O
Intel request DDPB can not support eDP
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
2
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
LVDS
LVDS
CRT
CRT
1
+3.3V_RUN
12
12
AP43
AP45
AM42
AM40
AP39
AP40
PCH_SDVO_CTRLCLK
P38
PCH_SDVO_CTRLDATA
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
HDMIB_PCH_HPD <25>
TMDSB_PCH_N2 <25>
TMDSB_PCH_P2 <25>
TMDSB_PCH_N1 <25>
TMDSB_PCH_P1 <25>
TMDSB_PCH_N0 <25>
TMDSB_PCH_P0 <25>
TMDSB_PCH_CLK# <25>
TMDSB_PCH_CLK <25>
PCH_DDPC_CTRLCLK <26>
PCH_DDPC_CTRLDATA <26>
DPC_PCH_DOCK_AUX# <26>
DPC_PCH_DOCK_AUX <26>
DPC_PCH_DOCK_HPD <3 8>
DPC_PCH_LANE_N0 <38>
DPC_PCH_LANE_P0 < 38>
DPC_PCH_LANE_N1 <38>
DPC_PCH_LANE_P1 < 38>
DPC_PCH_LANE_N2 <38>
DPC_PCH_LANE_P2 < 38>
DPC_PCH_LANE_N3 <38>
DPC_PCH_LANE_P3 < 38>
PCH_DDPD_CTRLCLK <26>
PCH_DDPD_CTRLDATA <26>
DPD_PCH_DOCK_AUX# <26>
DPD_PCH_DOCK_AUX <26>
DPD_PCH_DOCK_HPD <3 8>
DPD_PCH_LANE_N0 <38>
DPD_PCH_LANE_P0 < 38>
DPD_PCH_LANE_N1 <38>
DPD_PCH_LANE_P1 < 38>
DPD_PCH_LANE_N2 <38>
DPD_PCH_LANE_P2 < 38>
DPD_PCH_LANE_N3 <38>
DPD_PCH_LANE_P3 < 38>
RH351 2 .2K_0402_5%~DRH351 2 .2K_0402_5%~D
RH352 2 .2K_0402_5%~DRH352 2 .2K_0402_5%~D
PCH_SDVO_CTRLCLK <25>
PCH_SDVO_CTRLDATA <2 5>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sh eet of
Date: Sh eet of
Date: Sh eet of
Compal Electronics, Inc.
PCH (3/8)
PCH (3/8)
PCH (3/8)
LA-7731P
LA-7731P
LA-7731P
1
16 59Thursday, September 01, 2011
16 59Thursday, September 01, 2011
16 59Thursday, September 01, 2011
0.3
0.3
0.3
+3.3V_RUN
5
4
3
2
1
PCH_PLTRST#
5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LCD_CBL_DET#
CAM_MIC_CBL_DET#
BT_DET#
PCH_GPIO3
+3.3V_RUN
5
1
P
B
2
A
G
3
CLK_PCI_5048<39>
CLK_PCI_MEC<40>
CLK_PCI_DOCK<38>
CLK_PCI_LOOPBACK<15>
CH102
CH102
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
UH3
UH3
PCH_PLTRST#_EC
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
USB3RN1<36>
USB3RN2<36>
USB3RN4<38>
USB3RP1<36>
USB3RP2<36>
USB3RP4<38>
USB3TN1<36>
USB3TN2<36>
USB3TN4<38>
USB3TP1<36>
USB3TP2<36>
USB3TP4<38>
PCIE_MCARD2_DET#<34>
BT_DET#<41>
LCD_CBL_DET#<24>
CAM_MIC_CBL_DET#<24>
HDD_FALL_INT<27>
PCH_PLTRST#<7,31,32,33>
RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 22_0402_5%~DRH103 22_0402_5%~D
RH105 22_0402_5%~DRH105 22_0402_5%~D
PCH_PLTRST#_EC <32,34,35,39,40>
12
12
1 2
12
1
CH110
CH110
10P_0402_50V8J~D
10P_0402_50V8J~D
2
4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
BT_DET#
BBS_BIT1
PCI_GNT3#
LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
T104PAD~D @T104PAD~D @
PCH_PLTRST#
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
CLK_PCI_MECCLK_PCI_5048
1
CH109
CH109
10P_0402_50V8J~D
10P_0402_50V8J~D
2
UH4E
UH4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3TP1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
RSVD
RSVD
USB30
USB30
PCI
PCI
USB
USB
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
0 0
0 1
1 0
1 1
LPC
Reserved (NAND)
PCI
SPI
3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0USBP0+
USBP1USBP1+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USBP0- <36>
USBP0+ <36>
USBP1- <36>
USBP1+ <36>
USBP3- <38>
USBP3+ <38>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <32>
USBP7+ <32>
USBP8- <38>
USBP8+ <38>
USBP9- <37>
USBP9+ <37>
USBP10- <35>
USBP10+ <35>
USBP11- <41>
USBP11+ <41>
USBP12- <24>
USBP12+ <24>
Within 500 mils
1 2
RH151
RH151
22.6_0402_1%~D
22.6_0402_1%~D
USB_OC0# <36>
USB_OC4# <36>
SIO_EXT_SMI# <40>
BBS_BIT1
----->Right Side Top
----->Right Side Bottom
----->MLK DOCK
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash
----->USH
----->DOCK
----->Left side E-SATA
----->Express Card
----->Blue Tooth
----->Camera
12
RH342
@RH342
@
1K_0402_1%~D
1K_0402_1%~D
2
INTEL feedback 0307
USB_OC0#
USB_OC1#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#
RH350 10K _0402_5%~DRH350 10K_0402_5%~D
1 2
RH341 10K _0402_5%~DRH341 10K_0402_5%~D
1 2
RH343 10K _0402_5%~DRH343 10K_0402_5%~D
1 2
RH345 10K _0402_5%~DRH345 10K_0402_5%~D
1 2
RH346 10K _0402_5%~DRH346 10K_0402_5%~D
1 2
RH347 10K _0402_5%~DRH347 10K_0402_5%~D
1 2
RH348 10K _0402_5%~DRH348 10K_0402_5%~D
1 2
RH349 10K _0402_5%~DRH349 10K_0402_5%~D
1 2
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/8)
PCH (4/8)
PCH (4/8)
LA-7731P
LA-7731P
LA-7731P
17 59Thursday, September 01, 2011
17 59Thursday, September 01, 2011
17 59Thursday, September 01, 2011
1
0.3
0.3
0.3
1 2
D D
C C
RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D
1 2
RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~DRH327 10K_0402 _5%~D
1 2
RH330 10K_0402_5%~DRH330 10K_0402 _5%~D
1 2
RH331 10K_0402_5%~DRH331 10K_0402 _5%~D
1 2
RH328 10K_0402_5%~DRH328 10K_0402 _5%~D
1 2
RH332 10K_0402_5%~DRH332 10K_0402 _5%~D
PCI_GNT3#
12
RH333
@RH333
@
1K_0402_1%~D
1K_0402_1%~D
A16 swap overri de Strap/Top-B lock
Swap Override jumper
PCI_GNT#3
B B
Remove RH335,RH336,RH337,RH338
to save room for D12" only
A A
PCH_PLTRST#<7,31,32,33>
Low = A16 swap
High = Default
5
4
3
2
1
+3.3V_ALW_PCH
RH53
RH53
4.7K_0402_5%~D
D D
C C
B B
A A
4.7K_0402_5%~D
1 2
SLP_ME_CSW_DE V#
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
+3.3V_ALW_PCH
SIO_EXT_WAKE#
RH177 10K_0402_5%~DRH177 10K_0402 _5%~D
RH354 1K_0402_1%~DRH354 1K _0402_1%~D
+3.3V_ALW_PCH
RH170 10K_0402_5%~DRH170 10K_0402_5%~D
+3.3V_RUN
RH171 10K_0402_5%~D@RH171 10K_0402_5%~D@
RH173 1K_0402_1%~D@RH 173 1K_0402_1%~D@
RH175 10K_0402_5%~DRH175 10K_0402_5%~D
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH181 10K_0402_5%~DRH181 10K_0402_5%~D
1 2
RH178 10K_0402_5%~DRH178 10K_0402_5%~D
1 2
RH269 8.2K_0402_5%~D@ RH269 8.2K_0402_5%~D@
1 2
RH163 10K_0402_5%~DRH163 10K_0402_5%~D
12
12
12
12
12
12
12
PCH_GPIO15
PCH_GPIO36
12
PCH_GPIO37
12
DBC_ENABLE
12
KB_DET#
PCH_GPIO36
PCH_GPIO37
ESATA_CD#
TEMP_ALERT#
PCH_GPIO22
PCH_GPIO7
DBC_ENABLE
PCH_GPIO6
5
1 2
INTEL feedback 0302
RH174 10K_0402_5%~DRH174 10K_0402 _5%~D
RH172 10K_0402_5%~DRH172 10K_0402 _5%~D
RH273 10K_0402_5%~DRH273 10K_0402 _5%~D
SIO_EXT_SCI#<40>
USH_DET#<32>
SIO_EXT_WAKE#<39>
PM_LANPHY_ENABLE<31>
ESATA_CD#<37>
DBC_ENABLE<24>
PCIE_MCARD1_DET#<34>
EXPRCRD_DET#<35>
SLP_ME_CSW_DE V#<39>
USB_MCARD1_DET#<34>
FFS_INT2<27>
TEMP_ALERT#<39>
KB_DET#<41>
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
+3.3V_RUN
RH267
RH267
10K_0402_5%~D
10K_0402_5%~D
TPM_ID0
1 2
RH270
@ RH270
@
10K_0402_5%~D
10K_0402_5%~D
1 2
USH_DET#
PCH_GPIO6
PCH_GPIO7
PM_LANPHY_ENABLE
PCH_GPIO15
DBC_ENABLE
PCH_GPIO22
EXPRCRD_DET#
SLP_ME_CSW_DE V#
USB_MCARD1_DET#
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
+3.3V_RUN
TPM_ID1
4
12
RH268
RH268
20K_0402_5%~D
20K_0402_5%~D
12
RH271
@RH271
@
2.2K_0402_5%~D
2.2K_0402_5%~D
UH4F
UH4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
BD82PPSM-QNHN-A0_BGA989~D
BD82PPSM-QNHN-A0_BGA989~D
GPIO
GPIO
NCTF
NCTF
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
1 1USH2.0
3
PECI
RCIN#
NC_1
TPM_ID1TPM_ID0
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
CONTACTLESS_DET#
PCH_GPIO69
PCIE_MCARD3_DET#
SIO_A20GATE
SIO_RCIN#
PCH_THRMTRIP#_R
DF_TVS
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
CONTACTLESS_DET# <32>
PCIE_MCARD3_DET# <34>
USB_MCARD2_DET# <34>
SIO_A20GATE <40>
SIO_RCIN# <40>
H_CPUPWRGD <7>
1
2
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
Due to remove VCCDFERM
jumper(PJP66), need to
change the power rail to
+1.8V_RUN for D12" only
H_SNB_IVB#<7>
2
+1.05V_RUN_VTT
12
RH262 56_0402_5%~DRH262 56_0402_5%~D
CH97
CH97
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2
RH150 0_0402_5%~DR H150 0_0402_5%~D
CONTACTLESS_DET#
PCH_GPIO69
RH256 10K _0402_5%~DRH256 10K_0402_5%~D
RH260 1.5K_0402 _1%~DRH260 1.5K_0402_1%~D
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
USH_DET#
PLACE RH150 CLO SE TO THE BRAN CHING POINT
( TO CPU and NV RAM CONNECTOR)
+1.8V_RUN
12
RH149
RH149
2.2K_0402_5%~D
2.2K_0402_5%~D
12
1 2
RH158 10K_0402_5%~DRH158 10K_0402 _5%~D
RH203 10K_0402_5%~DRH203 10K_0402 _5%~D
1 2
RH263 10K_0402_5%~DRH263 10K_0402 _5%~D
1 2
RH164 100K_0402_5%~DRH164 100K_0402_5%~D
RH149 need to close to CPU
1 2
RH358 1K_0402_1%~DRH358 1K_0402_1%~D
DMI & FDI Termination Voltage
DF_TVS
Set to Vss when LOW
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/8)
PCH (5/8)
PCH (5/8)
LA-7731P
LA-7731P
LA-7731P
+3.3V_RUN
+3.3V_RUN
12
12
DF_TVSDF_TVS_R
0.3
0.3
18 59Thursday, September 01, 2011
18 59Thursday, September 01, 2011
18 59Thursday, September 01, 2011
1
0.3
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