Compal LA-7571P QOQAE Ontario 10AS Schematic
A
1 1
B
C
D
E
QOQAE
2 2
Ontario 10AS
LA-7571P SchematicREV 1.0
3 3
AMD Llano FS1 Processor / Hudson M2/M3
2011-05-04 Rev 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
141Monday, May 09, 2011
141Monday, May 09, 2011
141Monday, May 09, 2011
E
B
B
B
of
of
of
A
B
C
D
E
EC SMBus
1 1
2 2
3 3
RTC CKT.
DC/DC Interface
page 12
page 32
HDMI-CEC
page 20
RJ45
page 24
HDMI Conn.
page 20
CRT
RTL8105E 10/100M
RTL8111E 1G
Cardreader
JMB389C
PCI-Express X4 5GHz
LVDS Translator
ANX3110
PCIe port4
page 17
LVDS Conn.
page 18
page19
APU PCIe port 0
page 24
FCH PCIe port2
page 25
PCIe X1
1.1V 5GT/s
SPI Bus
3.3V 33 MHz
AMD APU
FS1 Processor
Llano uPGA-722
page 5,6,7,8,9
DP0
(X1)
PCIe X1
1.1V 5GT/s
AMD FCH
Hudson M2/M3
FCBGA-656
page 12,13,14,15,16
LPC Bus
3.3V 33 MHz
35mm*35mm
DP1
(X4)
24.5mm*24.5mm
UMI X4
2.5GT/s
HD Audio
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333 MT/s
PCIe X1 X1
1.1V 5GT/s
USB Conn
USB port 0,1
Int. Camera
USB
5V 480MHz
USB port 5
PCIeMini Card
USB
5V 480MHz
SATA port 0
5V 6GHz(600MB/s)
SATA port 1
5V 6GHz(600MB/s)
USB 3.0 port0
5GHz
PCIe X1
1.1V 5GT/s
3.3V 24MHz
WLAN
SATA HDD
SATA ODD
USB3.0
UPD720200AF1-DAP-A
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
USB 3.0
USB port 8
page 23
page 23
FCH PCIe port1
page 26
USB port 10
page 21
page 18
APU PCIe port 1
SATA port 0
page 21
SATA port 1
page 21
PWM Fan Control
FingerPrinter
page 26
USB port 7
PCIeMini Card
3G
USB port 6
page 23
PCIeMini Card
JET
APU PCIe port 2
page 23
USB 3.0
page 5
page 10,11
page 22
USB3.0 port0
page 26
SIM
page 23
HDA Codec
Power Circuit DC/DC
page 33~40
SPI ROM
(2MB)
page14
Debug Port
page 30
ENE KB930
page 29
ALC269
page27
NBQAA Sub-board Conn
Power Membrane
4 4
page 31
Slot ODD
page 21
Touch Pad
FP/LOGO LED
page 22
Touch Pad
page 22
Cap Sensor
TP LED
page 22
A
page 22
B
Int.KBD
page 28'
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
EC ROM
(128KB)
page 30
C
G-Sensor
page 30
Compal Secret Data
Compal Secret Data
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
MIC Conn
page 18
D
MIC ConnInt.
page 28
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
HP CONN
page 28
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
E
SPK CONN
241Monday, May 09, 2011
241Monday, May 09, 2011
241Monday, May 09, 2011
page 28
of
of
of
B
B
B
5
B+
D D
Ipeak=5A, Imax=3.5A, Iocp min=7.9A
SUSP
N-CHANNEL
SI4800
TPS51125A
Ipeak=5A, Imax=3.5A, Iocp min=7.7A
4
KB_LED
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_PWR
P-CHANNEL
AO-3413
WOL_EN
P-CHANNEL
AO-3413
SYSON
P-CHANNEL
AO-3413
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A
DESIGN CURRENT 5A
DESIGN CURRENT 5A
DESIGN CURRENT 400mA
DESIGN CURRENT 300mA
DESIGN CURRENT 1.6A
DESIGN CURRENT 5A
DESIGN CURRENT 330mA
DESIGN CURRENT 0.2A
+3VL
+5VL
+5VALW
+5VS
+5VS_LED
+3VS_HDP
+5VS_ODD
+3VALW
+3V_LAN
+3V
3
2
1
SUSP
N-CHANNEL
C C
POK
G5603RU1U
VR_ON
SI4800
B B
ISL6267HRZ-T
VR_ON
Ipeak=94A, Imax=52A, Iocp min=122A
Ipeak=33A, Imax=21.5A, Iocp min=40A
LCD_ENVDD
P-CHANNEL
AO-3413
+3VS
LDO
APL5508-25DC
SUSP
N-CHANNEL
FDS6676AS
G5603RU1U
SYSON
G5603RU1U
Ipeak=16A, Imax=11.2A, Iocp min=22.46A
SUSP
N-CHANNEL
FDS6676AS
+3V
LDO
APL5930KAI-TRG
SUSP
G2992F1U
DESIGN CURRENT 5A
DESIGN CURRENT 1.5A
DESIGN CURRENT 1A
DESIGN CURRENT 5.3A
DESIGN CURRENT 4A
DESIGN CURRENT 50A
DESIGN CURRENT 23A
DESIGN CURRENT 6.5A
DESIGN CURRENT 20A
DESIGN CURRENT 2A
DESIGN CURRENT 1A
DESIGN CURRENT 1.5A
+3VS
+LCD_VDD
+2.5VS
+1.1VALW
+1.1VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
+1.5V
+1.5VS
+1.05V
+0.75VS
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
1
of
341Monday, May 09, 2011
of
341Monday, May 09, 2011
of
341Monday, May 09, 2011
B
B
B
A
B
C
D
E
Voltage Rails
State
S0
S1
S3
S5 S4/AC
power
plane
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
FCH SM Bus Address (SCL0/SDA0)
Power
3 3
+3VS
+3VS
+3VS
Device
DDR SO-DIMM 0
DDR SO-DIMM 1
WLAN
3G+3VS
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
HEX
B+
O
O
O
O
O
X
Address
1010 0000 bA0 H
1010 0100 bA4 H
+5VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+1.1VALW
+VSB
O
O
O
O
X
X
+1.5V
+3V
+1.05V
+5VS
+3VS
+2.5VS
+1.5VS
+1.2VS
+1.1VS
+0.75VS
+CPU_CORE
+CPU_CORE_NB
OO
OO
O
X
XX
X
X
XX
BTO Option Table
Function
description
explain
BTO
Function
description
explain
BTO
Function
description
explain
BTO
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G3 LOW LOW
HDMI-CEC
HDMI
Normal
ODD0@
Hudson-M2 Hudson-M3
SIGNAL
HDMI+CEC
CEC@
ODD
T
Slot
ODD1@
FCH
HM2 HM3 UM
M2@ M3@
SLP_S3#
HIGH HIGH
LOW
LOW
Y
SLP_S5#
HIGHHIGH
HIGH
HIGH
LOWLOW
LAN
UV
10/100
8105E@
Mini Card Chipset
G
3G JET
3G@
J
JET@
UMA
10/100/1000
8111E@
3G/JET
3GJET@
CAM+MIC
X
CAM
CAM@
FCH
Hudson-M3
HUDM3R1@ HUDM3R3@
KB LED
KB LED
KBL@
Renesas USB3.0
K
Renesas USB3.0
EC
N/A Reserved
KB-930 KB-9012
KB930@ KB9012@
Reserved
RENE@
EC SM Bus1 Address
Device Address Address
+3VL
+3VL
4 4
HDMI-CEC 34 H 0011 0100 b
A
HEX HEX
16 H
0001 0110 bSmart Battery
PowerPower
+3VS
HEXDevice AddressPower
Virtual I2CCap. Sensor+3VL
EC SM Bus2 Address
Device
G-Sensor
B
40 H
0100 0000 b
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
441Monday, May 09, 2011
441Monday, May 09, 2011
441Monday, May 09, 2011
E
of
of
of
B
B
B
A
JAPUA
JAPUA
AA8
AA9
P_ZVDDP
Y7
Y8
W5
W6
W8
W9
V7
V8
U5
U6
U8
U9
T7
T8
R5
R6
R8
R9
P7
P8
N5
N6
N8
N9
M7
M8
L5
L6
L8
L9
AC5
AC6
AC8
AC9
AB7
AB8
AA5
AA6
AF8
AF7
AE6
AE5
AE9
AE8
AD8
AD7
K5
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
1 1
2 2
PCIE_FRX_C_LANTX_P0<24>
3 3
4 4
PCIE_FRX_C_LANTX_N0<24>
PCIE_FRX_WLANTX_P1<23>
PCIE_FRX_WLANTX_N1<23>
UMI_MTX_C_FRX_P0<12>
UMI_MTX_C_FRX_N0<12>
UMI_MTX_C_FRX_P1<12>
UMI_MTX_C_FRX_N1<12>
UMI_MTX_C_FRX_P2<12>
UMI_MTX_C_FRX_N2<12>
UMI_MTX_C_FRX_P3<12>
UMI_MTX_C_FRX_N3<12>
+1.2VS
PCIE_FRX_C_LANTX_P0
PCIE_FRX_C_LANTX_N0
PCIE_FRX_WLANTX_P1
PCIE_FRX_WLANTX_N1
T29T29
T28T28
UMI_MTX_C_FRX_P0
UMI_MTX_C_FRX_N0
UMI_MTX_C_FRX_P1
UMI_MTX_C_FRX_N1
UMI_MTX_C_FRX_P2
UMI_MTX_C_FRX_N2
UMI_MTX_C_FRX_P3
UMI_MTX_C_FRX_N3
1 2
R9 196_0402_1%R9 196_0402_1%
close to APU close to APU
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
PCI EXPRESS
PCI EXPRESS
GPPUMI-LINK GRAPHICS
GPPUMI-LINK GRAPHICS
B
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
@
@
AA2
AA3
Y2
Y1
Y4
Y5
W2
W3
V2
V1
V4
V5
U2
U3
T2
T1
T4
T5
R2
R3
P2
P1
P4
P5
N2
N3
M2
M1
M4
M5
L2
L3
AD4
AD5
AC2
AC3
AB2
AB1
AB4
AB5
AF1
AF2
AF5
AF4
AE3
AE2
AD1
AD2
K4
PCIE_FTX_LANRX_P0
PCIE_FTX_LANRX_N0
PCIE_FTX_WLANRX_P1
PCIE_FTX_WLANRX_N1
PCIE_FTX_JETRX_P2
PCIE_FTX_JETRX_N2
UMI_FTX_MRX_P0
UMI_FTX_MRX_N0
UMI_FTX_MRX_P1
UMI_FTX_MRX_N1
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
UMI_FTX_MRX_P3
UMI_FTX_MRX_N3
P_ZVSS
1 2
R10 196_0402_1%R10 196_0402_1%
C
C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K
1 2
C50 0.1U_0402_16V7KC50 0.1U_0402_16V7K
1 2
C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K
1 2
C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K
1 2
C53 0.1U_0402_16V7KC53 0.1U_0402_16V7K
1 2
C54 0.1U_0402_16V7KC54 0.1U_0402_16V7K
1 2
C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K
1 2
C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K
1 2
C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K
1 2
C58 0.1U_0402_16V7KC58 0.1U_0402_16V7K
1 2
C59 0.1U_0402_16V7KC59 0.1U_0402_16V7K
1 2
C60 0.1U_0402_16V7KC60 0.1U_0402_16V7K
1 2
C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K
1 2
C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K
1 2
UMA_HDMI_TX2+ <20>
UMA_HDMI_TX2- <20>
UMA_HDMI_TX1+ <20>
UMA_HDMI_TX1- <20>
UMA_HDMI_TX0+ <20>
UMA_HDMI_TX0- <20>
UMA_HDMI_TXC+ <20>
UMA_HDMI_TXC- <20>
PCIE_FTX_C_LANRX_P0 <24>
PCIE_FTX_C_LANRX_N0 <24>
PCIE_FTX_C_WLANRX_P1 <23>
PCIE_FTX_C_WLANRX_N1 <23>
PCIE_FTX_C_JETRX_P2 <23>
PCIE_FTX_C_JETRX_N2 <23>
UMI_FTX_C_MRX_P0 <12>
UMI_FTX_C_MRX_N0 <12>
UMI_FTX_C_MRX_P1 <12>
UMI_FTX_C_MRX_N1 <12>
UMI_FTX_C_MRX_P2 <12>
UMI_FTX_C_MRX_N2 <12>
UMI_FTX_C_MRX_P3 <12>
UMI_FTX_C_MRX_N3 <12>
D
FAN Control Circuit
FAN_SPEED1<29>
+5VS
1 2
40 mils
+FAN1
LAN
WLAN
JET
1A
R14 0_0603_5%R14 0_0603_5%
2
C6
C6
10U_0805_10V6K
10U_0805_10V6K
1
@
@
+3VS
12
R13
R13
10K_0402_5%
10K_0402_5%
1
C7
C7
0.01U_0402_25V7K
0.01U_0402_25V7K
@
@
2
+5VS
1SS355TE-17_SOD323-2
1SS355TE-17_SOD323-2
D7
D7
1
BAS16_SOT23-3
BAS16_SOT23-3
E
JFAN
JFAN
1
FANPWM<29>
+FAN1
FANPWM
1
2
2
3
3
4
4
ACES_85204-0400N
ACES_85204-0400N
@
@
Close to Connector
1000P_0402_50V7KC81000P_0402_50V7K
221
D8
D8
10U_0805_10V6KC510U_0805_10V6K
12
C5
1
2
C8
2
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
541Monday, May 09, 2011
541Monday, May 09, 2011
541Monday, May 09, 2011
E
B
B
B
of
of
of
A
B
C
D
E
DDR_A_DQS[0..7]<10>
DDR_A_DQS#[0..7]<10>
1 1
DDR_A_MA[0..15]<10>
DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>
DDR_A_DM[0..7]<10>
2 2
DDR_A_CLK0<10>
DDR_A_CLK0#<10>
DDR_A_CLK1<10>
DDR_A_CLK1#<10>
DDR_A_CKE0<10>
DDR_A_CKE1<10>
DDR_A_ODT0<10>
DDR_A_ODT1<10>
3 3
DDR_A_SCS0#<10>
DDR_A_SCS1#<10>
DDR_A_RAS#<10>
DDR_A_CAS#<10>
DDR_A_WE#<10>
MEM_MA_RST#<10>
MEM_MA_EVENT#<10>
+1.5V
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_CKE0
DDR_A_CKE1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_SCS0#
DDR_A_SCS1#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
MEM_MA_RST#
MEM_MA_EVENT#
+MEM_VREF
M_ZVDDIO
1 2
R33 39.2_0402_1%R33 39.2_0402_1%
15mil
JAPUB
JAPUB
U20
MA_ADD0
R20
MA_ADD1
R21
MA_ADD2
P22
MA_ADD3
P21
MA_ADD4
N24
MA_ADD5
N23
MA_ADD6
N20
MA_ADD7
N21
MA_ADD8
M21
MA_ADD9
U23
MA_ADD10
M22
MA_ADD11
L24
MA_ADD12
AA25
MA_ADD13
L21
MA_ADD14
L20
MA_ADD15
U24
MA_BANK0
U21
MA_BANK1
L23
MA_BANK2
E14
MA_DM0
J17
MA_DM1
E21
MA_DM2
F25
MA_DM3
AD27
MA_DM4
AC23
MA_DM5
AD19
MA_DM6
AC15
MA_DM7
G14
MA_DQS_H0
H14
MA_DQS_L0
G18
MA_DQS_H1
H18
MA_DQS_L1
J21
MA_DQS_H2
H21
MA_DQS_L2
E27
MA_DQS_H3
E26
MA_DQS_L3
AE26
MA_DQS_H4
AD26
MA_DQS_L4
AB22
MA_DQS_H5
AA22
MA_DQS_L5
AB18
MA_DQS_H6
AA18
MA_DQS_L6
AA14
MA_DQS_H7
AA15
MA_DQS_L7
T21
MA_CLK_H0
T22
MA_CLK_L0
R23
MA_CLK_H1
R24
MA_CLK_L1
H28
MA_CKE0
H27
MA_CKE1
Y25
MA_ODT0
AA27
MA_ODT1
V22
MA_CS_L0
AA26
MA_CS_L1
V21
MA_RAS_L
W24
MA_CAS_L
W23
MA_WE_L
H25
MA_RESET_L
T24
MA_EVENT_L
W20
M_VREF
W21
M_ZVDDIO
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
MEMORY CHANNEL A
MEMORY CHANNEL A
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
@
@
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D[0..63] <10>
DDR_B_DQS[0..7]<11>
DDR_B_DQS#[0..7]<11>
JAPUC
JAPUC
MEMORY CHANNEL B
DDR_B_MA[0..15]<11>
DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>
DDR_B_DM[0..7]<11>
DDR_B_CLK0<11>
DDR_B_CLK0#<11>
DDR_B_CLK1<11>
DDR_B_CLK1#<11>
DDR_B_CKE0<11>
DDR_B_CKE1<11>
DDR_B_ODT0<11>
DDR_B_ODT1<11>
DDR_B_SCS0#<11>
DDR_B_SCS1#<11>
DDR_B_RAS#<11>
DDR_B_CAS#<11>
DDR_B_WE#<11>
MEM_MB_RST#<11>
MEM_MB_EVENT#<11>
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_CKE0
DDR_B_CKE1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_SCS0#
DDR_B_SCS1#
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
MEM_MB_RST#
MEM_MB_EVENT#
MEMORY CHANNEL B
T27
MB_ADD0
P24
MB_ADD1
P25
MB_ADD2
N27
MB_ADD3
N26
MB_ADD4
M28
MB_ADD5
M27
MB_ADD6
M24
MB_ADD7
M25
MB_ADD8
L26
MB_ADD9
U26
MB_ADD10
L27
MB_ADD11
K27
MB_ADD12
W26
MB_ADD13
K25
MB_ADD14
K24
MB_ADD15
U27
MB_BANK0
T28
MB_BANK1
K28
MB_BANK2
D14
MB_DM0
A18
MB_DM1
A22
MB_DM2
C25
MB_DM3
AF25
MB_DM4
AG22
MB_DM5
AH18
MB_DM6
AD14
MB_DM7
C15
MB_DQS_H0
B15
MB_DQS_L0
E18
MB_DQS_H1
D18
MB_DQS_L1
E22
MB_DQS_H2
D22
MB_DQS_L2
B26
MB_DQS_H3
A26
MB_DQS_L3
AG24
MB_DQS_H4
AG25
MB_DQS_L4
AG21
MB_DQS_H5
AF21
MB_DQS_L5
AG17
MB_DQS_H6
AG18
MB_DQS_L6
AH14
MB_DQS_H7
AG14
MB_DQS_L7
R26
MB_CLK_H0
R27
MB_CLK_L0
P27
MB_CLK_H1
P28
MB_CLK_L1
J26
MB_CKE0
J27
MB_CKE1
W27
MB_ODT0
Y28
MB_ODT1
V25
MB_CS_L0
Y27
MB_CS_L1
V24
MB_RAS_L
V27
MB_CAS_L
V28
MB_WE_L
J25
MB_RESET_L
T25
MB_EVENT_L
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
@
@
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] <11>
EVENT# pull high 0.75V Reference Voltage
+1.5V
4 4
R11 1K_0402_5%R11 1K_0402_5%
1 2
R12 1K_0402_5%R12 1K_0402_5%
1 2
MEM_MA_EVENT#
MEM_MB_EVENT#
A
R31
R31
1K_0402_1%
1K_0402_1%
R32
R32
1K_0402_1%
1K_0402_1%
+1.5V
1 2
1 2
B
1
C63
C63
1000P_0402_50V7K
1000P_0402_50V7K
2
15mil
+MEM_VREF
2
C64
C64
0.1U_0402_16V7K
0.1U_0402_16V7K
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
E
of
of
of
641Monday, May 09, 2011
641Monday, May 09, 2011
641Monday, May 09, 2011
B
B
B
A
To LVDS Translator
C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K
DP0_TXP0_C<17>
DP0_TXN0_C<17>
1 2
C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K
1 2
DP0_TXP0
DP0_TXN0
Close to APU
1 1
Close to APU
C71 0.1U_0402_16V7KC71 0.1U_0402_16V7K
ML_VGA_TXP0<14>
ML_VGA_TXN0<14>
ML_VGA_TXP1<14>
To FCH
ML_VGA_TXN1<14>
ML_VGA_TXP2<14>
ML_VGA_TXN2<14>
ML_VGA_TXP3<14>
ML_VGA_TXN3<14>
100MHz (SS)
2 2
100MHz (NSS)
APU_SVC<39>
APU_SVD<39>
SB-TSI
APU_RST#
12
C258 1000P_0402_50V7KC258 1000P_0402_50V7K
C83 1000P_0402_50V7KC83 1000P_0402_50V7K
+1.5VS
Close to R38 and R39
@
@
1 2
C199 0.1U_0402_16V7K
C199 0.1U_0402_16V7K
R38 1K_0402_5%@R38 1K_0402_5%@
3 3
4 4
1 2
R39 1K_0402_5%@R39 1K_0402_5%@
1 2
R47 300_0402_5%R47 300_0402_5%
1 2
R48 300_0402_5%R48 300_0402_5%
1 2
+1.5V
R40 1K_0402_5%R40 1K_0402_5%
1 2
R41 1K_0402_5%R41 1K_0402_5%
1 2
R42 1K_0402_5%R42 1K_0402_5%
1 2
R145 1K_0402_5%R145 1K_0402_5%
1 2
R146 1K_0402_5%R146 1K_0402_5%
1 2
APU_VDDNB_RUN_FB_L<39>
+1.5V
Close to JHDT
R95 1K_0402_5%R95 1K_0402_5%
1 2
R97 1K_0402_5%R97 1K_0402_5%
1 2
R100 1K_0402_5%R100 1K_0402_5%
1 2
R116 1K_0402_5%R116 1K_0402_5%
1 2
R117 300_0402_5%R117 300_0402_5%
1 2
APU_PWRGD
12
APU_SVC_R
APU_SVD_R
APU_RST#
APU_PWRGD
APU_SIC
APU_SID
APU_ALERT#
APU_SVC_R
APU_SVD_R
APU_VDD_RUN_FB_L<39>
APU_VDDNB_SENSE<39>
APU_VDD_SENSE<39>
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
A
1 2
C72 0.1U_0402_16V7KC72 0.1U_0402_16V7K
1 2
C73 0.1U_0402_16V7KC73 0.1U_0402_16V7K
1 2
C74 0.1U_0402_16V7KC74 0.1U_0402_16V7K
1 2
C75 0.1U_0402_16V7KC75 0.1U_0402_16V7K
1 2
C76 0.1U_0402_16V7KC76 0.1U_0402_16V7K
1 2
C77 0.1U_0402_16V7KC77 0.1U_0402_16V7K
1 2
C78 0.1U_0402_16V7KC78 0.1U_0402_16V7K
1 2
APU_CLKP<12>
APU_CLKN<12>
APU_DISP_CLKP<12>
APU_DISP_CLKN<12>
route on high speed layer
R216 0_0402_5%R216 0_0402_5%
1 2
R217 0_0402_5%R217 0_0402_5%
1 2
APU_SIC<9,13>
APU_SID<9,13>
APU_RST#<12>
APU_PWRGD<12>
APU_ALERT#<14>
T23T23
T22T22
Avoid leakage issue
R58 0_0402_5%R58 0_0402_5%
1 2
R212 0_0402_5%R212 0_0402_5%
1 2
R214 0_0402_5%R214 0_0402_5%
1 2
R215 0_0402_5%R215 0_0402_5%
1 2
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SVC_R
APU_SVD_R
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
APU_ALERT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
VSS_SENSE
T1T1
VDDNB_SENSE
T4T4
VDD_SENSE
T5T5
B
JAPUD
JAPUD
F2
DP0_TXP0
F1
DP0_TXN0
E3
DP0_TXP1
E2
DP0_TXN1
D2
DP0_TXP2
D1
DP0_TXN2
C2
DP0_TXP3
C3
DP0_TXN3
K2
DP1_TXP0
K1
DP1_TXN0
J3
DP1_TXP1
J2
DP1_TXN1
H2
DP1_TXP2
H1
DP1_TXN2
G2
DP1_TXP3
G3
DP1_TXN3
AH7
CLKIN_H
AH6
CLKIN_L
AH4
DISP_CLKIN_H
AH3
DISP_CLKIN_L
B8
SVC
A8
SVD
AH11
SIC
AG11
SID
AF10
RESET_L
AE10
PWROK
AD10
PROCHOT_L
AG12
THERMTRIP_L
AH12
ALERT_L
C12
TDI
A12
TDO
A11
TCK
D12
TMS
B12
TRST_L
B11
DBRDY
C11
DBREQ_L
E8
RSVD_1
K21
RSVD_2
AC11
RSVD_3
B9
VSS_SENSE
C8
VDDP_SENSE
A9
VDDNB_SENSE
B10
VDDIO_SENSE
C9
VDD_SENSE
A10
VDDR_SENSE
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
B
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST6
TEST9
TEST10
TEST12
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST21
TEST DISPLAY PORT MISC.
TEST DISPLAY PORT MISC.
TEST22
TEST23
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35
FS1R1
DMAACTIVE_L
THERMDA
TEST4
THERMDC
TEST5
C
@
@
DP0_AUXP
D4
DP0_AUXN
D5
DP1_AUXP
E5
DP1_AUXN
E6
J5
J6
H4
H5
UMA_HDMI_CLK
G5
UMA_HDMI_DATA
G6
F4
F5
DP0_HPD
D7
DP1_HPD
E7
J7
H7
DP4_HPD
G7
F7
DP_ENBKL
C6
DP_ENVDD
C5
DP_INT_PWM
C7
DP_AUX_ZVSS
D8
AA10
G10
H10
H12
D9
E9
G9
H9
APU_TEST18
H11
APU_TEST19
G11
APU_TEST20
F12
APU_TEST21
E11
APU_TEST22
D11
F10
APU_TEST24
G12
TEST25_H
AH10
TEST25_L
AH9
K7
K8
AA12
AB12
M_TEST
K22
AB11
AA11
TEST35
D10
FS1R1
Y11
DMA_ACTIVE#
AB10
AE12
AD12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Close to APU
C79 0.1U_0402_16V7KC79 0.1U_0402_16V7K
1 2
C80 0.1U_0402_16V7KC80 0.1U_0402_16V7K
1 2
C81 0.1U_0402_16V7KC81 0.1U_0402_16V7K
1 2
C82 0.1U_0402_16V7KC82 0.1U_0402_16V7K
1 2
UMA_HDMI_CLK <20>
UMA_HDMI_DATA <20>
DP0_HPD <9>
DP1_HPD <9>
DP4_HPD <9>
DP_ENBKL <9>
DP_ENVDD <9>
DP_INT_PWM <9>
R61 150_0402_1%R61 150_0402_1%
1 2
R129 1K_0402_5%R129 1K_0402_5%
1 2
T6T6
T7T7
T8T8
T9T9
R130 1K_0402_5%R130 1K_0402_5%
1 2
R131 1K_0402_5%R131 1K_0402_5%
1 2
R136 1K_0402_5%R136 1K_0402_5%
1 2
R137 1K_0402_5%R137 1K_0402_5%
1 2
R142 1K_0402_5%R142 1K_0402_5%
1 2
R152 1K_0402_5%R152 1K_0402_5%
1 2
T11T11
T12T12
T13T13
T14T14
FS1R1 will be low
for non-FS1 APU
DMA_ACTIVE# <12>
Llano do not support
T15T15
internal thermal die
T16T16
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
C
DP0_AUXP_C <17>
DP0_AUXN_C <17>
ML_VGA_AUXP <14>
ML_VGA_AUXN <14>
LVDS
CRT
HDMI
Compal Secret Data
Compal Secret Data
Compal Secret Data
AUX 2~5 are for GFX interface use,
they could be selected to DDC or
AUX logic
VDDIO level
Need level shifter
APU_PROCHOT#<12>
Thermal Shutdown Temperature:
125 degree
HDT Debug conn
Deciphered Date
Deciphered Date
Deciphered Date
D
To LVDS Translator
To FCH
+1.5V
@
@
1 2
R122 10K_0402_5%
R122 10K_0402_5%
@
@
1 2
R123 10K_0402_5%
R123 10K_0402_5%
@
@
1 2
R124 10K_0402_5%
R124 10K_0402_5%
Debug Stuff
D
APU_PROCHOT#
Change TEST35 PH to
avoid HDMI issue
design guide 2K PH P.97
Avoid leakage issue
R43
R43
1K_0402_5%
1K_0402_5%
1 2
R52
R52
1K_0402_5%
1K_0402_5%
APU_THERMTRIP#
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
JHDT
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
SAMTE_ASP-136446-07-B
SAMTE_ASP-136446-07-B
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
10K_0402_5%
10K_0402_5%
1 2
10K_0402_5%
10K_0402_5%
+1.5V
1 2
@JHDT
@
2
4
6
8
10
12
14
16
18
20
Custom
Custom
Custom
E
E
3 1
2
4
6
8
10
12
14
16
18
20
E
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
TEST25_L
TEST25_H
TEST35
M_TEST
FS1R1
DMA_ACTIVE#
UMA_HDMI_CLK
UMA_HDMI_DATA
DMA_ACTIVE#
R44
R44
R46
R46
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
12
R51
R51
10K_0402_5%
10K_0402_5%
B
B
2
Q5
Q5
C
C
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
R34 1.8K_0402_5%R34 1.8K_0402_5%
R35 1.8K_0402_5%R35 1.8K_0402_5%
R36 1.8K_0402_5%R36 1.8K_0402_5%
R37 1.8K_0402_5%R37 1.8K_0402_5%
R156 510_0402_1%R156 510_0402_1%
1 2
R160 510_0402_1%R160 510_0402_1%
1 2
R155 300_0402_5%R155 300_0402_5%
1 2
R128 300_0402_5%@R128 300_0402_5%@
1 2
R191 39.2_0402_1%@R191 39.2_0402_1%@
1 2
R192 39.2_0402_1%R192 39.2_0402_1%
1 2
R203 10K_0402_5%R203 10K_0402_5%
1 2
R49 1K_0402_5%@R49 1K_0402_5%@
1 2
R55 1K_0402_5%R55 1K_0402_5%
1 2
R57 1K_0402_5%R57 1K_0402_5%
1 2
R126 1K_0402_5%R126 1K_0402_5%
1 2
+3VS+1.5V
12
12
R45
R45
10K_0402_5%
10K_0402_5%
2
B
B
Q41
Q41
E
E
31
C
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
4019D7
4019D7
4019D7
E
12
12
12
12
H_PROCHOT# <29,34,39>
H_THERMTRIP# <13>
741Monday, May 09, 2011
741Monday, May 09, 2011
741Monday, May 09, 2011
of
of
of
+1.2VS
+1.5V
+1.5V
+3VALW
+1.5VS
+1.5V
B
B
B
A
B
C
D
E
CPU BOTTOM SIDE DECOUPLING
+CPU_CORE
C132
C132
C133
C133
C135
C135
C134
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C152
C152
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C91
C91
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
C105
C105
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
2
C128
C128
C129
C129
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C116
C116
C117
C117
1000P_0402_50V7K
1000P_0402_50V7K
1
1
2
2
C134
1
2
C153
C153
1
2
C92
C92
1
2
If the VSS plane is cut to
create a VDDIO plane,
place across the VDDIO
and VSS plane split
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1000P_0402_50V7K
1000P_0402_50V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
1 1
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C170
C170
+CPU_CORE_NB
+2.5VS_VDDA
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
C164
C164
1
12
2
+1.5V
+1.2VS
+1.2VS
3300P_0402_50V7K
3300P_0402_50V7K
1
C198
C198
180P_0402_50V8J
180P_0402_50V8J
@
@
2
2 2
3 3
+2.5VS
L1
L1
FBM_L11_201209_300LMA30T_0805
FBM_L11_201209_300LMA30T_0805
1 2
100U_B2_4VM_R35M
100U_B2_4VM_R35M
1
+
+
C196
C196
@
@
2
C165
C165
JAPUE
C1
VDD
D3
VDD
D6
VDD
E1
VDD
F3
VDD
F6
VDD
F8
VDD
G1
VDD
H3
VDD
H6
VDD
H8
VDD
J1
VDD
K3
VDD
K6
VDD
L1
VDD
L11
VDD
L19
VDD
M3
VDD
M6
VDD
M10
VDD
M18
VDD
N1
VDD
N11
VDD
N19
VDD
P3
VDD
P6
VDD
P10
VDD
P18
VDD
R1
VDD
R11
VDD
R19
VDD
T3
VDD
J9
VDDNB
J10
VDDNB
J11
VDDNB
J12
VDDNB
J14
VDDNB
J16
VDDNB
K9
VDDNB
K10
VDDNB
G28
VDDIO
H26
VDDIO
J28
VDDIO
K20
VDDIO
K23
VDDIO
K26
VDDIO
L22
VDDIO
L25
VDDIO
L28
VDDIO
M20
VDDIO
M23
VDDIO
M26
VDDIO
N22
VDDIO
N25
VDDIO
N28
VDDIO
P20
VDDIO
P23
VDDIO
P26
VDDIO
AG2
VDDP_A_1
AG3
VDDP_A_2
AG4
VDDP_A_3
AG5
VDDP_A_4
AG6
VDDR
AG7
VDDR
AG8
VDDR
AG9
VDDR
AE11
VDDA
AF11
VDDA
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
50A
22.5A
4A
3.5A
3A
0.75A
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDP_B_1
VDDP_B_2
VDDP_B_3
VDDP_B_4
VDDR
VDDR
VDDR
VDDR
@JAPUE
@
+CPU_CORE
T6
T10
T18
U1
U11
U19
V3
V6
V10
V18
W1
W11
W13
W15
W17
W19
Y3
Y6
Y10
Y12
Y14
Y16
Y18
Y20
AA1
AB3
AB6
AC1
AD3
AD6
AE1
K11
K12
K13
K14
K16
K17
K18
L18
R22
R25
R28
T20
T23
T26
U22
U25
U28
V20
V23
V26
W22
W25
W28
Y24
Y26
AA28
A3
A4
B3
B4
A5
A6
B5
B6
+CPU_CORE_NB
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C123
C123
2
180P_0402_50V8J
180P_0402_50V8J
1
C119
C119
2
C124
C124
C120
C120
1
2
1
2
1
C131
C131
2
+CPU_CORE_NB
1
C149
C149
2
+1.5V
1
C88
C88
2
+1.5V
1
C102
C102
2
VDDP Decoupling
C126
C126
C125
C125
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
VDDR Decoupling
C121
C121
C122
C122
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
2
22U_0805_6.3V6M
1
2
C150
C150
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C89
C89
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C103
C103
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
C127
C127
180P_0402_50V8J
180P_0402_50V8J
1
2
C115
C115
180P_0402_50V8J
180P_0402_50V8J
1
2
1
2
C151
C151
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C90
C90
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C104
C104
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
180P_0402_50V8J
180P_0402_50V8J
1
2
1000P_0402_50V7K
1000P_0402_50V7K
1
2
C137
C137
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
C154
C154
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
C93
C93
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
+1.2VS
1
+
+
C130
C130
330U_2.5V_M_R17
330U_2.5V_M_R17
2
C118
C118
1000P_0402_50V7K
1000P_0402_50V7K
1
2
C136
C136
C138
22U_0805_6.3V6M
22U_0805_6.3V6M
C138
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
C139
C139
C140
C140
0.01U_0402_16V7K
0.01U_0402_16V7K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
4/27 change to 330u/9m ohm on Pre-MP
C155
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+1.2VS
C155
C94
C94
C158
C158
180P_0402_50V8J
180P_0402_50V8J
1
1
2
2
C95
C95
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C160
C160
C159
C159
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
2
C96
C96
C97
C97
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
330U_D2_2V_Y
330U_D2_2V_Y
1
+
+
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
C141
C141
C201
C201
C98
C98
1
2
1
+
+
2
1
2
C142
C142
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
330U_D2_2V_Y
330U_D2_2V_Y
C99
C99
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
C143
C143
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
C100
C100
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
2
C145
C145
C144
C144
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
2
C101
C101
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
1
2
C146
C146
330U_D2_2V_Y
330U_D2_2V_Y
1
1
+
+
+
+
2
2
1
+
+
C106
C106
330U_2.5V_M_R17
330U_2.5V_M_R17
2
330U_D2_2V_Y
330U_D2_2V_Y
C147
C147
C148
C148
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
+
+
+
+
2
2
JAPUF
A7
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
A25
VSS
B7
VSS
C4
VSS
C10
VSS
C14
VSS
C16
VSS
C18
VSS
C20
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D25
VSS
D27
VSS
E4
VSS
E10
VSS
E12
VSS
F9
VSS
F11
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
G4
VSS
G8
VSS
G13
VSS
G15
VSS
G17
VSS
G19
VSS
G21
VSS
G23
VSS
G25
VSS
J4
VSS
J8
VSS
J18
VSS
J20
VSS
J22
VSS
J24
VSS
K19
VSS
L4
VSS
L7
VSS
L10
VSS
M9
VSS
M11
VSS
M19
VSS
N4
VSS
N7
VSS
N10
VSS
N18
VSS
P9
VSS
P11
VSS
P19
VSS
R4
VSS
R7
VSS
R10
VSS
R18
VSS
T9
VSS
AMD_TOPEDO_FS-1
AMD_TOPEDO_FS-1
@JAPUF
@
T11
VSS
T19
VSS
U4
VSS
U7
VSS
U10
VSS
U18
VSS
V9
VSS
V11
VSS
V19
VSS
W4
VSS
W7
VSS
W10
VSS
W12
VSS
W14
VSS
W16
VSS
W18
VSS
Y9
VSS
Y22
VSS
AA4
VSS
AA7
VSS
AB9
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB25
VSS
AB27
VSS
AC4
VSS
AC7
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC20
VSS
AC22
VSS
AC24
VSS
AC26
VSS
AC28
VSS
AD9
VSS
AD11
VSS
AE4
VSS
AE7
VSS
AE13
VSS
AE15
VSS
AE17
VSS
AE19
VSS
AE21
VSS
AE23
VSS
AE25
VSS
AE27
VSS
AF3
VSS
AF6
VSS
AF9
VSS
AF12
VSS
AF14
VSS
AF16
VSS
AF18
VSS
AF20
VSS
AF22
VSS
AF24
VSS
AF26
VSS
AF28
VSS
AG10
VSS
AH5
VSS
AH8
VSS
AH13
VSS
AH15
VSS
AH17
VSS
AH19
VSS
AH21
VSS
AH23
VSS
AH25
VSS
C112
C112
C111
C111
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
C114
C114
2
4 4
A
B
1
1
2
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
C113
C113
C107
C107
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
1
1
2
2
C109
C109
C110
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C110
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
2
2
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
C
VDD:
470uF x 6
22uF x 9
0.22uF x 2
0.01uF x 3
180pF x 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C108
C108
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CRB Decoupling Capacitor (include PWM side)：
VDDNB:
470uF x 4
22uF x 6
0.22uF x 2
180pF x 3
D
VDDIO:
680uF x 1
330uF x 1
22uF x 2
4.7uF x 4
0.22uF x 8
180pF x 4
VDDP/R_PWM:
470uF x 2
10uF x 1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VDDP:
10uF x 3
0.22uF x 2
180pF x 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
VDDR:
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
E
VDDA:
100uF x 1
4.7uF x 1
0.22uF x 1
3.3nF x 1
841Monday, May 09, 2011
841Monday, May 09, 2011
841Monday, May 09, 2011
of
of
of
B
B
B
5
4
3
2
1
HPD
D D
C C
Translator HPD
From Translator or Conn
LVDS_HPD<17> DP0_HPD <7>
LVDS_HPD
R207 100K_0402_5%R207 100K_0402_5%
CRT HPD
From FCH
FCH_CRT_HPD<14> DP1_HPD <7>
FCH_CRT_HPD
R64 100K_0402_5%R64 100K_0402_5%
HDMI HPD
From HDMI Conn
HDMI_HPD<13,20> DP4_HPD <7>
HDMI_HPD
R204 100K_0402_5%R204 100K_0402_5%
12
12
12
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
R54
R54
1 2
B
B
E
E
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
+3VS
R150
R150
1 2
B
B
E
E
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
+3VS
R267
R267
1 2
B
B
E
E
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
12
R59
R59
10K_0402_5%
10K_0402_5%
2
Q26
Q26
C
C
12
R62
R62
10K_0402_5%
10K_0402_5%
2
Q16
Q16
C
C
12
R208
R208
10K_0402_5%
10K_0402_5%
2
Q27
Q27
C
C
+1.5VS
12
R60
R60
4.7K_0402_5%
4.7K_0402_5%
+1.5VS
12
R63
R63
4.7K_0402_5%
4.7K_0402_5%
+1.5VS
12
R210
R210
4.7K_0402_5%
4.7K_0402_5%
Panel ENBKL
DP_ENBKL<7>
Panel ENVDD
DP_ENVDD<7>
@ R65
@
1 2
@ R69
@
R65
100K_0402_5%
100K_0402_5%
@
@
1 2
R66 2.2K_0402_5%
R66 2.2K_0402_5%
@
@
1 2
R71 2.2K_0402_5%
R71 2.2K_0402_5%
R69
100K_0402_5%
100K_0402_5%
1 2
+3VS
R67
@ R67
@
100K_0402_5%
100K_0402_5%
1 2
C
C
Q15
Q15
2
B
B
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
E
E
3 1
@
@
+3VS
@ R74
@
2
B
B
E
E
@
@
12
R68
@ R68
@
4.7K_0402_5%
4.7K_0402_5%
61
Q14A
Q14A
2N7002DW-T/R7_SOT363-6@
2N7002DW-T/R7_SOT363-6@
2
@ R75
@
R74
100K_0402_5%
100K_0402_5%
1 2
5
C
C
Q28
Q28
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
3 1
12
R75
4.7K_0402_5%
4.7K_0402_5%
3
Q14B
Q14B
2N7002DW-T/R7_SOT363-6@
2N7002DW-T/R7_SOT363-6@
4
APU_ENBKL <18>
APU_ENVDD <18>
B B
SB-TSI
Panel PWM
+3VS
Need to confirm R93 value
4.7K or 47K
Q37
Q37
Q42
Q42
Vgs of BSH111 :
Min = 0.4V
Max = 1.3V
4
EC_SMB_DA2 <29,30>
EC_SMB_CK2 <29,30>
12
R92
R92
47K_0402_5%
47K_0402_5%
C
C
Q21
DP_INT_PWM<7>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
R89 2.2K_0402_5%R89 2.2K_0402_5%
12
R76
R76
4.7K_0402_5%
4.7K_0402_5%
Compal Secret Data
Compal Secret Data
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
Compal Secret Data
Q21
2
B
B
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
E
E
3 1
Deciphered Date
Deciphered Date
Deciphered Date
2
G
G
12
R93
R93
47K_0402_5%
47K_0402_5%
13
D
D
Q35
Q35
2N7002_SOT23-3
2N7002_SOT23-3
S
S
2
APU_INVT_PWM <17,18>
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
1
B
B
B
of
of
of
941Monday, May 09, 2011
941Monday, May 09, 2011
941Monday, May 09, 2011
+1.5VS
12
12
R219
R219
R218
2
Q22
Q22
APU_SID<7,13>
A A
APU_SIC<7,13>
5
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
2
Q25
Q25
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
31
31
R218
2.2K_0402_5%
2.2K_0402_5%
APU_SID_Q
APU_SIC_Q
2.2K_0402_5%
2.2K_0402_5%
2
3 1
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
2
3 1
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
5
+VREF_DQA
D D
C C
B B
A A
+3VS
DDR_A_SCS1#<6>
C181
C181
DDR_A_BS2<6>
DDR_A_CLK0<6>
DDR_A_CLK0#<6>
DDR_A_BS0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
1
C182
C182
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
R90
R90
1 2
10K_0402_5%
10K_0402_5%
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
+0.75VS
12
R91
R91
10K_0402_5%
10K_0402_5%
+1.5V
JDDRH
JDDRH
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
LOTES_AAA-DDR-111-K01_204P
LOTES_AAA-DDR-111-K01_204P
@
@
BOSS1
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
BOSS1
BOSS2
VSS
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
CK1
VDD
BA1
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
4
+1.5V
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
MEM_MA_RST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_CKE1
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDR_A_SCS0#
DDR_A_ODT0
DDR_A_ODT1
+VREF_CAA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
MEM_MA_EVENT#
FCH_SDATA0
FCH_SCLK0
+0.75VS
4
DDR3 SO-DIMM A
Standard Type
MEM_MA_RST# <6>
DDR_A_CKE1 <6>DDR_A_CKE0<6>
DDR_A_CLK1 <6>
DDR_A_CLK1# <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDR_A_SCS0# <6>
DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
1
C66
C66
1000P_0402_50V7K
1000P_0402_50V7K
Close to JDDRH.126
MEM_MA_EVENT# <6>
FCH_SDATA0 <11,13,23>
FCH_SCLK0 <11,13,23>
1
C162
C162
C161
C161
0.1U_0402_16V7K
0.1U_0402_16V7K
2.2U_0603_6.3V6K
2
Issued Date
Issued Date
Issued Date
2.2U_0603_6.3V6K
2
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+VREF_DQA
DDR_A_DQS[0..7] <6>
DDR_A_DQS#[0..7] <6>
DDR_A_D[0..63] <6>
DDR_A_MA[0..15] <6>
DDR_A_DM[0..7] <6>
1
1
C157
C156
C156
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C157
2
C65
C65
1000P_0402_50V7K
1000P_0402_50V7K
Close to JDDRH.1
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
+1.5V
12
R79
R79
1K_0402_1%
1K_0402_1%
12
R81
R81
1K_0402_1%
1K_0402_1%
@
@
4/27 For ESD request Pre-MP
+1.5V
C343 0.1U_0402_16V4ZC343 0.1U_0402_16V4Z
C344 0.1U_0402_16V4ZC344 0.1U_0402_16V4Z
C345 0.1U_0402_16V4ZC345 0.1U_0402_16V4Z
C346 0.1U_0402_16V4ZC346 0.1U_0402_16V4Z
C347 0.1U_0402_16V4ZC347 0.1U_0402_16V4Z
C348 0.1U_0402_16V4ZC348 0.1U_0402_16V4Z
C349 0.1U_0402_16V4ZC349 0.1U_0402_16V4Z
C350 0.1U_0402_16V4ZC350 0.1U_0402_16V4Z
+1.5V
C223 33P_0402_50V8JC223 33P_0402_50V8J
C224 33P_0402_50V8JC224 33P_0402_50V8J
C247 33P_0402_50V8JC247 33P_0402_50V8J
C251 33P_0402_50V8JC251 33P_0402_50V8J
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
For EMI request
1 2
1 2
1 2
1 2
Place equally on moat
+1.5V
12
R80
R80
1K_0402_1%
1K_0402_1%
12
1
R82
R82
@
@
1K_0402_1%
1K_0402_1%
2
Compal Secret Data
Compal Secret Data
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
3
Compal Secret Data
Layout Note:
Place near JDDRH
+1.5V
C218 330U_D2_2VM_R9M
C218 330U_D2_2VM_R9M
C166 0.1U_0402_16V4ZC166 0.1U_0402_16V4Z
C168 0.1U_0402_16V4ZC168 0.1U_0402_16V4Z
C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z
C174 0.1U_0402_16V4ZC174 0.1U_0402_16V4Z
C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z
C176 0.1U_0402_16V4ZC176 0.1U_0402_16V4Z
C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z
C178 0.1U_0402_16V4ZC178 0.1U_0402_16V4Z
C185 0.1U_0402_16V4ZC185 0.1U_0402_16V4Z
C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z
Deciphered Date
Deciphered Date
Deciphered Date
+
+
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SGA20331E10
Layout Note:
Place near JDDRH.203 and 204
+0.75VS
C85 0.1U_0402_16V4Z
C85 0.1U_0402_16V4Z
C84 4.7U_0603_6.3V6KC84 4.7U_0603_6.3V6K
C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z
C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
3/22 For EMI request PVT
+1.5V
C21 47P_0402_50V8JC21 47P_0402_50V8J
1 2
C20 47P_0402_50V8JC20 47P_0402_50V8J
1 2
C22 47P_0402_50V8JC22 47P_0402_50V8J
1 2
C23 47P_0402_50V8JC23 47P_0402_50V8J
1 2
Place equally on moat
+1.5V
@
@
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
10 41Monday, May 09, 2011
10 41Monday, May 09, 2011
10 41Monday, May 09, 2011
1
B
B
B
of
of
of
A
+VREF_DQB
1 1
DDR_B_CKE0<6>
2 2
3 3
4 4
+3VS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C207
C207
@
@
DDR_B_BS2<6>
DDR_B_CLK0<6>
DDR_B_CLK0#<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_B_SCS1#<6>
1
2
1
C208
C208
2
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R98
R98
1 2
10K_0402_5%
10K_0402_5%
+0.75VS
R99
R99
10K_0402_5%
10K_0402_5%
1 2
+1.5V
JDDRL
JDDRL
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
LOTES_AAA-DDR-109-K01_204P
LOTES_AAA-DDR-109-K01_204P
@
@
BOSS1
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND2
BOSS1
BOSS2
VSS
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
CK1
VDD
BA1
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
A15
A14
A11
A7
A6
A4
A2
A0
S0#
NC
Change SODIMM1 SMB address to A2 01/25
A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
B
+1.5V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
MEM_MB_RST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_CKE1
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDR_B_SCS0#
DDR_B_ODT0
DDR_B_ODT1
+VREF_CAB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
MEM_MB_EVENT#
FCH_SDATA0
FCH_SCLK0
+0.75VS
B
DDR3 SO-DIMM B
Standard Type
MEM_MB_RST# <6>
DDR_B_CKE1 <6>
DDR_B_CLK1 <6>
DDR_B_CLK1# <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>DDR_B_BS0<6>
DDR_B_SCS0# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1
C68
C68
C188
C188
1000P_0402_50V7K
1000P_0402_50V7K
2
Close to JDDRL.126
MEM_MB_EVENT# <6>
FCH_SDATA0 <10,13,23>
FCH_SCLK0 <10,13,23>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
1
C187
C187
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2
C
+VREF_DQB
1
C67
C67
1000P_0402_50V7K
1000P_0402_50V7K
2
Close to JDDRL.1
+1.5V
12
R86
R86
1K_0402_1%
1K_0402_1%
12
R94
R94
@
@
1K_0402_1%
1K_0402_1%
+1.5V
C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z
C169 0.1U_0402_16V4ZC169 0.1U_0402_16V4Z
C172 0.1U_0402_16V4ZC172 0.1U_0402_16V4Z
C175 0.1U_0402_16V4ZC175 0.1U_0402_16V4Z
C195 0.1U_0402_16V4ZC195 0.1U_0402_16V4Z
C177 0.1U_0402_16V4ZC177 0.1U_0402_16V4Z
C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z
C191 0.1U_0402_16V4ZC191 0.1U_0402_16V4Z
C192 0.1U_0402_16V4ZC192 0.1U_0402_16V4Z
C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DDR_B_DQS#[0..7] <6>
DDR_B_DQS[0..7] <6>
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
DDR_B_DM[0..7] <6>
1
C184
C184
Layout Note:
Place near JDDRH
1
C183
C183
0.1U_0402_16V7K
0.1U_0402_16V7K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
D
+1.5V
12
1K_0402_1%
1K_0402_1%
12
1K_0402_1%
1K_0402_1%
D
R83
R83
R84
R84
E
Layout Note:
Place near JDDRH.203 and 204
+0.75VS
@
@
C87 0.1U_0402_16V4Z
C87 0.1U_0402_16V4Z
1 2
C86 4.7U_0603_6.3V6KC86 4.7U_0603_6.3V6K
1 2
C194 0.1U_0402_16V4ZC194 0.1U_0402_16V4Z
1 2
C206 0.1U_0402_16V4ZC206 0.1U_0402_16V4Z
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
+1.5V
of
of
of
11 41Monday, May 09, 2011
11 41Monday, May 09, 2011
11 41Monday, May 09, 2011
E
B
B
B
A
APU_PCIE_RST#_R
LPC_RST#_R
R229
R229
1M_0402_5%
1M_0402_5%
Y2
Y2
4
OSC
1
OSC
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
PCIE_CALRP
PCIE_CALRN
PCIE_MTX_USBRX_P1
PCIE_MTX_USBRX_N1
PCIE_MTX_CRRX_P2
PCIE_MTX_CRRX_N2
PCIE_MRX_C_USBTX_P1
PCIE_MRX_C_USBTX_N1
PCIE_MRX_C_CRTX_P2
PCIE_MRX_C_CRTX_N2
CLK_CALRN
APU_DISP_CLKP
APU_DISP_CLKN
TRAVIS_CLKP
TRAVIS_CLKN
APU_CLKP
APU_CLKN
CLK_CR
CLK_CR#
CLK_WLAN
CLK_WLAN#
CLK_LAN
CLK_LAN#
CLK_USB30
CLK_USB30#
3
NC
2
NC
C202 0.1U_0402_16V7KC202 0.1U_0402_16V7K
UMI_MTX_C_FRX_P0<5>
UMI_MTX_C_FRX_N0<5>
UMI_MTX_C_FRX_P1<5>
UMI_MTX_C_FRX_N1<5>
UMI_MTX_C_FRX_P2<5>
UMI_MTX_C_FRX_N2<5>
UMI_MTX_C_FRX_P3<5>
1 1
USB3.0
Cardreader
2 2
UMI_MTX_C_FRX_N3<5>
UMI_FTX_C_MRX_P0<5>
UMI_FTX_C_MRX_N0<5>
UMI_FTX_C_MRX_P1<5>
UMI_FTX_C_MRX_N1<5>
UMI_FTX_C_MRX_P2<5>
UMI_FTX_C_MRX_N2<5>
UMI_FTX_C_MRX_P3<5>
UMI_FTX_C_MRX_N3<5>
+PCIE_VDDR_FCH
PCIE_MTX_C_USBRX_P1<26>
PCIE_MTX_C_USBRX_N1<26>
PCIE_MTX_C_CRRX_P2<25>
PCIE_MTX_C_CRRX_N2<25>
PCIE_MRX_C_USBTX_P1<26>
PCIE_MRX_C_USBTX_N1<26>
PCIE_MRX_C_CRTX_P2<25>
PCIE_MRX_C_CRTX_N2<25>
+1.1VS_CKVDD
SS
APU Display
NSS
LVDS translator
APU
Cardreader
WLAN
SS
LAN
3 3
4 4
JET
USB3.0
A
C220 27P_0402_50V8JC220 27P_0402_50V8J
1 2
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
1 2
C230 27P_0402_50V8JC230 27P_0402_50V8J
C248 15P_0402_50V8JC248 15P_0402_50V8J
1 2
20M_0402_5%
20M_0402_5%
1 2
C249 15P_0402_50V8JC249 15P_0402_50V8J
1 2
C203 0.1U_0402_16V7KC203 0.1U_0402_16V7K
1 2
C204 0.1U_0402_16V7KC204 0.1U_0402_16V7K
1 2
C209 0.1U_0402_16V7KC209 0.1U_0402_16V7K
1 2
C210 0.1U_0402_16V7KC210 0.1U_0402_16V7K
1 2
C211 0.1U_0402_16V7KC211 0.1U_0402_16V7K
1 2
C213 0.1U_0402_16V7KC213 0.1U_0402_16V7K
1 2
C212 0.1U_0402_16V7KC212 0.1U_0402_16V7K
1 2
R220 590_0402_1%R220 590_0402_1%
1 2
R221 2K_0402_1%R221 2K_0402_1%
1 2
RENE@
RENE@
C214 0.1U_0402_16V7K
C214 0.1U_0402_16V7K
1 2
C215 0.1U_0402_16V7KRENE@C215 0.1U_0402_16V7KRENE@
1 2
C216 0.1U_0402_16V7KC216 0.1U_0402_16V7K
1 2
C219 0.1U_0402_16V7KC219 0.1U_0402_16V7K
1 2
R228 2K_0402_1%R228 2K_0402_1%
1 2
Input from external clock generator
NC for internal clock generator
APU_DISP_CLKP<7>
APU_DISP_CLKN<7>
TRAVIS_CLKP<17>
TRAVIS_CLKN<17>
APU_CLKP<7>
APU_CLKN<7>
CLK_CR<25>
CLK_CR#<25>
CLK_WLAN<23>
CLK_WLAN#<23>
CLK_LAN<24>
CLK_LAN#<24>
CLK_USB30<26>
CLK_USB30#<26>
12
Y1
Y1
12
R230
R230
32.768KHZ_12.5PF_Q13MC14610002
32.768KHZ_12.5PF_Q13MC14610002
B
U1A
U1A
AE2
PCIE_RST#
AD5
A_RST#
AE30
UMI_TX0P
AE32
UMI_TX0N
AD33
UMI_TX1P
AD31
UMI_TX1N
AD28
UMI_TX2P
AD29
UMI_TX2N
AC30
UMI_TX3P
AC32
UMI_TX3N
AB33
UMI_RX0P
AB31
UMI_RX0N
AB28
UMI_RX1P
AB29
UMI_RX1N
Y33
UMI_RX2P
Y31
UMI_RX2N
Y28
UMI_RX3P
Y29
UMI_RX3N
AF29
PCIE_CALRP
AF31
PCIE_CALRN
V33
GPP_TX0P
V31
GPP_TX0N
W30
GPP_TX1P
W32
GPP_TX1N
AB26
GPP_TX2P
AB27
GPP_TX2N
AA24
GPP_TX3P
AA23
GPP_TX3N
AA27
GPP_RX0P
AA26
GPP_RX0N
W27
GPP_RX1P
V27
GPP_RX1N
V26
GPP_RX2P
W26
GPP_RX2N
W24
GPP_RX3P
W23
GPP_RX3N
F27
CLK_CALRN
G30
PCIE_RCLKP
G28
PCIE_RCLKN
R26
DISP_CLKP
T26
DISP_CLKN
H33
DISP2_CLKP
H31
DISP2_CLKN
T24
APU_CLKP
T23
APU_CLKN
J30
SLT_GFX_CLKP
K29
SLT_GFX_CLKN
H27
GPP_CLK0P
H28
GPP_CLK0N
J27
GPP_CLK1P
K26
GPP_CLK1N
F33
GPP_CLK2P
F31
GPP_CLK2N
E33
GPP_CLK3P
E31
GPP_CLK3N
25M_X1
25M_X2
32K_X1
32K_X2
B
M23
M24
M27
M26
N25
N26
R23
R24
N27
R27
J26
C31
C33
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
14M_25M_48M_OSC
25M_X1
25M_X2
HUDSON-M3_FCBGA656
HUDSON-M3_FCBGA656
T66T66
T67T67
HUDSON-2
HUDSON-2
PCI CLKS
PCI CLKS
PCICLK4/14M_OSC/GPO39
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
PCI INTERFACE
PCI INTERFACE
INT PU 15K
INT PU 8.2K
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
INT PU 8.2K
CLOCK GENERATOR
CLOCK GENERATOR
LPCAPUS5 PLUS
LPCAPUS5 PLUS
INT PU 8.2K
LDRQ1#/CLK_REQ6#/GPIO49
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
SERIRQ/GPIO48
INTRUDER_ALERT#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HUDM3R3@
HUDM3R3@
PCICLK0
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
GNT0#
GNT1#/GPO44
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
S5_CORE_EN
RTCCLK
VDDBT_RTC_G
32K_X1
32K_X2
C
C
AF3
PCI_CLK1
AF1
AF5
PCI_CLK3
AG2
PCI_CLK4
AF6
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
PCI_AD23
AE12
PCI_AD24
AC12
PCI_AD25
AE13
PCI_AD26
AF13
PCI_AD27
AH13
AH14
AD15
AC15
FELICA_PWR
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
AF18
AE18
AC16
AD18
B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
G25
E28
E26
G26
F26
H7
F1
F3
E6
G2
G4
1 2
R283 8.2K_0402_5%R283 8.2K_0402_5%
LPC_CLK0
LPC_CLK1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SERIRQ
DMA_ACTIVE#
APU_PROCHOT#_R
APU_PWRGD
APU_RST#
RTC_CLK_R
+RTCVCC_R
32K_X1
32K_X2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
PCI_CLK1 <15>
PCI_CLK3 <15>
PCI_CLK4 <15>
PCI_AD23 <15>
PCI_AD24 <15>
PCI_AD25 <15>
PCI_AD26 <15>
PCI_AD27 <15>
FELICA_PWR
CLKREQ_USB30# <26>
+3VS
R255 22_0402_5%R255 22_0402_5%
1 2
R258 22_0402_5%R258 22_0402_5%
1 2
1 2
R259 0_0402_5%R259 0_0402_5%
T25T25
1 2
R260 0_0402_5%R260 0_0402_5%
20 mils
1
C250
C250
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
2
2
Deciphered Date
Deciphered Date
Deciphered Date
Strap
Strap
C252
C252
1U_0402_6.3V6K
1U_0402_6.3V6K
D
APU_PCIE_RST#_R
place close to FCH
LPC_RST#_R
12
R72 100K_0402_5%R72 100K_0402_5%
CLK_PCI_EC <15,29>
CLK_PCI_DDR <15,30>
LPC_AD0 <29,30>
LPC_AD1 <29,30>
LPC_AD2 <29,30>
LPC_AD3 <29,30>
LPC_FRAME# <29,30>
SERIRQ <29>
DMA_ACTIVE# <7>
APU_PROCHOT# <7>
APU_PWRGD <7>
APU_RST# <7>
RTC_CLK <15,29>
R271
R271
1 2
120_0402_5%
120_0402_5%
+RTCVCC
CMOS Setting
Place under DDR
Door
D
12
R225 33_0402_5%R225 33_0402_5%
R226 33_0402_5%R226 33_0402_5%
Strap
Strap
R355
R355
1 2
120_0402_5%
120_0402_5%
JCMOS@JCMOS
@
E
PCIE_RST# is for PCIE devices on APU
1 2
C221
C221
150P_0402_50V8J
150P_0402_50V8J
1
2
R223
R223
100K_0402_5%
100K_0402_5%
@
@
1 2
APU_PCIE_RST# <17,23,24>
A_RST# is for LPC devices
1 2
C222
C222
150P_0402_50V8J
150P_0402_50V8J
1
2
R224
R224
100K_0402_5%
100K_0402_5%
@
@
1 2
LPC_RST# <29,30>
For ESD request 3/24
APU_PWRGD
APU_RST#
+3VS+1.5VS
12
R269
R269
10K_0402_5%
10K_0402_5%
B
B
2
Q46
Q46
E
APU_PWRGD
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
S5_CORE_EN is for S5+ mode
used to turn off +1.1VALW and
+3VALW of FCH on S5+ mode
+RTCBATT_R +RTCBATT_D
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R268
R268
1 2
1K_0402_5%
1K_0402_5%
1
C256
C256
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
12
C332 100P_0402_50V8JC332 100P_0402_50V8J
12
C333 100P_0402_50V8JC333 100P_0402_50V8J
R270
R270
4.7K_0402_5%
4.7K_0402_5%
1 2
1
D13
D13
BAS40-04_SOT23-3
BAS40-04_SOT23-3
2
3
E
APU_PWRGD_L <39>
+RTCBATT
+3VL
of
of
of
12 41Monday, May 09, 2011
12 41Monday, May 09, 2011
12 41Monday, May 09, 2011
B
B
B
A
FCH_PCIE_RST#<25,26>
1 1
+3VS
1 2
R301 8.2K_0402_5%
R301 8.2K_0402_5%
SM Bus 0-->S0 PWR domain
SM Bus 1-->S5 PWR domain
(for ASF device only)
VGA_PD: Support CRT power saving
L: MLDAC power on
2 2
H: MLDAC power off
PEG_CLKREQ#
@
@
H_THERMTRIP#<7>
CLKREQ_LAN#<24>
USB_OC1# is for USB port10
USB_OC0# is for USB port0 and port1
AZ_BITCLK_HD<27>
AZ_SDOUT_HD<27>
AZ_SDIN0_HD<27>
AZ_SYNC_HD<27>
AZ_RST_HD#<27>
+3VALW
3 3
4 4
1 2
R421 10K_0402_5%R421 10K_0402_5%
1 2
R293 10K_0402_5%
R293 10K_0402_5%
1 2
R278 10K_0402_5%R278 10K_0402_5%
1 2
R288 10K_0402_5%R288 10K_0402_5%
1 2
R289 10K_0402_5%R289 10K_0402_5%
1 2
R272 10K_0402_5%
R272 10K_0402_5%
1 2
R276 10K_0402_5%R276 10K_0402_5%
1 2
R306 10K_0402_5%
R306 10K_0402_5%
1 2
R318 10K_0402_5%R318 10K_0402_5%
1 2
R319 10K_0402_5%R319 10K_0402_5%
+3VS
1 2
R286 2.2K_0402_5%R286 2.2K_0402_5%
1 2
R287 2.2K_0402_5%R287 2.2K_0402_5%
1 2
R291 8.2K_0402_5%
R291 8.2K_0402_5%
1 2
R290 8.2K_0402_5%
R290 8.2K_0402_5%
1 2
R281 8.2K_0402_5%
R281 8.2K_0402_5%
1 2
R284 8.2K_0402_5%
R284 8.2K_0402_5%
R280 100K_0402_5%R280 100K_0402_5%
1 2
R324 10K_0402_5%
R324 10K_0402_5%
1 2
R325 10K_0402_5%
R325 10K_0402_5%
@
@
@
@
RENE@
RENE@
@
@
@
@
@
@
@
@
@
@
@
@
CR_CPPE#
VGA_PD_FCH
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
EC_LID_OUT#
FCH_PCIE_WAKE#
USB30_SMI#
USB_OC0#
USB_OC1#
FCH_SCLK0
FCH_SDATA0
CLKREQ_WLAN#
CLKREQ_JET#
CLKREQ_CR#
R282 1K_0402_5%R282 1K_0402_5%
CLKREQ_LAN#_R
EC_RSMRST#
12
HDA_BITCLK
AZ_SDIN0_HD
A
Close to FCH
R227 100K_0402_5%@R227 100K_0402_5%@
C19 150P_0402_50V8JC19 150P_0402_50V8J
1 2
VGA_PD<15>
Change ACIN to low
active for ACIN LED
issue with PEQAE
Set cardreader clock
as free-running
12
12
EC_LID_OUT#<29>
SLP_S3#<29>
SLP_S5#<29>
PBTN_OUT#<29>
FCH_PWRGD<29>
GATEA20<29>
KB_RST#<29>
EC_SCI#<29>
EC_SMI#<29>
FCH_PCIE_WAKE#<24,26>
1 2
+3VS
R279 10K_0402_5%R279 10K_0402_5%
EC_RSMRST#<29>
@
@
CLKREQ_JET#<23>
21
D17 RB751V40_SC76-2
D17 RB751V40_SC76-2
1 2
R361 0_0402_5%R361 0_0402_5%
FCH_SPKR<27>
FCH_SCLK0<10,11,23>
FCH_SDATA0<10,11,23>
CLKREQ_WLAN#<23>
R292 0_0402_5%@R292 0_0402_5%@
1 2
USB30_SMI#<26>
ODD_PLUGIN#<21>
CR_CPPE#<25>
USB_OC1#<23,26,29>
USB_OC0#<21,29>
R320 33_0402_5%R320 33_0402_5%
1 2
R321 33_0402_5%R321 33_0402_5%
1 2
R322 33_0402_5%R322 33_0402_5%
1 2
R323 33_0402_5%R323 33_0402_5%
1 2
ACIN<29,31,35>
B
PCIE_RST2# is for PCIE devices on FCH
R222
R222
33_0402_5%
33_0402_5%
FCH_PCIE_RST#_R
1 2
EC_LID_OUT#
SLP_S3#
SLP_S5#
PBTN_OUT#
FCH_PWRGD
TEST0
TEST1
TEST2
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
T31T31
FCH_PCIE_WAKE#
T60T60
H_THERMTRIP#
WD_PWRGD
EC_RSMRST#
CLKREQ_JET#
CLKREQ_LAN#_R
CLKREQ_CR#
FCH_SPKR
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
CLKREQ_WLAN#
T30T30
VGA_PD_FCH
T58T58
HDMI_HPD_Q
PEG_CLKREQ#
USB30_SMI#
ODD_DA#_FCH
T61T61
CR_CPPE#
USB_OC1#
USB_OC0#
HDA_BITCLK
HDA_SDOUT
AZ_SDIN0_HD
HDA_SYNC
HDA_RST#
T26T26
T27T27
ACIN_FCH#
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
Q208B
Q208B
T33T33
4
T32T32
T35T35
T34T34
T37T37
T36T36
T38T38
T39T39
T45T45
T44T44
T46T46
T47T47
T41T41
T40T40
T42T42
T43T43
T49T49
T48T48
For FCH internal debug use
+3VALW
(Internal 10K pull-down)
@
@
1 2
R273 2.2K_0402_5%
R273 2.2K_0402_5%
@
@
1 2
R274 2.2K_0402_5%
R274 2.2K_0402_5%
@
@
1 2
R275 2.2K_0402_5%
R275 2.2K_0402_5%
B
U1D
U1D
AB6
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVENT2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
AE24
CLK_REQ3#/SATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/SATA_IS3#/GPIO60
AH17
SATA_IS4#/FANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN#/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GPIO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GPIO167
Y5
AZ_SDIN1/GPIO168
Y3
AZ_SDIN2/GPIO169
Y1
AZ_SDIN3/GPIO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/SDA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
HUDSON-M3_FCBGA656
HUDSON-M3_FCBGA656
TEST0
TEST1
TEST2
C
HUDM3R3@
HUDSON-2
HUDSON-2
INT PU 10K
USBCLK/14M_25M_48M_OSC
USB MISCUSB 1.1USB 2.0USB 3.0
USB MISCUSB 1.1USB 2.0USB 3.0
INT PD 15K
INT PU8.2K
INT PU8.2K
INT PU10K
INT PU8.2K
INT PU10K
INT PU10K
INT PU10K
INT PU10K
INT PU10K
INT PU8.2K
INT PU8.2K
INT PU8.2K
INT PU8.2K
INT PU8.2K
INT PU8.2K
INT PU10K
INT PU8.2K
INT PU8.2K
INT PU10K
INT PU10K
INT PU10K
INT PU8.2K
INT PU10K
INT PU10K
INT PU10K
INT PU10K
INT PU10K
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
INT PU10K
INT PU10K
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
INT PU10K
INT PD 50K
INT PU 10K
INT PU 10K
EMBEDDED CTRL
EMBEDDED CTRL
INT PU 10K
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
INT PU 10K
INT PU 10K
+3VS
G
G
S
HDMI_HPD<9,20>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
S
2N7002_SOT23-3
2N7002_SOT23-3
C
+3VALW
2
Q39
Q39
CEC@
CEC@
13
D
D
2011/01/11 2011/11/11
2011/01/11 2011/11/11
2011/01/11 2011/11/11
HUDM3R3@
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
R313
R313
10K_0402_5%
10K_0402_5%
@
@
1 2
HDMI_HPD_Q
Compal Secret Data
Compal Secret Data
Compal Secret Data
G8
USB_RCOMP
B9
H1
H3
H6
H5
H10
G10
K10
J12
G12
F12
USB20_P10
K12
USB20_N10
K13
B11
D11
USB20_P8
E10
USB20_N8
F10
USB20_P7
C10
USB20_N7
A10
USB20_P6
H9
USB20_N6
G9
USB20_P5
A8
USB20_N5
C8
F8
E8
C6
A6
C5
A5
USB20_P1
C1
USB20_N1
C3
USB20_P0
E1
USB20_N0
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
A14
C14
C12
A12
D15
B15
E14
F14
F15
G15
H13
G13
USB30_TX0P
J16
USB30_TX0N
H16
USB30_RX0P
J15
USB30_RX0N
K15
R326 10K_0402_5%R326 10K_0402_5%
H19
R328 10K_0402_5%R328 10K_0402_5%
G19
FCH_SIC
G22
FCH_SID
G21
E22
H22
EC_PWM2
J22
H21
K21
K22
F22
F24
E24
B23
C24
F18
Deciphered Date
Deciphered Date
Deciphered Date
D
R329 11.8K_0402_1%R329 11.8K_0402_1%
1 2
R330 1K_0402_1%M3@R330 1K_0402_1%M3@
1 2
R334 1K_0402_1%
R334 1K_0402_1%
1 2
1 2
1 2
1 2
R338 0_0402_5%R338 0_0402_5%
1 2
R343 0_0402_5%R343 0_0402_5%
Place R425 and C363
close to FCH for ESD
ODD_DA#_FCH
1
C363
C363
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
D
USB20_P10 <23>
USB20_N10 <23>
USB20_P8 <23>
USB20_N8 <23>
USB20_P7 <22>
USB20_N7 <22>
USB20_P6 <23>
USB20_N6 <23>
USB20_P5 <18>
USB20_N5 <18>
USB20_P1 <21>
USB20_N1 <21>
USB20_P0 <21>
USB20_N0 <21>
M3@
M3@
USB30_TX0P <26>
USB30_TX0N <26>
USB30_RX0P <26>
USB30_RX0N <26>
EC_PWM2 <15>
1 2
R425 0_0402_5%R425 0_0402_5%
E
Hudson-M2/M3
OHCI (DEV-20, FUN-5)
Hudson-M2
OHCI (DEV-22, FUN-0)
EHCI (DEV-22, FUN-2)
USB 3.0
(For Hudson M3 only)
WLAN (BT)
Finger Printer
Hudson-M3
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)
Hudson-M2/M3
OHCI (DEV-19, FUN-0)
EHCI (DEV-19, FUN-2)
3G
Int. Camera
Hudson-M2/M3
OHCI (DEV-18, FUN-0)
EHCI (DEV-18, FUN-2)
USB-Left2
<Support Wakeup>
USB-Left1
+VDDANCR_11_SSUSB
Hudson-M3
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)
USB 3.0
(For Hudson M3 only)
+3VALW
APU_SIC <7,9>
APU_SID <7,9>
SB-TSI
Strap
+3VALW
1 2
ODD_DA#_Q
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+3VS +3VS
R312
R312
10K_0402_5%
10K_0402_5%
@
@
2
Q208A
Q208A
6 1
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A7571
SCHEMATIC MB A7571
SCHEMATIC MB A7571
4019D7
4019D7
4019D7
R311
R311
10K_0402_5%
10K_0402_5%
1 2
E
ODD_DA# <21>
B
B
13 41Monday, May 09, 2011
13 41Monday, May 09, 2011
13 41Monday, May 09, 2011
B
of
of
of
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