A
ZZZ
1 1
PCB
Part Number = DAZ0K400100
B
C
D
E
Compal Confidential
2 2
K73TA Schematics Document
AMD Sabine
APU Llano / Hudson M3 / Whistler
DIS only
3 3
2011-03-08
LA-7553P REV: 0.2
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
QBL70 LA-7553P
E
151Friday, April 29, 2011
0.22
of
A
Compal Confidential
Model Name : QBL70
B
C
D
E
1 1
VRAM 512M/1G/2G
64M16/128M16 x 8
page 23, 24
Sabine
DDR3
Thermal Sensor
ADM1032
page 19
Vancuver Whistler
ATI
uFCBGA-962
Page 18~22
GFX x 4
APU HDMI
(UMA / Muxless)
DP x1 (DP0 TXP/N0)
Gen2GFX x 8
AMD FS1 APU
Llano
uPGA-722 Package
Memory BUS(DDR3)
Dual Channel
1.5V DDRIII 800~1333MHz
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Page 11,12
HDMI Conn.
page 28
2 2
LVDS Conn.
LVDS
Reserve eDP
page 27
CRT Conn.
page 27
3 3
Travis LVDS
Translator
page 26
LAN(GbE)
RTL8111E
RJ45
GPP0
page 31
page 31
FCH CRT (VGA DAC)
GPP0
MINI Card 1
WLAN
page 35
P_GPP x 2
GEN1
DP x 4
(DP1 TXP/ N 0~4)
Hudson-M2/M3
uFCBGA-656
Page 6~10
FCH
Page 13~17
UMI
LPC BUS
USB2
page 30
USB
3.3V 48MHz
HD Audio
S-ATA
Gen2
port 0
SATA HDD1
Conn.
page 29
USB2
page 30 page 27
Port 0 Port 5
3.3V 24.576MHz/48M hz
USB2 x 2
(LS-7323P)
page 33
Port 1
port 2
SATA HDD2
page 29
CMOS
Camera
ODD
Conn.
page 29
Mini Card
(with BT)
Port2 Port 3
port 1
HDA Codec
ALC269
page 35
Card Reader
RTS5137
page 34
Port 4
page 33
ENE KB930
page 32
Touch Pad Int.KBD
LED
page 35
RTC CKT.
4 4
page 13
DC/DC
Interface CKT.
page 38
External board
LS-7324P
HDD/B
LS-7325P
Power/B
page 36
page 36
BIOS ROM
SYS BIOS (2M)
page 15
LS-7323P
Power Circuit
page 39~48
A
Audio BD
page 33 page 32
EC BIOS (128K)
B
page 37
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
page 37
Compal Secret Data
Deciphered Date
D
Date: Sheet
Title
Size Document Number Rev
B
Compal Electronics, Inc.
Block Diagrams
QBL70 LA-7553P
251Friday, April 29, 2011
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of
0.22
5
4
3
2
1
CLOCK DISTRIBUTION
DISPLAY DISTRIBUTION
: LVDS PATH
D D
B_SODIMM
A_SODIMM
AMD
MEM_MA_CLK7_P/N
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
1066~1600MHz
C C
AMD
CPU FS1 SOCKET
DP0_AUX
MEM_MA_CLK1_P/N
1066~1600MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
100MHz
LVDS Transtator
ATI VG A
Whistler
CLK_PEG_VGAP/N
100MHz
AMD
FCH
Hudson-M2/M3
Internal CLK GEN
GPP_CLK
100MHz
32.768KHz 25MHz
: APU HDMI PATH
APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA
LVDS_OUT
RTD2132
DP_IN
C
TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA
LVDS CONN
R
DP0_TXP/N[0:1]
DP0_AUXP/N
B B
WLAN
GbE LAN
Mini PCI Socket
25MHz
GPP0GPP1
APU
DP1
DP0
PCIE_GFX[0:7]
PCIE_GFX[12:15]
C
C
PCIE_GFX[0:7]
VGA
FCH
R
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
CLOCK / DISPLAY DISTRIBUTION
Size Document Number Rev
Custom
QBL70 LA-7553P
2
Date: Sheet
LS
HDMI CONNCRT CONN
1
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B
C
D
E
Voltage Rails
SIGNAL
Power Plane Description
VIN
B+
+CPU_CORE
+CPU_CORE_1 ON OFF OFF
1 1
+CPU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
+VGA_CORE OFFOFFON0.95-1.2V switched power rail
+0.75VS ONON OFF0.75V swi tched power rai l for DDR termina tor
+1.0VSG ON OFF OFF1.0V switched power rail for VGA
+1.1ALW 1.1V switched power rail for FCH ON ON*ON
+1.1VS
+1.2VS ON OFF OFF
+1.5V ON
+1.5VS
+1.8VSG OFFON OFF1.8V switched power rail
+2.5VS
+3VALW
+3V_LAN ONONON
+3VS
+5VALW
+5VS
2 2
+VSB ON ON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply ( 19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for CPU (0.7-1.2V)
1.2V switched power rail for APU
1.5V power r ail for CPU VDDIO a nd DDR
1.5V switched power rail
2.5V for CP U_VDDA
3.3V always on power rail
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF OFF1.1V switched power rail for FCH
ON OFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
ON
ON*
OFF
OFFON
ONON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
SLP_S1# SLP_S3#
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW
LOW LOW
LOW
AD_BID
0
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
OFF
OFF
V
AD_BID
0.538 V
0.875 V
ON ON
ON
OFF
OFF
OFF
max
0 V
HIGH
LOW
HIGHHIGHHIGH
HIGH
HIGH
LOW
V typ
AD_BID
0.503 V
0.819 V
ON
ON
ON
ON
ON
0 V 0 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
BOARD ID Table
Board ID
M3@
U25
0
1
2
3
4
5
6
7
NA
P5WS5
P5WH5
P7YE5
P7YS5
NA
NA
NA
PCB Revision
BTO Option Table
BTO ItemBOM Structure
VGA@ Use VGA (Mux)
128@ Use VRAM channel A&B
M2@ Use Hudson-M2
x = 1 is read cmd, x= 0 is writee cmd.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
3 3
M3@ Use Hudson-M3
USB30@ USB30 on M/B
USB20@ USB20 on M/B
TranslatorTL@
VRAM ID TableX76@
FCH M3
Part Number = SA000043ID0
BOM Config
EC SM Bus1 address EC SM Bus2 address
Device Address HEX
Smart Battery
0001 011X b
FCH
SM Bus 0 address
4 4
Device Address Device Address
DDR DIMM1
DDR DIMM2
1101 000X b
1101 001X b
A
Device Address HEX
16H
ADI ADM1032 (VGA)
1001 101X b
FCH
SM Bus 1 address
HEX
D0
D2
9AH
HEX
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet
Compal Electronics, Inc.
Notes List
QBL70 LA-7553P
E
451Friday, April 29, 2011
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5
4
3
2
1
BATTERY
12.6V
AC ADAPTOR
D D
19V 90W
BATT+
VIN
PU3
CHARGER
ISL6251AHAZ-T
B+
C C
+INVPWR_B+
LCD panel
15.6"
B+ 300mA
+3.3 350mA
B B
FAN Control
APL5607
+5VS 500mA
U22/U23
TPA2301DRG4
+USB_VCCA
+USB_VCCB
PU13
ISL6267HRZ-T
PU6
G5603RU1U
PU10
G5603RU1U
PU11
TPS51218DSCR
PU12
G5603RU1U
PU5
G5603RU1U
PU4
RT8205EGQW
+3VS
+5VS
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+VGA_CORE
+VDDCI
+1.1VALW
+3VALW
+5VALW
+5VALW
+3VS
U33
SI4800
Q57
SI2301
U33
SI4800
+2.5VS
PU9
APL5508
PU8
G9731G11U
U34
AO4430L
PU7
SY8033BDBC
PU2
UP7711U8
+1.0VSG
+1.5VSG
+1.8VSG
Q61
SI2301
U34
AO4430L
+0.75VS
+3VSG
+1.1VS
+CPU_CORE
+CPU_CORE_NB
+2.5VS
+1.5V
+1.2VS
+0.75VS
+VGA_CORE
+VDDCI
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
+1.1VS
+1.1VALW
+3VS
USB X3
+5V
Dual+1
2.5A
SATA
HDD*2
ODD*1
+5V 3A
+3.3V
A A
Audio Codec
ALC271X
+5V 45mA
+3.3VS 25mA
Realtek
RTS5138
EC
ENE KB930
+3.3VALW 30mA
+3.3VS 3mA
+3VALW
LAN
Atheros AR8151
+3.3VALW 201mA
+1.5VS
Mini Card*2
+1.5VS 500mA
+3.3VS 1A+3.3VS 300mA
+3.3VALW 330mA
RTC
Bettary
+3VALW
AMD APU FS1
0.7~1.475V
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
VDD CORE 54A
VDDNB 27.5A
VDDA 500mA
VDDIO 4.6A
VDDR 6.7A
RAM DDR III SODIMMX2
+1.5V
+0.75VS
0.85~1.1V
0.9~1.0V
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
VDD_MEM 4A
VTT_MEM 0.5A
VGA AT I
Whistler/Seymour/Granville
VDDC 47A
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDR1: 3400 mA
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
A2VDD: 130 mA
VDDR3: 60 mA
FCH AMD Hudson M2/M3
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
+1.1VS
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
+3VS
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
+3VALW
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
GND
VDDIO_GBE_S
VDDBT_RTC_GRTC BAT
VRAM 512/1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG 2.4 A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/08/04 2010/08/04
Compal Secret Dat a
Deciphered Date
2
Title
POWER DELIVE RY CHART
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
1
551Friday, April 29, 2011
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PCIE_GTX_C_FRX_P[0..7]18
JCPU1A
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
1 1
2 2
PCIE_DTX_C_FRX_P031
3 3
4 4
PCIE_DTX_C_FRX_N031
UMI_MTX_C_FRX_P013
UMI_MTX_C_FRX_N013
UMI_MTX_C_FRX_P113
UMI_MTX_C_FRX_N113
UMI_MTX_C_FRX_P213
UMI_MTX_C_FRX_N213
UMI_MTX_C_FRX_P313
UMI_MTX_C_FRX_N313
+1.2VS
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
1 2
R1802 196_0402_1%
P_ZVDDP
AA8
AA9
Y7
Y8
W5
W6
W8
W9
V7
V8
U5
U6
U8
U9
T7
T8
R5
R6
R8
R9
P7
P8
N5
N6
N8
N9
M7
M8
L5
L6
L8
L9
AC5
AC6
AC8
AC9
AB7
AB8
AA5
AA6
AF8
AF7
AE6
AE5
AE9
AE8
AD8
AD7
K5
AMD_TOPEDO_FS-1
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
PCI EXPRESS
GPPUMI-LINK GRAPHICS
B
CONN@
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
PCIE_FTX_GRX_P0
AA2
PCIE_FTX_GRX_N0
AA3
PCIE_FTX_GRX_P1
Y2
PCIE_FTX_GRX_N1
Y1
PCIE_FTX_GRX_P2
Y4
PCIE_FTX_GRX_N2
Y5
PCIE_FTX_GRX_P3
W2
PCIE_FTX_GRX_N3
W3
PCIE_FTX_GRX_P4
V2
PCIE_FTX_GRX_N4
V1
PCIE_FTX_GRX_P5
V4
PCIE_FTX_GRX_N5
V5
PCIE_FTX_GRX_P6
U2
PCIE_FTX_GRX_N6
U3
PCIE_FTX_GRX_P7
T2
PCIE_FTX_GRX_N7
T1
T4
T5
R2
R3
P2
P1
P4
P5
PCIE_FTX_GRX_P12
N2
PCIE_FTX_GRX_N12
N3
PCIE_FTX_GRX_P13
M2
PCIE_FTX_GRX_N13
M1
PCIE_FTX_GRX_P14
M4
PCIE_FTX_GRX_N14
M5
PCIE_FTX_GRX_P15
L2
PCIE_FTX_GRX_N15
L3
PCIE_FTX_DRX_P0
AD4
PCIE_FTX_DRX_N0
AD5
AC2
AC3
AB2
AB1
AB4
AB5
UMI_FTX_MRX_P0
AF1
UMI_FTX_MRX_N0
AF2
UMI_FTX_MRX_P1
AF5
UMI_FTX_MRX_N1
AF4
UMI_FTX_MRX_P2
AE3
UMI_FTX_MRX_N2
AE2
UMI_FTX_MRX_P3
AD1
UMI_FTX_MRX_N3
AD2
P_ZVSS
K4
C917 0.1U_0402_16V7K
C918 0.1U_0402_16V7K
C919 0.1U_0402_16V7K
C920 0.1U_0402_16V7K
C921 0.1U_0402_16V7K
C922 0.1U_0402_16V7K
C923 0.1U_0402_16V7K
C924 0.1U_0402_16V7K
C925 0.1U_0402_16V7K
C926 0.1U_0402_16V7K
C927 0.1U_0402_16V7K
C928 0.1U_0402_16V7K
C929 0.1U_0402_16V7K
C930 0.1U_0402_16V7K
C931 0.1U_0402_16V7K
C932 0.1U_0402_16V7K
1 2
R1803 196_0402_1%
C
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
To HDMI
0
CK
C950 0.1U_0402_16V7K
1 2
C951 0.1U_0402_16V7K
1 2
C956 0.1U_0402_16V7K
1 2
C957 0.1U_0402_16V7K
1 2
C958 0.1U_0402_16V7K
1 2
C959 0.1U_0402_16V7K
1 2
C960 0.1U_0402_16V7K
1 2
C961 0.1U_0402_16V7K
1 2
C962 0.1U_0402_16V7K
1 2
C963 0.1U_0402_16V7K
1 2
PCIE_FTX_C_GRX_P[0..7] 18
PCIE_FTX_C_GRX_N[0..7] 18PCIE_GTX_C_FRX_N[0..7]18
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_C_DRX_P0 31
PCIE_FTX_C_DRX_N0 31
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
For UMA Mux.
GLAN
D
APU To HDMI
CPU TSI interface level shift
C935 0.1U_0402_16V4Z
1 2
R1798
1 2
+3VS
31.6K_0402_1%
APU_SID8,14
APU_SIC8,14
APU_SID
BSH111 1N_SOT23-3
APU_SIC
BSH111 1N_SOT23-3
G
S
G
S
1 2
30K_0402_1%
2
Q9
13
D
2
Q10
13
D
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
R1799
EC_SMB_DA
EC_SMB_CK
PCIE_FTX_GRX_P[12..15] 28
PCIE_FTX_GRX_N[12..15] 28
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
1 2
R1800 0_0402_5%
1 2
R1801 0_0402_5%
E
EC_SMB_DA2 19,32
To EC
EC_SMB_CK2 19,32
Group A
Group B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
AMD FS1 PCIE / UMI / TSI
QBL70 LA-7553P
E
651Friday, April 29, 2011
0.22
of
A
1 1
JCPU1B
DDRA_SMA[15..0]11
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11
DDRA_SDM[7..0]11
2 2
DDRA_SDQS011
DDRA_SDQS0#11
DDRA_SDQS111
DDRA_SDQS1#11
DDRA_SDQS211
DDRA_SDQS2#11
DDRA_SDQS311
DDRA_SDQS3#11
DDRA_SDQS411
DDRA_SDQS4#11
DDRA_SDQS511
DDRA_SDQS5#11
DDRA_SDQS611
DDRA_SDQS6#11
DDRA_SDQS711
DDRA_SDQS7#11
DDRA_CLK011
DDRA_CLK0#11
DDRA_CLK111
DDRA_CLK1#11
DDRA_CKE011
DDRA_CKE111
DDRA_ODT011
DDRA_ODT111
3 3
DDRA_SCS0#11
DDRA_SCS1#11
DDRA_SRAS#11
DDRA_SCAS#11
DDRA_SWE#11
MEM_MA_RST#11
MEM_MA_EVENT#11
+MEM_VREF
+1.5V
Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#
Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#
Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE0
DDRA_CKE1
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
MEM_MA_RST#
MEM_MA_EVENT#
15mil
1 2
R1804 39.2_0402_1%
M_ZVDDIO
U20
MA_ADD0
R20
MA_ADD1
R21
MA_ADD2
P22
MA_ADD3
P21
MA_ADD4
N24
MA_ADD5
N23
MA_ADD6
N20
MA_ADD7
N21
MA_ADD8
M21
MA_ADD9
U23
MA_ADD10
M22
MA_ADD11
L24
MA_ADD12
AA25
MA_ADD13
L21
MA_ADD14
L20
MA_ADD15
U24
MA_BANK0
U21
MA_BANK1
L23
MA_BANK2
E14
MA_DM0
J17
MA_DM1
E21
MA_DM2
F25
MA_DM3
AD27
MA_DM4
AC23
MA_DM5
AD19
MA_DM6
AC15
MA_DM7
G14
MA_DQS_H0
H14
MA_DQS_L0
G18
MA_DQS_H1
H18
MA_DQS_L1
J21
MA_DQS_H2
H21
MA_DQS_L2
E27
MA_DQS_H3
E26
MA_DQS_L3
AE26
MA_DQS_H4
AD26
MA_DQS_L4
AB22
MA_DQS_H5
AA22
MA_DQS_L5
AB18
MA_DQS_H6
AA18
MA_DQS_L6
AA14
MA_DQS_H7
AA15
MA_DQS_L7
T21
MA_CLK_H0
T22
MA_CLK_L0
R23
MA_CLK_H1
R24
MA_CLK_L1
H28
MA_CKE0
H27
MA_CKE1
Y25
MA_ODT0
AA27
MA_ODT1
V22
MA_CS_L0
AA26
MA_CS_L1
V21
MA_RAS_L
W24
MA_CAS_L
W23
MA_WE_L
H25
MA_RESET_L
T24
MA_EVENT_L
W20
M_VREF
W21
M_ZVDDIO
AMD_TOPEDO_FS-1
MEMORY CHANNEL A
CONN@
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
B
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ[63..0] 11
C
DDRB_SMA[15..0]12
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SBS2#12
DDRB_SDM[7..0]12
DDRB_SDQS012
DDRB_SDQS0#12
DDRB_SDQS112
DDRB_SDQS1#12
DDRB_SDQS212
DDRB_SDQS2#12
DDRB_SDQS312
DDRB_SDQS3#12
DDRB_SDQS412
DDRB_SDQS4#12
DDRB_SDQS512
DDRB_SDQS5#12
DDRB_SDQS612
DDRB_SDQS6#12
DDRB_SDQS712
DDRB_SDQS7#12
DDRB_CLK012
DDRB_CLK0#12
DDRB_CLK112
DDRB_CLK1#12
DDRB_CKE012
DDRB_CKE112
DDRB_ODT012
DDRB_ODT112
DDRB_SCS0#12
DDRB_SCS1#12
DDRB_SRAS#12
DDRB_SCAS#12
DDRB_SWE#12
MEM_MB_RST#12
MEM_MB_EVENT#12
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE0
DDRB_CKE1
DDRB_ODT0
DDRB_ODT1
DDRB_SCS0#
DDRB_SCS1#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
MEM_MB_RST#
MEM_MB_EVENT#
D
T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24
U27
T28
K28
D14
A18
A22
C25
AF25
AG22
AH18
AD14
C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
R26
R27
P27
P28
J26
J27
W27
Y28
V25
Y27
V24
V27
V28
J25
T25
JCPU1C
MEMORY CHANNEL B
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L
AMD_TOPEDO_FS-1
CONN@
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
E
DDRB_SDQ[63..0] 12
EVENT# pull high 0.75V reference voltage
+1.5V
4 4
R1806 1K_0402_5%
1 2
R1807 1K_0402_5%
1 2
MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF
A
R1805
1K_0402_1%
R1808
1K_0402_1%
+1.5V
1 2
1 2
B
1
C964
1000P_0402_50V7K
2
15mil
2
C965
0.1U_0402_16V7K
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Custom
D
Date: Sheet
Title
Size Document Number Rev
Compal Electronics, Inc.
AMD FS1 DDRIII I/F
QBL70 LA-7553P
751Friday, April 29, 2011
E
of
0.22
A
Place near APU
C971 0.1U_0402_16V7K
DP0_TXP0_C26
To LVDS
Translator
1 1
To FCH VGA ML
100MHz
2 2
100MHz_NSS
+1.5V
R575 1K_0402_5%
1 2
R576 1K_0402_5%
1 2
+1.5V
3 3
R579 1K_0402_5%
1 2
R581 1K_0402_5%
1 2
R791 1K_0402_5%
1 2
+1.5V
Close to Header
R592 1K_0402_5%
1 2
R593 1K_0402_5%
1 2
R594 1K_0402_5%
1 2
R595 1K_0402_5%
1 2
R596 300_0402_5%
1 2
Route as differen tial
with VSS_SENSE
4 4
DP0_TXN0_C26
DP0_TXP1_C26
DP0_TXN1_C26
ML_VGA_TXP015
ML_VGA_TXN015
ML_VGA_TXP115
ML_VGA_TXN115
ML_VGA_TXP215
ML_VGA_TXN215
ML_VGA_TXP315
ML_VGA_TXN315
APU_CLKP13
APU_CLKN13
APU_DISP_CLKP13
APU_DISP_CLKN13
APU_SVC47
APU_SVD47
Chang to PU +1.5VS (D G ref.)
20101111
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
APU_VDDNB_RUN_FB_L47
APU_VDD_RUN_FB_L47
A
1 2
C973 0.1U_0402_16V7K
1 2
C1016 0.1U_0402_16V7K
1 2
C1017 0.1U_0402_16V7K
1 2
T35
T20
T21
T22
Place near APU
C977 0.1U_0402_16V7K
1 2
C968 0.1U_0402_16V7K
1 2
C969 0.1U_0402_16V7K
1 2
C970 0.1U_0402_16V7K
1 2
C978 0.1U_0402_16V7K
1 2
C979 0.1U_0402_16V7K
1 2
C980 0.1U_0402_16V7K
1 2
C981 0.1U_0402_16V7K
1 2
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SVC
APU_SVD
APU_SIC6,14
TSI
APU_SID6,14
APU_RST#13
APU_PWRGD13
Serial VID
R597 0_0402_5%
R600 0_0402_5%
APU_VDDNB_SEN47
APU_VDD_SEN47
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
ALERT_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
1 2
1 2
APU_VDDNB_SEN
APU_VDD_SEN
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
B
JCPU1D
F2
DP0_TXP0
F1
DP0_TXN0
E3
DP0_TXP1
E2
DP0_TXN1
D2
DP0_TXP2
D1
DP0_TXN2
C2
DP0_TXP3
C3
DP0_TXN3
K2
DP1_TXP0
K1
DP1_TXN0
J3
DP1_TXP1
J2
DP1_TXN1
H2
DP1_TXP2
H1
DP1_TXN2
G2
DP1_TXP3
G3
DP1_TXN3
AH7
CLKIN_H
AH6
CLKIN_L
AH4
DISP_CLKIN_H
AH3
DISP_CLKIN_L
B8
SVC
A8
SVD
AH11
SIC
AG11
SID
AF10
RESET_L
AE10
PWROK
AD10
PROCHOT_L
AG12
THERMTRIP_L
AH12
ALERT_L
C12
TDI
A12
TDO
A11
TCK
D12
TMS
B12
TRST_L
B11
DBRDY
C11
DBREQ_L
E8
RSVD_1
K21
RSVD_2
AC11
RSVD_3
B9
VSS_SENSE
C8
VDDP_SENSE
A9
VDDNB_SENSE
B10
VDDIO_SENSE
C9
VDD_SENSE
A10
VDDR_SENSE
AMD_TOPEDO_FS-1
B
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
System DP
CONN@
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST6
TEST9
TEST10
TEST12
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST21
TEST DISPLAY PORT MISC.
TEST22
TEST23
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35
FS1R1
DMAACTIVE_L
THERMDA
THERMDC
C
Place near APU
DP0_AUXP
D4
DP0_AUXN
D5
ML_VGA_AUXP
E5
ML_VGA_AUXN
E6
J5
J6
H4
H5
G5
G6
APU_HDMI_CLK
F4
APU_HDMI_DATA
F5
D7
E7
J7
H7
G7
F7
C6
C5
C7
D8
AA10
G10
H10
H12
D9
E9
G9
H9
H11
G11
F12
E11
D11
F10
G12
AH10
AH9
K7
K8
AA12
AB12
K22
AB11
AA11
D10
Y11
AB10
AE12
AD12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C972 0.1U_0402_16V7K
1 2
C974 0.1U_0402_16V7K
1 2
C975 0.1U_0402_16V7K
1 2
C976 0.1U_0402_16V7K
1 2
APU_HDMI_CLK 28
APU_HDMI_DATA 28
DP0_HPD
DP1_HPD
DP5_HPD
DP_ENBKL
DP_ENVDD
DP_INT_PWM
DP_AUX_ZVSS
T6
T7
T8
T9
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
T10
APU_TEST24
TEST25_H
TEST25_L
T11
T12
M_TEST
T13
T14
TEST35
FS1R1
ALLOW_STOP
T15
T16
Llano do not support this thermal die
DP0_HPD 10
DP1_HPD 10
DP5_HPD 10
DP_ENBKL 10
DP_ENVDD 10
DP_INT_PWM 10
R569 150_0402_1%
1 2
Chang to unpop (DG ref.)
20101111
R573 0_0402_5%@
1 2
R574 1K_0402_5%
1 2
R582 1K_0402_5%
1 2
R583 1K_0402_5%
1 2
R584 1K_0402_5%
1 2
R585 1K_0402_5%
1 2
R589 1K_0402_5%
1 2
R590 1K_0402_5%
1 2
ALLOW_STOP 13
C639 0.1U_0402_16V4Z
1 2
@
2010/08/04 2010/08/04
C
DP0_AUXP_C 26
DP0_AUXN_C 26
ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15
LVDS
CRT
HDMI
HDT Debug conn
Compal Secret Data
AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic
VDDIO level
Need Level shift
VDDIO level
Need Level shift
VDDIO level
Need Level shift
APU_TRST#
R598 0_0402_5%
R601 10K_0402_5%
R603 10K_0402_5%
R605 10K_0402_5%
Deciphered Date
D
To LVDS
Translator
To FCH
Asserted as an input to force the
processor into the HTC-active state
APU_PROCHOT#
THERMTRIP shutdown
temperature: 125 degree
APU_THERMTRIP#
+1.5V
1 2
1 2
1 2
1 2
D
MISC
1 2
+1.5V
R610
1K_0402_5%
1 2
MMBT3904_NL_SOT23-3
JHDT1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
SAMTE_ASP-136446-07-B
CONN@
Custom
Date: Sheet
E
If not used, pins are left unconnected (DG ref.)
20101111
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
TEST25_L
TEST25_H
TEST35
TEST35 PD 300ohm (DG ref. )
20101111
M_TEST
FS1R1
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
ALLOW_STOP
APU_RST#
APU_PWRGD
R586
1K_0402_5%
1 2
R591 0_0402_5%
Indicates to the FCH that a thermal trip
12
has occurred. Its assertion will cause th e FCH to
transition the system to S5 immediately
R609
10K_0402_5%
B
2
Q12
E
3 1
C
R611 0_0402_5%
APU_TCK
2
2
APU_TMS
4
4
APU_TDI
6
6
APU_TDO
8
8
10
10
12
12
APU_DBRDY
14
14
APU_DBREQ#
16
16
R606 0_0402_5%
18
18
R608 0_0402_5%
20
20
Title
AMD FS1 Display / MISC / HDT
Size Document Number Rev
QBL70 LA-7553P
R554 1.8K_0402_5%
R555 1.8K_0402_5%
R1809 1.8K_0402_5%
R556 1.8K_0402_5%
R548 510_0402_1%
R557 510_0402_1%
R558 300_0402_5%
R559 300_0402_5%
R564 39.2_0402_1%@
R567 39.2_0402_1%
R571 10K_0402_5%
R1812 1K_0402_5%
R577 1K_0402_5%
R578 300_0402_5%
R580 300_0402_5%
+3VS+1.5V
12
R587
10K_0402_5%
2
B
Q11
E
31
C
MMBT3904_NL_SOT23-3
1 2
1 2
1 2
1 2
1 2
@
1 2
1 2
1 2
1 2
1 2
@
1 2
1 2
12
R588
10K_0402_5%
12
12
12
12
EC_THERM# 13,32,47
H_THERMTRIP# 14
Cut on CPU side, Debug mount
R599 0_0402_5%@
1 2
R602 0_0402_5%@
1 2
1 2
1 2
APU_TEST19
APU_TEST18
Compal Electronics, Inc.
851Friday, April 29, 2011
E
+1.2VS
+1.5V
+1.5V
+3VALW
+1.5V
+1.5VS
APU_PWRGD
APU_RST#
of
0.22
A
Power Name
VDD
+CPU_CORE
VDDNB
+CPU_CORE_N B
VDDIO
+1.5V
VDDP / VDDR
+1.2VS
VDDA
1 1
+2.5VS
CORE_NB
330uF X 2
22uF X 4
2 2
3 3
+2.5VS
Del C1039
201012061900
4 4
Consumption
50A
22.5A
4A
3A / 3.5A
0.75A
CPU_CORE
330uF X 4
22uF X 11
+CPU_CORE_NB
L1
FBMA-L11-201209-221LMA30T_0805
12
C1041
0.22U_0603_16V4Z
C1040
3300P_0402_50V7K
1
12
2
A
+CPU_CORE
+1.5V
+1.2VS
+1.2VS
40mil
VDDA
C1043
C18
180P_0402_50V8J
4.7U_0805_10V4Z
1
1
@
2
2
JCPU1E
C1
VDD
D3
VDD
D6
VDD
E1
VDD
F3
VDD
F6
VDD
F8
VDD
G1
VDD
H3
VDD
H6
VDD
H8
VDD
J1
VDD
K3
VDD
K6
VDD
L1
VDD
L11
VDD
L19
VDD
M3
VDD
M6
VDD
M10
VDD
M18
VDD
N1
VDD
N11
VDD
N19
VDD
P3
VDD
P6
VDD
P10
VDD
P18
VDD
R1
VDD
R11
VDD
R19
VDD
T3
VDD
J9
VDDNB
J10
VDDNB
J11
VDDNB
J12
VDDNB
J14
VDDNB
J16
VDDNB
K9
VDDNB
K10
VDDNB
G28
VDDIO
H26
VDDIO
J28
VDDIO
K20
VDDIO
K23
VDDIO
K26
VDDIO
L22
VDDIO
L25
VDDIO
L28
VDDIO
M20
VDDIO
M23
VDDIO
M26
VDDIO
N22
VDDIO
N25
VDDIO
N28
VDDIO
P20
VDDIO
P23
VDDIO
P26
VDDIO
AG2
VDDP_A_1
AG3
VDDP_A_2
AG4
VDDP_A_3
AG5
VDDP_A_4
AG6
VDDR
AG7
VDDR
AG8
VDDR
AG9
VDDR
AE11
VDDA
AF11
VDDA
AMD_TOPEDO_FS-1
Keep trace from resistor to APU
within 0.6"
Keep trace from Caps to APU
within 1.2"
CONN@
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDP_B_1
VDDP_B_2
VDDP_B_3
VDDP_B_4
VDDR
VDDR
VDDR
VDDR
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2000mil2000mil
T6
T10
T18
U1
U11
U19
V3
V6
V10
V18
W1
W11
W13
W15
W17
W19
Y3
Y6
Y10
Y12
Y14
Y16
Y18
Y20
AA1
AB3
AB6
AC1
AD3
AD6
AE1
K11
K12
K13
K14
K16
K17
K18
L18
R22
R25
R28
T20
T23
T26
U22
U25
U28
V20
V23
V26
W22
W25
W28
Y24
Y26
AA28
A3
A4
B3
B4
A5
A6
B5
B6
B
+CPU_CORE
900mil900mil
160mil160mil
120mil120mil
160mil160mil
B
+CPU_CORE_NB
+1.5V
VDDP decoupling
10U_0603_6.3V6M
C8
C7
1
1
2
2
VDDR decoupling
180P_0402_50V8J
C1044
C1045
1
1
2
2
C1052
0.22U_0603_16V4Z
C1053
1
1
2
2
C
CPU BOTTOM SIDE DECOUPLING
+CPU_CORE
C982
1
2
+CPU_CORE_NB
C1000
1
2
+1.5V
C1012
1
2
+1.5V
C1027
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C6
1
2
180P_0402_50V8J
180P_0402_50V8J
C1046
1
2
0.22U_0603_16V4Z
C1054
0.22U_0603_16V4Z
1
2
22U_0805_6.3V6M
C983
C996
22U_0805_6.3V6M
1
1
2
2
C1001
22U_0805_6.3V6M
22U_0805_6.3V6M
C1002
1
1
2
2
22U_0805_6.3V6M
C1013
22U_0805_6.3V6M
C14
1
1
2
2
0.22U_0603_16V4Z
C1029
C1028
0.22U_0603_16V4Z
1
1
2
2
180P_0402_50V8J
180P_0402_50V8J
C1035
C1034
1
1
2
2
1000P_0402_50V7K
180P_0402_50V8J
C1048
C1047
1
1
2
2
4.7U_0603_6.3V6K
C1055
0.22U_0603_16V4Z
C10
1
1
2
2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C997
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K
180P_0402_50V8J
C1036
1
2
C1049
1
2
C11
1
2
Issued Date
22U_0805_6.3V6M
C984
22U_0805_6.3V6M
1
1
2
2
C1004
C1003
22U_0805_6.3V6M
1
1
2
2
4.7U_0603_6.3V6K
C15
C16
1
1
2
2
C1030
180P_0402_50V8J
1
2
Decoupling between CPU and DIMMs
across VDDIO and VSS split
+1.2VS
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C1037
1
2
1000P_0402_50V7K
1000P_0402_50V7K
C1050
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C12
1
2
0.22U_0603_16V4Z
4.7U_0603_6.3V6K
C1051
C13
C985
22U_0805_6.3V6M
1
2
C1005
0.22U_0603_16V4Z
1
2
4.7U_0603_6.3V6K
C17
1
2
+1.2VS
1
+
2
1000P_0402_50V7K
+1.2VS
1
2
4.7U_0603_6.3V6K
2
1
C986
1
2
C1006
1
2
C1018
1
2
C1038
220U_6.3V_M
C1038 change to SF000002Y00
20101228
2010/08/04 2010/08/04
C
22U_0805_6.3V6M
C987
0.22U_0603_16V4Z
1
2
C1007
180P_0402_50V8J
180P_0402_50V8J
1
2
C1019
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
2
C988
0.22U_0603_16V4Z
C989
0.01U_0402_16V7K
1
1
2
2
C1008
180P_0402_50V8J
C1010
C1009
390U_2.5V_10M
1
1
+
2
2
C1021
0.22U_0603_16V4Z
C1020
0.22U_0603_16V4Z
1
1
2
2
Compal Secret Data
Deciphered Date
D
C998
0.01U_0402_16V7K
C991
180P_0402_50V8J
C990
0.01U_0402_16V7K
1
2
390U_2.5V_10M
1
+
2
C1022
0.22U_0603_16V4Z
1
2
Demo Board Capacitor (include PWM side)
CPU_CORE
470uF x 6
22uF x 9
0.22uF x 2
180pF x 2
10nF x 3
C1011
C1023
1
1
2
2
390U_2.5V_10M
1
+
2
0.22U_0603_16V4Z
C1024
180P_0402_50V8J
1
1
2
2
CORE_NB
470uF x 4
22uF x 6
0.22uF x 2
180uF x 3
C992
1
2
+CPU_CORE
C1025
1
2
D
C993
180P_0402_50V8J
1
+
2
C1014
180P_0402_50V8J
C5
C994
390U_2.5V_10M
390U_2.5V_10M
1
+
2
C1015
390U_2.5V_10M
1
1
+
2
2
330U_D2_2V_Y
1
+
2
VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4
C999
390U_2.5V_10M
C995
330U_D2_2V_Y
1
1
+
+
@
2
2
390U_2.5V_10M
+
VDDIO_SUS
(DIMM x2)
100uF x 4
0.1uF
Title
Size Document Number Rev
Custom
Date: Sheet
JCPU1F
A7
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
A25
VSS
B7
VSS
C4
VSS
C10
VSS
C14
VSS
C16
VSS
C18
VSS
C20
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D25
VSS
D27
VSS
E4
VSS
E10
VSS
E12
VSS
F9
VSS
F11
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
G4
VSS
G8
VSS
G13
VSS
G15
VSS
G17
VSS
G19
VSS
G21
VSS
G23
VSS
G25
VSS
J4
VSS
J8
VSS
J18
VSS
J20
VSS
J22
VSS
J24
VSS
K19
VSS
L4
VSS
L7
VSS
L10
VSS
M9
VSS
M11
VSS
M19
VSS
N4
VSS
N7
VSS
N10
VSS
N18
VSS
P9
VSS
P11
VSS
P19
VSS
R4
VSS
R7
VSS
R10
VSS
R18
VSS
T9
VSS
AMD_TOPEDO_FS-1
VDDP/R_PWM
470uF x 2
10uF x 1
VDDP
10uF x 3
0.22uF x 2
180pF x 2
Compal Electronics, Inc.
AMD FS1 PWR / GND
QBL70 LA-7553P
E
CONN@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E
T11
T19
U4
U7
U10
U18
V9
V11
V19
W4
W7
W10
W12
W14
W16
W18
Y9
Y22
AA4
AA7
AB9
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AC4
AC7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AD9
AD11
AE4
AE7
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AF3
AF6
AF9
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AH5
AH8
AH13
AH15
AH17
AH19
AH21
AH23
AH25
VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
951Friday, April 29, 2011
of
0.22
5
4
3
2
1
ʼnőŅ
ʼnőŅ őŢůŦŭġņŏŃŌō
ʼnőŅʼnőŅ
@
@
@
R615
1K_0402_5%
12
R622
1K_0402_5%
12
12
@
@
D D
Translator HPD
From Translator
LVDS_HPD26 DP0_HPD 8
LVDS_HPD
R618 100K_0402_5%
CRT HPD
From FCH
FCH_CRT_HPD15 DP1_HPD 8
C C
FCH_CRT_HPD
R627 100K_0402_5%
HDMI HPD
From HDMI Conn
APU_HDMI_HPD28 DP5_HPD 8
APU_HDMI_HPD
R659 100K_0402_5%
+3VS
12
R613
10K_0402_5%
2
1 3
D
Q13
2N7002_SOT23
+3VS
12
2
1 3
D
Q16
2N7002_SOT23
1 2
G
S
R621
10K_0402_5%
G
S
1 2
1 2
R677 0_0402_5%
R616
1K_0402_5%
+1.5VS
1 2
+1.5VS
12
1K_0402_5%
R623
+1.5VS
12
@
R630
4.7K_0402_5%
őŢůŦŭġņŏŃŌō
őŢůŦŭġņŏŃŌōőŢůŦŭġņŏŃŌō
DP_ENBKL8
őŢůŦŭġņŏŗŅŅ
őŢůŦŭġņŏŗŅŅ
őŢůŦŭġņŏŗŅŅőŢůŦŭġņŏŗŅŅ
DP_ENBKL
DP_ENVDD8
@
1 2
R619 2.2K_0402_5%
@
R620
100K_0402_5%
1 2
1 2
R633 2.2K_0402_5%
@
R634
100K_0402_5%
1 2
DP_ENBKL ENBKL
@
+3VS
@
R617
100K_0402_5%
1 2
2
C
E
3 1
2
B
MMBT3904_NL_SOT23-3
1 2
+3VS
@
R1810
100K_0402_5%
1 2
C
E
3 1
MMBT3904_NL_SOT23-3
G
@
Q15
2
B
R624 0_0402_5%
@
Q19
12
@
R614
4.7K_0402_5%
13
D
S
2
G
@
Q14
2N7002_SOT23
12
@
R632
4.7K_0402_5%
13
D
Q18
@
2N7002_SOT23
S
ENBKL
ENBKL 32
APU_ENVDD 27
B B
A A
5
4
őŢůŦŭġőŘŎ
őŢůŦŭġőŘŎ
őŢůŦŭġőŘŎőŢůŦŭġőŘŎ
DP_INT_PWM8
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
R637 2.2K_0402_5%
12
R638
4.7K_0402_5%
2010/08/04 2010/08/04
Compal Secret Data
+3VS
12
R635
47K_0402_5%
C
Q21
2
B
E
3 1
Deciphered Date
12
R636
4.7K_0402_5%
13
D
2
G
Q20
2N7002_SOT23
S
MMBT3904_NL_SOT23-3
2
APU_INVT_PWM 26,27
Q15 / Q19 / Q21 change to SB000006A00
20101228
Title
AMD FS1 Singal Level Shifter
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
1
10 51Friday, April 29, 2011
0.22
of
A
+1.5V +1.5V+VREF_DQ
JDIMM2
15mil
VREF_DQ1VSS1
3
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2
1 1
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_CKE07
2 2
3 3
4 4
C1080
2.2U_0603_6.3V4Z
DDRA_SBS2#7
DDRA_CLK07
DDRA_CLK0#7
DDRA_SBS0#7
DDRA_SWE#7
DDRA_SCAS#7 DDRA_ODT0 7
DDRA_SCS1#7
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
+3VS
1
1
C1081
0.1U_0402_16V4Z
2
2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS# DDRA_ODT0
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643 10K_0402_5%
+3VS
1 2
12
R645
10K_0402_5%
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1
CONN@
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
B
2
DDRA_SDQ4
4
DDRA_SDQ5
6
8
DDRA_SDQS0#
10
DDRA_SDQS0
12
14
DDRA_SDQ6
16
DDRA_SDQ7
18
20
DDRA_SDQ12
22
DDRA_SDQ13
24
26
DDRA_SDM1
28
MEM_MA_RST#
30
32
DDRA_SDQ14
34
DDRA_SDQ15
36
38
DDRA_SDQ20
40
DDRA_SDQ21
42
44
DDRA_SDM2
46
48
DDRA_SDQ22
50
DDRA_SDQ23
52
54
DDRA_SDQ28
56
DDRA_SDQ29
58
60
DDRA_SDQS3#
62
DDRA_SDQS3
64
66
DDRA_SDQ30
68
DDRA_SDQ31
70
72
DDRA_CKE1
74
76
DDRA_SMA15
78
DDRA_SMA14
80
82
DDRA_SMA11
84
DDRA_SMA7
86
A7
88
DDRA_SMA6
90
A6
A4
A2
A0
G2
DDRA_SMA4
92
94
DDRA_SMA2
96
DDRA_SMA0
98
100
DDRA_CLK1
102
DDRA_CLK1#
104
106
DDRA_SBS1#
108
DDRA_SRAS#
110
112
DDRA_SCS0#
114
116
118
DDRA_ODT1
120
122
124
15mil
126
128
DDRA_SDQ36
130
DDRA_SDQ37
132
134
DDRA_SDM4
136
138
DDRA_SDQ38
140
DDRA_SDQ39
142
144
DDRA_SDQ44
146
DDRA_SDQ45
148
150
DDRA_SDQS5#
152
DDRA_SDQS5
154
156
DDRA_SDQ46
158
DDRA_SDQ47
160
162
DDRA_SDQ52
164
DDRA_SDQ53
166
168
DDRA_SDM6
170
172
DDRA_SDQ54
174
DDRA_SDQ55
176
178
DDRA_SDQ60
180
DDRA_SDQ61
182
184
DDRA_SDQS7#
186
DDRA_SDQS7
188
190
DDRA_SDQ62
192
DDRA_SDQ63
194
196
MEM_MA_EVENT#
198
200
202
204
206
+0.75VS
DDRA_SDQS0# 7
DDRA_SDQS0 7
MEM_MA_RST# 7
DDRA_SDQS3# 7
DDRA_SDQS3 7
DDRA_CKE1 7
DDRA_CLK1 7
DDRA_CLK1# 7
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
DDRA_ODT1 7
1
C1066
1000P_0402_50V7K
2
DDRA_SDQS5# 7
DDRA_SDQS5 7
DDRA_SDQS7# 7
DDRA_SDQS7 7
MEM_MA_EVENT# 7
FCH_SDATA0 12,14,35
FCH_SCLK0 12,14,35
+VREF_CA
C
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
Place near DIMM1
+1.5V
0.1U_0402_16V4Z
2
C1067
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1077
1
0.1U_0402_16V4Z
15mil
4.7U_0603_6.3V6K
+VREF_DQ
1
1
@
C1060
2
2
0.1U_0402_16V4Z
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
2
C1068
1
0.1U_0402_16V4Z
2
C1078
1
4.7U_0603_6.3V6K
1
C1061
2
1000P_0402_50V7K
2
1
C1062
0.1U_0402_16V4Z
2
C1070
C1069
1
C1106 0.1U_0402_16V4Z
1
C1079
2
+1.5V+VREF_DQ
R639
1K_0402_1%
1 2
R641
1K_0402_1%
1 2
D
2
C1071
1
0.1U_0402_16V4Z
+1.5V+0.75VS
@
1 2
Add C1106
20101101
0.1U_0402_16V4Z
2
C1072
1
4.7U_0603_6.3V6K
1
2
2
C1073
1
0.1U_0402_16V4Z
15mil
+VREF_CA
1
@
C1063
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1074
1
1
C1064
2
1000P_0402_50V7K
2
C1075
1
0.1U_0402_16V4Z
+1.5V+VREF_CA
C1065
0.1U_0402_16V4Z
2
C1076
1
R640
1K_0402_1%
1 2
R642
1K_0402_1%
1 2
E
Security Classification
DIMM_A STD H:9.2mm
<Address: 00>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
DDRIII SO-DIMM 2
QBL70 LA-7553P
E
11 51Friday, April 29, 2011
0.22
of
A
B
C
D
E
DQ4
DQ5
DQ6
DQ7
DM1
DM2
NC2
DM4
DM6
SDA
A15
A14
A11
CK1
BA1
S0#
SCL
+1.5V+1.5V
2
DDRB_SDQ4
4
DDRB_SDQ5
6
8
DDRB_SDQS0#
10
DDRB_SDQS0
12
14
DDRB_SDQ6
16
DDRB_SDQ7
18
20
DDRB_SDQ12
22
DDRB_SDQ13
24
26
DDRB_SDM1
28
MEM_MB_RST#
30
32
DDRB_SDQ14
34
DDRB_SDQ15
36
38
DDRB_SDQ20
40
DDRB_SDQ21
42
44
DDRB_SDM2
46
48
DDRB_SDQ22
50
DDRB_SDQ23
52
54
DDRB_SDQ28
56
DDRB_SDQ29
58
60
DDRB_SDQS3#
62
DDRB_SDQS3
64
66
DDRB_SDQ30
68
DDRB_SDQ31
70
72
DDRB_CKE1
74
76
DDRB_SMA15
78
DDRB_SMA14
80
82
DDRB_SMA11
84
DDRB_SMA7
86
A7
88
DDRB_SMA6
90
A6
A4
A2
A0
G2
DDRB_SMA4
92
94
DDRB_SMA2
96
DDRB_SMA0
98
100
DDRB_CLK1
102
DDRB_CLK1#
104
106
DDRB_SBS1#
108
DDRB_SRAS#
110
112
DDRB_SCS0#
114
DDRB_ODT0DDRB_SCAS#
116
118
DDRB_ODT1
120
122
124
15mil
126
128
DDRB_SDQ36
130
DDRB_SDQ37
132
134
DDRB_SDM4
136
138
DDRB_SDQ38
140
DDRB_SDQ39
142
144
DDRB_SDQ44
146
DDRB_SDQ45
148
150
DDRB_SDQS5#
152
DDRB_SDQS5
154
156
DDRB_SDQ46
158
DDRB_SDQ47
160
162
DDRB_SDQ52
164
DDRB_SDQ53
166
168
DDRB_SDM6
170
172
DDRB_SDQ54
174
DDRB_SDQ55
176
178
DDRB_SDQ60
180
DDRB_SDQ61
182
184
DDRB_SDQS7#
186
DDRB_SDQS7
188
190
DDRB_SDQ62
192
DDRB_SDQ63
194
196
MEM_MB_EVENT#
198
200
202
204
206
+0.75VS
DDRB_SDQS0# 7
DDRB_SDQS0 7
MEM_MB_RST# 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_CKE1 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
1
C1088
1000P_0402_50V7K
2
DDRB_SDQS5# 7
DDRB_SDQS5 7
DDRB_SDQS7# 7
DDRB_SDQS7 7
MEM_MB_EVENT# 7
FCH_SDATA0 11,14,35
FCH_SCLK0 11,14,35
+VREF_CA
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
Place near DIMM2
+1.5V
0.1U_0402_16V4Z
2
2
C1089
1
0.1U_0402_16V4Z
+0.75VS
0.1U_0402_16V4Z
+VREF_DQ +VREF_CA
15mil 15mil
4.7U_0603_6.3V6K
1
@
C1082
2
C1090
1
0.1U_0402_16V4Z
2
2
C1099
1
1
+VREF_DQ +VREF_CA
0.1U_0402_16V4Z
1
C1083
2
1000P_0402_50V7K
2
C1091
1
0.1U_0402_16V4Z
1
C1101
C1100
2
4.7U_0603_6.3V6K
1
C1084
2
0.1U_0402_16V4Z
2
1
C1107 0.1U_0402_16V4Z
4.7U_0603_6.3V6K
1
2
C1092
0.1U_0402_16V4Z
@
1 2
0.1U_0402_16V4Z
@
C1085
2
1
1
2
C1093
Add C1107
20101101
C1086
0.1U_0402_16V4Z
2
C1094
1
1
C1087
2
1000P_0402_50V7K
2
C1095
1
0.1U_0402_16V4Z
+1.5V+1.5V
12
+
@
C1668
330U_2.5V_M_R15
C1102 change to OSCON
20101101
0.1U_0402_16V4Z
2
C1096
1
2
C1097
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1098
1
+VREF_DQ
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
+3VS
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646 10K_0402_5%
1 2
12
<BOM Structure>
R648
<BOM Structure>
10K_0402_5%
1 1
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQS2#7
DDRB_SDQS27
DDRB_CKE07
2 2
3 3
4 4
DDRB_SBS2#7
DDRB_CLK07
DDRB_CLK0#7
DDRB_SBS0#7
DDRB_SWE#7
DDRB_SCAS#7
DDRB_SCS1#7
DDRB_SDQS4#7
DDRB_SDQS47
DDRB_SDQS6#7
DDRB_SDQS67
15mil
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
CONN@
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
Security Classification
DIMM_B STD H:5.2mm
<Address: 01>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
DDRIII SO-DIMM 1
QBL70 LA-7553P
E
12 51Friday, April 29, 2011
0.22
of
A
C1195 150P_0402_50V8J
12
R829 33_0402_5%
PCI Host Bus Reset (To EC)
1 1
A_RST#32
UMI_MTX_C_FRX_P06
UMI_MTX_C_FRX_N06
UMI_MTX_C_FRX_P16
UMI_MTX_C_FRX_N16
UMI_MTX_C_FRX_P26
UMI_MTX_C_FRX_N26
UMI_MTX_C_FRX_P36
UMI_MTX_C_FRX_N36
UMI_FTX_C_MRX_P06
UMI_FTX_C_MRX_N06
UMI_FTX_C_MRX_P16
UMI_FTX_C_MRX_N16
UMI_FTX_C_MRX_P26
UMI_FTX_C_MRX_N26
UMI_FTX_C_MRX_P36
UMI_FTX_C_MRX_N36
+PCIE_VDDR_FCH
C1189 0.1U_0402_16V7K
C1190 0.1U_0402_16V7K
C1191 0.1U_0402_16V7K
C1192 0.1U_0402_16V7K
C1196 0.1U_0402_16V7K
C1197 0.1U_0402_16V7K
C1198 0.1U_0402_16V7K
C1194 0.1U_0402_16V7K
R827 590_0402_1%
R828 2K_0402_1%
PCIE_W_FTX_DRX_P035
PCIE_W_FTX_DRX_N035
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
PCIE_CALRP
PCIE_CALRN
PCIE_W_FTX_DRX_P0
PCIE_W_FTX_DRX_N0
WLAN
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCIE_W_DTX_C_FRX_P0
PCIE_W_DTX_C_FRX_N0
CLK_CALRN
APU_DISP_CLKP_R
TRAVIS_CLKP_R
APU_CLKP_R
APU_CLKN_R
CLK_PEG_VGA_R
CLK_PEG_VGA#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_ MINI1_R
CLK_PCIE_MINI1#_R
PCIE_W_DTX_C_FRX_P035
PCIE_W_DTX_C_FRX_N035
ňőőġőŰųŵıġŇŰųġŖŔŃĴıġŰůġŔŖŔİŃ
ňőőġőŰųŵıġŇŰųġŖŔŃĴıġŰůġŔŖŔİŃ
ňőőġőŰųŵıġŇŰųġŖŔŃĴıġŰůġŔŖŔİŃňőőġőŰųŵıġŇŰųġŖŔŃĴıġŰůġŔŖŔİŃ
ňőőġőŰųŵIJġŇŰųġŖŔŃĴıġŰůġŎİŃġġijıIJıIJIJıĴ
ňőőġőŰųŵIJġŇŰųġŖŔŃĴıġŰůġŎİŃġġijıIJıIJIJıĴ
ňőőġőŰųŵIJġŇŰųġŖŔŃĴıġŰůġŎİŃġġijıIJıIJIJıĴňőőġőŰųŵIJġŇŰųġŖŔŃĴıġŰůġŎİŃġġijıIJıIJIJıĴ
2 2
SS
APU DISP
NSS
Translator
APU
VGA
GLAN
WLAN
+1.1VS_CKVDD
For "EXT" CLK mode, input to PCIE,
APU_DISP_CLKP8
APU_DISP_CLKN8
TRAVIS_CLKP26
TRAVIS_CLKN26
APU_CLKP8
APU_CLKN8
CLK_PEG_VGA18
CLK_PEG_VGA#18
CLK_PCIE_LAN31
CLK_PCIE_LAN#31
CLK_PCIE_ MINI135
CLK_PCIE_ MINI1#35
R833 2K_0402_1%
1 2
APU_DISP_CLKP
APU_DISP_CLKN APU_DISP_CLKN_R
TRAVIS_CLKP
TRAVIS_CLKN TRAVIS_CLKN_R
APU_CLKP
APU_CLKN
CLK_PEG_VGA
CLK_PEG_VGA#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_ MINI1
CLK_PCIE_ MINI1#
R566 0_0402_5%
R565 0_0402_5%
R612 0_0402_5%
R568 0_0402_5%
R162 0_0402_5%
R163 0_0402_5%
R607 0_0402_5%
R570 0_0402_5%
R604 0_0402_5%
R625 0_0402_5%
R644 0_0402_5%
R572 0_0402_5%
SS
3 3
EMI
R657 22_0402_5%
CLK_SD_48M34
1 2
C1200
12P_0402_50V8J
25MHZ_20PF_7A25000012
1 2
C1201
10P_0402_50V8J
4 4
A
C1205
1 2
10P_0402_50V8J
R861
20M_0402_5%
C1206
1 2
8P_0402_50V
1 2
1 2
12
12
R856 0_0402_5%
R858
X1
1M_0402_5%
Y4
4
OSC
1
OSC
32.768KHZ 7PF Q13MC1461000100
Close to HUDSON-M2
3
NC
2
NC
B
APU_PCIE_RST#_C
A_RST#_R
CLK_SD_48M_R
25M_X1
25M_X2
32K_X1
32K_X2
B
U25A
AE2
PCIE_RST#
AD5
A_RST#
AE30
UMI_TX0P
AE32
UMI_TX0N
AD33
UMI_TX1P
AD31
UMI_TX1N
AD28
UMI_TX2P
AD29
UMI_TX2N
AC30
UMI_TX3P
AC32
UMI_TX3N
AB33
UMI_RX0P
AB31
UMI_RX0N
AB28
UMI_RX1P
AB29
UMI_RX1N
Y33
UMI_RX2P
Y31
UMI_RX2N
Y28
UMI_RX3P
Y29
UMI_RX3N
AF29
PCIE_CALRP
AF31
PCIE_CALRN
V33
GPP_TX0P
V31
GPP_TX0N
W30
GPP_TX1P
W32
GPP_TX1N
AB26
GPP_TX2P
AB27
GPP_TX2N
AA24
GPP_TX3P
AA23
GPP_TX3N
AA27
GPP_RX0P
AA26
GPP_RX0N
W27
GPP_RX1P
V27
GPP_RX1N
V26
GPP_RX2P
W26
GPP_RX2N
W24
GPP_RX3P
W23
GPP_RX3N
F27
CLK_CALRN
G30
PCIE_RCLKP
G28
PCIE_RCLKN
R26
DISP_CLKP
T26
DISP_CLKN
H33
DISP2_CLKP
H31
DISP2_CLKN
T24
APU_CLKP
T23
APU_CLKN
J30
SLT_GFX_CLKP
K29
SLT_GFX_CLKN
H27
GPP_CLK0P
H28
GPP_CLK0N
J27
GPP_CLK1P
K26
GPP_CLK1N
F33
GPP_CLK2P
F31
GPP_CLK2N
E33
GPP_CLK3P
E31
GPP_CLK3N
M23
GPP_CLK4P
M24
GPP_CLK4N
M27
GPP_CLK5P
M26
GPP_CLK5N
N25
GPP_CLK6P
N26
GPP_CLK6N
R23
GPP_CLK7P
R24
GPP_CLK7N
N27
GPP_CLK8P
R27
GPP_CLK8N
J26
14M_25M_48M_OSC
C31
25M_X1
C33
25M_X2
HUDSON-M2_FCBGA656
M2@
HUDSON-2
PCI CLKS
PCICLK4/14M_OSC/GPO39
PCI EXPRESS INTERFACES
PCI INTERFACE
REQ2#/CLK_R EQ8#/GPIO41
REQ3#/CLK_R EQ5#/GPIO42
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLOCK GENERATOR
LPCAPUS5 PLUS
LDRQ1#/CLK_REQ6#/GPIO49
C
AF3
PCICLK0
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
GNT0#
CLKRUN#
LOCK#
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
RTCCLK
32K_X1
32K_X2
AF1
AF5
AG2
AF6
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
VGA_PWRGD_R
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
AF18
AE18
AC16
AD18
B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
G25
E28
E26
G26
F26
H7
F1
F3
E6
G2
G4
LPC_CLK1_R
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
32K_X1
32K_X2
T23
T24
R671 0_0402_5%
R844
APU_PWRGD
2010/08/04 2010/08/04
C
PCICLK1/GPO3 6
PCICLK2/GPO3 7
PCICLK3/GPO3 8
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
REQ1#/GPIO40
GNT1#/GPO44
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
SERIRQ/GPIO48
DMA_ACTIVE#
S5_CORE_EN
INTRUDER_ALERT#
VDDBT_RTC_G
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCI_CLK1 16
PCI_CLK3 16
PCI_CLK4 16
APU_PCIE_RST#_C
1 2
R842 0_0402_5%
PE_GPIO1
R843 22_0402_5%
LPC_CLK0_ECLPC_CLK0_EC_R
1 2
1 2
1 2
0_0402_5%
R853 0_0402_5%@
1 2
R855 22_0402_5%
1 2
RTCVCC_R
C1202
1
2
0.1U_0402_16V4Z
Compal Secret Data
Deciphered Date
1 2
R1811 10K_0402_5%
@
C1203
1
2
D
For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)
R825 33_0402_5%
1 2
C1188
150P_0402_50V8J
VGA_PWRGD25,48
PCI_AD23 16
PCI_AD24 16
PCI_AD25 16
PCI_AD26 16
PCI_AD27 16
PE_GPIO0 18
PE_GPIO1 25,32
LPC_CLK0_EC 16,32
CLK_PCI_DB 35
LPC_CLK1 16
LPC_AD0 32,35
LPC_AD1 32,35
LPC_AD2 32,35
LPC_AD3 32,35
LPC_FRAME# 32,35
SERIRQ 32
ALLOW_STOP 8
EC_THERM# 8,32,47
APU_PWRGD 8
APU_RST# 8
RTC_CLK 16,32
1 2
R859 510_0402_5%
W=20mils
for Clear CMOS
1U_0402_6.3V4Z
D
2
R826
8.2K_0402_5%@
1
1 2
VGA_PWRGD VGA_PWRGD_R
@
NC7SZ08P5X_NL_SC70-5
ōŦŷŦŭġŴũŪŧŵġŵŰġŊŔōķijķĸ
10K_0402_5%
APU_PWRGD
œŕńġŃłŕŕġńŰůůį
APU_PG/APU_RST#/L DT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify D MA activity. This will cause the APU
to reestablish the UMI link quicker.
12
CLRP1
SHORT PADS
@
Custom
Date: Sheet
E
+3VALW
2
B
1
A
+3VALW
U27
2
B
1
A
+1.5VS
R834
B
E
3 1
Q38
MMBT3904_NL_SOT23-3
+RTCVCC
C1204
Title
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Size Document Number Rev
QBL70 LA-7553P
@
C1193
1 2
0.1U_0402_16V4Z
5
@
P
4
Y
G
U26
NC7SZ08P5X_NL_SC70-5
3
1 2
R835 0_0402_5%
C1199
@
1 2
0.1U_0402_16V4Z
5
P
G
3
R832 0_0402_5%
12
2
1
2
4
Y
1 2
C
0.1U_0402_16V4Z
1 2
R830 0_0402_5%@
1 2
R831 100K_0402_5%@
+3VS
1 2
CONN@
R836
4.7K_0402_5%
1
Q38 change to SB000006A00
20101228
+RTCBATT
D23
DAN202UT106_SC70-3
Compal Electronics, Inc.
E
1
+
-
2
+RTCBATT
2
3
PLT_RST# 18,26,31,35
APU_PWRGD_L 47
JRTC1
SUYIN_060003HA002G202ZL
12
R857
1K_0402_5%
+CHGRTC
13 51Friday, April 29, 2011
of
0.22
A
B
C
D
E
PCIE_RST2 : Reset PCIE device on Hudson2
U25D
AB6
EC_LID_OUT#32
SLP_S3#32
SLP_S5#32
PBTN_OUT#32
FCH_PWRGD32
1 1
EC_GA2032
EC_KBRST#32
EC_SCI#32
EC_SMI#32
HDA_BITCLK_AUDIO33
HDA_SDOUT_AUDIO33
HDA_SDIN033
HDA_SYNC_AUDIO33
HDA_RST_AUDIO#33
USB_OC2#
USB_OC0#
USB_OC1#
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
EC_LID_OUT#
FCH_PCIE_WAKE#
FCH_SCLK0
FCH_SDATA0
MINI1_CLKREQ#
LAN_CLKREQ#_1
Modify 20101111
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
A
FCH_PCIE_WAKE#31,32,35
H_THERMTRIP#8
EC_RSMRST#32
LAN_CLKREQ#31
FCH_SCLK011,12,35
FCH_SDATA011,12,35
MINI1_CLKREQ#35
VGA_PD16
USB_OC2#30
USB_OC1#33
USB_OC0#30
+3VALW
@
+3VALW
THERMTRIP:
Need level shift f rom +3VALW to +1.5V
SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
2 2
+3VALW
1 2
R56 100K_0402_5%
3 3
4 4
R55 100K_0402_5%
1 2
R54 100K_0402_5%
1 2
R871 10K_0402_5%
1 2
R874 2.2K_0402_5%
1 2
R876 2.2K_0402_5%
1 2
R877 10K_0402_5%
1 2
R878 10K_0402_5%@
+3VS
1 2
R880 2.2K_0402_5%
1 2
R881 2.2K_0402_5%
1 2
R882 8.2K_0402_5%
1 2
R940 8.2K_0402_5%
1 2
R884 2.2K_0402_5%
1 2
R885 10K_0402_5%
1 2
R886 10K_0402_5%
1 2
R888 10K_0402_5%
1 2
@
@
@
@
+3VALW
FCH_PCIE_WAKE#
+3VS
R81 0_0402_5%
1 2
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
MINI1_CLKREQ#
VGA_PD
USB_OC2#
USB_OC1#
USB_OC0#
R866 33_0402_5%
1 2
R867 33_0402_5%
1 2
R868 33_0402_5%
1 2
R869 33_0402_5%
1 2
8.2K_0402_5%
@
8.2K_0402_5%
@
R47
R48
12
R45
8.2K_0402_5%
@
12
R46
@
12
R43
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
8.2K_0402_5%
@
12
Project SKU ID
GPIO189 (use VGA) L(NO)
R44
GPIO190 (use PX)
GPIO191
Add Project ID Table
201011301600
8.2K_0402_5%
12
8.2K_0402_5%
12
For FCH internal debug use
@
1 2
R887 2.2K_0402_5%
@
1 2
R889 2.2K_0402_5%
@
1 2
R890 2.2K_0402_5%
EC_LID_OUT#
TEST0
TEST1
TEST2
SYS_RESET#
@
1 2
R18 10K_0402_5%
1 2
R862 10K_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SYNC
HDA_RST#
TEST0
TEST1
TEST2
LAN_CLKREQ#_1
1 2
R1813 10K_0402_5%
T29
T36
T37
T27
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
H(YES)
R44
R43
L(NO)
H(YES)
R45
R46
L(15")
H(17")
R48
R47
B
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVENT2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/S ATA_IS0#/GPIO64
AE24
CLK_REQ3#/S ATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/S ATA_IS3#/GPIO60
AH17
SATA_IS4#/F ANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN#/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GP IO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GP IO167
Y5
AZ_SDIN1/GP IO168
Y3
AZ_SDIN2/GP IO169
Y1
AZ_SDIN3/GP IO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/S DA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
HUDSON-M2_FCBGA656
M2@
HUDSON-2
EMBEDDED CTRL
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
USBCLK/14M_25M_48M_OSC
USB MISCUSB 1.1USB 2.0USB 3.0
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
2010/08/04 2010/08/04
G8
USB_RCOMP
B9
H1
H3
H6
H5
H10
G10
K10
J12
USB20_P11
G12
USB20_N11
F12
USB20_P10
K12
USB20_N10
K13
B11
D11
E10
F10
C10
A10
H9
G9
A8
C8
USB20_P4
F8
USB20_N4
E8
USB20_P3
C6
USB20_N3
A6
USB20_P2
C5
USB20_N2
A5
USB20_P1
C1
USB20_N1
C3
USB20_P0
E1
USB20_N0
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
A14
C14
C12
A12
D15
B15
E14
F14
F15
G15
H13
G13
USB30_MTX_DRX_P0
J16
USB30_MTX_DRX_N0
H16
USB30_MRX_DTX_P0
J15
USB30_MRX_DTX_N0
K15
R870 10K_0402_5%
H19
R872 10K_0402_5%
G19
APU_SIC
G22
APU_SID
G21
E22
H22
EC_PWM2
J22
H21
K21
K22
For PCIE device reset on FS1
F22
(GFX,GLAN,WLAN,LVDS Travis)
F24
E24
B23
C24
F18
Compal Secret Data
Deciphered Date
R863 11.8K_0402_1%
1 2
USB20_P11 33
USB20_N11 33
USB20_P10 30
USB20_N10 30
USB20_P4 34
USB20_N4 34
USB20_P3 35
USB20_N3 35
USB20_P2 27
USB20_N2 27
USB20_P1 33
USB20_N1 33
USB20_P0 30
USB20_N0 30
R864 1K_0402_1%M3@
1 2
R865 1K_0402_1%
1 2
M3@
C39 0.1U_0402_16V7K
C37 0.1U_0402_16V7K
1 2
1 2
D
1 2
M3@
1 2
M3@
APU_SIC 6,8
APU_SID 6,8
EC_PWM2 16
USB4
USB1
For USB 3.0
CardReder
WLAN(BT)
CMOS
USB3
USB2
Custom
Date: Sheet
Hudson-M2 Hudson-M3
EHCI CTL
DEV 22, Fn 2
<Disable CTL of M2>
Hudson-M2/M3
EHCI CTL
DEV 19, Fn 2
Hudson-M2/M3
EHCI CTL
DEV 18, Fn 2
+FCH_VDD_11_SSUSB_S
USB30_MTX_C_DRX_P0 30
USB30_MTX_C_DRX_N0 30
USB30_MRX_DTX_P0 30
USB30_MRX_DTX_N0 30
Title
Size Document Number Rev
Compal Electronics, Inc.
Hudson-M2/M3-ACPI/USB/EC
QBL70 LA-7553P
E
On board
USB Conn
14 51Friday, April 29, 2011
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0
Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0
of
0.22
A
SATA_STX_DRX_P029
+3VS
SATA_STX_DRX_N029
SATA_DTX_C_SRX_N029
SATA_DTX_C_SRX_P029
SATA_STX_DRX_P129
SATA_STX_DRX_N129
SATA_DTX_C_SRX_N129
SATA_DTX_C_SRX_P129
SATA_STX_DRX_P229
SATA_STX_DRX_N229
SATA_DTX_C_SRX_N229
SATA_DTX_C_SRX_P229
WL_OFF#35
HDD1
ODD
1 1
HDD2
2 2
+AVDD_SATA
3 3
B
SATA_CALRP
R8991K_0402_1%
12
SATA_CALRN
R9001K_0402_1%
12
SATA_LED#35
R902 10K_0402_5%
1 2
BT_ON35
R13 10K_0402_5%
R14 10K_0402_5%
R15 10K_0402_5%
R16 10K_0402_5%
SATA_LED#
T28
BT_ON
WL_OFF#
1 2
1 2
1 2
1 2
U25B
AK19
SATA_TX0P
AM19
SATA_TX0N
AL20
SATA_RX0N
AN20
SATA_RX0P
AN22
SATA_TX1P
AL22
SATA_TX1N
AH20
SATA_RX1N
AJ20
SATA_RX1P
AJ22
SATA_TX2P
AH22
SATA_TX2N
AM23
SATA_RX2N
AK23
SATA_RX2P
AH24
SATA_TX3P
AJ24
SATA_TX3N
AN24
SATA_RX3N
AL24
SATA_RX3P
AL26
SATA_TX4P
AN26
SATA_TX4N
AJ26
SATA_RX4N
AH26
SATA_RX4P
AN29
SATA_TX5P
AL28
SATA_TX5N
AK27
SATA_RX5N
AM27
SATA_RX5P
AL29
NC6
AN31
NC7
AL31
NC8
AL33
NC9
AH33
NC10
AH31
NC11
AJ33
NC12
AJ31
NC13
AF28
SATA_CALRP
AF27
SATA_CALRN
AD22
SATA_ACT#/GPIO67
AF21
SATA_X1
AG21
SATA_X2
AH16
FANOUT0/GPIO5 2
AM15
FANOUT1/GPIO5 3
AJ16
FANOUT2/GPIO5 4
AK15
FANIN0/GPIO56
AN16
FANIN1/GPIO57
AL16
FANIN2/GPIO58
K6
TEMPIN0/GPIO1 71
K5
TEMPIN1/GPIO1 72
K3
TEMPIN2/GPIO1 73
M6
TEMPIN3/TALERT#/GPIO174
HUDSON-M2_FCBGA656
M2@
HUDSON-2
SERIAL ATA
HW MONITOR
C
SD_CLK/SC LK_2/GPIO73
SD_CMD/S LOAD_2/GPIO74
SD_DATA0 /SDATI_2/GPIO77
SD_DATA1 /SDATO_2/GPIO78
SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK
SD_DATA2/GPIO79
SD_DATA3/GPIO80
GBE_RXCTL/RXDV
GBE_TXCTL/TXEN
GBE_PHY_RST#
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161
VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
VGA_DAC_RSET
AUX_VGA_CH_P
AUX_VGA_CH_N
ML_VGA_HPD/GPIO229
VIN2/SDATI_ 1/GPIO177
VIN3/SDATO_ 1/GPIO178
VIN4/SLOAD_ 1/GPIO179
VIN5/SCLK_ 1/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
SD_CD/GPIO75
SD_WP/GP IO76
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_PHY_PD
GBE_PHY_INTR
SPI_DI/GPIO164
VGA_RED
VGA_GREEN
VGA_BLUE
AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
VIN0/GPIO175
VIN1/GPIO176
NC1
NC2
NC3
NC4
NC5
AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14
AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9
V6
V5
V3
T6
V1
L30
L32
M29
M28
N30
M33
N32
K31
V28
V29
U28
T31
T33
T29
T28
R32
R30
P29
P28
C29
N2
M3
L2
N4
P1
P3
M1
M5
AG16
AH10
A28
G27
L4
GBE_COL
GBE_CRS
GBE_MDIO
GBE_RXERR
GBE_PHY_INTR
FCH_SPI_CLK_R
R896 150_0402_1%
1 2
R897 150_0402_1%
1 2
R898 150_0402_1%
1 2
R901 715_0402_1%
1 2
AUXCAL
1 2
R903 100_0402_1%
FCH_CRT_HPD
1 2
R5 10K_0402_5%
1 2
R6 10K_0402_5%
1 2
R7 10K_0402_5%
1 2
R8 10K_0402_5%
1 2
R9 10K_0402_5%
1 2
R10 10K_0402_5%
1 2
R11 10K_0402_5%@
1 2
R12 10K_0402_5%
D
SYS BIOS ROM
+3VALW
FCH_SPI_MISO
FCH_SPI_MOSI
R35 0_0402_5%@
1 2
FCH_SPI_CS1#
FCH_SPI_WP#
ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
ML_VGA_TXP0 8
ML_VGA_TXN0 8
ML_VGA_TXP1 8
ML_VGA_TXN1 8
ML_VGA_TXP2 8
ML_VGA_TXN2 8
ML_VGA_TXP3 8
ML_VGA_TXN3 8
FCH_CRT_HPD 10
@
1 2
@
R626 1K_0402_5%
1 2
@
R934 10K_0402_5%
1 2
R935 10K_0402_5%
FCH_SPI_CLK
FCH_CRT_R 27
FCH_CRT_G 27
FCH_CRT_B 27
FCH_CRT_HSYNC 27
FCH_CRT_VSYNC 27
FCH_CRT_DDC_SDA 27
FCH_CRT_DDC_SCL 27
+VDDAN_11_ML
FCH_SPI_CS1#
FCH_SPI_WP#
FCH_SPI_HOLD#
FCH_SPI_CLK
Add for EMI 201011291330
Change to PD 20101112
Add SYS BIOS ROM
20101111
FCH_CRT_HPD
E
@
U28
1
CS#
3
7
4
GBE_MDIO
GBE_PHY_INTR
GBE_COL
GBE_CRS
GBE_RXERR
VCC
WP#
SCLK
HOLD#
GND
MX25L1606EM2I-12G SOP 8P
SA000041N00
1 2
R36
@
SO
10_0402_5%
R891 10K_0402_5%
R892 10K_0402_5%
R893 10K_0402_5%
R894 10K_0402_5%
R895 10K_0402_5%
8
FCH_SPI_CLK
6
FCH_SPI_MOSI
5
SI
FCH_SPI_MISO
2
C23
@
1 2
1 2
1 2
1 2
1 2
1 2
+FCH_VDDAN_33_DAC_R
12
R90410K_0402_5%
+3VALW
@
C4660.1U_0402_16V4Z
12
10P_0402_50V8J
+3VALW
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Hudson-M2/M3-SATA/GBE/HWM
QBL70 LA-7553P
15 51Friday, April 29, 2011
E
of
0.22
A
STRAP PINS
B
C
D
E
12
12
R910 10K_0402_5%
R921 2.2K_0402_5%
RTC_CLKLPC_CLK1
S5 PLUS
MODE
DISABLED
DEFAULT
S5 PLUS
MODE
ENABLED
+3VALW+3VALW+3VALW+3VALW+3VS+3VS+3VS
12
12
@
R911 10K_0402_5%
R922 2.2K_0402_5%
+3VS +FCH_VDDAN_33_DAC_R
AP2301GN-HF_SOT23-3
+1.1VS +FCH_VDDAN_11_MLDAC
AP2301GN-HF_SOT23-3
VGA_PD: Support MLDAC power
save if not conne ct
0: MLDAC power on
1: MLDAC power off
Check VGA_PD states
VGA_PD14
If support ML DAC power down when no VGA plug
L47
1 2
FBMA-L11-201209-221LMA30T_0805
220 ohm
Q39
@
3 1
VGA_PD#
R912 0_0402_5%
Q40
@
3 1
VGA_PD#
@
2.2K_0402_5%
FBMA-L11-201209-221LMA30T_0805
2
AO3413 Vgs(max)=1V
1 2
1 2
R913 0_0402_5%
2
R923
1K_0402_5%
@
1 2
1 2
R925
C1212
1U_0402_6.3V4Z
1 2
30mil
+FCH_VDDAN_33_DAC
0_0402_5%
R924
@
5
1
2
L48
@
1 2
220 ohm
12
34
30mil
R916
100K_0402_5%
Q41B
DMN66D0LDW-7_SOT363-6
+3VS
C1209
12
1
2
2.2U_0603_6.3V4Z
R914
100K_0402_5%
1U_0402_6.3V4Z
1
@
2
C1210
C1211
1
2
0.1U_0402_16V4Z
VGA_PD#
Q41A
DMN66D0LDW-7_SOT363-6
61
2
PCI_CLK1
1 1
2 2
PULL
HIGH
PULL
LOW
PCI_CLK113
PCI_CLK313
PCI_CLK413
LPC_CLK0_EC13,32
LPC_CLK113
EC_PWM214
RTC_CLK13,32
ALLOW
PCIE GEN2
DEFAULT
FORCE
PCIE GEN1
@
12
12
R905 10K_0402_5%
R915 10K_0402_5%
PCI_CLK3
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAP
DEFAULT
12
@
12
PCI_CLK4 LPC_CLK0
NON_FUSION
CLOCK MODE
FUSION
CLOCK
MODE
DEFAULT
R906 10K_0402_5%
R917 10K_0402_5%
R907 10K_0402_5%
12
@
R918 10K_0402_5%
12
EC
ENABLED
EC
DISABLED
DEFAULT
12
@
12
CLKGEN
ENABLED
DEFAULT DEFAULT
CLKGEN
DISABLE
R908 10K_0402_5%
R919 10K_0402_5%
@
EC_PWM2
LPC ROM
SPI ROM
R909 10K_0402_5%
12
R920 10K_0402_5%
12
@
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:2 3]
3 3
PULL
HIGH
PULL
LOW
PCI_AD27PCI_AD26
USE PCI
PLL
DEFAULT
BYPASS
PCI PLL
DISABLE
ILA
AUTORUN
DEFAULT
ENABLE
ILA
AUTORUN
PCI_AD25 PCI_AD24
USE FC
PLL
BYPASS
FC PLL
USE DEFAULT
PCIE STRAPS
DEFAULT
USE EEPROM
PCIE STRAPS
PCI_AD23
DISABLE PCI
MEM BOOT
DEFAULTDEFAULT
ENABLE PCI
MEM BOOT
PCI_AD2713
PCI_AD2613
PCI_AD2513
PCI_AD2413
PCI_AD2313
4 4
A
R926 2.2K_0402_5%
12
@
R927 2.2K_0402_5%
12
@
R928 2.2K_0402_5%
12
@
R929 2.2K_0402_5%
12
@
B
R930 2.2K_0402_5%
12
@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Hudson-M2/M3-STRAP
QBL70 LA-7553P
E
16 51Friday, April 29, 2011
0.22
of
A
B
C
D
E
C1218 / C1219 / C1247 Change to SE00000I10
20101228
131mA
R20 0_0603_5%
+3VS
1 1
+FCH_VDDAN_33_DAC_R
+3VS
+3VALW
2 2
+VDDAN_33_USB
change to 0ohm-AMD request
20110212
+3VS
+3VS
3 3
For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S
Connected to VSS.
4 4
L3
1 2
MBK1608221YZF_2P
220 ohm
+FCH_VDDPL_33_MLDAC
1 2
R19 0_0603_5%
L4
@
1 2
MBK1608221YZF_2P
220 ohm
L6
M3@
1 2
MBK1608221YZF_2P
+FCH_VDDPL_33_SSUSB_S
220 ohm
L7
+FCH_VDDPL_33_USB_S
1 2
0_0603_5%
220 ohm
L15
1 2
MBK1608221YZF_2P
220 ohm
L22
1 2
MBK1608221YZF_2P
220 ohm
M2@
M2@
C1275
C1281
0_0402_5%
21
0_0402_5%
21
+VDDPL_3.3V
2.2U_0603_6.3V4Z
C1222
1
2
2.2U_0603_6.3V4Z
C1227
1
2
2.2U_0603_6.3V4Z
C1238
1
M3@
M3@
2
2.2U_0603_6.3V4Z
C1248
1
2
+VDDPL_33_PCIE
2.2U_0603_6.3V4Z
C1258
1
2
+VDDPL_33_SATA
2.2U_0603_6.3V4Z
C1266
1
2
A
.1U_0402_16V7K
C1229
1
2
.1U_0402_16V7K
C1231
VDDPL_33_SSUSB_S
1
For Hudson3 USB3.0 only
For Hudson2, connect to GND
2
LDO_CAP: Internally generated 1.8V
supply for the RGB outputs
+FCH_VDDAN_11_MLDAC
.1U_0402_16V7K
C1239
1
2
.1U_0402_16V7K
C1249
1
2
.1U_0402_16V7K
C1259
1
2
.1U_0402_16V7K
C1267
1
2
+1.1VALW
+3VS
+VDDPL_3.3V
+FCH_VDDPL_33_MLDAC
1 2
MBK1608221YZF_2P
220 ohm/2A
+3VALW
FBMA-L11-201209-221LMA30T_0805
+1.1VALW
+1.1VALW
L61
FBMA-L11-201209-221LMA30T_0805
42 ohm/4A
1 2
47mA
20mA
20mA
200mA
+FCH_VDDAN_33_DAC_R
R936 0_0402_5%M2@
+FCH_VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA
For A11: Cap = 1nF
For A12, Cap = DNI
L24
+VDDPL_11_DAC_L +VDDPL_11_DAC
R24 0_0402_5%
R1148 0_0603_5%
L54
1 2
658mA
220 ohm/2A
L57
220 ohm
L59
220 ohm
12
+FCH_VDD_11_SSUSB_S
140mA
197mA
1 2
R1149 0_0603_5%
1 2
R1150 0_0603_5%
1 2
MBK1608221YZF_2P
1 2
MBK1608221YZF_2P
+FCH_VDD_11_SSUSB_S
40mils
M3@
22U_0805_6.3V6M
C1218
1
2
1 2
R22 0_0402_5%
1 2
R23 0_0402_5%
20mA
12
17mA
43mA
93mA
7mA
1 2
226mA
1 2
1U_0402_6.3V6K
C1253
C1254
1
1
2
2
2.2U_0603_6.3V4Z
C1263
C1262
1
1
2
2
2.2U_0603_6.3V4Z
C1269
C1268
1
1
2
2
282mA
M3@
M3@
424mA
M3@
B
+VDDIO_33_PCIGP
.1U_0402_16V7K
.1U_0402_16V7K
C1221
C1220
C1228
1
2
C1232 2.2U_0603_6.3V4Z
C1240
4.7U_0603_6.3V6K
1
2
R945 0_0402_5%
1U_0402_6.3V6K
C1255
.1U_0402_16V7K
.1U_0402_16V7K
C1270
1U_0402_6.3V6K
C1273
1
2
C1278
M3@
1
1
2
2
+VDDPL_33_DAC
+VDDPL_33_ML
+FCH_VDDPL_33_SSUSB_S
@
1 2
+VDDAN_11_ML
.1U_0402_16V7K
.1U_0402_16V7K
C1241
C1242
1
1
2
2
1 2
+VDDAN_33_USB
10U_0603_6.3V6M
10U_0603_6.3V6M
C1256
1
1
2
2
+VDDAN_11_USB_S
+VDDCR_1.1V_USB
.1U_0402_16V7K
1
2
+VDDAN_SSUSB
.1U_0402_16V7K
C1274
C1275
1
1
M3@
M3@
2
2
+VDDCR_11_SSUSB
1U_0402_6.3V6K
10U_0603_6.3V6M
C1279
1
1
M3@
M3@
2
2
.1U_0402_16V7K
C1257
1
2
.1U_0402_16V7K
C1280
1
2
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
20mils
30mils
.1U_0402_16V7K
10mils
10mils
20mils
30mils
.1U_0402_16V7K
M3@
C1281
U25C
AB17
VDDIO_33_PCIGP_1
AB18
VDDIO_33_PCIGP_2
AE9
VDDIO_33_PCIGP_3
AD10
VDDIO_33_PCIGP_4
AG7
VDDIO_33_PCIGP_5
AC13
VDDIO_33_PCIGP_6
AB12
VDDIO_33_PCIGP_7
AB13
VDDIO_33_PCIGP_8
AB14
VDDIO_33_PCIGP_9
AB16
VDDIO_33_PCIGP_10
H24
VDDPL_33_SYS
V22
VDDPL_33_DAC
U22
VDDPL_33_ML
T22
VDDAN_33_DAC
L18
VDDPL_33_SSUSB_S
D7
VDDPL_33_USB_S
AH29
VDDPL_33_PCIE
AG28
VDDPL_33_SATA
M31
LDO_CAP
V21
VDDPL_11_DAC
Y22
VDDAN_11_ML_1
V23
VDDAN_11_ML_2
V24
VDDAN_11_ML_3
V25
VDDAN_11_ML_4
AB10
VDDIO_33_GBE_S
AB11
VDDCR_11_GBE_S_1
AA11
VDDCR_11_GBE_S_2
AA9
VDDIO_GBE_S_1
AA10
VDDIO_GBE_S_2
G7
VDDAN_33_USB_S_1
H8
VDDAN_33_USB_S_2
J8
VDDAN_33_USB_S_3
K8
VDDAN_33_USB_S_4
K9
VDDAN_33_USB_S_5
M9
VDDAN_33_USB_S_6
M10
VDDAN_33_USB_S_7
N9
VDDAN_33_USB_S_8
N10
VDDAN_33_USB_S_9
M12
VDDAN_33_USB_S_10
N12
VDDAN_33_USB_S_11
M11
VDDAN_33_USB_S_12
U12
VDDAN_11_USB_S_1
U13
VDDAN_11_USB_S_2
T12
VDDCR_11_USB_S_1
T13
VDDCR_11_USB_S_2
P16
VDDAN_11_SSUSB_S_1
M14
VDDAN_11_SSUSB_S_2
N14
VDDAN_11_SSUSB_S_3
P13
VDDAN_11_SSUSB_S_4
P14
VDDAN_11_SSUSB_S_5
N16
VDDCR_11_SSUSB_S_1
N17
VDDCR_11_SSUSB_S_2
P17
VDDCR_11_SSUSB_S_3
M17
VDDCR_11_SSUSB_S_4
HUDSON-M2_FCBGA656
.1U_0402_16V7K
M2@
1
Security Classification
2
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
HUDSON-2
PCI/GPIO I/O
USB SS USB MAIN LINKGBE LAN
POWER
CORE S0
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O
VDDAN_11_CLK_7
VDDAN_11_CLK_8
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10
VDDPL_11_SYS_S
VDDAN_33_HWM_S
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
VDDXL_33_S
VDDCR_11_S_1
VDDCR_11_S_2
VDDIO_AZ_S
2010/08/04 2010/08/04
50mils
T14
T17
T20
U16
U18
V14
V17
V20
Y17
20mils
H26
J25
K24
L22
M22
N21
N22
P22
50mils
AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27
60mils
AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19
10mils
N18
L19
M18
V12
V13
Y12
Y13
W11
10mils
G24
10mils
N20
M20
10mils
J24
10mils
M8
10mils
AA4
Compal Secret Data
1U_0402_6.3V6K
C1213
C1214
1
2
+1.1VS_CKVDD
1U_0402_6.3V6K
C1223
C1224
1
2
+PCIE_VDDR_FCH
1U_0402_6.3V6K
C1233
C1234
1
2
+AVDD_SATA
1U_0402_6.3V6K
C1244
C1243
1
2
+VDDIO_33_S
.1U_0402_16V7K
C1251
C1250
1
2
+VDDXL_3.3V
+VDDCR_1.1V
+VDDPL_1.1V
+VDDAN_33_HWM
+VDDIO_AZ
Deciphered Date
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
.1U_0402_16V7K
1
2
+VCC_FCH_R
1007mA
.1U_0402_16V7K
C1215
1
2
C1225
1
2
C1235
1
2
C1245
1
2
C1252
1
2
C1260
1
2
C1264
1
2
C1271
1
2
C1472
1
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1337mA
.1U_0402_16V7K
2.2U_0603_6.3V4Z
.1U_0402_16V7K
1U_0402_6.3V6K
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C1216
C1217
1
1
2
2
+1.1VS_CKVDD
340mA
.1U_0402_16V7K
C1230
C1226
1
1
2
2
+PCIE_VDDR_FCH
1088mA
.1U_0402_16V7K
C1237
C1236
1
1
2
2
+AVDD_SATA
.1U_0402_16V7K
C1246
C1247
1
1
2
2
59mA
5mA
2.2U_0603_6.3V4Z
C1261
1
2
187mA
2.2U_0603_6.3V4Z
C1265
1
2
70mA
.1U_0402_16V7K
C1272
1
2
12mA
.1U_0402_16V7K
R27 0_0402_5%
C1665
1
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
22U_0805_6.3V6M
R26 0_0402_5%
MBK1608221YZF_2P
R1145 0_0603_5%
MBK1608221YZF_2P
26mA
R28 0_0402_5%
1 2
C1276 2.2U_0603_6.3V4Z
1 2
C1277 .1U_0402_16V7K
D
R937 0_0805_5%
1 2
22U_0805_6.3V6M
C1219
1
2
1 2
R25 0_0603_5%
1 2
R938 0_0805_5%
1 2
R941 0_0805_5%
1 2
L28
1 2
220 ohm
1 2
L29
1 2
220 ohm
+3VALW
1 2
1 2
+1.1VS
U25E
A3
A33
B7
+1.1VS
+1.1VS
+1.1VS
+3VALW
+3VALW
+1.1VALW
+1.1VALW
B13
D13
E12
E16
E29
F11
F13
F16
F17
F19
F23
F25
F29
G16
G32
H12
H15
H29
K16
K27
K28
M13
M16
M21
M25
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R11
R25
R28
T11
T16
T18
K25
H25
D9
E5
F7
F9
G6
J6
J9
J10
J13
J28
J32
K7
L6
L12
L13
L15
L16
L21
N6
R4
N8
Connected to VSS through a dedicated via.
AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3 .3V_S 5 directly if HWM is not use d.
+3VS
VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Hudson-M2/M3-POWER/GND
QBL70 LA-7553P
HUDSON-2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSAN_HWM
VSSXL
VSSPL_SYS
HUDSON-M2_FCBGA656
M2@
GROUND
VSSANQ_DAC
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPL_DAC
VSSAN_DAC
VSSIO_DAC
EFUSE
17 51Friday, April 29, 2011
T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33
T21
L28
K33
N28
R6
of
0.22
A
GFX PCIE LANE REVERSAL
PCIE_FTX_C_GRX_P[0..7]6
PCIE_FTX_C_GRX_N[0..7]6
1 1
2 2
3 3
CLK_PEG_VGA13
CLK_PEG_VGA#13
PCIE_FTX_C_GRX_P[0..7]
PCIE_FTX_C_GRX_N[0..7]
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
R389 10K_0402_5%
12
VGA_RST#
U8A
AA38
PCIE_RX0P
Y37
PCIE_RX0N
Y35
PCIE_RX1P
W36
PCIE_RX1N
W38
PCIE_RX2P
V37
PCIE_RX2N
V35
PCIE_RX3P
U36
PCIE_RX3N
U38
PCIE_RX4P
T37
PCIE_RX4N
T35
PCIE_RX5P
R36
PCIE_RX5N
R38
PCIE_RX6P
P37
PCIE_RX6N
P35
PCIE_RX7P
N36
PCIE_RX7N
N38
PCIE_RX8P
M37
PCIE_RX8N
M35
PCIE_RX9P
L36
PCIE_RX9N
L38
PCIE_RX10P
K37
PCIE_RX10N
K35
PCIE_RX11P
J36
PCIE_RX11N
J38
PCIE_RX12P
H37
PCIE_RX12N
H35
PCIE_RX13P
G36
PCIE_RX13N
G38
PCIE_RX14P
F37
PCIE_RX14N
F35
PCIE_RX15P
E37
PCIE_RX15N
CLOCK
AB35
PCIE_REFCLKP
AA36
PCIE_REFCLKN
AH16
PWRGOOD
AA30
PERSTB
2160809000A11SEYMOU_FCBGA962
B
PCIE_GTX_C_FRX_P[0..7]
PCIE_GTX_C_FRX_N[0..7]
Y33
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCI EXPRESS INTERFACE
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
PCIE_CALRP
PCIE_CALRN
PCIE_GTX_FRX_N0
Y32
PCIE_GTX_FRX_P1
W33
PCIE_GTX_FRX_N1
W32
PCIE_GTX_FRX_P2
U33
PCIE_GTX_FRX_N2
U32
U30
PCIE_GTX_FRX_N3
U29
T33
PCIE_GTX_FRX_N4
T32
T30
PCIE_GTX_FRX_N5 PCIE_GTX_C_FRX_N5
T29
PCIE_GTX_FRX_P6
P33
PCIE_GTX_FRX_N6
P32
P30
PCIE_GTX_FRX_N7 PCIE_GTX_C_FRX_N7
P29
N33
N32
N30
N29
L33
L32
L30
L29
K33
K32
J33
J32
K30
K29
H33
H32
VGA_PCIE_CALRP
Y30
VGA_PCIE_CALRN
Y29
C580 0.1U_0402_16V7K
C291 0.1U_0402_16V7K
C247 0.1U_0402_16V7K
C473 0.1U_0402_16V7K
C572 0.1U_0402_16V7K
C288 0.1U_0402_16V7K
C579 0.1U_0402_16V7K
C316 0.1U_0402_16V7K
C287 0.1U_0402_16V7K
C228 0.1U_0402_16V7K
C224 0.1U_0402_16V7K
C576 0.1U_0402_16V7K
C295 0.1U_0402_16V7K
C472 0.1U_0402_16V7K
C242 0.1U_0402_16V7K
C468 0.1U_0402_16V7K
PCIE_GTX_C_FRX_P[0..7] 6
PCIE_GTX_C_FRX_N[0..7] 6
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R388 1.27K_0402_1%
1 2
R390 2K_0402_1%
1 2
C
+1.0VSG
PCIE_GTX_C_FRX_P0PCIE_GTX_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3PCIE_GTX_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4PCIE_GTX_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5PCIE_GTX_FRX_P5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7PCIE_GTX_FRX_P7
For UMA Mux.
D
<DIGON>
Controls panel digital power on/off.
Active High ,external PD need
U8G
LVDS CONTROL
LVTMDP
2160809000A11SEYMOU_FCBGA962
Change to APU_PCIE_RST# (SCH ref.)
20101111
VARY_BL
DIGON
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
TXOUT_L3P
TXOUT_L3N
PE_GPIO013
PLT_RST#13,26,31,35
2.2K_0402_5%
<VARY_BL>
LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High ,external PD need
R386 10K_0402_5%
AK27
AJ27
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37
@
R394
1 2
R387 10K_0402_5%
1 2
+3VSG
12
U21
5
2
P
B
1
A
G
3
NC7SZ08P5X_NL_SC70-5
@
1 2
R159 0_0402_5%
E
VGA_RST#
4
Y
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/07/12 2012/07/12
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Vancouver_ PCIE / LVDS
QBL70 LA-7553P
E
0.22
of
18 51Friday, April 29, 2011
A
Strap Name Pin Straps description <all internal PD>
VIP_DEVICE_EN
1 1
VGA_DIS
TX_PWRS_ENB
TX_DEEMPH_EN
CONFIG[2]
CONFIG[1]
CONFIG[0]
BIOS_ROM_EN
AUD[1]
AUD(0)
(GENLK_VSYNC)
BIF_GEN2_EN GPIO2
RESERVED
+1.8VSG
ŗœłŎġŊŅ
ŗœłŎġŊŅ
ŗœłŎġŊŅŗœłŎġŊŅ
@
@
R426
10K_0402_5%
10K_0402_5%
12
12
2 2
@
@
R432
10K_0402_5%
10K_0402_5%
12
12
+3VSG
R395 10K_0402_5%
1 2
R396 10K_0402_5%
1 2
R397 10K_0402_5%
1 2
R398 10K_0402_5%@
1 2
R401 10K_0402_5%@
1 2
R405 10K_0402_5%
1 2
R406 10K_0402_5%@
1 2
R408 10K_0402_5%@
1 2
R409 3K_0402_5%@
1 2
3 3
XTALOUT 27MCLK
C353
12P_0402_50V8J
VIP Device Strap Enable indicates to the software driv er (Internal PD)
0: Driver would ignore the value sampled on VHAD_0 during reset
V2SYNC
1: VHAD_0 to determine whether or not a VIP slave device
VGA Disable determines (Internal PD)
0: VGA Controller capacity enabled
GPIO9
1: The device will not be recognized as the system’s VGA controller
Transmitter Power Saving Enable (Inter nal PD)
0: 50% Tx output swing
GPIO0
1: full Tx output swing
PCI Express Transmitter De-emphasis Enable (Internal PD)
0: Tx de-emphasis diabled
GPIO1
1: Tx de-emphasis enabled
GPIO13,12,11 (config 2,1,0) : (Internal PD)
a) If BIOS_ROM_EN = 1, then Config[2:0] defines
GPIO13
the ROM type.
GPIO12
b) If BIOS_ROM_EN = 0, then Config[2:0] defines
GPIO11
the primary memory apertur e size.
Enable external BIOS ROM device (Intern al PD)
GPIO22
0: Diable, 1: Enable
00: No audio function; 10: Audio for DisplayPort only;
HSYNC
01: Audio for DisplayPort and HDMI if adapter is detected;
VSYNC
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-o n
1= Advertises the PCI-E device as 5.0 GT/s capable at power-o n
5.0 GT/s capability will be controlled by software
Internal use only. THIS PAD HAS AN INTERNAL
H2SYNC
(GENLK_CLK)
PULL-DOWN AND MUST BE 0 V AT RESET. The
GPIO8
pad may be left unconnected
GPIO21
@
@
R428
10K_0402_5%
R429
10K_0402_5%
R427
12
12
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
@
@
R434
10K_0402_5%
R433
R435
10K_0402_5%
12
12
VGA_GPIO 0
VGA_GPIO 1
VGA_GPIO 2
VGA_GPIO 3
VGA_GPIO 4
VGA_GPIO 11
VGA_GPIO 12
VGA_GPIO 13
GPIO_22_ROMCSB
12
R445 1M_0402_5%
Y3
2 1
27MHZ_16PF_X5H027000FG1H
GPIO5 fast-power reduction:
HW control will casue display disturb
should use SW method control
GPIO6 voltage control signal ,No use can NC
GPIO7 Controls backlight on/off.
Active High ,need external PD
if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
GPIO6,15,16,20
Voltage control signal
GPIO6,15 no use can NC
Thermal monitor interrupt
Critical temperature fault
Reserved
External BIOS device
ON(1)/OFF(0) inter PD
Internal Debug
no use can floating
ON(1)/OFF(0)
Stereo Sync
no use can NC
For ATI Cross fire
no use can NC
C354
12P_0402_50V8J
memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010
SM010030010
200ma 120ohm@100mhz DCR 0.2
+1.8VSG
+1.0VSG
BLM18AG121SN1D_0603
AMD ref:470ohm/1A
BLM18AG121SN1D_0603
AMD ref:470ohm/1A
Setting
0
0
1
1
001
0
00
1
DNI
GPU_VID048
GPU_VID148
+1.8VSG
L10
L126
12
12
+DPLL_ PVDD
10U_0603_6.3V6M
+DPLL_VDDC
10U_0603_6.3V6M
1
2
Seymour(XT)
Location
VRAM
4 4
Samsung
SA00004GS30 64M16
K4W1G1646G-BC11
Samsung
SA000047QA0 128M16
K4W2G1646C-HC11
Hynix
SA000041S60 64M16
H5TQ1G63DFR-11C
Hynix
SA00003YO30 128M16
H5TQ2G63BFR-11C
VRAM_ID2
VRAM_ID3
010
A
VRAM_ID0VRAM_ID1
000
0
+1.8VSG
0
1
000
L127
BLM18AG121SN1D_0603
120ohm/0.3A
Future ASIC call MLPS
OLD ASIC is Fan PWM
12
1001
B
Don't have this strap on
Whistler and Seymour
NC on Park,
Robson and Seymour
NC on Park, Robson
NC on Park,
Robson and Seymour
Global Swap Lock on
Multiple GPUs
Move to
DDCCLK_AUX3P,DDCDATA_AUX3N,
12
R413 10K_0402_5%
T30
T32
T18
T33
T34
T17
R430 499_0402_1%
1 2
R431 249_0402_1%
1 2
C335 0.1U_0402_16V4Z
1 2
1
C339
2
C345
C346
0.1U_0402_16V4Z
1
2
1
1
C350
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
1
2
C347
1U_0402_6.3V6K
1
2
R443
0_0402_5%
GPU_THERM_D+
GPU_THERM_D-
+TSVDD
1
C351
1U_0402_6.3V6K
2
B
VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
VGA_GPIO 0
VGA_GPIO 1
VGA_GPIO 2
VGA_GPIO 3
VGA_GPIO 4
VGA_ENBKL
ROM
VGA_GPIO 11
VGA_GPIO 12
VGA_GPIO 13
GPU_VID0
THM_ALERT#
GPU_VID1
GPIO_22_ROMCSB
C341
1U_0402_6.3V6K
C340
1
2
XO_IN
XO_IN2
12
R444
@
@
0_0402_5%
1 2
10mil
C352
0.1U_0402_16V4Z
20mil
+VGA_VREF
20mil
20mil
27MCLK
XTALOUT
U8B
MUTI GFX
AR8
NC_DVPCNTL_MVP_0
AU8
NC_DVPCNTL_MVP_1
AP8
NC_DVPCNTL_0
AW8
NC_DVPCNTL_1
AR3
NC_DVPCNTL_2
AR1
NC_DVPCLK
AU1
DVPDATA_0
AU3
DVPDATA_1
AW3
DVPDATA_2
AP6
DVPDATA_3
AW5
DVPDATA_4
AU5
DVPDATA_5
AR6
DVPDATA_6
AW6
DVPDATA_7
AU6
DVPDATA_8
AT7
DVPDATA_9
AV7
DVPDATA_10
AN7
DVPDATA_11
AV9
DVPDATA_12
AT9
DVPDATA_13
AR10
DVPDATA_14
AW10
DVPDATA_15
AU10
DVPDATA_16
AP10
NC_DVPDATA_17
AV11
NC_DVPDATA_18
AT11
NC_DVPDATA_19
AR12
NC_DVPDATA_20
AW12
NC_DVPDATA_21
AU12
NC_DVPDATA_22
AP12
NC_DVPDATA_23
AJ21
SWAPLOCKA
AK21
SWAPLOCKB
I2C
AK26
SCL
AJ26
SDA
GENERAL PURPOSE I/O
AH20
GPIO_0
AH18
GPIO_1
AN16
GPIO_2
AH23
GPIO_3_SMBDATA
AJ23
GPIO_4_SMBCLK
AH17
GPIO_5_AC_BATT
AJ17
GPIO_6
AK17
GPIO_7_BLON
AJ13
GPIO_8_ROMSO
AH15
GPIO_9_ROMSI
AJ16
GPIO_10_ROMSCK
AK16
GPIO_11
AL16
GPIO_12
AM16
GPIO_13
AM14
GPIO_14_HPD2
AM13
GPIO_15_PWRCNTL_0
AK14
GPIO_16
AG30
GPIO_17_THERMAL_INT
AN14
GPIO_18_HPD3
AM17
GPIO_19_CTF
AL13
GPIO_20_PWRCNTL_1
AJ14
GPIO_21_BB_EN
AK13
GPIO_22_ROMCSB
AN13
GPIO_23_CLKREQB
AM23
JTAG_TRSTB
AN23
JTAG_TDI
AK23
JTAG_TCK
AL24
JTAG_TMS
AM24
JTAG_TDO
AJ19
GENERICA
AK19
GENERICB
AJ20
GENERICC
AK20
GENERICD
AJ24
GENERICE_HPD4
AH26
NC_GENERICF_HPD5
AH24
NC_GENERICG_HPD6
AK24
HPD1
AH13
VREFG
AM32
DPLL_PVDD
AN32
AN31
AV33
AU34
AW34
AW35
AF29
AG29
AK32
AL31
AJ32
AJ33
75mA
DPLL_PVSS
PLL/CLOCK
DPLL_VDDC
125mA
XTALIN
XTALOUT
XO_IN
XO_IN2
DPLUS
THERMAL
DMINUS
TS_FDO
TS_A/ NC
TSVDD
20mA
TSVSS
2160809000A11SEYMOU_FCBGA962
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
DPA
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
NC_TXCDP_DPD3P
NC_TXCDM_DPD3N
NC_TX3P_DPD2P
NC_TX3M_DPD2N
DPD
NC_TX4P_DPD1P
NC_TX4M_DPD1N
NC_TX5P_DPD0P
NC_TX5M_DPD0N
DAC1
HSYNC
VSYNC
RSET
70mA
AVDD
AVSSQ
100mA
VDD1DI
VSS1DI
R2/NC
R2B/NC
G2/NC
G2B/NC
B2/NC
B2B/NC
C/NC
Y/NC
COMP/NC
DAC2
H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC
VDD2DI/NC
100mA
VSS2DI/NC
100mA
A2VDD/NC
2mA
A2VDDQ/NC
A2VSSQ/TSVSSQ
R2SET/NC
DDC/AUX
DDC1CLK
DDC1DATA
AUX1P
AUX1N
DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
C
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
R
AD37
RB
AE36
G
AD35
GB
AF37
B
AE38
BB
HSYNC
AC36
VSYNC
AC38
R414 499_0402_1%
AB34
+AVDD
AD34
AE34
+VDD1DI
AC33
AC34
AC30
AC31
AD30
AD31
AF30
AF31
AC32
AD32
AF32
AD29
AC29
10mil
+VDD2DI
AG31
VSS2DI
AG32
10mil
+A2VDD
AG33
10mil
+A2VDDQ
AD33
AF33
1 2
AA29
R436 715_0402_1%
AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
NC on Park,
AM29
Robson and Seymour
AN21
AM21
AJ30
AJ31
AK30
AK29
C
NC on Park,
Robson and Seymour
Not share via for other GND
1 2
10mil
T2
T3
NC on Park,
Robson and Seymour
1U_0402_6.3V6K
1
2
C333
0.1U_0402_16V4Z
C332
1U_0402_6.3V6K
1
1
1
2
2
2
Back compatibility(Manhattan)
R77 0_0402_5%@
1 2
R209 0_0402_5%@
1 2
R70 0_0402_5%@
1 2
R256 0_0402_5%@
1 2
D
+3VSG
@
C324
0.1U_0402_16V4Z
1
GPU_THERM_D+ VGA_SMB_DA2
2
GPU_THERM_D-
04/19
VGA_SMB_CK2
VGA_SMB_DA2
L8
BLM18AG121SN1D_0603
10mil
C330
0.1U_0402_16V4Z
C329
1
1
2
2
L9
BLM18AG121SN1D_0603
C334
10U_0603_6.3V6M
AMD ref:120ohm/0.3A
SM010030010
200ma 120ohm@100mhz DCR 0.2
@
C342
1U_0402_6.3V6K
1
1
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C331
22U_0805_6.3V6M
AMD ref:120ohm/0.3A
12
+1.8VSG
+VDD1DI
@
@
C344
10U_0603_6.3V6M
C343
0.1U_0402_16V4Z
1
2
12
+1.8VSG
NC on Whistler
and Seymour
Whistler and Seymour
Except A2VSSQ change to TSVSSQ,
others are NC
+3VSG
+1.8VSG
2010/07/12 2012/07/12
Compal Secret Data
Deciphered Date
D
External VGA Thermal Sensor
U9
@
1
VDD
2
2200P_0402_50V7K
1 2
C325
@
@
R1814 0_0402_5%
@
R1815 0_0402_5%
SM_DA2
SM_CK2
D+
3
D-
THERM#4GND
ADM1032ARMZ-2REEL_MSOP8
+3VSG
R392
4.7K_0402_5%
1 2
12
12
R1816 0_0402_5%
R1817 0_0402_5%
R393
4.7K_0402_5%
1 2
SM_CK2
SM_DA2
AUD Strap
GPIO8 Serial-ROM output from ROM.
GPIO9 Serial-ROM input to ROM.
GPIO10 Serial-ROM clock to ROM.
GPIO22 erternal BIOS-ROM enable
GPIO8,GPIO9,GPIO10 no use can NC
GPIO22
Enable need 3K PH ,no use must NC
E
VGA_SMB_CK2
8
SCLK
7
SDATA
ALERT#
12
12
Title
Vancouver_Strape/DP/HDMI//CRT
Size Document Number R ev
Custom
Date: Sheet
THM_ALERT#
6
5
HSYNC:VSYNC
11: Audio for both DisplayPort and HDMI
VSYNC
HSYNC
1 2
R391 4.7K_0402_5%@
+3VSG
2
EC_SMB_CK2
61
Q8A DMN66D0LDW-7_SOT363-6
5
EC_SMB_DA2
34
Q8B DMN66D0LDW-7_SOT363-6
VGA_GPIO 3
VGA_GPIO 4
04/19
R417 10K_0402_5%@
1 2
R418 10K_0402_5%@
1 2
if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
if GPIO22 Low ,GPIO 11-13->CFG[0:2]
Config Primary memory-aperture size
CFG[3:0]
128MB 000
256MB 001 *
64MB 010
EC_SMB_CK2 6,32
EC_SMB_DA2 6,32
Compal Electronics, Inc.
QBL70 LA-7553P
E
19 51Friday , April 29, 2011
+3VSG
of
+3VSG
0.22
A
B
C
D
E
U8C
DDR2
GDDR3/GDDR5
MDA[0..63]23
1 1
+1.5VSG
12
R446
40.2_0402_1%
12
R448
100_0402_1%
+1.5VSG
12
R450
40.2_0402_1%
2 2
100_0402_1%
3 3
R452
12
MDA[0..63]
15mil
MVREFDA
C355
0.1U_0402_16V4Z
1
2
15mil
MVREFSA ODTB0
C357
0.1U_0402_16V4Z
1
2
+1.5VSG
1 2
R454 243_0402_1%
1 2
R455 243_0402_1%
1 2
R456 243_0402_1%
1 2
R457 243_0402_1%
1 2
R458 243_0402_1%
1 2
R460 243_0402_1%
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MVREFDA
MVREFSA
DDR3
C37
NC_DQA0_0/DQA_0
C35
NC_DQA0_1/DQA_1
A35
NC_DQA0_2/DQA_2
E34
NC_DQA0_3/DQA_3
G32
NC_DQA0_4/DQA_4
D33
NC_DQA0_5/DQA_5
F32
NC_DQA0_6/DQA_6
E32
NC_DQA0_7/DQA_7
D31
NC_DQA0_8/DQA_8
F30
NC_DQA0_9/DQA_9
C30
NC_DQA0_10/DQA_10
A30
NC_DQA0_11/DQA_11
F28
NC_DQA0_12/DQA_12
C28
NC_DQA0_13/DQA_13
A28
NC_DQA0_14/DQA_14
E28
NC_DQA0_15/DQA_15
D27
NC_DQA0_16/DQA_16
F26
NC_DQA0_17/DQA_17
C26
NC_DQA0_18/DQA_18
A26
NC_DQA0_19/DQA_19
F24
NC_DQA0_20/DQA_20
C24
NC_DQA0_21/DQA_21
A24
NC_DQA0_22/DQA_22
E24
NC_DQA0_23/DQA_23
C22
NC_DQA0_24/DQA_24
A22
NC_DQA0_25/DQA_25
F22
NC_DQA0_26/DQA_26
D21
NC_DQA0_27/DQA_27
A20
NC_DQA0_28/DQA_28
F20
NC_DQA0_29/DQA_29
D19
NC_DQA0_30/DQA_30
E18
NC_DQA0_31/DQA_31
C18
NC_DQA1_0/DQA_32
A18
NC_DQA1_1/DQA_33
F18
NC_DQA1_2/DQA_34
D17
NC_DQA1_3/DQA_35
A16
NC_DQA1_4/DQA_36
F16
NC_DQA1_5/DQA_37
D15
NC_DQA1_6/DQA_38
E14
NC_DQA1_7/DQA_39
F14
NC_DQA1_8/DQA_40
D13
NC_DQA1_9/DQA_41
F12
NC_DQA1_10/DQA_42
A12
NC_DQA1_11/DQA_43
D11
NC_DQA1_12/DQA_44
F10
NC_DQA1_13/DQA_45
A10
NC_DQA1_14/DQA_46
C10
NC_DQA1_15/DQA_47
G13
NC_DQA1_16/DQA_48
H13
NC_DQA1_17/DQA_49
J13
NC_DQA1_18/DQA_50
H11
NC_DQA1_19/DQA_51
G10
NC_DQA1_20/DQA_52
G8
NC_DQA1_21/DQA_53
K9
NC_DQA1_22/DQA_54
K10
NC_DQA1_23/DQA_55
G9
NC_DQA1_24/DQA_56
A8
NC_DQA1_25/DQA_57
C8
NC_DQA1_26/DQA_58
E8
NC_DQA1_27/DQA_59
A6
NC_DQA1_28/DQA_60
C6
NC_DQA1_29/DQA_61
E6
NC_DQA1_30/DQA_62
A5
NC_DQA1_31/DQA_63
L18
NC_MVREFDA
L20
NC_MVREFSA
L27
NC_MEM_CALRN0
N12
MEM_CALRN1
AG12
NC_MEM_CALRN2
M12
MEM_CALRP1
M27
NC_MEM_CALRP0
AH12
NC_MEM_CALRP2
2160809000A11SEYMOU_FCBGA962
DDR2
GDDR5/GDDR3
DDR3
NC_MAA0_0/MAA_0
NC_MAA0_1/MAA_1
NC_MAA0_2/MAA_2
NC_MAA0_3/MAA_3
NC_MAA0_4/MAA_4
NC_MAA0_5/MAA_5
NC_MAA0_6/MAA_6
NC_MAA0_7/MAA_7
NC_MAA1_0/MAA_8
NC_MAA1_1/MAA_9
NC_MAA1_2/MAA_10
NC_MAA1_3/MAA_11
NC_MAA1_4/MAA_12
NC_MAA1_5/MAA_13_BA2
NC_MAA1_6/MAA_14_BA0
NC_MAA1_7/MAA_A15_BA1
NC_WCKA0_0/DQMA_0
NC_WCKA0B_0/DQMA_1
NC_WCKA0_1/DQMA_2
NC_WCKA0B_1/DQMA_3
NC_WCKA1_0/DQMA_4
NC_WCKA1B_0/DQMA_5
NC_WCKA1_1/DQMA_6
NC_WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
MEMORY INTERFACE A
NC_EDCA0_0/QSA_0/RDQSA_0
NC_EDCA0_1/QSA_1/RDQSA_1
NC_EDCA0_2/QSA_2/RDQSA_2
NC_EDCA0_3/QSA_3/RDQSA_3
NC_EDCA1_0/QSA_4/RDQSA_4
NC_EDCA1_1/QSA_5/RDQSA_5
NC_EDCA1_2/QSA_6/RDQSA_6
NC_EDCA1_3/QSA_7/RDQSA_7
NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DDBIA1_3/QSA_7B/WDQSA_7
NC_ADBIA0/ODTA0
NC_ADBIA1/ODTA1
NC_CSA0B_0
NC_CSA0B_1
NC_CSA1B_0
NC_CSA1B_1
GDDR5
NC_CLKA0
NC_CLKA0B
NC_CLKA1
NC_CLKA1B
NC_RASA0B
NC_RASA1B
NC_CASA0B
NC_CASA1B
NC_CKEA0
NC_CKEA1
NC_WEA0B
NC_WEA1B
NC_MAA0_8
NC_MAA1_8
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
K24
K27
M13
K16
K21
J20
K26
L15
H23
J19
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
ODTA0
ODTA1
CLKA0
CLKA0#
CLKA1
CLKA1#
RASA0#
RASA1#
CASA0#
CASA1#
CSA0#_0
CSA1#_0
CKEA0
CKEA1
WEA0#
WEA1#
MAA[0..12]
A_BA[0..2]
DQMA#[0..7]
QSA[0..7]
QSA#[0..7]
ODTA0 23
ODTA1 23
CLKA0 23
CLKA0# 23
CLKA1 23
CLKA1# 23
RASA0# 23
RASA1# 23
CASA0# 23
CASA1# 23
CSA0#_0 23
CSA1#_0 23
CKEA0 23
CKEA1 23
WEA0# 23
WEA1# 23
MAA13 23
MAA[0..12] 23
A_BA[0..2] 23
DQMA#[0..7] 23
40.2_0402_1%
QSA[0..7] 23
100_0402_1%
QSA#[0..7] 23
40.2_0402_1%
100_0402_1%
R447
R449
R451
R453
+1.5VSG
+1.5VSG
MDB[0..63]24
12
MVREFDB
12
12
MVREFSB
12
MDB[0..63]
15mil
C356
0.1U_0402_16V4Z
1
2
15mil
C358
0.1U_0402_16V4Z
1
2
51.1_0402_1%
Note:
route 50ohms single-ended
and 100ohms diff
and keep short
REF137-03 suggest
@
R464
@
R459
5.11K_0402_1%
0.1U_0402_16V4Z
C360
2
1
12
12
TEST_MCLK
TEST_YCLK
0.1U_0402_16V4Z
2
1
12
R465
@
51.1_0402_1%
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MVREFDB
MVREFSB
TESTEN
C361
@
U8D
DDR2
GDDR3/GDDR5
DDR3
C5
DQB0_0/DQB_0
C3
DQB0_1/DQB_1
E3
DQB0_2/DQB_2
E1
DQB0_3/DQB_3
F1
DQB0_4/DQB_4
F3
DQB0_5/DQB_5
F5
DQB0_6/DQB_6
G4
DQB0_7/DQB_7
H5
DQB0_8/DQB_8
H6
DQB0_9/DQB_9
J4
DQB0_10/DQB_10
K6
DQB0_11/DQB_11
K5
DQB0_12/DQB_12
L4
DQB0_13/DQB_13
M6
DQB0_14/DQB_14
M1
DQB0_15/DQB_15
M3
DQB0_16/DQB_16
M5
DQB0_17/DQB_17
N4
DQB0_18/DQB_18
P6
DQB0_19/DQB_19
P5
DQB0_20/DQB_20
R4
DQB0_21/DQB_21
T6
DQB0_22/DQB_22
T1
DQB0_23/DQB_23
U4
DQB0_24/DQB_24
V6
DQB0_25/DQB_25
V1
DQB0_26/DQB_26
V3
DQB0_27/DQB_27
Y6
DQB0_28/DQB_28
Y1
DQB0_29/DQB_29
Y3
DQB0_30/DQB_30
Y5
DQB0_31/DQB_31
AA4
DQB1_0/DQB_32
AB6
DQB1_1/DQB_33
AB1
DQB1_2/DQB_34
AB3
DQB1_3/DQB_35
AD6
DQB1_4/DQB_36
AD1
DQB1_5/DQB_37
AD3
DQB1_6/DQB_38
AD5
DQB1_7/DQB_39
AF1
DQB1_8/DQB_40
AF3
DQB1_9/DQB_41
AF6
DQB1_10/DQB_42
AG4
DQB1_11/DQB_43
AH5
DQB1_12/DQB_44
AH6
DQB1_13/DQB_45
AJ4
DQB1_14/DQB_46
AK3
DQB1_15/DQB_47
AF8
DQB1_16/DQB_48
AF9
DQB1_17/DQB_49
AG8
DQB1_18/DQB_50
AG7
DQB1_19/DQB_51
AK9
DQB1_20/DQB_52
AL7
DQB1_21/DQB_53
AM8
DQB1_22/DQB_54
AM7
DQB1_23/DQB_55
AK1
DQB1_24/DQB_56
AL4
DQB1_25/DQB_57
AM6
DQB1_26/DQB_58
AM1
DQB1_27/DQB_59
AN4
DQB1_28/DQB_60
AP3
DQB1_29/DQB_61
AP1
DQB1_30/DQB_62
AP5
DQB1_31/DQB_63
Y12
MVREFDB
AA12
MVREFSB
AD28
TESTEN
AK10
CLKTESTA
AL10
CLKTESTB
2160809000A11SEYMOU_FCBGA962
DDR2
GDDR5/GDDR3
DDR3
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
MEMORY INTERFACE B
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7
DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
WEB0B
WEB1B
MAB0_8
MAB1_8
DRAM_RST
GDDR5
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
T7
W7
L9
L8
AD8
AD7
T10
Y10
W10
AA10
P10
L10
AD10
AC10
U10
AA11
N10
AB11
T8
W8
AH11
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
ODTB1
CLKB0
CLKB0#
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0#_0
CSB1#_0
CKEB0
CKEB1
WEB0#
WEB1#
R461 10_0402_5%
R463
5.11K_0402_1%
1 2
1 2
1
C359
120P_0402_50V8
2
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
Park&Seymour is single channel for
MAB[0..12]
B_BA[0..2]
DQMB#[0..7]
QSB[0..7]
QSB#[0..7]
ODTB0 24
ODTB1 24
CLKB0 24
CLKB0# 24
CLKB1 24
CLKB1# 24
RASB0# 24
RASB1# 24
CASB0# 24
CASB1# 24
CSB0#_0 24
CSB1#_0 24
CKEB0 24
CKEB1 24
WEB0# 24
WEB1# 24
MAB13 24
1 2
R462 51.1_0402_1%
MAB[0..12] 24
B_BA[0..2] 24
DQMB#[0..7] 24
QSB[0..7] 24
QSB#[0..7] 24
VRAM_RST# 23, 24
memory (channel B only)
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/07/12 2012/07/12
Compal Secret Data
Deciphered Date
Title
Size Document Num ber Rev
Custom
D
Date: Sh eet
Compal Electronics, Inc.
Vancouver_Memory
QBL70 LA-7553P
E
0.22
of
20 51Friday, April 29, 2011
A
+1.5VSG
1
+
C374
330U_2.5V_M
2
C374 change to SF000002Z00
1 1
SM010030010
300ma 120ohm@100mhz DCR 0.3
20101228
C396
10U_0603_6.3V6M
1
2
+1.8VSG
120ohm/0.3A
1
2
1
2
1
2
C375
1U_0402_6.3V6K
1
2
C385
1U_0402_6.3V6K
1
2
C371
10U_0603_6.3V6M
1
2
BLM18AG121SN1D_0603
C362
1U_0402_6.3V6K
C376
1U_0402_6.3V6K
1
2
C366
1U_0402_6.3V6K
C386
1U_0402_6.3V6K
1
2
C373
10U_0603_6.3V6M
C372
10U_0603_6.3V6M
1
2
L129
Ref137-12~ remove Bead
2 2
SM010030010
300ma 120ohm@100mhz DCR 0.3
+3VSG
+1.8VSG
120ohm/0.3A
L16
BLM18AG121SN1D_0603
12
470ohm/1A
SM010030010
200ma 120ohm@100mhz DCR 0.2
+1.8VSG
3 3
4 4
SM010030010
200ma 120ohm@100mhz DCR 0.2
+1.8VSG
BLM18AG121SN1D_0603
L17
BLM18AG121SN1D_0603
L20
12
12
1
2
C459
1U_0402_6.3V6K
C458
10U_0603_6.3V6M
1
1
2
2
C440
10U_0603_6.3V6M
1
2
C460
0.1U_0402_16V4Z
1
2
C442
0.1U_0402_16V4Z
C443
1U_0402_6.3V6K
C441
1U_0402_6.3V6K
1
1
2
2
+1.0VSG
BLM18AG121SN1D_0603
SM010030010
200ma 120ohm@100mhz DCR 0.2
470ohm/1A
C444
0.1U_0402_16V4Z
1
2
L18
12
B
U8E
1
2
1
2
1
2
C377
1U_0402_6.3V6K
C378
1U_0402_6.3V6K
1
1
2
2
C388
1U_0402_6.3V6K
C387
1U_0402_6.3V6K
1
1
2
2
C398
1U_0402_6.3V6K
C397
10U_0603_6.3V6M
1
1
2
2
12
1
2
1
2
C437
10U_0603_6.3V6M
C438
1U_0402_6.3V6K
1
1
2
2
C445
10U_0603_6.3V6M
C446
1U_0402_6.3V6K
1
1
2
2
GCORE_SEN48
C363
1U_0402_6.3V6K
C380
1U_0402_6.3V6K
C379
1U_0402_6.3V6K
1
1
2
2
C390
1U_0402_6.3V6K
C367
1U_0402_6.3V6K
C389
1U_0402_6.3V6K
1
1
2
2
C401
C399
C402
C415
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C447
1
2
1
2
1
2
20mil
10mil
20mil
C400
1U_0402_6.3V6K
C403
1U_0402_6.3V6K
C426
1U_0402_6.3V6K
C439
NC 20101116
0_0402_5%
1U_0402_6.3V6K
1
2
C404
0.1U_0402_16V4Z
1
2
C427
0.1U_0402_16V4Z
1
2
+VDDR4_5
+MPV_18
+SPV_18
+SPV10
GCORE_SEN
@
R466
10mil
20mil
FB_GND
12
20mil
+VDD_CT
10mil
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1
2
MEM I/O
AC7
VDDR1#1
AD11
VDDR1#2
AF7
VDDR1#3
AG10
VDDR1#4
AJ7
VDDR1#5
AK8
VDDR1#6
AL9
VDDR1#7
G11
VDDR1#8
G14
VDDR1#9
G17
VDDR1#10
G20
VDDR1#11
G23
VDDR1#12
G26
VDDR1#13
G29
VDDR1#14
H10
VDDR1#15
J7
VDDR1#16
J9
VDDR1#17
K11
VDDR1#18
K13
VDDR1#19
K8
VDDR1#20
L12
VDDR1#21
L16
VDDR1#22
L21
VDDR1#23
L23
VDDR1#24
L26
VDDR1#25
L7
VDDR1#26
M11
VDDR1#27
N11
VDDR1#28
P7
VDDR1#29
R11
VDDR1#30
U11
VDDR1#31
U7
VDDR1#32
Y11
VDDR1#33
Y7
VDDR1#34
LEVEL
TRANSLATION
AF26
VDD_CT#1
AF27
VDD_CT#2
AG26
AG27
AF23
AF24
AG23
AG24
AF13
AF15
AG13
AG15
AD12
AF11
AF12
AG11
AM10
AN10
AF28
AG28
AH29
M20
M21
V12
U12
H7
H8
AN9
219mA
VDD_CT#3
VDD_CT#4
I/O
VDDR3#1
VDDR3#2
60mA
VDDR3#3
VDDR3#4
VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8
170mA
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6
NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB
PLL
MPV18#1
150mA
MPV18#2
75mA
SPV18
120mA
SPV10
SPVSS
VOLTAGE
SENESE
FB_VDDC
FB_VDDCI
FB_GND
2160809000A11SEYMOU_FCBGA962
C
PCIE
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
440mA
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCI E_PVDD
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
2A3400mA
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
CORE
POWER
47A
VDDC/BIF_VDDC#33
55mA
VDDC/BIF_VDDC#42
5A
ISOLATED
CORE I/O
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15
VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
Granville VDDC:47A
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
Granville VDDCI:4.6A
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
D
Seymour/Whist ler
PCIE_VDDR,PCIE_ PVDD can combian to PCI E_VDDR
40mil
C381
0.1U_0402_16V4Z
1
2
C391
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
1
2
+BIF_VDDC
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park , VDDCI and VDDC can shar e one common regulator
(GDDR3/DDR3 1. 12V@4A VDDCI)
(GDDR5 1.12V @16A VDDCI)
+VDDCI
烉烉烉烉
+PCIE_VDDR
1
2
1
2
C405
C416
C428
1
2
C364
1U_0402_6.3V6K
C382
0.1U_0402_16V4Z
C392
1U_0402_6.3V6K
1
2
1
2
1
2
2010/04/27
non-BACO design,N27,T27
connect BIF_VDDC to VDDC
For BACO design
C448
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
1
2
C406
1U_0402_6.3V6K
C417
1U_0402_6.3V6K
C429
10U_0603_6.3V6M
+BIF_VDDC
160mil
1U_0402_6.3V6K
1
2
C368
C449
C383
1U_0402_6.3V6K
1
2
C393
1U_0402_6.3V6K
1
2
C407
1U_0402_6.3V6K
1
2
C418
1U_0402_6.3V6K
1
2
C430
10U_0603_6.3V6M
1
2
C450
1U_0402_6.3V6K
1
2
SM010014520 3000ma 220ohm@100mhz DCR 0.04
C365
1U_0402_6.3V6K
C384
10U_0603_6.3V6M
1
1
2
2
1
2
BIF_VDDC
Park/Madison:Connect to VDDC
Seymour/Whisler:
dGPU operating:VDDC
BACO mode:+1.0 V
1
2
C369
1U_0402_6.3V6K
1
2
C408
1U_0402_6.3V6K
1
2
C419
1U_0402_6.3V6K
1
2
C431
10U_0603_6.3V6M
1
2
C451
1U_0402_6.3V6K
1
2
C394
1U_0402_6.3V6K
C370
1U_0402_6.3V6K
1
1
2
2
C409
1U_0402_6.3V6K
1
1
2
2
C420
1U_0402_6.3V6K
1
1
2
2
C432
10U_0603_6.3V6M
1
1
2
2
C453
1U_0402_6.3V6K
C452
1U_0402_6.3V6K
1
1
2
2
C461
1U_0402_6.3V6K
1
1
2
2
L128
FBMA-L11-201209-221LMA 30T_0805
220ohm/2A
C395
10U_0603_6.3V6M
C411
1U_0402_6.3V6K
C410
1U_0402_6.3V6K
1
2
C422
1U_0402_6.3V6K
C421
1U_0402_6.3V6K
1
2
C433
10U_0603_6.3V6M
C434
10U_0603_6.3V6M
1
C435
2
330U_D2_2V_Y
C455
1U_0402_6.3V6K
C454
1U_0402_6.3V6K
1
2
C462
0.1U_0402_16V4Z
C463
10U_0603_6.3V6M
1
2
+1.0VSG
C412
1U_0402_6.3V6K
1
2
C423
1U_0402_6.3V6K
1
2
1
+
2
C456
1U_0402_6.3V6K
1
2
C464
10U_0603_6.3V6M
1
2
E
12
C436
330U_D2_2V_Y
1
2
1
2
1
+
2
C413
1U_0402_6.3V6K
C424
1U_0402_6.3V6K
C474
390U_2.5V_10M
+1.8VSG
C414
1U_0402_6.3V6K
+VGA_CORE
1
Granville PRO VDDC:47A
2
Madison PRO VDDC+VDDCI=31 .3A
Whistler PRO VDDC+VDDCI=24A
SeymourXT VDDC+VDDCI=14.2A
C425
1U_0402_6.3V6K
1
RobsonXT VDDC+VDDCI=1 2.9A
2
1
1
+
+
C560
390U_2.5V_10M
2
2
SM01000BY00 5000ma 120ohm@100mhz DCR 0.02
12
C457
1U_0402_6.3V6K
1
2
C465
10U_0603_6.3V6M
1
2
L19
FBMA-L11-201209-121LMA 50T_0805
FBMA-L11-201209-121LMA 50T_0805
12
L21
Seymour/Whist ler
+VGA_CORE
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/07/12 2012/07/12
Compal Secret Data
Deciphered Date
D
Title
Size Doc ument Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Vancouver_Power/GND
QBL70 LA-7553P
E
of
21 51Friday, April 29, 2011
0.22
A
U8F
AB39
PCIE_VSS#1
E39
PCIE_VSS#2
F34
PCIE_VSS#3
F39
PCIE_VSS#4
G33
PCIE_VSS#5
G34
PCIE_VSS#6
H31
PCIE_VSS#7
H34
PCIE_VSS#8
H39
PCIE_VSS#9
J31
1 1
2 2
3 3
4 4
REF137-13 update
PCIE_VSS#10
J34
PCIE_VSS#11
K31
PCIE_VSS#12
K34
PCIE_VSS#13
K39
PCIE_VSS#14
L31
PCIE_VSS#15
L34
PCIE_VSS#16
M34
PCIE_VSS#17
M39
PCIE_VSS#18
N31
PCIE_VSS#19
N34
PCIE_VSS#20
P31
PCIE_VSS#21
P34
PCIE_VSS#22
P39
PCIE_VSS#23
R34
PCIE_VSS#24
T31
PCIE_VSS#25
T34
PCIE_VSS#26
T39
PCIE_VSS#27
U31
PCIE_VSS#28
U34
PCIE_VSS#29
V34
PCIE_VSS#30
V39
PCIE_VSS#31
W31
PCIE_VSS#32
W34
PCIE_VSS#33
Y34
PCIE_VSS#34
Y39
PCIE_VSS#35
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162
GND
A
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
2160809000A11SEYMOU_FCBGA962
GND/PX_EN#61
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
A39
AW1
AW39
DPA_VDD18,DPA_PVDD,DPB_V DD18,DPB_PVDD
can combian to DPAB_VDD18
DPC_VDD18,DPC_PVDD,DPD_V DD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD, DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18
DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F
PX_EN
PX_EN: PU at P.20
SBIOS will control VGA power on/off.
High :BACO mode enable
LOW:BACO disable
B
Seymour/Whistler
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10
Manhatann:300mA
Seymour:150mA
Manhatann:220mA
Seymour:110mA
PX_EN 25,32
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
+1.8VSG
L26
MBK1608221YZF_2P
FootPrint
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
+1.0VSG
L27
MBK1608221YZF_2P
FootPrint
DP mode:300mA
LVDS mode:440mA
12
C478
10U_0603_6.3V6M
1
2
DP mode:220mA
LVDS mode:240mA
12
C481
10U_0603_6.3V6M
1
2
Park/Madison :AL21left NC
Seymour/Whistler:
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:tu rn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC
B
C
D
烉烉烉烉
U8H
20mil
+DPABCD_VDD18
20mil
+DPABCD_VDD10
20mil
+DPABCD_VDD18
20mil
+DPABCD_VDD10
R467
150_0402_1%
12
20mil
C479
1U_0402_6.3V6K
1
1
2
2
+DPEF_VDD18
C480
0.1U_0402_16V4Z
20mil
+DPEF_VDD10
20mil
+DPEF_VDD18
20mil
+DPEF_VDD10
C483
0.1U_0402_16V4Z
C482
1U_0402_6.3V6K
1
1
2
2
R470
150_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DP C/D POWER
AP20
DPCD/DPC_VDD18#1
AP21
DPCD/DPC_VDD18#2
AP13
DPCD/DPC_VDD10#1
AT13
DPCD/DPC_VDD10#2
AN17
DP/DPC_VSSR#1
AP16
DP/DPC_VSSR#2
AP17
DP/DPC_VSSR#3
AW14
DP/DPC_VSSR#4
AW16
DP/DPC_VSSR#5
AP22
DPCD/DPD_VDD18#1
AP23
DPCD/DPD_VDD18#2
AP14
DPCD/DPD_VDD10#1
AP15
DPCD/DPD_VDD10#2
AN19
DP/DPD_VSSR#1
AP18
DP/DPD_VSSR#2
AP19
DP/DPD_VSSR#3
AW20
DP/DPD_VSSR#4
AW22
DP/DPD_VSSR#5
AW18
DPCD_CALR
DP E/F POWER
AH34
DPEF/DPE_VDD18#1
AJ34
DPEF/DPE_VDD18#2
AL33
DPEF/DPE_VDD10#1
AM33
DPEF/DPE_VDD10#2
AN34
DP/DPE_VSSR#1
AP39
DP/DPE_VSSR#2
AR39
DP/DPE_VSSR#3
AU37
DP/DPE_VSSR#4
AF34
DPEF/DPF_VDD18#1
AG34
DPEF/DPF_VDD18#2
AK33
DPEF/DPF_VDD10#1
AK34
DPEF/DPF_VDD10#2
AF39
DP/DPF_VSSR#1
AH39
DP/DPF_VSSR#2
AK39
DP/DPF_VSSR#3
AL34
DP/DPF_VSSR#4
AM34
DP/DPF_VSSR#5
AM39
12
DPEF_CALR
2160809000A11SEYMOU_FCBGA962
2010/07/12 2012/07/12
DP A/B POWER
DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2
DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5
DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2
DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2
DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5
DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS
DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS
DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS
Compal Secret Data
Deciphered Date
DPAB_CALR
AN24
+DPABCD_VDD18
AP24
AP31
+DPABCD_VDD10
AP32
AN27
AP27
AP28
AW24
AW26
AP25
+DPABCD_VDD18
AP26
AN33
+DPABCD_VDD10
AP33
AN29
AP29
AP30
AW30
AW32
AW28
20mA
+DPABCD_VDD18
AU28
AV27
20mA
+DPABCD_VDD18
AV29
AR28
20mA
+DPABCD_VDD18
AU18
AV17
20mA
+DPABCD_VDD18
AV19
AR18
20mA
+DPEF_VDD18
AM37
AN38
20mA
+DPEF_VDD18
AL38
AM35
D
20mil
20mil
20mil
20mil
R468
150_0402_1%
1 2
E
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
L23
300mA
220mA
1
C469
10U_0603_6.3V6M
2
C475
0.1U_0402_16V4Z
1
2
MBK1608221YZF_2P
1
1
C471
1U_0402_6.3V6K
C470
0.1U_0402_16V4Z
2
2
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
L25
MBK1608221YZF_2P
C477
10U_0603_6.3V6M
C476
1U_0402_6.3V6K
1
1
2
2
12
FootPrint
12
FootPrint
+1.8VSG
+1.0VSG
10mil
10mil
10mil
10mil
10mil
10mil
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Vancouver_Power/GND
QBL70 LA-7553P
E
22 51Friday, April 29, 2011
of
0.22
A
X76L02@
X76L04@
A_BA020
A_BA120
A_BA220
CKEA020
CSA0#_020
RASA0#20
CASA0#20
WEA0#20
R471
243_0402_1%
ODTA0_1
R484
56_0402_1%
1 2
R486
56_0402_1%
1 2
ODTA1_1
VREFCA_A1
VREFDA_Q1
CLKA0#
ODTA0_1
QSA2
QSA0
DQMA#2
DQMA#0
QSA#2
QSA#0
VRAM_RST#
12
+1.5VSG
ZZZ
X76L01@
1G SAM
ZZZ
1 1
X76L03@
1G HYNIX
MDA[0..63]20
MAA[13..0]20
DQMA#[7..0]20
QSA[7..0]20
2 2
QSA#[7..0]20
ZZZ
2G SAM
ZZZ
2G HYNIX
MDA[0..63]
VRAM_RST#20,24
Pull high for Madison and Park...
3 3
ODTA020
ODTA120
ODTA0
R483 0_0402_5%
ODTA1
R485 0_0402_5%
12
12
U11
M8
VREFCA
H1
VREFDQ
MAA0
N3
A0
MAA1
P7
A1
MAA2
P3
A2
N2
A3
MAA4
P8
A4
MAA5
P2
A5
MAA6
R8
A6
MAA7
R2
A7
MAA8
T8
A8
MAA9 MAA9
R3
MAA10
MAA11
MAA12
MAA13 MAA13 MAA13 MAA13
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
4.99K_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
@
+1.5VSG +1.5VSG
12
R475
15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
12
1
C484
R487
4.99K_0402_1%
2
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
0.1U_0402_16V4Z
B
MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17
MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6
+1.5VSG
+1.5VSG
4.99K_0402_1%
4.99K_0402_1%
R472
243_0402_1%
12
R476
12
R488
VREFCA_A2
VREFDA_Q2
A_BA0
A_BA1
A_BA2
CLKA0
CLKA0#
CKEA0
ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#
QSA3
QSA1
DQMA#3
DQMA#1
QSA#3
QSA#1
VRAM_RST#
12
C485
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
1
2
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
0.1U_0402_16V4Z
U12
96-BALL
SDRAM DDR3
12
R477
12
R489
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
@
VREFCA_A2VREFCA_A1 VREFCA_A4VREFDA_Q1 VREFCA_A3 VREFDA_Q3 VREFDA_Q4
C486
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
K4B1G1646E-HC12_FBGA96
4.99K_0402_1%
4.99K_0402_1%
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
0.1U_0402_16V4Z
1
2
C
CKEA120
CSA1#_020
RASA1#20
CASA1#20
WEA1#20
R473
243_0402_1%
12
12
C487
VREFCA_A3
VREFDA_Q3
MAA0
MAA1
MAA2
MAA3MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA0
A_BA1
A_BA2
CLKA1CLKA0
CLKA1#
ODTA1_1
QSA4
QSA5
DQMA#4
DQMA#5
QSA#4
QSA#5
VRAM_RST#
12
VREFDA_Q2
1
2
MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28
MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8
+1.5VSG
+1.5VSG
+1.5VSG+1.5VSG +1.5VSG+1.5VSG +1.5VSG+1.5VSG
R478
4.99K_0402_1%
R490
4.99K_0402_1%
0.1U_0402_16V4Z
4.99K_0402_1%
U13
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
12
R479
4.99K_0402_1%
12
C488
R491
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
4.99K_0402_1%
0.1U_0402_16V4Z
1
4.99K_0402_1%
2
MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33
MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47
+1.5VSG
+1.5VSG
R480
R492
D
R474
243_0402_1%
12
12
C489
0.1U_0402_16V4Z
1
2
VREFCA_A4
VREFDA_Q4
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA10
MAA11
MAA12
A_BA0
A_BA1
A_BA2
CLKA1
CLKA1#
CKEA1
ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#
QSA6
QSA7
DQMA#6
DQMA#7
QSA#6
QSA#7
VRAM_RST#
12
U14
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
12
R481
4.99K_0402_1%
12
R493
4.99K_0402_1%
C490
E
MDA48
E3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
@
1
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0.1U_0402_16V4Z
MDA51
F7
MDA55
F2
MDA54
F8
MDA50
H3
MDA52
H8
MDA49
G2
MDA53
H7
MDA63
D7
MDA58
C3
MDA60
C8
MDA59
C2
MDA61
A7
MDA56
A2
MDA62
B8
MDA57
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R482
4.99K_0402_1%
R494
4.99K_0402_1%
12
12
0.1U_0402_16V4Z
1
C491
2
+1.5VSG+1.5VSG +1.5VSG
1U_0402_6.3V6K
C492
1U_0402_6.3V6K
1
+1.5VSG
1
2
2
1
1
C513
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
CLKA020
CLKA0#20
4 4
CLKA120
CLKA1#20
1 2
R495 56_0402_1%
1 2
R1794 56_0402_1%
1 2
R497 56_0402_1%
1 2
R498 56_0402_1%
A
1
C512
0.01U_0402_16V7K
2
1
C521
0.01U_0402_16V7K
2
C493
1U_0402_6.3V6K
1
2
1
10U_0603_6.3V6M
C514
2
C495
1U_0402_6.3V6K
C496
C494
C515
1U_0402_6.3V6K
1
1
2
2
1
C516
10U_0603_6.3V6M
2
B
1U_0402_6.3V6K
1
2
1U_0402_6.3V6K
C497
1
2
C498
C500
1U_0402_6.3V6K
C501
1
2
1U_0402_6.3V6K
1
1
2
2
C499
1U_0402_6.3V6K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
C502
1U_0402_6.3V6K
C503
1U_0402_6.3V6K
1
2
+1.5VSG
C519
10U_0603_6.3V6M
1
2
2010/07/12 2012/07/12
1U_0402_6.3V6K
1
1
2
2
C520
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
Compal Secret Data
Deciphered Date
C506
1U_0402_6.3V6K
C505
1U_0402_6.3V6K
C504
1
1
2
2
C518
10U_0603_6.3V6M
C517
1
2
D
+1.5VSG
1
2
C508
1U_0402_6.3V6K
C507
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
Title
VRAM_DDR3 / Channel A
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
C510
1U_0402_6.3V6K
C511
C509
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
E
23 51Friday, April 29, 2011
0.22
of
A
VREFCB_A1
VREFDB_Q1
1 1
B_BA020
B_BA120
243_0402_1%
12
12
R499
ODTB0_1
R512
56_0402_1%
1 2
R514
56_0402_1%
1 2
ODTB1_1
B_BA220
CLKB0 CLKB0
CLKB0#
CKEB020
ODTB0_1
CSB0#_020
RASB0#20
CASB0#20
WEB0#20
QSB3
QSB1
DQMB#3
DQMB#1
QSB#3
QSB#1
VRAM_RST#
12
+1.5VSG
1
C530
0.01U_0402_16V7K
2
1
C559
0.01U_0402_16V7K
2
MDB[0..63]20
MAB[13..0]20
DQMB#[7..0]20
QSB[7..0]20
2 2
QSB#[7..0]20
MDB[0..63]
VRAM_RST#20,23
Pull high for Madison and Park...
3 3
ODTB020
ODTB120
CLKB020
CLKB0#20
CLKB120
4 4
CLKB1#20
ODTB0
ODTB1
R511
0_0402_5%
R513
0_0402_5%
R523 56_0402_1%
1 2
R524 56_0402_1%
1 2
R525
56_0402_1%
1 2
R526
56_0402_1%
1 2
A
U15
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
MAB13 MAB13 MAB13 MAB13
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
@
4.99K_0402_1%
4.99K_0402_1%
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
+1.5VSG +1.5VSG +1.5VSG+1.5VSG
12
R503
VREFCB_A1 VREFCB_A2 VREFDB_Q2VREFDB_Q1
12
0.1U_0402_16V4Z
R515
+1.5VSG +1.5VSG
1
C522
2
C532
1U_0402_6.3V6K
C531
1U_0402_6.3V6K
1
1
2
2
MDB26
E3
MDB28
F7
MDB27
F2
MDB31
F8
MDB25
H3
MDB30
H8
MDB24
G2
MDB29
H7
MDB15
D7
MDB10
C3
MDB12
C8
MDB11
C2
MDB13
A7
MDB9
A2
MDB14
B8
MDB8
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R504
4.99K_0402_1%
R516
4.99K_0402_1%
C533
1U_0402_6.3V6K
1
1
2
2
B
C534
1U_0402_6.3V6K
B
R500
243_0402_1%
12
12
C523
C535
1U_0402_6.3V6K
1
2
+1.5VSG
C
MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16
MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5
+1.5VSG
+1.5VSG
R506
4.99K_0402_1%
R518
4.99K_0402_1%
C539
1U_0402_6.3V6K
C538
1U_0402_6.3V6K
1
1
2
2
12
12
1U_0402_6.3V6K
1
2
R501
243_0402_1%
1
C525
2
C540
M8
H1
MAB0
N3
MAB1
MAB2
MAB3
N2
MAB4
MAB5
MAB6
R8
MAB7
R2
MAB8
MAB9
R3
MAB10
MAB11
R7
MAB12
N7
M7
M2
N8
M3
C7
D3
G3
4.99K_0402_1%
4.99K_0402_1%
C552
10U_0603_6.3V6M
1
2
P7
P3
P8
P2
T8
L7
T3
T7
J7
K7
K9
K1
L2
J3
K3
L3
F3
E7
B7
T2
L8
J1
L1
J9
L9
U16
96-BALL
SDRAM DDR3
12
12
1
2
10U_0603_6.3V6M
1
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
C524
C536
1U_0402_6.3V6K
C553
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
K4B1G1646E-HC12_FBGA96
@
R505
R517
C554
10U_0603_6.3V6M
1
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
0.1U_0402_16V4Z
1
2
C537
1U_0402_6.3V6K
1
2
VREFCB_A2
VREFDB_Q2
B_BA0
B_BA1
B_BA2 B_BA2
CLKB0#
CKEB0
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#
QSB2
QSB0
DQMB#2
DQMB#0
QSB#2
QSB#0
VRAM_RST#
12
0.1U_0402_16V4Z
1
2
C551
10U_0603_6.3V6M
1
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
VREFCB_A3
VREFDB_Q3
B_BA0
B_BA1
CLKB1
CKEB120
ODTB1_1
CSB1#_020
RASB1#20
CASB1#20
WEB1#20
QSB4
QSB5
DQMB#4
DQMB#5
QSB#4
QSB#5
VRAM_RST#
12
4.99K_0402_1%
0.1U_0402_16V4Z
4.99K_0402_1%
2010/07/12 2012/07/12
U17
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
@
+1.5VSG +1.5VSG +1.5VSG+1.5VSG
12
R507
12
R519
+1.5VSG
1
2
96-BALL
SDRAM DDR3
1
C526
2
C541
1U_0402_6.3V6K
1
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
4.99K_0402_1%
0.1U_0402_16V4Z
4.99K_0402_1%
C542
1U_0402_6.3V6K
1
2
Compal Secret Data
Deciphered Date
D
MDB35
E3
MDB37
F7
MDB34
F2
MDB39
F8
MDB33
H3
MDB38
H8
MDB32
G2
MDB36
H7
MDB44
D7
MDB43
C3
MDB47
C8
MDB41
C2
MDB45
A7
MDB40
A2
MDB46
B8
MDB42
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R508
R520
C544
1U_0402_6.3V6K
C543
1U_0402_6.3V6K
1
2
D
VREFCB_A4
VREFDB_Q4
B_BA0
B_BA1
B_BA2
CLKB1
CLKB1#CLKB1#
CKEB1
ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#
QSB6
QSB7
DQMB#6
DQMB#7
QSB#6
QSB#7
VRAM_RST#
12
R502
4.99K_0402_1%
4.99K_0402_1%
1
C556
10U_0603_6.3V6M
C555
2
R509
R521
1
2
243_0402_1%
12
VREFDB_Q3VREFCB_A3 VREFCB_A4 VREFDB_Q4
12
0.1U_0402_16V4Z
1
C527
2
C545
1U_0402_6.3V6K
1
2
+1.5VSG
1
10U_0603_6.3V6M
2
U18
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
@
12
12
C528
+1.5VSG
C546
1U_0402_6.3V6K
1
1
2
2
1
C557
10U_0603_6.3V6M
C558
10U_0603_6.3V6M
2
Title
VRAM_DDR3 / Channel B
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
4.99K_0402_1%
0.1U_0402_16V4Z
1
4.99K_0402_1%
2
C548
1U_0402_6.3V6K
C547
1U_0402_6.3V6K
1
2
Compal Electronics, Inc.
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R510
R522
1
2
E
MDB55
E3
MDB49
F7
MDB52
F2
MDB50
F8
MDB53
H3
MDB48
H8
MDB54
G2
MDB51
H7
MDB56
D7
MDB59
C3
MDB63
C8
MDB62
C2
MDB57
A7
MDB61
A2
MDB58
B8
MDB60
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
12
12
0.1U_0402_16V4Z
1
C529
2
C550
1U_0402_6.3V6K
C549
1U_0402_6.3V6K
1
2
E
24 51Friday, April 29, 2011
0.22
of
5
4
3
2
1
Power Sequence of Whistler and Seymour
SUSP#
+3VSG
(JUMP form +3VS)
VGA_ON
D D
VGA_PWR_ON
10ms
1.5_VDDC_PWREN
+VGA_CORE
+1.5VSG
VGA Muxless with BACO Status Mapping table
Normal mode
PX_EN
1.5_VDDC_PWREN
VDDC_EN
1.0_EN VGA_PWR_ON source signal
01
10 VGA Power Enable Signal Mapping table
1
01
+3.3VSG ON
+1.8VSG
+1.0VSG
+VGA_CORE
+1.5VSG
ON +1.8VSG
ON
ON
ON
+BIF_VDDC +VGA_CORE
BACO mode
0
ON
ON
ON
OFF
OFF
+1.0VSG
+3.3VSG
+1.0VSG
+VDDCI
+VGA_CORE
+1.5VSG
Whislter
VGA_ON
SUSP#
VGA_PWR_ON
VGA_PWR_ON
Combine with +VGA_CORE
1.5_VDDC_PWREN
1.5_VDDC_PWREN
+1.0VSG
+1.8VSG
For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON
PE_GPIO1
C C
Delay SUSP# 10ms
VGA_ON32
PE_GPIO113,32
B B
1 2
R1793 0_0402_5%
@
R119
1 2
10K_0402_1%
VGA_PWR_ON >2ms
For VGA Power on control
VGA_PWR_ON 38,42,45
20ms
PX_EN22,32
VGA_PWRGD13,48
1 2
R651 0_0402_5%
12
R1792
5.11K_0402_1%
1.5_VDD_PWREN
From +VGA_CORE regulator
VGA_PWR_ON
R650 10K_0402_5%
1 2
+3VS
2
G
1 2
R1797 0_0402_5%
13
D
Q22
S
2N7002_SOT23
C1104
0.1U_0402_16V4Z
12
R649 0_0402_5%
+3VS
5
2
P
B
1
A
G
NC7SZ08P5X_NL_SC70-5
3
+3VS
5
U20
2
P
B
Y
1
A
G
NC7SZ08P5X_NL_SC70-5
3
@
1 2
C1103
0.1U_0402_16V4Z
1 2
U19
1.5_VDD_PWREN
4
Y
1K_0402_5%
4
2
+5VS +5VS
R1795
1K_0402_5%
1 2
Q23A
DMN66D0LDW-7_SOT363-6
61
1.5_VDD_PWREN 38,48
R1796
1 2
34
5
VDDC_EN
1.0_EN
Q23B
DMN66D0LDW-7_SOT363-6
+1.0VSG
AO3416_SOT23-3
1.0_EN
VDDC_EN
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/08/04 2010/08/04
+VGA_CORE
Compal Secret Data
Deciphered Date
Q24
D
S
13
AO3416_SOT23-3
G
2
G
2
30mil
13
D
S
Q26
AO3416_SOT23-3
Q24 / Q25 / Q26 / Q27 change to SB00000FG10
20101228
2
1 3
1 3
D
D
Q25
S
G
2
2
G
S
Q114
AO3416_SOT23-3
+BIF_VDDC
30mil20mil
1
C1105
2
22U_0805_6.3V6M
AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V
Title
VGA power sequence and BACO
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
@
1 2
R656 0_0805_5%
C1105 Change to SE00000I10
20101228
Compal Electronics, Inc.
+VGA_CORE
1
25 51Friday, April 29, 2011
0.22
of
5
4
3
2
1
+3VS +3VS_ANX
D D
+1.2VS +1.2VS_ANX
+1.2VS_ANX
C C
+1.2VS_ANX
+3VS_ANX
40mil
1 2
R529 0_0805_5%
40mil
1 2
R527 0_0805_5%
L31
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
L30
12
2
C286
1
0.1U_0402_16V7K
12
2
C337
1
0.1U_0402_16V7K
20mil
L32
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V7K
12
2
C338
1
0.1U_0402_16V7K
2
C292
C289
1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C564
C336
1
0.01U_0402_16V7K
+DVDD33
1
C565
2
2.2U_0603_6.3V6K
0.1U_0402_16V7K
2
C296
1
0.01U_0402_16V7K
1
C562
2
2
C317
1
0.01U_0402_16V7K
+AVDD12
20mil
1
C349
2
2.2U_0603_6.3V6K
0.01U_0402_16V7K
1
C326
2
1
2
20mil
1
C327
2
2.2U_0603_6.3V6K
+DVDD12
1
2
+DVDD12
9
+AVDD12
DP0_AUXN_C8
DP0_AUXP_C8
LVDS_HPD10
DP0_TXN0_C8
DP0_TXP0_C8
DP0_TXN1_C8
DP0_TXP1_C8
PLT_RST#13,18,31,35
TL_ENVDD27
DP0_AUXN_C
DP0_AUXP_C
R1291 0_0402_5%
1 2
DP0_TXN0_C
DP0_TXP0_C
DP0_TXN1_C
DP0_TXP1_C
+3VS_ANX
+3VS_ANX
1 2
R399 10K_0402_5%
1 2
R404 1M_0402_5%
C223 0.1U_0402_16V7K
R403 10K_0402_5%
1 2
12
R400 12K_0402_1%
1 2
C225 100P_0402_50V8J
1 2
R402 10K_0402_5%
12
CLK_SEL
TL_ENVDD
T25
T31
T26
T38
T39
T50
T51
T52
R_BIAS
U3
1
AVDD12
60
DPRX_AUX_N
61
DPRX_AUX_P
58
DPPX_HPD
4
DPRX_LN0_N
3
DPRX_LN0_P
7
DPRX_LN1_N
6
DPRX_LN1_P
10
CLK_SEL
12
RESET_L
14
DIGON
34
POR
51
CFG_SCL
52
CFG_SDA
16
GPIO_0
17
GPIO_1
18
GPIO_2
64
R_BIAS
55
TDI
57
TMS
56
TCK
54
TDO
11
TEST_EN
65
PAD
+DVDD33
13
DVDD12
LVDS_CLKL_N
LVDS_CLKL_P
LVDS_CLKU_N
LVDS_CLKU_P
CPU_VARY_BL
AVSS
AVSS
AVSS
ANX3110_QFN64_9X9
2
5
62
53
AVDD33
DVDD33
DVDD33
AVDD33
AVDD33
AVDD33
AVDD33
LVDS_L0_N
LVDS_L0_P
LVDS_L1_N
LVDS_L1_P
LVDS_L2_N
LVDS_L2_P
LVDS_L3_N
LVDS_L3_P
LVDS_U0_N
LVDS_U0_P
LVDS_U1_N
LVDS_U1_P
LVDS_U2_N
LVDS_U2_P
LVDS_U3_N
LVDS_U3_P
DDC_CLK
DDC_DATA
BL_EN
VARY_BL
OSC_OUT
OSC_IN
8
25
33
39
63
26
27
19
20
21
22
23
24
28
29
42
43
35
36
37
38
40
41
44
45
49
50
15
47
48
31
30
+AVDD33
APU_TXOUT_CLKAPU_TXOUT_CLK+
APU_TXOUT0APU_TXOUT0+
APU_TXOUT1APU_TXOUT1+
APU_TXOUT2APU_TXOUT2+
APU_TZOUT_CLKAPU_TZOUT_CLK+
APU_TZOUT0APU_TZOUT0+
APU_TZOUT1APU_TZOUT1+
APU_TZOUT2APU_TZOUT2+
APU_LVDS_CLK
APU_LVDS_DAT
TL_BKOFF#
TL_INVT_PWM
APU_INVT_PWM
TRAVIS_CLKN
TRAVIS_CLKP
APU_TXOUT_CLK- 27
APU_TXOUT_CLK+ 27
APU_TXOUT0- 27
APU_TXOUT0+ 27
APU_TXOUT1- 27
APU_TXOUT1+ 27
APU_TXOUT2- 27
APU_TXOUT2+ 27
APU_TZOUT_CLK- 27
APU_TZOUT_CLK+ 27
APU_TZOUT0- 27
APU_TZOUT0+ 27
APU_TZOUT1- 27
APU_TZOUT1+ 27
APU_TZOUT2- 27
APU_TZOUT2+ 27
APU_LVDS_CLK 27
APU_LVDS_DAT 27
TL_BKOFF# 27,32
TL_INVT_PWM 27
APU_INVT_PWM 10,27
TRAVIS_CLKN 13
TRAVIS_CLKP 13
32
46
59
DVDD12
DVDD12
DVDD12
B B
+3VS_ANX
L33
FBMA-L11-201209-221LMA30T_0805
12
0.1U_0402_16V7K
C563
2
2
C348
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C567
C561
1
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C467
2
20mil
1
C566
2
2.2U_0603_6.3V6K
+AVDD33
1
2
DP0_AUXP_C
DP0_AUXN_C
@
12
R531 1M_0402_5%
@
12
R528 1M_0402_5%
+3VS_ANX
APU_LVDS_CLK
APU_LVDS_DAT
1 2
R530 4.7K_0402_5%
1 2
R469 4.7K_0402_5%
+3VS_ANX
Place via on each trace bus and let resistor very close the via
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/11/11 2011/11/11
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
LVDS Translator-ANX3110
PEQAE LA-7291P M/B
26 51Friday, April 29, 2011
1
0.22
of
5
C R T
D D
FCH_CRT_R15
FCH_CRT_G15
FCH_CRT_B15
FCH_CRT_HSYNC15
C C
FCH_CRT_R
FCH_CRT_G
FCH_CRT_B
Close to APU
R1634
1 2
R1635
1 2
R1636
1 2
12
R1641 0_0402_5%
12
R1651 0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
C1578
1 2
C1579
1 2
0.1U_0402_16V4Z
R1637
+CRT_VCC
0.1U_0402_16V4Z
5
A2Y
3
+CRT_VCC
5
A2Y
3
CRT_R_R
12
12
R1638
150_0402_1%
150_0402_1%
R1640
1 2
1
P
CRT_HSYNC_D
4
OE#
G
U87
74AHCT1G125GW_SOT353-5
R1648
1 2
1
P
CRT_VSYNC_D
4
OE#
G
U88
74AHCT1G125GW_SOT353-5
CRT_G_R
R1639
1K_0402_5%
1K_0402_5%
12
150_0402_1%
4
1
C1572
2
1 2
R1643 0_0603_5%
1 2
R1650 0_0603_5%
1
C1573
2
10P_0402_50V8J
1
C1583
2
L116 FCM2012CF-800T06_2P
1 2
L117 FCM2012CF-800T06_2P
1 2
L118 FCM2012CF-800T06_2P
1 2
1
C1574
2
10P_0402_50V8J
10P_0402_50V8J
HSYNC_L
VSYNC_L
C1584
1
2
15P_0402_50V8J
15P_0402_50V8J
For EMI
FCH_CRT_DDC_SDA15
FCH_CRT_DDC_SCL15FCH_CRT_VSYNC15
C1575
3
1
2
10P_0402_50V8J
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL
1
C1576
2
10P_0402_50V8J
R1647 0_0402_5%
R1649 0_0402_5%
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL
C1577
1 2
1 2
R17
R31
1
2
10P_0402_50V8J
CRT_DATA
@
1 2
@
1 2
CRT_CLK
RED
GREEN
BLUECRT_B_R
R1645
0_0402_5%
0_0402_5%
+CRT_VCC
VGA_DDC_CLK_C
12
12
R1644
2.2K_0402_5%
2.2K_0402_5%
5
4
Q2B
DMN66D0LDW-7_SOT363-6
VGA_DDC_DATA_C
VGA_DDC_CLK_C
For AMD DG-47520-1-10
BLUE
GREEN
RED
HSYNC_L
VSYNC_L
VGA_DDC_DATA_C
ESD
12
R1646
2
4.7K_0402_5%
61
Q2A DMN66D0LDW-7_SOT363-6
3
2
D1
2
3
YSDA0502C 3P C/A SOT-23
D2
2
3
YSDA0502C 3P C/A SOT-23
D15
2
3
YSDA0502C 3P C/A SOT-23
D16
2
3
YSDA0502C 3P C/A SOT-23
+CRT_VCC+3VS
12
R1642
4.7K_0402_5%
VGA_DDC_DATA_C
VGA_DDC_CLK_C
1
W=40mils
+5VS_CRTVCC
+CRT_VCC
VGA_DDC_DATA_C
VGA_DDC_CLK_C
1
2
100P_0402_50V8J
Q92
1
VIN
VOUT
GND
@
2
AP2230_SOT23-3
L115
SMD1812P075TF .75A 13.2V
C1570
CRTTEST
T19
3
W=40mils
21
1
2
0.1U_0402_16V4Z
JCRT1
6
11
1
7
12
2
8
16
G
13
17
G
3
9
14
4
10
15
5
SUYIN_070546FR015S297ZR
CONN@
+CRT_VCC
1
C1571
@
2
0.1U_0402_16V4Z
1
C1580
+5VS
1
2
C1581
100P_0402_50V8J
@
2 1
D4
RB491D_SOT23-3
RED
GREEN
HSYNC_L
BLUE
VSYNC_L
1
2
C1582
100P_0402_50V8J
@
1
1
1
+LCDVDD
+LCDVDD
1
1
C1588
C1587
B B
0.1U_0402_16V4Z
APU_ENVDD10
2
TL_ENVDD26
0.1U_0402_16V4Z
2
R1652
100_0805_5%
R712 0_0402_5%
1 2
R1659 0_0402_5%@
1 2
12
61
LCD POWER CIRCUIT
+5VALW
12
R1653
47K_0402_5%
2
2N7002DW-7-F_SOT363-6
Q99A
5
12
R1660
100K_0402_5%
3
Q99B
2N7002DW-7-F_SOT363-6
4
R1656
220K_0402_1%
C1585
4.7U_0805_10V4Z
0.047U_0402_16V7K
12
+LCDVDD
1
2
C1589
Q93
SI2301BDS-T1-E3_SOT23-3
1 3
D
W=60mils
+3VS
S
G
1
2
C1586
2
4.7U_0805_10V4Z
+3VS
C1590
@
1
2
0.1U_0402_16V4Z
L123
B+
FBMA-L11-201209-221LMA30T_0805
APU_TXOUT0+26
APU_TXOUT0-26
APU_TXOUT1-26
APU_TXOUT1+26
APU_TXOUT2+26
APU_TXOUT2-26
APU_TXOUT_CLK+26
APU_TXOUT_CLK-26
Panel PWM Control
Panel Backlight Control
@
D5 RB751V_SOD323
21
A A
TL_BKOFF#26,32
BKOFF#32
TL_BKOFF#
BKOFF#
5
R1672
@
1 2
@
D32 R B751V_SOD323
R1673
1 2
0_0402_5%
21
0_0402_5%
+3VS
@
12
R1670
10K_0402_5%
DISPOFF#
12
R1677
10K_0402_5%
TL_INVT_PWM26
APU_INVT_PWM10,26
EC_INVT_PWM32
4
TL_INVT_PWM
1 2
R722 0_0402_5%
R1654
@
1 2
R1655
@
1 2
0_0402_5%
0_0402_5%
INVTPWM
12
R1657
10K_0402_5%
12
C131
@
680P_0402_50V7K
W=80mils W=80mils
1 2
APU_TXOUT0+
APU_TXOUT0-
APU_TXOUT1-
APU_TXOUT1+
APU_TXOUT2+
APU_TXOUT2-
APU_TXOUT_CLK+
APU_TXOUT_CLK-
INVTPWM
DISPOFF#
JLVDS1
GMD41GND
393940
373738
353536
333334
313132
292930
272728
252526
232324
212122
19
19
171718
15
15
131314
111112
9910
778
556
334
112
ACES_87242-4001-09
CONN@
42
40
38
36
34
32
APU_TZOUT0+
30
APU_TZOUT0-
28
26
APU_TZOUT1-
24
APU_TZOUT1+
22
20
20
16
APU_TZOUT2+
18
APU_TZOUT2-
16
14
APU_TZOUT_CLK-
12
APU_TZOUT_CLK+
10
8
APU_LVDS_CLK
6
APU_LVDS_DAT
4
2
USB20_N214
USB20_P214
DMIC_CLK33
DMIC_DATA33
+LCDVDD
APU_TZOUT0+ 26
APU_TZOUT0- 26
APU_TZOUT1- 26
APU_TZOUT1+ 26
APU_TZOUT2+ 26
APU_TZOUT2- 26
APU_TZOUT_CLK- 26
APU_TZOUT_CLK+ 26
APU_LVDS_CLK 26
APU_LVDS_DAT 26
+5VS
ESD
Security Classification
Issued Date
THIS SHEET OF ENGINEERIN G DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/06/30 2012/06/30
Compal Secret Dat a
Deciphered Date
2
USB20_N2
USB20_P2
DMIC_CLK
DMIC_DATA
D28
6
I/O4
5
VDD
GND
4
I/O3
AZC099-04S.R7G_SOT23-6
@
DMIC_CLK
@
2
C132
1
22P_0402_50V8J
EMI
Camera
JCM1
+3VS
3
I/O2
2
1
I/O1
Title
Size Document Number Rev
C
Date: Sheet
1
1
2
2
3
3
4
4
5
7
5
G1
6
8
6
G2
ACES_87213-0600G
CONN@
Compal Electronics, Inc.
P10-LVDS/CRT CONN
QBL70 LA-7553P
1
27 51Friday, April 29, 2011
of
0.22
5
4
3
2
1
+VSB
12
13
D
S
+5VS
@
C1591
470K_0402_5%
Q96
SSM3K7002FU_SC70-3
+1.5VS +1.5VS
4.7K_0402_5%
4.7K_0402_5%
12
12
R205
R202
D D
APU_HDMI_CLK8
APU_HDMI_DATA8
1 2
R203 0_0402_5%
1 2
R206 0_0402_5%
HDMICLK HDMI_SCLK
HDMIDAT
G
2
S
Q36
G
2
BSH111 1N_SOT23-3
13
D
S
Q33
BSH111 1N_SOT23-3
13
D
HDMI_SDATA
+HDMI_5V_OUT
3.9K_0402_1%
3.9K_0402_1%
12
12
R201
R200
R200, R201 place near JHDMI connect
+5VS +HDMI_5V _OUT
Q94
1
VIN
@
VOUT
GND
2
AP2230_SOT23-3
3
R1678
SUSP38,45
2
G
1
2
EN_HDMI
1U_0603_10V6K
R1679
Q95
D
S
6
4 5
2
1
W=40mils
G
3
SI3456BDV-T1-E3 1N TS OP6
12
1.5M_0402_5%
+HDMI_5V
C1601
0.5A 15VDC_FUSE
1
2
0.1U_0402_16V7K
21
+HDMI_5V_OUT
C1592
1
2
1U_0603_10V4Z
F2
5V PULL UP IN CONNECTOR SIDE
+HDMI_5V_OUT
HDMI_HPD
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JHDMI1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
SUYIN_100042GR019M23DZL
CONN@
GND
GND
GND
GND
12
R768
100K_0402_5%
20
21
22
23
HDMI_HPD
HDMI_SDATA
GND
HDMI_SCLK
HDMI_R_CLK#
HDMI_R_CLK
HDMI_R_TX0#
HDMI_R_TX0
HDMI_R_TX1#
HDMI_R_TX1
HDMI_R_TX2#
HDMI_R_TX2
HDMI_SDATA
3
I/O2
2
HDMI_SCLK
1
I/O1
+1.5VS
R755
2.2K_0402_5%
1 2
13
D
2
G
S
Q35
SSM3K7002FU_SC70-3
C C
From APU
B B
A A
Near the connector
PCIE_FTX_GRX_P156
PCIE_FTX_GRX_N156
PCIE_FTX_GRX_P146
PCIE_FTX_GRX_N146
PCIE_FTX_GRX_P136
PCIE_FTX_GRX_N136
PCIE_FTX_GRX_P126
PCIE_FTX_GRX_N126
ESD
C1602 0.1U_0402_16V7K
1 2
C1603 0.1U_0402_16V7K
1 2
C1604 0.1U_0402_16V7K
1 2
C1605 0.1U_0402_16V7K
1 2
C1606 0.1U_0402_16V7K
1 2
C1607 0.1U_0402_16V7K
1 2
C1608 0.1U_0402_16V7K
1 2
C1609 0.1U_0402_16V7K
1 2
HDMI_TX0# HDMI_TX0#
HDMI_TX0 HDMI_TX0
HDMI_CLK#
D3
1
2
4
5
3
8
L15ESDL5V0NA-4 SLP2510P 8
9
8
HDMI_CLK#
7
HDMI_CLKHDMI_CLK
6
HDMI_CLK
HDMI_CLK#
HDMI_TX0
HDMI_TX0#
HDMI_TX1
HDMI_TX1#
HDMI_TX2
HDMI_TX2#
HDMI_CLK
HDMI_CLK#
HDMI_TX0
HDMI_TX0#
HDMI_TX1
HDMI_TX1#
HDMI_TX2
HDMI_TX2#
R1690 604_0402_1%
1 2
R1691 604_0402_1%
1 2
R1693 604_0402_1%
1 2
R1695 604_0402_1%
1 2
R1696 604_0402_1%
1 2
R1697 604_0402_1%
1 2
R1698 604_0402_1%
1 2
R1699 604_0402_1%
1 2
+HDMI_5V_OUT
NEAR CONNECTOR
HDMI_TX1#
HDMI_TX1
HDMI_TX2#
HDMI_TX2
D6
1
2
4
5
3
8
L15ESDL5V0NA-4 SLP2510P 8
12
R1700
100K_0402_5%
9
8
7
6
2
G
HDMI_TX1#
HDMI_TX1
HDMI_TX2#
HDMI_TX2
@
1 2
R208 0_0402_5%
L11
4
HDMI_CLK#
13
D
Q97SSM3K7002FU_SC70-3
S
HDMI_TX0#
HDMI_TX0
HDMI_TX1#
HDMI_TX1
HDMI_TX2# HDMI_R_TX2#
HDMI_TX2
BOT SIDE NEAR CONNECTOR
1
WCM-2012-670T_4P
R210 0_0402_5%@
R211 0_0402_5%
L12
1
4
WCM-2012-670T_4P
R213 0_0402_5%@
R214 0_0402_5%
L13
1
4
WCM-2012-670T_4P
R220 0_0402_5%
1 2
R223 0_0402_5%
L14
1
1
4
4
WCM-2012-670T_4P
1 2
R226 0_0402_5%
4
1
1 2
@
1 2
1
4
1 2
@
1 2
1
4
@
1 2
@
@
3
2
2
3
2
3
2
2
3
3
HDMI_R_CLKHDMI_CLK
3
HDMI_R_CLK#
2
HDMI_R_TX0#
2
HDMI_R_TX0
3
HDMI_R_TX1#
2
HDMI_R_TX1
3
HDMI_R_TX2
HDMI_HPD
+5VS
+HDMI_5V_OUT
ESD
APU_HDMI_HPD10
D7
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/06/30 2012/06/30
Compal Secret Data
Deciphered Date
2
Title
Size Doc ument Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
P11-HDMI CONN
QBL70 LA-7553P
1
28 51Friday, April 29, 2011
of
0.22
A
B
C
D
E
F
G
H
SATA HDD BTB Conn.
JHDD1
1 1
2 2
SATA_STX_DRX_P015
SATA_STX_DRX_N015
SATA_DTX_C_SRX_N015
SATA_DTX_C_SRX_P015
SATA_STX_DRX_P215
SATA_STX_DRX_N215
SATA_DTX_C_SRX_N215
SATA_DTX_C_SRX_P215
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
GND31GND32GND33GND34GND35GND
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
ACES_88018-304G
36
CONN@
+5VS
+3VS
SATA ODD FFC Conn.
JODD1
1
C1310 0.01U_0402_16V7K
SATA_STX_DRX_P115
SATA_STX_DRX_N115
SATA_DTX_C_SRX_N115
SATA_DTX_C_SRX_P115
1 2
C1311 0.01U_0402_16V7K
1 2
C1308 0.01U_0402_16V7K
1 2
C1309 0.01U_0402_16V7K
1 2
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
80mils
+5VS
+3VS
1 2
R4 10K _0402_5%
@
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
DP
9
+5V
10
+5V
11
MD
12
GND
13
GND
SANTA_206001-1
CONN@
GND1
GND2
14
15
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2010/08/20 2012/06/30
E
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
F
Date: Sheet
Compal Electronics, Inc.
P28-HDD & ODD CONN
QBL70 LA-7553P
G
29 51Friday, April 29, 2011
H
0.22
of
5
+5VALW
OUT
OUT
OUT
OC#
OUT
OUT
OUT
OC#
+USB_VCCA
0_0402_5%
8
7
6
5
+USB_VCCB
8
7
6
5
1
2
1
2
C710
C715
1000P_0402_50V7K@
1000P_0402_50V7K@
1 2
1 2
U54
1
GND
2
C707 0.1U_0402_16V4Z
12
USBAI_PEN#32
D D
C708 0.1U_0402_16V4Z
12
USB_ON#32,33
USBAI_PEN#
+5VALW
USB_ON#
IN
3
IN
4
EN#
AP2301MPG-13 MSOP 8P
Low Active
U55
1
GND
2
IN
3
IN
4
EN#
AP2301MPG-13 MSOP 8P
Low Active
R109
R1110_0402_5%
4
USB_OC0# 14
USB_OC2# 14
USB20_N0_C
+5VALW
USB20_P0_C
USB20_N0_CON
USB20_P0_CON
ESD
6
5
4
R652 0_0402_5%
@
L60
1
1
4
4
WCM-2012HS-900T
R631 0_0402_5%@
EMI request
D14
I/O4
VDD
I/O3
AZC099-04S.R7G_SOT23-6
GND
3
I/O2
2
1
I/O1
12
2
3
12
USB20_N10_C
USB20_P10_C
3
USB20_N0_C
2
USB20_P0_C
3
470P_0402_50V7K
2
Left USB Conn.
+USB_VCCA
1
C711
1
C712
47U_0805_6.3V
2
2
W=80mils
USB20_N0_C
USB20_P0_C
1
OCTEK_USB-04APEB
CONN@
JUSB1
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
AI CHARGER
R949 0_0402_5%
USB20_N014
12
USB20_P014
R1016
100K_0402_5%
0.1U_0402_16V7K~N
1 2
USB20_N0 USB20_N0_CON
USB20_P0
+5VALW
2
C1669
1
8
7
6
5
MAX14566EETA+_TDFN-EP8_2X2~D
CEN
CB
TDM
TDP
GND
VCC
GND
Auto detection charger identification active
CB=0
DM
DP
U2
CEN#
1
2
USB20_P0_CON
3
4
9
@
R33 0_0402_5%
1 2
AI_CEN# 32USBAI_EN32
Connect DP/DM to TDP/TDMCB=1
C C
R655 0_0402_5%
12
@
USB REDRIVER
+3VS
@
R227 4.7K_0402_5%
USB30_MRX_DTX_P014
USB30_MRX_DTX_N014
USB30_MTX_C_DRX_P014
USB30_MTX_C_DRX_N014
B B
EQ1
EQ2
DE1
DE2
OS1
A A
OS2
USB30_MRX_DTX_P0
USB30_MRX_DTX_N0
USB30_MTX_C_DRX_P0
USB30_MTX_C_DRX_N0
5
C21 0.1U_0402_16V7KM3@
C22 0.1U_0402_16V7KM3@
+3VS
4.7K_0402_5%
12
R204
@
4.7K_0402_5%
12
R218
@
1 2
12
12
4.7K_0402_5%
12
R207
@
4.7K_0402_5%
12
R219
@
TEST
I2C_EN
4.7K_0402_5%
12
R212
@
4.7K_0402_5%
12
R221
@
USB30_MRX_P0
USB30_MRX_N0
4.7K_0402_5%
@
4.7K_0402_5%
@
U56
1
13
EQ1
2
DE1
3
OS1
4
5
12
11
9
8
7
24
6
10
SN65LVPE502RGER_QFN24_4X4
M3@
4.7K_0402_5%
12
12
R216
R215
@
4.7K_0402_5%
12
12
R222
R224
@
VCC
VCC
EQ1
DE1
OS1
EN_RXD
TX2+
TX2RX1+
RX1-
NC
NC
GND
GND
4.7K_0402_5%
@
4.7K_0402_5%
@
EQ2
DE2
OS2
RX2+
RX2-
TX1+
TX1-
CM
GND
GND
GPAD
4.7K_0402_5%
12
12
R217
R1818
@
4.7K_0402_5%
12
12
R1820
R225
@
4
DE2
16
OS2
15
U3RXDP_A_R
19
U3RXDN_A_R
20
U3TXDP_A_C U3TXDP_A
22
U3TXDN_A_C
23
R228 4.7K_0402_5%
1 2
14
@
18
21
25
4.7K_0402_5%
12
R1819
@
TEST
I2C_EN
4.7K_0402_5%
12
R1821
@
C3 0.1U_0402_16V7KM3@
C4 0.1U_0402_16V7KM3@
C19 0.1U_0402_16V7KM3@
C20 0.1U_0402_16V7KM3@
EQ2
17
USB20_N1014
USB20_P1014
12
12
12
12
+3VS
must to close to JUSB2
USB20_N10
USB20_P10
U3RXDP_A_R_C
U3RXDN_A_R_C
U3TXDN_A
U3RXDP_A_R_C
U3RXDN_A_R_C
U3TXDP_A
U3TXDN_A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
L55
1
1
2
4
WCM-2012HS-900T
@
1 2
R933 0_0402_5%
WCM-2012-900T_0805
1
1
4
4
L56
M3@
@
1 2
R931 0_0402_5%
@
1 2
R939 0_0402_5%
WCM-2012-900T_0805
1
1
4
4
L58
M3@
@
1 2
R946 0_0402_5%
3
4
R654 0_0402_5%
12
@
2
2
3
3
2
2
3
3
2010/08/20 2012/06/30
USB20_N10_C
2
USB20_P10_C
3
U3RXDP_A_R_0
U3RXDN_A_R_0
U3TXDP_A_R
U3TXDN_A_R
Compal Secret Data
Deciphered Date
+USB_VCCB
C714
470P_0402_50V7K
2
W=80mils
1
1
C713
47U_0805_6.3V
2
2
For USB3.0 ESD diode
U3TXDP_A_R
U3TXDN_A_R
U3RXDP_A_R_0
U3RXDN_A_R_0
JUSB2
1
USB20_N10_C
USB20_P10_C
U3RXDN_A_R_0
U3RXDP_A_R_0
U3TXDN_A_R
U3TXDP_A_R
D41
1
2
4
5
3
8
YSCLAMP0524P_SLP2510P8-10-9
M3@
Title
Size Document Number Rev
Custom
Date: Sheet
9
8
7
6
Compal Electronics, Inc.
QBL70 LA-7553P
VBUS
2
D-
3
D+
4
GND
5
6
7
8
9
OCTEK_USB-09EAEB
CONN@
U3TXDP_A_R
U3TXDN_A_R
U3RXDP_A_R_0
U3RXDN_A_R_0
SSRXSSRX+
GND
SSTXSSTX+
GND
GND
GND
GND
10
11
12
13
P31-USB/BT/USBsub
1
30 51Friday, April 29, 2011
of
0.22
5
J8
2
W=60mils
+3VALW
1
C1610
1U_0402_6.3V6K
D D
EN_WOL32
R1789
10K_0402_5%
PCIE_DTX_C_FRX_P06
PCIE_DTX_C_FRX_N06
PCIE_FTX_C_DRX_P06
PCIE_FTX_C_DRX_N06
C C
R540
1 2
+3VS
1K_0402_5%
15K_0402_5%
B B
C1635
1 2
0.01U_0402_16V7K
A A
+5VALW
2
G
1 2
C1629 0.1U_0402_16V7K
C1630 0.1U_0402_16V7K
LAN_CLKREQ#14
PLT_RST#13,18,26,35
CLK_PCIE_LAN13
CLK_PCIE_LAN#13
R541
1 2
+LAN_IO
3.3V : Enable switching regulator
0V : Disable switching regulator
+V_DAC
LAN_MDIP0
LAN_MDIN0
+V_DAC
LAN_MDIP1
LAN_MDIN1
+V_DAC
LAN_MDIP2
LAN_MDIN2
+V_DAC
LAN_MDIP3
LAN_MDIN3
5
2
R533
100K_0402_5%
R534
1 2
1 2
220K_0402_5%~N
13
D
Q30
SSM3K7002FU_SC70-3
S
1 2
1 2
ISOLATEB
+LAN_IO
R544 0_0402_5%
R34 0_0603_5%
R76 0_0603_5%
12
R547 2.49K_0402_1%
TS1
1
TCT1
MCT1
2
TD1+
MX1+
3
TD1-
4
TCT2
MCT2
5
TD2+
MX2+
TD2-6MX2-
7
TCT3
MCT3
8
TD3+
MX3+
9
TD3-
10
TCT4
MCT4
11
TD4+
MX4+
12
TD4-
TAIMAG_IH-160
12
@
12
@
MX1-
MX3-
MX4-
112
JUMP_43X118@
Q29
D
S
13
G
AO3419L 1P SOT23-3
2
EN_WOL#
1
C1624
0.1U_0603_25V7K
2
PCIE_FRX_C_DTX_P0
PCIE_FRX_C_DTX_N0
XTLO
XTLI
LAN_WAKE#
R542 10K_0402_5%
1 2
R543 1K_0402_5%
1 2
+LAN_VDDREG
1 2
24
RJ45_TX0+
23
RJ45_TX0-
22
21
RJ45_RX1+
20
RJ45_RX1-
19
18
RJ45_TX2+
17
RJ45_TX2-
16
15
RJ45_TX3+
14
RJ45_TX3-
13
LANGAN
LANGAN
4
W=60mils
+LAN_IO
C1611
1.5A
1
C1612
2
0.1U_0402_16V7K
1
C1613
2
0.1U_0402_16V7K
1
C1614
2
0.1U_0402_16V7K
These caps close to Pin 12,27,39,42, 47,48
FCH_PCIE_WAKE#14,32,35
U49
22
HSOP
23
HSON
17
HSIP
18
HSIN
16
CLKREQB
25
PERSTB
19
REFCLK_P
20
REFCLK_N
43
CKXTAL1
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
14
NC/SMBCLK
15
NC/SMBDATA
38
GPO/SMBALERT
33
ENSWREG
34
VDDREG
35
VDDREG
46
RSET
24
GND
49
PGND
RTL8111E-VL-GR_QFN48_6X6
D18 LSE-200NX3216TRLF_1206-2@
D19 LSE-200NX3216TRLF_1206-2@
D29 LSE-200NX3216TRLF_1206-2@
D31 LSE-200NX3216TRLF_1206-2@
R549 75_0402_5%
R1529 75_0402_5%
R1530 75_0402_5%
R552 75_0402_5%
1 2
1 2
1 2
1 2
LED3/EEDO
LED1/EESK
LED0
EECS/SCL
EEDI/SDA
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
DVDD10
DVDD10
DVDD10
DVDD33
DVDD33
AVDD33
AVDD33
AVDD33
AVDD33
EVDD10
AVDD10
AVDD10
AVDD10
AVDD10
REGOUT
1 2
1 2
1 2
1 2
31
37
40
R537 10K_0402_5%
30
1 2
R538 10K_0402_5%
1 2
32
LAN_MDIP0
1
LAN_MDIN0
2
LAN_MDIP1
4
LAN_MDIN1
5
LAN_MDIP2
7
LAN_MDIN2
8
LAN_MDIP3
10
LAN_MDIN3
11
13
29
41
27
39
12
42
47
48
+LAN_EVDD10
21
3
6
9
45
+LAN_SROUT1.05
36
ESD
4
1
2
0.1U_0402_16V7K
1
C1615
2
+LAN_IO
1 3
+LAN_VDD
+LAN_IO
+LAN_VDD
2
C1636
100P_1206_2KV7K
1
04/19
1
C1616
2
0.1U_0402_16V7K
R1658
10K_0402_5%
2
G
1 2
D
LAN_WAKE#
S
SSM3K7002FU_SC70-3
Q98
3
+LAN_IO
R1788
0.1U_0402_16V7K
470_0603_5%
1 2
+LAN_IO_DISC
13
D
G
SSM3K7002FU_SC70-3
S
Q113
+LAN_IO
+LAN_SROUT1.05
RJ45_TX2+ RJ45_TX2-
RJ45_TX3+
W=20mils
EN_WOL#
2
R535
1 2
2.2UH +-5% NLC252018T-2R2J-N
D34 LSE-200NX3216TRLF_1206-2@
D35 LSE-200NX3216TRLF_1206-2@
D36 LSE-200NX3216TRLF_1206-2@
D37 LSE-200NX3216TRLF_1206-2@
+LAN_VDDREG
0_0603_5%
W=60mils W=60mils
C1625
1 2
1 2
1 2
1 2
1
2
4.7U_0603_6.3V6K
L120
1 2
These components close to Pin 36
( Should be place within 200 mils )
RJ45_TX0-RJ45_TX0+
RJ45_RX1-RJ45_RX1+
RJ45_TX3-
W=40mils W=20mils
C1626
1
2
C1631
2
+LAN_VDD
1
1
C1618
C1617
2
C1619
2
0.1U_0402_16V7K
0.1U_0402_16V7K
These caps close to Pin 3,6,9,13, 29,41,45
0.1U_0402_16V7K
1
C1632
2
0.1U_0402_16V7K
+LAN_VDD
+LAN_VDD
1
2
4.7U_0603_6.3V6K
ESD
LAN_MDIP1
+LAN_IO +LAN_IO
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
D11
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
2010/3/31 2012/06/30
3
I/O2
2
GND
1
I/O1
Compal Secret Data
Deciphered Date
LAN_MDIP0
LAN_MDIN0LAN_MDIN1
ESD
2
LAN_MDIP3
LAN_MDIN3
1
1
C1620
2
0.1U_0402_16V7K
R536
1 2
0_0603_5%
RJ45_TX3-
RJ45_TX3+
RJ45_RX1-
RJ45_TX2-
RJ45_TX2+
RJ45_RX1+
RJ45_TX0-
RJ45_TX0+
D13
6
I/O4
5
VDD
4
I/O3
AZC099-04S.R7G_SOT23-6
Title
Size Document Number Rev
Custom
Date: Sheet
1
1
C1621
C1622
2
2
I/O2
GND
I/O1
0.1U_0402_16V7K
8
7
6
5
4
3
2
1
3
2
1
0.1U_0402_16V7K
+LAN_EVDD10
C1627
1 2
1 2
JLAN1
PR4-
PR4+
PR2-
PR3-
PR3+
PR2+
PR1-
PR1+
SANTA_130451-Y
CONN@
LAN_MDIP2
LAN_MDIN2
Compal Electronics, Inc.
P24-LAN RTL8111E
QBL70 LA-7553P
1
1
C1623
2
2
0.1U_0402_16V7K
1
1
C1628
2
C163312P_0402_50V8J
C163412P_0402_50V8J
2
1U_0402_6.3V6K
0.1U_0402_16V7K
R539
0_0402_5%
Y6
25MHZ_12PF_X5H025000FC1H-H
1 2
12
SHLD4
11
SHLD3
10
SHLD2
9
SHLD1
1
0.1U_0402_16V7K
XTLI
12
XTLO
31 51Friday, April 29, 2011
0.22
of
5
0.1U_0402_16V4Z
C1346
1
1
C1345
2
2
12
KSO[0..15]
KSI[0..7]
100K_0402_5%
0.1U_0402_16V4Z
EC_INVT_PWM27
EC_TX_P80_DATA35
EC_RX_P80_CLK35
R1037
EC_GA2014
EC_KBRST#14
SERIRQ13
LPC_FRAME#13,35
LPC_AD313,35
LPC_AD213,35
LPC_AD113,35
LPC_AD013,35
A_RST#13
EC_SCI#14
KSO[0..15] 37
KSI[0..7] 3 7
USBAI_EN30
USBAI_PEN#30
EC_SMB_CK140
EC_SMB_DA140
EC_SMB_CK26,19
EC_SMB_DA26,19
SLP_S3#14
SLP_S5#14 EC_LID_OUT# 14
EC_SMI#14
FAN_SPEED136
ON/OFF36
NUM_LED#35
1 2
R1036 0_0402_5%
12
2
C1358
22P_0402_50V8J
1
1 2
R1618 0_0402_5%
+3VS
D D
C C
B B
A A
1 2
R1623 10K_0402_5%
R1661 100K_0402_5%
@
+3VALW
+3VALW
+3VALW
15P_0402_50V8J
R1020 2.2K_0402_5%@
+3VS
R1021 2.2K_0402_5%
R1022 2.2K_0402_5%
R1023 2.2K_0402_5%@
1 2
R1027 2.2K_0402_5%
1 2
R1028 2.2K_0402_5%
1 2
R1029 47K_0402_5%
1 2
R1030 47K_0402_5%
@
1 2
R1032 10K_0402_5%
1 2
R1616 10K_0402_5%
1 2
R1619 10K_0402_5%
EC_CRY1 EC_CRY2
2
@
C1361
1
12
+3VALW
1 2
1 2
1 2
1 2
EC_SCI#
ENBKL
C1352
@
22P_0402_50V8J
12
R1014 33_0402_5%
LPC_CLK0_EC13,16
EC_SMB_CK1
EC_SMB_DA1
EC_MUTE#
1
OSC4OSC
NC3NC
2
5
12
R1011 47K_0402_5%
12
C1353 0.1U_0402_16V4Z
EC_SMB_CK2
EC_SMB_DA2
KSO1
KSO2
EC_PME#
USB_ON#
2
@
@
C1362
15P_0402_50V8J
X2
1
32.768KHZ_12.5PF_Q13MC14610002
@
RTC_CLK13,16
FCH_PCIE_WAKE#14,31,35
4
0.1U_0402_16V4Z
1
C1347
2
0.1U_0402_16V4Z
LPC_CLK0_EC
A_RST#
EC_SCI#
USBAI_EN
USBAI_PEN#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
SLP_S3#
SLP_S5#
EC_SMI#
EC_INVT_PWM
FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF
NUM_LED#
EC_CRY1
EC_CRY2
@
4
1
C1348
2
EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
2
C1349
1000P_0402_50V7K
1
U31
1
GA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ#
4
LFRAME#
5
LAD3
7
LAD2
8
LAD1
10
LPC & MISC
LAD0
12
PCICLK
13
PCIRST#/GPIO05
37
ECRST#
20
SCI#/GPIO0E
38
CLKRUN#/GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44
KSO5/GPIO25
45
KSO6/GPIO26
46
KSO7/GPIO27
47
KSO8/GPIO28
48
KSO9/GPIO29
49
KSO10/GPIO2A
50
KSO11/GPIO2B
51
KSO12/GPIO2C
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
81
KSO16/GPIO48
82
KSO17/GPIO49
77
SCL1/GPIO44
78
SDA1/GPIO45
79
SCL2/GPIO46
80
SDA2/GPIO47
6
PM_SLP_S3#/GPIO04
14
PM_SLP_S5#/GPIO07
15
EC_SMI#/GPIO08
16
LID_SW#/GPIO0A
17
SUSP#/GPIO0B
18
PBTN_OUT#/GPIO0C
19
EC_PME#/GPIO0D
25
EC_THERM#/GPIO11
28
FAN_SPEED1/FANFB1/GPIO1 4
29
FANFB2/GPIO15
30
EC_TX/GPIO16
31
EC_RX/GPIO17
32
ON_OFF/GPIO18
34
PWR_LED#/GPI O19
36
NUMLED#/GPIO1A
122
XCLK1
123
XCLK0
EC_PME#
3
+3VALW
L65
1 2
2
1
BLM18AG601SN1D_2P
C1350
1000P_0402_50V7K
9
22
VCC
PS2 Interface
Int. K/B
Matrix
SM Bus
11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+EC_VCCA
33
96
111
125
67
VCC
VCC
VCC
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPI O10
ACOFF/FANPWM2/GPIO 13
PWM Output
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
AD Input
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
DA Output
EN_DFAN1/DA1/GPIO3 D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SPI Device Interface
SPI Flash ROM
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPI O52
GPIO
BATT_LOW_LED#/GPIO54
VR_ON/XCLK32K/GPIO57
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
ICH_PWROK/G PXO06
GPO
GPIO
PM_SLP_S4#/GPXID1
GPI
GND
GND
GND
AGND
GND
GND
35
94
113
KB930QF A1 LQFP 128P
69
20mil
ECAGND
24
1
C1351
2
0.1U_0402_16V4Z
ECAGND
21
23
SPIDI/RD#
SPICS#
GPXO10
GPXO11
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R
L114
1 2
26
ACOFF
27
BATT_TEMP
63
64
ADP_I
65
BRDID
66
75
76
68
70
71
72
83
84
85
86
87
88
97
98
99
109
119
120
126
128
73
74
89
90
91
92
93
95
121
127
100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118
124
1 2
R30 0_0402_5%
EN_DFAN1
IREF
CHGVADJ
EC_MUTE#
USB_ON#
WLAN_LED#
BT_LED#
TP_CLK
TP_DATA
VGATE
EN_WOL
VLDT_EN
LID_SW#
SPI_SO_R
SPI_SI_R
SPI_CS#
AI_CEN#
PX_EN
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
PWR_LED#
SYSON
VR_ON
ACIN
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_PME#
FCH_PWRGD
BKOFF#
WL_OFF#_EC
PE_GPIO1
ENBKL_R
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
TL_BKOFF#_R
Compal Secret Data
ENBKL
EMI
L125
1 2
@
1 2
R32 0_0402_5%
1
C1359
4.7U_0603_6.3V6K
2
Deciphered Date
ACOFF 39
ADP_I 39
EN_DFAN1 36
IREF 39
CHGVADJ 39
EC_MUTE# 33
USB_ON# 30,33
WLAN_LED# 35
BT_LED# 35
TP_CLK 37
TP_DATA 37
VGATE 47
EN_WOL 31
VLDT_EN 38,46
LID_SW# 37
SPI_CLK
FBMA-10-100505-101T
AI_CEN# 30
PX_EN 22,25
FSTCHG 39
CHARGE_LED0# 35
CAPS_LED# 35
CHARGE_LED1# 35
PWR_LED# 35,36
SYSON 38,43
VR_ON 47
ACIN 39
EC_RSMRST# 14
EC_ON 36
FCH_PWRGD 14
BKOFF# 27
WL_OFF#_EC 35
RF_LED# 35
VGA_ON 25
PE_GPIO1 13,25
EAPD 33
EC_THERM# 8,13,47
SUSP# 35,38
PBTN_OUT# 14
FANPWM1/GPIO12
ADP_I/AD2/GPIO 3A
AD3/GPIO3B
AD4/GPIO42
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPIDO/WR#
SPICLK/GPIO58
CIR_RX/GPIO40
CIR_RLC_TX/GPIO 41
CAPS_LED#/GPIO53
SUSP_LED#/GPIO55
SYSON/GPIO56
AC_IN/GPIO59
EC_ON/GPXO05
EC_SWI#/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
ENBKL/GPXID2
FBM-11-160808-601-T_0603
2010/08/04 2010/08/04
3
2
VGA_DBCLK
EC must program to 500KHZ output
Start and stop follow SUP high/Low
1 2
C2 100P_0402_50V8J
ENBKL 10
SPI_CS#
2
ECAGND
BATT_TEMP 40
Delay EC_PWROK 50ms
for VGA criterial
+3VALW
1
C1539
0.1U_0402_16V4Z
2
1 2
R1630 15_0402_5%
1
ID BRD ID Ra Rb Vab
0
1
2
R01 SR
R02 ER
R10 PR
BRDID
100K
100K
100K
Ra
R1603 100K_0402_5%
1 2
R1606 215K_0402_1%
1 2
115K
154K
215K
1.6613V
1.8857V
2.1261V
+3VALW
Rb
+5VS
TL_BKOFF#_R
R1620 0_0402_5%
TP_CLK
TP_DATA
ACIN
FCH_PWRGD
1 2
C1363 100P_0402_50V8J
12
R10184.7K_0402_5%
12
R10194.7K_0402_5%
12
@
1 2
R1625 10K_0402_5%
TL_BKOFF# 26,27
SPI_CLK_R
12
R180
@
33_0402_5%
1
@
C1535
22P_0402_50V8J
2
+3VS
EMI
20mils
U48
1
CS#
2
SO
3
WP#
4
GND
MX25L1606EM2I-12G SOP 8P
SA000041N00
Title
Size Document Number Rev
B
QBL70 LA-7553P
Date: Sheet
8
VCC
7
HOLD#
6
SCLK
5
SI
Compal Electronics, Inc.
EC ENE KB930
12
R1629
10K_0402_5%
SPI_HOLD#SPI_SO_R SPI_SO
1 2
15_0402_5%
SPI_SI
1 2
15_0402_5%
1
R1631
R1632
SPI_CLKSPI_CLK_R
SPI_SI_R
of
32 51Friday, April 29, 2011
0.22
A
B
C
D
E
F
G
H
1 2
1 2
1 2
1 2
12
R1538
@
1
C1492
2
@
1 2
C9 0.1U_0402_16V7K
1 2
C123 0.1U_0402_16V7K
1 2
C124 0.1U_0402_16V7K
1 2
C125 0.1U_0402_16V7K
0_0402_5%
22P_0402_50V8J
MIC2
MIC1
@
@
@
@
SPK_L1
SPK_L2
SPK_R1
SPK_R2
C1474 1U_0603_10V6K@
C1483 1U_0603_10V6K@
R1541 2.2K_0402_1%
1 2
R1542 2.2K_0402_1%
1 2
USB20_N114
USB20_P114
1 2
C1473 0.22U_0603_16V7K
1
@
2
1 2
C1478 0.22U_0603_16V7K
@
1 2
C1480 0.22U_0603_16V7K
1
@
2
1 2
C1484 0.22U_0603_16V7K
@
ESD
+MIC1_VREFO_R
+MIC1_VREFO_L
USB_ON#30,32
USB_OC1#14
USB20_P1114
USB20_N1114
+5VALW
USB_ON#
SPK_R1
SPK_R2
SPK_L1
SPK_L2
2
3
1
YSDA0502C 3P C/A SOT-23
@
MIC_JD
HP_JD
HP_OUTR
HP_OUTL
10
11
12
13
14
15
16
17
18
19
20
21
USB20_P11
USB20_N11
22
23
24
25
26
3
D9
@
JAU1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
ACES_85202-24051
CONN@
JSPK1
1
1
2
2
3
3
G1
4
4
G2
ACES_88266-04001
CONN@
2
D10
1
YSDA0502C 3P C/A SOT-23
5
6
SPKOUT_L1
SPKOUT_L2
SPKOUT_R1
SPKOUT_R2
+5VS
HDA_SDOUT_AUDIO
EMI
HDA_SYNC_AUDIO
1
C1501
2
0.1U_0402_16V7K
close to JSPK1
10U_0805_10V6K
R1532 0_0603_5%
R1533 0_0603_5%
R1535 0_0603_5%
R1536 0_0603_5%
HDA_BITCLK_AUDIO
2
C1491
1
@
10P_0402_50V8J
2
C1494
1
@
10P_0402_50V8J
For EMI (on MIC and Headphone AGND to connected with
DGND)
EMI
0.1U_0402_16V7K
L108
12
HDA_SYNC_AUDIO 14
HDA_BITCLK_AUDIO 14
HDA_SDOUT_AUDIO 14
HDA_SDIN0 14
EAPD 32
1
1
C1500
2
2
@
10U_0805_10V6K
1
2
1
2
R1546
33_0402_5%
R1547
0_0402_5%
+MIC1_VREFO_R
R1552
+5VS_PVDD
C1477
0.1U_0402_16V7K
MBK1608800YZF 0603
10U_0805_10V6K
C1499
1
2
R1531
C1485
38
U50
AVDD125AVDD2
12
0_0805_5%
C1475
1
C1486
2
0.1U_0402_16V7K
SPKOUT_L1
40
SPKOUT_L2
41
SPKOUT_R1
45
SPKOUT_R2
44
HP_OUTL
32
HP_OUTR
33
HDA_SYNC_AUDIO
10
HDA_BITCLK_AUDIO
6
HDA_SDOUT_AUDIO
5
HDA_SDIN_AUDIO
8
47
48
20
29
30
28
AC97_VREF
27
AC_JDREF
19
34
26
37
1
C1476
2
10U_0805_10V6K
1
C1487
2
0.1U_0402_16V7K
1 2
1 2
1 2
20K_0402_1%
1 2
C1498
2.2U_0603_16V6K
+5VS
1 1
+3VS
R1539
2 2
DMIC_DATA27
DMIC_CLK27
EC_MUTE#32
3 3
+1.5VS
1 2
MIC2 MIC2_R
R1540
1 2
DMIC_DATA
DMIC_CLK
EC_MUTE#
12
4.7K_0402_5%
R1553
@
HDA_RST_AUDIO#
@
1
0.1U_0402_16V7K
C1503
2
+3VS_DVDD
R1537
12
0_0603_5%
MIC1_RMIC1
1K_0402_5%
1K_0402_5%
1 2
1 2
R1543 0_0402_5%
1 2
1 2
L124 FBMA-L10-160808-301LMT_2P
R1545 0_0402_5%
1 2
HDA_RST_AUDIO#14
MIC_JD
+MIC1_VREFO_L
R1534
0_0603_5%
1
C1488
C1489
2
10U_0603_6.3V6M
C1490 4.7U_0603_6.3V6K
C1493 4.7U_0603_6.3V6K
R1548
1 2
20K_0402_1%
R1549
39.2K_0402_1%
C1497 2.2U_0603_16V6K
12
C1481
+3VS_DVDD
1
2
0.1U_0402_16V7K
DMIC_DATA_CODEC
DMIC_CLK_CODEC
HDA_RST_AUDIO#
SENSE_AHP_JD
12
1 2
+3VS_DVDD_R
1
C1482
2
0.1U_0402_16V7K
MIC1_C
MIC2_C
PD#
1
2
+5VS_PVDD
10U_0603_6.3V6M
9
1
DVDD
PVDD139PVDD2
DVDD_IO
23
LINE1_L
24
LINE1_R
14
LINE2_L
15
LINE2_R
21
MIC1_L
22
MIC1_R
16
MIC2_L
17
MIC2_R
2
GPIO0/DMIC_D ATA
3
GPIO1/DMIC_C LK
4
PD#
11
RESET#
12
PCBEEP
13
SENSE A
18
SENSE B
36
CBP
35
CBN
31
MIC1_VREFO_L
43
PVSS2
42
PVSS1
49
DVSS2
7
DVSS1
ALC269Q-VB5-GR_QFN48_7X7
MIC1_VREFO_R
R1556 0_0402_5%
1 2
R1557 0_0402_5%
1 2
R1558 0_0402_5%
1 2
R1559 0_0402_5%
1 2
+VDDA
46
SPK_OUT_L+
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_R-
HP_OUT_L
HP_OUT_R
SYNC
BCLK
SDATA_OUT
SDATA_IN
EAPD
SPDIFO
MONO_OUT
MIC2_VREFO
LDO_CAP
VREF
JDREF
CPVEE
AVSS1
AVSS2
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2010/3/31 2012/06/30
E
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
F
Date: Sheet
Compal Electronics, Inc.
P25-HD CODEC ALC259
QBL70 LA-7553P
G
33 51Friday, April 29, 2011
H
0.22
of
5
4
3
2
1
Card Reader RTS5137
(only SD/MMC/MS function)
+3VS +3VS_CR
USB20_N4
USB20_P4
+CARDPWR
1 2
MS_INS#
SDD1
SDD0
MSD3
0.1U_0402_16V4Z
R370_0402_5%
30mil
10mil
+RREF
10mil
C1515
1
2
3
4
5
6
7
8
9
10
11
12
1
2
U51
REFE
DM
DP
3V3_IN
CARD_3V3
V18
NC
SP1
SP2
SP3
SP4
SP5
1
C1513
0.1U_0402_16V4Z
2
Close to connector
GPIO0
CLK_IN
NC
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
EPAD
RTS5137-GR_QFN24_4X4
25
17
24
23
22
21
20
19
18
16
15
14
13
@
1 2
R1561 10_0402_5%
CLK_SD_48M
MS_BS
SDD2_MS_D5
SDD3_MSD1
SDCMD
MSD0
1 2
SDCD#
SDCLK_MSD2
R740_0402_5%
C1509 10P_0402_50V8J@
EMI
1 2
CLK_SD_48M 13
SDCD#
SDWP_MSCLK
SDD1
SDD0
MS_BS
SDCLK_MSD2
SDD3_MSD1
MSD0
MS_INS#
MSD3
SDCMD
SDD2_MS_D5
+CARDPWR
JCR1
1
SD-CD
2
SD-WP
3
SD-DAT1
4
SD-DAT0
5
MS-GND
6
SD-GND
7
MS-BS
8
CD-CLK
9
MS-DAT1
10
MS-DAT0
11
SD-VCC
12
MS-DAT2
13
SD-GND
14
MS-INS
15
MS-DAT3
16
SD-CMD
17
MS-SCLK
18
MS-VCC
19
20
21
GND
SD-DAT3
GND
MS-GND
SD-DAT2
TAITW_R009-142-HM_RV
CONN@
22
23
D D
1
C1510
4.7U_0805_10V4Z
2
2
1
0.1U_0402_16V4Z
R1560 0_0603_5%
C1511
1
C1512
1U_0402_6.3V6K
2
1 2
@
12
C1507 100P_0402_50V8J
C1508
1 2
6.2K_0603_1%
USB20_N414
USB20_P414
+3VS_CR
30mil
+VREG
EMI
SDWP_MSCLK
Card Reader Connector
C C
+CARDPWR
30mil
@
1
R1562
100K_0402_5%
1 2
C1514
0.1U_0402_16V4Z
2
SDWP_MSCLK SDCLK_MSD2
B B
A A
5
4
EMI
close U51
1
C128
2
@
22P_0402_50V8J
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C129
2
@
22P_0402_50V8J
2009/10/08 2012/06/30
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
P26-RTS5137 Media Card Controller
QBL70 LA-7553P
1
34 51Friday, April 29, 2011
of
0.22
A
Mini-Express Card for WLAN/WiMAX(Half)
1 1
FCH_PCIE_WAKE#14,31,32
MINI1_CLKREQ#14
PCIE_W_DTX_C_FRX_N013
PCIE_W_DTX_C_FRX_P013
PCIE_W_FTX_DRX_N013
PCIE_W_FTX_DRX_P013
EC_TX_P80_DATA32
EC_RX_P80_CLK32
2 2
Mini-Express Card(WLAN/WiMAX)
BT_ON15
BT_ON15
R1565 0_0402_5%
1 2
R1587 0_0402_5%
MINI1_CLKREQ#
CLK_PCIE_MINI1#13
CLK_PCIE_MINI113
PCIE_W_DTX_C_FRX_N0
PCIE_W_DTX_C_FRX_P0
1 2
C952 0.1U_0402_16V7K
1 2
C953 0.1U_0402_16V7K
EC_TX_P80_DATA
EC_RX_P80_CLK
For EC to detect
debug card insert.
1 2
1 2
@
R1566 0_0402_5%
1 2
@
1 2
PCIE_W_FTX_C_DRX_N0
PCIE_W_FTX_C_DRX_P0
100_0402_1%
R1581
R1582
100_0402_1%
@
PCI_RST#_R
CLK_PCI_DB
+3VS_WLAN
EC_TX_P80_DATA_R
EC_RX_P80_CLK_R
1 2
WLAN_WAKE#
R1583
100K_0402_5%
JMINI1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
ACES_88915-5204
CONN@
B
R1563 0_1206_5%
@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
FCH_SMCLK0_R
30
30
FCH_SMDAT0_R
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
GND2
+1.5VS
+3VS_WLAN+3VS
12
R1567 0_0402_5%@
1 2
R1568 0_0402_5%
1 2
R1569 0_0402_5%@
1 2
R1570 0_0402_5%@
1 2
R1571 0_0402_5%@
1 2
R1572 0_0402_5%@
1 2
BT_LED_R#
+3VALW +1.5VS
1
@
C1516
0.1U_0402_16V4Z
2
12
R1564
0_1206_5%
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
USB20_N3 14
USB20_P3 14
1
C1517
0.1U_0402_16V4Z
2
WL_OFF# 15
WL_OFF#_EC 32
PLT_RST# 13,18,26,31
+3VALW
+3VS
FCH_SCLK0 11,12,14
FCH_SDATA0 11,12,14
WLAN_LED#WLAN_LED_R#
R15750_0402_5%
12
BT_LED#
R15770_0402_5%
12
1
C1518
0.1U_0402_16V4Z
2
C
SUSP#32, 38
WLAN_LED# 32
BT_LED# 32
W=60mils W=60mils
+3VALW
C1664
1U_0402_6.3V6K
+5VALW
R545
100K_0402_5%
1 2
1 2
R114 20K_0402_5%
13
D
Q32
2
SSM3K7002FU_SC70-3
G
S
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R PLT_RST#
CLK_PCI_DB
R1573 0_0402_5%
R1574 0_0402_5%
R1576 0_0402_5%
R1578 0_0402_5%
R1579 0_0402_5%
R1580 0_0402_5%
1
2
1 2
1 2
1 2
1 2
1 2
1 2
WLAN_EN#
Q31
S
G
AO3419L 1P SOT23-3
2
1
2
D
13
C1663
4700P_0603_50V7K
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
D
+3VS_WLAN
R1590 0_1206_5%
12
LPC_FRAME# 13,32
LPC_AD3 13,32
LPC_AD2 13,32
LPC_AD1 13,32
LPC_AD0 13,32
CLK_PCI_DB 13
EMI
CLK_PCI_DB
R93
C133
@
@
E
12
0_0402_5%
1
2
22P_0402_50V8J
+5VALW
LED
PWR_LED#32,36
CHARGE_LED1#32
CHARGE_LED0#32
3 3
RF_LED#32
SATA_LED#15
NUM_LED#32
4 4
CAPS_LED#32
A
1 2
R110 10K_0402_5%
Green
Orange
BATT_LOW_LED#
BATT_CHG_LED#
Green
D24
@
WLAN_LED_R# RF_D_LED#
RB751V_SOD323
D30
@
BT_LED_R#
RB751V_SOD323
R1589 0_0402_5%
1 2
Green
21
21
Green
Green
Green
LED1
1 2
19-21SYGC/S530-E3/TR8 0603 Y/G
LED2
O
W
HT-297DQ/GQ 0603 AMB/YG
LED3
1 2
19-21SYGC/S530-E3/TR8 0603 Y/G
LED4
1 2
19-21SYGC/S530-E3/TR8 0603 Y/G
LED5
1 2
19-21SYGC/S530-E3/TR8 0603 Y/G
LED6
1 2
19-21SYGC/S530-E3/TR8 0603 Y/G
12
+3VALW
R1584100_0402_5%
PWR_LED#
21
43
12
R1585300_0402_5%
12
R1586100_0402_5%
+3VALW
+3VALW
12
+3VS
R1588100_0402_5%
12
R1591100_0402_5%
+3VS
CHARGE_LED1#
CHARGE_LED0#
RF_D_LED#
SATA_LED#
NUM_LED#
CAPS_LED#
D22
@
2
1
3
YSDA0502C 3P C/A SOT-23
D25
@
2
1
3
YSDA0502C 3P C/A SOT-23
D26
@
2
1
3
YSDA0502C 3P C/A SOT-23
D27
@
2
1
3
YSDA0502C 3P C/A SOT-23
ESD
12
R1593100_0402_5%
12
R1594100_0402_5%
B
+3VS
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERIN G DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010/06/30 2012/06/30
Compal Secret Dat a
Deciphered Date
D
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
P27-Mini PCIE/LED
QBL70 LA-7553P
E
35 51Friday, April 29, 2011
of
0.22
For SR
JBTN1
G1
E-T_6905K-Q04N-00R
G2
CONN@
7RS6LGH
%RWWRP6LGH
4
4
3
3
2
2
1
1
5
6
SMT1-05-A_4P
1
2
ON/OFFBTN#
@
@
SW3
SMT1-05-A_4P
1
2
5
6
@
SW4
5
6
2
3
1
ON/OFF switch
ON/OFFBTN#ON/OFFBTN#
3
4
3
4
PJSOT24CH_SOT23-3
D21
EC_ON32
Power Button
D12
1
DAN202UT106_SC70-3
EC_ON
2
G
R496
10K_0402_5%
1 2
PWR_LED# 32,35
+5VALW
+3VALW
R1791
100K_0402_5%
1 2
2
3
Change to SC600000B00
13
D
S
2
C773
1000P_0402_50V7K
1
SSM3K7002FU_SC70-3
Q27
ON/OFF 32
51_ON# 40
10K_0402_5%
FAN_SPEED1
1000P_0402_50V7K
C702
R653
Fan Control Circuit
+5VS+3VS
2
C701
2.2U_0603_106K
1 2
1
2
8
7
6
5
APL5607KI-TRG_SO8
EN_DFAN132
GND
GND
GND
GND
VOUT
VSET
U53
1
EN
2
VIN
3
4
1
12
C703
10U_0603_6.3V6M
H7
H_3P0
@
1
+5VS_FAN
H6
H_3P0
1
FAN_SPEED132
H18
H_4P2
@
1
H5
H_3P0
@
@
1
H_4P2
H4
H_3P0
H17
1
H16
H_4P2
@
1
H3
H_3P0
@
H_3P2
H_4P2
@
1
@
1
1
2
FAN_SPEED1
H19
@
1
H15
@
1
H2
H_3P0
@
1
C700
1000P_0402_50V7K
JFAN1
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N
CONN@
3.2
4.2
3.0
FD1
1
FIDUCIAL_C40M80
H27
H_3P0
1
H8
H10
H_2P5
H_2P5
@
1
H23
H_4P5X3P2
@
FD2
1
FIDUCIAL_C40M80
FD3
1
FIDUCIAL_C40M80
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FD4
1
FIDUCIAL_C40M80
2010/08/20 2012/06/30
Compal Secret Data
Deciphered Date
1
H_2P5
@
1
4.5X3.2
@
H1
@
1
H26
H_3P0
@
1
2.5
H12
H_3P0
H_3P0
@
1
H28
H_3P8
1
Title
Size Document Number Rev
Custom
QBL70 LA-7553P
Date: Sheet
H20
H11
@
H_3P0
@
1
H_6P0
H25
H_3P8
H24
1
H9
H_3P0
H14
H_6P0
H22
H_3P8
H21
H_3P3
@
1
@
1
@
1
@
1
3.0
6.0
3.8
3.3
@
1
@
1
@
Compal Electronics, Inc.
P33-Other IO/USB (right)
of
36 51Friday, April 29, 2011
0.22
5
4
3
2
1
INT_KBD Conn.
KSI[0..7]
D D
C C
KSO[0..15]
KSO2
C1543 100P_0402_50V8J@
KSO15
C1546 100P_0402_50V8J@
KSO6
C1547 100P_0402_50V8J@
KSO8
C1549 100P_0402_50V8J@
KSO13
C1551 100P_0402_50V8J@
KSO12
C1553 100P_0402_50V8J@
KSO11
C1555 100P_0402_50V8J@
KSO10
C1557 100P_0402_50V8J@
KSO3
C1559 100P_0402_50V8J@
KSO4
C1561 100P_0402_50V8J@
KSI0
C1563 100P_0402_50V8J@
KSO0
C1565 100P_0402_50V8J@
CONN PIN define need double check
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
KSI[0..7] 3 2
KSO[0..15] 32
KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
C1544 100P_0402_50V8J@
1 2
C1545 100P_0402_50V8J@
1 2
C1548 100P_0402_50V8J@
1 2
C1550 100P_0402_50V8J@
1 2
C1552 100P_0402_50V8J@
1 2
C1554 100P_0402_50V8J@
1 2
C1556 100P_0402_50V8J@
1 2
C1558 100P_0402_50V8J@
1 2
C1560 100P_0402_50V8J@
1 2
C1562 100P_0402_50V8J@
1 2
C1564 100P_0402_50V8J@
1 2
C1566 100P_0402_50V8J@
1 2
KSO7
KSO0
KSI1
KSI7
KSO9
KSI6
KSI5
KSO3
KSI4
KSI2
KSO1
KSI3
KSI0
KSO13
KSO5
KSO2
KSO4
KSO8
KSO6
KSO11
KSO10
KSO12
KSO14
KSO15
To TP/B Conn.
+5VS
C1567
0.1U_0402_16V4Z
TP_CLK32
TP_DATA32
B B
1
@
C1568
100P_0402_50V8J
2
1
@
C1569
100P_0402_50V8J
2
TP_CLK
TP_DATATP_DATA
SW/L
SW/R
E-T_6905-E06N-00R
6
5
4
3
2
1
CONN@
GND
GND
6
5
4
3
2
1
JTP1
8
7
ACES_85202-24051
26
G2
25
G1
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JKB1
CONN@
+3VALW
C136
0.1U_0402_16V4Z
REED Switch
@
Q34
VDD2VOUT
GND
1
+3VALW
LID_SW#
3
APX9131AAI-TRG_SOT23-3
12
R140
47K_0402_5%
LID_SW# 32
2
3
@
1
YSDA0502C 3P C/A SOT-23
D20
YSDA0502C 3P C/A SOT-23
2
3
D17
@
1
ESD
SW/L
A A
5
DTSM-61N-S-V-T-R(756)_4P
3
4
1
2
SW5
SW/R
DTSM-61N-S-V-T-R(756)_4P
3
4
1
2
SW6
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/06/30 2012/06/30
3
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
P30-KB /SW/TP/Lid
QBL70 LA-7553P
1
of
37 51Friday, April 29, 2011
0.22
A
ĬĶŗłōŘġŕŐġĬĶŗŔ
ĬĶŗłōŘġŕŐġĬĶŗŔ
ĬĶŗłōŘġŕŐġĬĶŗŔĬĶŗłōŘġŕŐġĬĶŗŔ
ĩĶłĪ
ĩĶłĪ
ĩĶłĪĩĶłĪ
10U_0805_10V4Z
1 1
1 2
+VSB
R1103 47K_0402_5%
SSM3K7002FU_SC70-3
ĬĴŗłōŘġŕŐġĬĴŗŔġĩĴįĴłĪ
ĬĴŗłōŘġŕŐġĬĴŗŔġĩĴįĴłĪ
ĬĴŗłōŘġŕŐġĬĴŗŔġĩĴįĴłĪĬĴŗłōŘġŕŐġĬĴŗŔġĩĴįĴłĪ
10U_0603_6.3V6M
1
2
+VSB
2 2
ĬIJįĶŗġŕŐġĬIJįĶŗŔġĩIJįĶłĪ
ĬIJįĶŗġŕŐġĬIJįĶŗŔġĩIJįĶłĪ
ĬIJįĶŗġŕŐġĬIJįĶŗŔġĩIJįĶłĪĬIJįĶŗġŕŐġĬIJįĶŗŔġĩIJįĶłĪ
3 3
R1112 200K_0402_5%
SSM3K7002FU_SC70-3
SUSP#
+1.0VSG
+5VALW
U38
SI4178DY-T1-GE3 1N SO8
8
7
10U_0805_10V4Z
C1443
1
2
SUSP
C1453
12
SUSP
R1122
47K_0402_5%
0.22U_0603_16V4Z
5
1
C1445
2
5VS_GATE
13
D
Q3
2
G
S
+3VALW +3VS
U40
SI4178DY-T1-GE3 1N SO8
8
7
10U_0603_6.3V6M
5
1
C1454
2
3VS_GATE
13
D
Q7
2
G
S
R1116
100K_0402_5%
SSM3K7002FU_SC70-3
12
C1463
+VGA_CORE
1 2
2
G
1
2
4
1
C1450
0.1U_0603_25V7K
2
1
2
36
4
1
C1456
0.1U_0603_25V7K
2
AP2301GN-HF_SOT23-3
Q63
3 1
2
13
D
Q45
S
+5VS
1
2
36
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
+1.8VSG
10U_0805_10V4Z
1
2
1
C1452
2
+1.5VS+1.5V
C1461
D
S
1U_0603_10V6K
C1446
12
1U_0402_6.3V4Z
C1455
1
2
R1117
470_0603_5%
1 2
13
Q46
2
G
SSM3K7002FU_SC70-3
C1444
D
S
R1110
470_0603_5%
1 2
13
D
Q28
S
SSM3K7002FU_SC70-3
SUSP
+1.2VS
B
R1099
470_0603_5%
1 2
13
Q4
SUSP
2
G
SSM3K7002FU_SC70-3
SUSP
2
G
C
ĬIJįIJŗłōŘġŕŐġĬIJįIJŗŔġĩIJįIJłĪ
ĬIJįIJŗłōŘġŕŐġĬIJįIJŗŔġĩIJįIJłĪ
ĬIJįIJŗłōŘġŕŐġĬIJįIJŗŔġĩIJįIJłĪĬIJįIJŗłōŘġŕŐġĬIJįIJŗŔġĩIJįIJłĪ
R1100
1K_0402_5%
1 2
+VSB
R1105 47K_0402_5%
VLDT_EN#
SSM3K7002FU_SC70-3
ŗňłġőŰŸŦų
ŗňłġőŰŸŦų
ŗňłġőŰŸŦųŗňłġőŰŸŦų
+1.1VALW
U39
AO4430L_SO8
8
7
10U_0603_6.3V6M
2
G
Q5
1
C1448
2
1.1VS_GATE
13
D
S
6
5
12
+1.5V to +1.5VSG (1.5A)
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C1459
2
1 2
+VSB
R1118 100K_0402_5%
1.5_VDD_PWREN#
0.1U_0402_16V7K
12
R1120 47K_0402_5%
SSM3K7002FU_SC70-3
1
C1464
2
1
2
3
4
1
C1451
0.1U_0603_25V7K
2
+1.5V
8
7
6
5
1
C1460
2
1.5VSG_GATE
13
D
Q37
2
G
S
+1.1VS
10U_0603_6.3V6M
1
2
U41
AO4430L_SO8
C1447
4
1U_0402_6.3V4Z
C1449
1
2
+1.5VSG
1
2
10U_0603_6.3V6M
3
1
C1462
0.1U_0603_25V7K
2
R1101
470_0603_5%
1 2
13
D
Q6
VLDT_EN#
2
G
S
SSM3K7002FU_SC70-3
Current
1
1
C1458
C1457
1U_0402_6.3V4Z
2
2
D
VLDT_EN32,46
10K_0402_5%
R1114
470_0603_5%
1 2
13
D
Q42
1.5_VDD_PWREN#
2
G
S
SSM3K7002FU_SC70-3
R1102
VLDT_EN#
2
G
12
+5VALW
1 2
13
R1097
100K_0402_5%
D
Q51
2N7002_SOT23
S
VGA_PWR_ON25,42,45
SSM3K7002FU_SC70-3
SYSON32,43
100K_0402_5%
SUSP28,45
SUSP#32,35
SSM3K7002FU_SC70-3
VGA_PWR_ON
100K_0402_5%
E
SYSON#
Q43
2
G
12
R1104
SUSP
SSM3K7002FU_SC70-3
10K_0402_5%
R1123
R1109
VGA_PWR_ON#
12
2
G
12
Q68
2
G
+5VALW
1 2
13
+5VALW
Q44
+5VALW
1 2
13
D
S
D
S
R1098
100K_0402_5%
R1108
100K_0402_5%
1 2
13
D
S
R1119
100K_0402_5%
A
R1126
470_0603_5%
1 2
13
D
S
R1136
470_0603_5%
1 2
13
D
S
1.5_VDD_PWREN#
2
G
Q72
2N7002_SOT23
2
G
Q79
2N7002_SOT23
D
S
+0.75VS+2.5VS
D
S
R1127
33_0603_5%
1 2
13
2
G
Q73
2N7002_SOT23
R1137
470_0603_5%
1 2
13
2
G
2N7002_SOT23
Q80
04/19
VGA_PWR_ON#
SUSPSUSP
R1128
470_0603_5%
1 2
13
D
S
B
VLDT_EN#
2
G
Q74
2N7002_SOT23
+3VS to +3VSG (3.3A)
Change to Jump
201012062000
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+5VALW
R1131
PJ14
@
2
112
JUMP_43X118
C
+3VSG+3VS
2010/08/04 2010/08/04
Compal Secret Data
Deciphered Date
D
1.5_VDD_PWREN#
SSM3K7002FU_SC70-3
1.5_VDD_PWREN25,48
R1134
10K_0402_5%
Title
Size Document Number Rev
B
Date: Sheet
Compal Electronics, Inc.
DC Interface
QBL70 LA-7553P
E
100K_0402_5%
1 2
13
D
Q77
2
G
12
S
38 51Friday, April 29, 2011
0.22
of
R1125
470_0603_5%
1 2
13
D
VGA_PWR_ON#
2
G
Q71
S
2N7002_SOT23
+1.5V
4 4
R1135
470_0603_5%
1 2
13
D
S
2
G
Q78
2N7002_SOT23
SYSON#
A
B
C
D
(B+ 6A,240mils ,Via NO.= 12)
B+
4
3
VIN
RB751V-40TE17_SOD323-2
12
PC109
2.2U_0603_6.3V6K
6251_EN CSON
PR130
CHG_ICOMP
CHG_VCOMP
CHG_ICM
6251VREF
6251aclim
CHG_VADJ
PR106
22K_0402_1%
1 2
1 2
CHG_VIN
1 2
PU101
10_1206_5%
1
VDD
2
ACSET
ACPRN
3
EN
4
CELLS
5
ICOMP
6
VCOMP
7
PHASE
ICM
8
UGATE
VREF
9
CHLIM
10
ACLIM
11
VADJ
LGATE
12
GND
ISL6251AHAZ-T QSOP 24P
PR113
DCIN
CSON
CSOP
CSIN
CSIP
BOOT
VDDP
PGND
PD101
PR108
191K_0402_1%
1 2
24
23
22
21
20
19
18
17
BST_CHG
16
15
DL_CHG
14
13
PL102
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
ACSETIN
12
12
PC110
1000P_0402_50V7K
PC112
1U_0603_25V6K
DCIN
1 2
ACPRN
CHG_CSON
PC113
0.047U_0603_16V7K
1 2
CHG_CSIN
PC118
0.1U_0603_25V7K
CHG_CSIP
1 2
LX_CHG
DH_CHG
0_0603_5%
6251VDDP
PR126
1 2
PC123
1 2
4.7U_0805_6.3V6K
PR118
20_0603_5%
1 2
1 2
PR119
20_0603_5%
20_0603_5%
1 2
PR122
2.2_0603_1%
0_0402_5%
1 2
BST_CHGA
12
47K_0402_1%
12
CSIN
CSIP
PR111
14.3K_0402_1%
12
PR120
PR134
PC121
0.1U_0603_25V7K
PD106
RB751V-40TE17_SOD323-2
6251VDD
1 2
PR129
4.7_0603_5%
12
PR131
ACPRN
MMBT3904WH NPN SOT323-3
CSOPCHG_CSOP
12
2
B
6251VDD
12
C
E
3 1
12
PC103
4.7U_0805_25V6-K
PR132
10K_0402_1%
PQ112
CHG_B+
12
12
12
PC104
10U_0805_25V6K
5
4
PR133
10K_0402_1%
1 2
12
PR136
20K_0402_1%
PC106
PC105
0.1U_0402_25V6
2200P_0402_25V7K
PR112
47K_0402_1%
LTC015EUBFS8TL NPN UMT3F
3 5
241
786
PQ106
PQ108
AON7408L_DFN8-5
10UH +-20% MSCDRI-104A-100M-E
1 2
12
PQ110
PR125
@4.7_1206_5%
AO4468L_SO8
123
CHG_SNUB
12
PC124
@680P_0402_50V7K
ACIN 3 2
PACIN
PL101
1
2
36
12
PQ107B
P2
12
PC108
0.1U_0603_25V7K
12
CHG_N_002
34
5
PQ102
AO4409L_SO8
1
2
3 6
4
PR107
200K_0402_1%
CHG_N_003
PR116
150K_0402_1%
FSTCHG32
PC120 must close EC pin.
13
IREF32
PQ111
LTC015EUBFS8TL NPN UMT3F
PR103
150K_0402_1%
140K_0402_1%
12
PR104
8
7
5
PC107
@5600P_0402_25V7K
0.01U_0402_25V7K
ADP_ I32
PQ101
PQ104
2
CHG_N_009
PACIN
ACOFF
AO4435L_SO8
8
7
5
4
2
CHG_N_010
1 3
13
PQ105
LTC015EUBFS8TL NPN UMT3F
SSM6N7002FU_US6
PR124
22K_0402_5%
1 2
2
VIN
1 1
LTA044EUBFS8TL PNP UMT3F
12
2
ACOFF32
PR109
CHG_N_001
61
PQ107A
SSM6N7002FU_US6
47K_0402_1%
2 2
3 3
1 2
12
2S: Float
3S: GND
PC117
1 2
12
PC122
0.01U_0402_25V7K
CHGVADJ32
P3
10K_0402_1%
PC116 6800P_0402_25V7K
6251VREF
PR101
0.02_1206_1%
1
2
PR114
12
12
PR117
1 2
PR121 10K_0402_1%
1 2
PR123 100_0402_1%
1 2
1 2
PC120
0.1U_0402_16V7K
PR127
1 2
12.4K_0402_1%
Rtop
PR128
20K_0402_1%
PR105
10K_0402_1%
1 2
6251VDD
ACSETIN
100K_0402_1%
CHG_CHLIM
12
0_0402_5%
1 2
CP= 85%*Iada;
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K
90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
4 4
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A
1 2
CHG_N_008
13
B+
AO4407AL 1P SO8
1
2
3 6
CHG_N_005
PR110
200K_0402_1%
1 2
CHG_N_006
2
PC114
@2200P_0402_25V7K
PR102
0.02_1206_1%
CHG
1
2
PQ103
4
VIN
PR115
100K_0402_1%
1 2
12
4
3
8
7
5
CHG_N_001
13
D
ACPRN
2
G
PQ109
S
@SSM3K7002FU_SC70-3
12
12
PC101
PC102
10U_0805_25V6K
10U_0805_25V6K
BATT+
12
PC111
10U_0805_25V6K
CC=0.25A~3A
IREF=1.016*Icharge
IREF=0.254V~3.048V
VCHLIM need over 95mV
A
CHGVADJ=(Vcell-4)/0.10627
Vcell
4V
4.2V
CHGVADJ
0V
1.882V
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/01/23 2010/01/23
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CHARGER
NCL61 LA-6321P M/B
D
39 49Friday, April 29, 2011
of
0.1
A
B
C
D
PL1
HCB2012KF-121T50_0805
1 2
PL2
12
@4.7U_0805_25V6-K
HCB2012KF-121T50_0805
1 2
12
PC2
100P_0402_50V8J
PC3
12
PC14
1000P_0402_50V7K
PJPDC1
4
4
3
3
1 1
@CVILU_CI0104P1VRB-NH
PJP2
1
2
3
4
5
6
7
8
2 2
9
G1
G2
2
2
1
1
1
2
3
4
EC_SMCA
5
EC_SMDA
6
TS_A
7
8
9
10
11
ADPIN
PD1
12
PC1
PC13
1000P_0402_50V7K
PR27
1
1K_0402_1%
1 2
VIN
12
12
PC4
@4.7U_0805_25V6-K
100P_0402_50V8J
HCB2012KF-121T50_0805
VMB
HCB2012KF-121T50_0805
12
PC6
1000P_0402_50V7K
PL3
1 2
PL4
1 2
0.01U_0402_25V7K
PC7
0.1U_0603_16V7K
X7R type
12
12
PC15
10U_0805_25V6K
PC5
BATT+
PH1 under CPU botten side :
CPU thermal protection at 92 +-3 degree C
Recovery at 80 +-3 degree C
VL
12
OTP_N_003
PU1
1
VCC
2
GND
3
OT1
4
OT2
G718TM1U_SOT23-8
PR4
0_0402_5%
TMSNS1
RHYST1
TMSNS2
RHYST2
12
8
OTP_N_002
7
6
5
VS_ON 41
OTP_N_001
PR1
1 2
12
PR2 22.1K_0402_1%
12
PH1
100K_0402_1%_NCP15W F104F03RC
22K_0402_1%
@SUYIN_200275MR009G180ZR
2
3
@PJSOT24CW_SOT323-3
PD2
2
1
3
PR28
100_0402_1%
1 2
1 2
PR31
100_0402_1%
PR30
1 2
3 3
1K_0402_1%
@PJSOT24CW _SOT323-3
PR29
1 2
100K_0402_5%
+3VALW
BATT_TEMP 32
EC_SMB_CK1 32
EC_SMB_DA1 32
100K_0402_1%
SPOK41,44
PR13
VIN
VL
1 2
B+
PR16
0_0402_5%
1 2
VSB_N_002
12
12
12
PC8
PR10
2
G
PR12
22K_0402_1%
1 2
VSB_N_003
13
D
PQ2
SSM3K7002FU_SC70-3
S
100K_0402_1%
TP0610K-T1-GE3_SOT23-3
0.22U_0603_25V7K
VSB_N_001
PC10
13
2
PQ1
+VSBP
12
PC9
0.1U_0603_25V7K
0.1U_0402_16V7K
PD3
RLS4148_LL34-2
1 2
BATT+
RLS4148_LL34-2
PD4
12
PQ3
TP0610K-T1-GE3_SOT23-3
N1
12
PR21
4 4
51_ON#36
100K_0402_1%
1 2
PR22
22K_0402_1%
12
PC11
0.22U_0603_25V7K
VS_N_002
2
PR17
68_1206_5%
13
VS_N_001
12
12
PR18
68_1206_5%
12
PC12
0.1U_0603_25V7K
VS
+VSBP +VSB
(120mA,40mils ,Via NO.= 1)
PJ2
2
@JUMP_43X39
112
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2010/01/232009/01/23
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DCIN / BATT CONN / OTP
NCL61 LA-6321P M/B
D
40 49Friday, April 29, 2011
0.1
of
A
B
C
D
E
2VREF_6182
1 1
1U_0603_16V6K
PR301
13.7K_0402_1%
1 2
133K_0402_1%
12
PR302
20K_0402_1%
1 2
PR303
1 2
PU301
25
7
8
9
10
11
12
12
PC320
1U_0603_10V6K
2VREF_6182
P PAD
VO2
VREG3
BOOT2
UGATE2
PHASE2
LGATE2
B+
2 2
3 3
PL301
HCB2012KF-121T50_0805
1 2
12
PC322
@680P_0402_50V7K
B++
12
12
PC309
PC310
0.1U_0402_25V6
2200P_0402_50V7K
+3VALWP
220U 6.3V M 6.3X5.9 R15M VL HF
12
PC304
4.7U_0805_25V6-K
PL303
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
+
PC303
2
12
PR312
@4.7_1206_5%
PC316
@680P_0402_50V7K
+3VLP
PQ303
AON7408L_DFN8-5
10U_0805_6.3V6M
3 5
241
786
123
5
PQ304
AO4468L_SO8
12
SNUB_3V
12
0.1U_0402_10V7K
4
PC313
PC314
1 2
LX_3V
12
1 2
0_0402_5%
B++
PR311
1 2
95.3K_0402_1%
PR308
1 2
0_0402_5%
LG_3V
PR314
499K_0402_1%
EN0
PR315
PC308
FB_3V
ENTRIP2
6
13
12
PR305
30.9K_0402_1%
1 2
PR306
20K_0402_1%
FB_5V
1 2
PR307
165K_0402_1%
ENTRIP1
1 2
3
4
2
5
FB2
ENTRIP2
SKIPSEL
EN
14
15
TONSEL
1
FB1
REF
ENTRIP1
VO1
PGOOD
BOOT1
UGATE1
PHASE1
LGATE1
NC18VREG5
VIN16GND
17
RT8205LZQW(2) WQFN 24P PWM
24
23
BST_5V
22
UG_5VUG_3V
21
LX_5V
20
LG_5V
19
VL
12
PC318
4.7U_0805_10V6K
12
B++
PC319
0.1U_0603_25V7K
PR309
2.2_0402_5%
1 2
B++
12
PC311
0.1U_0402_25V6
BST1_5VBST1_3V BST_3V
PR310
1 2
0_0402_5%
12
PC312
2200P_0402_50V7K
PC315
0.1U_0402_10V7K
1 2
SPOK 40,44
12
PC306
10U_0805_25V6K
AO4406AL 1N SO8
PQ306
4
3 5
241
786
5
PQ305
AON7408L_DFN8-5
123
PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1 2
12
1
+
PC305
220U 6.3V M 6.3X5.9 R15M VL HF
2
SNUB_5V
12
PR313
@4.7_1206_5%
PC317
@680P_0402_50V7K
+5VALWP
ENTRIP1
61
D
PQ307A
SSM6N7002FU_US6
S
VS_ON40
1 2
VS
PR319
100K_0402_1%
4 4
EC:+3VL, reserve PR319, install PR318, PR320 100K
EC:+3VALW, reserve PR318, install PR319, PR320 42.2K
A
12
PR320
12
42.2K_0402_1%
2
G
PC321
N_3_5V_001
13
2
2.2U_0603_10V6K
ENTRIP2
34
D
S
1 2
PR317
100K_0402_5%
PQ307B
SSM6N7002FU_US6
5
G
PQ308
LTC015EUBFS8TL NPN UMT3F
B
+3VLP
PJP306
VL
+5VALWP
+5VALWP
+3VALWP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
PAD-OPEN 4x4m
PJP305
1 2
PAD-OPEN 4x4m
PJP303
1 2
PAD-OPEN 4x4m
C
2007/08/02 2008/08/02
(5A,200mils ,Via NO.= 10)
+5VALW
(5A,200mils ,Via NO.= 10)
+5VALW
(4A,120mils ,Via NO.= 8)
+3VALW
Compal Secret Data
Deciphered Date
VL
Title
Size Document Number Rev
Custom
D
Date: Sheet
PJP302
2 1
PAD-OPEN 2x2m
PJP301
2 1
PAD-OPEN 2x2m
Compal Electronics, Inc.
+CHGRTC
3.3VALWP/5VALWP
LAXXXX
41 49Friday, April 29, 2011
E
0.1
of
A
1 1
B
C
D
+5VALW
1 2
12
2 2
VGA_PWR_ON25,38,45
1 2
PR404 200K_0402_5%
1 2
PD401
1SS355_SOD323-2
PC403
22U_0805_6.3VAM
EN_1.8VSP
@47K_0402_5%
1.8VSP_VIN
12
PR405
PL402
HCB1608KF-121T30_0603
PU401
4
10
PVIN
PG
9
PVIN
8
SVIN
5
EN
TP
NC
7
11
12
PC405
RT8061AZQW W DFN 10P
1.8VSP_LX
2
LX
3
LX
1.8VSP_FB
6
FB
NC
1
0.1U_0402_10V7K
PL401
1UH_VLS252012T-1R0N1R7_2.4A_30%
1 2
12
PR403
4.7_1206_5%
20K_0402_1%
12
PR401
12
PR402
10K_0402_1%
SNUB_1.8VSP
12
<Vo=1.8V> VFB=0.6V
+1.8VSGP
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
12
PC404
68P_0402_50V8J
12
12
PC402
PC401
22U_0805_6.3VAM
22U_0805_6.3VAM
PC406
680P_0402_50V7K
+1.8VSGP
1 2
(2A, 80mils, Via NO.= 4)
+1.8VSG
PJP401
PAD-OPEN 3x3m
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2010/01/232009/01/23
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.8VSGP
NCL61 LA-6321P M/B
D
42 49Friday, April 29, 2011
0.1
of
5
D D
4
3
2
1
PQ502
+1.5VP
1.5V_B+
3 5
578
3 6
PQ501
AON7408L_DFN8-5
241
241
12
12
PC503
PC504
10U_0805_25V6K
@4.7U_0805_25V6-K
PL501
1UH +-20% VMPI0703AR-1R0M-Z01 11A
1 2
12
PR509
@4.7_1206_5%
SNUB_1.5V
12
PC511
@680P_0402_50V7K
PJP502
1 2
@PAD-OPEN 4x4m
PJP501
1 2
@PAD-OPEN 4x4m
12
PC506
2200P_0402_50V7K
+1.5V
PR503
SYSON32,38
C C
+5VALW
B B
+1.5VP
1 2
PR507
100_0402_1%
PC509
4.7U_0603_10V6K
0_0402_5%
V5FILT_1.5V+5VALW
+1.5VP
12
12
PC505
12
@0.1U_0402_10V7K
PR506
255K_0402_1%
1 2
PR501
1 2
2.21K_0402_1%
2.15K_0402_1%
PR502
TON_1.5V
FB_1.5V
12
EN_1.5V
2
3
4
5
6
PU501
TON
VOUT
VDD
FB
PGOOD
14
1
15
NC
BOOT
EN/DEM
UGATE
PHASE
VDDP
LGATE
GND7PGND
8
RT8209MGQW_W QFN14_3P5X3P5
CS
PR504
2.2_0402_5%
1 2
UG_1.5V
13
LX_1.5V
12
TRIP_1.5V
11
10
LG_1.5V
9
BST1_1.5VBST_1.5V
0.1U_0402_10V7K
PR508
1 2
+5VALW
1 2
PC508
15K_0402_1%
+5VALW
12
PC510
4.7U_0805_10V6K
PR505
0_0402_5%
12
FDS6690AS-G_SO8
PL502
HCB1608KF-121T30_0603
12
PC507
0.1U_0402_25V6
+1.5VP
1
+
PC501
220U 6.3V M 6.3X5.9 R15M VL HF
2
(8A,320mils ,Via NO.= 16)
B+
12
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/05/29 2008/05/29
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
+1.5VP
LAXXXX
1
of
43 49Friday, April 29, 2011
0.1
5
4
3
2
1
D D
SPOK40,41
+1.1VALWP
+5VALW
C C
B B
1 2
PR707
100_0402_1%
4.7U_0603_6.3V6M
PC708
PR703
0_0402_5%
V5FILT_1.1V+5VALW
+1.1VALWP
12
12
PC704
12
@0.1U_0402_10V7K
255K_0402_1%
1 2
1 2
4.75K_0402_1%
10K_0402_1%
PR705
PR701
PR702
TON_1.1V
FB_1.1V
12
EN_1.1V
2
3
4
5
6
PU701
TON
VOUT
VDD
FB
PGOOD
1
EN/DEM
GND7PGND
PR704
2.2_0402_5%
1 2
14
15
NC
13
BOOT
UGATE
12
PHASE
11
CS
10
VDDP
9
LGATE
RT8209MGQW_W QFN14_3P5X3P5
8
UG_1.1V
LX_1.1V
TRIP_1.1V
LG_1.1V
BST1_1.1VBST_1.1V
PC707
0.1U_0402_10V7K
PR708 14K_0402_1%
1 2
+5VALW
12
1 2
+5VALW
PC709
4.7U_0805_10V6K
PR710
0_0402_5%
12
AO4468L_SO8
PQ702
1.1V_B+
5
4
+1.1VALWP
AON7408L_DFN8-5
3 5
241
786
123
PQ701
1
12
PC702
2
10U_0805_25V6K
2.2UH_PCMC063T-2R2MN_8A_20%
1 2
12
PR709
@4.7_1206_5%
SNUB_1.1V
12
PC710
@680P_0402_50V7K
PJP701
1 2
PAD-OPEN 4x4m
HCB1608KF-121T30_0603
12
PC705
PC706
2200P_0402_50V7K
PL701
PR706
@100K_0402_5%
+1.1VALW
PL702
0.1U_0402_25V6
B+
12
+1.1VALWP
1
+
PC701
220U 6.3V M 6.3X5.9 R15M VL HF
2
1 2
(5A,200mils ,Via NO.=20)
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/12/01 2010/12/31
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
PWR+1.1VALWP
Size Document Number Rev
Custom
LAXXXX
2
Date: Sheet
44 49Friday, April 29, 2011
1
0.1
of
5
+1.5V
D D
SUSP28,38
PR604
0_0402_5%
4.7U_0805_6.3V6K
SSM3K7002FU_SC70-3
0.75VS_N_002
12
PC601
PQ602
2
G
12
PC606
@0.1U_0402_10V7K
12
VREF_G2992
13
D
S
12
PR601
1K_0402_1%
12
PR602
1K_0402_1%
4
PU601
1
2
3
4
APL5336KAI-TRL_SOP 8P8
VIN
GND
VREF
VOUT
VCNTL
8
NC
7
NC
6
5
NC
9
TP
12
PC603
1U_0603_10V6K
+3VALW
3
2
1
+0.75VSP
12
12
PC605
10U_0805_6.3V6M
0.1U_0402_16V7K
PC604
PR609
15K_0402_1%
1 2
1 2
PD601
1SS355_SOD323-2
PJP601
1 2
PAD-OPEN 3x3m
+1.5V
12
PC611
4.7U_0805_6.3V6K
0.1U_0402_16V7K
PC613
+1.0VSP
+5VALW
(2A,80mils ,Via NO.= 4)
+0.75VS
12
PC612
1U_0603_10V6K
PU602
APL5930KAI-TRG_SO 8
6
VCNTL
5
VIN
VOUT
9
VIN
VOUT
8
EN
7
POK
GND
12
1
PJP603
1 2
PAD-OPEN 3x3m
FB
3
4
1.82K_0402_1%
2
7.32K_0402_1%
12
PR610
PR611
+1.0VSG
12
PC614
12
(2.5A,100mils ,Via NO.= 5)
PU603
APL5508-25DC-TRL_SOT89-3
PC607
2
IN
PJP602
1 2
PAD-OPEN 3x3m
+3VS
12
1U_0402_6.3V6K
+2.5VSP
+1.0VSP
12
PC615
180P_0402_50V8J
22U_0805_6.3V6M
GND
3
OUT
1
12
PC608
4.7U_0805_6.3V6K
+2.5VS
12
PR605
@150_1206_5%
+2.5VSP
C C
B B
VGA_PWR_ON25,38,42
A A
+0.75VSP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/11/23 2007/11/23
Compal Secret Data
Deciphered Date
2
Title
Size Doc ument Number Rev
Date: Sheet
Compal Electronics, Inc.
PWR 0.75VSP/1.0VSP/2.5VSP
LAXXXX
1
of
45 49Friday, April 29, 2011
0.1
A
1 1
B
C
D
PQ802
4
1.2V_B+
3 5
5
PQ801
AON7408L_DFN8-5
241
786
123
12
PC802
10U_0805_25V6K
2.2UH_PCMC063T-2R2MN_8A_20%
1 2
12
PR809
@4.7_1206_5%
SNUB_1.2V
12
PC810
@680P_0402_50V7K
12
PL801
PR803
VLDT_EN32,38
2 2
+5VALW
3 3
1 2
PR807
100_0402_1%
PC808
4.7U_0603_6.3V6M
0_0402_5%
V5FILT_1.2V+5VALW
12
12
PC804
12
@0.1U_0402_10V7K
+1.2VS
3.24K_0402_1%
PR805
255K_0402_1%
1 2
+1.2VS
PR801
1 2
PR802
5.36K_0402_1%
TON_1.2V
FB_1.2V
12
EN_1.2V
2
3
4
5
6
PU801
TON
VOUT
VDD
FB
PGOOD
14
1
15
NC
BOOT
UGATE
EN/DEM
PHASE
VDDP
LGATE
GND7PGND
RT8209MGQW _WQFN14_3P5X3P5
8
CS
PR804
2.2_0402_5%
1 2
UG_1.2V
13
LX_1.2V
12
TRIP_1.2V
11
10
LG_1.2V
9
BST1_1.2VBST_1.2V
1 2
PC807
0.1U_0402_10V7K
PR808
1 2
+5VALW
12
15K_0402_1%
+5VALW
PC809
4.7U_0805_10V6K
AO4406AL 1N SO8
PL802
HCB1608KF-121T30_0603
12
PC806
PC805
0.1U_0402_25V6
2200P_0402_50V7K
+
PC801
+1.2VS
1
2
B+
12
220U_D2_2VY_R15M
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2010/01/232009/01/23
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
+1.2VSP
NCL61 LA-6321P M/B
D
46 49Friday, April 29, 2011
0.1
of
5
PR202
10_0402_5%
PR204
10_0402_5%
12
12
D D
APU_VDDNB_RUN_FB_L8
APU_VDDNB_SEN8
+CPU_CORE_NB
PC231
0.01U_0402_16V7K
1 2
12
PC266
@330P_0402_50V7K
PC232
@330P_0402_50V7K
1 2
PLACE NEAR NB L-MOS
PR207
12
PC241
VR_ON32
8.06K_0402_1%
PC251
+CPU_CORE
PR208
2.37K_0402_1%
12
FB_NB_1
12
PR210
324_0402_1%
PH202_CPU
12
PC239
1000P_0402_50V7K
PR223 0_0402_5%
PR227 0_0402_5%
PR229 0_0402_5%
PR253 0_0402_5%
PR233 27.4K_0402_1%
PH202 470K_0402_5%_TSM0B474J4702RE
12
PR236
12
PR241
143K_0402_1%
1000P_0402_50V7K
PR239
324_0402_1%
12
2.43K_0402_1%
PC247
10_0402_5%
10_0402_5%
12
12
12
12
PR242
COMP_NB
VW_NB
NTC_CPU
FB_CPU_1
12
PR248
PR252
FB_NB
SDA
12
ALERT#
12
SCLK
12
12
12
PC252
12
1000P_0402_50V7K
12
12
+5VS
48
PU201
1
FB2_NB
2
FB_NB
3
COMP_NB
4
VW_NB
5
PGOOD_NB
6
SVD
7
PWROK
8
SVC
9
ENABLE
10
PGOOD
11
PROC_HOT
12
NTC
VW
13
VW_CPU
COMP_CPU
PC248 33P_0402_50V8J
1 2
FB_CPU
ISEN2
ISEN1
VSUM-
12
PC261
@330P_0402_50V7K
1 2
PC264
0.01U_0402_16V7K
PR209
100K_0402_1%
8.06K_0402_1%
PC236
470P_0402_50V7K
12
PR216
1 2
COMP_NB_1
12
PC238
100P_0402_50V8J
143K_0402_1%
12
1000P_0402_50V7K
1 2
Rfset(Kohm)=(Period(uS))-0.29)*2.65
C C
+3VS
12
APU_SVD8
12
PR221
100K_0402_5%
VGATE32
EC_THERM#8,13,32
@100K_0402_5%
PR225
APU_PWRGD_L13
APU_SVC8
PR232 3.83K_0402_1%
PLACE NEAR Phase1 L-MOS
B B
Rfset(Kohm)=(Period(uS))-0.29)*2.65
PR238
100K_0402_1%
12
470P_0402_50V7K
APU_VDD_SEN8
APU_VDD_RUN_FB_L8
A A
PC255
12
68P_0402_50V8J
COMP_CPU_1
44
45
46
RTN_NB
VSEN_NB
ISEN2_NB47ISEN1_NB
ISL6267HRZ-T_QFN48_6X6
ISEN3/FB216COMP
15
14
ISEN3_FB2_CPU
12
PC256
PC257
0.22U_0402_10V6K
12
PC263
@330P_0402_50V7K
4
12
12
PC234
PC233
0.1U_0402_10V7K
PH204
12
470K_0402_5%_TSM0B474J4702RE
1 2
27.4K_0402_1%
PR206
845_0402_1%
1 2
PR217
1 2
ISUMN_NB
PROG2
NTC_NB
43
41
42
PROG2
NTC_NB
ISUMP_NB
ISUMN_NB
VSEN
ISEN217FB
RTN20ISEN1
19
18
12
0.22U_0402_10V6K
PLACE NEAR NB choke
VSUMG+
12
PR203
12
4.02K_0402_1%
PR201
11K_0402_1%
0.047U_0402_16V7K
PR211
6.65K_0402_1%
BOOT1_NB
40
BOOT1_NB
ISUMN21VDD
ISUMN_CPU
NTC_NB_1
UGATE_NB
2.2_0603_5%
39
38
PH1_NB
UG1_NB
ISUMP
22
23
VIN_CPU
VDD_CPU
12
PC249 1U_0603_10V6K
PR244
976_0402_1%
PH203_NB
12
PH203
10K_0402_5%_ERTJ0ER103J
VSUMG-
12
PC235
0.1U_0603_50V7K
1 2
PR212
3.83K_0402_1%
PR215
BOOST1_NB1
12
37
LG1_NB
PWM2_NB
BOOT2
UG2
PH2
LG2
VCCP
PWM3
LG1
PH1
UG1
BOOT1
PROG1
VIN
TP
24
49
PR235
PR237
1_0603_5%
12
PC250
0.22U_0603_25V7K
12
PC258
0.22U_0402_16V7K
12
0.1U_0603_50V7K
36
35
34
33
32
31
30
29
28
27
26
25
12
0_0603_5%
12
12
PC259
PLACE NEAR Phase1 choke
PC240
BOOT2
UGATE2
PHASE2
LGATE2
6267_VCCP
PWM3
LGATE1
PHASE1
UGATE1
BOOT1
PROG1_CPU
+5VS
PR243
0.01U_0402_16V7K
0_0603_5%
12
PR224
1 2
0_0402_5%
1 2
6.65K_0402_1%
CPU_B+
12
11K_0402_1%
PR254
PR234
12
PH201_CPU
12
12
5
4
12
123
5
PQ206
4
123
LGATE_NB
+5VS
12
12
PR219
0_0603_5%
PR218
0_0402_5%
6267_VCCP1
BOOT2
12
PC245
1U_0603_10V6K
VSUM+
PR240
2.61K_0402_1%
PH201
10K_0402_5%_ERTJ0ER103J
VSUM-
PC262
0.1U_0603_50V7K
3
PQ205
TPCA8065-H_PPAK56-8-5
PHASE_NB
TPCA8059-H_PPAK56-8-5
PC237
680P_0402_50V7K
UGATE2
PHASE2
PR226
2.2_0603_5%
BOOT2_1
12
LGATE2
UGATE1
PHASE1
PR247
2.2_0603_5%
BOOT1
LGATE1
12
PR205
4.7_1206_5%
SNUB_NB
VSUMG+
12
VSUMG-
PR255
0_0603_5%
PC244
0.1U_0603_50V7K
0.1U_0603_50V7K
BOOT1_1
12
PC226
12
12
CPU_B+
12
12
12
PC225
PC228
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_25V7K
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PR213
3.65K_0805_1%
12
PR214
1_0402_1%
12
5
PQ203
4
TPCA8065-H_PPAK56-8-5
123
5
PQ204
4
123
TPCA8059-H_PPAK56-8-5
5
4
PC260
5
12
4
12
PC229
2200P_0402_50V7K
PL203
1
2
VSUMG+_1
12
PR228
4.7_1206_5%
SNUB_CPU2
PC246
12
680P_0402_50V7K
PQ201
TPCA8065-H_PPAK56-8-5
123
PQ202
123
TPCA8059-H_PPAK56-8-5
2
PL204
HCB2012KF-121T50_0805
1 2
PL205
HCB2012KF-121T50_0805
1 2
4
3
VSUMG-_1
CPU_B+
12
12
PC223
PC224
10U_0805_25V6K
10U_0805_25V6K
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
ISEN2
PR220
10K_0402_1%
VSUM+
3.65K_0805_1%
1_0402_1%
If the layout of each phase to CPU
is symmetric, the two res. can be
removed.
They are used for phase current
balance adjustment.
PC222
10U_0805_25V6K
12
PR249
4.7_1206_5%
SNUB_CPU1
PC265
12
680P_0402_50V7K
1
12
2
PR230
VSUM+_2
12
PR231
12
CPU_B+
12
12
12
PC254
PC221
10U_0805_25V6K
0.01U_0402_25V7K
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
ISEN1
PR245
10K_0402_1%
VSUM+
PR250
3.65K_0805_1%
PR251
1_0402_1%
VSUM-_2VSUM-
PC253
12
12
12
+CPU_CORE_N B
12
PC243
PC242
0.01U_0402_25V7K
PL202
4
3
12
2200P_0402_50V7K
1
2
VSUM+_1
VSUM-_1VSUM-
1
+
PC230
2
@68U_25V_M
12
2200P_0402_50V7K
PR222
1 2
10K_0402_1%
PL201
4
3
1
+
PC227
2
ISEN1
PR246
1 2
10K_0402_1%
1
B+
68U_25V_M
+CPU_CORE
ISEN2
Security Classification
Issued Date
THIS SHEET OF ENGINEERIN G DRAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010/11/11 2011/11/11
Compal Secret Data
Deciphered Dat e
2
Title
Size Docum ent Number Rev
Date: Sheet
Compal Electronics, Inc.
PWR_+CPU_CORE/+CPU_CORE_NB
PEQAE LA-7291P M/B
Friday, April 29, 2011
1
of
47 49
0.1
A
PL902
HCB2012KF-121T50_0805
1 2
1 1
B+
+3VS
PR905
10K_0402_1%
VGA_PWRGD13,25
PR908
1.5_VDD_PWREN25,38
2 2
3 3
Rtrip = 73.2K, OCP = 34.42A
1 2
0_0402_5%
1 2
1 2
73.2K_0402_1%
12
PC917
PU901
1
RF_VGA
PR911
470K_0402_1%
1 2
PGOOD
2
TRIP
3
EN
4
VFB
5
RF
RT8237CZQW(2) WDFN
PR901
TRIP_VGA DH_VGA
PR907
EN_VGA
FB_VGA
@.1U_0402_16V7K
Rrf = 470K, FSW = 290KHz
PR902
Whistler ProGPU VID1 GPU VID0
6.98K_0402_1%
VGA_B+
12
PC912
10U_0805_25V6K
VBST
DRVH
SW
V5IN
DRVL
TP
1 2
3.01K_0402_1%
12
12
PC911
10U_0805_25V6K
BST_VGA
10
9
LX_VGA
8
7
DL_VGA
6
11
+VGA_CORE1
B
12
PC913
@4.7U_0805_25V6-K
PR919 0_0603_5%
V5IN_VGA
0.1U_0402_25V6
PC914
12
PR906
BST1_VGA
1 2
2.2_0603_5%
12
PR909
1 2
0_0603_5%
1 2
PC919
2.2U_0603_6.3V6K
PR904
@10K_0402_1%
1 2
FB1_VGA
13
D
PQ904
S
@SSM3K7002FU_SC70-3
2200P_0402_50V7K
PC915
12
PC916
1 2
0.1U_0603_25V7K
+5VALW
GPU_VID1_1
2
G
12
TPCA8059-H_PPAK56-8-5
PR915
@5.1K_0402_1%
1 2
@10K_0402_5%
PC921
@.1U_0402_16V7K
PR916
PQ901
PQ902
+3VSG
1 2
1 2
5
4
5
4
PR913
@10K_0402_1%
GPU_VID119
SSM3K7002FU_SC70-3
C
PQ906
4
123
TPCA8065-H_PPAK56-8-5
PQ903
4
123
PR903
1 2
6.19K_0402_1%
FB0_VGA
13
D
2
G
S
PQ905
5
123
5
123
GPU_VID0_1
12
PC922
0.1U_0402_16V7K
@TPCA8065-H_PPAK56-8-5
0.36UH_PDME104T-R36MS0R825_37A_20%
TPCA8059-H_PPAK56-8-5
PR917
5.1K_0402_1%
1 2
PL901
1 2
12
PR910
@4.7_1206_5%
0.1U_0402_10V7K
SNUB_VGA
12
PC920
@680P_0402_50V7K
+3VSG
PR914
10K_0402_1%
PC918
1 2
PR918
@10K_0402_5%
1 2
D
+VGA_CORE
1
+
1 2
GPU_VID019
PC901
2
330U_D2_2V_Y
PR912
100_0402_1%
12
GCORE_SEN 21
XL
X
H
H 0.9V
L
1.0V
HH
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2007/05/29 200810/11
Compal Secret Data
Deciphered Date
C
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
VGA_CORE
LAXXXX
D
of
48 49Friday, April 29, 2011
0.1
5
4
3
2
Version change list (P.I.R. List) Power section Page 1 of 1
1
Item Reason for change PG# Modify List
Date Phase
1
2
D D
3
4
5
6
7
C C
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal S ecret Data
2008/09/15 2010/12/31
Deciphered Date
2
Compal Electronics, Inc.
Title
Changed-List History
Size Docume nt Numbe r Rev
Date: Sheet
QBL70 LA-7553P
of
49 51Friday, April 29, 2011
1
0.22
5
4
3
2
1
32:(56(48(1&(
$&,1%$77,1
9$/:
D D
9$/:
9$/:
(&B560567
57&B&/.
3%71B287
6/3B6
6/3B6
6<621
9
6863
C C
96
96
96
9696
9/'7B(1
96
9*$B21
B9''&B3:5(1
9*$B&25(96*
B B
96*96*
9*$B3:5*'
95B21
$38B&25($38B&25(B1%
7!PV
7$PV
7!QV
7!PV
'HOD\6/3B6
'HOD\6/3B6
'HOD\6863PV
'HOD\6863PV
$1'IURP9*$B213;B(1
7PV
7$!QV
FCH_PWRGD
96*WR96*SRZHUXS
9*$B21'HOD\PV
9*$7(
)&+B3:5*'
$38B3:5*'
A A
$B567
3/7B567
$38B567
5
7$PV
PV7PV
PV7$PV
PV7PV
7$QV
PV7&PV
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRO NICS, INC.
Compal Secret Data
2010/06/30 2012/06/30
Deciphered Date
2
7%PV
Title
Power Sequence
Size Document Number Rev
LA-7553P
Friday, April 29, 2011
Date: Sheet
1
50 51
of
0.22
5
4
3
2
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRIIRU+:
5HDVRQIRUFKDQJH 5HY 3* 0RGLI\/LVW 'DWH 3KDVH)L[HG,VVXH,WHP
1
D D
For PBL70 MEMO
For LED brightness.
For LED1 brightness. 0.11 PG#32 Change LED1 power to 3VALW 03/15 ER
For USB3.0 & AI charger 0.12 USBP0 connect to JUSB1 and USBP10 connect to JUSB2
For LED1 LED1 connect to +3VALW0.12
C C
B B
For AI charger 0.2 U2 reserve CEN# to EC
For AMD spec 0.2 R1642 & R1646 change to 4.7K ohm
For share ROM request 0.2
For +3VS leakage from CRT 0.21
For Crystal EA 0.21 Y4 change to SJ100007N00
For EMI ISN 0.22 C1636 change to 100P
For thermal team recommand 0.22 Add R1816,R1817 reserve R1814,R1815
For BRD ID 0.22 Change R1606 to 215K.
Reserve PX_EN signal 0.22 Reserve PX_EN signal to EC pin74
For JDIMM1 and JDIMM2 location definition 0.22 Swap JDIMM1 and JDIMM2 location
Prevent the leakage from CRT monitor. Add R1644, R1645, Q2 and Del R17, R31.0.23
for EMI request 0.23 H1 change to connect to GND
Don't use for MP 0.23 Unpop C1193
For VGA Sequence. 0.23 Change R1127 from 470 ohm to 33 ohm.
for EMI request modify USB3.0 redriver schemaitc
A A
For some HDMI device detect error 1.0 Change R200,R201 to 3.9K ohm 04/25 PRPG#28
0.11
0.11
0.11 PG#32 03/15 ER
0.2For +5VS rising time R1103 change to 47K
1.0
1.0For de-emphasis USB3.0 signal reserve TEST and I2C_EN net
1.0For WLAN module rising time specification Change R114 to 20K ohm C1663 change to 4700PPG#35 04/25 PR
Add U2 & U55For AI charge function
PG#34
PG#32
Change R1584 to 100 ohm.
Change R1586,R1588,R1591,R1592,R1593 to 100 ohm
PG#30
PG#35
PG#38
PG#30
PG#27
Unpop U28,R626,R935,R934,R35,C466
PG#15
Pop R910,unpop R921
PG#16
Add Q101,R1644,R1645
PG#27
Delete R17,R31
PG#13
PG#31
PG#19
PG#32
PG#32
PG#11
PG#12
PG#27
PG#31
PG#13
PG#38
PG#30
PG#30
03/15 ERPG#260.11For AMD reuqest Translator change to ANX3110
03/15
03/15Change LED1 to Green color.
03/22
03/22ERER
03/25
03/25
03/25
03/25
03/31
03/31PRPR
04/19
04/19
04/19
04/19
04/19 PR
04/22
04/22
04/22
04/22
04/25
04/25
ER
ER
ER
ER
ER
ER
PR
PR
PR
PR
PR
PR
PR
PR
PR
PR
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010/06/30 2012/06/30
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
HW-PIR
LA-7322P
1
51 51Friday, April 29, 2011
of
0.22
5
4
3
2
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRIIRU+:
5HDVRQIRUFKDQJH 5HY 3* 0RGLI\/LVW 'DWH 3KDVH)L[HG,VVXH,WHP
1
D D
Reduce the component count for MP.
04/25 PR1.0 Change below the footprints from 0 ohm to R short.
C C
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
HW-PIR3
QBL60 LA-7552P
1
53 53Friday, April 29, 2011
of
1.0
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