Compal LA-7551P QBL50, K43T, K43TA, K43TK, K43TY Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

QBL50 Schematics Document

AMD Sabine

APU Llano / Hudson M2_M

UMA only / PX

3 3

Muxless with BACO

3 / Vancouver Whistler

2011-04-25

Rev:1.0

4 4

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/

03/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal E

Cover Page

QB

L50 LA-7551P

lectronics, Inc.

153Wednesday, April 27, 2011

E

1.0

of

A

B

C

D

E

Com

Model Nam

1 1

pal Confidential

e : QBL50

VRAM 128M16 x 4/8

1G/2G

page 23, 24

Sabine

DDR3

hermal Sensor

T

AD

M1032

page 19

Vancuver Whistler

ATI

uF

CBGA-962

Page 18~22

8

GF

X x 4

APU HDMI (UMA / Muxless)

D

P x1 (DP0 T XP/N0)

Gen2GFX x

AMD FS1 APU

Llano

uP

GA-722 Package

Memory BUS(

D

ual Channel

1

.5V DDRIII 800~1333MHz

DDR3)

204pin DDRIII-SO-DIMM X

BANK 0, 1, 2, 3

Page 11,12

2

HDMI Conn.

page 28

LV

2 2

LVDS Conn.

DS

Reserve eDP

page 27

RT Conn.

C

page 27

3 3

avis LVDS

Tr Translator

page 26

MINI Ca WLAN

rd 1

page 32

F

CH CRT (VGA DAC)

GPP0GPP1

RJ

45

E)

page 29

LAN(Gb RTL8111E-VL

P_

GPP x 2

GEN1

DP (DP1 TXP/ N 0~4)

Hudson-M2/M3

CBGA-656

uF

Page 6~10

x 4

FCH

Page 13~17

UMI

LPC BUS

USB

B

US

3V 48MHz

3.

HD Au

dio

S-ATA

S

ATA HDD1

Conn.

page 33

USB

2/

2

USB3.0

page 34

Po

3.

Gen

page 34

Po

rt 0 Port 5

3V 24.576MHz/48Mhz

rt 10

2

port 0

2

USB (LS-7322P)

page 30

CMOS Ca

ODD C

onn.

page 33

mera

page 27

Po

rt2 Port 3

port 1

ni Card

Mi (with BT)

page 32

HDA Co ALC269

dec

page 30

C

ard Reader

RTS5137

page 31

Po

rt 4

ENE KB930

page 36

ouch Pad Int.KBD

T

LED

page 37

RTC CKT.

4 4

page 25

DC/DC Interface CKT

Po

wer Circuit

.

page 39

page 40~48

A

ernal board

Ext

L

S-7321P

Power/B

S-7322P

L Audio BD

page 35

page 30

BIOS ROM

EC BIOS

(2M)

B

page 35

page 38

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/

03/04 2011/12/31

page 38

pal Secret Data

Com

Deciphered Date

D

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

B

Date: Sheet

Compal E

B

lock Diagrams

QB

L50 LA-7551P

lectronics, Inc.

253Wednesday, April 27, 2011

E

of

1.0

5

4

3

2

1

CL

OCK DISTRIBUTION

MEM_MB_CLK1_P/N

MEM_MB_CLK7_P/N

AM

S1 SOCKET

_AUX

DP0

A_ SODIMM

MEM_MA_CLK1_P/N

MEM_MA_CL

1066~1600MHz

K7_P/N

D

U_DISP_CLKP/N

AP

100M

Hz

U_CLKP/N

AP

100M

Hz

AM

I VGA

AT

histler

W

AMD

FCH Huds

on-M2/M3

Internal CLK GEN

32.768KHz 25MHz

D

C

LK_PEG_VGAP/N

100M

Hz

PP_CLK

G

100M

Hz

D D

C C

B_ SODIMM

1066~1600MHz

CPU F

VDS Transtator

L

DISPLAY DISTRIBUTION

LVDS PATH

:

APU HDMI PATH

:

U_TXOUT[0:2]+/-

AP APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA

LVDS_OUT

R

TD2132

_IN

DP

TX

OUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA

VDS CONN

L

R

C

0_TXP/N[0:1]

DP

0_AUXP/N

DP

B B

W

LAN

PP1

G

Gb

Mini PCI Socket

E LAN

GPP0

AP

DP

DP0

U

PC

IE_GFX[0:7]

1

PCIE_GFX[12:15]

C

PC

IE_GFX[0:7]

VGA

25MHz

FC

H

LS

R

A A

HDM

I CONNCRT CONN

Security Classification

ssued Date

I

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/04 2011/12/31

C

ompal Secret Data

Deciphered Date

tle

Ti

CLOCK / DI

Size Document Number Rev

Custom

QBL50 LA-7551P

Date: Sheet

2

Date: Sheet

SPLAY DISTRIBUTION

1

1.0

of

353Wednesday, April 27, 2011

of

353Wednesday, April 27, 2011

of

353Wednesday, April 27, 2011

A

oltage Rails

V

Power Plane Description

VIN

B+

PU_CORE

+C

1 1

+C

PU_CORE_NB ON OFF OFF

+VGA_CORE OFFOFFON0.95-1.2V switched power rail

+0.75VS ONON OFF0.75V switc hed power rail f or DDR terminat or

+1.0VSG ON OFF OFF1.0V switched power rail for VGA

1ALW 1.1V switched power rail for FCH ON ON*ON

+1.

+1.1VS

+1.2VS ON OFF OFF

+1.5V ON

5VS

+1.

8VSG OFFON OFF1.8V switched power rail

+1.

+2.5VS

+3VALW

+LAN_IO ONONON

+3VS

+5VALW

+5VS

2 2

+VSB ON ON*

+R

TCVCC

ote : ON* means that t his power plane is ON only with A C power available, otherwise it is OFF .

N

Adapter power supply ( 19V)

AC or battery power rail for power circuit.

Core voltage for CPU

Vo

ltage for On-die VGA of A PU

1.2V switched power rail for APU

1

.5V power rail for CPU VDDIO and DDR

1.5V switched power rail

2.5V for CP U_VDDA

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

B

S3 S5

S1

N/A N/A N/A

ON OFF

ON OFF OFF1.1V switched power rail for FCH

ON OFF

ON

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON

ON*

OFF

OFFON

ONON

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

BTO Opt

ion Table

BTO ItemBOM Structure

V

GA@ Use VGA (Mux)

M2@ Use Hudson-M2

M3@ Use Hudson-M3

RAM ID TableX76@

V

C

SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH

HIGHHIGHHIGH

HIGH

LOW

HIGH

LOW

ON

OFF

ON

OFF

ON

M3@

F

P

BOM

D

ON

OFF

5

U2

CH M3

art Number = SA000043ID0

Config

E

ON

LOW

OFF

USB30@ USB30 on M/B

USB20@ USB20 on M/B

x =

1 is read cmd, x= 0 is writee cmd.

External

D

evice

3 3

E

C SM Bus1 address EC SM Bus2 address

D

evice Address HEX

Sm

FCH SM

4 4

D

evice Address Device Address

DDR DIMM1

DDR DI

PCI Devices

ID

SEL#

art Battery

0001 011X b

Bus 0 address

MM2

1101 000X b

1101 001X b

RE

Q#/GNT#

D

evice Address HEX

DI ADM1032 (VGA)

A

16H

(

APU)

TD2132S (TL)

R

I

nterrupts

1001 101X b

9A

H

FCH

Bus 1 address

SM

HE

X

D0

D2

A

HE

X

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal E

Notes List

QB

L50 LA-7551P

lectronics, Inc.

453Friday, April 29, 2011

E

1.0

of

5

BAT

TERY

12.6V

AC ADAPTO

D D

19V 90W

BATT+

R

VI

PU101 CHARGER

N

B+

C C

P

U201

ISL6267HRZ-T

P

U501

RT8209MGQW

PU801 RT8209MGQW

P

U901

RT8237CZQW

U701

P RT8209MGQW

U301

P RT8205LZQW

+3VS

+INVPWR_B+

D panel

LC

15.6"

B+ 300mA

+3.

3 350mA

FA

B B

N Control

APL5607

+

5VS 500mA

U54/U55 AP2301MPG

+USB_VCCA +USB_VCCB

+5VS

USB X3

+5

V

Dual+1

2.5A

SA

TA HDD*2 ODD*1

V 3A

+5

+3.3V

A A

A

udio Codec

ALC269-GR

+5V 45m

+3.3VS 25mA

4

+CPU_CORE

+CPU_CORE_NB

+1.5V

+1.2VS

+VGA_CORE

+1.1VALW

+3VALW

+5VALW

+3VS

+3VALW

EC ENE KB930

A

+3.3VALW 30mA +3.3VS 3mA

LA

N

RTL8111E

+3.3VALW 201mA

U3

3

SI4800

3

+1.5VS

M

ini Card

5VS 500mA

+1. +3.3VS 1A +3.3VALW 330mA

+2.5VS

PU603 APL5508-25DC

U4

0

SI4800

P

U602

APL5930KAI

U4

1

AO4430L

P

U401

SY8033BDBC

2

U601

P APL5336KAI

+1.0VSG

+1.5VSG

+1.8VSG

J14

P

U3

9

AO4430L

RTC Bettary

+0.75VS

+3VSG

+1.1VS

+CPU_CORE

+CPU_CORE_NB

+2.5VS

+1.5V

+1.2VS

+0.75VS

+VGA_CORE

+VDDCI

+1.0VSG

+1.5VSG

+1.8VSG

+3VSG

+1.1VS

+1.1VALW

+3VS

+3VALW

D APU FS1

AM

0.

7~1.475V

VDD CORE 54A

7~1.475V

0.

+2.5VS

+1.5V

+1.2VS

+1

+0.75VS

0.85~1.1V

0.

+1.

+1.5VSG

+1.8VSG

+3VSG

+1.1VS

+1.

+3VS

+3VALW

GND

VDDNB 27.5A

VDDA 500mA

VDDIO 4.6A

VDDR 6.7A

R

AM DDRIII SODIMM X2

VDD_

.5V

V

GA ATI

Whistler/Seymour/Granville

9~1.0V

0VSG

CH AMD Hudson M2/M3

F

1VALW

MEM 4A

TT_MEM 0.5A

V

VDDC 47A

VDDCI 4.6A

DPLL_VDDC: 125 mA SPV10: 120 mA PCIE_VDDC: 2000 mA D

P[A:E]_VDD10: 680 mA

3400 mA

VDDR1:

PLL_PVDD:

75 mA TSVDD: 20 mA AVDD: 70 mA VDD1DI: 100 mA VDD2DI: 50 mA A2VDDQ: 1.5 mA VDD_CT: 110 mA VDDR4: 170 mA PCIE_PVDD: 40 mA MPV18: 150 mA SPV18: 75 mA PCIE_VDDR: 400 mA DP[A:F]_VDD18: 920 mA DP[A:F]_PVDD: 120 mA

130 mA

A2VDD: VDDR3: 60 mA

VDDPL_11_DAC: 7 mA VDDAN_11_ML: 226 mA VDDCR_11: 1007 mA VDDAN_11_CLK: 340 mA VDDAN_11_PCIE: 1088 mA VDDAN_11_SATA: 1337 mA

VDDAN_11_USB_S: 140 mA VDDCR_11_USB_S: 197 mA VDDAN_11_SSUSB_S: 282 mA VDDCR_11_SSUSB_S: 424 mA VDDCR_11_S: 187 mA VDDPL_11_SYS: 70 mA

V

DDIO_33_PCIGP: 131 mA VDDPL_33_SYS: VDDPL_33_DAC: 20 mA VDDPL_33_ML: 20 mA VDDAN_33_DAC: 200 mA VDDPL_33_PCIE: 43 mA VDDPL_33_SATA: 93 mA VDDIO_AZ_S: 26 mA

VDDPL_33_SSUSB_S: 20 mA VDDPL_33_USB_S: 17 mA VDDAN_33_USB_S: 658 mA VDDIO_33_S: 59 mA VDDXL_33_S: 5 mA VDDAN_33_HWM_S: 12 mA

VDDIO_33_GBE_S

DDCR_11_GBE_S

V VDDIO_GBE_S

47 mA

VDDBT_RTC_GRTC BAT

1

RAM 1GB/2GB

V 64M / 128Mx16 * 4 / 8

5VSG 2.4 A

+1.

Security Classification

ssued Date

I

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M

M

AY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

AY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/04

Com

pal Secret Data

Deciphered Dat e

2

2011/12/31

Title

OWER DELIVERY CHART

P

Size Document Number Rev

Custom

QBL50 LA-7551P

Date: Sheet

1

553Wednesday, April 27, 2011

of

1.0

A

CIE_GTX_C_FRX_P[0..7]18

P

CIE_GTX_C_FRX_N[0..7]18

P

JC

PU1A

PCI EXPRESS

P

CIE_GTX_C_FRX_P0

CIE_GTX_C_FRX_N0

P

1 1

2 2

P

CIE_DTX_C_FRX_P029

CIE_DTX_C_FRX_N029

3 3

4 4

P

CIE_DTX_C_FRX_P132

CIE_DTX_C_FRX_N132

P

I_MTX_C_FRX_P013

UM

UMI_MTX_C_FRX_N013

I_MTX_C_FRX_P113

UM

I_MTX_C_FRX_N113

UM

I_MTX_C_FRX_P213

UM

I_MTX_C_FRX_N213

UM

I_MTX_C_FRX_P313

UM

I_MTX_C_FRX_N313

+1.2VS

CIE_GTX_C_FRX_P1

P

CIE_GTX_C_FRX_N1

P

CIE_GTX_C_FRX_P2

CIE_GTX_C_FRX_N2

P

CIE_GTX_C_FRX_P3

P

CIE_GTX_C_FRX_N3

P

CIE_GTX_C_FRX_P4

P

CIE_GTX_C_FRX_N4

P

CIE_GTX_C_FRX_P5

P

CIE_GTX_C_FRX_N5

CIE_GTX_C_FRX_P6

P

CIE_GTX_C_FRX_N6

P

CIE_GTX_C_FRX_P7

P

CIE_GTX_C_FRX_N7

1 2

R539 196_0402_1%R539 196_0402_1%

P_

ZVDDP

AA8

AA9

Y7

Y8

W5

W6

W8

W9

V7

V8

U5

U6

U8

U9

T7

T8

R5

R6

R8

R9

P7

P8

N5

N6

N8

N9

M7

M8

L5

L6

L8

L9

AC5

AC6

AC8

AC9

AB7

AB8

AA5

AA6

AF8

AF7

AE6

AE5

AE9

AE8

AD8

AD7

K5

AMD_TOPEDO_FS-1

GFX_RXP0

P_

GFX_RXN0

P_

GFX_RXP1

P_

GFX_RXN1

P_

GFX_RXP2

GFX_RXN2

P_

GFX_RXP3

GFX_RXN3

P_

GFX_RXP4

GFX_RXN4

P_

GFX_RXP5

P_

GFX_RXN5

GFX_RXP6

P_

GFX_RXN6

P_

GFX_RXP7

P_

GFX_RXN7

P_

GFX_RXP8

P_

GFX_RXN8

P_

GFX_RXP9

P_

GFX_RXN9

GFX_RXP10

P_

GFX_RXN10

P_

GFX_RXP11

P_

GFX_RXN11

GFX_RXP12

P_

GFX_RXN12

P_

GFX_RXP13

P_

GFX_RXN13

GFX_RXP14

P_

GFX_RXN14

P_

GFX_RXP15

P_

GFX_RXN15

P_

GPP_RXP0

P_

GPP_RXN0

P_

GPP_RXP1

P_

GPP_RXN1

GPP_RXP2

P_

GPP_RXN2

P_

P_GPP_RXP3

GPP_RXN3

P_

UMI_RXP0

P_

UMI_RXN0

P_UMI_RXP1

P_UMI_RXN1

UMI_RXP2

P_

UMI_RXN2

P_

UMI_RXP3

P_

UMI_RXN3

P_

P_ZVDDP

PCI EXPRESS

GPPUMI-LINK GRAPHICS

B

CONN@

GFX_TXP0

P_

GFX_TXN0

P_

GFX_TXP1

P_

GFX_TXN1

P_

GFX_TXP2

GFX_TXN2

P_

GFX_TXP3

GFX_TXN3

P_

GFX_TXP4

GFX_TXN4

P_

GFX_TXP5

P_

GFX_TXN5

GFX_TXP6

P_

GFX_TXN6

P_

GFX_TXP7

P_

GFX_TXN7

P_

GFX_TXP8

P_

GFX_TXN8

P_

GFX_TXP9

P_

GFX_TXN9

GFX_TXP10

P_

GFX_TXN10

P_

GFX_TXP11

P_

GFX_TXN11

GFX_TXP12

P_

GFX_TXN12

P_

GFX_TXP13

P_

GFX_TXN13

GFX_TXP14

P_

GFX_TXN14

P_

GFX_TXP15

P_

GFX_TXN15

P_

GPP_TXP0

P_

GPP_TXN0

P_

GPP_TXP1

P_

GPP_TXN1

GPP_TXP2

P_

GPP_TXN2

P_

P_GPP_TXP3

GPP_TXN3

P_

UMI_TXP0

P_

UMI_TXN0

P_UMI_TXP1

P_UMI_TXN1

UMI_TXP2

P_

UMI_TXN2

P_

UMI_TXP3

P_

UMI_TXN3

P_

P_ZVSS

AA2

AA3

Y2

Y1

Y4

Y5

W2

W3

V2

V1

V4

V5

U2

U3

T2

T1

T4

T5

R2

R3

P2

P1

P4

P5

N2

N3

M2

M1

M4

M5

L2

L3

AD4

AD5

AC2

AC3

AB2

AB1

AB4

AB5

AF1

AF2

AF5

AF4

AE3

AE2

AD1

AD2

K4

PC

IE_FTX_GRX_P0

IE_FTX_GRX_N0

PC

IE_FTX_GRX_P1

PC

IE_FTX_GRX_N1

PC

IE_FTX_GRX_P2

IE_FTX_GRX_N2

PC

IE_FTX_GRX_P3

PC

IE_FTX_GRX_N3

PC

IE_FTX_GRX_P4

PC

IE_FTX_GRX_N4

PC

IE_FTX_GRX_P5

PC

IE_FTX_GRX_N5

IE_FTX_GRX_P6

PC

IE_FTX_GRX_N6

PC

IE_FTX_GRX_P7

PC

IE_FTX_GRX_N7

P

CIE_FTX_GRX_P12

P

CIE_FTX_GRX_N12

P

CIE_FTX_GRX_P13

P

CIE_FTX_GRX_N13

CIE_FTX_GRX_P14

P

CIE_FTX_GRX_N14

P

CIE_FTX_GRX_P15

P

CIE_FTX_GRX_N15

P

IE_FTX_DRX_P0

PC

IE_FTX_DRX_N0

IE_FTX_DRX_P1

PC

IE_FTX_DRX_N1

I_FTX_MRX_P0

UM

I_FTX_MRX_N0

UM

I_FTX_MRX_P1

UM

I_FTX_MRX_N1

I_FTX_MRX_P2

UM

I_FTX_MRX_N2

UM

I_FTX_MRX_P3

UM

I_FTX_MRX_N3

UM

P_

ZVSS

1 2

R540 196_0402_1%R540 196_0402_1%

917 0.1U_0402_16V7KVGA@C917 0.1U_0402_16V7KVGA@

C

1 2

C

918 0.1U_0402_16V7KVGA@C918 0.1U_0402_16V7KVGA@

1 2

919 0.1U_0402_16V7KVGA@C919 0.1U_0402_16V7KVGA@

C

1 2

C

920 0.1U_0402_16V7KVGA@C920 0.1U_0402_16V7KVGA@

1 2

C

921 0.1U_0402_16V7KVGA@C921 0.1U_0402_16V7KVGA@

1 2

C

922 0.1U_0402_16V7KVGA@C922 0.1U_0402_16V7KVGA@

1 2

923 0.1U_0402_16V7KVGA@C923 0.1U_0402_16V7KVGA@

C

1 2

924 0.1U_0402_16V7KVGA@C924 0.1U_0402_16V7KVGA@

C

1 2

C

925 0.1U_0402_16V7KVGA@C925 0.1U_0402_16V7KVGA@

1 2

926 0.1U_0402_16V7KVGA@C926 0.1U_0402_16V7KVGA@

C

1 2

C

927 0.1U_0402_16V7KVGA@C927 0.1U_0402_16V7KVGA@

1 2

C

928 0.1U_0402_16V7KVGA@C928 0.1U_0402_16V7KVGA@

1 2

C

929 0.1U_0402_16V7KVGA@C929 0.1U_0402_16V7KVGA@

1 2

930 0.1U_0402_16V7KVGA@C930 0.1U_0402_16V7KVGA@

C

1 2

931 0.1U_0402_16V7KVGA@C931 0.1U_0402_16V7KVGA@

C

1 2

932 0.1U_0402_16V7KVGA@C932 0.1U_0402_16V7KVGA@

C

1 2

C

950 0.1U_0402_16V7K

1 2

C

951 0.1U_0402_16V7K

1 2

952 0.1U_0402_16V7K

C

1 2

953 0.1U_0402_16V7K

C

1 2

956 0.1U_0402_16V7K

C

1 2

957 0.1U_0402_16V7K

C

1 2

958 0.1U_0402_16V7K

C

1 2

959 0.1U_0402_16V7K

C

1 2

C

960 0.1U_0402_16V7K

1 2

C

961 0.1U_0402_16V7K

1 2

C

962 0.1U_0402_16V7K

1 2

963 0.1U_0402_16V7K

C

1 2

2

1

0

CK

C

To H

DMI

CIE_FTX_C_GRX_P[0..7] 18

P

CIE_FTX_C_GRX_N[0..7] 18

P

CIE_FTX_C_GRX_P0

CIE_FTX_C_GRX_N0

P

CIE_FTX_C_GRX_P1

P

CIE_FTX_C_GRX_N1

P

CIE_FTX_C_GRX_P2

CIE_FTX_C_GRX_N2

P

CIE_FTX_C_GRX_P3

P

CIE_FTX_C_GRX_N3

P

CIE_FTX_C_GRX_P4

P

CIE_FTX_C_GRX_N4

P

CIE_FTX_C_GRX_P5

P

CIE_FTX_C_GRX_N5

CIE_FTX_C_GRX_P6

P

CIE_FTX_C_GRX_N6

P

CIE_FTX_C_GRX_P7

P

CIE_FTX_C_GRX_N7

PC

IE_FTX_C_DRX_P0 29

IE_FTX_C_DRX_N0 29

PC

IE_FTX_C_DRX_P1 32

IE_FTX_C_DRX_N1 32

PC

MI_FTX_C_MRX_P0 13

U

UMI_FTX_C_MRX_N0 13

MI_FTX_C_MRX_P1 13

U

MI_FTX_C_MRX_N1 13

U

MI_FTX_C_MRX_P2 13

U

MI_FTX_C_MRX_N2 13

U

MI_FTX_C_MRX_P3 13

U

MI_FTX_C_MRX_N3 13

For U

GLA

WLAN

MA Mux.

N

D

APU To HDM

CP

U TSI interface level shift

+3V

S

31.6K_0402_1%

APU_

SID8,14

APU_

SIC8,14

Sequence of APU

Power

+1.

+2.5VS

+1.

+CPU_CORE

+CPU_CORE_NB

+1.2VS

R

535

1 2

SID

APU_

SH111 1N_SOT23-3

B

SIC

APU_

BSH111 1N_SOT23-3

5V

5VS

I

P

C

935 0.1U_0402_16V4Z

1 2

R

536

1 2

30K_0402_1%

G

2

Q9

C_SMB_DA

E

13

D

S

D

S

G

2

0

Q1

C_SMB_CK

E

13

D

S

D

S

P

CIE_FTX_GRX_P[12..15] 28

CIE_FTX_GRX_N[12..15] 28

BS

H111, the Vgs is: min = 0.4V Max = 1.3V

537

R

1 2

0_0402_5%

538

R

1 2

0_0402_5%

E

C_SMB_DA2 19,36

To

EC

E

C_SMB_CK2 19,36

Gr

oup A

Group B

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

A

MD FS1 PCIE / UMI / TSI

QB

L50 LA-7551P

lectronics, Inc.

653Wednesday, April 27, 2011

E

1.0

of

A

1 1

JC

PU1B

M

EMORY CHANNEL A

DDRA_

SMA[15..0]11

DDRA_

SBS0#11

DDRA_

SBS1#11 SBS2#11

DDRA_ DDRA_

SDM[7..0]11

2 2

SDQS011

DDRA_

SDQS0#11

DDRA_

SDQS111

DDRA_ DDRA_

SDQS1#11

DDRA_

SDQS211 SDQS2#11

DDRA_

SDQS311

DDRA_

SDQS3#11

DDRA_ DDRA_

SDQS411 SDQS4#11

DDRA_

SDQS511

DDRA_ DDRA_

SDQS5#11 DDRA_SDQS611 DDRA_

SDQS6#11

SDQS711

DDRA_

SDQS7#11

DDRA_

CLK011

CLK0#11

DDRA_

CLK111

DDRA_ DDRA_

CLK1#11

DDRA_

CKE011

CKE111

DDRA_

ODT011

ODT111

DDRA_

SCS0#11

3 3

DDRA_ DDRA_

DDRA_ DDRA_ DDRA_

M_MA_RST#11

ME M

EM_MA_EVENT#11

SCS1#11

SRAS#11

SCAS#11

SWE#11

+M

EM_VREF

5V

+1.

Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#

Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#

DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_

SBS0#

DDRA_ DDRA_

SBS1#

DDRA_

SBS2#

DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_

DDRA_ DDRA_ DDRA_ DDRA_ DDRA_SDQS2 DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_ DDRA_

CLK0

DDRA_ DDRA_

CLK0# CLK1

DDRA_

CLK1#

DDRA_

DDRA_CKE0 DDRA_

CKE1

ODT0

DDRA_

ODT1

DDRA_

SCS0#

DDRA_

SCS1#

DDRA_

SRAS#

DDRA_

SCAS# SWE#

DDRA_

ME

M_MA_RST#

M

EM_MA_EVENT#

1 2

541 39.2_0402_1%

R

SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMA13 SMA14 SMA15

SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7

SDQS0 SDQS0# SDQS1 SDQS1#

SDQS2# SDQS3 SDQS3# SDQS4 SDQS4# SDQS5 SDQS5# SDQS6 SDQS6# SDQS7 SDQS7#

15m

M_ZVDDIO

il

U20

M

R20

M

R21

M

P22

M

P21

M

N24

M

N23

M

N20

M

N21

M

M21

M

U23

M

M22

M

L24

M

AA25

M

L21

M

L20

M

U24

M

U21

M

L23

M

E14

MA

J17

MA

E21

MA

F25

MA

AD27

MA

AC23

MA

AD19

MA

AC15

MA

G14

M

H14

M

G18

M

H18

M

J21

M

H21

M

E27

M

E26

M

AE26

M

AD26

M

AB22

M

AA22

M

AB18

M

AA18

M

AA14

M

AA15

M

T21

M

T22

M

R23

M

R24

M

H28

M

H27

M

Y25

MA

AA27

MA

V22

M

AA26

M

V21

M

W24

M

W23

MA

H25

M

T24

M

W20

M

W21

M_ZVDDIO

AMD_TOPEDO_FS-1

EMORY CHANNEL A

A_ADD0 A_ADD1 A_ADD2 A_ADD3 A_ADD4 A_ADD5 A_ADD6 A_ADD7 A_ADD8 A_ADD9 A_ADD10 A_ADD11 A_ADD12 A_ADD13 A_ADD14 A_ADD15

A_BANK0 A_BANK1 A_BANK2

_DM0 _DM1 _DM2 _DM3 _DM4 _DM5 _DM6 _DM7

A_DQS_H0 A_DQS_L0 A_DQS_H1 A_DQS_L1 A_DQS_H2 A_DQS_L2 A_DQS_H3 A_DQS_L3 A_DQS_H4 A_DQS_L4 A_DQS_H5 A_DQS_L5 A_DQS_H6 A_DQS_L6 A_DQS_H7 A_DQS_L7

A_CLK_H0 A_CLK_L0 A_CLK_H1 A_CLK_L1

A_CKE0 A_CKE1

_ODT0 _ODT1

A_CS_L0 A_CS_L1

A_RAS_L A_CAS_L

_WE_L

A_RESET_L A_EVENT_L

_VREF

CONN@

M

A_DATA0

M

A_DATA1

M

A_DATA2 A_DATA3

M

A_DATA4

M M

A_DATA5

M

A_DATA6 A_DATA7

M

A_DATA8 A_DATA9

M

A_DATA10 A_DATA11

M

A_DATA12

M M

A_DATA13 A_DATA14

M

A_DATA15

M

A_DATA16 A_DATA17

M

A_DATA18

M

A_DATA19

M

A_DATA20

M M

A_DATA21 A_DATA22

M M

A_DATA23

M

A_DATA24 A_DATA25

M

A_DATA26

M M

A_DATA27 A_DATA28

M M

A_DATA29 A_DATA30

M M

A_DATA31

M

A_DATA32 A_DATA33

M

A_DATA34

M M

A_DATA35 A_DATA36

M M

A_DATA37 A_DATA38

M M

A_DATA39

A_DATA40

M

A_DATA41

M

A_DATA42

M M

A_DATA43 A_DATA44

M M

A_DATA45 A_DATA46

M M

A_DATA47

A_DATA48

M M

A_DATA49 A_DATA50

M M

A_DATA51 A_DATA52

M M

A_DATA53

M

A_DATA54

M

A_DATA55

A_DATA56

M M

A_DATA57 A_DATA58

M M

A_DATA59 MA_DATA60 M

A_DATA61

A_DATA62

M MA_DATA63

B

DDRA_

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_

SDQ0 SDQ1

DDRA_ DDRA_

SDQ2 SDQ3

DDRA_

SDQ4

DDRA_ DDRA_

SDQ5 SDQ6

DDRA_ DDRA_

SDQ7

DDRA_

SDQ8

DDRA_

SDQ9

DDRA_

SDQ10 SDQ11

DDRA_

SDQ12

DDRA_ DDRA_

SDQ13 SDQ14

DDRA_ DDRA_

SDQ15

DDRA_

SDQ16

DDRA_

SDQ17 SDQ18

DDRA_

SDQ19

DDRA_

SDQ20

DDRA_ DDRA_

SDQ21 SDQ22

DDRA_ DDRA_

SDQ23

DDRA_

SDQ24

DDRA_

SDQ25 SDQ26

DDRA_ DDRA_

SDQ27 SDQ28

DDRA_ DDRA_

SDQ29 SDQ30

DDRA_ DDRA_SDQ31

DDRA_

SDQ32

DDRA_

SDQ33 SDQ34

DDRA_ DDRA_

SDQ35 SDQ36

DDRA_ DDRA_

SDQ37 SDQ38

DDRA_ DDRA_

SDQ39

SDQ40

DDRA_ DDRA_

SDQ41 SDQ42

DDRA_ DDRA_

SDQ43 SDQ44

DDRA_

SDQ45

DDRA_

SDQ46

DDRA_ DDRA_SDQ47

SDQ48

DDRA_

SDQ49

DDRA_

SDQ50

DDRA_ DDRA_

SDQ51 SDQ52

DDRA_

SDQ53

DDRA_ DDRA_

SDQ54

DDRA_

SDQ55

SDQ56

DDRA_

SDQ57

DDRA_ DDRA_

SDQ58

DDRA_

SDQ59 SDQ60

DDRA_ DDRA_

SDQ61 SDQ62

DDRA_ DDRA_

SDQ63

SDQ[63..0] 11

C

DDRB_

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDQS612 DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_

DDRB_ DDRB_ DDRB_

M_MB_RST#12

ME M

EM_MB_EVENT#12

SMA[15..0]12

SBS0#12 SBS1#12 SBS2#12 SDM[7..0]12

SDQS012 SDQS0#12 SDQS112 SDQS1#12 SDQS212 SDQS2#12 SDQS312 SDQS3#12 SDQS412 SDQS4#12 SDQS512 SDQS5#12

SDQS6#12 SDQS712 SDQS7#12

CLK012 CLK0#12 CLK112 CLK1#12

CKE012 CKE112

ODT012 ODT112

SCS0#12 SCS1#12

SRAS#12 SCAS#12 SWE#12

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDQS2 DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_CKE0 DDRB_

DDRB_ DDRB_

DDRB_ DDRB_ DDRB_

ME

M_MB_RST#

M

EM_MB_EVENT#

SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMA13 SMA14 SMA15

SBS0# SBS1# SBS2#

SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7

SDQS0 SDQS0# SDQS1 SDQS1#

SDQS2# SDQS3 SDQS3# SDQS4 SDQS4# SDQS5 SDQS5# SDQS6 SDQS6# SDQS7 SDQS7#

CLK0 CLK0# CLK1 CLK1#

CKE1

ODT0 ODT1

SCS0# SCS1#

SRAS# SCAS# SWE#

D

T27 P24 P25 N27 N26 M28 M27 M24 M25

L26

U26

L27

K27

W26

K25 K24

U27 T28 K28

D14 A18 A22 C25

AF25 AG22 AH18 AD14

C15 B15 E18 D18 E22 D22 B26

A26 AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

R26

R27

P27

P28

J26 J27

W27

Y28

V25

Y27

V24

V27

V28

J25

T25

JC

PU1C

M

EMORY CHANNEL B

M

B_ADD0

M

B_ADD1

M

B_ADD2 B_ADD3

M

B_ADD4

M M

B_ADD5

M

B_ADD6 B_ADD7

M

B_ADD8

M M

B_ADD9 B_ADD10

M M

B_ADD11 B_ADD12

M

B_ADD13

M M

B_ADD14 B_ADD15

M

B_BANK0

M M

B_BANK1 B_BANK2

M

_DM0

MB

_DM1

MB MB

_DM2 _DM3

MB MB

_DM4 _DM5

MB MB

_DM6 _DM7

MB

M

B_DQS_H0 B_DQS_L0

M M

B_DQS_H1 B_DQS_L1

M M

B_DQS_H2

M

B_DQS_L2

M

B_DQS_H3 B_DQS_L3

M

B_DQS_H4

M M

B_DQS_L4 B_DQS_H5

M M

B_DQS_L5 B_DQS_H6

M M

B_DQS_L6

M

B_DQS_H7 B_DQS_L7

M

B_CLK_H0

M M

B_CLK_L0 B_CLK_H1

M M

B_CLK_L1

M

B_CKE0

M

B_CKE1

MB

_ODT0 _ODT1

MB

B_CS_L0

M M

B_CS_L1

M

B_RAS_L

M

B_CAS_L

_WE_L

MB

B_RESET_L

M M

B_EVENT_L

AMD_TOPEDO_FS-1

CONN@

M

B_DATA0

M

B_DATA1

M

B_DATA2 B_DATA3

M

B_DATA4

M M

B_DATA5

M

B_DATA6 B_DATA7

M

B_DATA8 B_DATA9

M

B_DATA10 B_DATA11

M

B_DATA12

M M

B_DATA13 B_DATA14

M

B_DATA15

M

B_DATA16 B_DATA17

M

B_DATA18

M

B_DATA19

M

B_DATA20

M M

B_DATA21 B_DATA22

M M

B_DATA23

M

B_DATA24 B_DATA25

M

B_DATA26

M M

B_DATA27 B_DATA28

M M

B_DATA29 B_DATA30

M M

B_DATA31

M

B_DATA32 B_DATA33

M

B_DATA34

M M

B_DATA35 B_DATA36

M M

B_DATA37 B_DATA38

M M

B_DATA39

B_DATA40

M

B_DATA41

M

B_DATA42

M M

B_DATA43 B_DATA44

M M

B_DATA45 B_DATA46

M M

B_DATA47

B_DATA48

M M

B_DATA49 B_DATA50

M M

B_DATA51 B_DATA52

M M

B_DATA53

M

B_DATA54

M

B_DATA55

B_DATA56

M M

B_DATA57 B_DATA58

M M

B_DATA59 MB_DATA60 M

B_DATA61

B_DATA62

M MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_

SDQ0 SDQ1

DDRB_ DDRB_

SDQ2 SDQ3

DDRB_

SDQ4

DDRB_ DDRB_

SDQ5 SDQ6

DDRB_ DDRB_

SDQ7

DDRB_

SDQ8

DDRB_

SDQ9

DDRB_

SDQ10 SDQ11

DDRB_

SDQ12

DDRB_ DDRB_

SDQ13 SDQ14

DDRB_ DDRB_

SDQ15

DDRB_

SDQ16

DDRB_

SDQ17 SDQ18

DDRB_

SDQ19

DDRB_

SDQ20

DDRB_ DDRB_

SDQ21 SDQ22

DDRB_ DDRB_

SDQ23

DDRB_

SDQ24

DDRB_

SDQ25 SDQ26

DDRB_ DDRB_

SDQ27 SDQ28

DDRB_ DDRB_

SDQ29 SDQ30

DDRB_ DDRB_SDQ31

DDRB_

SDQ32

DDRB_

SDQ33 SDQ34

DDRB_ DDRB_

SDQ35 SDQ36

DDRB_ DDRB_

SDQ37 SDQ38

DDRB_ DDRB_

SDQ39

SDQ40

DDRB_ DDRB_

SDQ41 SDQ42

DDRB_ DDRB_

SDQ43 SDQ44

DDRB_

SDQ45

DDRB_

SDQ46

DDRB_ DDRB_SDQ47

SDQ48

DDRB_

SDQ49

DDRB_

SDQ50

DDRB_ DDRB_

SDQ51 SDQ52

DDRB_

SDQ53

DDRB_ DDRB_

SDQ54

DDRB_

SDQ55

SDQ56

DDRB_

SDQ57

DDRB_ DDRB_

SDQ58

DDRB_

SDQ59 SDQ60

DDRB_ DDRB_

SDQ61 SDQ62

DDRB_ DDRB_

SDQ63

E

DDRB_

SDQ[63..0] 12

ENT# pull high 0.75V reference voltage

EV

5V

+1.

4 4

EM_MA_EVENT#

544 1K_0402_5%

R

1 2

R545 1K_0402_5%R545 1K_0402_5%

1 2

M

EM_MB_EVENT#

A

R542

1K_0402_1%

R543

1K_0402_1%

+1.5V

1 2

B

1

C964

1000P_0402_50V7K

2

15m

+M

EM_VREF

2

C

965

0.1U_0402_16V7K

1

il

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

A

MD FS1 DDRIII I/F

QB

L50 LA-7551P

lectronics, Inc.

753Wednesday, April 27, 2011

E

1.0

of

A

P

lace near APU

971 0.1U_0402_16V7K

C

To LVD

S

Translator

1 1

T

o FCH VGA ML

100MHz

2 2

100MHz_NSS

+1.

5V

R

575 1K_0402_5%

576 1K_0402_5%

R

+1.

5V

3 3

579 1K_0402_5%

R

581 1K_0402_5%

R

791 1K_0402_5%

R

+1.

5V

R592 1K_0402_5%R592 1K_0402_5%

R593 1K_0402_5%R593 1K_0402_5%

594 1K_0402_5%

R

595 1K_0402_5%

R

596 300_0402_5%

R

ute as differentia l

Ro with VSS_SENSE

APU_VDDNB_RUN_FB_L APU_VDDNB_SEN route as differential

4 4

APU_VDD_RUN_FB_L APU_VDD_SE N route as differential

C 20101111

1 2

Close to Header

1 2

P0_TXP0_C26

D

P0_TXN0_C26

D

L_VGA_TXP015

M

L_VGA_TXN015

M

L_VGA_TXP115

L_VGA_TXN115

M

L_VGA_TXP215

M

L_VGA_TXN215

M

L_VGA_TXP315

M

L_VGA_TXN315

A

PU_CLKP13

PU_CLKN13

A

APU_

DISP_CLKP13

DISP_CLKN13

APU_

SVC47

APU_

SVD47

APU_

hang to PU +1.5VS (DG ref. )

APU_SVC

APU_

ERT_L

AL

APU_

VDDNB_RUN_FB_L47

APU_

A

SVD

SIC

SID

TDI

TCK

TMS

TRST#

DBREQ#

VDD_RUN_FB_L47

1 2

973 0.1U_0402_16V7K

C

1 2

T25T25

T28T28

T19T19

T20T20

T21T21

T22T22

P

lace near APU

977 0.1U_0402_16V7K

C

1 2

C

968 0.1U_0402_16V7K

1 2

969 0.1U_0402_16V7K

C

1 2

970 0.1U_0402_16V7K

C

1 2

C

978 0.1U_0402_16V7K

1 2

979 0.1U_0402_16V7K

C

1 2

C

980 0.1U_0402_16V7K

1 2

C

981 0.1U_0402_16V7K

1 2

CLKP

APU_

CLKN

APU_

DISP_CLKP

APU_

DISP_CLKN

APU_

SVC

APU_

SVD

SIC6,14

APU_

TSI

APU_SID6,14

APU_

RST#13

PWRGD13

APU_

rial VID

Se

APU_

VDDNB_SEN47

APU_

VDD_SEN47

R

597 0_0402_5%

1 2

R

600 0_0402_5%

1 2

APU_

AL

APU_

ERT_L

DP0

D

DP0

D

DP0

D

DP0

D

DP1

D

DP1

D

DP1

D

DP1

D

SIC

SID

RST#

PWRGD

PROCHOT#

THERMTRIP#

TDI

TDO

TCK

TMS

TRST#

DBRDY

DBREQ#

VDDNB_SEN

VDD_SEN

_TXP0

P0_TXN0

_TXP1

P0_TXN1

_TXP2

P0_TXN2

_TXP3

P0_TXN3

_TXP0

P1_TXN0

_TXP1

P1_TXN1

_TXP2

P1_TXN2

_TXP3

P1_TXN3

B

PU1D

JC

F2

DP0

F1

D

E3

DP0

E2

D

D2

DP0

D1

D

C2

DP0

C3

D

K2

DP1

K1

D

J3

DP1

J2

D

H2

DP1

H1

D

G2

DP1

G3

D

AH7

CL

AH6

CL

AH4

DI

AH3

DI

B8

SVC

A8

SVD

AH11

SI

AG11

SI

AF10

RESET_

AE10

PW

AD10

PRO

AG12

THERM

AH12

AL

C12

TD

A12

TD

A11

TC

D12

TM

B12

TRST_L

1

B1

DBRDY

C11

DBREQ

E8

RSVD_

K21

RSVD_2

AC11

RSVD_3

B9

VSS_

C8

VDDP_

A9

VDDNB_

B10

VDDI

C9

VDD_

A10

VDDR_

AMD_TOPEDO_FS-1

B

_TXP0

P0_TXN0

_TXP1

P0_TXN1

_TXP2

P0_TXN2

_TXP3

P0_TXN3

_TXP0

P1_TXN0

_TXP1

P1_TXN1

_TXP2

P1_TXN2

S

_TXP3

P1_TXN3

KIN_H

KIN_L

SP_CLKIN_H

SP_CLKIN_L

C

D

L

ROK

CHOT_L

TRIP_L

ERT_L

I

O

K

S

_L

1

SENSE

O_SENSE

SENSE

DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE

ystem DP

CONN@

_AUXP

DP0

_AUXN

_AUXP

DP1

_AUXN

DP1

DP2

_AUXP

_AUXN

DP2

DP3

_AUXP

_AUXN

DP3

DP4

_AUXP

_AUXN

DP4

_AUXP

DP5

_AUXN

P0_HPD

D

P1_HPD

P2_HPD

D

P3_HPD

P4_HPD

D

P5_HPD

D

DP_

BLON

D

P_DIGON

VARY_BL

DP_

AUX_ZVSS

TEST6

TEST9

TEST10

TEST12

TEST14

TEST15

TEST16

TEST17

TEST18

TEST19

TEST20

TEST21

TEST DISPLAY PORT MISC.

TEST22

TEST23

TEST24

TE

ST25_H

TE

ST25_L

TEST28_H

TEST28_L

TEST30_H

ST30_L

TE

TEST31

ST32_H

TE

ST32_L

TEST35

FS1R1

DMAACTIVE_L

THERM

DA

THERM

DC

C

Place near APU

_AUXP

DP0

D4

DP0

D5

L_VGA_AUXP

M

E5

M

L_VGA_AUXN

E6

J5

J6

H4

H5

G5

G6

APU_

F4

APU_

F5

D7

E7

J7

H7

G7

F7

C6

C5

C7

D8

AA1

0

G1

0

H1

2

H1

D9

E9

G9

H9

H1

1

G1

F12

1

E1

D1

1

F10

G1

2

AH10

AH9

K7

K8

AA12

AB12

2

K2

AB11

AA11

D1

0

Y11

AB10

AE12

AD12

Llano do not support this thermal die

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

_AUXN

HDMI_CLK

HDMI_DATA

P0_HPD

D

P1_HPD

P5_HPD

D

DP_

ENBKL

DP_

ENVDD

INT_PWM

DP_

AUX_ZVSS

APU_TEST18

TEST19

APU_

TEST20

APU_

TEST21

APU_

TEST22

TEST24

APU_

TE

ST25_H

TE

ST25_L

_TEST

M

TEST35

FS1R

1

A

LLOW_STOP

T6T6

T7T7

T8T8

T9T9

T10T10

T11T11

T12T12

T13T13

T14T14

T15T15

T16T16

C

972 0.1U_0402_16V7K

C

1 2

974 0.1U_0402_16V7K

C

1 2

C

975 0.1U_0402_16V7K

1 2

976 0.1U_0402_16V7K

C

1 2

HDMI_CLK 28

APU_

HDMI_DATA 28

P0_HPD 10

D

P1_HPD 10

D

P5_HPD 10

D

P_ENBKL 10

DP_

ENVDD 10

D

P_INT_PWM 10

R

569 150_0402_1%

1 2

hang to unpop (DG ref.)

C 20101111

R

573 0_0402_5%@

1 2

574 1K_0402_5%

R

1 2

R

582 1K_0402_5%

1 2

583 1K_0402_5%

R

1 2

584 1K_0402_5%

R

1 2

585 1K_0402_5%

R

1 2

R

589 1K_0402_5%

1 2

R

590 1K_0402_5%

1 2

ALLOW_STOP 13

C

639 0.1U_0402_16V4Z

1 2

@

2010/

08/04 2011/12/31

LVDS

CRT

_AUXP_C 26

DP0

_AUXN_C 26

DP0

M

L_VGA_AUXP_C 15

L_VGA_AUXN_C 15

M

2~5 are for GFX interface

AUX use, they could be selected to I2C or AUX logic

VDDIO level Need Level shift

I

HDM

V

DDIO level

Need Level shift

H

DT Debug conn

TRST#

APU_

R

pal Secret Data

Com

Deciphered Date

D

To LVD

S

Translator

To FCH

Asserted as an input to force the processor into the HTC-active state

APU_

TH

ERMTRIP shutdown

temperature: 125 degree

APU_

5V

+1.

598 0_0402_5%

R

1 2

601 10K_0402_5%

1 2

603 10K_0402_5%

1 2

605 10K_0402_5%

1 2

D

PROCHOT#

THERMTRIP#

E

I

f not used, pins are left unconnected (DG ref.)

20101111

_AUXP

DP0

M

L_VGA_AUXP

L_VGA_AUXN

M

TEST25_L

TEST25_H

TEST35

_TEST

M

FS1R

FS1R In laptop, seems no use

A

LLOW_STOP

MI

5V

+1.

R

R 1K_0402_5%

1K_0402_5%

1 2

R

591 0_0402_5%

+1.

5V

R

610

1K_0402_5%

1 2

MMBT3904_NL_SOT23-3

1

JP

1

3

5

7

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

CONN@

Title

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

APU_

SC

APU_PWRGD

586

1 2

E

3 1

2

4

6

8

10K_0402_5%

Indicates to the FCH that a thermal trip

12

has occurred. Its assertion will cause th e FCH to transition the system to S5 immediately

609

R

10K_0402_5%

B

2

Q1

2

C

R

APU_TCK

2

APU_TMS

4

APU_

6

APU_

8

10

12

APU_

14

APU_

16

R

606 0_0402_5%

1 2

18

R

608 0_0402_5%

1 2

20

Compal E

AM

D FS1 Display / MISC / HDT

QB

L50 LA-7551P

554 1.8K_0402_5%

R

_AUXN

1

1 : Control S5 Dual PWR plane

RST#

R

1

Q1

MMBT3904_NL_SOT23-3

1 2

611 0_0402_5%

TDI

TDO

R

DBRDY

DBREQ#

R

555 1.8K_0402_5%

547 1.8K_0402_5%

R

556 1.8K_0402_5%

548 510_0402_1%

R

1 2

R

557 510_0402_1%

1 2

R

558 300_0402_5%

1 2

559 300_0402_5%@

R

1 2

564 39.2_0402_1%@

R

1 2

R

567 39.2_0402_1%

1 2

571 10K_0402_5%

R

1 2

612 1K_0402_5%

R

1 2

R

577 1K_0402_5%

1 2

@

R

578 300_0402_5%

1 2

R

580 300_0402_5%

1 2

S

+3V

12

R

587

10K_0402_5%

2

B

E

31

C

ut on CPU side, Debug mount

C

599 0_0402_5%@R599 0_0402_5%@

1 2

602 0_0402_5%@R602 0_0402_5%@

1 2

lectronics, Inc.

E

588

APU_

12

E

C_THERM# 13,36,47

THERMTRIP# 14

H_

TEST19

TEST18

853Wednesday, April 27, 2011

APU_

of

+1.

3VALW

+

+1.

PWRGD

RST#

2VS

5V

5VS

1.0

A

C

Power Name

D

VD +C

PU_CORE

DDNB

V +CPU_CORE_NB

V

DDIO

+1.5V

DDP / VDDR

V +1.

2VS

DDA

V

1 1

+2.5VS

CORE_NB 330uF X 2 22uF X 4

2 2

3 3

5VS

+2.

4 4

onsumption

50A

22.

5A

4A

/ 3.5A

3A

75A

0.

U_CORE

CP 330uF X 4 22uF X 11

L1

L1 FB

FB

MA-L11-201209-221LMA30T_0805

12

3300P_0402_50V7K

C

1040

1041

12

A

+

CPU_CORE_NB

5V

+1.

2VS

+1.

2VS

+1.

VDDA_APU

+

4.7U_0805_10V4Z

0.22U_0603_16V4Z

0.22U_0603_16V4Z C1

C1

1

8

2

18 & C1043 follow AMD request

C 201012061900

JC

PU1E

C1

VDD

D3

VDD

D6

VDD

E1

VDD

F3

VDD

F6

VDD

F8

VDD

G1

VDD

H3

VDD

H6

VDD

H8

VDD

J1

VDD

K3

VDD

K6

VDD

L1

VDD

L11

VDD

L19

VDD

M3

VDD

M6

VDD

0

M1

VDD

M1

8

VDD

N1

VDD

1

N1

VDD

9

N1

VDD

P3

VDD

P6

VDD

0

P1

VDD

8

P1

VDD

R1

VDD

R1

1

VDD

9

R1

VDD

T3

VDD

J9

VDDNB

J10

VDDNB

J11

VDDNB

J12

VDDNB

J14

VDDNB

J16

VDDNB

K9

VDDNB

K1

0

VDDNB

G28

O

VDDI

H26

VDDI

O

J28

O

VDDI

K20

VDDI

O

K23

O

VDDI

K26

VDDI

O

L22

VDDI

O

L25

O

VDDI

L28

O

VDDI

M20

O

VDDI

M23

VDDI

O

M26

O

VDDI

N22

VDDI

O

N25

O

VDDI

N28

VDDI

O

P20

VDDI

O

P23

O

VDDI

P26

VDDI

O

AG2

DDP_A_1

V

AG3

V

DDP_A_2

AG4

V

DDP_A_3

AG5

V

DDP_A_4

AG

6

VDDR

7

AG

VDDR

AG

8

VDDR

AG9

VDDR

il

AE11

VDDA

AF11

VDDA

AMD_TOPEDO_FS-1

Keep trace from resistor to APU within 0.6"

Keep trace from Caps to APU within 1.2"

C

C 1043

1043

+C

1

2

PU_CORE

40m

180P_0402_50V8J

@

VDDP_ VDDP_ VDDP_ VDDP_

CONN@

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI

VDDR VDDR VDDR VDDR

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

B

CPU BOTTOM

PU_CORE

+C

C

22U_0805_6.3V6M

982

C7

C

C 1045

1045

C

C 1053

1053

1

2

1

2

1

2

CPU_CORE_NB

+

+1.

10U

_0603_6.3V6M

C6

1

2

180P_0402_50V8J

C

C 1046

1046

1

2

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 1054

1054

1

2

982

C

C 1000

1000

C

C 1012

1012

C

C 1027

1027

10U

_0603_6.3V6M

180P_0402_50V8J

0.22U_0603_16V4Z

1

2

22U_0805_6.3V6M

1

2

5V

22U_0805_6.3V6M

1

2

5V

0.22U_0603_16V4Z

1

2

C

C 1034

1034

1

2

C

C 1047

1047

1

2

C

C 1055

1055

1

2

2000mil2000mil

PU_CORE

+C

T6 T10 T18 U1

1

U1

9

U1 V3 V6 V1

0 8

V1 W1 W1

1

W1

3 5

W1

7

W1 W1

9 Y3 Y6

0

Y1

2

Y1 Y1

4 6

Y1

8

Y1

0

Y2 AA1 AB3 AB6 AC1 AD3 AD6 AE1

900mil900mil

1

K1

2

K1 K1

3 4

K1 K1

6 7

K1 K1

8

L18

160mil160mil

R22

O

R25

O

R28

O

T20

O

T23

O

T26

O

U22

O

U25

O

U28

O

V20

O

V23

O

V26

O

W22

O

W25

O

W28

O

Y24

O

Y26

O

AA28

O

A3

B_1

A4

B_2

B3

B_3

B4

B_4

A5 A6 B5 B6

+

CPU_CORE_NB

5V

+1.

DP decoupling

VD

120mil120mil

160mil160mil

B

10U

_0603_6.3V6M

C8

1

2

DDR decoupling

V

180P_0402_50V8J

C

C 1044

1044

1

2

C

0.22U_0603_16V4Z

1052

1

2

22U_0805_6.3V6M

983

996

1

2

22U_0805_6.3V6M

C

1001

1002

1

2

4.7U_0603_6.3V6K

C

22U_0805_6.3V6M

1013

C1

1

4

2

C

0.22U_0603_16V4Z

180P_0402_50V8J

1028

1029

1

2

180P_0402_50V8J

C

1036

1035

1

2

1000P_0402_50V7K

180P_0402_50V8J

C

1049

1048

1

2

4.7U_0603_6.3V6K

0.22U_0603_16V4Z

0.22U_0603_16V4Z C1

C1

1

0

1

2

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SIDE DECOUPLING

C

22U_0805_6.3V6M

0.22U_0603_16V4Z

4.7U_0603_6.3V6K

C

C 1051

1051

C1

C1 3

3

985

1

2

C

C 1005

1005

1

2

C1

1

7

2

+1.

+

1000P_0402_50V7K

1

2

4.7U_0603_6.3V6K

2

1

C

C987

22U_0805_6.3V6M

986

1

2

0.22U_0603_16V4Z

180P_0402_50V8J

C1007

C

C 1006

1006

1

2

4.7U_0603_6.3V6K

C1019

C

0.22U_0603_16V4Z

1018

1

2

2VS

1

1038

C

C 220U_6.3V_M

220U_6.3V_M

2

C1038 change to SF000002Y00 20101228

+1.2VS

2010/

08/04 2011/12/31

C

22U_0805_6.3V6M

984

997

1

2

22U_0805_6.3V6M

C

1004

1003

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C1

C1

1

6

5

2

C

180P_0402_50V8J

1030

1

2

Decoupling between CPU and DIMMs across VDDIO and VSS split

2VS

+1.

0.22U_0603_16V4Z

C

C 1037

1037

1

2

1000P_0402_50V7K

C

C 1050

1050

1

2

4.7U_0603_6.3V6K

C1

1

2

C

D

C991

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 988

988

1

2

180P_0402_50V8J

C

C 1008

1008

1

2

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 1020

1020

1

2

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 989

989

1

2

180P_0402_50V8J

C

C 1009

1009

1

+

2

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 1021

1021

1

2

pal Secret Data

Com

C

0.01U_0402_16V7K

0.01U_0402_16V7K 998

998

1

2

390U_2.5V_10M

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 1022

1022

1

2

D

CP 470uF x 6 22uF x 9

0.22uF x 2 180pF x 2 10nF x 3

Deciphered Date

C991

C

0.01U_0402_16V7K

0.01U_0402_16V7K 990

990

1

2

C

0.22U_0603_16V4Z

0.22U_0603_16V4Z 1023

1023

1

2

emo Board Capacitor (include PWM side)

U_CORE

0.01U_0402_16V7K

0.22U_0603_16V4Z

180P_0402_50V8J

1

2

C1024

180P_0402_50V8J

1

2

CORE_NB 470uF x 4 22uF x 6

0.22uF x 2 180uF x 3

D

C

C 992

992

C

C 1025

1025

1

2

1

2

180P_0402_50V8J

C5

@

330U

1

_D2_2V_Y

+

2

VDDIO_SUS (CPU side) 680uF x 1 330uF x 1 22uF x 3

4.7uF x 4

0.22uF x 6 180pF x 4

VDDIO_SUS (DIMM x2) 100uF x 4

0.1uF

Title

Ti

tle

AM

Size Document Number Rev

Custom

Date: Sheet

QB

A1 A1 A1 A1 A2 A2 A2

C1 C1 C1 C1 C2 C2 C2 C2 C2 D1 D1 D1 D1 D2 D2 D2 D2

E1 E1

F11 F14 F16 F18 F20 F22 F24 F26 F28

G1 G1 G1 G1 G2 G2 G2

J18 J20 J22 J24

K1

L10

M1 M1

N1 N1

P1 P1

R1 R1

V

DDP/R_PWM 470uF x 2 10uF x 1

Compal E

D FS1 PWR / GND

L50 LA-7551P

PU1F

JC

A7

VSS

3

VSS

5

VSS

7

VSS

9

VSS

1

VSS

3

VSS

5

VSS

B7

VSS

C4

VSS

0

VSS

4

VSS

6

VSS

8

VSS

0

VSS

2

VSS

4

VSS

6

VSS

8

VSS

3

VSS

5

VSS

7

VSS

9

VSS

1

VSS

3

VSS

5

VSS

7

VSS

E4

VSS

0

VSS

2

VSS

F9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G4

VSS

G8

VSS

3

VSS

5

VSS

7

VSS

9

VSS

1

VSS

3

VSS

5

VSS

J4

VSS

J8

VSS VSS VSS VSS VSS

9

VSS

L4

VSS

L7

VSS VSS

M9

VSS

1

VSS

9

VSS

N4

VSS

N7

VSS

0

VSS

8

VSS

P9

VSS

1

VSS

9

VSS

R4

VSS

R7

VSS

0

VSS

8

VSS

T9

VSS

AMD_TOPEDO_FS-1

lectronics, Inc.

E

CONN@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDP 10uF x 3

0.22uF x 2 180pF x 2

E

T11 T19 U4 U7 U1 U1 V9 V1 V1 W4 W7 W1 W1 W1 W1 W1 Y9 Y2 AA4 AA7 AB9 AB1 AB1 AB1 AB1 AB2 AB2 AB2 AB2 AC4 AC7 AC1 AC1 AC1 AC1 AC1 AC2 AC2 AC2 AC2 AC2 AD9 AD1 AE4 AE7 AE1 AE1 AE1 AE1 AE2 AE2 AE2 AE2 AF3 AF6 AF9 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG AH5 AH8 AH1 AH1 AH1 AH1 AH2 AH2 AH2

1 9

2

0 8

0 2 4 6 8

3 5 7 9 1 3 5 7

0 2 4 6 8 0 2 4 6 8

1

3 5 7 9 1 3 5 7

10

3 5 7 9 1 3 5

VDDR

4.7uF x 4

0.22uF x 4 1nF x 4 180pF x 4

953Wednesday, April 27, 2011

1.0

of

5

S

1 2

+3V

12

R

613

10K_0402_5%

2

G

1 3

D

S

D

S

3

Q1

Q1 2N7002K_SOT23-3

2N7002K_SOT23-3

+3V

S

12

621

R

R 10K_0402_5%

10K_0402_5%

2

G

1 3

D

S

D

S

Q1

6

2N7002K_SOT23-3

1K_0402_5%

˛ˣ˗

˛ˣ˗ ˣ˴˸˿ʳ˘ˡ˕˞˟

˛ˣ˗˛ˣ˗

@

R

615

1K_0402_5%

12

R

622

1K_0402_5%

12

@

D D

T

ranslator HPD

From

Translator

LV

DS_HPD

DS_HPD26

LV

618 100K_0402_5%

R

CRT HPD

From FCH

F

CH_CRT_HPD15

C C

CH_CRT_HPD

F

627 100K_0402_5%

R

HDMI HPD

From HDMI Conn

HDMI_HPD28

APU_

HDMI_HPD

APU_

@

12

659 100K_0402_5%

R

1 2

677 0_0402_5%

R

616

623

+1.

5VS

1 2

5VS

+1.

1 2

5VS

+1.

12

@

R

4.7K_0402_5%

4

DP0

_HPD 8

DP1

_HPD 8

630

_HPD 8

DP5

3

ˣ˴˸˿ʳ˘ˡ˕˞˟

ˣ˴˸˿ʳ˘ˡ˕˞˟ˣ˴˸˿ʳ˘ˡ˕˞˟

ENBKL8

DP_

ˣ˴˸˿ʳ˘ˡ˩˗˗

ˣ˴˸˿ʳ˘ˡ˩˗˗ˣ˴˸˿ʳ˘ˡ˩˗˗

DP_

ENVDD8

1 2

R

619 2.2K_0402_5%

@

620

R

100K_0402_5%

1 2

R

@

R

634

100K_0402_5%

1 2

@

Q1

DP_

Q1

ENBKL

@

1 2

633 2.2K_0402_5%

+3V

S

@

617

R

R 100K_0402_5%

100K_0402_5%

1 2

2

G

C

5

2

B

E

3 1

MBT3904_NL_SOT23-3

MBT3904_NL_SOT23-3 M

M

1 2

R

676 0_0402_5%

+3V

S

@

631

R

100K_0402_5%

1 2

@

C

9

Q1

2

B

E

3 1

MMBT3904_NL_SOT23-3

@

2

G

2

12

@

R

614

4.7K_0402_5%

APU_

13

D

Q1

4

2N7002K_SOT23-3

S

ENBKL

12

@

632

R

4.7K_0402_5%

13

D

@

2N7002K_SOT23-3

S

ENBKL

Q1

1

R

624 0_0402_5%@R624 0_0402_5%@

1 2

APU_

ENVDD 27

8

ENBKL

36

B B

A A

5

4

ˣ˴˸˿ʳˣ˪ˠ

ˣ˴˸˿ʳˣ˪ˠˣ˴˸˿ʳˣ˪ˠ

INT_PWM8

DP_

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

637 2.2K_0402_5%

R

12

638

R

4.7K_0402_5%

ompal Secret Data

C

2010/

08/04 2011/12/31

C

S

+3V

12

R

R 47K_0402_5%

47K_0402_5%

C

1

Q2

2

B

E

3 1

Deciphered Date

12

636

2

G

13

D

S

2

R

4.7K_0402_5%

636

0

Q2

2N7002K_SOT23-3

A

PU_INVT_PWM 26,27

Q15 /

Q19 / Q21 change to SB000006A00

20101228

Ti

tle

MD FS1 Singal Level Shifter

A

Size Document Number Rev

Custom

Q

BL50 LA-7551P

Date: Sheet

1

1.0

10 53Wednesday, April 27, 2011

1.0

of

635

MMBT3904_NL_SOT23-3

A

B

C

D

E

SDQ0 SDQ1

SDM0

SDQ2 SDQ3

SDQ8 SDQ9

SDQS1# SDQS1

SDQ10 SDQ11

SDQ16 SDQ17

SDQS2# SDQS2

SDQ18 SDQ19

SDQ24 SDQ25

SDM3

SDQ26 SDQ27

CKE0

SBS2#

SMA12 SMA9

SMA8 SMA5

SMA3 SMA1

CLK0 CLK0#

SMA10 SBS0#

SWE# SCAS#

SMA13 SCS1#

SDQ33

SDQS4# SDQS4

SDQ34 SDQ35

SDQ40 SDQ41

SDM5

SDQ42 SDQ43

SDQ48 SDQ49

SDQS6

SDQ50

SDQ56 SDQ57

SDM7

SDQ58 SDQ59

12

R645

10K_0402_5%

+1.

5V

15mil

DIMM2

J

1

VREF_

3

VSS2

5

0

DQ

7

DQ

1

9

VSS4

11

DM

0

13

VSS5

15

DQ

2

17

3

DQ

19

VSS7

21

DQ

8

23

9

DQ

25

VSS9

27

S#1

DQ

29

S1

DQ

31

VSS1

33

DQ

10

35

DQ

11

37

VSS1

39

16

DQ

41

DQ

17

43

VSS1

45

S#2

DQ

47

S2

DQ

49

VSS1

51

18

DQ

53

DQ

19

55

VSS2

57

24

DQ

59

DQ

25

61

VSS2

63

3

DM

65

VSS2

67

DQ

26

69

27

DQ

71

VSS2

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

2/BC#

A1

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0

105

VDD1

107

A

10/AP

109

BA0

111

VDD1

113

WE

115

CAS#

117

VDD1

119

3

A1

121

S1

#

123

VDD1

125

NCTEST

127

VSS2

129

DQ

32

131

DQ

33

133

VSS2

135

DQ

S#4

137

S4

DQ

139

VSS3

141

34

DQ

143

DQ

35

145

VSS3

147

DQ

40

149

DQ

41

151

VSS3

153

DM

5

155

VSS3

157

DQ

42

159

DQ43

161

VSS3

163

48

DQ

165

DQ49

167

VSS4

169

DQS#6

171

DQ

S6

173

VSS44

175

DQ

50

177

51

DQ

179

VSS46

181

56

DQ

183

DQ57

185

VSS4

187

7

DM

189

VSS4

191

58

DQ

193

DQ

59

195

VSS5

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013310-1

DQ

VSS1

DQ DQ

VSS3

S#0

DQ

VSS6

DQ

DQ VSS8 DQ DQ

VSS1

DM

RESET#

VSS1

1

DQ DQ

3

VSS1

DQ DQ

VSS1

5

DM

VSS1

DQ

8

DQ

VSS1

0

DQ DQ

VSS2

2

S#3

DQ

3

VSS2

DQ DQ

5

VSS2

CKE1 VDD2

A1 A1

VDD4

A1

VDD6

VDD8

VDD1

CK1 CK1

#

1

VDD1

BA1

RAS#

VDD1

3

#

S0

OD

5

VDD1

OD

NC2

7

VDD1

VREF_

CA

7

VSS2

DQ DQ

9

VSS3

DM

VSS3

DQ

2

DQ

VSS3

DQ

4

DQ

VSS3

6

S#5

DQ

7

VSS3

DQ DQ47

VSS4

9

DQ DQ53

VSS4

1

DM6

VSS4

DQ54 DQ

VSS4

DQ60 DQ

VSS47

8

S#7

DQ

VSS5

9

DQ DQ

1

VSS5

EVENT#

SDA

SCL VTT2

G2

VREF_DQ

+

DDRA_ DDRA_

DDRA_

+3V

S

DDRA_

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

DDRA_SDQ32 DDRA_

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

DDRA_SDQS6# DDRA_

DDRA_ DDRA_SDQ51

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

R

643 10K_0402_5%

1 2

R645

1 1

SDQS1#7

DDRA_ DDRA_

SDQS17

SDQS2#7

DDRA_ DDRA_

SDQS27

DDRA_

CKE07

2 2

3 3

4 4

C

1080

2.2U_0603_6.3V4Z

+3VS

1

2

DDRA_

CLK07

DDRA_

CLK0#7

DDRA_

DDRA_SBS0#7

DDRA_

SCAS#7

DDRA_

SCS1#7

DDRA_

SDQS4#7 SDQS47

DDRA_

SDQS6#7

DDRA_

SDQS67

DDRA_

1

C

1081

0.1U_0402_16V4Z

2

SBS2#7

SWE#7

5V

+1.

2

DDRA_

4

6

5

8 10 12

S0

14 16

6

18

7

20 22

12

24

13

26

0

28

1

30 32

2

34

14

36

15

38

4

40

20

42

21

44

6

46

2

48

7

50

22

52

23

54

9

56

28

58

29

60

1

62 64

S3

66

4

68

30

70

31

72

6

74 76 78

5

80

4

82 84

1

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100

0

102 104

#

106

2

108 110 112

4

114

#

116

T0

118

6

120

T1

122 124

8

126 128

8

130

36

132

37

134

0

136

4

138

1

140

38

142

39

144

3

146

44

148

45

150

5

152 154

S5

156

8

158

46

160 162

0

164

52

166 168

2

170 172

3

174 176

55

178

5

180 182

61

184 186 188

S7

190

0

192

62

194

63

196

2

198 200 202 204

206

SDQ4 SDQ5

DDRA_

SDQS0# SDQS0

DDRA_

SDQ6

DDRA_

SDQ7

DDRA_

SDQ12 SDQ13

DDRA_

SDM1

DDRA_

M_MA_RST#

ME

SDQ14

DDRA_ DDRA_

SDQ15

SDQ20

DDRA_ DDRA_

SDQ21

DDRA_

SDM2

DDRA_

SDQ22

DDRA_

SDQ23

SDQ28

DDRA_

SDQ29

DDRA_

SDQS3#

DDRA_ DDRA_

SDQS3

DDRA_

SDQ30

DDRA_

SDQ31

DDRA_

DDRA_ DDRA_

DDRA_

15m

il

DDRA_SDQ36 DDRA_

DDRA_

DDRA_ DDRA_

DDRA_SDM6

DDRA_SDQ54 DDRA_

DDRA_ DDRA_

M

EM_MA_EVENT#

CKE1

SMA15 SMA14

SMA11 SMA7

SMA6 SMA4

SMA2 SMA0

CLK1 CLK1#

SBS1# SRAS#

SCS0# ODT0

ODT1

SDQ37

SDM4

SDQ38 SDQ39

SDQ44 SDQ45

SDQS5# SDQS5

SDQ46 SDQ47

SDQ52 SDQ53

SDQ55

SDQ60 SDQ61

SDQS7# SDQS7

SDQ62 SDQ63

SDQS0# 7

DDRA_ DDRA_

SDQS0 7

ME

M_MA_RST# 7

DDRA_

SDQS3# 7

DDRA_

SDQS3 7

DDRA_

CKE1 7

DDRA_

CLK1 7 CLK1# 7

DDRA_

SBS1# 7

DDRA_SRAS# 7

SCS0# 7

DDRA_

ODT0 7

DDRA_

ODT1 7

VREF_CA

+

1

1066

C

1000P_0402_50V7K

2

SDQS5# 7

DDRA_ DDRA_

SDQS5 7

DDRA_SDQS7# 7

SDQS7 7

DDRA_

M

EM_MA_EVENT# 7

FC

H_SDATA0 12,14,32 H_SCLK0 12,14,32

FC

75VS

+0.

SDQ[0..63]

DDRA_

SDM[0..7]

DDRA_

SMA[0..15]

lace near DIMM1

P

+1.

5V

0.1U_0402_16V4Z

2

1067

C

1

0.1U_0402_16V4Z

+0.

75VS

2

C

1077

1

0.1U_0402_16V4Z

+

VREF_DQ

15mil

4.7U_0603_6.3V6K

1

@

C1060

2

DDRA_

2

1068

C

1

0.1U_0402_16V4Z

2

C

1078

1

+

VREF_DQ

1

1061

C

2

_0402_50V7K

1U_0402_16V4Z

0.

1000P

SDQ[0..63] 7

SDM[0..7] 7

SMA[0..15] 7

0.1U_0402_16V4Z

2

1069

C

1

C

1079

2

4.7U_0603_6.3V6K

+1.

1 2

1

1062

C

2

1 2

2

1070

C

1

0.1U_0402_16V4Z

@

1 2

1106 0.1U_0402_16V4Z

C

A

dd C1106

20101101

5V

639

R

R 1K_0402_1%

1K_0402_1%

641

R

R 1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

2

1071

C

1

+1.

5V

VREF_CA

+

1072

C

0.1U_0402_16V4Z

15mil

4.7U_0603_6.3V6K

1

@

C1063

2

1073

C

1

+

VREF_CA

1

2

0.1U_0402_16V4Z

2

1074

C

1

C

1064

2

1000P_0402_50V7K

2

1075

C

1

0.1U_0402_16V4Z

+1.

C

1065

0.1U_0402_16V4Z

2

1076

C

1

5V

R

640

1K_0402_1%

1 2

642

R

R 1K_0402_1%

1K_0402_1%

1 2

curity Classification

Se

Issued Date

DIM

M_A STD H:9.2mm

<A

ddress: 00>

A

B

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

DDRIII S

QB

L50 LA-7551P

lectronics, Inc.

O-DIMM 1

E

1.0

11 53Wednesday, April 27, 2011

1.0

of

A

B

C

D

E

5V

+1.

2

DDRB_

4

6

5

8 10 12

S0

14 16

6

18

7

20 22

12

24

13

26

0

28

1

30 32

2

34

14

36

15

38

4

40

20

42

21

44

6

46

2

48

7

50

22

52

23

54

9

56

28

58

29

60

1

62 64

S3

66

4

68

30

70

31

72

6

74 76 78

5

80

4

82 84

1

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100

0

102 104

#

106

2

108 110 112

4

114

#

116

T0

118

6

120

T1

122 124

8

126 128

8

130

36

132

37

134

0

136

4

138

1

140

38

142

39

144

3

146

44

148

45

150

5

152 154

S5

156

8

158

46

160 162

0

164

52

166 168

2

170 172

3

174 176

55

178

5

180 182

61

184 186 188

S7

190

0

192

62

194

63

196

2

198 200 202 204

206

G2

SDQ4 SDQ5

DDRB_

SDQS0# SDQS0

DDRB_

SDQ6

DDRB_

SDQ7

DDRB_

SDQ12 SDQ13

DDRB_

SDM1

DDRB_

M_MB_RST#

ME

SDQ14

DDRB_ DDRB_

SDQ15

SDQ20

DDRB_ DDRB_

SDQ21

DDRB_

SDM2

DDRB_

SDQ22

DDRB_

SDQ23

SDQ28

DDRB_

SDQ29

DDRB_

SDQS3#

DDRB_ DDRB_

SDQS3

DDRB_

SDQ30

DDRB_

SDQ31

DDRB_

DDRB_ DDRB_

DDRB_

15mil

DDRB_SDQ36 DDRB_

DDRB_

DDRB_ DDRB_

DDRB_SDM6

DDRB_SDQ54 DDRB_

DDRB_ DDRB_

M

EM_MB_EVENT#

CKE1

SMA15 SMA14

SMA11 SMA7

SMA6 SMA4

SMA2 SMA0

CLK1 CLK1#

SBS1# SRAS#

SCS0# ODT0

ODT1

SDQ37

SDM4

SDQ38 SDQ39

SDQ44 SDQ45

SDQS5# SDQS5

SDQ46 SDQ47

SDQ52 SDQ53

SDQ55

SDQ60 SDQ61

SDQS7# SDQS7

SDQ62 SDQ63

+0.

75VS

SDQS0# 7

DDRB_ DDRB_

SDQS0 7

ME

M_MB_RST# 7

DDRB_

SDQS3# 7

DDRB_

SDQS3 7

DDRB_

CKE1 7

DDRB_ DDRB_

DDRB_ DDRB_SRAS# 7

DDRB_ DDRB_

DDRB_

1

2

DDRB_ DDRB_

DDRB_SDQS7# 7 DDRB_

M

EM_MB_EVENT# 7

FC

H_SDATA0 11,14,32 H_SCLK0 11,14,32

FC

CLK1 7 CLK1# 7

SBS1# 7

SCS0# 7 ODT0 7

ODT1 7

VREF_CA

+

1088

C

C 1000P_0402_50V7K

1000P_0402_50V7K

SDQS5# 7 SDQS5 7

SDQS7 7

+

VREF_DQ

SDQ[0..63]

DDRB_

SDM[0..7]

SMA[0..15]

DDRB_

Place near DIMM2

+1.

5V

0.1U_0402_16V4Z

2

C

1089

1

0.1U_0402_16V4Z

+0.

75VS

0.1U_0402_16V4Z

2

1099

C

1

0.1U_0402_16V4Z

15mil 15mil

VREF_DQ

+

4.7U_0603_6.3V6K

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

1

1083

C1082

1083

C

2

@

2

C

1090

1

2

C

1

_0402_50V7K

1000P

2

1

0.1U_0402_16V4Z

1

1100

2

4.7U_0603_6.3V6K

1

1084

C

2

SDQ[0..63] 7

SDM[0..7] 7

SMA[0..15] 7

0.1U_0402_16V4Z

2

C

1091

1092

1

1 2

1107 0.1U_0402_16V4Z

C

1101

C

+

VREF_CA

4.7U_0603_6.3V6K

1

@

C1085

2

C

1093

1

0.1U_0402_16V4Z

+1.

5V

@

A

dd C1107

20101101

VREF_CA

+

0.1U_0402_16V4Z

1

1086

C

2

0.1U_0402_16V4Z

2

C

1094

1

1087

C

2

1000P_0402_50V7K

2

C

1095

1

0.1U_0402_16V4Z

+1.

5V

1

+

C9

330U

2

0.1U_0402_16V4Z

2

C

1096

1

_X_2VM_R6M@

2

C

1097

1

0.1U_0402_16V4Z

2

C

1098

1

SDQ0 SDQ1

SDM0

SDQ2 SDQ3

SDQ8 SDQ9

SDQS1# SDQS1

SDQ10 SDQ11

SDQ16 SDQ17

SDQS2# SDQS2

SDQ18 SDQ19

SDQ24 SDQ25

SDM3

SDQ26 SDQ27

CKE0

SBS2#

SMA12 SMA9

SMA8 SMA5

SMA3 SMA1

CLK0 CLK0#

SMA10 SBS0#

SWE# SCAS#

SMA13 SCS1#

SDQ33

SDQS4# SDQS4

SDQ34 SDQ35

SDQ40 SDQ41

SDM5

SDQ42 SDQ43

SDQ48 SDQ49

SDQS6

SDQ50

SDQ56 SDQ57

SDM7

SDQ58 SDQ59

12

R648

10K_0402_5%

5V

+1.

15m

J

il

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

DIMM1

DQ

VREF_ VSS2

0

DQ DQ

1 VSS4 DM

0 VSS5 DQ

2

3

DQ VSS7 DQ

8

9

DQ VSS9

S#1

DQ

S1

DQ VSS1

1

DQ

10 DQ

11

3

VSS1

16

DQ DQ

17 VSS1

5

S#2

DQ

S2

DQ VSS1

8

18

DQ DQ

19

0

VSS2

24

DQ DQ

25

2

VSS2

3

DM

3

VSS2 DQ

26

27

DQ

5

VSS2

CKE0 VDD1 NC1 BA2 VDD3

2/BC#

A1 A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0

#

1

VDD1 A

10/AP BA0 VDD1

3

WE

#

CAS#

5

VDD1

3

A1 S1

#

7

VDD1 NCTEST

VREF_

7

VSS2 DQ

32

DQ

33

9

VSS2 DQ

S#4 S4

DQ VSS3

2

34

DQ DQ

35

VSS3

4

DQ

40

DQ

41

6

VSS3 DM

5

7

VSS3 DQ

42 DQ43 VSS3

9

48

DQ DQ49 VSS4

1 DQS#6 DQ

S6 VSS44 DQ

50

51

DQ VSS46

56

DQ DQ57

8

VSS4

7

DM VSS4

9

58

DQ DQ

59

1

VSS5 SA0 VDDSPD SA1 VTT1

G1

TYCO_2-2013289-1

VSS1

DQ DQ

VSS3

DQ

VSS6

DQ

DQ VSS8 DQ DQ

VSS1

DM

RESET#

VSS1

DQ DQ

VSS1

DQ DQ

VSS1

DM

VSS1

DQ DQ

VSS1

DQ DQ

VSS2

DQ

VSS2

DQ DQ

VSS2

CKE1 VDD2

VDD4

VDD6

VDD8

VDD1

CK1

VDD1

RAS#

VDD1

OD

VDD1

OD

NC2

VDD1

VSS2

DQ DQ

VSS3

DM

VSS3

DQ DQ

VSS3

DQ DQ

VSS3

DQ

VSS3

DQ DQ47

VSS4

DQ DQ53

VSS4

DM6

VSS4

DQ54 DQ

VSS4

DQ60 DQ

VSS47

DQ

VSS5

DQ DQ

VSS5

EVENT#

SDA

VTT2

S#0

S#3

A1 A1

A1

CK1

BA1

S0

S#5

S#7

SCL

CA

VREF_DQ

+

DDRB_ DDRB_

DDRB_

S

DDRB_

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_SDQ32 DDRB_

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_SDQS6# DDRB_

DDRB_ DDRB_SDQ51

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

R

646 10K_0402_5%

1 2

<BOM Structure>R648

1 1

SDQS1#7

DDRB_ DDRB_

SDQS17

SDQS2#7

DDRB_ DDRB_

SDQS27

DDRB_

CKE07

2 2

3 3

4 4

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_SBS0#7

DDRB_

SBS2#7

CLK07 CLK0#7

SWE#7

SCAS#7

SCS1#7

SDQS4#7 SDQS47

SDQS6#7 SDQS67

+3V

curity Classification

Se

Issued Date

DIM

M_B STD H:5.2mm

<A

ddress: 01>

A

B

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

DDRIII S

lectronics, Inc.

O-DIMM 2

QB

L50 LA-7551P

1.0

12 53Wednesday, April 27, 2011

E

1.0

of

A

C

1195 150P_0402_50V8J

12

APU_

829 33_0402_5%

R

RST#36

CI Host Bus Reset (To EC)

P

1 1

˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕

˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕ ˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

2 2

SS

APU DISP

NSS

AP

U

VGA

GLA

N

AN

WL

A_

UM

I_MTX_C_FRX_P06

UM

I_MTX_C_FRX_N06

UM

I_MTX_C_FRX_P16 I_MTX_C_FRX_N16

UM UM

I_MTX_C_FRX_P26 I_MTX_C_FRX_N26

UM UM

I_MTX_C_FRX_P36 I_MTX_C_FRX_N36

UM

I_FTX_C_MRX_P06 I_FTX_C_MRX_N06

UM

I_FTX_C_MRX_P16

UM

I_FTX_C_MRX_N16

UM UM

I_FTX_C_MRX_P26 I_FTX_C_MRX_N26

UM

I_FTX_C_MRX_P36

UM

I_FTX_C_MRX_N36

UM

+

PCIE_VDDR_FCH

1.1VS_CKVDD

+

"EXT" CLK mode, input to PCIE,

For

APU_

DISP_CLKP8 DISP_CLKN8

APU_

S_CLKP26

TRAVI TRAVI

S_CLKN26

CLKP8

APU_ APU_

CLKN8

CL

K_PEG_VGA18 K_PEG_VGA#18

CL

K_PCIE_LAN29

CL

K_PCIE_LAN#29

LK_PCIE_M INI132

C C

LK_PCIE_M INI1#32

1 2

C

1189 0.1U_0402_16V7K

1 2

C

1190 0.1U_0402_16V7K

1 2

C

1191 0.1U_0402_16V7K

1 2

1192 0.1U_0402_16V7K

C

1 2

1196 0.1U_0402_16V7K

C

1 2

C

1197 0.1U_0402_16V7K

1 2

C

1198 0.1U_0402_16V7K

1 2

1194 0.1U_0402_16V7K

C

1 2

R

827 590_0402_1%

1 2

R

828 2K_0402_1%

1 2

R

833 2K_0402_1%

1 2

APU_DISP_CLKP APU_

DISP_CLKN

TRAVI

S_CLKP S_CLKN

TRAVI

CLKP

APU_ APU_

CLKN

CL

K_PEG_VGA

CL

K_PEG_VGA#

CL

K_PCIE_LAN K_PCIE_LAN#

CL

LK_PCIE_M INI1

C

LK_PCIE_M INI1#

C

R

604 0_0402_5%

R

625 0_0402_5%

644 0_0402_5%

R

572 0_0402_5%

R

1 2 1 2

A_

UM

I_MTX_FRX_P0 I_MTX_FRX_N0

UM UM

I_MTX_FRX_P1

UM

I_MTX_FRX_N1 I_MTX_FRX_P2

UM

I_MTX_FRX_N2

UM UM

I_MTX_FRX_P3

UM

I_MTX_FRX_N3

UM

I_FTX_C_MRX_P0 I_FTX_C_MRX_N0

UM UM

I_FTX_C_MRX_P1 I_FTX_C_MRX_N1

UM

I_FTX_C_MRX_P2

UM UM

I_FTX_C_MRX_N2 I_FTX_C_MRX_P3

UM UM

I_FTX_C_MRX_N3

E_CALRP

PCI PCI

E_CALRN

CL

K_CALRN

CL CL

LK_PCIE_M INI1_R

C

LK_PCIE_MINI1#_R

C

SS

3 3

EMI

R

657 22_0402_5%

LK_SD_48M31

C

1200

12

12P_0402_50V8J

HZ_20PF_7A25000012

25M

12

1201

C

12P_0402_50V8J

C1205

4 4

A

C1205

1 2

10P_0402_50V8J

861

R

20M_0402_5%

1206

C

1 2

10P_0402_50V8J

1 2

856 0_0402_5%

R

12

1 2

R

858

X1

1M_0402_5%

Y4

4

1

32.768KHZ_7PF_Q13MC1461000100

Close to HUDSON-M2

3

2

PCIE_RST#_C

RST#_R

K_PCIE_LAN_R K_PCIE_LAN#_R

CLK_SD_48M_R

_X1

25M

_X2

25M

32K

32K_X2

B

AE2 AD5

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

Y33 Y31 Y28 Y29

AF29 AF31

V33

V31 W30 W32

AB26 AB27 AA24 AA23

AA27 AA26

W27

V27

V26 W26 W24 W23

F27

G30 G28

R26

T26

H33

H31

T24

T23

J30

K29

H27

H28

J27

K26

F33

F31

E33

E31

M23 M24

M27 M26

N25

N26

R23

R24

N27

R27

J26

C31

C33

_X1

B

25A

U

PCI

E_RST#

A_

RST#

I_TX0P

UM

I_TX0N

UM UM

I_TX1P I_TX1N

UM UM

I_TX2P I_TX2N

UM UM

I_TX3P I_TX3N

UM

I_RX0P I_RX0N

UM UM

I_RX1P I_RX1N

UM

I_RX2P

UM UM

I_RX2N

UM

I_RX3P

UM

I_RX3N

E_CALRP

PCI PCI

E_CALRN

PP_TX0P

G

PP_TX0N

G G

PP_TX1P PP_TX1N

G G

PP_TX2P PP_TX2N

G

PP_TX3P

G G

PP_TX3N

PP_RX0P

G

PP_RX0N

G G

PP_RX1P PP_RX1N

G

PP_RX2P

G

PP_RX2N

G

PP_RX3P

G G

PP_RX3N

CL

K_CALRN

E_RCLKP

PCI PCI

E_RCLKN

DI

SP_CLKP

DI

SP_CLKN

ISP2_CLKP

D

ISP2_CLKN

D

PU_CLKP

A A

PU_CLKN

SL

T_GFX_CLKP

SL

T_GFX_CLKN

PP_CLK0P

G

PP_CLK0N

G

PP_CLK1P

G G

PP_CLK1N

G

PP_CLK2P

G

PP_CLK2N

G

PP_CLK3P PP_CLK3N

G

PP_CLK4P

G G

PP_CLK4N

G

PP_CLK5P

G

PP_CLK5N

G

PP_CLK6P PP_CLK6N

G

GPP_CLK7P G

PP_CLK7N

GPP_CLK8P G

PP_CLK8N

14M_25M_48M_OSC

_X1

25M

_X2

HUDSON-M2_FCBGA656

M2@

HUDSON-2

PCI CLKS

CICLK4/14M_OSC/GPO39

P

PCI EXPRESS INTERFACES

PCI INTERFACE

EQ2#/CLK_RE Q8#/GPIO41

R R

EQ3#/CLK_RE Q5#/GPIO42

G

NT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPCAPUS5 PLUS

DRQ1#/CLK_REQ6#/GPIO49

L

C

AF3

PCI

CLK0

RST#

PCI

A

D0/GPIO0 D1/GPIO1

A

D2/GPIO2

A A

D3/GPIO3 D4/GPIO4

A A

D5/GPIO5 D6/GPIO6

A

D7/GPIO7

A A

D8/GPIO8

A

D9/GPIO9 D10/GPIO10 D11/GPIO11 D12/GPIO12 D13/GPIO13 D14/GPIO14 D15/GPIO15 D16/GPIO16 D17/GPIO17 D18/GPIO18 D19/GPIO19 D20/GPIO20 D21/GPIO21 D22/GPIO22 D23/GPIO23 D24/GPIO24 D25/GPIO25 D26/GPIO26 D27/GPIO27 D28/GPIO28 D29/GPIO29 D30/GPIO30 D31/GPIO31

CBE0 CBE1 CBE2 CBE3

FRAM

DEVSEL

I

RDY# RDY#

T

PAR STO PERR# SERR# REQ

GN

T1#/GPO44

CL

KRUN#

CK#

LO

TE#/GPIO32

TF#/GPIO33 TG#/GPIO34 TH#/GPIO35

PCCLK0

L

PCCLK1

L

LA LA LA LA

LFRAM

L

DRQ0#

A_ACTIVE#

CHOT#

PRO

APU_PG

LDT_STP#

APU_RST#

_CORE_EN

CCLK

RT

_RTC_G

32K

AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13

A_PWRGD_R

VG

AH14 AD15 AC15 AE16 AN3

#

AJ8

#

AN10

#

AD12

#

AG10

E#

AK9

#

AL10 AF10 AE1

0

AH1

P#

AM

9 AH8 AG15

0#

AG13 AF15 AM17 AD16

T0#

AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

L

B25

L

D25

LP

D27

D0

LP

C28

D1

LP

A26

D2

LP

A29

D3

A31

E#

B27 AE27 AE19

G25 E28 E26 G2

6 F26

H7 F1 F3 E6

32K

G2

_X1

32K

G4

_X2

C

T23T23

R

T24T24

PC_CLK0_EC_R

PC_CLK1_R

C_AD0 C_AD1 C_AD2 C_AD3

APU_

R

R R

R

844

R

PWRGD

R

_X1

_X2

2010/

08/04 2011/12/31

P

CICLK1/GPO36 CICLK2/GPO37

P

CICLK3/GPO38

P

A A A A A A A A A A A A A A A A A A A A A A

EQ1#/GPIO40

R

GN

NT2#/SD_LED/GPO45

IN

IN IN IN

S

ERIRQ/GPIO48

DM

S5

INTRUDER_ALERT#

VDDBT

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CI_CLK1 16

P

CI_CLK3 16

P

CI_CLK4 16

APU_

842 0_0402_5%

1 2

P

E_GPIO1

PC_CLK0_EC

L

843

1 2

671

22_0402_5%

1 2

22_0402_5%

1 2

0_0402_5%

R853 0_0402_5%@R853 0_0402_5%@

1 2

855 22_0402_5%

1 2

CVCC_R

RT

1202

C

1

2

1U_0402_16V4Z

0.

pal Secret Data

Com

Deciphered Date

PCIE_RST#_C

1 2

109 10K_0402_5%

R

@

C

1

2

D

For PCIE device reset on FS1 (GLAN,WLAN)

R

825 33_0402_5%

1 2

150P_0402_50V8J

VG

A_PWRGD25,48

PCI

_AD23 16

PCI

_AD24 16

PCI

_AD25 16

PCI

_AD26 16 _AD27 16

PCI

P

E_GPIO0 18

PE_GPIO1 25,36

C_CLK0_EC 16,36

LP CL

K_PCI_DB 32

PC_CLK1 16

L

C_AD0 32,36

LP

C_AD1 32,36

LP

C_AD2 32,36

LP

C_AD3 32,36

LP

C_FRAME# 32,36

LP

RQ 36

SERI

LLOW_STOP 8

A EC_

THERM# 8,36,47

APU_PWRGD 8

RST# 8

APU_

RT

C_CLK 16,36

1 2

859 510_0402_5%

R

1203

W=20mils

for Clear CMOS

_0402_6.3V6K

_0402_6.3V6K 1U

1U

D

C

1188

+3

VALW

1193

@C1193

@

C

1 2

0.1U_0402_16V4Z

5

@

2

P

B

4

Y

1

A

G

U2

6

2

1

VG

A_PWRGD

826

R

8.2K_0402_5%@

1 2

U2

7

@

2

1

NC7SZ08P5X_NL_SC70-5

3

1 2

835 0_0402_5% R835 0_0402_5%

R

+3

VALW

@C1199

@

1 2

0.1U_0402_16V4Z

5

P

B

4

Y

A

G

3

1 2

832 0_0402_5% R832 0_0402_5%

R

6

C

1199

1 2

830 0_0402_5%@R830 0_0402_5%@

R

1 2

R

831 100K_0402_5%@R831 100K_0402_5%@

˟˸˸˿ʳ˻˼˹ʳʳ˜˦˟ˉ˅ˉˊ

+3V

1 2

S

836

R

4.7K_0402_5%

APU_

10K_0402_5%

PWRGD

5VS

+1.

12

834

R

B

2

E

3 1

C

Q3

8

MMBT3904_NL_SOT23-3

˥˧˖ʳ˕˔˧˧ʳ˖ˁ

CONN@

PU_PG/APU_RST#/LD T_STP# : OD pin

A DMA_ACTIVE# : IN/OD, 0.8V threshold PROCHOT# : IN, 0.8V threshold LDT_STP : No use, NC

DM

A active. The FCH drives the DMA_ACTIVE# to APU to notify D MA activity. This will cause the APU to reestablish the UMI link quicker.

D2

1

DAN202UT106_SC70-3

12

RP1

CL

SHORT PADS

@

+R

TCVCC

1

1204

C

2

1U_0402_16V4Z

0.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

Compal E

Hudson-M2/M3-UMI/P

QB

L50 LA-7551P

E

P

LT_RST# 18,26,29,32

VG

Q38 ch

ange to SB000006A00

20101228

PU_PWRGD_L 47

A

+RTCBATT

1

JR

TC1

+

SUYIN_060003HA002G202ZL

-

2

+RTCBATT

12

3

2

3

lectronics, Inc.

CI/CLOCK/LPC/RTC

13 53Wednesday, April 27, 2011

E

A_PWRGD_R

857

R

R 1K_0402_5%

1K_0402_5%

CHGRTC

+

of

1.0

A

P

CIE_RST2 : Reset PCIE device on Hudson2

EC_

LID_OUT#36

SL

P_S3#36 P_S5#36

SL

PBTN_

OUT#36

CH_PWRGD36

F

1 1

GA2036

EC_

KBRST#36 SCI#36

EC_

SMI#36

EC_

PCIE_WAKE#

FCH_

BITCLK_AUDIO30 SDOUT_AUDIO30

SDIN030

SYNC_AUDIO30

RST_AUDIO#30

OC2#

USB_

OC0#

USB_

OC1#

H_

THERMTRIP#

CH_SCLK1

F

FCH_

SDATA1

EC_

LID_OUT#

FCH_

PCIE_WAKE#

SDATA0

odify 20101111

RSMRST#

BITCLK

SDIN0

PCIE_WAKE#29,32,36

H_

THERMTRIP#8

EC_

RSMRST#36

AN_CLKREQ#29

L

F

CH_SCLK011,12,32

SDATA011,12,32

FCH_

INI1_CLKREQ#32

M

A_PD16

VG

OC2#34

USB_

OC1#34

USB_ USB_

OC0#34

THERMTRIP: Need level shift f rom +3VALW to +1.5V

SM bus 0-->S0 PWR domain SM bus 1-->S5 PWR domain

VGA_PD: Support MLDAC power save if connect 0: MLDAC power on 1: MLDAC power off

2 2

HDA_ HDA_

HDA_

+3

VALW

1 2

R

56 100K_0402_5%

3 3

4 4

1 2

54 100K_0402_5%

R

1 2

871 10K_0402_5%

R

1 2

874 2.2K_0402_5%

R

1 2

876 2.2K_0402_5%

R

1 2

R877 10K_0402_5%

1 2

R878 10K_0402_5%

S

+3V

1 2

880 2.2K_0402_5%

R

1 2

881 2.2K_0402_5%

R

1 2

882 8.2K_0402_5%

R

1 2

R

940 8.2K_0402_5%

1 2

R884 2.2K_0402_5%R884 2.2K_0402_5%

1 2

R885 10K_0402_5%

1 2

R886 10K_0402_5%

1 2

888 10K_0402_5%

R

1 2

55 100K_0402_5%

R

@

HDA_

odify 2010212-AMD request

M

F

CH_SCLK0

FCH_

INI1_CLKREQ#

M

odify 2010212-AMD request

M

AN_CLKREQ#_1

L

M

EC_

HDA_

HDA_SDIN1

A

FCH_

R

M

odify 2010212-AMD request

F FCH_ F FCH_

M

VG

USB_ USB_ USB_

R

866 33_0402_5%

1 2

R

867 33_0402_5%

1 2

R

868 33_0402_5%

1 2

869 33_0402_5%

R

1 2

VALW

+3

8.2K_0402_5%

@

8.2K_0402_5%

@

12

R4

7

5

R4

8.2K_0402_5%

@

8.2K_0402_5%

@

12

@

8

R4

R4 6

6

+3VALW

For FC

1 2

R887 2.2K_0402_5%

1 2

R889 2.2K_0402_5%

1 2

890 2.2K_0402_5%

R

1 2

VALW

+3

R

1 2

+3V

S

R

81 0_0402_5%

1 2

CH_SCLK0

SDATA0

CH_SCLK1

SDATA1

INI1_CLKREQ#

A_PD

OC2# OC1# OC0#

8.2K_0402_5%

@

8.2K_0402_5%

@

R4

R4 3

3

CH_GPIO189

F FCH_GPIO190

CH_GPIO191

F

8.2K_0402_5%

@

8.2K_0402_5%

@

Pr

oject SKU ID

IO189 (use VGA)L(NO)

GP

R4

R4 4

4

GPIO190 (use PX)

IO191

GP

dd Project ID Table

A 201011301600

H internal debug use

@

B

EC

TEST0 TEST1 TEST2

SY

@

18 10K_0402_5%

862 10K_0402_5%

1 2

R

873 10K_0402_5%

HDA_ HDA_ HDA_ HDA_

HDA_SYNC HDA_

TEST0

TEST1

TEST2

B

_LID_OUT#

S_RESET#

L

AN_CLKREQ#_1

T29T29

BITCLK SDOUT SDIN0 SDIN1

T31T31 T35T35

RST#

T27T27

CH_GPIO189

F F

CH_GPIO190

F

CH_GPIO191

H(YES)

R44

R43

L(NO)

(YES)

H

R46

R45

L(15")

H(17")

R48

R47

25D

U

AB6

E_RST2#/PCI_PME#/GEVENT4#

PCI

R2

#/GEVENT22#

RI

W7

_CS3#/GBE_STAT1/GEVENT21#

SPI

T3

SL

P_S3#

W2

P_S5#

SL

J4

PW

R_BTN#

N7

WR_GOOD

P

T9

TEST0

T10

TMS

TEST1/

V9

TEST2

AE22

G

A20IN/GEVENT0#

AG19

AF19

AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25

AG25 AG22

AG26

AF25

/GEVENT1#

KBRST#

R9

L

PC_PME#/GEVENT3#

C26

L

PC_SMI#/GEVENT23#

T5

L

PC_PD#/GEVENT5#

U4

S_RESET#/GEVENT19#

SY

K1

AKE#/GEVENT8#

W

V7

I

R_RX1/GEVENT20#

R10

THRM

TRIP#/SMBALERT#/GEVENT2#

_PWRGD

WD

U2

RSM

RST#

C

LK_REQ4#/SA TA_IS0#/GPIO64 LK_REQ3#/SA TA_IS1#/GPIO63

C

ARTVOLT1/SATA_IS2#/GPIO50

SM C

LK_REQ0#/SA TA_IS3#/GPIO60

ATA_IS4#/FA NOUT3/GPIO55

S

IS5#/FANIN3/GPIO59

SATA_

GPIO66

SPKR/ S

CL0/GPIO43

/GPIO47

SDA0

T7

CL1/GPIO227

S

R7

/GPIO228

SDA1

K_REQ2#/FANIN4/GPIO62

CL CL

K_REQ1#/FANOUT4/GPIO61

J2

R_LED#/LLB#/GPIO184

I SM

ARTVOLT2/SHUTDOWN#/GPIO51

V8

_RST#/GEVENT7#/VGA_PD

DDR3

W8

GB

E_LED0/GPIO18 3

Y6

_HOLD#/GBE_LED1/GEVENT9#

SPI

V10

BE_LED2/GEVENT10#

G

AA8

G

BE_STAT0/GEVENT11#

K_REQG#/GPIO65/OSCIN/IDLEEXIT#

CL

M7

BL

INK/USB_OC7#/GEVENT18#

R8

USB_

OC6#/IR_TX1/GEVENT6#

T1

USB_

OC5#/IR_TX0/GEVENT17#

P6

OC4#/IR_RX0/GEVENT16#

USB_

F5

OC3#/AC_PRES/TDO/GEVENT15#

USB_

P5

USB_

OC2#/TCK/GEVENT14#

J7

OC1#/TDI/GEVENT13#

USB_

T8

USB_

OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

AB3

BITCLK

AZ_

AB1

SDOUT

AZ_

AA2

A

Z_SDIN0/GPIO1 67

Y5

Z_SDIN1/GPIO1 68

A

Y3

A

Z_SDIN2/GPIO1 69

Y1

Z_SDIN3/GPIO1 70

A

AD6

AZ_SY

NC

AE4

AZ_RST#

K19

S2_DAT/SD A4/GPIO187

P

J19

P

S2_CLK/CEC/SCL4/GPIO188

J21

SPI

_CS2#/GBE_STAT2/GPIO166

D21

PS2

KB_DAT/GPIO189

C20

KB_CLK/GPIO190

PS2

D23

PS2

M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

K

SO_0/GPIO209

E20

KSO_1/GPIO210

F20

K

SO_2/GPIO211

A22

KSO_3/GPIO212

E18

K

SO_4/GPIO213

A20

SO_5/GPIO214

K

J18

KSO_6/GPIO215

H18

SO_7/GPIO216

K

G18

KSO_8/GPIO217

B21

SO_9/GPIO218

K

K18

SO_10/GPIO219

K

D19

K

SO_11/GPIO220

A18

SO_12/GPIO221

K

C18

K

SO_13/GPIO222

B19

SO_14/GPIO223

K

B17

K

SO_15/GPIO224

A24

SO_16/GPIO225

K

D17

KSO_17/GPIO226

HUDSON-M2_FCBGA656

M2@

C

HUDSON-2

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

EMBEDDED CTRL

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SBCLK/14M_25M_48M_OSC

U

USB MISCUSB 1.1USB 2.0USB 3.0

C_PWM0/EC_TIMER0/GPIO197

E EC_PWM1/EC_TIMER1/GPIO198

E

C_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

2010/

USB_

FSD1P/GPIO186

USB_

FSD0P/GPIO185

USB_ USB_

USBSS_

USB_ USB_

USB_

USB_ USB_

USB_

USB_ USB_

USB_

USB_ USB_

USB_

CL2/GPIO193

S

SDA2 SCL3_LV/GPIO195 S

DA3_LV/GPIO196

KSI_0/GPIO201

K

SI_1/GPIO202 SI_2/GPIO203

K

KSI_3/GPIO204

SI_4/GPIO205

K

KSI_5/GPIO206

SI_6/GPIO207

K

SI_7/GPIO208

K

08/04 2011/12/31

USB_

USB_ USB_

Com

RCOMP

FSD1N

FSD0N

HSD13P HSD13N

HSD12P HSD12N

HSD11P HSD11N

HSD10P HSD10N

HSD9P HSD9N

HSD8P HSD8N

HSD7P HSD7N

HSD6P HSD6N

HSD5P HSD5N

HSD4P HSD4N

HSD3P HSD3N

HSD2P HSD2N

HSD1P HSD1N

HSD0P HSD0N

CALRP CALRN

SS_TX3P SS_TX3N

SS_RX3P

SS_RX3N

SS_TX2P SS_TX2N

SS_RX2P

SS_RX2N

SS_TX1P SS_TX1N

SS_RX1P

SS_RX1N

SS_TX0P SS_TX0N

SS_RX0P

SS_RX0N

/GPIO194

G8

USB_

B9

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

U

K12

U

K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

U

F8

U

E8

U

C6

U

A6

U

C5

U

A5

U

C1

U

C3

USB20_P0

E1

U

E3

USBSS_

C16

USBSS_

A16

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

USB30_M

J16

USB30_M

H16

USB30_M

J15

USB30_M

K15

870 10K_0402_5%

R

H19

872 10K_0402_5%

R

G19

APU_

G22

APU_

G21 E22 H22

EC_

J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

pal Secret Data

Deciphered Date

SB20_P10 SB20_N10

SB20_P4 SB20_N4

SB20_P3 SB20_N3

SB20_P2 SB20_N2

SB20_P1 SB20_N1

SB20_N0

D

RCOMP

R

863 11.8K_0402_1%

CALRP

864 1K_0402_1%M3@

R

CALRN

R

865 1K_0402_1%

TX_DRX_P0 TX_DRX_N0

RX_DTX_P0 RX_DTX_N0

1 2

SIC SID

PWM2

D

1 2

U

SB20_P10 34 SB20_N10 34

U

SB20_P4 31 SB20_N4 31

U

SB20_P3 32 SB20_N3 32

U

SB20_P2 27

U U

SB20_N2 27

SB20_P1 30

U

SB20_N1 30

U

SB20_P0 34 SB20_N0 34

U

1 2 1 2

M3@

39 0.1U_0402_16V7K

C

1 2

37 0.1U_0402_16V7K

C

1 2

M3@

APU_ APU_

EC_

USB1

CardReder

WLAN(BT)

CMOS

USB3

USB2

M3@

SIC 6,8 SID 6,8

PWM2 16

E

Hudson-M2 Hudson-M3 E

HCI CTL DEV 22, Fn 2 <Disable CTL of M2>

Hudson-M2/M3 EHCI CTL DEV 19, Fn 2

Hudson-M2/M3 EHCI CTL DEV 18, Fn 2

H_VDD_11_SSUSB_S

+FC

TX_C_DRX_P0 34

USB30_M USB30_M

SB30_MRX_DTX_P0 34

U

SB30_MRX_DTX_N0 34

U

Ti

tle

Hudson-M2/M3-A

Size Document Number Rev

Custom

QB

Date: Sheet

TX_C_DRX_N0 34

Compal E

L50 LA-7551P

On board US

lectronics, Inc.

CPI/USB/EC

E

B Conn

14 53Friday, April 29, 2011

xHCI CTL DEV 16, Fn 1 x

HCI CTL

DEV 16, Fn 0

Hudson-M3 xHCI CTL DEV 16, Fn 1 x

HCI CTL

DEV 16, Fn 0

of

1.0

A

STX_DRX_P033

SATA_ SATA_

HDD1

ODD

1 1

2 2

AVDD_SATA

+

3 3

STX_DRX_N033

SATA_

DTX_C_SRX_N033

SATA_

DTX_C_SRX_P033

SATA_

STX_DRX_P133 STX_DRX_N133

SATA_

DTX_C_SRX_N133

SATA_ SATA_

DTX_C_SRX_P133

+3V

S

W

B

8991K_0402_1%

R

12

9001K_0402_1%

R

12

LED#32

SATA_

902 10K_0402_5%

R

1 2

T40T40

N32

BT_O

L_OFF#32

1 2

R13 10K_0402_5%R13 10K_0402_5%

1 2

R

14 10K_0402_5%

1 2

15 10K_0402_5%

R

1 2

16 10K_0402_5%

R

SATA_

BT_O

L_OFF#

W

CALRP

CALRN

LED#

N

U

25B

AK19

SATA_

TX0P

AM19

TX0N

SATA_

AL20

RX0N

SATA_

AN20

SATA_

RX0P

AN22

SATA_

TX1P

AL22

TX1N

SATA_

AH20

RX1N

SATA_

AJ20

RX1P

SATA_

AJ22

TX2P

SATA_

AH22

SATA_

TX2N

AM23

RX2N

SATA_

AK23

SATA_

RX2P

AH24

SATA_

TX3P

AJ24

TX3N

SATA_

AN24

SATA_

RX3N

AL24

SATA_

RX3P

AL26

TX4P

SATA_

AN26

SATA_

TX4N

AJ26

SATA_

RX4N

AH26

RX4P

SATA_

AN29

SATA_

TX5P

AL28

TX5N

SATA_

AK27

RX5N

SATA_

AM27

SATA_

RX5P

L29

A

NC6

1

AN3

NC7

A

L31

NC8

L33

A

NC9

AH33

0

NC1

AH31

NC1

1

AJ33

2

NC1

AJ31

NC1

3

AF28

SATA_

CALRP

AF27

CALRN

SATA_

AD22

ACT#/GPIO67

SATA_

AF21

SATA_

X1

AG21

SATA_

X2

AH16

F

ANOUT0/GPIO52

AM15

F

ANOUT1/GPIO53

AJ16

F

ANOUT2/GPIO54

AK15

N0/GPIO56

FANI

AN16

FANI

N1/GPIO57

AL16

N2/GPIO58

FANI

K6

T

EMPIN0/GPIO17 1

K5

T

EMPIN1/GPIO17 2

K3

TEMPIN2/GPIO1 73

M6

TEMPIN3/TALERT#/GPIO174

HUDSON-M2_FCBGA656

M2@

HUDSON-2

SERIAL ATA

HW MONITOR

C

S

D_CLK/SCL K_2/GPIO73

D_CMD/SL OAD_2/GPIO74

S

D_DATA0/S DATI_2/GPIO77

D_DATA1/S DATO_2/GPIO78

S

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

M_RST#/SPI_WP#/GPIO161

RO

VG VG

M

V

IN3/SDATO_1 /GPIO178

V

VIN4/SLOAD_ 1/GPIO179

V

VI

N6/GBE_STAT3/GPIO181

VI

N7/GBE_LED3/GPIO182

D_CD/GPIO75

S

D_WP/GPIO7 6

S

SD_

DATA2/GPIO79 DATA3/GPIO80

SD_

BE_COL

G

BE_CRS

G

BE_MDCK

BE_MDIO

G

BE_RXCLK

BE_RXD3

G

BE_RXD2

G G

BE_RXD1

G

BE_RXD0

G

BE_RXCTL/RXDV

BE_RXERR

G

BE_TXCLK

G

BE_TXD3

G

BE_TXD2 BE_TXD1

G

BE_TXD0

G

BE_TXCTL/TXEN

BE_PHY_PD

G

BE_PHY_RST#

BE_PHY_INTR

G

PI_DI/GPIO164

S

PI_DO/GPIO163

S

PI_CLK/GPIO162

S

PI_CS1#/GPIO165

A_RED

VG

A_GREEN

A_BLUE

VG

A_HSYNC/GPO68

VG VG

A_VSYNC/GPO69

A_DDC_SDA/GPO70 A_DDC_SCL/GPO71

A_DAC_RSET

VG

AUX_

VGA_CH_P

VGA_CH_N

AUX_

AUXCAL

L_VGA_L0P

M

L_VGA_L0N

M

L_VGA_L1P L_VGA_L1N

M

L_VGA_L2P L_VGA_L2N

M

L_VGA_L3P

M

L_VGA_L3N

L_VGA_HPD/GPIO229

V

IN0/GPIO175

V

IN1/GPIO176

IN2/SDATI_1 /GPIO177

IN5/SCLK_1/GP IO180

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

V6 V5 V3 T6 V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U2

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG AH1 A2 G2 L4

G

BE_COL BE_CRS

G

BE_MDIO

G

BE_RXERR

G

BE_PHY_INTR

G

H_SPI_CLK_R

FC

R

896 150_0402_1%

1 2

897 150_0402_1%

R

1 2

R

898 150_0402_1%

1 2

R

901 715_0402_1%

1 2

AUXCAL

1 2

8

903 100_0402_1%

R

CH_CRT_HPD

F

1 2

R

5 10K_0402_5%

1 2

6 10K_0402_5%

R

1 2

R

7 10K_0402_5%

1 2

8 10K_0402_5%

R

1 2

9 10K_0402_5%

R

1 2

10 10K_0402_5%

R

1 2

R

11 10K_0402_5%@R11 10K_0402_5%@

1 2

R

12 10K_0402_5%

16

0 8 7

35 0_0402_5%@R35 0_0402_5%@

R

D

SYS BIO

VALW

+3

SPI_MISO

FCH_ FCH_

SPI_MOSI

1 2

FCH_

SPI_CS1#

FCH_

SPI_WP#

M

L_VGA_AUXP_C 8

ML_VGA_AUXN_C 8

M

L_VGA_TXP0 8

M

L_VGA_TXN0 8 L_VGA_TXP1 8

M

L_VGA_TXN1 8

M M

L_VGA_TXP2 8 L_VGA_TXN2 8

M M

L_VGA_TXP3 8 L_VGA_TXN3 8

M

CH_CRT_HPD 10

F

S ROM

1 2

R

626 1K_0402_5%

1 2

R

934 10K_0402_5%

1 2

@

935 10K_0402_5%

R

@

@ @

@

SPI_CLK

FCH_

F

CH_CRT_R 27

F

CH_CRT_G 27

CH_CRT_B 27

F

CH_CRT_HSYNC 27

F

CH_CRT_VSYNC 27

F

CH_CRT_DDC_SDA 27 CH_CRT_DDC_SCL 27

F

+VDDAN_11_M

10/2011: Please enabled integrated pull-up/pul l-down and left unconnected.

GL-02/

L

FCH_

SPI_CS1# SPI_WP#

FCH_ FCH_

SPI_HOLD#

FC

H_SPI_CLK

dd for EMI 201011291330

A

hange to PD 20101112

C

dd SYS BIOS ROM

A 20101111

CH_CRT_HPD

F

E

8

U2

1

CS#

3 7 4

@

BE_MDIO

G

BE_PHY_INTR

G

BE_COL

BE_CRS

G

BE_RXERR

VCC

#

WP

SCL

HO

LD# D

GN

MX25L1606EM2I-12G SOP 8P

SA000041N00

6

@R36

@

R3

1 2

10_0402_5%

8

@

H_SPI_CLK

FC

6

K

FCH_

5

SI

FCH_

2

SO

3

@C23

@

C2

1 2

10P_0402_50V8J

1 2

R

891 10K_0402_5%

1 2

R

892 10K_0402_5%

1 2

R

893 10K_0402_5%

1 2

R

894 10K_0402_5%

1 2

895 10K_0402_5%

R

+

FCH_VDDAN_33_DAC_R

12

R

90410K_0402_5%

@

4660.1U_0402_16V4Z

C

12

SPI_MOSI SPI_MISO

+3

VALW

+3

4 4

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

Hudson-M2/M3-S

QB

L50 LA-7551P

lectronics, Inc.

ATA/GBE/HWM

15 53Wednesday, April 27, 2011

E

1.0

of

A

STRA

P PINS

B

C

D

E

VALW

R 909 10K_0402_5%R909 10K_0402_5%

12

R

R 920 10K_0402_5%

920 10K_0402_5%

12

_PWM2

EC

L

PC ROM

DEFAULT

SPI ROM

+3

VALW

12

@

PC

I_AD23

DISABLE PCI MEM BOOT

FAULT

DE

ENABLE PCI MEM BOOT

CI_CLK1

P

1 1

2 2

P

L

EC_

RT

PU HIGH

PU LOW

CI_CLK113

CI_CLK313

CI_CLK413

PC_CLK0_EC13,36

PC_CLK113

PWM214

C_CLK13,36

A

LLOW

LL

P

CIE GEN2

DE

FAULT

ORCE

F

LL

P

CIE GEN1

+3V

@

DEBUG STRA

F

CH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

3 3

LL

PU HIGH

PULL LOW

S

12

R 905 10K_0402_5%R905 10K_0402_5%

R

R 915 10K_0402_5%

915 10K_0402_5%

PC

USE PCI PLL

DE

BYPASS PCI

CI_CLK3

P

USE DEBUG STRAPS

GNORE

I DEBUG STRAP

DE

I_AD27PCI_AD26

FAULT

PLL

FAULT

+3V

@

S

12

R

R 906 10K_0402_5%

906 10K_0402_5%

R 917 10K_0402_5%R917 10K_0402_5%

PS

DISABLE ILA AUTORUN

DE

ENABLE IL AUTORUN

P

NON_ CLOCK MODE

FUSI CLOCK MODE

DE

FAULT

A

CI_CLK4 LPC_CLK0

EC

FUSION

ENABLED

ON

EC DI

SABLED

FAULT

@

+3V

DE

S

R

R 907 10K_0402_5%

907 10K_0402_5%

12

R 918 10K_0402_5%R918 10K_0402_5%

12

PC

I_AD25 PCI_AD24

USE FC PLL

FAULT

DE

BYPASS FC PLL

FAULT

+3

@

VALW

12

R

R 908 10K_0402_5%

908 10K_0402_5%

R 919 10K_0402_5%R919 10K_0402_5%

CL

KGEN

ENABLED

DE

FAULT

KGEN

CL DISABLE

+3

@

USE DEFAULT PCIE STRAPS

FAULT

DE

USE EEPROM PCI

E STRAPS

R

R 910 10K_0402_5%

910 10K_0402_5%

R

R 921 2.2K_0402_5%

921 2.2K_0402_5%

C_CLKLPC_CLK1

RT

S5 PLUS MODE DI

SABLED

DE

FAULT

S5 PLUS MODE ENABLED

+3

VALW

12

@

R 911 10K_0402_5%R911 10K_0402_5%

R

R 922 2.2K_0402_5%

922 2.2K_0402_5%

S

+3V

AP2301GN-HF_SOT23-3

1VS

+1.

AP2301GN-HF_SOT23-3

VGA_PD: Support MLDAC power save if not conne ct 0: MLDAC power on 1: MLDAC power off

Check VGA_PD states

A_PD14

VG

I

f support ML DAC power down when no VGA plug

L47

1 2

FB

MA-L11-201209-221LMA30T_0805

220 ohm

9

@Q39

@

Q3

3 1

2

A_PD#

VG

@Q40

@

A_PD#

VG

AO3413 Vgs(max)=1V

1 2

912 0_0402_5%

R

0

Q4

3 1

2

R

1K_0402_5%

923

@

1 2

925

1212

R

C

2.2K_0402_5%

C

1 2

FB

MA-L11-201209-221LMA30T_0805

1 2

R

913 0_0402_5%

@

1 2

1U_0402_6.3V6K

30m

+FCH_VDDAN_33_D

@

1 2

220 ohm

@

0_0402_5%

R924

5

1

2

L48

12

34

il

AC

R

100K_0402_5%

916

Q

DMN66D0LDW-7_SOT363-6

41B

+FCH_VDDAN_33_D

C1209

+FCH_VDDAN_11_M

30mil

+3V

S

12

1

2

2U_0603_6.3V4Z

2.

R914

100K_0402_5%

1

@

2

AC_R

C1210

1

2

1U_0402_16V4Z

0.

LDAC

VG

A_PD#

Q

DMN66D0LDW-7_SOT363-6

61

41A

2

1U_0402_6.3V6K

C1211

_AD2713

PCI

_AD2613

PCI

_AD2513

PCI

_AD2413

PCI

_AD2313

R

4 4

A

R 926 2.2K_0402_5%

926 2.2K_0402_5%

12

@

R

R 927 2.2K_0402_5%

927 2.2K_0402_5%

12

@

R 928 2.2K_0402_5%

928 2.2K_0402_5%

12

@

R

R 929 2.2K_0402_5%

929 2.2K_0402_5%

12

@

B

R

R 930 2.2K_0402_5%

930 2.2K_0402_5%

12

@

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal E

Hudson-M2/M3-S

QB

L50 LA-7551P

lectronics, Inc.

TRAP

16 53Wednesday, April 27, 2011

E

1.0

of

A

C1219 / C1247 Change to SE00000I10

C1218 / 20101228

1 2

+3V

S

1 1

+FCH_VDDAN_33_D

R

+3V

S

VALW

+3

2 2

DDAN_33_USB

+V

ch 20110212

S

+3V

S

3 3

FCH M2 - BOM option

For VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S Connected to VSS.

4 4

L3

1 2

M

BK1608221YZF_2P

hm

220 o

AC_R

+FC

1 2

19 0_0603_5%

L4

@

1 2

M

BK1608221YZF_2P

220 ohm

L6

M3@

1 2

M

BK1608221YZF_2P

220 ohm

L7

1 2

0_0603_5%

ange to 0ohm-AMD request

L15

1 2

M

BK1608221YZF_2P

220 ohm

L22

1 2

BK1608221YZF_2P

M

220 ohm

M2@

1275

1281

C

C 0_0402_5%

0_0402_5%

21

1281

C

C 0_0402_5%

0_0402_5%

21

+V

DDPL_3.3V

2.2U_0603_6.3V4Z

C

C 1222

1222

1

2

H_VDDPL_33_MLDAC

+FCH_VDDPL_33_SSUSB_S

+FCH_VDDPL_33_U

C

C 1238

1238

1

@

M3

2

C

C 1248

1248

1

2

DDPL_33_PCIE

+V

C

C 1258

1258

1

2

DDPL_33_SATA

+V

C

C 1266

1266

1

2

A

C

C 1227

1227

2.2U_0603_6.3V4Z

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C

C 1239

1239

@

M3

SB_S

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C

C 1249

1249

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C

C 1259

1259

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C

C 1267

1267

0.1U_0402_16V7K

C

C 1229

1229

1

2

0.1U_0402_16V7K

C

C 1231

1231

VDDPL_33_SSUSB_S

1

For Hudson3 USB3.0 only For Hudson2, connect to GND

2

O_CAP: Internally generated 1.8V

LD supply for the RGB outputs

+FCH_VDDAN_11_M

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

2

+1

.1VALW

S

20 0_0603_5%

R

+V

DDPL_3.3V

+FCH_VDDPL_33_M

LDAC

VALW

+3

FB

+1

.1VALW

+1

LDAC

For A11: Cap = 1nF For A12, Cap = DNI

L24

VDDPL_11_DAC_L

+

1 2

M

BK1608221YZF_2P

220 ohm/2A

L54

1 2

MA-L11-201209-221LMA30T_0805

220 ohm/2A

L57

1 2

BK1608221YZF_2P

M

220 ohm

L59

1 2

BK1608221YZF_2P

M

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

+FCH_VDD_11_SSUSB_S

M3@

L61

FBMA-L11-201209-221LMA30T_0805

12

42 ohm/4A

B

131mA

22U_0805_6.3V6M

C

C 1218

1218

1

2

47mA

20m

A

1 2

22 0_0402_5%

R

20mA

1 2

R

23 0_0402_5%

200mA

+FCH_VDDAN_33_D

936 0_0402_5%M2@

R

+FC

H_VDDPL_33_USB_S

DDPL_33_PCIE

+V

DDPL_33_SATA

R

1148 0_0603_5%

R

658mA

140mA

197mA

1 2

R

1149 0_0603_5%

1 2

R1150 0_0603_5%

AC_R

20mA

12

17mA

A

43m

93mA

7mA

1 2

24 0_0402_5%

226mA

1 2

R

1242 change to 2.2uf-AMD request

20110212

1U_0402_6.3V6K

C

1253

1254

1

2

2.2U_0603_6.3V4Z

C

1262

1263

1

2

2.2U_0603_6.3V4Z

C

1268

1269

1

2

282mA

M3@

M3

424mA

M3@

B

+V

DDIO_33_PCIGP

0.1U_0402_16V7K

0.1U_0402_16V7K C

C

1220

1228

1

2

+V

DDPL_33_DAC

DDPL_33_ML

+V

+FCH_VDDPL_33_SSUSB_S

@

1 2

C

1232 2.2U_0603_6.3V4Z

+V

+VDDAN_11_M

0.1U_0402_16V7K

C

4.7U_0603_6.3V6K

1240

1241

1242

1

2

1 2

R

945 0_0402_5%

+V

DDAN_33_USB

10U_0603_6.3V6M

1U_0402_6.3V6K

C

1256

1255

1

2

DDAN_11_USB_S

+V

0.1U_0402_16V7K

VDDCR_1.1V_USB

+

0.1U_0402_16V7K

C

C 1270

1270

1

2

VDDAN_SSUSB

+

0.1U_0402_16V7K

1U_0402_6.3V6K

C

1274

1273

1

@

M3

2

+VDDCR_11_SSUSB

10U_0603_6.3V6M

C

C 1278

1278

1

M3@

2

M3@

C

C 1279

1279

M3

1

2

0.1U_0402_16V7K

C

C 1221

1221

1

2

DDPL_11_DAC

2.2U_0603_6.3V4Z

10U_0603_6.3V6M

0.1U_0402_16V7K

C

C 1257

1257

1

2

0.1U_0402_16V7K

C

C 1275

1275

1

@

2

1U_0402_6.3V6K

0.1U_0402_16V7K

C

C 1280

1280

1

M3@

2

10m

10mils

L

20mils

30mils

10mils

20mils

30mils

C

C 1281

1281

1

M3@

2

ils

C

U

25C

AB17

DDIO_33_PCIGP_1

V

AB18

V

DDIO_33_PCIGP_2

AE9

DDIO_33_PCIGP_3

V

AD10

V

DDIO_33_PCIGP_4

AG7

DDIO_33_PCIGP_5

V

AC13

DDIO_33_PCIGP_6

V

AB12

V

DDIO_33_PCIGP_7

AB13

DDIO_33_PCIGP_8

V

AB14

V

DDIO_33_PCIGP_9

AB16

DDIO_33_PCIGP_10

V

H24

V

DDPL_33_SYS

V22

V

DDPL_33_DAC

U22

DDPL_33_ML

V

T22

V

DDAN_33_DAC

L18

DDPL_33_SSUSB_S

V

D7

DDPL_33_USB_S

V

AH29

DDPL_33_PCIE

V

AG28

V

DDPL_33_SATA

M31

O_CAP

LD

V21

DDPL_11_DAC

V

Y22

DDAN_11_ML_1

V

V23

V

DDAN_11_ML_2

V24

DDAN_11_ML_3

V

V25

V

DDAN_11_ML_4

AB10

V

DDIO_33_GBE_S

AB11

VDDCR_11_G

AA11

AA10

M10

M12

M11

M14

M17

0.1U_0402_16V7K

AA9

G7

H8

J8 K8 K9

M9

N9

N10

N12

U12 U13

T12 T13

P16

N14 P13 P14

N16 N17 P17

BE_S_1

VDDCR_11_G

BE_S_2

O_GBE_S_1

VDDI

O_GBE_S_2

VDDI

V

DDAN_33_USB_S_1 DDAN_33_USB_S_2

V V

DDAN_33_USB_S_3

V

DDAN_33_USB_S_4 DDAN_33_USB_S_5

V

DDAN_33_USB_S_6

V

DDAN_33_USB_S_7

V V

DDAN_33_USB_S_8 DDAN_33_USB_S_9

V V

DDAN_33_USB_S_10 DDAN_33_USB_S_11

V V

DDAN_33_USB_S_12

V

DDAN_11_USB_S_1 DDAN_11_USB_S_2

V

VDDCR_11_USB_S_1 VDDCR_11_U

SB_S_2

VDDAN_11_SSUSB_S_1

DDAN_11_SSUSB_S_2

V

DDAN_11_SSUSB_S_3

V V

DDAN_11_SSUSB_S_4 DDAN_11_SSUSB_S_5

V

VDDCR_11_SSU VDDCR_11_SSUSB_S_2 VDDCR_11_SSU VDDCR_11_SSUSB_S_4

HUDSON-M2_FCBGA656

M2@

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SB_S_1

SB_S_3

C

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

50mils

DDXL_33_S

T14 T17 T20 U1

6 8

U1

4

V1 V1

7 0

V2 Y1

7

20mils

H26 J25 K24 L22 M22 N21 N22 P22

50mils

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

60mils

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

10mils

N18 L19 M18 V12 V13 Y12 Y13 W11

10mils

G24

10mils

0

N2 M2

0

10mils

J24

10mils

M8

10mils

AA4

pal Secret Data

Com

Deciphered Date

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7

CORE S0

VDDCR_11_8 VDDCR_11_9

V

DDAN_11_CLK_1

V

DDAN_11_CLK_2

V

DDAN_11_CLK_3 DDAN_11_CLK_4

V

DDAN_11_CLK_5

V V

DDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

V

DDAN_11_CLK_7 DDAN_11_CLK_8

V

DDAN_11_PCIE_1 DDAN_11_PCIE_2

V

DDAN_11_PCIE_3

V V

DDAN_11_PCIE_4 DDAN_11_PCIE_5

V

DDAN_11_PCIE_6

V

DDAN_11_PCIE_7

V V

DDAN_11_PCIE_8

DDAN_11_SATA_1

V V

DDAN_11_SATA_4 DDAN_11_SATA_2

V V

DDAN_11_SATA_3 DDAN_11_SATA_5

V V

DDAN_11_SATA_6 DDAN_11_SATA_7

V

DDAN_11_SATA_8

V V

DDAN_11_SATA_9

DDAN_11_SATA_10

V

DDIO_33_S_1

V

DDIO_33_S_2

V

DDIO_33_S_3 DDIO_33_S_4

V

DDIO_33_S_5

V V

DDIO_33_S_6 DDIO_33_S_7

V V

DDIO_33_S_8

V

VDDCR_11_S_1 VDDCR_11_S_2

V

DDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

2010/

08/04 2011/12/31

C

C 1213

1213

C

C 1223

1223

C

C 1233

1233

C

C 1243

1243

C

C 1250

1250

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

+

+V

+

1U_0402_6.3V6K

C1214

1

2

+

1.1VS_CKVDD

1U_0402_6.3V6K

C1224

1

2

PCIE_VDDR_FCH

+

1U_0402_6.3V6K

C1234

1

2

+

AVDD_SATA

1U_0402_6.3V6K

C1244

1

2

+VDDIO_33_S

1U_0402_6.3V6K

C1251

1

2

DDXL_3.3V

+V

VDDCR_1.1V

DDPL_1.1V

DDAN_33_HWM

VDDIO_AZ

D

+

VCC_FCH_R

1007mA

0.1U_0402_16V7K

0.1U_0402_16V7K C1217

C1216

340mA

0.1U_0402_16V7K

0.1U_0402_16V7K C1226

C1226

1088mA

0.1U_0402_16V7K

0.1U_0402_16V7K C1236

C1236

1337mA

0.1U_0402_16V7K

0.1U_0402_16V7K C1246

C1246

1U_0402_6.3V6K

C1282

0.1U_0402_16V7K

0.1U_0402_16V7K C1261

C1261

1U_0402_6.3V6K

C1265

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C1272

C1272

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C1473

C1473

C1217

1

2

1.1VS_CKVDD

+

0.1U_0402_16V7K

0.1U_0402_16V7K C1230

C1230

1

2

PCIE_VDDR_FCH

+

0.1U_0402_16V7K

0.1U_0402_16V7K C1237

C1237

1

2

+

AVDD_SATA

0.1U_0402_16V7K

0.1U_0402_16V7K C1247

C1247

1

2

59mA

1U_0402_6.3V6K

26 0_0402_5%

R

1

2

5mA

2.2U_0603_6.3V4Z

M

1

2

A

187m

2.2U_0603_6.3V4Z

1

2

70mA

0.1U_0402_16V7K

M

1

2

12mA

0.1U_0402_16V7K

27 0_0402_5%

R

1

2

C

C 1215

1215

C

C 1225

1225

C

C 1235

1235

C

C 1245

1245

C

C 1252

1252

C

C 1260

1260

C

C 1264

1264

C

C 1271

1271

C

C 1472

1472

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

26mA

R28 0_0402_5%R28 0_0402_5%

1 2

1276 2.2U_0603_6.3V4Z

C

1 2

C1277 0.1U_0402_16V7KC1277 0.1U_0402_16V7K

D

1 2

2.2U_0603_6.3V4Z

22U_0805_6.3V6M

R

937 0_0805_5%

C1219

1

2

1 2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z 25 0_0603_5%

25 0_0603_5%

R

1 2

2.2U_0603_6.3V4Z

R

938 0_0805_5%

1 2

22U_0805_6.3V6M

941 0_0805_5%

R

+3

1 2

c

hange to four 1uf-AMD req uest

20110212

+3

L28

1 2

BK1608221YZF_2P

220 ohm

+1

1 2

R

1145 0_0603_5%

+1

L29

1 2

BK1608221YZF_2P

220 ohm

VALW

+3

1 2

+3V

1 2

Ti

Title

Size Document Number Rev

Custom

Date: Sheet

+1.

1VS

A3

3

B7

B1

1VS

+1.

1VS

+1.

1VS

+1.

VALW

.1VALW

D reply:

AM VDDAN_33_HWM_S: Please connect it to +3 .3V_S 5 directly if HWM is not use d.

S

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

tle

QB

3

D9

3

D1

E5

E1

2

E1

6 9

E2

F7

F9 F11 F13 F16 F17 F19 F23 F25 F29

G6

6

G1

2

G3

2

H1 H1

5 9

H2

J6

J9 J10 J13 J28 J32

K7

K1

6 7

K2

8

K2

L6 L12 L13 L15 L16 L21

M1

3 6

M1

1

M2 M2

5

N6

N1

1 3

N1 N2

3

N2

4 2

P1

8

P1

0

P2 P2

1 1

P3 P3

3

R4

R1

1

R2

5 8

R2 T11 T16 T18

N8

K2

5

H25

nnected to VSS through a dedicated via.

Co

Compal E

Hudson-M2/M3-P

L50 LA-7551P

E

U

25E

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_

VSSXL

VSSPL

HUDSON-M2_FCBGA656

M2@

GROUND

HWM

VSSANQ

_SYS

lectronics, Inc.

OWER/GND

E

VSSPL

VSSAN_

VSSI

_DAC

O_DAC

EFUSE

17 53Friday, April 29, 2011

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DAC

T25 T27 U6 U1

4 7

U1

0

U2 U2

1

U3

0

U3

2

1

V1

6

V1 V1

8 W4 W6

5

W2 W2

8

4

Y1 Y1

6

8

Y1 AA6 AA1

2 3

AA1

4

AA1

6

AA1 AA1

7 5

AA2

8

AA2

0

AA3

2

AA3 AB2

5 AC6 AC1

8

AC2 AD2

7 AE6

5

AE1 AE2

1

8

AE2 AF8 AF12 AF16 AF33 AG

30 32

AG AH5 AH1

1

8

AH1 AH1

9

1

AH2 AH2

3 AH2

5

7

AH2

18

AJ

28

AJ AJ

29

1

AK2 AK2

5

L18

A AM

21

AM

25 AN1 AN1

8 8

AN2 AN3

3

T21 L28 K33 N28

R6

1.0

of

A

G

FX PCIE LANE REVERSAL

E_FTX_C_GRX_P[0..7]

PCI

E_FTX_C_GRX_P[0..7]6

PCI

E_FTX_C_GRX_N[0..7]6

1 1

2 2

3 3

CLK_PEG_VGA13 CLK_PEG_VGA

PCI

E_FTX_C_GRX_N[0..7]

PCI

E_FTX_C_GRX_P0

PCI

E_FTX_C_GRX_N0

PCI

E_FTX_C_GRX_P1

PCI

E_FTX_C_GRX_N1

PCI

E_FTX_C_GRX_P2

PCI

E_FTX_C_GRX_N2

E_FTX_C_GRX_P3

PCI

E_FTX_C_GRX_N3

PCI

E_FTX_C_GRX_P4

PCI

E_FTX_C_GRX_N4

PCI

E_FTX_C_GRX_P5

PCI

E_FTX_C_GRX_N5

PCI

E_FTX_C_GRX_P6

PCI

E_FTX_C_GRX_N6

E_FTX_C_GRX_P7

PCI

E_FTX_C_GRX_N7

PCI

#13

12

10K_0402_5%VGA@

R389

VGA

_RST#

AA38

Y37

Y35

W36

W38

V37

V35 U36

U38 T37

T35 R36

R38 P37

P35 N36

N38

M37

M35

K37

K35

H37

H35

G36

G38

F37

F35 E37

AB35 AA36

AH16

AA30

L36

L38

J36

J38

U8A

PCI

E_RX0P

PCI

E_RX0N

E_RX1P

PCI

E_RX1N

PCI

E_RX2P

PCI

E_RX2N

E_RX3P

PCI

E_RX3N

PCI

E_RX4P

PCI

E_RX4N

PCI

E_RX5P

PCIE_RX5N

E_RX6P

PCI PCI

E_RX6N

PCI

E_RX7P

PCI

E_RX7N

E_RX8P

PCI

E_RX8N

PCI

E_RX9P

PCI

E_RX9N

PCI

E_RX10P E_RX10N

PCI

E_RX11P

PCI

E_RX11N

PCI

E_RX12P

PCI

E_RX12N

E_RX13P

PCI

E_RX13N

PCI

E_RX14P

PCI

E_RX14N

PCIE_RX15P

E_RX15N

PCI

CLOCK

PCI

E_REFCLKP

PCI

E_REFCLKN

RGOOD

PW

PERSTB

2160809000A

VGA@

11SEYMOU_FCBGA962

B

CIE_GTX_C_FRX_P[0..7]

P

CIE_GTX_C_FRX_N[0..7]

P

E_TX0P

PCI

E_TX0N

E_TX1P

PCI

E_TX1N

PCI

E_TX2P

PCI

E_TX2N

E_TX3P

PCI

E_TX3N

PCI

E_TX4P

PCI EXPRESS INTERFACE

PCI

E_TX4N

PCI

E_TX5P

PCIE_TX5N

E_TX6P

PCI PCI

E_TX6N

PCI

E_TX7P

PCI

E_TX7N

E_TX8P

PCI

E_TX8N

PCI

E_TX9P

PCI

E_TX9N

PCI

E_TX10P E_TX10N

PCI

E_TX11P

PCI

E_TX11N

PCI

E_TX12P

PCI

E_TX12N

E_TX13P

PCI

E_TX13N

PCI

E_TX14P

PCI

E_TX14N

PCIE_TX15P

E_TX15N

PCI

CALIBRATION

E_CALRP

PCI

E_CALRN

PCI

Y32

W33 W32

U33 U32

U30 U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30

Y29

PCI

E_GTX_FRX_N0

PCI

E_GTX_FRX_P1

PCI

E_GTX_FRX_N1

PCI

E_GTX_FRX_P2

PCI

E_GTX_FRX_N2

E_GTX_FRX_P3

PCI

E_GTX_FRX_N3

PCI

E_GTX_FRX_P4

PCI

E_GTX_FRX_N4

PCI

E_GTX_FRX_P5

PCI

E_GTX_FRX_N5

PCI

E_GTX_FRX_P6

PCI

E_GTX_FRX_N6

E_GTX_FRX_P7

PCI

E_GTX_FRX_N7

PCI

_PCIE_CALRP

VGA

VGA_PCIE_CALRN

PCI

E_GTX_FRX_P0

Y33

PCI

C580

C580 C291

C291

C247

C247 C473

C473

C572

C572 C288

C288

C579

C579 C316

C316

C287

C287 C228

C228

C224

C224 C576

C576

C295

C295 C472

C472

C242

C242 C468

C468

1 2

R388

R390

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

PCI

E_GTX_C_FRX_P[0..7] 6

E_GTX_C_FRX_N[0..7] 6

0.1U_0402_16V7K

1.27K_0402_1%

2K_0402_1%

C

PCI

E_GTX_C_FRX_P0

PCI

E_GTX_C_FRX_N0

PCI

E_GTX_C_FRX_P1

PCI

E_GTX_C_FRX_N1

PCI

E_GTX_C_FRX_P2

PCI

E_GTX_C_FRX_N2

E_GTX_C_FRX_P3

PCI

E_GTX_C_FRX_N3

PCI

E_GTX_C_FRX_P4

PCI

E_GTX_C_FRX_N4

PCI

E_GTX_C_FRX_P5

PCI

E_GTX_C_FRX_N5

PCI

E_GTX_C_FRX_P6

PCI

E_GTX_C_FRX_N6

E_GTX_C_FRX_P7

PCI

E_GTX_C_FRX_N7

PCI

+1.0VSG

For UMA Mux.

D

<DIGON> Controls panel digital power on/off. Active High ,external PD need

U8G

LVDS CONTROL

LVTMDP

2160809000A

VGA@

11SEYMOU_FCBGA962

VARY

_BL

DI

GON

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

PE_GPI

PLT

O013

_RST#13,26,29,32

2.2K_0402_5%

ARY_BL>

<V LCD PWM (pulse width modulated) output to adjust LCD brightness Active High ,external PD need

R386

R386 R387

R387

12

2

1

1 2

R159

1 2 1 2

+3VSG

VGA@

U21

5

P

B

A

G

3

NC7SZ08P5X

@

0_0402_5%

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW AU35

AR37 AU39

AP35 AR35

AN36 AP37

37

@

R394

E

10K_0402_5%VGA@

10K_0402_5%VGA@ 10K_0402_5%VGA@

10K_0402_5%VGA@

_RST#

VGA

4

Y

_NL_SC70-5

4 4

curity Classification

Se

Is

sued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/12 2011/12/31

C

ompal Secret Data

C

Dec

iphered Date

Electronics, Inc.

Compal

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal

Vancouver_ PCIE / LVDS

QBL50 LA-7551P

E

1.0

of

18 53Wednesday, April 27, 2011

of

18 53Wednesday, April 27, 2011

of

18 53Wednesday, April 27, 2011

A

.8VSG

+1

L10

12

L11

12

L12

BLM18AG121SN1D_0603

VGA@

120ohm/0.3A

Setti

0

1

001

0

00

1

DNI

U_VID048

GP

+

DPLL_PVD D

10U_0603_6.3V6M

+

DPLL_VDDC

VG

1

2

Future ASIC call MLPS OLD ASIC is Fan PWM

12

trap Name Pin Straps description <all internal PD>

S

DEVICE_EN

VIP_

1 1

2 2

VSG

+3

3 3

4 4

(GENLK_VSYNC)

VGA_DIS

T

X_PWRS_ENB

T

X_DEEMPH_EN

IG[2]

CONF

IG[1]

CONF

IG[0]

BI

OS_ROM_EN

A

UD[1]

AUD(0)

BI

F_GEN2_EN GPIO2

RESERVED

(G

.8VSG

+1

˩˥˔ˠʳ˜˗

˩˥˔ˠʳ˜˗˩˥˔ˠʳ˜˗

X

76@

R

10K_0402_5%

12

426

427

76@

X

10K_0402_5%

R

12

433

432

395 10K_0402_5%VGA@

R

1 2

R

396 10K_0402_5%VGA@

1 2

R

397 10K_0402_5%VGA@

1 2

R

398 10K_0402_5%@R398 10K_0402_5%@

1 2

R

401 10K_0402_5%@R401 10K_0402_5%@

1 2

405 10K_0402_5%VGA@

R

1 2

406 10K_0402_5%@R406 10K_0402_5%@

R

1 2

R408 10K_0402_5%@R408 10K_0402_5%@

1 2

R

409 3K_0402_5%@R409 3K_0402_5%@

1 2

SM

_CK2

_DA2

SM

VRA

M

amsung

S

SA00004GS30 64M16x8 K4W1G1646G-BC11

amsung

S

SA000047QA0 128M16x8 K4W2G1646C-HC11

Hynix

SA000041S60 64M16x8 H5TQ1G63DFR-11C

Hynix

SA00003YO30 128M16x8 H5TQ2G63BFR-11C

X

TALOUT

27M

2

C353

C353 15P_0402_50V8J

15P_0402_50V8J

1

VGA@

IP Device Strap Enable indicates to the software driv er (Internal PD)

V

0:

Driver would ignore the value sampled on VHAD_0 during reset

V2SY

NC

VHAD_0 to determine whether or not a VIP slave device

1:

V

GA Disable determines (Internal PD)

0:

VGA Controller capacity enabled

GPIO9

: The device will not be recognized as the system’s VGA controller

1

T

ransmitter Power Saving Enable (Internal PD)

0: 50% Tx output swing

GP

IO0

1: full Tx output swing

P

CI Express Transmitter De-emphasis Enable (Int ernal PD)

0: Tx de-emphasis diabled

GP

IO1

1: Tx de-emphasis enabled

G

PIO13,12,11 (config 2,1,0) : (Internal PD)

a) If BIOS_ROM_EN = 1, then Config[2:0] defines

GPIO13

the ROM type.

GPIO12

b) If BIOS_ROM_EN = 0, then Config[2:0] defines

GP

IO11

the primary memory apertur e size.

E

nable external BIOS ROM device (Internal PD)

GP

IO22

0: Diable, 1: Enable

0

0: No audio function; 10: Audio for DisplayPort only;

HSY

NC

01: Audio for DisplayPort and HDMI if adapter is detected;

VSYNC

11: Audio for both DisplayPort and HDMI 0= A

dvertises the PCI-E device as 2.5 GT/s capable at power-on

1= Advertises the PCI-E device as 5.0 GT/s capable at power-o n

5.0 GT/s capability will be controlled by software

In

ternal use only. THIS PAD HAS AN INTERNAL

SYNC

H2

ENLK_CLK)

PULL-DOWN AND MUST BE 0 V AT RESET. The

GPIO8

pa

GPIO21

Location VRAM_ID3

d may be left unconnected

X

76@

R

10K_0402_5%

12

429

428

V

RAM_ID0

V

RAM_ID1

V

RAM_ID2

V

RAM_ID3

76@

X

10K_0402_5%

R

12

434

435

A_GPIO0

VG

A_GPIO1

VG VG

A_GPIO2

VG

A_GPIO3 A_GPIO4

VG

A_GPIO1 1

VG

A_GPIO1 2

VG VG

A_GPIO1 3 IO_22_ROMCSB

GP

R78 0_0402_5%VGA @R78 0_0402_5%VG A@

1 2

R

79 0_0402_5%VGA@

1 2

00

0

VGA@

12

R445 1M_0402_5%

VGA@

Y3

2 1

HZ_16PF_X5H027000FG1H

A

PIO5 fast-power reduction:

G HW control will casue display disturb should use SW method control

GPI

O6 voltage control signal ,No use can NC

G

PIO7 Controls backlight on/off.

Active High ,need external PD

if

GPIO22 High ,GPIO 11-13->CFG[0:2]

Config ROM type ,GPU has internal PD

G

PIO6,15,16,20 Voltage control signal GPIO6,15 no use can NC T

hermal monitor interrupt

ritical temperature fault

C

Reserved

External BIOS device ON(1)/OFF(0) inter PD

rnal Debug

Inte no use can floating ON(1)/OFF(0)

tereo Sync

S no use can NC

For ATI Cross fire no use can NC

VG

A_GPIO4

A_GPIO3

VG

VRAM_ID2 VRAM_ID1 VRAM_ID0

00

0

1

27M

CLK

2

C354

C354 12P_0402_50V8J

12P_0402_50V8J

1

VGA@

memor

y apertures CONFIG[3:0] 128 MB 000 256 MB 001 * 64 MB 010

S

M010030010

200ma 120ohm@100mhz DCR 0.2

.8VSG

+1

.0VSG

VGA@

18AG121SN1D_0603

BLM

AMD ref:470ohm/1A

VGA@ L11

VGA@

BLM18AG121SN1D_0603

AMD ref:470ohm/1A

1

0

10

+1.8VSG

B

ng

D

on't have this strap on

Whistler and Seymour

NC o

n Park, Robson and Seymour N

C on Park, Robson

NC on Park, Robson and Seymour

lobal Swap Lock on

G Multiple GPUs

ve to

Mo

K_AUX3P,DDCDATA_AUX3N,

DDCCL

VGA@

12

R

413 10K_0402_5%

U_VID148

T30T3

0

T32T3

2

T18T1

8 3

T33T3

4

T34T3

7

T17T1

R430 499_0402_1%VGA@R430 499_0402_1%VGA@

1 2

R431 249_0402_1%VGA@R431 249_0402_1%VGA@

1 2

C

335 0.1U_0402_16V4Z

1 2

VGA@

A@

VG

0.1U_0402_16V4Z

C

1

340

2

VG

A@

C

0.1U_0402_16V4Z

C

0.1U_0402_16V4Z 346

346

C

C 350

350

2

VG

A@

C

1U_0402_6.3V6K

C

1U_0402_6.3V6K

1

347

2

443

R

0_0402_5%

GPU_THERM_D+ GP

U_THERM_D-

SVDD

+T

1

VGA@

C

1U_0402_6.3V6K

C

1U_0402_6.3V6K

351

2

B

340

@

1

VGA@

2

10U_0603_6.3V6M

VGA@

C339

A@

C

C 345

345

1

2

VGA@

10U_0603_6.3V6M

1

2

RAM_ID0

V V

RAM_ID1

V

RAM_ID2

V

RAM_ID3

VG

A_GPIO0

VG

A_GPIO1

VG

A_GPIO2

VG

A_GPIO3 A_GPIO4

VG

GA_ENBKL

V

A_GPIO1 1

VG

A_GPIO1 2

VG

A_GPIO1 3

VG

GP

U_VID0

T

HM_ALERT#

U_VID1

GP

IO_22_ROMCSB

GP

VG

1U_0402_6.3V6K

1

2

XO

12

@

1 2

10mil

C

0.1U_0402_16V4Z

C

0.1U_0402_16V4Z 352

352

ROM

A@

C

C 341

341

_IN

_IN2

444

R

0_0402_5%

20mil

VGA_VREF

+

20mil

27M XTALOUT

U8B

AR8

NC_

AU8

NC_

AP8

NC_

AW8

NC_

AR3

NC_

AR1

NC_

AU1

VPDATA_0

D

AU3

D

VPDATA_1

AW3

D

VPDATA_2

AP6

VPDATA_3

D

AW5

VPDATA_4

D

AU5

D

VPDATA_5

AR6

VPDATA_6

D

AW6

VPDATA_7

D

AU6

D

VPDATA_8

AT7

D

VPDATA_9

AV7

D

VPDATA_10

AN7

D

VPDATA_11

AV9

D

VPDATA_12

AT9

D

VPDATA_13

AR10

VPDATA_14

D

AW10

VPDATA_15

D

AU10

D

VPDATA_16

AP10

N

C_DVPDATA_17

AV11

C_DVPDATA_18

N

AT11

N

C_DVPDATA_19

AR12

N

C_DVPDATA_20

AW12

N

C_DVPDATA_21

AU12

C_DVPDATA_22

N

AP12

N

C_DVPDATA_23

AJ21

SW

AK21

SW

AK26

SC

AJ26

SD

GENERAL PURPOSE I/O

AH20

GPI

AH18

GPI

AN16

GPI

AH23

GPI

AJ23

GPI

AH17

GPI

AJ17

GPI

AK17

GPI

AJ13

GPI

AH15

GPI

AJ16

GPI

AK16

GPI

AL16

GPI

AM16

GPI

AM14

GPI

AM13

GPI

AK14

GPI

AG30

GPI

AN14

GPI

AM17

GPI

AL13

GPI

AJ14

GPI

AK13

GPI

AN13

GPI

AM23

TAG_TRSTB

J

AN23

J

TAG_TDI

AK23

J

TAG_TCK

AL24

J

TAG_TMS

AM24

TAG_TDO

J

AJ19

G

ENERICA

AK19

G

ENERICB

AJ20

ENERICC

G

AK20

ENERICD

G

AJ24

ENERICE_HPD4

G

AH26

NC_GENERICF_HPD5

AH24

NC_GENERICG_HPD6

AK24

HP

AH13

VR

AM32

PLL_PVDD

D

AN32

PLL_PVSS

D

AN31

D

PLL_VDDC

CLK

AV33

XT

AU34

XT

AW34

XO_I

AW35

XO_I

AF29

DP

AG29

DMINUS

AK32

TS_FDO

AL31

TS

AJ32

SVDD

T

AJ33

SVSS

T

2160809000A11SEYMOU_FCBGA962

VGA@

MUTI GFX

DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK

APLOCKA APLOCKB

I2C

L A

O_0 O_1 O_2 O_3_SMBDATA O_4_SMBCLK O_5_AC_BATT O_6 O_7_BLON O_8_ROMSO O_9_ROMSI O_10_ROMSCK O_11 O_12 O_13 O_14_HPD2 O_15_PWRCNTL_0 O_16 O_17_THERMAL_INT O_18_HPD3 O_19_CTF O_20_PWRCNTL_1 O_21_BB_EN O_22_ROMCSB O_23_CLKREQB

D1

EFG

75mA

PLL/CLOCK

125mA

ALIN ALOUT

N

N2

LUS

THERMAL

_A/NC

20mA

XCAP_DPA3P

T

XCAM_DPA3N

X0P_DPA2P

T T

X0M_DPA2N

DPA

X1P_DPA1P

T

X1M_DPA1N

T

X2P_DPA0P

T

X2M_DPA0N

T

XCBP_DPB3P

T

XCBM_DPB3N

X3P_DPB2P

T T

X3M_DPB2N

DPB

X4P_DPB1P

T

X4M_DPB1N

T

X5P_DPB0P

T

X5M_DPB0N

T

XCCP_DPC3P

T

XCCM_DPC3N

T

X0P_DPC2P

T

X0M_DPC2N

DPC

X1P_DPC1P

T

X1M_DPC1N

X2P_DPC0P

T

X2M_DPC0N

NC_

TXCDP_DPD3P

TXCDM_DPD3N

NC_

N

C_TX3P_DPD2P

N

C_TX3M_DPD2N

DPD

N

C_TX4P_DPD1P

N

C_TX4M_DPD1N

C_TX5P_DPD0P

N

C_TX5M_DPD0N

DAC1

70mA

100mA

DAC2

H2SYNC/GENLK_CLK

NC/GENLK_VSYNC

V2SY

VDD2DI/NC

100mA

VSS2D

100mA

2mA

A

A2VSSQ/TSVSSQ

DDC/AUX

DDC1

DDC2DATA

DDCCLK_AUX3P

DDCDA

NC_DDCCLK_AUX4P

DDCDATA_AUX4N

NC_

DDCCL

DDCDATA_AUX5N

DDC6

NC_DDCCLK_AUX7P

DDCDATA_AUX7N

NC_

HS VSY

R

AVD

AVSSQ

DD1DI

V

VSS1D

R2

B/NC

G2/

G2B/

B2/

B2B/

C/NC

MP/NC

CO

A2VDD/NC

2VDDQ/NC

R2SET/NC

DDC1CLK

DATA

AU AU

DDC2

AU AU

TA_AUX3N

K_AUX5P

DDC6

DATA

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD

39

R

AD

37

RB

AE36

G

AD

35

GB

37

AF

B

AE38

BB

H

AC36

YNC

V

SYNC

AC38

NC

AB34

SET

AD34

D

AE34

AC33 AC34

I

AC30

/NC

AC31

AD30

NC

AD31

NC

AF30

NC

AF31

NC

AC

32

AD32

NC

Y/

AF32

AD29 AC29

10mil

AG31 AG32

I/NC

10mil

AG33

10mil

AD33

AF33

AA29

R436 715_0402_1%VGA@R436 715_0402_1%VGA@

AM26 AN26

AM27

X1P

AL27

X1N

AM19

CLK

AL19

AN20

X2P

AM20

X2N

AL30 AM30

AL29 AM29

AN21 AM21

AJ30

CLK

AJ31

AK30 AK29

C

NC o

n Park,

Robson and Seymour

ot share via for other GND

N

SYNC

414 499_0402_1%

R

1 2

VGA@

VDD

+A

10mil

+

VDD1DI

VG

A@

1U_0402_6.3V6K

C

1

332

2

T2T2

B

ack compatibility(Manhattan)

T3T3

+

VDD2DI

R77 0_0402_5%@R77 0_0402_5%@

SS2DI

V

+

A2VDD

+

A2VDDQ

1 2

NC on Park, Robson and Seymour

C

1 2

R

209 0_0402_5%@R209 0_0402_5%@

1 2

R70 0_0402_5%@R70 0_0402_5%@

1 2

R

256 0_0402_5%@R256 0_0402_5%@

1 2

NC on Park, Robson and Seymour

D

VSG

+3

VG

A@

0.1U_0402_16V4Z

C

1

324

GP

U_THERM_D+

2200P_0402_50V7K

GP

GA_SMB_CK2

V

GA_SMB_DA2

V

U_THERM_D-

80 0_0402_5%@R80 0_0402_5%@

R

82 0_0402_5%@R82 0_0402_5%@

R

2200P_0402_50V7K

C

2

L8

18AG121SN1D_0603

BLM

10mil

A@

VG

1U_0402_6.3V6K

0.1U_0402_16V4Z

C329

C330

1

2

L9

VGA@

VG

A@

BLM

10U_0603_6.3V6M

0.1U_0402_16V4Z

C

C333

1

334

AMD ref:120ohm/0.3A

M010030010

S 200ma 120ohm@100mhz DCR 0.2

2

@

1U_0402_6.3V6K

C342

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A@

VGA@

VG

C

22U_0805_6.3V6M

331

MD ref:120ohm/0.3A

A

12

+1

18AG121SN1D_0603

+

VDD1DI

@

0.1U_0402_16V4Z

10U_0603_6.3V6M

C

C344

1

343

2

12

+1

.8VSG

NC o

.8VSG

+3VSG

.8VSG

+1

2010/07/12 2011/12/31

n Whistler

and Seymour

Whistler and Seymour Except A2VSSQ change to TSVSSQ, others are NC

mpal Secret Dat a

Co

Deciphered Date

D

E

xternal VGA Thermal Sensor

1 2

325

VGA@C325

VGA@

1 2

1

2

3

4

M1032ARMZ-2REEL_MSOP8

AD

R

392

4.7K_0402_5%

VGA@

U9

D

LK

VD

SC

D+

SD

ATA

ALER

D-

T#

ERM#

D

TH

GN

+3

VSG

R

393

4.7K_0402_5%

VGA@

1 2

_CK2

SM

_DA2

SM

AUD Strap

GPI

O8 Serial-ROM output from ROM. GPIO9 Serial-ROM input to ROM. GPIO10 Serial-ROM clock to ROM. GPIO22 erternal BIOS-ROM enable

GPI

O8,GPIO9,GPIO10 no use can NC GPIO22 Enable need 3K PH ,no use must NC

Title

Vancouver_Strape/DP/HDMI//CRT

Size Document Number R ev

stom

Cu

Date: Sheet

E

V

GA_SMB_CK2

8

V

GA_SMB_DA2

7

HM_ALERT#

T

6

5

HSY 11: Audio for both DisplayPort and HDMI

V H

QBL50 LA-7551P

1 2

R

391 4.7K_0402_5%VGA@R391 4.7K_0402_5%VGA@

VSG

+3

2

VGA@

_SMB_CK2

EC

61

Q8A

DMN66D0LDW-7_SOT363-6

5

VGA@

_SMB_DA2

EC

34

Q8B

DMN66D0LDW-7_SOT363-6

NC:VSYNC

SYNC

417 10K_0402_5%@R417 10K_0402_5%@

R

1 2

R

418 10K_0402_5%@R418 10K_0402_5%@

1 2

if GPIO22 High ,GPIO 11-13->CFG[0:2] Config ROM type ,GPU has internal PD

i

f GPIO22 Low ,GPIO 11-13->CFG[0:2] Config Primary memory-aperture size CFG[3:0] 128MB 000 256MB 001 * 64MB 010

ompal Electronics, Inc.

C

E

_SMB_CK2 6,36

EC

_SMB_DA2 6,36

19 53Wednesday, April 27, 2011

+3

VSG

+3

VSG

1.

of

0

A

U8C

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

AG12

AH12

C37 C35

A35

E34 G32 D33

F32

E32 D31

F30 C30

A30

F28 C28

A28

E28 D27

F26 C26

A26

F24 C24

A24

E24 C22

A22

F22 D21

A20

F20 D19

E18 C18

A18

F18 D17

A16

F16 D15

E14

F14 D13

F12

A12 D11

F10

A10 C10 G13 H13

J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18

L20

L27 N12

M12 M27

DDR3

NC_

DQA0_0/DQA_0

NC_

DQA0_1/DQA_1 DQA0_2/DQA_2

NC_

DQA0_3/DQA_3

NC_

DQA0_4/DQA_4

NC_ NC_

DQA0_5/DQA_5

NC_

DQA0_6/DQA_6

NC_

DQA0_7/DQA_7 DQA0_8/DQA_8

NC_

DQA0_9/DQA_9

NC_

C_DQA0_10/DQA_10

N

C_DQA0_11/DQA_11

N N

C_DQA0_12/DQA_12

N

C_DQA0_13/DQA_13

N

C_DQA0_14/DQA_14

N

C_DQA0_15/DQA_15

N

C_DQA0_16/DQA_16 C_DQA0_17/DQA_17

N

C_DQA0_18/DQA_18

N

C_DQA0_19/DQA_19

N N

C_DQA0_20/DQA_20

N

C_DQA0_21/DQA_21

N

C_DQA0_22/DQA_22 C_DQA0_23/DQA_23

N

C_DQA0_24/DQA_24

N

C_DQA0_25/DQA_25

N

C_DQA0_26/DQA_26

N N

C_DQA0_27/DQA_27

N

C_DQA0_28/DQA_28

N

C_DQA0_29/DQA_29 C_DQA0_30/DQA_30

N

C_DQA0_31/DQA_31

N

DQA1_0/DQA_32

NC_ NC_

DQA1_1/DQA_33

NC_

DQA1_2/DQA_34

NC_

DQA1_3/DQA_35

NC_

DQA1_4/DQA_36 DQA1_5/DQA_37

NC_

DQA1_6/DQA_38

NC_

DQA1_7/DQA_39

NC_ NC_

DQA1_8/DQA_40

NC_

DQA1_9/DQA_41

N

C_DQA1_10/DQA_42 C_DQA1_11/DQA_43

N

C_DQA1_12/DQA_44

N

C_DQA1_13/DQA_45

N

C_DQA1_14/DQA_46

N N

C_DQA1_15/DQA_47

N

C_DQA1_16/DQA_48

N

C_DQA1_17/DQA_49 C_DQA1_18/DQA_50

N

C_DQA1_19/DQA_51

N

C_DQA1_20/DQA_52

N N

C_DQA1_21/DQA_53

N

C_DQA1_22/DQA_54

N

C_DQA1_23/DQA_55

N

C_DQA1_24/DQA_56 C_DQA1_25/DQA_57

N

C_DQA1_26/DQA_58

N

C_DQA1_27/DQA_59

N N

C_DQA1_28/DQA_60

N

C_DQA1_29/DQA_61

N

C_DQA1_30/DQA_62 C_DQA1_31/DQA_63

N

MVREFDA

NC_

MVREFSA

NC_

MEM_CALRN0

M

EM_CALRN1

MEM_CALRN2

NC_

M_CALRP1

ME NC_

MEM_CALRP0

NC_

MEM_CALRP2

2160809000A

11SEYMOU_FCBGA962

VGA@

M

DA[0..63]23

M

1 1

+

1.5VSG

12

446

R

VGA@

40.2_0402_1%

12

448

VGA@

448

VGA@

R

100_0402_1%

+

1.5VSG

12

450

R

VGA@

40.2_0402_1%

2 2

100_0402_1%

3 3

12

452

VGA@

R

VG

DA[0..63]

15mil

MV

REFDA

0.1U_0402_16V4Z

C

1

355

VG

A@

2

15mil

MV

REFSA

0.1U_0402_16V4Z

C

1

357

A@

2

+

1.5VSG

VGA@

1 2

VGA@

R454 243_0402_1%

1 2

455 243_0402_1%

VGA@

R

1 2

456 243_0402_1%

R

VGA@

1 2

R

VGA@

457 243_0402_1%

1 2

R

458 243_0402_1%

VGA@

1 2

R

460 243_0402_1%

MD

A0 A1

MD MD

A2 A3

MD

A4

MD

A5

MD MD

A6

MD

A7

MD

A8

MD

A9

MD

A10 A11

MD

A12

MD

A13

MD MD

A14

MD

A15 A16

MD

A17

MD

A18

MD

A19

MD MD

A20

MD

A21

MD

A22

MD

A23 A24

MD

A25

MD MD

A26

MD

A27

MD

A28

MD

A29

MD

A30 A31

MD

A32

MD

A33

MD MD

A34

MD

A35

MD

A36

MD

A37

MD

A38 A39

MD

A40

MD MD

A41

MD

A42

MD

A43

MD

A44

MD

A45 A46

MD

A47

MD

A48

MD MD

A49

MD

A50

MD

A51

MD

A52 A53

MD

A54

MD

A55

MD MD

A56

MD

A57

MD

A58

MD

A59 A60

MD

A61

MD

A62

MD

A63

MD

MV

REFDA

MV

REFSA

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

N

C_MAA0_0/MAA_0

N

C_MAA0_1/MAA_1 C_MAA0_2/MAA_2

N

C_MAA0_3/MAA_3

N

C_MAA0_4/MAA_4

N N

C_MAA0_5/MAA_5

N

C_MAA0_6/MAA_6

N

C_MAA0_7/MAA_7 C_MAA1_0/MAA_8

N

C_MAA1_1/MAA_9

N C_MAA1_2/MAA_10

N

C_MAA1_3/MAA_11

N N

C_MAA1_4/MAA_12

N

C_MAA1_5/MAA_13_BA2

N

C_MAA1_6/MAA_14_BA0

N

C_MAA1_7/MAA_A15_BA1

C_WCKA0_0/DQMA_0

N

WCKA0B_0/DQMA_1

NC_

C_WCKA0_1/DQMA_2

N

NC_

WCKA0B_1/DQMA_3

N

C_WCKA1_0/DQMA_4

NC_

WCKA1B_0/DQMA_5

C_WCKA1_1/DQMA_6

N

WCKA1B_1/DQMA_7

NC_

GDDR5/DDR2/GDDR3

MEMORY INTERFACE A

C_EDCA0_0/QSA_0/RDQSA_0

N N

C_EDCA0_1/QSA_1/RDQSA_1

N

C_EDCA0_2/QSA_2/RDQSA_2

N

C_EDCA0_3/QSA_3/RDQSA_3 C_EDCA1_0/QSA_4/RDQSA_4

N

C_EDCA1_1/QSA_5/RDQSA_5

N

C_EDCA1_2/QSA_6/RDQSA_6

N N

C_EDCA1_3/QSA_7/RDQSA_7

N

C_DDBIA0_0/QSA_0B/WDQSA_0

N

C_DDBIA0_1/QSA_1B/WDQSA_1 C_DDBIA0_2/QSA_2B/WDQSA_2

N

C_DDBIA0_3/QSA_3B/WDQSA_3

N

C_DDBIA1_0/QSA_4B/WDQSA_4

N N

C_DDBIA1_1/QSA_5B/WDQSA_5

N

C_DDBIA1_2/QSA_6B/WDQSA_6

N

C_DDBIA1_3/QSA_7B/WDQSA_7

C_ADBIA0/ODTA0

N

C_ADBIA1/ODTA1

N

GDDR5

NC_

CLKA0

NC_

CLKA0B

CLKA1

NC_

CLKA1B

NC_

N

C_RASA0B

N

C_RASA1B

N

C_CASA0B C_CASA1B

N

C_CSA0B_0

N N

C_CSA0B_1

N

C_CSA1B_0 C_CSA1B_1

N

C_CKEA0

N

C_CKEA1

N

NC_

WEA0B

NC_

WEA1B

MAA0_8

NC_ NC_

MAA1_8

B

AA[0..12]

AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12

BA2 BA0 BA1

EA0# EA1#

MA#0 MA#1 MA#2 MA#3 MA#4 MA#5 MA#6 MA#7

TA0 TA1

M

A_

QMA#[0..7]

D

SA[0..7]

Q

SA#[0..7]

BA[0..2]

M

G24

M

J23

M

H24

M

J24

M

H26

M

J26

M

H21

M

G21

M

H19

M

H20

M

L13

M

G16

M

J16

A_

H16

A_

J17

A_

H17

DQ

A32

DQ

C32

DQ

D23

DQ

E22

DQ

C14

DQ

A14

DQ

E10

DQ

D9

Q

SA0

C34

Q

SA1

D29

Q

SA2

D25

Q

SA3

E20

Q

SA4

E16

SA5

Q

E12

SA6

Q

J10

SA7

Q

D7

Q

SA#0

A34

Q

SA#1

E30

Q

SA#2

E26

Q

SA#3

C20

SA#4

Q

C16

SA#5

Q

C12

Q

SA#6

J11

Q

SA#7

F8

OD

J21

OD

G19

LKA0

C

H27

LKA0#

C

G27

C

LKA1

J14

C

LKA1#

H14

ASA0#

R

K23

ASA1#

R

K19

C

ASA0#

K20

C

ASA1#

K17

C

SA0#_0

K24 K27

SA1#_0

C

M13 K16

C

KEA0

K21

C

KEA1

J20

W

K26

W

L15

H23 J19

TA0 23

OD OD

TA1 23

C

LKA0 23

C

LKA0# 23

LKA1 23

C

LKA1# 23

C

R

ASA0# 23

R

ASA1# 23

ASA0# 23

C C

ASA1# 23

SA0#_0 23

C

SA1#_0 23

KEA0 23

C

KEA1 23

C

W

EA0# 23

W

EA1# 23

MAA13 23

AA[0..12] 23

M

A_

BA[0..2] 23

QMA#[0..7] 23

D

Q

SA[0..7] 23

Q

SA#[0..7] 23

R

40.2_0402_1%

R

100_0402_1%

R

40.2_0402_1%

R

100_0402_1%

447

449

451

453

+

1.5VSG

12

VGA@

12

VGA@

12

VGA@

12

VGA@

C

U8D

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

M

DB[0..63]24

M

15m

REFDB

MV

1

VG

A@

2

15mil

MV

REFSB

1

VG

A@

2

DB[0..63]

il

0.1U_0402_16V4Z

C

C 356

356

C

0.1U_0402_16V4Z

0.1U_0402_16V4Z 358

358

0.1U_0402_16V4Z

@

R

464

@

51.1_0402_1%

te:

No route 50ohms single-ended and 100ohms diff and keep short REF137-03 suggest

459

R

5.11K_0402_1%

VGA@

C

2

360

1

12

EST_MCLK

T T

EST_YCLK

0.1U_0402_16V4Z

2

1

12

R

465

@

51.1_0402_1%

MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD

MV MV

T

C361

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63

REFDB REFSB

ESTEN

@

DDR3

C5

D

QB0_0/DQB_0

C3

D

QB0_1/DQB_1

E3

QB0_2/DQB_2

D

E1

QB0_3/DQB_3

D

F1

QB0_4/DQB_4

D

F3

D

QB0_5/DQB_5

F5

D

QB0_6/DQB_6

G4

D

QB0_7/DQB_7

H5

QB0_8/DQB_8

D

H6

QB0_9/DQB_9

D

J4

QB0_10/DQB_10

D

K6

QB0_11/DQB_11

D

K5

D

QB0_12/DQB_12

L4

D

QB0_13/DQB_13

M6

D

QB0_14/DQB_14

M1

D

QB0_15/DQB_15

M3

D

QB0_16/DQB_16

M5

QB0_17/DQB_17

D

N4

QB0_18/DQB_18

D

P6

QB0_19/DQB_19

D

P5

D

QB0_20/DQB_20

R4

D

QB0_21/DQB_21

T6

D

QB0_22/DQB_22

T1

QB0_23/DQB_23

D

U4

QB0_24/DQB_24

D

V6

QB0_25/DQB_25

D

V1

QB0_26/DQB_26

D

V3

D

QB0_27/DQB_27

Y6

D

QB0_28/DQB_28

Y1

D

QB0_29/DQB_29

Y3

QB0_30/DQB_30

D

Y5

QB0_31/DQB_31

D

AA4

QB1_0/DQB_32

D

AB6

D

QB1_1/DQB_33

AB1

D

QB1_2/DQB_34

AB3

D

QB1_3/DQB_35

AD6

D

QB1_4/DQB_36

AD1

QB1_5/DQB_37

D

AD3

QB1_6/DQB_38

D

AD5

QB1_7/DQB_39

D

AF1

D

QB1_8/DQB_40

AF3

D

QB1_9/DQB_41

AF6

D

QB1_10/DQB_42

AG4

QB1_11/DQB_43

D

AH5

QB1_12/DQB_44

D

AH6

QB1_13/DQB_45

D

AJ4

QB1_14/DQB_46

D

AK3

D

QB1_15/DQB_47

AF8

D

QB1_16/DQB_48

AF9

D

QB1_17/DQB_49

AG8

QB1_18/DQB_50

D

AG7

QB1_19/DQB_51

D

AK9

QB1_20/DQB_52

D

AL7

D

QB1_21/DQB_53

AM8

D

QB1_22/DQB_54

AM7

D

QB1_23/DQB_55

AK1

D

QB1_24/DQB_56

AL4

QB1_25/DQB_57

D

AM6

QB1_26/DQB_58

D

AM1

QB1_27/DQB_59

D

AN4

D

QB1_28/DQB_60

AP3

D

QB1_29/DQB_61

AP1

D

QB1_30/DQB_62

AP5

QB1_31/DQB_63

D

Y12

REFDB

MV

AA12

MV

REFSB

AD28

ESTEN

T

AK10

C

LKTESTA

AL10

C

LKTESTB

2160809000A

VGA@

Park&Seym

D

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

M

AB0_0/MAB_0

M

AB0_1/MAB_1 AB0_2/MAB_2

M

AB0_3/MAB_3

M

AB0_4/MAB_4

M M

AB0_5/MAB_5

M

AB0_6/MAB_6

M

AB0_7/MAB_7 AB1_0/MAB_8

M

AB1_1/MAB_9

M

AB1_2/MAB_10

M

AB1_3/MAB_11

M M

AB1_4/MAB_12

M

AB1_5/BA2

M

AB1_6/BA0

M

AB1_7/BA1

CKB0_0/DQMB_0

W

CKB0B_0/DQMB_1

W

CKB0_1/DQMB_2

W

CKB0B_1/DQMB_3

W

CKB1_0/DQMB_4

W

CKB1B_0/DQMB_5

CKB1_1/DQMB_6

W

CKB1B_1/DQMB_7

W

GDDR5/DDR2/GDDR3

DCB0_0/QSB_0/RDQSB_0

E

MEMORY INTERFACE B

E

DCB0_1/QSB_1/RDQSB_1

E

DCB0_2/QSB_2/RDQSB_2

E

DCB0_3/QSB_3/RDQSB_3 DCB1_0/QSB_4/RDQSB_4

E

DCB1_1/QSB_5/RDQSB_5

E

DCB1_2/QSB_6/RDQSB_6

E E

DCB1_3/QSB_7/RDQSB_7

D

DBIB0_0/QSB_0B/WDQSB_0

D

DBIB0_1/QSB_1B/WDQSB_1 DBIB0_2/QSB_2B/WDQSB_2

D

DBIB0_3/QSB_3B/WDQSB_3

D

DBIB1_0/QSB_4B/WDQSB_4

D D

DBIB1_1/QSB_5B/WDQSB_5

D

DBIB1_2/QSB_6B/WDQSB_6

D

DBIB1_3/QSB_7B/WDQSB_7

BIB0/ODTB0

AD

BIB1/ODTB1

AD

C

LKB0

C

LKB0B

LKB1

C LKB1B

C

R

ASB0B

R

ASB1B

C

ASB0B ASB1B

C

SB0B_0

C C

SB0B_1

C

SB1B_0 SB1B_1

C

KEB0

C

KEB1

C

W

EB0B

W

EB1B

AB0_8

M M

AB1_8

DRA

M_RST

GDDR5

11SEYMOU_FCBGA962

our is single channel for

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8

AH11

VGA@

AB[0..12]

M

AB0 AB1

M M

AB2 AB3

M

AB4

M

AB5

M M

AB6

M

AB7

M

AB8

M

AB9

M

AB10 AB11

M

AB12

M

BA2

B_ B_

BA0

B_

BA1

MB#0

DQ

MB#1

DQ

MB#2

DQ DQ

MB#3

DQ

MB#4

DQ

MB#5

DQ

MB#6 MB#7

DQ

Q

SB0

Q

SB1

Q

SB2

Q

SB3

Q

SB4 SB5

Q

SB6

Q

SB7

Q

SB#0

Q

SB#1

Q

SB#2

Q

SB#3 SB#4

Q

SB#5

Q Q

SB#6

Q

SB#7

OD

TB0

OD

TB1

LKB0

C

LKB0#

C

LKB1

C

LKB1#

ASB0#

R

ASB1#

R

C

ASB0#

C

ASB1#

C

SB0#_0

SB1#_0

C

KEB0

C

KEB1

W

EB0# EB1#

W

R

461 10_0402_5%

1 2

VGA@

R

463

5.11K_0402_1%

1 2

M

BA[0..2]

B_

QMB#[0..7]

D

SB[0..7]

Q

SB#[0..7]

TB0 24

OD OD

TB1 24

C

LKB0 24

C

LKB0# 24

LKB1 24

C

LKB1# 24

C

R

ASB0# 24

R

ASB1# 24

ASB0# 24

C C

ASB1# 24

SB0#_0 24

C

SB1#_0 24

KEB0 24

C

KEB1 24

C

W

EB0# 24

W

EB1# 24

MAB13 24

1 2

R

462 51.1_0402_1%VGA@

1

C

359

VGA@C359

VGA@

120P_0402_50V8

2

Pl

ace all these components very close to GPU (Within 25mm) and keep all component close to each Other (within5mm) except Rser2

E

AB[0..12] 24

M

B_

BA[0..2] 24

QMB#[0..7] 24

D

Q

SB[0..7] 24

Q

SB#[0..7] 24

V

RAM_RST# 23, 24

memory (channel B only)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/07/12 2011/12/31

Compal Secret Data

Deciphered Date

C

ompal Electronics, Inc.

Ti

tle

Vanc

Size Document Num ber Rev

stom

Cu

Date: Sh eet

D

Date: Sh eet

ompal Electronics, Inc.

ouver_Memory

QBL50 LA-7551P

0

1.

20 53Wednesday, April 27, 2011

E

20 53Wednesday, April 27, 2011

1.

of

A

.5VSG

+1

1 1

1

A@

VG

2

SM010030010 300ma 120ohm@100mhz DCR 0.3

120ohm/0.3A

VG

VG 1

2

VG

VG 1

2

C396

10U_0603_6.

C396

10U_0603_6.

1

2

3V6M

+1

.8VSG

VG

A@

C375

1U_0402_6.

C375

1U_0402_6.

1

2

3V6K

A@

VG

C385

1U_0402_6.

C385

1U_0402_6.

1

2

3V6K

A@

VG

C371

10U_0603_6.

C371

10U_0603_6.

1

2

3V6M

VG

A@

C376

1U_0402_6.

C376

1U_0402_6.

C362

1U_0402_6.

C362

1U_0402_6.

1

2

3V6K

A@

VG

C386

1U_0402_6.

C386

1U_0402_6.

C366

1U_0402_6.

C366

1U_0402_6.

1

2

3V6K

A@

VG

C373

10U_0603_6.

C373

10U_0603_6.

C372

10U_0603_6.

C372

10U_0603_6.

1

2

3V6M

L14

B

LM18AG121SN1D_0603

VGA@

Ref137-12~ remove Bead

+

2 2

SM010030010 300ma 120ohm@100mhz DCR 0.3

470o

hm/1A

010030010

SM 200ma 120ohm@100mhz DCR 0.2

+

1.8VSG

3 3

4 4

SM010030010 200ma 120ohm@100mhz DCR 0.2

1.8VSG

+

LM18AG121SN1D_0603

B

LM18AG121SN1D_0603

B

L20

12

VGA@

L17

VGA@

A@

VG

10U_0603_6.

1

2

3V6M

C458

12

A@

VG

1U_0402_6.

1

2

3V6K

A@

VG

10U_0603_6.

1

2

3V6M

C459

VG

C440

1

2

A@

VG

C460

0.

C460

0.

1

1U_0402_16V4Z

2

3VSG

VG

VG 1

2

L18

VGA@

A@

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

12

L16

C444

12

1.8VSG

+

B

LM18AG121SN1D_0603

C441

A@

VG

C442

0.

C442

0.

1

1U_0402_16V4Z

2

LM18AG121SN1D_0603

A@

VG

C443

1U_0402_6.

C443

1U_0402_6.

1

2

3V6K

LM18AG121SN1D_0603

B

470ohm/1A

120ohm/0.3A

A@

1U_0402_6.

3V6K

+1.0VSG

M010030010

S 200ma 120ohm@100mhz DCR 0.2

VG

A@

1U_0402_6.

1

2

3V6K

A@

VG

1U_0402_6.

1

2

3V6K

VG

10U_0603_6.

1

2

3V6M

12

VG

VG 1

2

VG

C377

1

2

VG

C387

1

2

A@

VG

C397

1

2

VG

A@

C437

10U_0603_6.

C437

10U_0603_6.

1

2

3V6M

VG

A@

C445

10U_0603_6.

C445

10U_0603_6.

1

2

3V6M

B

A@

C378

1U_0402_6.

C378

1U_0402_6.

3V6K

A@

C388

1U_0402_6.

C388

1U_0402_6.

3V6K

A@

C398

1U_0402_6.

C398

1U_0402_6.

3V6K

VG

A@

1U_0402_6.

1

2

3V6K

A@

C446

1U_0402_6.

C446

1U_0402_6.

3V6K

GCORE_SEN48

VG

A@

1U_0402_6.

1

2

3V6K

A@

VG

1U_0402_6.

1

2

3V6K

VG

1U_0402_6.

1

2

3V6K

1

VG

10U_0603_6.

2

3V6M

1

VG

10U_0603_6.

2

3V6M

C438

1

2

C379

C367

A@

C399

A@

C402

A@

C415

1

2

VG

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

VG

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

A@

C447

VG

VG 1

2

VG

VG 1

2

1

2

1

2

1

2

A@

C439

20mil

10mil

20mil

VG

A@

C380

1U_0402_6.

C380

1U_0402_6.

1

2

3V6K

A@

VG

C389

1U_0402_6.

C389

1U_0402_6.

1

2

3V6K

VG

A@

VG

C400

1U_0402_6.

C400

1U_0402_6.

1

2

3V6K

1

A@

VG

C403

1U_0402_6.

C403

1U_0402_6.

2

3V6K

1

VG

A@

C426

1U_0402_6.

C426

1U_0402_6.

2

3V6K

+V

NC 20101116

R466

0_0402_5%

A@

C363

1U_0402_6.

C363

1U_0402_6.

3V6K

A@

C390

1U_0402_6.

C390

1U_0402_6.

3V6K

A@

C401

1U_0402_6.

C401

1U_0402_6.

3V6K

C404

0.

C404

0. 1U_0402_16V4Z

1U_0402_16V4Z

A@

VG

C427

0.

C427

0. 1U_0402_16V4Z

1U_0402_16V4Z

VG

A@

10mil

20mil

DDR4_5

MPV_18

+

+SPV_18

+SPV10

GCORE_SEN

FB

12

@

+V

_GND

20mil

DD_CT

10mil

AD11

AG10

AF26 AF27 AG26 AG27

AF23 AF24 AG23 AG24

AF13 AF15 AG13 AG15

AD12 AF11 AF12 AG11

AM10

AN

AF28

AG28

AH29

AC7

AF7

AK8

G11 G14 G17 G20 G23 G26 G29 H10

M11 N11

R11 U11

M20 M21

U12

AN9

AJ7

AL9

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7

P7

U7 Y11

Y7

V12

H7

H8

10

U8E

MEM I/O

V

DDR1#1

V

DDR1#2

V

DDR1#3 DDR1#4

V V

DDR1#5

V

DDR1#6

V

DDR1#7

V

DDR1#8

V

DDR1#9

V

DDR1#10

V

DDR1#11

V

DDR1#12

V

DDR1#13

V

DDR1#14

V

DDR1#15

V

DDR1#16

V

DDR1#17

V

DDR1#18

V

DDR1#19

V

DDR1#20

V

DDR1#21

V

DDR1#22

V

DDR1#23

V

DDR1#24

V

DDR1#25

V

DDR1#26

V

DDR1#27

V

DDR1#28

V

DDR1#29 DDR1#30

V

DDR1#31

V

DDR1#32

V V

DDR1#33

V

DDR1#34

LEVEL

LEVEL TRANSLATION

TRANSLATION

DD_CT#1

V

DD_CT#2

V

DD_CT#3

V

DD_CT#4

V

I/O

DDR3#1

V

DDR3#2

V V

DDR3#3

VDDR3#4

DDR4#4

V V

DDR4#5

V

DDR4#7 DDR4#8

V

DDR4#1

V

DDR4#2

V

DDR4#3

V

DDR4#6

NC_

VDDRHA

NC_

VSSRHA

NC_

VDDRHB

NC_

VSSRHB

PLL

PV18#1

M M

PV18#2

SPV1

8

SPV10

SPVSS

VOLTAGE

VOLTAGE SENESE

SENESE

F

B_VDDC

F

B_VDDCI

_GND

FB

2160809000A

VGA@

440mA

P

2A3400mA

219mA

60mA

170mA

150mA

75mA

120mA

11SEYMOU_FCBGA962

C

PCIE

P

CIE_VDDR#1

P

CIE_VDDR#2

P

CIE_VDDR#3 CIE_VDDR#4

P P

CIE_VDDR#5

P

CIE_VDDR#6

P

CIE_VDDR#7

P

CIE_VDDR#8

CIE_VDDR/PCIE _PVDD

P

CIE_VDDC#1

P

CIE_VDDC#2

P

CIE_VDDC#3

P

CIE_VDDC#4

P

CIE_VDDC#5

P

CIE_VDDC#6

P

CIE_VDDC#7

P

CIE_VDDC#8

P

CIE_VDDC#9

P

CIE_VDDC#10

P

CIE_VDDC#11

P

CIE_VDDC#12

V

DDC#1

CORE

V

DDC#2

V

DDC#3

V

DDC#4

V

DDC#5 DDC#6

V

DDC#7

V

DDC#8

V V

DDC#9

V

DDC#10 DDC#11

V

DDC#12

V

DDC#13

V

DDC#14

V

DDC#15

V

POWER

DDC#16

V

DDC#17

V

DDC#18

V

DDC#19

V

DDC#20

V

DDC#21

V

DDC#22

V

DDC#23

V

DDC#24

V

DDC#25

V V

DDC#26

VDDC#27

47A

DDC#28

V

DDC#29

V

DDC#30

V V

DDC#31

V

DDC#32

DDC/BIF_VDDC#33

V

DDC#34

V

DDC#35

V

DDC#36

55mA

V

DDC#37

V

DDC#38

V

DDC#39

V

DDC#40

V

DDC#41

V

DDC/BIF_VDDC#42

V

DDC#43

V

DDC#44

V

DDC#45

V

DDC#46

V

DDC#47

V

DDC#48

V

DDC#49

V

DDC#50

V

DDC#51 DDC#52

V V

DDC#53

V

DDC#54

V

DDC#55

VDDC#56

DDC#57

V V

DDC#58

V

DDCI#1 VDDCI#2 VDDCI#3

DDCI#4

V VDDCI#5

DDCI#6

V

DDCI#7

V V

DDCI#8

5A

VDDCI#9 DDCI#10

V V

DDCI#11

V

DDCI#12

V

DDCI#13 DDCI#14

V V

DDCI#15

ISOLATED

DDCI#16

V

CORE I/O

VDDCI#17

DDCI#18

V V

DDCI#19

VDDCI#20 VDDCI#21 VDDCI#22

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

Granville VDDC:47A

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

anville VDDCI:4.6A

Gr

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

D

Seymour/Whist ler P

CIE_VDDR,PCIE_P VDD can combian to PCIE _VDDR

40mil

VG

A@

C381

0.1U_0402_16V4Z

C381

0.1U_0402_16V4Z

1

2

A@

VG

C391

1U_0402_6.3V6K

C391

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

A@

VG

2

1U_0402_6.3V6K

1

A@

VG

2

10U_0603_6.3V6M

1

VG

A@

2

IF_VDDC

+B

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison and Park , VDDCI and VDDC can shar e one common regulator

GDDR3/DDR3 1.1 2V@4A VDDCI)

( (GDDR5 1.12V @16A VDDCI)

DDCI

+V

ΚΚΚΚ

CIE_VDDR

+P

VG

1

2

VG

1

2

C405

VG

C416

VG

C428

VG

VGA@

1

2

VG

A@

C382

C392

C448

1

2

1

2

1

2

1U_0402_6.

1

2

3V6K

A@

VG

1U_0402_6.

1

2

3V6K

C406

1U_0402_6.3V6K

C406

1U_0402_6.3V6K

VG

C417

1U_0402_6.3V6K

C417

1U_0402_6.3V6K

VG

C429

10U_0603_6.3V6M

C429

10U_0603_6.3V6M

VG

+B

04/27

160mil

VGA@

1U_0402_6.

1

2

3V6K

C364

C368

A@

IF_VDDC

C449

A@

1U_0402_6.

1

2

3V6K

A@

VG

1U_0402_6.

1

2

3V6K

1U_0402_6.

1

3V6K

2

1U_0402_6.

1

2

3V6K

10U_0603_6.

1

2

3V6M

VGA@

1U_0402_6.

1

2

3V6K

C383

C393

C407

VG

C418

VG

C430

C450

A@

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

A@

1U_0402_6.

3V6K

A@

2010/ non-BACO design,N27,T27 connect BIF_VDDC to VDDC For BACO design

1U_0402_6.

3V6K

SM

VG

A@

C365

1U_0402_6.3V6K

C365

1U_0402_6.3V6K

C384

10U_0603_6.3V6M

C384

10U_0603_6.3V6M

1

2

A@

VG

1U_0402_6.3V6K

1

2

1

A@

2

1

A@

2

1

VG

A@

2

BIF_VDDC Park/Madison:Connect to VDDC Seymour/Whisler: dGPU operating:VDDC BACO mode:+1.0 V

VGA@

1U_0402_6.3V6K

1

2

C369

1U_0402_6.3V6K

10U_0603_6.3V6M

C451

A@

VG

1

2

C408

A@

VG

C419

A@

VG

C431

VG

A@

VGA@

1

2

VG

C370

1U_0402_6.3V6K

C370

1U_0402_6.3V6K

C394

1U_0402_6.3V6K

C394

1U_0402_6.3V6K

1

2

1U_0402_6.

C409

1U_0402_6.3V6K

C409

1U_0402_6.3V6K

1

A@

VG

3V6K

2

C420

1U_0402_6.3V6K

C420

1U_0402_6.3V6K

1U_0402_6.

1

A@

VG

2

3V6K

C432

10U_0603_6.3V6M

C432

10U_0603_6.3V6M

10U_0603_6.

1

VG

A@

2

3V6M

VGA@

C452

1U_0402_6.3V6K

C452

1U_0402_6.3V6K

C453

1U_0402_6.3V6K

C453

1U_0402_6.3V6K

1

2

VG

A@

C461

1U_0402_6.3V6K

C461

1U_0402_6.3V6K

1

2

010014520 3000ma 220ohm@100mhz DCR 0.04

L13

VGA@

F

BMA-L11-201209-221LMA 30T_0805

220ohm/2A

+1

1U_0402_6.

1

3V6K

2

1U_0402_6.

1

2

3V6K

10U_0603_6.

1

2

3V6M

VGA@

1U_0402_6.

1

2

3V6K

VG

A@

10U_0603_6.

1

3V6M

2

C411

C422

C434

C455

C463

.0VSG

C412

1U_0402_6.

C412

1U_0402_6.

1

A@

VG

3V6K

2

C423

1U_0402_6.

C423

1U_0402_6.

1

A@

VG

2

3V6K

VGA@

C456

1U_0402_6.3V6K

C456

1U_0402_6.3V6K

1

2

VG

A@

C464

10U_0603_6.3V6M

C464

10U_0603_6.3V6M

1

2

A@

C395

10U_0603_6.

C395

10U_0603_6.

3V6M

C410

A@

VG

C421

A@

VG

C433

VG

A@

C454

1U_0402_6.

C454

1U_0402_6.

3V6K

A@

C462

0.

C462

0. 1U_0402_16V4Z

1U_0402_16V4Z

12

A@

VG

VGA@

1

2

VG

1

2

C413

1U_0402_6.3V6K

C413

1U_0402_6.3V6K

1

A@

VG

2

C424

1U_0402_6.3V6K

C424

1U_0402_6.3V6K

1

A@

VG

2

C457

1U_0402_6.3V6K

C457

1U_0402_6.3V6K

A@

C465

10U_0603_6.3V6M

C465

10U_0603_6.3V6M

E

+

1.8VSG

C414

1U_0402_6.3V6K

C414

1U_0402_6.3V6K

+

1

2

1

2

SM

VGA_CORE

Granville PRO VDDC:47A Madison PRO VDDC+VDDCI=31 .3A Whistler PRO VDDC+VDDCI=24A SeymourXT VDDC+VDDCI=14.2A

C425

1U_0402_6.3V6K

C425

1U_0402_6.3V6K

RobsonXT VDDC+VDDCI=1 2.9A

01000BY00 5000ma 120ohm@100mhz DCR 0.02

12

VGA@

L19

FBMA-L11-201209-121LMA 50T_0805

F

BMA-L11-201209-121LMA 50T_0805

12

VGA@

L21

Seymour/Whist ler

+

VGA_CORE

ecurity Classification

S

Is

sued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/

07/12 2011/12/31

Compal Secret Data

Deciphered Date

D

C

ompal Electronics, Inc.

Title

Vanc

Size Doc ument Number Rev

Custom

Date: Sheet

ompal Electronics, Inc.

ouver_Power/GND

BL50 LA-7551P

Q

of

21 53Wednesday, April 27, 2011

E

21 53Wednesday, April 27, 2011

1.0

A

U8F

AB39

E_VSS#1

PCI

E39

E_VSS#2

PCI

F34

E_VSS#3

PCI

F39

PCI

E_VSS#4

G33

E_VSS#5

PCI

G34

PCI

E_VSS#6

H31

E_VSS#7

PCI

H34

PCI

E_VSS#8

H39

E_VSS#9

PCI

J31

E_VSS#10

1 1

2 2

3 3

4 4

REF137-13 update

PCI

J34

PCI

E_VSS#11

K31

E_VSS#12

PCI

K34

PCI

E_VSS#13

K39

E_VSS#14

PCI

L31

E_VSS#15

PCI

L34

PCI

E_VSS#16

M34

PCI

E_VSS#17

M39

PCI

E_VSS#18

N31

E_VSS#19

PCI

N34

E_VSS#20

PCI

P31

PCI

E_VSS#21

P34

PCI

E_VSS#22

P39

E_VSS#23

PCI

R34

E_VSS#24

PCI

T31

PCI

E_VSS#25

T34

E_VSS#26

PCI

T39

PCI

E_VSS#27

U31

E_VSS#28

PCI

U34

E_VSS#29

PCI

V34

PCI

E_VSS#30

V39

E_VSS#31

PCI

W31

E_VSS#32

PCI

W34

E_VSS#33

PCI

Y34

PCI

E_VSS#34

Y39

E_VSS#35

PCI

GND

ND#100

G G

ND#101 ND#102

G

ND#103

G G

ND#104 ND#105

G G

ND#106 ND#107

G G

ND#108

G

ND#109

G

ND#110 ND#111

G

ND#112

G G

ND#113 ND#114

G G

ND#115 ND#116

G G

ND#117

G

ND#118 ND#119

G

ND#120

G

ND#121

G G

ND#122 ND#123

G G

ND#124 ND#125

G G

ND#126

G

ND#127 ND#128

G G

ND#129 ND#130

G G

ND#131 ND#132

G G

ND#133

G

ND#134

G

ND#135

G

ND#136 ND#137

G G

ND#138 ND#139

G G

ND#140 GND#141 G

ND#142

ND#143

G GND#144 G

ND#145 GND#146 G

ND#147 GND#148 G

ND#149

ND#150

G GND#151

ND#153

G GND#154

ND#155

G

ND#156

G G

ND#157

ND#158

G G

ND#159

ND#160

G G

ND#161

ND#163

G GND#164

ND#165

G GND#166 G

ND#167 GND#168 G

ND#169 GND#170 G

ND#171 GND#172 GND#173

ND#174

G GND#175

ND#152

G GND#162

GND

A

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33

F7

F9 G2 G6

H9

J2

J27

J6 J8

K14

K7

L11 L17

L2

L22 L24

L6

M17 M22 M24

N16 N18

N2

N21 N23 N26

N6

R15 R17

R2

R20 R22 R24 R27

R6

T11 T13 T16 T18 T21 T23 T26 U15 U17

U2

U20 U22 U24 U27

U6

V11 V16 V18 V21 V23 V26

W2 W6

Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

2160809000A11SEYMOU_FCBGA962

VGA@

ND/PX_EN#61

G

VSS_MECH#1 VSS_ VSS_MECH#3

ND#1

G

ND#2

G

ND#3

G G

ND#4 ND#5

G G

ND#6 ND#7

G G

ND#8 ND#9

G

ND#10

G G

ND#11 ND#12

G G

ND#13 ND#14

G

ND#15

G G

ND#16

G

ND#17

G

ND#18 ND#19

G

ND#20

G G

ND#21

G

ND#22 ND#23

G

ND#24

G G

ND#25 ND#26

G G

ND#27 ND#28

G

ND#29

G G

ND#30 ND#31

G

ND#32

G

ND#33

G G

ND#34 ND#35

G

ND#36

G

ND#37

G

ND#38

G G

ND#39 ND#40

G G

ND#41 ND#42

G G

ND#43 ND#44

G

ND#45

G G

ND#46 ND#47

G G

ND#48 ND#49

G G

ND#50

G

ND#51

G

ND#52 ND#53

G

ND#54

G G

ND#55 ND#56

G G

ND#57 ND#58

G G

ND#59

G

ND#60

ND#62

G

ND#63

G G

ND#64 ND#65

G G

ND#66 ND#67

G G

ND#68

G

ND#69 ND#70

G G

ND#71 ND#72

G G

ND#73 ND#74

G G

ND#75

G

ND#76

G

ND#77

G

ND#78 ND#79

G G

ND#80 ND#81

G G

ND#82 GND#83 G

ND#84

ND#85

G GND#86 G

ND#87 GND#88 G

ND#89 GND#90 G

ND#91

ND#92

G GND#93

ND#94

G GND#95

ND#96

G

ND#97

G G

ND#98

MECH#2

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

DPA_VDD18,DPA_PVDD,DPB_V DD18,DPB_PVDD can combian to DPAB_VDD18 DPC_VDD18,DPC_PVDD,DPD_V DD18,DPD_PVDD can combian to DPCD_VDD18 (DPD_VDD18,DPD_PVDD not applicable on Robson/Park) DPE_VDD18,DPE_PVDD, DPF_VDD18,DPF_PVDD can combian to DPEF_VDD18

DPx-VSSR,DPx_PVSS can combian to DP_VSSR (Manhatann should have individual GND) where x is A,B,C,D,E,F

EN

PX_

EN: PU at P.20 SBIOS will control VGA power on/off. High :BACO mode enable LOW:BACO disable

B

Seymour/Whistler DP can combian to DPAB_VDD10 DPC_VDD10,DPD_VDD10 can combian to DPCD_VDD10 DPE_VDD10,DPD_VDD10 can combian to DPEF_VDD10

Manhatann:300mA Seymour:150mA

M

anhatann:220mA

Seymour:110mA

S

PX_

M01000BL00

1000ma 470ohm@100mhz DCR 0.2

.8VSG

+1

EN 25,36

S

M01000BL00

1000ma 470ohm@100mhz DCR 0.2

+1

.0VSG

M

FootPrint

M

FootPrint

L26

BK1608221YZF_2P

VGA@

L27

BK1608221YZF_2P

VGA@

DP mode:300mA LVDS mode:440mA

12

VG

A@

C

10U_0603_6.3V6M

1

478

2

DP mode:220mA LVDS mode:240mA

12

A@

VG

10U_0603_6.3V6M

C

1

481

2

Park/Madison :AL21left NC

Seymour/Whistler: AL21:PX_EN use to control discreate GPU regulators for power express BACO mode Support BACO: output High3.3V:turn off regulators (BACO mode on) output Low0V:turn on regulators (BACO mode off) need PD resistor No support BACO: left NC

B

C

A_VDD10,DPB_VDD10

VG

A@

C

1U_0402_6.3V6K

1

479

2

A@

VG

1U_0402_6.3V6K

C

1

482

2

ΚΚΚΚ

U8H

DP C/D POWER

20mil

DPABCD_VDD18

+

20mil

DPABCD_VDD10

+

20mil

DPABCD_VDD18

+

20mil

DPABCD_VDD10

+

467

R

R 150_0402_1%

150_0402_1%

12

VGA@

20mil

+

VG

1

2

DPEF_VDD18

A@

C

0.1U_0402_16V4Z

0.1U_0402_16V4Z 480

480

20mil

+

DPEF_VDD10

20mil

+

DPEF_VDD18

20mil

+

DPEF_VDD10

A@

VG

0.1U_0402_16V4Z

C

1

483

2

R

470

VGA@

150_0402_1%

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DP C/D POWER

AP20

DPCD/

DPC_VDD18#1

AP21

DPC_VDD18#2

DPCD/

AP13

DPC_VDD10#1

DPCD/

AT13

DPC_VDD10#2

DPCD/

AN17

DP/

DPC_VSSR#1

AP16

DPC_VSSR#2

DP/

AP17

DPC_VSSR#3

DP/

AW14

DP/

DPC_VSSR#4

AW16

DPC_VSSR#5

DP/

AP22

DPD_VDD18#1

DPCD/

AP23

DPD_VDD18#2

DPCD/

AP14

DPD_VDD10#1

DPCD/

AP15

DPCD/

DPD_VDD10#2

AN19

DPD_VSSR#1

DP/

AP18

DP/

DPD_VSSR#2

AP19

DPD_VSSR#3

DP/

AW20

DP/

DPD_VSSR#4

AW22

DPD_VSSR#5

DP/

AW18

12

CALR

DPCD_

DP E/F POWER

AH34

DPEF/

DPE_VDD18#1

AJ34

DPE_VDD18#2

DPEF/

AL33

DPE_VDD10#1

DPEF/

AM33

DPE_VDD10#2

DPEF/

AN34

DPE_VSSR#1

DP/

AP39

DP/

DPE_VSSR#2

AR39

DP/

DPE_VSSR#3

AU37

DPE_VSSR#4

DP/

AF34

DPEF/

DPF_VDD18#1

AG34

DPEF/

DPF_VDD18#2

AK33

DPEF/

DPF_VDD10#1

AK34

DPF_VDD10#2

DPEF/

AF39

DPF_VSSR#1

DP/

AH39

DP/DPF_VSSR#2

AK39

DP/

DPF_VSSR#3

AL34

DP/DPF_VSSR#4

AM34

DP/

DPF_VSSR#5

AM39

DPEF_CALR

160809000A11SEYMOU_FCBGA962

2

VGA@

2010/

07/12 2011/12/31

DPCD_

pal Secret Data

Com

DP A/B POWER

DPAB/

DPA_VDD18#1 DPA_VDD18#2

DPAB/

DPA_VDD10#1

DPAB/

DPA_VDD10#2

DPAB/

DP/

DPA_VSSR#1 DPA_VSSR#2

DP/

DPA_VSSR#3

DP/ DP/

DPA_VSSR#4 DPA_VSSR#5

DP/

DPB_VDD18#1

DPAB/

DPB_VDD18#2

DPAB/

DPB_VDD10#1

DPAB/ DPAB/

DPB_VDD10#2

DPB_VSSR#1

DP/ DP/

DPB_VSSR#2 DPB_VSSR#3

DP/ DP/

DPB_VSSR#4 DPB_VSSR#5

DP/

DPAB_

DP PLL POWER

DPAB_

VDD18/DPA_PVDD

VSSR/DPA_PVSS

DP_

VDD18/DPB_PVDD

DPAB_

VSSR/DPB_PVSS

DP_

VDD18/DPC_PVDD

DP_

VSSR/DPC_PVSS

VDD18/DPD_PVDD

DP_

VSSR/DPD_PVSS

DPEF_

VDD18/DPE_PVDD

DP_

VSSR/DPE_PVSS

DPEF_

VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

Deciphered Date

CALR

D

M01000BL00

S

20mil

AN24

DPABCD_VDD18

+

AP24

20mil

AP31

DPABCD_VDD10

+

AP32

AN27 AP27 AP28 AW24 AW26

AP25

DPABCD_VDD18

+

AP26

AN33

+

DPABCD_VDD10

AP33

AN29 AP29 AP30 AW30 AW32

AW28

20mA

AU28 AV27

20mA

AV29 AR28

20mA

AU18 AV17

20mA

AV19 AR18

20mA

AM37 AN38

20mA

AL38 AM35

D

R

R 150_0402_1%

150_0402_1%

1 2

VGA@

+

DPABCD_VDD18

+

DPABCD_VDD18

+

DPABCD_VDD18

+

DPEF_VDD18

+

DPEF_VDD18

20mil

468

300mA

1

A@

VG

10U_0603_6.3V6M

C

C 469

469

2

220mA

A@

VG

0.1U_0402_16V4Z

C

1

475

2

10mil

il

10m

10mil

Ti

tle

V

Size Document Number Rev

Custom

Date: Sheet

1000ma 470ohm@100mhz DCR 0.2

M

1

A@

VG

1U_0402_6.3V6K

0.1U_0402_16V4Z

C

C 470

470

2

S 1000ma 470ohm@100mhz DCR 0.2

M

A@

VG

10U_0603_6.3V6M

1U_0402_6.3V6K

C

1

476

2

C

ompal Electronics, Inc.

ancouver_Power/GND

QB

L50 LA-7551P

L23

BK1608221YZF_2P

VGA@

A@

C471

FootPrint

M01000BL00

L25

BK1608221YZF_2P

VGA@

A@

C477

FootPrint

E

12

E

.8VSG

+1

.0VSG

1.0

22 53Wednesday, April 27, 2011

1.0

of

A

A_ A_ A_

CKEA020

C

SA0#_020 RASA0 CASA0 W

EA0#20

471

R

243_0402_1%

VGA@

DTA0_1

O

R

484

56_0402_1%

1 2

VGA@

486

R

R 56_0402_1%

56_0402_1%

1 2

VGA@

DTA1_1

O

VREFCA_ VREFDA_

M M M M

BA020 BA120 BA220

CL

KA0

CL

KA0#

O

DTA0_1

#20 #20

SA2

Q

SA0

Q

DQ

MA#2 MA#0

DQ

SA#2

Q Q

SA#0

VRAM_RST#

12

.5VSG

+1

M M M M M M M M M M

AA10 AA11 AA12 AA13

ZZZ1

1

GVRAM-SAM

X

76L01@

ZZZ3

1 1

1

GVRAM-HYNIX

76L03@

X

M

DA[0..63]20

AA[13..0]20

M

QMA#[7..0]20

D

QS

A[7..0]20

2 2

QS

A#[7..0]20

l high for Madison and Park...

Pul

3 3

OD

TA020

OD

TA120

ZZZ2

2

GVRAM-SAM

X

76L02@

ZZZ4

2

GVRAM-HYNIX

76L04@

X

M

DA[0..63]

VRAM

TA0

OD

1 2

R

483 0_0402_5%

TA1

OD

1 2

485 0_0402_5%

R

_RST#20,24

U1

A1

M8

Q1

H1

AA0

N3

AA1

P7

AA2

P3

AA3

N2

AA4

P8

AA5

P2

AA6

R8

AA7

R2

AA8

T8

AA9

R3 L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3

B7

T2

L8

J1 L1 J9 L9

K4B1G1646E-HC12_FBGA96

4.99K_0402_1% VGA@

4.99K_0402_1%

1

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A

10/AP

1

A1 A1

2 3

A1

4

A1 A1

5/BA3

BA0 BA1 BA2

CK CK CKE/

CKE0

OD

T/ODT0

CS0

CS/ RAS CAS WE

SL

DQ

SU

DQ

DM

L U

DM

SL

DQ DQ

SU

RESET

Z

Q/ZQ0

N

C/ODT1

CS1

NC/ NC/

CE1

Q1

NCZ

BALL

96-

96SDRAM DDR3

SDRAM DDR3

+1

R

VGA@

L0

DQ DQ

L1

DQ

L2 L3

DQ

L4

DQ

L5

DQ DQ

L6 L7

DQ

U0 U1

DQ

U2

DQ DQ

U3 U4

DQ DQ

U5 U6

DQ

U7

DQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

X76@

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12

475

15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil

VREFCA_

12

487

1

484

C

A@

VG

2

MD

E3

MD

F7

MD

F2

MD

F8

MD

H3

MD

H8

MD

G2

MD

H7

MD

D7

MD

C3

MD

C8

MD

C2

MD

A7

MD

A2

MD

B8

MD

A3

+1

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

A1

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

B

A22 A19 A21 A18 A23 A16 A20 A17

A0 A5 A1 A7 A3 A4 A2 A6

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472

R

243_0402_1%

VGA@

+1

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12

R

476

4.99K_0402_1% VGA@

12

488

R

4.99K_0402_1%

VGA@

12

485

C

VG

VREFCA_ VREFDA_

A@

A2 Q2

AA0

M M

AA1 AA2

M M

AA3

M

AA4 AA5

M

AA6

M M

AA7

M

AA8 AA9

M

AA10 AA11

M M

AA12 AA13

M

BA0

A_

BA1

A_ A_

BA2

CL

KA0

CL

KA0#

CKEA0

O

DTA0_1 SA0#_0

C RASA0

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CASA0 W

EA0#

SA3

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SA1

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MA#3 MA#1

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Q Q

SA#1

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VREFDA_

0.

1

1U_0402_16V4Z

2

U1

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A

10/AP

R7

1

A1

N7

A1

2

T3

3

A1

T7

4

A1

M7

A1

5/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/

CKE0

K1

OD

T/ODT0

L2

CS0

CS/

J3

RAS

K3

CAS

L3

WE

F3

SL

DQ

C7

SU

DQ

E7

DM

L

D3

U

DM

G3

SL

DQ

B7

DQ

SU

T2

RESET

L8

Z

Q/ZQ0

J1

N

C/ODT1

L1

CS1

NC/

J9

NC/

CE1

L9

Q1

NCZ

BALL

96-

96SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

+1

.5VSG

R

477

4.99K_0402_1% VGA@

Q1

489

R

4.99K_0402_1%

VGA@

C

DQ DQ

L1

DQ

L2 L3

DQ

L4

DQ

L5

DQ DQ

L6 L7

DQ

U0 U1

DQ

U2

DQ DQ

U3 U4

DQ DQ

U5 U6

DQ

U7

DQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

12

VREFCA_

12

486

C

A@

VG

X76@

F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1

2

A30

MD MD

A24 A29

MD MD

A26 A31

MD MD

A27

MD

A28

MD

A15

MD

A11 A14

MD MD

A10 A13

MD

A12

MD

+1

.5VSG

+1

4.99K_0402_1% VGA@

A2

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

4.99K_0402_1%

A9

A8

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R

VGA@

+1

R

490

A25

MD

E3

L0

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12

478

12

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C RASA1 CASA1 W

473

R

VGA@

C

VG

VREFCA_ VREFDA_

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12

VREFDA_

487

A@

AA0

M M

AA1 AA2

M M

AA3

M

AA4 AA5

M

AA6

M M

AA7

M

AA8 AA9

M

AA10 AA11

M M

AA12 AA13

M

BA0

A_

BA1

A_ A_

BA2

CL

KA1

CL

KA1#

O

DTA1_1

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SA4

Q

SA5

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MA#4 MA#5

DQ

SA#4

Q Q

SA#5

VRAM_RST#

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0.1U_0402_16V4Z

1

2

U1

A3

M8

VREFCA

Q3

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A

10/AP

R7

A1

N7

A1

T3

A1

T7

A1

M7

A1

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/

K1

OD

L2

CS/

J3

RAS

K3

CAS

L3

WE

F3

DQ

C7

DQ

E7

DM

D3

DM

G3

DQ

B7

DQ

T2

RESET

L8

Z

Q/ZQ0

J1

N

L1

NC/

J9

NC/

L9

NCZ

K4B1G1646E-HC12_FBGA96

R

4.99K_0402_1% VGA@

491

R

4.99K_0402_1%

VGA@

3

1 2 3 4 5/BA3

CKE0

T/ODT0

CS0

SL SU

L U

SL SU

C/ODT1

CS1 CE1

Q1

BALL

96-

96SDRAM DDR3

SDRAM DDR3

+1

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12

479

12

VREFCA_

488

C

A@

VG

DQ DQ DQ DQ DQ DQ DQ DQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

X76@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L0 L1 L2 L3 L4 L5 L6 L7

U0 U1 U2 U3 U4 U5 U6 U7

0.1U_0402_16V4Z

1

2

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%VGA@

A3

4.99K_0402_1%

MD MD MD MD MD MD MD MD

+1

VGA@

A35 A32 A38 A34 A37 A36 A39 A33

A43 A44 A40 A45 A42 A46 A41 A47

.5VSG

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R

480

492

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D

R

243_0402_1%

VGA@

12

489

C

474

VREFDA_

0.1U_0402_16V4Z

1

2

VREFCA_ VREFDA_

M M M M M M M M M M

M

AA10 AA11

M M

AA12 AA13

M

BA0

A_

BA1

A_ A_

BA2

CL

KA1

CL

KA1#

CKEA1

O

DTA1_1 SA1#_0

C RASA1 CASA1 W

EA1#

SA6

Q

SA7

Q

DQ

MA#6 MA#7

DQ

SA#6

Q Q

SA#7

VRAM_RST#

12

Q3

A@

VG

AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9

4

U1

A4

M8

VREFCA

Q4

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A

10/AP

R7

1

A1

N7

A1

2

T3

3

A1

T7

4

A1

M7

A1

5/BA3

M2

BA0

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BA1

M3

BA2

J7

CK

K7

CK

K9

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CKE0

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T/ODT0

L2

CS0

CS/

#

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#

K3

CAS

L3

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F3

SL

DQ

C7

SU

DQ

E7

DM

L

D3

U

DM

G3

SL

DQ

B7

DQ

SU

T2

RESET

L8

Z

Q/ZQ0

J1

N

C/ODT1

L1

CS1

NC/

J9

NC/

CE1

L9

Q1

NCZ

96-

96SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

+1

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12

R

481

4.99K_0402_1% VGA@

12

493

R

4.99K_0402_1%

VGA@

BALL

VREFCA_

490

C

A@

VG

X76@

1

2

DQ DQ DQ DQ DQ DQ DQ DQ

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

L0

DQ

F7

DQ

L1

F2

DQ

L2

F8

L3

DQ

H3

L4

DQ

H8

L5

DQ

G2

DQ

L6

H7

L7

DQ

D7

U0

C3

U1

C8

U2

C2

U3

A7

U4

A2

U5

B8

U6

A3

U7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1% VGA@

A4

0.

0. 1U_0402_16V4Z

1U_0402_16V4Z

4.99K_0402_1%

MD MD MD MD MD MD MD

MD MD MD MD MD MD MD MD

VGA@

E

A48 A51 A55 A54 A50 A52 A49

MD

A53

A63 A58 A60 A59 A61 A56 A62 A57

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+1

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12

R

482

VREFDA_

Q4

12

0.1U_0402_16V4Z

1

491

494

C

R

A@

VG

2

+1.5VSG+1.5VSG +1.5VSG

VG

A@

VGA@

KA020

CL

KA0#20

CL

4 4

KA120

CL

KA1#20

1 2

495 56_0402_1%

R

VGA@

1 2

496 56_0402_1%

R

VGA@C512

VGA@

1 2

497 56_0402_1%

R

VGA@

1 2

498 56_0402_1%

R

VGA@

A

1

512

C

0.01U_0402_16V7K

2

1

C

521

0.01U_0402_16V7K

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1

2

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VG

VG 1

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VG

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1U_0402_6.3V6K

C

C 492

492

10U_0603_6.3V6M

C

C 513

513

1U_0402_6.3V6K

C

1

493

2

A@

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1

10U_0603_6.3V6M

C

C 514

514

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1U_0402_6.3V6K

C

C 494

494

C

C 515

515

C

1

496

495

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10U_0603_6.3V6M

C

C 516

516

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1U_0402_6.3V6K

C

1

497

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1U_0402_6.3V6K

C

1

498

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1U_0402_6.3V6K

C

C 499

499

Se

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

500

501

2

curity Classification

Issued Date

C

VG

A@

1U_0402_6.3V6K

C503

1

2

A@

VG

10U_0603_6.3V6M

C520

1

2

pal Secret Data

Com

A@

1U_0402_6.3V6K

A@

10U_0603_6.3V6M

Deciphered Date

1U_0402_6.3V6K

C502

1

2

+1

.5VSG

A@

VG

10U_0603_6.3V6M

C519

1

2

2010/

07/12 2011/12/31

VG

A@

1U_0402_6.3V6K

C506

C505

C504

1

2

A@

VG

10U_0603_6.3V6M

C518

C517

1

2

D

+1

.5VSG

A@

VG

C

C507

1U_0402_6.3V6K

1

508

2

Title

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

A@

VG

C509

1U_0402_6.3V6K

1

2

VRAM_DDR3 / Channel A

QB

A@

VG

C

1U_0402_6.3V6K

1

510

511

2

C

ompal Electronics, Inc.

L50 LA-7551P

E

1.0

23 53Wednesday, April 27, 2011

1.0

of

A

VREFCB_ VREFDB_

M M M M M M M M M

BA020

B_ B_

BA120 BA220

B_

CKEB020

C

SB0#_020 RASB0 CASB0 W

EB0#20

VRAM_RST#

12

+1

512

R

R 56_0402_1%

56_0402_1%

514

R

R 56_0402_1%

56_0402_1%

1

C

530

0.01U_0402_16V7K

2

1

559

C

0.01U_0402_16V7K

2

#20 #20

SB3

Q

SB1

Q

DQ DQ

SB#3

Q Q

SB#1

VGA@

.5VSG

CL CL

O

DTB0_1

MB#3 MB#1

M M M M M

KB0 KB0#

1 1

DB[0..63]

DB[0..63]20

M

AB[13..0]20

D

QMB#[7..0]20

B[7..0]20

QS

2 2

Pul

3 3

4 4

B#[7..0]20

QS

l high for Madison and Park...

TB020

OD

TB120

OD

KB020

CL

KB0#20

CL

KB120

CL

CLKB1#20

M

VRAM

OD

TB0

1 2

511 0_0402_5%

R

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TB1

1 2

513 0_0402_5%

R

523 56_0402_1%

1 2

VGA@

R

524 56_0402_1%

1 2

VGA@

525

R

R 56_0402_1%

56_0402_1%

1 2

VGA@

526

R

R 56_0402_1%

56_0402_1%

1 2

VGA@

A

_RST#20,23

R

243_0402_1%

DTB0_1

O

1 2

O

DTB1_1

VGA@C530

VGA@

VGA@C559

VGA@

499

VGA@

U1

A1

M8

Q1

H1

AB0

N3

AB1

P7

AB2

P3

AB3

N2

AB4

P8

AB5

P2

AB6

R8

AB7

R2

AB8

T8

AB9

R3

AB10

L7

AB11

R7

AB12

N7

AB13

T3 T7

M7

M2

N8

M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3

B7

T2

L8

J1 L1 J9 L9

K4B1G1646E-HC12_FBGA96

X76@

4.99K_0402_1% VGA@

5

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A

10/AP

1

A1 A1

2 3

A1

4

A1 A1

5/BA3

BA0 BA1 BA2

CK CK CKE/

CKE0

OD

T/ODT0

CS0

CS/ RAS CAS WE

SL

DQ

SU

DQ

DM

L U

DM

SL

DQ DQ

SU

RESET

Z

Q/ZQ0

N

C/ODT1

CS1

NC/ NC/

CE1

Q1

NCZ

BALL

96-

96SDRAM DDR3

SDRAM DDR3

.5VSG

+1

R

503

515

R

.5VSG

+1

L0

DQ DQ

L1

DQ

L2 L3

DQ

L4

DQ

L5

DQ DQ

L6 L7

DQ

U0 U1

DQ

U2

DQ DQ

U3 U4

DQ DQ

U5 U6

DQ

U7

DQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

12

VREFCB_

12

1

522

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1U_0402_6.3V6K

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1

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B

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B28

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F7

MD

B27

F2

B31

MD

F8

MD

B25

H3

B30

MD

H8

MD

B24

G2

MD

B29

H7

MD

B15

D7

MD

B10

C3

B12

MD

C8

MD

B11

C2

B13

MD

A7

MD

B9

A2

B14

MD

B8

MD

A3

.5VSG

+1

B2 D9 G7 K2 K8 N1 N9 R1 R9

.5VSG

+1

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

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+1

R

504

4.99K_0402_1% VGA@

A1

0.

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1U_0402_16V4Z

516

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4.99K_0402_1% VGA@

VG

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1U_0402_6.3V6K

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2

VREFCB_

M8

VREFCA

Q2

VREFDB_

H1

VREFDQ

AB0

M

N3

A0

M

AB1

P7

A1

AB2

M

P3

A2

M

AB3

N2

A3

M

AB4

P8

A4

AB5

M

P2

A5

AB6

M

R8

A6

M

AB7

R2

A7

M

AB8

T8

A8

AB9

M

R3

A9

M

AB10

L7

A

10/AP

AB11

M

R7

1

A1

M

AB12

N7

A1

AB13

M

BA0

B_

BA1

B_ B_

BA2

CL

KB0

CL

KB0#

CKEB0

O

DTB0_1 SB0#_0

C RASB0 CASB0 W

EB0#

SB2

Q

SB0

Q

DQ

MB#2 MB#0

DQ

SB#2

Q Q

SB#0

VRAM_RST#

12

500

VGA@

VREFDB_

Q1

0.

1

1U_0402_16V4Z

523

C

A@

VG

2

A@

1U_0402_6.3V6K

C

C 535

535

.5VSG

+1

A@

VG

C

10U_0603_6.3V6M

1

551

2

T3

3

A1

T7

4

A1

M7

A1

5/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/

CKE0

K1

OD

T/ODT0

L2

CS0

CS/

#

J3

RAS

#

K3

CAS

L3

WE

F3

SL

DQ

C7

SU

DQ

E7

DM

L

D3

U

DM

G3

SL

DQ

B7

DQ

SU

T2

RESET

L8

Z

Q/ZQ0

J1

N

C/ODT1

L1

CS1

NC/

J9

NC/

CE1

L9

Q1

NCZ

BALL

96-

96SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

X76@

.5VSG

+1

R

505

4.99K_0402_1% VGA@

517

R

4.99K_0402_1% VGA@

.5VSG

+1

A@

VG

C

10U_0603_6.3V6M

1

554

552

2

12

VG

VG 1

2

VG

E3

L0

DQ

F7

DQ

L1

F2

DQ

L2

F8

L3

DQ

H3

L4

DQ

H8

L5

DQ

G2

DQ

L6

H7

L7

DQ

D7

DQ

U0

C3

U1

DQ

C8

U2

DQ

C2

DQ

U3

A7

U4

DQ

A2

DQ

U5

B8

U6

DQ

A3

U7

DQ

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

VREFCB_

0.

1

1U_0402_16V4Z

524

C

A@

VG

2

VG

A@

1U_0402_6.3V6K

C

1

536

537

2

A@

C

10U_0603_6.3V6M

553

6

U1

A2

C

B22

MD

B20

MD MD

B21 B18

MD MD

B19 B17

MD MD

B23

MD

B16

MD

B1

MD

B6 B0

MD MD

B4 B3

MD MD

B7 B2

MD

B5

MD

.5VSG

+1

.5VSG

+1

R

243_0402_1%

.5VSG

+1

12

R

506

4.99K_0402_1% VGA@

A2

4.99K_0402_1% VGA@

VG

A@

1U_0402_6.3V6K

1

2

VREFDB_

12

525

518

C

R

VG

C

1

538

2

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A@

VG

A@

1U_0402_6.3V6K

C539

C

1

540

2

C

VREFCB_ VREFDB_

M M M M M M M M M M M M M M

BA0

B_

BA1

B_ B_

BA2

CL

KB1

CL

KB1#

CKEB120

O

DTB1_1

C

SB1#_020

RASB1

#20

CASB1

#20

W

EB1#20

SB4

Q

SB5

Q

DQ

MB#4 MB#5

DQ

SB#4

Q Q

SB#5

VRAM_RST#

12

501

VGA@

4.99K_0402_1% VGA@

Q2

0.

1

1U_0402_16V4Z

4.99K_0402_1% VGA@

2

2010/

7

U1

A3

M8

VREFCA

Q3

H1

VREFDQ

AB0

N3

A0

AB1

P7

A1

AB2

P3

A2

AB3

N2

A3

AB4

P8

A4

AB5

P2

A5

AB6

R8

A6

AB7

R2

A7

AB8

T8

A8

AB9

R3

A9

AB10

L7

A

10/AP

AB11

R7

1

A1

AB12

N7

A1

2

AB13

T3

3

A1

T7

4

A1

M7

A1

5/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/

CKE0

K1

OD

T/ODT0

L2

CS0

CS/

J3

RAS

K3

CAS

L3

WE

F3

SL

DQ

C7

SU

DQ

E7

DM

L

D3

U

DM

G3

SL

DQ

B7

DQ

SU

T2

RESET

L8

Z

Q/ZQ0

J1

N

C/ODT1

L1

CS1

NC/

J9

NC/

CE1

L9

Q1

NCZ

96-

96SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

X76@

.5VSG

+1

12

507

R

12

519

R

+1

.5VSG

A@

VG

1U_0402_6.3V6K

1

2

Com

07/12 2011/12/31

Com

DQ DQ DQ DQ DQ DQ DQ DQ

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

BALL

VREFCB_

0.

1

1U_0402_16V4Z

526

C

A@

VG

2

A@

VG

C

C541

1U_0402_6.3V6K

1

542

2

pal Secret Data

Deciphered Date

L0 L1 L2 L3 L4 L5 L6 L7

U0 U1 U2 U3 U4 U5 U6 U7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

4.99K_0402_1% VGA@

VG

VG 1

2

D

B35

MD

E3

B37

MD

F7

MD

B34

F2

B39

MD

F8

MD

B33

H3

B38

MD

H8

MD

B32

G2

MD

B36

H7

MD

B44

D7

MD

B43

C3

B47

MD

C8

MD

B41

C2

B45

MD

A7

MD

B40

A2

B46

MD

B8

B42

MD

A3

.5VSG

+1

B2 D9 G7 K2 K8 N1 N9 R1 R9

.5VSG

+1

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

.5VSG

+1

508

R

A3

520

R

A@

VG

C

C543

1U_0402_6.3V6K

1

544

2

D

243_0402_1%

12

VREFDB_

12

0.

1

1U_0402_16V4Z

527

C

A@

VG

2

A@

VG

C545

1U_0402_6.3V6K

1

2

+1

.5VSG

1

VG

10U_0603_6.3V6M

2

VRAM_RST#

12

502

R

VGA@

4.99K_0402_1% VGA@

Q3

4.99K_0402_1% VGA@

1

A@

VG

10U_0603_6.3V6M

C

555

556

2

VREFCB_ VREFDB_

M M M M M M M M M M M M M M

BA0

B_

BA1

B_ B_

BA2

CL

KB1

CL

KB1#

CKEB1

O

DTB1_1 SB1#_0

C RASB1 CASB1 W

EB1#

SB6

Q

SB7

Q

DQ

MB#6 MB#7

DQ

SB#6

Q Q

SB#7

+1

509

R

521

R

+1

A@

10U_0603_6.3V6M

C557

8

U1

A4

M8

VREFCA

Q4

H1

VREFDQ

AB0

N3

A0

AB1

P7

A1

AB2

P3

A2

AB3

N2

A3

AB4

P8

A4

AB5

P2

A5

AB6

R8

A6

AB7

R2

A7

AB8

T8

A8

AB9

R3

A9

AB10

L7

A

10/AP

AB11

R7

1

A1

AB12

N7

A1

2

AB13

T3

3

A1

T7

4

A1

M7

A1

5/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/

CKE0

K1

OD

T/ODT0

L2

CS0

CS/

#

J3

RAS

#

K3

CAS

L3

WE

F3

SL

DQ

C7

SU

DQ

E7

DM

L

D3

U

DM

G3

SL

DQ

B7

DQ

SU

T2

RESET

L8

Z

Q/ZQ0

J1

N

C/ODT1

L1

CS1

NC/

J9

NC/

CE1

L9

Q1

NCZ

BALL

96-

96SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

X76@

.5VSG

12

4.99K_0402_1% VGA@

A4

VREFCB_

12

0.

1

1U_0402_16V4Z

528

C

4.99K_0402_1% VGA@

A@

VG

2

.5VSG

A@

VG

C

1U_0402_6.3V6K

1

546

2

1

A@

VG

10U_0603_6.3V6M

C

C 558

558

2

Title

Ti

tle

VRAM_DDR3 / Channel B

Size Document Number Rev

Custom

Date: Sheet

A@

VG

C

1U_0402_6.3V6K

1

547

2

C

ompal Electronics, Inc.

QB

L50 LA-7551P

C548

DQ DQ DQ DQ DQ DQ DQ DQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E

B55

MD

E3

L0 L1 L2 L3 L4 L5 L6 L7

U0 U1 U2 U3 U4 U5 U6 U7

+1

510

R

522

R

VG

VG 1

2

A@

1U_0402_6.3V6K

F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

.5VSG

C

C 549

549

12

VG

VG 1

2

+1

A@

1U_0402_6.3V6K

E

B49

MD MD

B52 B50

MD MD

B53 B48

MD MD

B54

MD

B51

MD

B56

MD

B59 B63

MD MD

B62 B57

MD MD

B61 B58

MD

B60

MD

.5VSG

+1

VREFDB_

529

C

A@

VG

C

C 550

550

Q4

0.

1

1U_0402_16V4Z

2

1.0

24 53Wednesday, April 27, 2011

1.0

of

5

4

3

2

1

Power Sequence of Whistler and Seymour

SUSP#

VSG

+3

(

JUMP form +3VS)

VG

A_ON

D D

VGA_PWR_ON

5_VDDC_PWREN

1.

A_CORE

+VG

+1

.5VSG

+1

.0VSG

+1.8VSG

For PX sequence, >2mS delay is required between PE_GPIO1 and VGA_PWR_ON

PE_

GPIO1

C C

Del

ay SUSP# 10ms

VG

A_ON36

E_GPIO113,36

P

B B

VGA@

1 2

R

111 0_0402_5%

@

R

119

1 2

10K_0402_1%

VGA_PWR_ON >2ms

For

A_PWR_ON

VG

VGA Power on control

VG

10m

A_PWR_ON 38,42,45

s

20m

VGA Muxless with BACO Status Mapping table

Normal mode

PX_EN

1.5_VDDC_PWREN VDDC_EN

1.0_EN VGA_PWR_ON source signal

01 10 VGA Power Enable Signal Mapping table 1

01 +3.3VSG ON +1.8VSG +1.0VSG +VGA_CORE +1.5VSG +BIF_VDDC

s

ON +1.8VSG

ON

+VGA_CORE

BACO mode

0

ON ON ON OFF OFF

+1.0VSG

EN22,36

PX_

A_PWRGD13,48

VG

Fr

om +VGA_CORE regulator

+3V

VGA@

1 2

651 0_0402_5%

R

12

VGA@

R

652

5.11K_0402_1%

5_VDD_PWREN

1.

+3.3VSG

+1.0VSG +VDDCI +VGA_CORE +1.5VSG

VG

A_PWR_ON

R

650 10K_0402_5%

1 2

S

VGA@

2

R

13

D

Q2

2

VGA@

G

2N7002K_SOT23-3

S

1104

VGA@C1104

VGA@

C

0.1U_0402_16V4Z

VGA@

1 2

655 0_0402_5%

2

B

1

A

+3V

S

12

5

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5

3

@

R

649 0_0402_5%

1 2

+3V

S

1103

VGA@

1103

VGA@

C

0.1U_0402_16V4Z

1 2

VGA@

5

U1

9

P

.5_VDD_PWREN

1

4

Y

G

NC7SZ08P5X_NL_SC70-5

3

VGA@

653

R

1K_0402_5%

VGA@

0

U2

4

Y

2

Whislter VGA_ON

SUSP# VGA_PWR_ON VGA_PWR_ON

Combine with +VGA_CORE

1.5_VDDC_PWREN

5_VDD_PWREN 38,48

1.

S

+5V

1 2

DMN66D0LDW-7_SOT363-6

Q

61

23A

VGA@

R

1K_0402_5%

5

S

+5V

654

1 2

34

VDDC_EN

0_EN

1.

DMN66D0LDW-7_SOT363-6

Q

Q 23B

23B

VGA@

BIF_VDDC

+1.0VSG

AO3416_SOT23-3

0_EN

1.

EN

VDDC_

A A

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/

08/04 2011/12/31

+

VGA_CORE

ompal Secret Data

C

Deciphered Date

4

VGA@

4

VGA@

Q2

D

S

D

S

13

AO3416_SOT23-3

G

2

G

2

30mil

13

D

S

D

S

VGA@

Q26

AO3416_SOT23-3

Q25 / Q26 / Q27 change to SB00000FG10

Q24 / 20101228

2

VGA@

1 3

D

5

Q2

S

G

2

G

VGA@

S

Q27

AO3416_SOT23-3

+

30m

1

VGA@

C

2

22U_0805_6.3V6M

A Vgs(th)(Max)= 1V Rds(on)(Max)= 22m ohm @Vgs=4.5V

Ti

tle

V

GA power sequence and BACO

Size Document Number Rev

Custom

QB

L50 LA-7551P

Date: Sheet

@

il20mil

1 2

R

656 0_0805_5%

1105

ange to SE00000I10

C1105 Ch 20101228

O3416 NMOS

C

ompal Electronics, Inc.

VGA_CORE

+

1.0

25 53Wednesday, April 27, 2011

1

25 53Wednesday, April 27, 2011

1.0

of

5

4

3

2

1

+3VS +3VS_ANX

D D

+1.

2VS

+1.

2VS_ANX

C C

+1.

2VS_ANX

+3VS_ANX

FBMA-

il

40m

1 2

R570

0_0805_5%

40mil

1 2

R607

FBMA-

0_0805_5%

L31

L11-201209-221LMA30T_0805

12

C286

0.

1U_0402_16V7K

L30

L11-201209-221LMA30T_0805

L32

12

C337

0.

1U_0402_16V7K

0.

12

C338

+1.

2VS_ANX

1U_0402_16V7K

0.

2

C289

1

1U_0402_16V7K

0.

2

C564

1

20mil

1U_0402_16V7K

2

C565

1

2U_0603_6.3V6K

2.

2

1

0.

2

1

+DVDD33

1

2

0.

2

C292

C296

1

1U_0402_16V7K

0.

1

C336

C562

2

0.

01U_0402_16V7K

1U_0402_16V7K

2

C317

1

0.

01U_0402_16V7K

20mil

01U_0402_16V7K

1

C349

2

2.

2U_0603_6.3V6K

0.

1

C326

2

+AVDD12

1

2

20mil

01U_0402_16V7K

1

C327

2

2.

2U_0603_6.3V6K

+DVDD12

1

2

32

2

DVDD1

46

59

DVDD12

AVSS

2

+DVDD33

13

53

3

AVDD3

DVDD33

DVDD3

AVDD3 AVDD3 AVDD3 AVDD3

DS_CLKL_N

LV LV

DS_CLKL_P

LV

DS_L0_N DS_L0_P

LV

DS_L1_N

LV LV

DS_L1_P DS_L2_N

LV

DS_L2_P

LV LV

DS_L3_N

LV

DS_L3_P

LV

DS_CLKU_N

LV

DS_CLKU_P

DS_U0_N

LV

DS_U0_P

LV LV

DS_U1_N

LV

DS_U1_P DS_U2_N

LV

DS_U2_P

LV LV

DS_U3_N

LV

DS_U3_P

DDC_

B VARY_ VARY_BL

CPU_

OS

C_OUT

OS

AVSS

ANX3110_QFN64_9X9

5

62

CLK

DATA

L_EN

C_IN

3 3 3 3 3

BL

8 25 33 39 63

26 27 19 20 21 22 23 24 28 29

42 43 35 36 37 38 40 41 44 45

49 50

15 47 48 31 30

+AVDD33

APU_TXOUT_CLKAPU_TXOUT_CLK+ APU_TXOUT0APU_TXOUT0+ APU_TXOUT1APU_TXOUT1+ APU_TXOUT2APU_TXOUT2+

APU_LVDS_CLK APU_LVDS_DAT

TL_BKOFF#

NVT_PWM

TL_I APU_I

NVT_PWM

TRAVI

S_CLKN

TRAVI

S_CLKP

APU_TXOUT_CLKAPU_TXOUT_CLK+ APU_TXOUT0APU_TXOUT0+ APU_TXOUT1APU_TXOUT1+ APU_TXOUT2APU_TXOUT2+

APU_LVDS_CLK APU_LVDS_DAT

TL_BKOFF#

27,36

TL_I

NVT_PWM 27

NVT_PWM 10,27

APU_I

S_CLKN 13

TRAVI

S_CLKP 13

TRAVI

27 27

27

27 27

+DVDD12

9

U3

+AVDD12

DP0_AUXN_C8 DP0_AUXP_C8

LVDS_HPD10 DP0_TXN0_C8 DP0_TXP0_C8

18,29,32

PLT_RST#13,

TL_ENVDD27

R1291

+3VS_ANX

DP0_AUXN_C DP0_AUXP_C

1 2

DP0_TXN0_C DP0_TXP0_C

+3VS_ANX

R402

C226

R400

R411

C225

R410

1 2

R407

1 2

0_0402_5%

CLK_SEL

10K_0402_5%

TL_ENVDD

1M_0402_5%

12

0.1U_0402_16V7K

T36T36 T37T37

1 2

T26T26 T38T38

12

12K_0402_1%

100P_0402_50V8J

T39T39 T50T50 T51T51 T52T52

10K_0402_5%

R_BI

U3

1

2

AVDD1

60

DPRX_

AUX_N

61

AUX_P

DPRX_

58

HPD

DPPX_

4

D

PRX_LN0_N

3

D

PRX_LN0_P

7

PRX_LN1_N

D

6

PRX_LN1_P

D

10

K_SEL

CL

12

RESET_

L

14

D

IGON

34

PO

R

51

CF

G_SCL

52

CF

G_SDA

16

IO_0

GP

17

GP

IO_1

18

GP

IO_2

AS

64

R_

BIAS

55

TD

I

57

TM

S

56

TC

K

54

O

TD

11

TEST_EN

65

PAD

B B

+3VS_ANX

A A

L33

L11-201209-221LMA30T_0805

FBMA-

12

5

1U_0402_16V7K

0.

2

C563

1

0.

2

C561

C348

1

1U_0402_16V7K

2

C567

1

01U_0402_16V7K

0.

01U_0402_16V7K

0.

1

C467

2

20mil

1

2

2.

+AVDD33

1

C566

2

2U_0603_6.3V6K

4

+3VS_ANX

@

DP0_AUXP_C

DP0_AUXN_C

Place v

ia on each trace bus and let resistor very close the via

ecurity Classification

S

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AN

AN

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

12

1M_0402_5%

R531

@

12

R532

1M_0402_5%

Compal Secret Data

2010/11/11 2011/12/31

3

Compal Secret Data

Deciphered Date

+3VS_ANX

APU_LVDS_CLK

APU_LVDS_DAT

ompal Electronics, Inc.

C

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

C

LVD

S Translator-ANX3110

Q

BL50 LA-7551P

1 2

R566

1 2

R565

1

4.7K_0402_5%

of

26 53Wednesday, April 27, 2011

of

26 53Wednesday, April 27, 2011

of

26 53Wednesday, April 27, 2011

1.0

5

C R T

D D

CRT_R

1578

C

1 2

1579

C

1 2

0.1U_0402_16V7K

FCH_

CRT_G

FCH_

CRT_B

+

CRT_VCC

0.1U_0402_16V7K

5

A2Y

3

CRT_VCC

+

5

A2Y

3

CRT_R15

FCH_

CRT_G15

FCH_

CRT_B15

FCH_

CRT_HSYNC_R

FCH_

CRT_HSYNC15

C C

CRT_VSYNC15

FCH_

12

R

1641 0_0402_5%

12

1651 0_0402_5%

R

FCH_

CRT_VSYNC_R

Close to APU

Panel LCDVDD Control

+

LCDVDD

+

1

C

1588

1587

B B

0.1U_0402_16V4Z

A A

0.1U_0402_16V4Z

2

PU_ENVDD10

A

TL_ENVDD26

anel Backlight Control

P

TL_BKOFF#26,36

BKOFF#36

1652

R

100_0805_5%

R

1659

1 2

R

712 0_0402_5% R712 0_0402_5%

TL_BKOFF#

12

61

@R1659

@

1 2

F#

BKOF

0_0402_5%

2

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6 Q99A

Q99A

718 0_0402_5%@R718 0_0402_5%@

R

5VALW

+

5

12

R1660

100K_0402_5%

@

D14 R B751V_SOD323

21

1 2

@

D8 RB751V_SOD323

21

12

R

1653

47K_0402_5%

3

Q99B

Q99B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

4

R

1634 0_0402_5%

R

1635 0_0402_5%

1636 0_0402_5%

R

1640

R

1 2

1

#

P

CRT_

4

OE

G

U8

7

74AHCT1G125GW_SOT353-5

1648

R

1 2

1

#

P

CRT_VSYN

4

OE

G

8

U8

74AHCT1G125GW_SOT353-5

4.7U_0805_10V4Z

R1656

0.047U_0402_16V7K

12

220K_0402_1%

+

3VS

12

R

1670

@

10K_0402_5%

POFF#

DIS

1 2

1K_0402_5%

HSYNC_D

1K_0402_5%

+

C1585

C_D

LCDVDD

1

2

C1589

W=60mils

4

12

1637

R

1 2

R

1643 0_0603_5%

1 2

R

1650 0_0603_5%

Q93

2301BDS-T1-E3_SOT23-3

SI

1 3

D

2

S

G

Panel PWM Control

T

L_INVT_PWM26

APU_INVT_PWM10,26

EC

150_0402_1%

C1586

_INVT_PWM36

R

C

CRT_VCC

+

1638

1583

+

3VS

1

2

BLU

GR

C

RT_B_R

12

R

150_0402_1%

1

C

2

15P_0402_50V8J

7U_0805_10V4Z

4.

T

E

EEN

D

RE

RT_R_R

RT_G_R

12

1639

1584

1

2

L_INVT_PWM

D1

2

3

C199-02SPR7G_SOT23-3

AZ

D2

2

3

AZ

C199-02SPR7G_SOT23-3

150_0402_1%

HS

YNC_L

FCH_

VSYN

C_L

FCH_

15P_0402_50V8J

1 2

R722 0_0402_5%

R

1654

@R1654

@

1 2

R1655

@R1655

@

1 2

1

CRT_DDC_SDA15

CRT_DDC_SCL15

0_0402_5%

C

1572

1

1573

C

2

10P_0402_50V8J

1

2

10P_0402_50V8J

FCH_

INVTPWM

12

R1657

R1657 10K_0402_5%

10K_0402_5%

3

1

1574

C

2

CRT_DDC_SDA

CRT_DDC_SCL

FCH_

L116

1 2

C

HILISIN NBQ160808T-800Y-N 0603

L117

1 2

C

HILISIN NBQ160808T-800Y-N 0603

L118

1 2

C

HILISIN NBQ160808T-800Y-N 0603

10P_0402_50V8J

CRT_DDC_SDA

CRT_DDC_SCL

AMD DG-47520-1-10

For

HS

VSYN

VGA_DDC_

For EMI

R4

1

R3

_LVDS_CLK26

APU APU_LVDS_DAT26

YNC_L

C_L

C

12

2.2K_0402_5%

@R4

@

1 2

@R31

@

1 2

D3

2

3

AZ

D6

DATA_C

2

CLK_C

3

AZ

1

1575

C

2

10P_0402_50V8J

R1644

R

12

1645

2.2K_0402_5%

Q101B

VGA_DDC_

0_0402_5%

VGA_DDC_

0_0402_5%

EMI, close to JLVDS1.

For

MIC_CLK30

D

DATA30

DMIC_

12

R

1661

@

AZC199-02SPR7G_SOT23-3

2

1

3

C199-02SPR7G_SOT23-3

2

1

3

C199-02SPR7G_SOT23-3

1

1576

C

2

10P_0402_50V8J

VS

+3

2

Q101A

MN66D0LDW-7_SOT363-6

D

5

34

DMN66D0LDW-7_SOT363-6

DATA_C

CLK_C

1

C1

9

2

@

R2

R2 0_0402_5%

0_0402_5%

@

1 2

+3

VS

12

R

1662

@

2K_0402_5%

2.

@D30

@

ESD

1

1577

2

10P_0402_50V8J

+

4.7K_0402_5%

R1646

4.7K_0402_5%

R1646

12

61

B+

APU APU

APU APU_TXOUT1+26

22P_0402_50V8J

APU

1

APU_TXOUT2+26

APU APU

U

SB20_N214

USB20_P214

0

D3

2

D

RE

GR

EEN

BLU

E

CRT_VCC

4.7K_0402_5%

R1642

4.7K_0402_5%

R1642

12

DATA_C

VGA_DDC_

CLK_C

VGA_DDC_

L119

1 2

F

BMA-L11-201209-221LMA30T_0805

_TXOUT0-26 _TXOUT0+26

_TXOUT1-26

_TXOUT2-26

_TXOUT_CLK-26 _TXOUT_CLK+26

SB20_N2

U

SB20_P2

W=60mils

+

LCDVDD

+

3VS

@

1

C

1590

2

3

223

@D29

@

D2

1

AZC199-02SPR7G_SOT23-3

1

0.1U_0402_16V4Z

3

9

+

W

Camera

I DISPOFF#

223

1

5VS

2

3

1580

C

=60mils

B+

_L

NVTPWM

=40mils

W

D4

R

1

B491D_SOT23-3

DDC_MD2

1

2

1581

C

100P_0402_50V8J

@

C

122680P_0402_50V7K @C122680P_0402_50V7K @

1 2

Q92

1

VI

VO

N

GND

@

2

AP2230_SOT

L115

+

5VS_CRTVCC

SM

D1812P075TF .75A 13.2V

C

D

RE

GR

EEN

YNC_L

HS

E

BLU

VSYN

C_L

VGA_DDC_

1

VGA_DDC_

1

2

C

1582

100P_0402_50V8J

@

2

EMI, close to JLVDS1.

For

LVDS1

J

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

G1

37

G2

38

G3

39

G4

40

G5

HONDA_LVD-A40SFYG+

CONN@

3

UT

23-3

=40mils

W

21

1

1570

2

0.1U_0402_16V7K

+

CRT_VCC

9

T6

PAD

DATA_C

CLK_C

100P_0402_50V8J

41 42 43 44 45

1

CRT_VCC

+

1

1571

C

@

2

1U_0402_16V7K

0.

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SU

YIN_070546FR015S263ZR

CONN@

16

G

17

G

R

719 0_0402_5% R719 0_0402_5%

1 2

5

12

R1677

R1677 10K_0402_5%

10K_0402_5%

Security Classification

ssued Date

I

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M

M

AY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

AY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30

Com

pal Secret Data

Deciphered Dat e

2

2011/12/31

Title

Size Document Number Rev

C

Date: Sheet

0-LVDS/CRT CONN

P1

Q

BL50 LA-7551P

1

53Wednesday, April 27, 2011

27

of

pal Electronics, Inc.

Com

Title

1.0

5

D D

HDMI_CLK8

APU_

HDMI_DATA8

S

5VS

+3V

+1.

12

469

R469

R

100_0402_1%

2N7002K_SOT23-3

C C

Fr

om APU

B B

A A

APU_

HDMI_HPD10

Near the connector

CIE_FTX_GRX_N126

P

CIE_FTX_GRX_P126

P

CIE_FTX_GRX_N136 CIE_FTX_GRX_P136

P

CIE_FTX_GRX_N146 CIE_FTX_GRX_P146

P

CIE_FTX_GRX_N156

P

CIE_FTX_GRX_P156

P

I_R_D1+

HDM

I_R_D1-

HDM

I_R_D2+

HDM

I_R_D2-

5

L15ESDL5V0NA-4 SLP2510P8

1166 0.1U_0402_16V7K

C

1167 0.1U_0402_16V7K

C

1168 0.1U_0402_16V7K

C

1169 0.1U_0402_16V7K

1170 0.1U_0402_16V7K

C

C C

C

1171 0.1U_0402_16V7K

1172 0.1U_0402_16V7K

C

1173 0.1U_0402_16V7K

C

1

D1

1

2

4

5

3

8

@

755

R

R 0_0402_5%

0_0402_5%

1 2

13

D

Q3

4

10

9

7

6

9

8

7

6

S

12

R

R 10K_0402_5%

10K_0402_5%

HDM

775

12 12

G

2

I_R_D1+

I_R_D1-

I_R_D2+

I_R_D2-

R

4

5VS

+1.

4.7K_0402_5%

1 2

762 150K_0402_5%

12

R

746

745

HDM

I_C_TX2I_C_TX2+

HDM

I_C_TX1-

HDM HDM

I_C_TX1+

I_C_TX0-

HDM

I_C_TX0+

HDM

I_C_CLKI_C_CLK+

HDM

4

I_HPD

HDM

12

@

R

768

365K_0402_1%

UM VGA use 499 ohm

784 604_0402_1%

R

1 2

786 604_0402_1%

R

1 2

R

788 604_0402_1%

1 2

R

790 604_0402_1%

1 2

792 604_0402_1%

R

1 2

R

795 604_0402_1%

1 2

797 604_0402_1%

R

1 2

799 604_0402_1%

R

1 2

DMI_5V_OUT

+H

I_R_D0+

HDM

I_R_D0-

HDM

I_R_CK+

HDM

I_R_CK-

5VS

+1.

R

748

0_0402_5%

1 2

G

2

13

D

S

D

S

6

Q3

G

2

BSH111 1N_SOT23-3

13

D

S

D

S

3

Q3

BSH111 1N_SOT23-3

A use 604 ohm

2

G

12

R

801

100K_0402_5%

3

D1

1

2

4

5

3

8

L15ESDL5V0NA-4 SLP2510P8

10

9

7

6

3

DMI_5V_OUT

+H

2K_0402_1%

13

D

5

Q3

S

SSM3K7002FU_SC70-3

I_R_D0+

HDM

9

I_R_D0-

HDM

8

I_R_CK+

HDM

7

HDM

I_R_CK-

6

2K_0402_1%

12

R

750

749

I_SCLK

HDM

I_SDATA

HDM

45

I_C_CLK-

I_C_CLK+

I_C_TX0-

I_C_TX0+

I_C_TX1-

I_C_TX1+

I_C_TX2-

I_C_TX2+

SUSP38,

L38

L38 CM-2012HS-900T

CM-2012HS-900T

W

L39

L39 CM-2012HS-900T

CM-2012HS-900T

W

L40

W

CM-2012HS-900T

L41

W

CM-2012HS-900T

HDM

+5VS

+HDMI_5V_OUT

756 0_0402_5%

R

1 2

1

4

1 2

765 0_0402_5%

R

769 0_0402_5%

1 2

1

4

1 2

779 0_0402_5%

R

781 0_0402_5%

R

1 2

1

4

1 2

R782 0_0402_5%R782 0_0402_5%

R783 0_0402_5%R783 0_0402_5%

1 2

1

4

1 2

794 0_0402_5%

R

I_HPD

For ESD request.

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/

08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

2

@

C

1591

+VSB

12

1678

R

470K_0402_5%

13

D

6

Q9

2

SSM3K7002FU_SC70-3

G

S

2

3

2

3

2

3

2

3

2

D3

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

For ESD request.

2

1

+5V

1

2

EN_

I/O2

GN

I/O1

Q9

S

1U_0603_10V6K

HDMI

D

5

D

S

6

HDM

3

2

1

4 5

R

1679

HDM

I_R_CK-

I_R_CK+

I_R_D0-

HDM

I_R_D0+

HDM

I_R_D1-

I_R_D1+

I_R_D2-

HDM

I_R_D2+

HDM

Custom

HDMI_5V

+

2 1

=40mils

W

G

3

SI3456BDV-T1-E3 1N TSOP6

12

C

1601

1

1.5M_0402_5%

HDM

I_HPD

I_SDATA

HDM HDM

I_SCLK

I_R_CK-

HDM

I_R_CK+ I_R_D0-

HDM

I_R_D0+

HDM HDM

I_R_D1-

I_R_D1+

HDM HDM

I_R_D2-

HDM

I_R_D2+

I_SDATA

I_SCLK

Title

Ti

tle

HDMI Connector

Size Document Number Rev

Date: Sheet

2

DMI_5V_OUT

+H

Compal E

QB

L50 LA-7551P

F2

2 1

5A_15V_SMD1812P050TF

0.

0.1U_0402_16V7K

J

HDMI1

19

HP_

18

+5V

17

DDC/

16

SDA

15

SCL

14

served

Re

13

CEC

12

CK-

11

K_shield

C

10

CK+

9

-

D0

8

D

0_shield

7

+

D0

6

D1

-

5

1_shield

D

4

+

D1

3

D2

-

2

2_shield

D

1

D2

+

SUYIN_100042MR019S153ZL

CONN@

lectronics, Inc.

DET

CEC_GND

1

C

GN GN GN GN

1592

D D D D

+H

DMI_5V_OUT

1

2

_0603_10V4Z

_0603_10V4Z 1U

1U

20 21 22 23

28 53Wednesday, April 27, 2011

1.0

of

5

=60mils

W

+3

VALW

1

C

1610

1U_0402_6.3V6K

+5

D D

WOL36

EN_

P

CIE_DTX_C_FRX_P06

P

CIE_DTX_C_FRX_N06

PC

IE_FTX_C_DRX_P06

PC

IE_FTX_C_DRX_N06

C C

R

661

1 2

+3V

S

1K_0402_5%

15K_0402_5%

R

B B

A A

1 2

0_0603_5%

R

@

1 2

0_0603_5%

@

1635

C

1 2

0.01U_0402_16V7K

2

G

R

553

10K_0402_5%

1 2

C

1629 0.1U_0402_16V7K

C

1630 0.1U_0402_16V7K

AN_CLKREQ#14

L

PLT_R

K_PCIE_LAN13

CL

K_PCIE_LAN#13

R

662

1 2

+LA

N_IO

3.3V : Enable switching regulator 0V : Disable switching regulator

568

546

+V LA LA

+V LAN_MDIN2 LA

+V LA LA

5

VALW

R

533

100K_0402_5%

1 2

220K_0402_5%~N

13

D

Q3

0

SSM3K7002FU_SC70-3

S

1 2

ST#13,18,26,32

I

SOLATEB

+LA

N_IO

R

647 0_0402_5%

ND_LAN

G

_DAC N_MDIN3 N_MDIP3

_DAC

N_MDIP2

_DAC N_MDIN1 N_MDIP1

_DAC N_MDIN0 N_MDIP0

2

534

R

TS1

1

TC

2

TD1+

3

TD

4

TC

5

TD2+

6

TD

7

TCT3

8

TD

9

TD3-

10

TC

11

TD

12

TD

X

J8

2

112

MP_43X118@

JU

9

Q2

D

S

D

S

13

G

AO3419L_SOT23-3

2

WOL#

EN_

1

C

1624

0.1U_0603_25V7K

2

E_FRX_DTX_P0

PCI

E_FRX_DTX_N0

PCI

L

AN_WAKE#

R

561 10K_0402_5%

1 2

R

562 1K_0402_5% R562 1K_0402_5%

1 2

12

LAN_VDDREG

+

563 2.49K_0402_1%

1 2

24

T1

MC MX1+

MX

1-

MC

T2

MX2+

MX

2-

MCT3

3+

MX

MX3-

T4

MC MX

4+ 4-

MX

'FORM_ IH-160 LAN

R

J45_TX3-

23

J45_TX3+

R

22

1-

21

T2

RJ45_TX2-

20

J45_TX2+

R

19

2-

18

J45_RX1-

R

17

3+

R

J45_RX1+

16

15

T4

J45_TX0-

R

14

4+

J45_TX0+

R

13

4-

XTLO

XTLI

4

W=60mils

N_IO

+LA

1611

C

1.5A

1612

1

C

2

1U_0402_16V7K

0.

1613

1

1614

C

2

1U_0402_16V7K

0.

1

C

2

1U_0402_16V7K

0.

These caps close to Pin 12,27,39,42, 47,48

31 37 40

D0

551 10K_0402_5%

R

30

R

660 10K_0402_5%

32

LA

1

IP0

LA

2

LA

4

IP1

LA

5

LA

7

LA

8

LAN_MDIP3

10

LA

11

13

0

29

0

41

0

27

3

39

3

12

3

42

3

47

3

48

3

+LAN_EVDD10

21

0

3

0

6

0

9

0

45

0

+LA

36

1 3

1 2 1 2

N_MDIP0 N_MDIN0 N_MDIP1 N_MDIN1 N_MDIP2 N_MDIN2

N_MDIN3

FCH_

PCIE_WAKE#14,32,36

U4

9

22

P

HSO

23

N

HSO

17

P

HSI

18

HSI

N

16

KREQB

CL

25

PERSTB

19

R

EFCLK_P

20

EFCLK_N

R

43

CKXTAL

1

44

2

CKXTAL

28

L

ANWAKEB

26

I

SOLATEB

14

SMBCLK

NC/

15

SMBDATA

NC/

38

G

PO/SMBALERT

33

REG

ENSW

34

VDDREG

35

VDDREG

46

RSET

24

GN

D

49

PG

ND

RTL8111E-VL-CGT_QFN48_6X6

R549 75_0603_1%R549 75_0603_1%

1 2

1529 75_0603_1%

R

1 2

R1530 75_0603_1%R1530 75_0603_1%

1 2

R

552 75_0603_1%

1 2

D

D34 LSE-200NX3216TRLF_1206-2@D34 LSE-200NX3216TRLF_1206-2@

ED3/EEDO

L

ED1/EESK

L

EECS/

EEDI

NC/

DVDD1 DVDD1 DVDD1

DVDD3 DVDD3

AVDD3 AVDD3 AVDD3 AVDD3

EVDD1

AVDD1 AVDD1 AVDD1 AVDD1

R

21 LSE-200NX3216TRLF_1206-2@D21 LSE-200NX3216TRLF_1206-2@

1 2

22 LSE-200NX3216TRLF_1206-2@D22 LSE-200NX3216TRLF_1206-2@

1 2

31 LSE-200NX3216TRLF_1206-2@D31 LSE-200NX3216TRLF_1206-2@

1 2

LE

/SDA

MD MD MD MD MDIP2 MDIN2 MDIP3 MDIN3

EGOUT

SCL

IN0

IN1

ESD

4

1

1615

C

2

1U_0402_16V7K

0.

+LA

N_IO

2

G

D

S

D

S

1

Q9

Q9 2N7002_SOT23

2N7002_SOT23

N_SROUT1.05

2

C

1636

120P_1206_2KV NPO

1

G

ND_LAN

1

2

1620

R

R 10K_0402_5%

10K_0402_5%

1 2

AN_WAKE#

L

N_VDD

+LA

N_IO

+LA

N_VDD

+LA

C

1U_0402_16V7K

0.

+LA

N_SROUT1.05

3

1

1616

2

1U_0402_16V7K

0.

+LA

N_SROUT1.05

2.

2UH +-5% NLC252018T-2R2J-N

D1

LAN_MDIP1

+LA

N_IO

LA

N_MDIN1

N_MDIP3

LA

+LA

N_IO

N_MDIN3

LA

D1

6

5

4

AZC099-04S.R7G_SOT23-6

D1

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

+LA

W=60m

8

I/O4

VDD

I/O3

9

N_IO

+LA

1106

R

470_0603_5%

1 2

13

D

Q5

4

EN_

WOL#

2

G

S

SSM3K7002FU_SC70-3

N_IO

R

560

+

LAN_VDDREG

1 2

0_0603_5%

L120

ils

1 2

These components close to Pin 36

( S

I/O2

D

GN

I/O1

I/O2

GND

I/O1

1

1625

C

2

7U_0603_6.3V6K

4.

W=60m

C

1631

hould be place within 200 mils )

LAN_MDIN0

3

2

LA

N_MDIP0

1

N_MDIP2

LA

3

2

N_MDIN2

LA

1

ils W=20mils

W=40m

1

C

1626

2

1U_0402_16V7K

0.

+LA

N_VDD

ils

1

C

1632

2

0.1U_0402_16V7K

R

RJ

R

RJ

R

For ESD request.

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/

03/04 2011/12/31

ompal Secret Data

C

Deciphered Date

2

C

4.7U_0603_6.3V6K

J45_TX3-

J45_TX3+

45_RX1-

J45_TX2-

J45_TX2+

45_RX1+

J45_TX0-

J45_TX0+

2

+LA

N_VDD

1

1617

1

1618

C

2

0.1U_0402_16V7K

1

1619

1620

C

2

C

2

1U_0402_16V7K

0.1U_0402_16V7K

0.

These caps close to Pin 3,6,9,13, 29,41,45

+LA

N_VDD

R

658

1 2

0_0603_5%

15P_0402_50V8J

N1

JLA

8

PR4

-

7

PR4

+

6

PR2

-

5

-

PR3

4

+

PR3

3

+

PR2

2

-

PR1

1

PR1

+

SANTA_130452-C

R

J45_TX0+

45_RX1+

RJ

J45_TX2+

R

J45_TX3+

R

ESD

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

1

1621

C

2

1U_0402_16V7K

0.

LAN_EVDD10

+

C

1633

C

1 2

C

163412P_0402_50V8JC163412P_0402_50V8J

1 2

8

D3

1

2

PD10943-T7_SOD323-2

9

D3

1

2

@

0

PD10943-T7_SOD323-2

1

PD10943-T7_SOD323-2

2

PD10943-T7_SOD323-2

2

PD10943-T7_SOD323-2@

D4

1

@

D4

1

@

SOD323 package

Compal E

25-LAN RTL8111E

P

L50 LA-7551P

QB

1

1623

1622

C

2

1U_0402_16V7K

0.1U_0402_16V7K

0.

1

C

1627

1628

2

0.1U_0402_16V7K

550

R

0_0402_5%

Y6

HZ_12PF_X5H025000FC1H-H

25M

9

SHL

D1

10

SHL

D2

ND_LAN

G

R

J45_TX0-

2

J45_RX1-

R

2

J45_TX2-

R

2

J45_TX3-

R

2

lectronics, Inc.

1

2

1U_0402_16V7K

0.

1

_0402_6.3V6K

2

1U

XTLI

12

XTLO

3

1

A

1

@

D7

223

ZC199-02SPR7G_SOT23-3

29 53Wednesday, April 27, 2011

of

1.0

A

1 1

+3V

C1

MI

1539

R

2 2

DM

IC_DATA27

D

MIC_CLK27

EMI request 12.24

EC_

MUTE#36

3 3

+1.

MI

C2

5VS

12

4.7K_0402_5%

4.7K_0402_5% 1553

1553

R

HDA_

@

1

0.1U_0402_16V7K

C

1503

2

1 2

1540

R

1 2

IC_DATA

DM

D

MIC_CLK

MUTE#

EC_

@

RST_AUDIO#

+

3VS_DVDD

1537

R

S

1K_0402_5%

12

0_0603_5%

C

1488

IC1_R

M

1 2

M

IC2_R

1 2

1543 0_0402_5%

R

1 2

L121

1 2

MA-L10-160808-301LMT_2P

FB

R

1545 0_0402_5%

1 2

HDA_

RST_AUDIO#14

C_JD

MI

JD

HP_

+M

IC1_VREFO_L

20K_0402_1%

39.2K_0402_1%

R

1534

0_0603_5%

3VS_DVDD

+

1

C

1505

2

_0603_6.3V6M

10U

1490 4.7U_0603_6.3V6K

C

1493 4.7U_0603_6.3V6K

C

DM

D

MIC_CLK_CODEC

HDA_

1548

R

1 2

R

1549

12

C

B

3VS_DVDD_R

+

12

1

C

1481

2

1

2

1U_0402_16V7K

0.

IC1_C

M M

IC2_C

IC_DATA_CODEC

PD#

RST_AUDIO#

A

SENSE_

1 2

1497 2.2U_0603_16V6K

1

C

1482

2

1U_0402_16V7K

0.

1

DVDD

23

NE1_L

LI

24

NE1_R

LI

14

LI

NE2_L

15

NE2_R

LI

21

IC1_L

M

22

M

IC1_R

16

IC2_L

M

17

M

IC2_R

2

IO0/DMIC_DA TA

GP

3

GP

IO1/DMIC_CLK

4

PD#

11

RESET#

12

PCBEEP

13

SENSE A

18

SENSE B

36

CBP

35

CBN

31

M

IC1_VREFO_L

43

PVSS2

42

PVSS1

49

DVSS2

7

DVSS1

ALC269-GR_QFN48_7X7

C

R

1531

S

+

VDDA

AVDD125AVDD2

OUT_L+

OUT_L-

OUT_R+

OUT_R-

OUT_L

OUT_R

SY

BCL

OUT

SDATA_

EAPD

SPDI

ONO_OUT

O_CAP

LD

VREF

J

DREF

CPVEE

AVSS1 AVSS2

NC

IN

FO

38

K

1531

0_0805_5%

1485

C

U5

0

40 41

45 44

32 33

10

6

5

8

47

48

20

29

30 28

27

19

34

26 37

+5V

_0603_6.3V6M

+

5VS_PVDD

10U

9

46

IO

PVDD139PVDD2

DVDD_

SPK_

HP_

SDATA_

M

IC2_VREFO

M

IC1_VREFO_R

1556 0.1U_0402_16V7K

R

1 2

R

1557 0.1U_0402_16V7K

1 2

R

1558 0.1U_0402_16V7K

1 2

R

1559 0.1U_0402_16V7K

1 2

ange to 0.1U for EMI

Ch

1

2

SPKO SPKO

HDA_

AC9

AC_

12

1

C

1475

2

_0805_10V6K

10U

1

1486

C

2

1U_0402_16V7K

0.

UT_L1 UT_L2

UT_R1 UT_R2

OUTL

HP_ HP_

OUTR

SYNC_AUDIO

BITCLK_AUDIO_R

SDOUT_AUDIO

SDIN_AUDIO

7_VREF

JDREF

1 2

1498

C

2.2U_0603_16V6K

1

C

1476

2

1

1487

C

2

1 2

R

1546

1 2

33_0402_5%

1547

R

1 2

0_0402_5%

R

1552

20K_0402_1%

1 2

C

1U_0402_16V7K

0.

M

_0805_10V6K

10U

1590

R

+M

IC1_VREFO_R

+

1477

D

5VS_PVDD

1

2

1U_0402_16V7K

0.

L108

BK1608800YZF 0603

SYNC_AUDIO 14

HDA_

0_0402_5%

SDOUT_AUDIO 14

HDA_

SDIN0 14

HDA_

EAPD

1

C

1499

@

2

_0805_10V6K

10U

1500

12

HDA_

36

1

2

S

+5V

HDA_

SDOUT_AUDIO

HDA_

SYNC_AUDIO

BITCLK_AUDIO 14

1

1501

C

2

1U_0402_16V7K

0.

E

SPKO

UT_L1

R

1532 0_0603_5%

1 2

UT_L2

SPKO

2

1491

C

1

@

1494

C

@

+M

_0805_10V6K

10U

UT_R1

UT_R2

_0402_50V8J

10P

2

_0402_50V8J

1

10P

IC1_VREFO_R IC1_VREFO_L

OUTR

HP_

OUTL

HP_

R

1533 0_0603_5%

1 2

1535 0_0603_5%

R

1 2

1536 0_0603_5%

R

1 2

HDA_

BITCLK_AUDIO

12

1538

R

@

1

1492

C

2

@

R

1541 2.2K_0402_1%

1541 2.2K_0402_1% 1542 2.2K_0402_1%

1542 2.2K_0402_1%

R

1554

R

R 75_0603_1%

75_0603_1%

1 2

R1555

1 2

75_0603_1%

HP_

R

L

0_0402_5%

_0402_50V8J

22P

1 2

12 12

L111

L112

B

1502

C

470P_0402_50V7K

F

SPK_

L1

C

L2

SPK_

R1

SPK_

C

R2

SPK_

C2

MI

1 2

C1

MI

1 2

220P_0402_50V7K

HPRHP_

LM18PG121SN1D_0603

HPL

LM18PG121SN1D_0603

1

1504

C

C 470P_0402_50V7K

470P_0402_50V7K

2

1 2

C

24 0.22U_0603_16V7K

1

1474 1U_0603_10V6K@C1474 1U_0603_10V6K@

2

1 2

C

1478 0.22U_0603_16V7K

1 2

C

1480 0.22U_0603_16V7K

1

1483 1U_0603_10V6K@C1483 1U_0603_10V6K@

2

1 2

C

1484 0.22U_0603_16V7K

L109

C-2

MI

B

L110

LM18PG121SN1D_0603

C-1

MI

B

LM18PG121SN1D_0603

1

C

1495

2

@

ose to JSPK1

Cl

1

C

1496

220P_0402_50V7K

2

G

L1

SPK_

SPK_ SPK_ SPK_

+

USB_VCCB

U

SB20_N114

SB20_P114

U

MI

HP_ HPR HPL

R1 R2

C_JD

L2

JD

S SPK_L2 37 SPK_ SPK_

14 13 12 11 10

PK_L1 37

R1 37 R2 37

ACES_87213-1400G

14 13 12 11 10

9

8

7

6

5

4

3

2

1

U1

JA

H

4 4

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/

06/30 2011/12/31

E

ompal Secret Data

C

Deciphered Date

lectronics, Inc.

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

F

Date: Sheet

Compal E

P26-HD CODEC ALC259

L50 LA-7551P

QB

G

lectronics, Inc.

30 53Wednesday, April 27, 2011

of

H

1.0

5

4

3

2

1

Card Reader RT

S5137

(only SD/MMC/MS function)

S

+3V

D D

+RREF & +VREF need 12mils

1

C

1510

4.7U_0805_10V4Z

2

0.1U_0402_16V4Z

R

1560 0_0603_5%

1 2

@

12

C

1507 100P_0402_50V8J

R

1733

1 2

SB20_N414

U

SB20_P414

U

+

3VS_CR

1512

30mil

EG

SDW

P_MSCLK

0_0402_5%

+VR

2

1511

C

1

C

C 1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

Card Reader Connector

C C

CARDPWR

+

30m

il

@

1

R

100K_0402_5%

B B

1562

1 2

C

1514

0.1U_0402_16V4Z

2

6.2K_0603_1%

U

SB20_N4 SB20_P4

U

CARDPWR

+

R

529

1 2

MS SDD1 SDD0 MS

3VS_CR

+

30mil

12mil

+

RREF

10mil

S

DWP_MSCLK_R

_INS#

D3

C

1515

0.1U_0402_16V4Z

1

2

U51

1

REFE

2

DM

3

DP

4

3V

5

CARD_

6

V1

7

NC

8

SP1

9

SP2

10

SP3

11

SP4

12

SP5

3_IN

3V3

8

1

C

1513

0.1U_0402_16V4Z

2

ose to connector

Cl

GP

IO0

K_IN

CL

NC

SP1 SP1 SP1 SP1 SP1

SP9 SP8 SP7 SP6

EPAD

TS5137-GR_QFN24_4X4

R

25

4 3 2 1 0

17

24

23

22 21 20 19 18 16 15 14 13

SDCL

SDW

EMI

SDCL

K_MSD2

P_MSCLK

@

1 2

R

1561 10_0402_5%

LK_SD_48M

C

MS

_BS SDD2 S

DD3_MSD1

SDCM

D

D0

MS

KMSD2

1 2

R

441 0_0402_5%

SDCD#

C

1509 10P_0402_50V8J@C1509 10P_0402_50V8J@

EMI

K_MSD2

SDCL

@

787

C

1 2

0.1U_0402_16V4Z

@

788

C

1 2

0.1U_0402_16V4Z

Close to U51

1 2

LK_SD_48M 13

C

SDCD# SDW SDD1 SDD0

MS SDCL

MS

MS MSD3 SDCM

SDD3

SDD2

P_MSCLK

_BS

K_MSD2

D0

_INS#

D

_MSD1

+

CARDPWR

CR1

J

1

CD

SD-

2

SD-

WP

3

D1

SD-

4

SD-

D0

5

-GND

MS

6

SD-

GND

7

MS

-BS

8

CLK

SD-

9

-D1

MS

10

-D0

MS

11

SD-

VCC

12

-D2

MS

13

SD-

GND

14

-INS

MS

15

MS

-D3

16

SD-

CMD

17

-SCLK

MS

18

MS

-VCC

19

D3

SD-

20

MS

-GND

21

D2

SD-

22

GN

D

23

GN

D

TAITW_R009-142-HM

CONN@

A A

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/

06/30 2011/12/31

ompal Secret Data

C

Deciphered Date

Compal E

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal E

27-RTS5137 Media Card Controller

P

L50 LA-7551P

QB

lectronics, Inc.

31 53Wednesday, April 27, 2011

1

31 53Wednesday, April 27, 2011

1.0

of

A

Mini-Express Card for W

M

1 1

124

C

1 2

10P_0402_50V8J

@

EMI

2 2

3 3

CHA

RF_

SAT

530

R

0_0402_5%

@

PW

RGE_LED1#36

RGE_LED0#36

LED#36

A_LED#15

F

CH_PCIE_WAKE#14,29,36

INI1_CLKREQ#14

M

_TX_P80_DATA36

EC

_RX_P80_CLK36

EC

C

12

LK_PCI_DB

_ON15

BT

LK_PCIE_MINI1#13

C

IE_DTX_C_FRX_N16

PC PC

IE_DTX_C_FRX_P16

PC

IE_FTX_C_DRX_N16 IE_FTX_C_DRX_P16

PC

10K_0402_5%

LED

R_LED#35,36

Orange

White

W

LAN_R_LED#

RB751V_SOD323

BT

_R_LED#

RB751V_SOD323

R

1589 0_0402_5%

LAN/WiMAX(Half)

ini-Express Card(WLAN/WiMAX)

@

1565 0_0402_5%

R

1 2

_ON

1594 0_0402_5%@

BT

R

1 2

M

INI1_CLKREQ#

LK_PCIE_MINI113

100_0402_1%

1581

R

1566 0_0402_5% R1566 0_0402_5%

R

+

5VALW

R

669

1 2 1 2

@R1582

@

100_0402_1%

1 2

R

1582

R

EC

_TX_P80_DATA

EC

_RX_P80_CLK

BT

_ON

For EC to detect debug card insert.

BATT_LOW_LED#

BATT_CHG_LED#

@

4

D2

W

LAN_D_LED#

21

@

D2

5

21

1 2

C

560 1U_0402_6.3V6K C560 1U_0402_6.3V6K

1 2

568 1U_0402_6.3V6K C568 1U_0402_6.3V6K

1 2

569 1U_0402_6.3V6K C569 1U_0402_6.3V6K

570 1U_0402_6.3V6K C570 1U_0402_6.3V6K

1 2

571 1U_0402_6.3V6K C571 1U_0402_6.3V6K

1 2

PC

LK_PCI_DB

C

EC EC

W

I_RST#_R

+

3VS_WLAN

_TX_P80_DATA_R _RX_P80_CLK_R

R

1583

100K_0402_5%

1 2

LAN_WAKE#

Wh

1 2

R

628 33_0402_5%

1 2

629 33_0402_5%

R

1 2

R

678 33_0402_5%

Green

1 2

R679 33_0402_5%R679 33_0402_5%

G

1 2

R

680 33_0402_5%

B

+

3VS

1563 0_1206_5%@

R

JMINI1

1 3 5 7 9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

BELLW

Add to prevent leakage issue.

ite

19-21SYGC/S530-E3/TR8 0603 Y/G

reen

19-21SYGC/S530-E3/TR8 0603 Y/G

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

42

41

42

44

43

44

46

45

46

48

47

48

50

49

50

52

51

52

54

ND1

ND2

G

_80003-1021

1

LED

O

W

HT-297DQ/GQ 0603 AMB/YG

LED

3

4

LED

+

3VS_WLAN

12

SMCLK0_R

FCH_ FCH_

SMDAT0_R

LAN_R_LED#

W

_R_LED#

BT

21

2

21

43

21

+1

.5VS

12

R

1564

0_1206_5%

LPC

_FRAME#_R

LPC

_AD3_R _AD2_R

LPC LPC

_AD1_R

LPC

R

1567 0_0402_5%@

1 2

1568 0_0402_5%

R

1 2

1569 0_0402_5%@

R

1 2

R

1570 0_0402_5%@

1 2

1571 0_0402_5%@

R

1 2

1572 0_0402_5%@

R

1 2

0_0402_5%

12

R

12

1585300_0402_5%R1585300_0402_5%

R

12

R

1586100_0402_5%R1586100_0402_5%

12

R1588100_0402_5% R 1588100_0402_5%

12

R

_AD0_R

SB20_N3 14

U U

SB20_P3 14

LAN_LED#

W

R

1577

12

_LED#

1575

BT

R

12

+

3VALW

1584100_0402_5%R1584100_0402_5%

+

3VALW

+

+3VS

+

1591100_0402_5%R1591100_0402_5%

C

+

3VALW

1

@

C

1516

0.1U_0402_16V4Z

2

W W PLT

+

3VALW 3VS

+

CH_SCLK0 11,12,14

F

CH_SDATA0 11,12,14

F

LAN_LED# 36

W

_LED# 36

BT

UM_LED#36

N

3VS

L_OFF# 15 L_OFF#_EC 36

_RST# 13,18,26,29

+

1.5VS

1

C

1517

0.1U_0402_16V4Z

2

PW

R_LED#

CHA

RGE_LED1#

CHARGE_LED0#

LAN_D_LED#

W

SAT

A_LED#

NUM_LED#

C

APS_LED#

1

C

1518

0.1U_0402_16V4Z

2

SP#36,38

SU

R

eserve for SW mini-pcie debug card.

Series resistors closed to KBC side.

_FRAME#_R

LPC LPC LPC LPC LPC PC C

LK_PCI_DB

_AD3_R _AD2_R _AD1_R _AD0_R

I_RST#_R

2

3

2

3

2

3

2

3

R

1573 0_0402_5%

1 2

1574 0_0402_5%

R

1 2

1576 0_0402_5%

R

1 2

R

1578 0_0402_5%

1 2

1579 0_0402_5%

R

1 2

1580 0_0402_5%

R

1 2

D2

6

@

1

YSDA0502C 3P C/A SOT-23

D3

6

@

1

YSDA0502C 3P C/A SOT-23

7

D3

@

1

YSDA0502C 3P C/A SOT-23

D3

5

@

1

YSDA0502C 3P C/A SOT-23

D

LPC LPC LPC LPC LPC P

LT_RST#

2

G

_FRAME# _AD3 _AD2 _AD1 _AD0

1U_0402_6.3V6K

+

5VALW

=60mils

W

+

3VALW

1

C

1664

2

R

663

100K_0402_5%

1 2

115 20K_0402_5%

R

13

D

Q32

Q32 SSM

SSM

3K7002FU_SC70-3

S

LPC

_FRAME# 13,36

_AD3 13,36

LPC LPC

_AD2 13,36 _AD1 13,36

LPC

_AD0 13,36

LPC

C

LK_PCI_DB 13

Q31

S

D

13

G

AO3419L_SOT

2

1

C

1663

4.7nF_0603_50V7K

2

R

1596 0_1206_5%

23-3

12

E

3VS_WLAN

+

ESD

6

LED

Green

C573 1U_0402_6.3V6K@ C573 1U_0402_6.3V6K@

1 2

681 0_0402_5%

R

19-21SYGC/S530-E3/TR8 0603 Y/G

APS_LED#36

4 4

C

A

LED

21

B

12

1593100_0402_5%R1593100_0402_5%

R

3VS

+

Security Classification

ssued Date

I

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M

M

AY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30

Com

pal Secret Data

Deciphered Dat e

D

2011/12/31

Title

Size Document Number Rev

Date: Sheet

Mini PCIE/LED

P28-

Q

BL50 LA-7551P

E

of

32

of

32

of

32

53Wednesday, April 27, 2011

pal Electronics, Inc.

Com

Title

1.0

A

B

C

D

E

F

G

H

SATA HDD Conn.

J

HDD1

1

D

STX_DRX_P0

STX_DRX_P015

SATA_ SATA_

STX_DRX_N015

DTX_C_SRX_N015

SATA_ SATA_

1 1

2 2

3 3

DTX_C_SRX_P015

SATA_ SATA_

SATA_

DTX_C_SRX_N115

DTX_C_SRX_P115

SATA_

STX_DRX_N0

SATA_

DTX_C_SRX_N0 DTX_C_SRX_P0

SATA_

1595 0_0805_5%

R

+5V

STX_DRX_P115 STX_DRX_N115

+5V

1 2

S

80m

S

656 0.01U_0402_16V7K

C

1 2

C

658 0.01U_0402_16V7K

1 2

1519 0.01U_0402_16V7K

C

1 2

1520 0.01U_0402_16V7K

C

1 2

10U_0603_6.3V6M

1

660

C

648 0.01U_0402_16V7K

648 0.01U_0402_16V7K 649 0.01U_0402_16V7K

649 0.01U_0402_16V7K

C

C C

C

R

1598 0_0805_5%

1 2

ils

+3V

S

1

661

C

2

1U_0402_6.3V6K

1 2 1 2

1521 0.01U_0402_16V7K

1 2

1522 0.01U_0402_16V7K

1 2

670 10K_0402_5%

R

+3V

5VS_HDD

+

0.1U_0402_16V4Z

662

C

@

SATA_ SATA_

S

1

C2

0.1U_0402_16V4Z

2

1

2

1000P_0402_50V7K

SATA_ SATA_

+5

VS_ODD

STX_C_DRX_P0 STX_C_DRX_N0

DTX_SRX_N0 DTX_SRX_P0

2

1

663

C

2

STX_C_DRX_P1 STX_C_DRX_N1

DTX_SRX_N1 DTX_SRX_P1

GN

2

A+

3

A-

4

GN

D

5

B-

6

B+

7

GN

D

8

3

V3

9

3

V3

10

V3

3

11

GN

D

12

GN

D

13

D

GN

14

V5

15

V5

16

V5

17

D

GN

18

served

Re

19

GN

D

20 21 22

SUYIN_127043FR022S21MZR

ATA ODD FFC Conn.

S

ODD1

J

1

GN

2

A+

3

A-

4

GN

5

B-

6

B+

7

GN

8

DP

9

+5V

10

+5V

11

MD

12

GN

13

GN

OCTEK_SLS-13DC1G_RV

23

2

ND1

V1

G

24

V1

G

2

ND2

2

V1

D

D D

15

D

GN

14

GN

D

4 4

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/

06/30 2011/12/31

E

pal Secret Data

Com

Deciphered Date

Co

mpal Electronics, Inc.

Title

Ti

tle

Size Document Number Rev

B

Date: Sheet

F

Date: Sheet

G

mpal Electronics, Inc.

P29-

HDD & ODD CONN

QB

L50 LA-7551P

1.0

33 53Wednesday, April 27, 2011

H

1.0

of

A

+5V

ALW

ctive

+

OU

T T

OU

T

OU

OC

#

OU OU OU OC

L60

1

4

W

CM-2012HS-900T

L62

1

4

W

U5

4

1

GN

D

2

C

707 0.1U_0402_16V4Z

1 1

Left

12

USB Conn.

U

SB_ON#

IN

3

IN

4

EN

#

AP2301MPG-13 MSOP 8P

Low A

+5V

ALW

U5

5

1

D

GN

2

C

714 0.1U_0402_16V4Z

12

U

SB_ON#36

U

SB_ON#

Right USB Conn.

+5V

2 2

C

715 0.1U_0402_16V4Z

12

U

SBAI_PEN#36

ALW

U

SBAI_PEN#

Left USB Conn.

3 3

U

SB30_MTX_C_DRX_P014

U

SB30_MTX_C_DRX_N014

U

SB30_MRX_DTX_P014

U

SB30_MRX_DTX_N014

4 4

SB30_MTX_C_DRX_P0

U

SB30_MTX_C_DRX_N0

USB30_MRX_DTX_P0

IN

3

IN

4

#

EN

AP2301MPG-13 MSOP 8P

Low Active

U5

6

1

D

GN

2

IN

3

IN

4

EN

#

AP2301MPG-13 MSOP 8P

Low A

B

USB_VCCA

8 7 6 5

1

C

2

+

USB_VCCB

8

T

7

T

6

T

5

#

1

2

+

USB_VCCC

8

T

7

T

6

T

5

#

1

2

M3@

2

3

M3@

CM-2012HS-900T

710

1000P_0402_50V7K@

C

713

1000P_0402_50V7K@

C

716

1000P_0402_50V7K@

U

SB30_MTX_C_DRX_P0_CUSB30_MTX_C_DRX_P0_C

2

U

SB30_MTX_C_DRX_N0_CUSB30_MTX_C_DRX_N0_C

3

USB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_CUSB30_MRX_DTX_P0_C

2

USB30_MRX_DTX_N0_CUS B30_MRX_DTX_N0_CUSB30_MRX_DTX_N0

3

U

SB_OC0# 14

U

SB_OC1# 14

U

SB_OC2# 14

U

SB20_N1014

U

SB20_P1014

U

SB30_MTX_C_DRX_P0_C

U

SB30_MTX_C_DRX_N0_C

U

SB30_MRX_DTX_P0_C

U

SB30_MRX_DTX_N0_C

C

EMI request

L55

U

SB20_N10

U

SB20_P10

U

SB20_N0_U

U

SB20_P0_U

Y

I CHARGER

A

U

SBAI_EN36

L55

1

4

W

CM-2012HS-900T

L58

1

4

W

CM-2012HS-900T

D5

1

2

4

5

3

8

SCLAMP0524P_SLP2510P8-10-9

M3@

12

100K_0402_5%

+

USB_VCCA

C

708

470P_0402_50V7K

10

9

7

6

708

U

SB20_N10_C

2

U

SB20_P10_C

3

U

SB20_N0_C

2

U

SB20_P0_C

3

U

SB30_MTX_C_DRX_P0_C

9

U

SB30_MTX_C_DRX_N0_C

8

U

SB30_MRX_DTX_P0_C

7

U

SB30_MRX_DTX_N0_C

6

For ESD request.

R

949 0_0402_5%

U

SB20_N014

U

SB20_P014

R

1016

Left

USB Conn.

1

2

1 2

+

5VALW

D

W

=80mils

1

C

709

47U_0805_6.3V

2

Left

+

USB_VCCC

1

C

711

470P_0402_50V7K

U

SB20_N0

U

SB20_P0

C

U1546 0.1U_0402_16V4Z

2

+

1

M

AX14566EETA+_TDFN-EP8_2X2~D

2

U U

U

SB30_MRX_DTX_N0_C

U

SB30_MRX_DTX_P0_C

U

SB30_MTX_C_DRX_N0_C

U

SB30_MTX_C_DRX_P0_C

USB Conn.

=80mils

W

1

C

712

47U_0805_6.3V

2

D2

U

SB20_N10_C

5VALW

U

SB20_P10_C

8 7 6 5

CE

CB TD TD VC

CB=

DM

M P

DP

GN

C

GN

0

Auto detection charger identification active

CB=1 Connect DP/DM to TDP/TDM

6

5

4

U2

1

N

U

2

U

3 4

D

9

D

D2

I/

VD

I/

AZC099-04S.R7G_SOT23-6

SB20_N0_U SB20_P0_U

1

SB20_N10_C SB20_P10_C

0

O4

D

O3

2 3 4 5 6 7 8 9

10 11 12 13

U

SB20_N0_C

U

SB20_P0_C

O2

I/

GN

D

I/

O1

VBU DD+ GN Std Std 7 Std Std

GN GN GN GN

S

For ESD request.

E

JUSB2

S

D A_SSRXA_SSRX+

A_SSTXA_SSTX+

D D D D

INGA_2UB4016-000101

JUSB1

1

VC

C

2

D-

3

D+

4

GN

D

5

G

ND1

6

ND2

G

7

G

ND3

8

ND4

G

S

UYIN_020173MR004S50DZL

CONN@

U

SB20_N0_C

3

2

U

SB20_P0_C

1

CE

N# 36

ecurity Classification

S

2010/

06/30 2011/12/31

ssued Date

I

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

ND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

A DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M

M

AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

AY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

06/30 2011/12/31

C

pal Secret Data

Com

D

eciphered Date

C

ompal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

P32-U

SB/BT/USBsub

QBL50 LA-7551P

1.0

of

34 53Friday, April 29, 2011

E

5

N/OFF switch

O

D D

SW

3

@SW3

7236LGH

%RWWRP6LGH

C C

B B

@

SMT1-05-A_4P

1

2

6

SW

@SW4

@

SMT1-05-A_4P

1

2

5

6

ACES_85201-

ON/

OFFBTN#ON/OFFBTN#

3

4

5

4

3

4

GN GN

06051

JBTN1

1 2 3 4 5

6 D D

EC_ON36

OFFBTN#

ON/

1 2 3

LI

D_SW#

4 5 6 7 8

Power Button

D12

1

DAN202UT106_SC70-

EC_ON

2

G

R528

10K_0402_5%

2

@

3

1

1 2

PJSOT24CH_SOT23-

PJSOT24CH_SOT23D27

D27

+3VALW

R527

100K_0402_5%

1 2

2

3

Change to SC600000B00

C773

1000P_0402_50V7K

13

D

Q28

S

SSM3K7002FU_SC70-

R_LED# 32,36

PW

+5VALW

D_SW# 36

LI

+3VALW

3

4

OFF# 36

ON/

51_ON#

40

2

1

3

EC BI

EC_SPI

+3VALW

3

1000P_0402_50V7K

OS ROM

CS#/FSEL#36

R668

10K_0402_5%

FAN_SPEED

C702

EC_SPI

R1050

1 2

R1052

1 2

1

2

+3VALW

CS#/FSEL#

R1049

1 2

0_0603_5%

4.7K_0402_5%

Fan Control

8

GN

D

7

GN

D

6

D

GN

5

D

GN

APL5607KI

-TRG_SO8

FAN_SET36

EC_SPI

_WP# _HOLD#

EC_SPI

VO

VSET

VI

EN

UT

U53

N

C1370

1 3 7 4

2

+5VS+3VS

1 2 3 4

1 2

_VCC

+SPI

U42

CS# WP

# LD#

HO

D

GN

MX25L1606EM2I

SA000041N00

Circuit

2

C701

2.

2U_0603_106K

1

C703

C703 10U_0603_6.

10U_0603_6.

2

0.1U_0402_16V4Z

8

VCC

6

SCL

K

5

SI

2

SO

-12G SOP 8P

+5VS_FAN

3V6M

EC_SPI

CLK_R

EC_SO_SPI

_SPI_SO_R

EC_SI

_SI_R

1000P_0402_50V7K

FAN_SPEED36

R1055

1 2

R1051

1 2

R1053

1 2

R1054

1 2

33_0402_5%

C700

FAN_SPEED

C1374

C1374 22P_0402_50V8J

22P_0402_50V8J

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

1

2

1 2

1

ACES_85205-

5

GN

4

GN

3

2

1

JFAN1

CONN@

CLK 36

EC_SPI EC_SO_SPI EC_SI

_SPI_SO 36

D D

_SI 36

0300N

A A

ecurity Classification

S

2010/06/30 2011/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AN

AN

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/30 2011/12/31

3

Compal Secret Data

Deciphered Date

Inc.

Compal Electronics,

Ti

Title

tle

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics,

P31-KB /SW/TP/Lid

BL50 LA-7551P

Q

Inc.

1.0

53Wednesday, April 27, 2011

of

35

of

35

of

35

1

5

0.

1U_0402_16V4Z

C1346

1

C1345

2

0.

1U_0402_16V4Z

D D

R1037

32

USBAI

EC_SMB_CK140 EC_SMB_DA140 EC_SMB_CK26,

19

EC_SMB_DA26,

19

NVT_PWM27

EC_I

FAN_SPEED35

EC_TX_P80_DATA32

EC_RX_P80_CLK32

NUM_LED#32

12

C1352

@C1352

@

22P_0402_50V8J

LPC_CLK0_EC13,

16

+3VALW

R1011

C1353

C C

2.4V

HI: LOW: 0.8V

+3VALW

+3VS

+3VALW

1 2

R1027

1 2

R1028

B B

A A

1 2

R1029

1 2

R1030 47K_0402_5%R1030 47K_0402_5%

1 2

R37

1 2

R1619

1 2

R1617

1 2

R1616 10K_0402_5%R1616 10K_0402_5%

+3VS

1 2

R1623

C1361

15P_0402_50V8J

@

1 2

R1020

1 2

R1021

1 2

R1022

1 2

R1023

2.2K_0402_5%

47K_0402_5%

10K_0402_5%

@

10K_0402_5%

EC_CRY1 EC_CRY2

2

@

1

2.2K_0402_5%

EC_SMB_CK2

2.2K_0402_5%

EC_SMB_DA2

2.2K_0402_5%

2.2K_0402_5%@

HI:2.4V LOW: 0.8V

EC_SMB_CK1

EC_SMB_DA1

KSO1

KSO2

D_SW#

LI

USB_ON#

EC_SMI

EC_MUTE#

EC_SCI

4

1

@

X2

C

OS

NC3NC

2

5

@

12

R1014

33_0402_5%

12

47K_0402_5%

12

0.1U_0402_16V4Z

KSO[

SI[0..7]

K

12

0..15]

BATT

APU/VGA

#

16

RTC_CLK13,

100K_0402_5%

2

@

C1362

C1362 15P_0402_50V8J

15P_0402_50V8J

1

32.768KHZ_12.5PF_Q13MC14610002

0.

EC_GA2014

EC_KBRST#14

SERI

RQ13

LPC_FRAME#13,

LPC_AD313,

32 32

LPC_AD213,

32

LPC_AD113,

32

LPC_AD013,

A_RST#13

EC_SCI

#14

KSO[

0..15] 37

SI[0..7] 37

K

USBAI

_EN34

_PEN#34

SLP_S3#14 SLP_S5#14 EC_LI

EC_SMI

#14

ON/OFF#35

1 2

R1036

2

C1358

22P_0402_50V8J

1

4

0.

1U_0402_16V4Z

1

C1347

2

1U_0402_16V4Z

LPC_CLK0_EC A_RST#

EC_SCI

1 2

R1015

_EN

USBAI USBAI

_PEN#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

SLP_S3# SLP_S5# EC_SMI

EC_I

NVT_PWM

FAN_SPEED

EC_TX_P80_DATA EC_RX_P80_CLK ON/

OFF#

NUM_LED#

EC_CRY EC_CRY

0_0402_5%

4

1

C1348

2

EC_GA20 EC_KBRST#

RQ

SERI LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

#

10K_0402_5%@

0

KSI

1

KSI

2

KSI KSI

3

KSI

4

KSI

5

KSI

6 7

KSI KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

#

1 2

2

C1349

1000P_0402_50V7K

1

U31

1

G

A20/GPIO00

2

KBRST#

3

RQ#

SERI

4

L

FRAME#

5

LA

D3

7

D2

LA

8

D1

LA

10

LA

D0

12

CLK

PCI

13

RST#/GPIO05

PCI

37

ECRST

#

20

CI#/GPIO0E

S

38

KRUN#/GPIO1D

CL

55

SI0/GPIO30

K

56

K

SI1/GPIO31

57

K

SI2/GPIO32

58

SI3/GPIO33

K

59

SI4/GPIO34

K

60

K

SI5/GPIO35

61

K

SI6/GPIO36

62

SI7/GPIO37

K

39

SO0/GPIO20

K

40

K

SO1/GPIO21

41

K

SO2/GPIO22

42

SO3/GPIO23

K

43

SO4/GPIO24

K

44

K

SO5/GPIO25

45

SO6/GPIO26

K

46

SO7/GPIO27

K

47

K

SO8/GPIO28

48

K

SO9/GPIO29

49

K

SO10/GPIO2A

50

SO11/GPIO2B

K

51

K

SO12/GPIO2C

52

K

SO13/GPIO2D

53

SO14/GPIO2E

K

54

SO15/GPIO2F

K

81

K

SO16/GPIO48

82

K

SO17/GPIO49

77

S

CL1/GPIO44

78

SDA1

/GPIO45

79

CL2/GPIO46

S

80

/GPIO47

SDA2

6

P

M_SLP_S3#/GPIO04

14

P

M_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

D_SW#/GPIO0A

LI

17

SUSP#

/GPIO0B

18

PBTN_

OUT#/GPIO0C

19

C_PME#/GPIO0D

E

25

THERM#/GPIO11

EC_

28

FAN_

SPEED1/FANFB1/GPIO14

29

FANFB2

30

TX/GPIO16

EC_

31

RX/GPIO17

EC_

32

ON

_OFF/GPIO18

34

PW

R_LED#/GPIO19

36

LED#/GPIO1A

NUM

122

K1

XCL

123

XCLK0

3

+3VALW

L65

1 2

BLM18AG601SN1D_2P

2

C1350

C1350 1000P_0402_50V7K

1000P_0402_50V7K

1

9

22

VCC

/GPIO01

PC & MISC

L

PS2 Interface

t. K/B

In

In Matrix

Matrix

SM Bus

/GPIO15

11

ecurity Classification

S

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AN

AN

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_VCCA

33

96

111

125

67

VCC

AVCC

IN

VT_PWM/PWM1/GPIO0F

BEEP#

AC

BATT_TEM

AD Input

TP P_DATA/PSDAT3/GPIO4F

T

SPI Flash ROM

BAT

GPIO

B

V

GPO

GPI

GND

35

94

113

OFF/FANPWM2/GPIO 13

BATT_

D

AC_BRIG/DA0/GPIO3C

EN_

_CLK/PSCLK3/GPIO4E

F

STCHG/SELIO#/GPIO50

T_CHGI_LED#/GPI O52

ATT_LOW_LED#/GPIO54

R_ON/XCLK32K/GPIO57

EC_ EC_

I

ND AG

KB930QF A1 LQFP 128P

69

20m

ECAGND

PWM Output

DA Output

SPI Device Interface

GPIO

GND

24

1

C1351

2

0.

1U_0402_16V4Z

ECAGND

21

D4/GPIO42

A3/GPIO3F

/GPIO4B

/GPIO4D

SPI

DI/RD#

DO/WR#

SPI

CS#

N/GPIO56

PXO10

G G

PXO11

/GPXID2

G

PXID3 PXID4

G GPXID5

PXID6

G

PXID7

G

V18R

L66

1 2

23 26

ACOFF

27

BATT_TEMP

63 64

ADP_I

65

AD_BI

66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

D0

1 2

0_0402_5%

R30

FAN_SET

EF

IR CHGVADJ

EC_MUTE# USB_ON# W

LAN_LED# BT_LED# TP_CLK TP_DATA

EN_W

OL VLDT_EN LI

D_SW#

EC_SPI

PX_EN

CHARGE_LED0#

CAPS_LED# CHARGE_LED1# PW

R_LED#

SON

SY VR_ON

N

ACI

EC_RSMRST# EC_LID_OUT# EC_ON EC_PME# FCH_PW BKOFF#

PE_GPI

EAPD EC_THERM# SUSP# PBTN_OUT#

1 2

R29

0_0402_5%

Compal Secret Data

ENBKL

CLK_L

RGD

O1

@

1 2

R32

0_0402_5%

TL_BKOFF#

1

C1359

7U_0603_6.3V6K

4.

2

Deciphered Date

ACOFF

ADP_I

AD_BI

D0 37

FAN_SET IR

EF 3 9

CHGVADJ

EC_MUTE#

USB_ON#

LAN_LED# 32

W

BT_LED#

TP_CLK

TP_DATA

VGATE EN_W

VLDT_EN

LI

EC_SI EC_SO_SPI

EC_SPI

CEN#

PX_EN FSTCHG CHARGE_LED0# CAPS_LED# CHARGE_LED1#

PW SY

SON 38,43

VR_ON

N 39

ACI

EC_RSMRST#

EC_ON

FCH_PW

BKOFF#

L_OFF#_EC 32

W

RF_LED#

VGA_ON

PE_GPI

ENBKL

EAPD

EC_THERM#

SUSP# 32,38

PBTN_OUT#

/PWM2/GPI O10

NPWM1/GPIO12

FA

P/AD0/GPIO38

OVP/AD1/GPIO39

ADP_

I/AD2/GPIO 3A

D3/GPIO3B

A

S

ELIO2#/AD5/GPIO43

DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

D

SCLK1/GPIO4A

P PSDAT1 P

SCLK2/GPIO4C

PSDAT2

CS#/GPXOA00

SDI

CLK/GPXOA01

SDI

DO/GPXOA02

DIDI/GPXID0

S

SPI

CLK/GPIO58

SPI

R_RX/GPIO40

CI

R_RLC_TX/GPIO41

LED#/GPIO53

CAPS_

SUSP_

LED#/GPIO55

SYSO

A

C_IN/GPIO59

RSMRST#/GPXO03

LID_OUT#/GPXO04

EC_ON/GPXO05

C_SWI#/GPXO06

E

CH_PWROK/GPXO 06

BKO

FF#/GPXO08

L_OFF#/GPXO09

W

M_SLP_S4#/GPXID1

P

ENBKL

il

FBM-11-160808-601-T_0603

2010/08/04 2011/12/31

3

39

35

39

OL 29

D_SW# 35

_SPI_SO 35

CS#/FSEL# 35

R_LED# 32,35

D_OUT# 14

O1 13,25

C1360

30

34

32

37

47

38,46

_SI 35

34 22,25 39

47

35

RGD 14

27

32

25

30

14

2

32

14

ENBKL 10

8,13,47

TL_BKOFF#

2

D

100P_0402_50V8J

ECAGND

12

40

BATT_TEMP

D

elay EC_PWROK 50ms

for VGA criterial

elay SUSP# 10ms

26,27

E_WAKE#14,29,32

FCH_PCI

1

+3VS

FCH_PW

TP_CLK

TP_DATA

R1033

CLK_L

EC_SPI

Title

Size Document Number Rev

B

Date: Sheet

1 2

FBMA-

10-100505-101T

ACI

N

ENBKL

@

1 2

0_0402_5%

R2

Compal Electronics, Inc.

EC ENE KB930

BL50 LA-7551P

Q

@

RGD

1 2

R1035

Reser

C1363

10K_0402_5%

7K_0402_5%

@

33P_0402_50V8K

C1357

ve for EMI, close to EC

100P_0402_50V8J

12

1 2

@

+3VALW

12

1

EC_SPI

CLK 35

R1034100K_0402_5%

R1032

R1032 10K_0402_5%

10K_0402_5%

@

EC_PME#

36

+5VS

12

R10184.

12

R10194.

53Friday, April 29, 2011

of

1.0

INT_KB

C

D Conn.

SI[0..7]

K

SO[0..15]

K

KSO

KSI

KSO

2

C1543

15

C1546

6

C1547

8

C1549

13

C1551

12

C1553

11

C1555

10

C1557

3

C1559

4

C1561

0

C1563

0

C1565

1 2

SI[0..7] 36

K

SO[0..15] 36

K

100P_0402_50V8J@

ONN PIN define need double check

+5

VS

C1567

1U_0402_16V4Z

0.

P_CLK36

T

_DATA36

TP

100P_0402_50V8J

1

@

C1568

2

Left side Button

NTC010-BB1G-C100C

SW

/L

SW

2

4

5

SW

1

2

Y

/L

SW

/R

@

C1569

C1569 100P_0402_50V8J

100P_0402_50V8J

SDA0502C 3P C/A SOT-23

5

1

3

1

KSO

C1544

1 2

7

KSO

C1545

1 2

2

KSI

C1548

KSO

KSI

KSO

KSI

KSO

KSI

1 2

5

C1550

1 2

3

C1552

1 2

14

C1554

1 2

7

C1556

1 2

6

C1558

1 2

5

C1560

1 2

4

C1562

1 2

9

C1564

1 2

1

C1566

1 2

T

P_CLK

TP

_DATA

2

3

1

3

D17

@

1

Right side Button

NTC010-BB1G-C100C

/R

SW

2

4

100P_0402_50V8J@

To

TP/B Conn.

P1

JT

1

2

3

4

5

6

ACES_85201-06051

2

D28

@

SDA0502C 3P C/A SOT-23

Y

For

ESD.

Close to JTP1

6

SW

1

3

5

G GND2

+

VGA_CORE

ID

ACES_88514-02401-071

26

ND2

G

25

ND1

G

15

KSO

24

0

KSO

23

7

KSO

22

5

KSO

21

KSO KSO KSO KSO KSO KSO KSO KSI KSI KSI KSI KSI KSI KSI KSI KSO KSO KSO KSO KSO

7

ND1

8

21

2

20

4

19

8

18

6

17

11

16

10

15

12

14

3

13

0

12

2

11

4

10

6

9

7

8

1

7

5

6

13

5

1

4

3

9

2

14

1

J

KB1

CONN@

SPK_

R130

SPK_

R230

SPK_

L130

SPK_

L230

SDA0502C 3P C/A SOT-23

Y

SPK_ SPK_ SPK_ SPK_

3

R1 R2 L1 L2

2

1

C435

+

2

VG

A@

+

CPU_CORE_NB

C1010

ZZZ

PCB

D9

@

_Y

330U_D2_2V

1

+

2

1

C436

+

_Y

2

330U_D2_2V

VG

A@

.5VSG

+1

1

VGA@

C374

_Y

2

330U_D2_2V

C1011

330U_D2_2V_Y+C1011

330U_D2_2V_Y

1

+

_Y

2

1 2 3 4 5 6

ACES_85205-04001

For ESD.

2

3

Close to JSPK1

D10

@

1

SDA0502C 3P C/A SOT-23

Y

1

C474

+

_Y

2

330U_D2_2V

A@

+

SPK1

J

1 2 3 4 G5 G6

CONN@

Secu

rity Classification

I

ssued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MA

AD

_BID036

BRD ID3Ra Rb Vab

R1024

R1026

Ra

100K

1 2

0

1

2

R01 SR

R02 ER

R10 MP

Reserve

_BID0

AD

Rb

H5

H_3P

H4

0

1

H12

0

1

H20

0

1

H5

8

H_3P

@

1

H13

H_3P

0

@

1

H21

0

H_3P

@

1

H3

0X6P0N

H_10P

@

1

FD

2

1

FIDUCIAL_C40M80

H2

8

H_3P

@

1

H11

H_4P

3

@

1

H19

0

H_3P

@

1

H1

7X5P0N

H_2P

@

1

FD

1

FIDUCIAL_C40M80

Close to LED1

Close to LED2

Close to LED3

Close to LED4

Close to LED5

For ESD.

Cap to LED gap is 1.2mm.

pal Secret Data

Com

2011/03/04

Com

Deciphered Date

0

0V

8.2K

0.25V

18K

0.5V

33K

0.82V

+

3VALW

100K_0402_5%

18K_0402_5%

H6

H8

0

8

H_3P

@

1

H15

H14

H_4P

3

@

1

H23

H22

3

0

H_3P

H_7P

@

1

H7

H17

0

6N

@

1

FD

FIDUCIAL_C40M80

1 2

0.1U_0603_25V7K

1 2

0.1U_0603_25V7K

1 2

H_2P

1

6N

1

3

H_3P

C1644 0.1U_0603_25V7KC1644 0.1U_0603_25V7K

C1645 0.1U_0603_25V7KC1645 0.1U_0603_25V7K

C1646

C1647

C1648 0.1U_0603_25V7KC1648 0.1U_0603_25V7K

H9

8

H_3P

1

H16

H_3P

0

1

@

2011/12/31

H10

3

H_4P

@

1

H18

H_3P

8

@

1

FD

4

1

FIDUCIAL_C40M80

Title

Size Docum ent Number Rev

Custom

Date: Sheet

P9 FS1 PW

C993

1

+

2

C

ompal Electronics, Inc.

L50 LA-7551P

QB

R/GND

U_CORE

+CP

C995

330U_D2_2V_Y+C995

330U_D2_2V_Y

C1014

C994

330U_D2_2V

C994

330U_D2_2V

C999

1

+

_Y

2

P

33-Other IO/USB (right)

C1014

330U_D2_2V_Y+C999

330U_D2_2V_Y

1

+

2

1

+

2

ote: Differential page:

N P1,P2,P9,P29,P37 And Power schematic.

37 53Wednesday, April 27, 2011

330U_D2_2V

_Y

@

of

1.0

A

ʾˈ˩˔˟˪ʳ˧ˢʳʾˈ˩˦ʳʻˈ˔ʼ

ʾˈ˩˔˟˪ʳ˧ˢʳʾˈ˩˦ʳʻˈ˔ʼʾˈ˩˔˟˪ʳ˧ˢʳʾˈ˩˦ʳʻˈ˔ʼ

10U_0805_10V4Z

1

2

1 1

1 2

+VSB

1103 47K_0402_5%

R

SSM3K7002FU_SC70-3

ʾˆ˩˔˟˪ʳ˧ˢʳʾˆ˩˦ʳʻˆˁˆ˔ʼ

ʾˆ˩˔˟˪ʳ˧ˢʳʾˆ˩˦ʳʻˆˁˆ˔ʼʾˆ˩˔˟˪ʳ˧ˢʳʾˆ˩˦ʳʻˆˁˆ˔ʼ

10U_0603_6.3V6M

1

C

C 1453

1453

2

+VSB

2 2

ʾ˄ˁˈ˩ʳ˧ˢʳʾ˄ˁˈ˩˦ʳʻ˄ˁˈ˔ʼ

ʾ˄ˁˈ˩ʳ˧ˢʳʾ˄ˁˈ˩˦ʳʻ˄ˁˈ˔ʼʾ˄ˁˈ˩ʳ˧ˢʳʾ˄ˁˈ˩˦ʳʻ˄ˁˈ˔ʼ

3 3

+1.0VSG

R

1112 200K_0402_5%

SUSP

SSM3K7002FU_SC70-3

SUSP#

+5

10U_0805_10V4Z

C

1

1443

2

5

VS_GATE

SUSP

+3

10U_0603_6.3V6M

1

C

C 1454

1454

2

VS_GATE

3

12

Q5

2

G

+1.

5V

100K_0402_5%

1122

R

12

47K_0402_5%

1463

C

0.22U_0603_16V4Z

+VGA_CORE

VALW

U3

8

SI4800BDY-T1-GE3_SO8

8 7

5

C

C 1445

1445

13

D

6

Q5

2

G

S

VALW

U4

0

SI4800BDY-T1-GE3_SO8

8 7

5

13

D

9

S

R

1116

1 2

Q6

2

G

1

2

1 2 36

4

1

1450

C

0.1U_0603_25V7K

2

1 2 36

4

1

1456

C

0.1U_0603_25V7K

2

AP2301GN-HF_SOT23-3

3

Q6

3 1

2

13

D

0

S

SSM3K7002FU_SC70-3

10U_0603_6.3V6M

+3V

10U_0603_6.3V6M

1

2

+1.8VSG

1

2

10U_0805_10V4Z

C

C 1461

1461

S

+5V

C

1

1446

2

1U_0402_6.3V6K

C

C 1452

1452

+1.

5VS

R

R 470_0603_5%

470_0603_5%

1 2

13

D

Q6

S

SSM3K7002FU_SC70-3

1117

1U_0603_10V6K

12

C

1

1455

2

1

2

G

C

C 1444

1444

D

S

R

R 470_0603_5%

470_0603_5%

1 2 13

D

Q5

S

SSM3K7002FU_SC70-3

SUSP

B

1099

R

R 470_0603_5%

470_0603_5%

1 2

13

5

Q5

SUSP

2

G

SSM3K7002FU_SC70-3

1110

8

SUSP

2

G

+1.2VS

C

ʾ˄ˁ˄˩˔˟˪ʳ˧ˢʳʾ˄ˁ˄˩˦ʳʻ˄ˁ˄˔ʼ

ʾ˄ˁ˄˩˔˟˪ʳ˧ˢʳʾ˄ˁ˄˩˦ʳʻ˄ˁ˄˔ʼʾ˄ˁ˄˩˔˟˪ʳ˧ˢʳʾ˄ˁ˄˩˦ʳʻ˄ˁ˄˔ʼ

1100

R

1K_0402_5%

1 2

+VSB

R

1105 47K_0402_5%

VL

DT_EN#

SSM3K7002FU_SC70-3

˩˚˔ʳˣ˸

˩˚˔ʳˣ˸˩˚˔ʳˣ˸

+1.5V to +1.5VSG

1

.5_VDDC_PWREN#

10U_0603_6.3V6M

12

4

Q6

2

G

+VSB

0.1U_0402_16V7K

+1

.1VALW

8 7 6 5

1

C

C 1448

1448

2

1VS_GATE

1.

13

D

S

10U_0603_6.3V6M

1118 100K_0402_5%

R

1120 47K_0402_5%VGA@R1120 47K_0402_5%VGA@

R

SSM3K7002FU_SC70-3

VGA@

1464

C

9

U3

U3 AO4430L_SO8

AO4430L_SO8

(1.5A)

10U_0603_6.3V6M

VGA@

1

C

C 1459

1459

2

VGA@

1 2

12

VGA@

1

2

4

1 2 3

1

1451

C

0.1U_0603_25V7K

2

5V

+1.

8 7 6 5

1

VGA@

C

C 1460

1460

2

1.

13

D

Q7

4

2

G

S

+1.

1VS

10U_0603_6.3V6M

1

2

U4

1

VGA@

1

VGA@

AO4430L_SO8

5VSG_GATE

C1447

4

1U_0402_6.3V6K

C

1

1449

2

.5VSG

+1

1 2

10U_0603_6.3V6M

3

1

C

1462

VGA@

0.1U_0603_25V7K

2

1101

R

R 470_0603_5%

470_0603_5%

1 2 13

D

7

Q5

VL

DT_EN#

2

G

S

SSM3K7002FU_SC70-3

VGA@

1

VGA@

1458

C

C 1457

1457

1U_0402_6.3V6K

2

D

DT_EN36,46

VL

10K_0402_5%

VGA@

1114

R

R 470_0603_5%

470_0603_5%

1 2 13

D

3

Q7

.5_VDDC_PWREN#

1

2

G

VGA@

S

SSM3K7002FU_SC70-3

E

1104

1123

VALW

+5

1098

R

R 100K_0402_5%

100K_0402_5%

1 2

SY

SON#

13

D

2

Q5

2

G

12

S

SM3K7002FU_SC70-3

SM3K7002FU_SC70-3 S

S

VALW

+5

R

1108

100K_0402_5%

1 2

SUSP

13

D

Q5

3

2

G

12

S

SSM3K7002FU_SC70-3

VALW

+5

1 2

13

8

SSM3K7002FU_SC70-3

1119

R

R 100K_0402_5%

100K_0402_5%

D

S

R

1109

Q6

2

G

12

5VALW

+

1097

R

R 100K_0402_5%

100K_0402_5%

1 2

VL

DT_EN#

13

D

Q5

1

2

G

12

S

1102

R

S

SSM3K7002FU_SC70-3

VG

SY

SON36,43

R

100K_0402_5%

SUSP28,

45

SUSP#32,

36

10K_0402_5%

VG

A_PWR_ON#

A_PWR_ON25,42,45

R

100K_0402_5%

1128

1127

1126

1125

R

R 470_0603_5%

470_0603_5%

VGA@

1 2

13

D

7

Q6

A_PWR_ON#

VG

2

G

VGA@

S

SSM3K7002FU_SC70-3

5V

+1.

4 4

R

1135

470_0603_5%

1 2

13

D

Q71

2

G

S

SSM3K7002FU_SC70-3

SON#

SY

1126

R

R 470_0603_5%

470_0603_5%

VGA@

1 2

13

D

6

Q6

2

G

S

SSM3K7002FU_SC70-3

5VS

+2.

R

1136

470_0603_5%

1 2

13

D

Q72

2

G

S

SSM3K7002FU_SC70-3

A

.5_VDDC_PWREN#

1

VGA@

1127

R

R 33_0603_5%

33_0603_5%

VGA@

1 2

13

D

5

Q6

VG

2

G

VGA@

S

SSM3K7002FU_SC70-3

75VS

+0.

R

1137

470_0603_5%

1 2

13

D

Q70

2

G

S

SSM3K7002FU_SC70-3

A_PWR_ON#

SUSPSUSP

1128

R

R 470_0603_5%

470_0603_5%

1 2

13

D

2

Q6

VL

2

G

S

SSM3K7002FU_SC70-3

B

DT_EN#

+3VS to +3VSG (3.3A)

hange to Jump

C 201012062000

+3V

S

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VALW

+5

1131

R

1 2

13

7

Q7

2

G

12

SSM3K7002FU_SC70-3

38 53Wednesday, April 27, 2011

R 100K_0402_5%

100K_0402_5%

D

S

of

1.0

14

@PJ14

@

PJ

2

+3

112

JUMP_43X118

2010/

C

VSG

pal Secret Data

Com

08/04 2011/12/31

Com

Deciphered Date

D

.5_VDDC_PWREN#

1

1.5_VDD_PWREN25,48

Compal E

Ti

Title

tle

Size Document Number Rev

B

Date: Sheet

Compal E

DC Interface

QB

L50 LA-7551P

R1134

10K_0402_5%

lectronics, Inc.

E

A

Q101

P

AO4435L_SO8

R109

2

AO4435L_SO8

8 7

5

4

P

Q104

2

HG_N_010 C

1 3

13

Q105

P

P S TR LTC015EUBFS8TL NPN UMT3F

S TR LTC015EUBFS8TL NPN UMT3F

SSM6N7002FU_US6

HG_N_009

C

R124

P

22K_0402_5%

N

PACI

1 2

ACOFF

2

VIN

1 1

S TR LTA044EUBFS8TL PNP UMT3F

12

P

2

ACOFF36

P

HG_N_001 C

61

PQ107A

SSM6N7002FU_US6

47K_0402_1%

2 2

3 3

P2

AO4409L_SO8

0.1U_0603_25V7K

5

IREF36

Q111

P

AO4409L_SO8

1 2 3 6

12

P

R107

200K_0402_1%

HG_N_003

C

12

P

R116

150K_0402_1%

HG_N_002 C

34

150K_0402_1%

1 2 36

12

C108

C108 P

P

Q107B

P

13

S TR LTC015EUBFS8TL NPN UMT3F

Q102

P

4

TCHG36

FS

R103

P

140K_0402_1%

8 7

5

C107

C107 P

P

@5600P_0402_25V7K

0.01U_0402_25V7K

AD

12

R104

P

1 2

P_I36

12

P3

10K_0402_1%

C116 6800P_0402_25V7K

P

C117

1 2

6251V

12

C122

C122 P

P

0.01U_0402_25V7K

GVADJ36

CH

P

R114

1 2

P

R121 10K_0402_1%

1 2

P

C120

0.1U_0402_16V7K

REF

12.4K_0402_1%

20K_0402_1%

R101

P

0.02_1206_1%

1

2

12

R117

R117 P

P

R123 100_0402_1%

R127

P

1 2

R128

P

10K_0402_1%

1 2

B

6251V

DD

ACSETI

12

100K_0402_1%

1 2

CHG_

12

R105

4

3

C109

C109 P

P

2.2U_0603_6.3V6K

N

6251_E

P

R130

0_0402_5%

CHG_

ICOMP

CHG_

VCOMP

6251VREF

CHLIM

clim

6251a

_VADJ

CHG

1 2

B+

RB751V-40TE17_SOD323-2

12

1

2

N

3

4

5

6

CHG_

ICM

7

8

9

10

11

12

R106

P

22K_0402_1%

@10U_0805_25V6K

VIN

191K_0402_1%

P

D101

1 2

_VIN

P

R113

CHG

1 2

U101

P

10_1206_5%

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

ISL6251AHAZ-T QSOP 24P

C119 @10U_0805_25V6K

P

1 2

P

C115

1 2

L102

P

1.2UH_1231AS-H-1R2N=P3_2.9A_30%

P

R108

1 2

12

C112

P

N

1U_0603_25V6K

DCI

1 2

ACPRN

CSON

CHG_

P

C113

0.047U_0603_16V7K

CSOP

1 2

CHG_

CSIN

P

C118

0.1U_0603_25V7K

CHG_

CSIP

1 2

LX

_CHG

CHG

DH_

R126

P

2.2_0603_5%

CHG

BST_

1 2

DDP

6251V

DL

_CHG

1 2

12

CSI

ACSETI

N

12

C110

C110 P

P

R111

R111 P

P

1000P_0402_50V7K

14.3K_0402_1%

PR118

20_0603_5%

1 2

P

R119

20_0603_5%

P

R120

20_0603_5%

1 2

P

R122

2.2_0603_1%

2.2_0603_1% R134

R134

P

0_0402_5%

1 2

0.1U_0603_25V7K

CHGA

BST_

12

D106

P

P RB751V-40TE17_SOD323-2

RB751V-40TE17_SOD323-2

1 2

P

4.7_0603_5%

C123

P

4.7U_0805_6.3V6K

PR131

47K_0402_1%

MMBT3904WH NPN SOT323-3

CSI

N

P

12

R129

ACPRN

C

1 2

HG_N_008 C

13

B+

AO4407AL 1P SO8

1 2 3 6

CHG_N_005

R110

P

200K_0402_1%

1 2

CHG_

2

P

@2200P_0402_25V7K

CHG

1

2

CHG_

B+

12

C103

C103 P

P

4.7U_0805_25V6-K

12

PC125

@10U_0805_25V6K

CSON

CSOPCHG_

C121

P

12

6251V

DD

6251V

DD

12

R132

P

P 10K_0402_1%

10K_0402_1%

C

PQ112

2

B

E

3 1

12

PC111

@10U_0805_25V6K

12

PC105

0.1U_0402_25V6

S TR LTC015EUBFS8TL NPN UMT3F

Q108

P

P AON7408L_DFN8-5

AON7408L_DFN8-5

3 5

241

5

P

Q110

4

AON7406L_DFN8-5

123

R133

P

10K_0402_1%

1 2

PACI

R136

P

P 20K_0402_1%

20K_0402_1%

PC106

2200P_0402_25V7K

P

R112

47K_0402_1%

Q106

P

L101

10UH +-20% MSCDRI-104A-100M-E

1 2

12

PR125

4.7_1206_5%

_SNUB

CHG

12

PC124

680P_0402_50V7K

AC

IN 3 6

N

12

C104

C104 P

P

10U_0805_25V6K

P

4

VI

N_006

C114

P

R102

0.02_1206_1%

D

Q103

N

P

R115

100K_0402_1%

1 2

13

D

12

S

@SSM3K7002FU_SC70-3

4

3

8 7

5

C

HG_N_001

ACPRN

2

G

P

Q109

BA

TT+

12

C101

C101 P

P

10U_0805_25V6K

12

PC126

PC102

10U_0805_25V6K

4 4

ecurity Classification

S

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

EPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2011/12/31

C

ompal Secret Data

Dec

iphered Date

C

Co

mpal Electronics, Inc.

tle

Ti

Size Document Number Rev

Date: Sheet

mpal Electronics, Inc.

ER

CHARG

39

D

39

53Wednesday, April 27, 2011

of

1.

0

A

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

1

68_1206_5%

HCB2012KF-121T50_0805

1 2

12

PC2

_0402_50V8J

100P

N

VI

PD3

LS4148_LL34-2

R

1 2

S_N_001 V

12

7

PR1

13

12

PC1

0.1U_0603_25V7K

ADPI

N

PDC1

PJ

4

3

1 1

PJ

10

GND

11

2 2

3 3

4 4

GND

@SUYIN_200275MR009G186ZL

2

1

@CVILU_CI0104P1VRB-NH

P2

1

2

3

4

5

6

7

8

9

BATT+

N#35

51_O

EC_ EC_ TS_A

SMCA SMDA

LS4148_LL34-2

R

PD1

PD4

100K_0402_1%

1 2

PR22

22K_0402_1%

2

PR2

1

12

3

12

1

12

PJSOT24CW_SOT323-3

PJSOT24CW_SOT323-3 @

@

100_0402_1%

PR3

100_0402_1%

PR3

0

1 2

1K_0402_1%

12

3

PC1

@10U_0805_25V6K

1 2

2

3

PR2

8

1 2

1

1 2

100K_0402_5%

TP0610K-T1-GE3_SOT23-3

N1

1

PC1

0.22U_0603_25V7K

VS_N_002

PC1

_0402_50V7K

1000P

PR2

7

1K_0402_1%

PD2

@

PJSOT24CW _SOT323-3

PR2

9

3

PQ

2

PL

1

PL

2

VALW

+3

BATT_TEM

12

PR1

PR1 68_1206_5%

68_1206_5%

2

B

C

D

PH1 under CPU botten side :

VI

N

12

PC3

_0402_50V7K

1000P

EC_

SMB_CK1 36

SMB_DA1 36

EC_

P 36

8

VS

12

4

PC1

PC4

_0402_50V8J

100P

@10U_0805_25V6K

100P

HCB2012KF-121T50_0805

B

VM

HCB2012KF-121T50_0805

12

PC6

_0402_50V7K

1000P

PL

3

1 2

4

PL

1 2

PC127

10U_0805_25V6K

1U_0603_16V7K

0.

X7R type

12

PC7

01U_0402_25V7K

0.

PC5

BATT+

CPU thermal protection at 92 +-3 degree C Recovery at 80 +-3 degree C

VL

12

PU1

100K_0402_1%

K41,44

SPO

PU1

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G

718TM1U_SOT23-8

TP_N_003 O

PR4

12

0_0402_5%

B+

VL

3

PR1

6

PR1

1 2

0_0402_5%

VSB_N

1 2

+VSBP +VSB

(120mA,40mils ,Via NO.= 1)

8

7

6

5

VS_ON

_002

12

PC10

PJ

2

@JUMP_43X39

O

2

G

0.1U_0402_16V7K

2

TP_N_001

O

TP_N_002

41

_003

VSB_N

13

112

22K_0402_1%

D

S

2

PR1

1 2

PQ

2

SSM3K7002FU_SC70-3

12

PR10

100K_0402_1%

12

PC8

VSB_N_001

0.22U_0603_25V7K

12

R2 22.1K_0402_1%

P

12

PH1

_0402_1%_NCP15WF104F03R C

100K

13

2

1

PQ

TP0610K-T1-GE3_SOT23-3

PR1

22K_0402_1%

1 2

+VSBP

12

PC9

0.1U_0603_25V7K

Security Classification

Issued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D D

D

EPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ompal Secret Data

C

Deciphered Date

C

2011/

Co

mpal Electronics, Inc.

tle

Ti

12/312009/01/23

Ti

Size Document Number Rev

Date: Sheet

mpal Electronics, Inc.

NN / OTP

DCIN / BATT CO

61 LA-6321P M/B

NCL

D

NN / OTP

0

1.

of

40 53Wednesday, April 27, 2011

of

40 53Wednesday, April 27, 2011

of

40 53Wednesday, April 27, 2011

A

B

2VR

C

EF_6182

D

E

1 1

1U_0603_16V6K

R301

P

13.7K_0402_1%

1 2

R302

P

12

C309

C309 P

P

0.1U_0402_25V6

+3VA

B++

12

C310

C310 P

P

2200P_0402_50V7K

LWP

150U_B2_6.3VM_R35M

SSM6N7002FU_US6

VS_

VS

12

C304

C304 P

P

4.7U_0805_25V6-K

P

L303

4.7UH_FMJ-0630T-4R7 HF_5.5A_20%

1

+

C303

P

2

Q307A

P

ON40

1 2

P

R319

100K_0402_1%

12

P1

ENTRI

61

D

S

R320

R320 P

P

42.2K_0402_1%

12

G

R312

R312 P

P

4.7_1206_5%

C316

C316 P

P

680P_0402_50V7K

2

C321

C321 P

P

2.2U_0603_10V6K

12

3V

SNUB_

12

N

_3_5V_001

Q303

P

P AON7408L_DFN8-5

AON7408L_DFN8-5

3 5

241

786

5

Q304

P

4

AO4468L_SO8

123

P2

ENTRI

34

D

Q307B

P

1 2

R317

P

100K_0402_5%

Q308

P

SSM6N7002FU_US6

S

5

G

13

P

P S TR LTC015EUBFS8TL NPN UMT3F

S TR LTC015EUBFS8TL NPN UMT3F

P

C313

10U_0805_6.3V6M

C314

P

0.1U_0402_10V7K

1 2

LX_3V

VL

+3VL

12

B

ST1_3V

1 2

P

R318 0_0402_5%

1 2

B++

95.3K_0402_1%

P

R308

1 2

2.2_0402_5%

LG

_3V

P

R314

499K_0402_1%

EN0

R315

P

B+

2 2

3 3

4 4

L301

P

HCB2012KF-121T50_0805

1 2

12

C322

C322 P

P

@10U_0805_25V6K

133K_0402_1%

BST_

U

12

+5VALWP

VALWP

+3

P

20K_0402_1%

1 2

R303

P

1 2

25

7

8

3V

9

G_3V

10

11

12

C320

P

P 1U_0603_10V6K

1U_0603_10V6K

2VR

EF_6182

P

U301

P PAD

VO

VREG

B

OOT2

UG

PHASE2

L

GATE2

C308

P

FB_3V

P2

ENTRI

6

P2

ENTRI

2

3

ATE2

EN

13

B++

P306

PJ

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJ

PJ

P305

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJ

PJ

P303

1 2

PAD-OPEN 4x4m

5

14

FB2

PSEL

SKI

12

4

15

NSEL TO

D

GN

P

30.9K_0402_1%

1 2

P

P 20K_0402_1%

20K_0402_1%

FB_5V

1 2

P1

ENTRI

1 2

3

2

1

FB1

REF

ENTRIP1

1

VO

GOOD

P

B

OOT1

UG

ATE1

PHASE1

L

GATE1

N

NC18VREG5

VI

16

17

RT8205LZQW(2) WQFN 24P PWM

12

C318

P

4.7U_0805_10V6K

12

C319

P

0.1U_0603_25V7K

(5A,200mils ,Via NO.= 10)

VALW

+5

(5A,200mils ,Via NO.= 10)

VALW

+5

(4A,120mils ,Via NO.= 8)

VALW

+3

R305

R306

R307

P

P 165K_0402_1%

165K_0402_1%

24

23

22

21

20

19

VL

BST_

U

G_5V

LX_5V

LG

2.2_0402_5%

5V

1 2

_5V

R309

P

B++

12

PC312

PC311

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

B

ST1_5V

1 2

P

R321 0_0402_5%

S

POK 40,44

12

C306

C306 P

P

C315

P

0.1U_0402_10V7K

1 2

S TR AO4406AL 1N SO8

P

Q305

5

+3VL

VL

3 5

241

786

Q305

AON7408L_DFN8-5

123

P

2 1

PAD-OPEN 2x2m

2 1

PAD-OPEN 2x2m

P

L305

4.7UH_FMJ-0630T-4R7 HF_5.5A_20%

1 2

12

+

CHGRTC

1

+

P

P 150U_B2_6.3VM_R35M

150U_B2_6.3VM_R35M

2

5V

SNUB_

12

P302

PJ

P301

PJ

R313

R313 P

P

4.7_1206_5%

C317

C317 P

P

680P_0402_50V7K

C305

+5VA

LWP

10U_0805_25V6K

4

Q306

P

EC:+3VL, reserve PR319, install PR318, PR320 100K EC:+3VALW, reserve PR318, install PR319, PR320 42.2K

A

B

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/

08/02 2011/12/31

pal Secret Data

Com

Deciphered Date

D

Co

mpal Electronics, Inc.

Title

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

mpal Electronics, Inc.

.3VALWP/5VALWP

3

BL50 LA-7551P

Q

41 53Wednesday, April 27, 2011

E

of

1.0

A

1 1

L402

P

HCB1608KF-121T30_0603

VALW

+5

2 2

VGA

1 2

12

_PWR_ON25,38,45

1 2

P

R404 200K_0402_5%

D401

P

1 2

@1SS355_SOD323-2

C403

P

P 22U_0805_6.3VAM

22U_0805_6.3VAM

EN_

1.8VSP

@47K_0402_5%

1

.8VSP_VIN

P

R405

12

B

P

U401

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

S IC RT8061AZQW W DFN 10P PWM

C405

C405 P

P

0.1U_0402_10V7K

S IC RT8061AZQW W DFN 10P PWM

1.

8VSP_LX

2

LX

3

LX

.8VSP_FB

1

6

FB

NC

1

C406

C406 P

P

680P_0402_50V7K

P

L401

1 2

R403

R403 P

P

4.7_1206_5%

L401

P

R401

20K_0402_1%

R402

P

10K_0402_1%

12

1UH_VLS252012T-1R0N1R7_2.4A_30%

12

NUB_1.8VSP S

12

C

<Vo=1.8V> VFB=0.6V

.8VSGP

+1

12

PC404

68P_0402_50V8J

12

C402

C402 P

P

PC401

22U_0805_6.3VAM

Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V

D

PJ

P401

.8VSGP

+1

3 3

4 4

A

1 2

PAD-OPEN 3x3m

B

(2A, 80mils, Via NO.= 4)

.8VSG

+1

ecurity Classification

S

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

EPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

ompal Secret Data

Dec

iphered Date

C

2011/12/312009/01/23

Co

mpal Electronics, Inc.

tle

Ti

Size Document Number Rev

Date: Sheet

mpal Electronics, Inc.

+1.8VSGP

61 LA-6321P M/B

NCL

D

53Wednesday, April 27, 2011

of

42

of

42

of

42

0

1.

5

D D

PR503

N36,38

SYSO

C C

+5VALW

5VP

+1.

1 2

PR507

100_0402_1%

PC509

4.

7U_0603_10V6K

0_0402_5%

LT_1.5V

V5FI

+1.

12

PC505

12

0.1U_0402_10V7K

@

5VP

2.

PR506

255K_0402_1%

1 2

PR501

1 2

2.

21K_0402_1%

PR502

15K_0402_1%

TON_1.

12

FB_1.

4

5V

EN_1.

PR504

2_0402_5%

2.

BST_1.

5V

14

1

PU501

5V

2

TO

3

VO

4

VDD

5V

5

FB

6

GOOD

P

15

NC

OOT

GND7PG

8

B

ATE

UG

PHASE

CS

VDDP

ATE

LG

ND

RT8209MGQW

N

EN/DEM

UT

BST1_1.

1 2

UG_1.

5V

13

LX_1.

5V

12

P_1.5V

TRI

11

+5VALW

10

LG_1.

5V

9

_WQFN14_3P5X3P5

5V

1 2

PC508

0.

1U_0402_10V7K

PR508

1 2

12

PC510

4.

3

0_0402_5%

1 2

15K_0402_1%

+5VALW

7U_0805_10V6K

PR505

FDS6690AS-

PQ502

G_SO8

1.

5V_B+

578

PQ501

PQ501 AON7408L_DFN8-

AON7408L_DFN8-

3 5

241

3 6

241

12

PC503

10U_0805_25V6K

12

SNUB_1.5V

12

2

HCB1608KF-

12

PC504

@4.7U_0805_25V6-K

5

PL501

L 1UH +-20% VMPI0703AR-1R0M-Z01 11A

S COI

1 2

PR509

4.7_1206_5%

PC511

680P_0402_50V7K

12

PC506

2200P_0402_50V7K

PL502

PC507

0.1U_0402_25V6

1

2

121T30_0603

12

.5VP

+1

+

PC501

PC501 220U_6.

220U_6.

12

3VM_R15

B+

PC512

10U_0805_25V6K

10U_0805_25V6K @

@

1

B B

+1.

5VP

A A

ecurity Classification

S

2007/05/29 2011/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AN

AN

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2011/12/31

3

Compal Secret Data

Deciphered Date

PJP502

1 2

PAD-OPEN 4x4m

@

PJP501

1 2

@

PAD-OPEN 4x4m

(8A,320mils ,Via NO.= 16)

+1.

5V

Inc.

Compal Electronics,

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics,

+1.5VP

50 LA-7551P

QBL

1

Inc.

43

1.0

53W ednesday, April 27, 2011

of

5

4

3

2

1

D D

K40,41

SPO

1VALW

+1.

+5VALW

C C

B B

1 2

PR707

100_0402_1%

4.

7U_0603_6.3V6M

PC708

PR703

0_0402_5%

LT_1.1V

V5FI

+1.

1VALW

12

PC704

12

@

4.

64K_0402_1%

10K_0402_1%

0.1U_0402_10V7K

PR705

255K_0402_1%

1 2

PR701

1 2

PR702

TON_1.

FB_1.

12

1V

EN_1.

2

3

4

5

6

1V

PU701

TO

VO

VDD

FB

P

N

UT

GOOD

1

EN/DEM

GND7PG

15

NC

BST_1.

14

BOOT

ATE

UG

PHASE

CS

VDDP

ATE

LG

ND

RT8209MGQW

8

PR704

2_0402_5%

2.

1V

1 2

13

12

11

10

9

_WQFN14_3P5X3P5

UG_1.

LX_1.

TRI

LG_1.

1V

P_1.1V

1V

BST1_1.

0.

1 2

+5VALW

1V

1 2

PC707

1U_0402_10V7K

PR708

14K_0402_1%

+5VALW

12

PC709

4.

7U_0805_10V6K

PR710

0_0402_5%

1 2

AO4468L_SO8

PQ702

1.

1V_B+

1

PC703

2

@10U_0805_25V6K

PQ701

PQ701 AON7408L_DFN8-

AON7408L_DFN8-

3 5

241

786

5

4

123

12

SNUB_1.1V

12

PC705

PC702

2

10U_0805_25V6K

2200P_0402_50V7K

5

PL701

2UH_PCMC063T-2R2MN_8A_20%

2.

PR709

4.7_1206_5%

PC710

680P_0402_50V7K

PL701

1 2

100K_0402_5%

@

HCB1608KF-

12

PC706

PR706

PL702

121T30_0603

0.1U_0402_25V6

.1VALW

+1

1 2

1

+

2

12

PC701

PC701 220U_D2_2VY

220U_D2_2VY

B+

PC711

@10U_0805_25V6K

_R15M

A A

ecurity Classification

S

2009/12/01 2011/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AN

AN

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/12/01 2011/12/31

3

Compal Secret Data

Deciphered Date

pal Electronics, Inc.

Com

Title

PWR+1.1VALWP

Size Document Number Rev

Custom

QBL50 LA-7551P

Date: Sheet

2

Date: Sheet

1

of

44 53Wednesday, April 27, 2011

of

44 53Wednesday, April 27, 2011

of

44 53Wednesday, April 27, 2011

1.0

5

+1

.5V

D D

SU

SP28,38

C C

B B

VG

A_PWR_ON25,38,42

R604

P

0_0402_5%

4.7U_0805_6.3V6K

SSM3K7002FU_SC70-3

75VS_N_002

0.

12

+

0.75VSP

15K_0402_1%

1 2

C601

P

Q602

P

12

C606

P

P @0.1U_0402_10V7K

@0.1U_0402_10V7K

R609

P

D601

P

1SS355_SOD323-2

12

2

G

1 2

REF_G2992

V

13

D

S

01

PJP6

PAD-OPEN 3x3m

+1

.5V

12

C611

C611 P

P

4.7U_0805_6.3V6K

0.1U_0402_16V7K

C613

P

+

5VALW

4

12

P

R601

1K_0402_1%

12

R602

P

P 1K_0402_1%

1K_0402_1%

12

0.1U_0402_16V7K

C604

C604 P

P

(2A,80mils ,Via NO.= 4)

.75VS

+0

12

C612

C612 P

P

1U_0603_10V6K

P

U602 APL5930KAI-TRG_SO8

6

V

CNTL

5

VI

N

9

VI

N

8

EN

7

D

PO

K

GN

1

VO

UT

VO

UT

FB

P

1

2

3

4

APL5336KAI-TRL_SOP 8P8

12

C605

P

P 10U_0805_6.3V6M

10U_0805_6.3V6M

3 4

1.82K_0402_1%

2

7.32K_0402_1%

U601

VI

GN

VR

VO

N

D

EF

UT

0.75VSP

+

R610

P

PR611

3

8

NC

7

NC

6

V

CNTL

5

NC

9

TP

12

C603

P

P 1U_0603_10V6K

1U_0603_10V6K

+3V

ALW

+3VS

12

P

C607

1U_0402_6.3V6K

+

2.5VSP

12

+1.0VSP

12

C614

C614 P

P

PC615

180P_0402_50V8J

22U_0805_6.3V6M

2

P

U603

APL5508-25DC-TRL_SOT89-3

2

1 2

IN

GN

D

1

PJP6

02

PAD-OPEN 3x3m

T

OU

1

3

12

PC608

4.7U_0805_6.3V6K

+2

.5VS

12

P

R605

@150_1206_5%

+

2.5VSP

PJP603

+1

.0VSP

A A

5

1 2

PAD-OPEN 3x3m

4

(2.5A,100mils ,Via NO.= 5)

1.0VSG

+

Security Classification

Is

sued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE U

MAY BE U

SED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

11/23 2011/12/31

2006/

C

ompal Secret Data

ciphered Date

De

2

mpal Electronics, Inc.

Co

Title

Size Doc ument Number Rev

Date: Sheet

Co

PW

R 0.75VSP/1.0VSP/2.5VSP

50 LA-7551P

QBL

1

of

45

of

45

of

45

53Wednesday, April 27, 2011

1.0

A

1 1

PR803

VL

DT_EN36,38

2 2

+5

VALW

+5

VALW

3 3

1 2

P

R807

100_0402_1%

P

C808

4.7U_0603_6.3V6M

0_0402_5%

V5FI

LT_1.2V

+1.

12

P

C804

12

@0.1U_0402_10V7K

255K_0402_1%

1 2

+1.

1 2

2VS

3.24K_0402_1%

5.36K_0402_1%

P

R805

2VS

R801

P

R802

TO

N_1.2V

FB_1.

12

E

2V

N_1.2V

2

3

4

5

6

U801

P

TON

VOUT

VDD

FB

PGOOD

B

ST_1.2V

14

1

15

NC

BOOT

UGATE

EN/DEM

PHASE

VDDP

LGATE

GND7PGND

RT8209MGQW _WQFN14_3P5X3P5

8

CS

P

R804

2.2_0402_5%

1 2

U

G_1.2V

13

LX

12

TR

11

10

LG

9

B

_1.2V

IP_1.2V

+5

_1.2V

ST1_1.2V

P

0.1U_0402_10V7K

R808

P

1 2

VALW

12

1 2

C807

15K_0402_1%

VALW

+5

P

C809

4.7U_0805_10V6K

P

R806

0_0402_5%

1 2

C

P

Q802

S TR AO4406AL 1N SO8

Q802

4

1.

2V_B+

3 5

5

Q801

P

P AON7408L_DFN8-5

AON7408L_DFN8-5

241

786

123

12

C802

C802 P

P

10U_0805_25V6K

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

P

R809

@4.7_1206_5%

NUB_1.2V S

12

C810

P

@680P_0402_50V7K

12

2200P_0402_50V7K

L801

P

PL802

HCB1608KF-121T30_0603

12

PC806

C805

C805 P

P

0.1U_0402_25V6

+1.2VS

1

+

C801

C801 P

P

2

D

B+

12

C811

C811 P

P

@680P_0402_50V7K

220U_D2_2VY_R15M

4 4

ecurity Classification

S

I

ssued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

EPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

D

D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

ompal Secret Data

Dec

iphered Date

C

Co

mpal Electronics, Inc.

tle

Ti

2011/12/312009/01/23

Ti

Size Document Number Rev

Date: Sheet

mpal Electronics, Inc.

+1.2VSP

61 LA-6321P M/B

NCL

D

0

1.

53Wednesday, April 27, 2011

of

46

of

46

of

46

5

PR

202

10_0402_5%

PR

204

10_0402_5%

12

D D

A

PU_VDDNB_RUN_FB_L8

A

PU_VDDNB_SEN8

+

CPU_CORE_NB

PC

231

0.01U_0402_16V7K

12

PC

266

@330P_0402_50V7K

232

PC

@330P_0402_50V7K

1 2

PLACE NEAR NB L-MOS

208

207

MP_NB_1

12

PC

238

1 2

APU

_PWRGD_L13

APU

232 3.83K_0402_1%

PR

PC255

COMP_CPU_1

12

207

PR

143K_0402_1%

12

241

PC

1000P_0402_50V7K

_SVD8

_SVC8

_ON36

VR

8.06K_0402_1%

251

PC

68P_0402_50V8J

CPU_CORE

+

PR

2.49K_0402_1%

12

F

B_NB_1

12

PR

210

324_0402_1%

202_CPU

PH

12

202 470K_0402_5%_TSM0B474J4702RE

PH

12

PR236

1000P_0402_50V7K

12

324_0402_1%

PR241

12

143K_0402_1%

12

PC

239

1000P_0402_50V7K

CO

PR

223 0_0402_5%

227 0_0402_5%

PR

229 0_0402_5%

233 27.4K_0402_1%

PR

12

247

PC

239

PR

B_CPU_1

F

12

PR242

2.43K_0402_1%

248

PR

10_0402_5%

PR

252

10_0402_5%

F

B_NB

MP_NB

VW

_NB

SD

12

ALERT#

12

SCLK

12

C_CPU

NT

12

PC

1000P_0402_50V7K

12

PU

1

2

3

4

5

A

6

7

8

9

10

11

12

VW

MP_CPU

CO

PC248 33P_0402_50V8JPC248 33P_0402_50V8J

1 2

252

12

0.01U_0402_16V7K

+5

48

201

EN1_NB

F

B2_NB

IS

FB

_NB

MP_NB

CO

_NB

VW

P

GOOD_NB

SVD

ROK

PW

SVC

EN

ABLE

GOOD

P

PROC_HOT

NT

C

VW

13

_CPU

B_CPU

F

SEN2

I

SEN1

M-

VSU

12

261

PC

@330P_0402_50V7K

12

264

PC

236

PC

470P_0402_50V7K

CO

12

PR

209

100K_0402_1%

PR

8.06K_0402_1%

100P_0402_50V8J

216

1 2

Rfset(Kohm)=(Period(uS))-0.29)*2.65

C C

+3

VS

12

221

PR

100K_0402_5%

PR

225

@100K_0402_5%

VGAT

E36

E

C_THERM#8,13,36

PLACE NEAR Phase1 L-MOS

B B

Rfset(Kohm)=(Period(uS))-0.29)*2.65

238

PR

100K_0402_1%

12

470P_0402_50V7K

_VDD_SEN8

APU

PU_VDD_RUN_FB_L8

A

A A

VS

44

45

47

46

N_NB

EN2_NB

RT

VSEN_NB

IS

ISL6267HRZ-T_QFN48_6X6

MP

SEN3/FB2

FB

I

CO

14

15

17

16

SEN3_FB2_CPU I

12

256

257

PC

0.22U_0402_10V6K

12

PC

@330P_0402_50V7K

4

12

233

234

PC

0.1U_0402_10V7K

PH

12

470K_0402_5%_TSM0B474J4702RE

1 2

206

27.4K_0402_1%

PR

845_0402_1%

1 2

217

217 PR

PR

1 2

NB

UMN_NB

OG2

IS

PR

NTC_

43

41

42

C_NB

ROG2 P

NT

UMP_NB

UMN_NB

IS

N

SEN2

SEN1

VSEN

I

RT

I

20

19

18

12

0.22U_0402_10V6K

263

PLACE NEAR NB choke

VSU

MG+

12

203

203 PR

PR

12

201

4.02K_0402_1%

PR

203_NB

11K_0402_1%

0.047U_0402_16V7K

204

PR

6.65K_0402_1%

1_NB

BOOT

40

OOT1_NB B

UMN IS

21

UMN_CPU IS

211

NT

C_NB_1

U

GATE_NB

39

38

1_NB

H1_NB P

UG

D

UMP IS

VD

23

22

12

249 1U_0603_10V6K

249 1U_0603_10V6K PC

PC

PR

244

976_0402_1%

PH

12

PH

10K_0402_5%_ERTJ0ER103J

12

1 2

PR

3.83K_0402_1%

PR

215

2.2_0603_5%

BOOST

12

37

1_NB LG

P

WM2_NB

B

OOT2

UG

PH

LG

CCP

V

PW

LG

PH

UG

BOOT1

P

ROG1

N VI

24

49

IN_CPUVDD_CPU V

12

250

250 PC

PC

0.22U_0603_25V7K

12

258

258 PC

PC

12

203

VSU

MG-

235

PC

0.1U_0603_50V7K

212

0.1U_0603_50V7K

1_NB1

36

35

34

2

33

2

32

2

31

30

M3

29

1

28

1

27

1

26

25

TP

235

PR

12

0_0603_5%

12

237

PR

PR 1_0603_5%

1_0603_5%

12

259

259 PC

PC

0.22U_0402_16V7K

PLACE NEAR Phase1 choke

PR

0_0603_5%

PC

BOOT

2

U

GATE2

PH

ASE2

LGAT

E2

6267_VC

PWM3

LGATE1

PH

ASE1

U

GATE1

BOOT

1

OG1_CPU

PR

+5

243

243 PR

PR

0.01U_0402_16V7K

255

240

12

CP

1 2

CP

VS

12

11K_0402_1%

12

PR

224

0_0402_5%

1 2

6.65K_0402_1%

U_B+

12

201_CPU PH

12

5

4

5

PQ206

4

LGATE_NB

VS

+5

12

PR

219

0_0603_5%

0_0402_5%

PR218

CP1

6267_VC

12

245

245 PC

PC

1U_0603_10V6K

234

PR

M+

VSU

PR

240

2.61K_0402_1%

PH

201

10K_0402_5%_ERTJ0ER103J

VSUM-

262

PC

0.1U_0603_50V7K

3

PQ205

T

PCA8065-H_PPAK56-8-5

123

PH

123

TPCA8059-H_PPAK56-8-5

PC

237

680P_0402_50V7K

GATE2

U

PH

ASE2

PR

226

2.2_0603_5%

2

BOOT

LGAT

E2

PH

PR

2.2_0603_5%

BOOT

1

LGATE1

ASE_NB

UGATE1

ASE1

247

12

4.7_1206_5%

NUB_NB S

12

253

PR

0_0603_5%

0.1U_0603_50V7K

2_1

BOOT

12

PC226

10U_0805_25V6K

PR

205

VSU

MG+

VSU

MG-

4

12

PC

244

12

4

PR254

0_0603_5%

PC

0.1U_0603_50V7K

1_1

U_B+

CP

12

225

228

PC

10U_0805_25V6K

0.01U_0402_25V7K

0.

36UH_VMPI1004AR-R36M-Z03_30A_20%

PR

213

3.65K_0805_1%

12

PR

214

1_0402_1%

12

5

PQ203

PCA8065-H_PPAK56-8-5

T

123

5

PQ204

123

PCA8059-H_PPAK56-8-5

PCA8059-H_PPAK56-8-5 T

T

5

4

12

260

5

12

4

12

229

229 PC

PC

2200P_0402_50V7K

PL203

1

2

VSUMG+_1

12

PR

4.7_1206_5%

NUB_CPU2 S

PC246

12

680P_0402_50V7K

PQ201

T

PCA8065-H_PPAK56-8-5

123

PQ202

123

PCA8059-H_PPAK56-8-5

PCA8059-H_PPAK56-8-5 T

T

2

PL204

PL204 H

H

CB2012KF-121T50_0805

1 2

PL205

CB2012KF-121T50_0805

H

1 2

4

3

MG-_1

VSU

CP

U_B+

12

223

224

PC

10U_0805_25V6K

0.

36UH_VMPI1004AR-R36M-Z03_30A_20%

PR

220

12

PR230

12

3.65K_0805_1%

PR

231

1_0402_1%

12

U_B+

CP

12

221

221 PC

PC

10U_0805_25V6K

I

SEN1

M+

VSU

M-

VSU

1

2

VSUM+_2

12

PC254

0.01U_0402_25V7K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

PR

245

10K_0402_1%

250

PR

3.65K_0805_1%

251

PR

1_0402_1%

I

SEN2

10K_0402_1%

228

VSUM+

VSU

M-

If the layout of each phase to CPU is symmetric, the two res. can be removed. They are used for phase current balance adjustment.

222

222 PC

PC

12

PR

249

4.7_1206_5%

NUB_CPU1 S

265

PC

12

680P_0402_50V7K

+

12

242

242 PC

PC

0.01U_0402_25V7K

PL202

VSU

M-_2

12

253

253 PC

PC

2200P_0402_50V7K

1

12

2

M+_1

VSU

12

1

+

230

230 PC

PC

2

@100U_25V_M

CPU_CORE_NB

12

243

243 PC

PC

2200P_0402_50V7K

4

PR

222

3

1 2

10K_0402_1%

PL201

4

3

M-_1

VSU

1

+

227

227 PC

PC

2

I

SEN1

PR

246

1 2

10K_0402_1%

1

B+

12

267

PC268

PC

@10U_0805_25V6K

S ELE CAP 68U 25V M 6.3X5.8 ESR0.36 FK

+C

PU_CORE

I

SEN2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/11/11 2011/12/31

Compal Secret Data

eciphered Date

D

2

C

tle

Ti

Size Docum ent Number Rev

Date: Sheet

ompal Electronics, Inc.

R_+CPU_CORE/+CPU_CORE_NB

PW

Q

BL50 LA-7551P

Wednesday, April 27, 2011

1

47

53

of

0

1.

A

PL902

HCB2012KF-

121T50_0805

1 2

12

B+

PR907

2K_0402_1%

73.

PC917

0.1U_0402_16V7K

@

@ 10U_0805_25V6K

10U_0805_25V6K

PC923

12

TRI

P_VGA

EN_VGA

FB_VGA

RF_VGA

PR911

PR911 470K_0402_1%

470K_0402_1%

1 2

PU901

1

P

GOOD

2

TR

3

EN

4

VFB

5

RF

RT8237CZQW

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1 1

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+3

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IN

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10

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9

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8

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6

11

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@10U_0805_25V6K

PC925

12

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@

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@

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@

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4

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4

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@

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1 2

5

PQ906

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TPCA8065-H_PPAK56-8-5

5

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5

4

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2

G

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@

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0.

1 2

12

PR910

7_1206_5%

4.

0.

SNUB_VGA

TPCA8059-H_PPAK56-8-5

123

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PC922

0.1U_0402_16V7K

PR917

5.

1K_0402_1%

1 2

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680P_0402_50V7K

PR914

PL901

PC918

1U_0402_10V7K

+3VSG

10K_0402_1%

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@

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D

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+

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GCORE_SEN

21

XL

X

H

L

1.0V

0.9V

HH

4 4

S

ecurity Classification

2007/

05/29 2011/12/31

Is

sued Date

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL

D TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

05/29 2011/12/31

Compal Secret Data

Deciphered Date

C

Compal Electronics,

tle

Ti

Size Document Number Rev

Date: Sheet

Compal Electronics,

V

GA_CORE

50 LA-7551P

QBL

D

Inc.

48 53Wednesday, April 27, 2011

of

0

1.

Version change list (P.I.R. List)

5

4

3

2

1

Power section Page 1 of 1

Item Reason for change PG# Modify List

Date Phase

1

2

D D

3

4

5

6

7

C C

B B

A A

Security Classification

ssued Date

I

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTM

DEPARTM MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal S ecret Data

2008/09/15 2011/12/31

Deciphered Date

2

ompal Electronics, Inc.

C

tle

Ti

C

hanged-List History

Size Docume nt Numbe r Rev

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QBL50 LA-7551P

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49 53Wednesday, April 27, 2011

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I

ssued Date

T

HIS SHEET OF ENGINEER ING DRAWI NG IS THE PROPR IETARY PROPER TY OF COMPAL ELECT RONICS, I NC. AND C ONTAINS CON FIDENTI AL

HIS SHEET OF ENGINEER ING DRAWI NG IS THE PROPR IETARY PROPER TY OF COMPAL ELECT RONICS, I NC. AND C ONTAINS CON FIDENTI AL A

A

ND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

pal Secret Data

Com

2010/06/30 2011/12/31

Deciphered Date

2

7%PV

Ti

tle

P

ower Sequence

Size Document Number Rev

BL50 LA-7551P

Q

W

ednesday, April 27, 2011

Date: Sheet

1

50 53

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1.0

5

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3

2

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D D



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





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C C







For PBL60 MEMO

For switch quality of ME.

For LED brightness.

For DFB. 0.12 PG#11 JDIMM1 footprint change to FOX_AS0A626-J8SG-7H_204P-T 03/17 ER

For USB3.0 & AI charge. 0.12 PG#34 USBP0 connect to JUSB1 and USBP10 connect to JUSB2. 03/17 ER

For Back light function. 0.12 PG#36 U31.15 connect to ENBKL from APU. 03/17 ER

For HDMI HPD issue. 0.12 PG#10 Q34 change to 2N7002(ESD)

For DP0_HPD & DP1_HPD from AMD recommend. 0.12 PG#10 Swap Q13.1 & Q13.3, R618 unmount.

For Travis Vendor request Del DP0_TXN0_C & DP0_TXP0_C0.12 PG#26 03/22 ER

For LED1 0.12 LED1 connect to +3VALW 03/22 ERPG#32





For Sourcer recommend







B B

















A A





5

For Sourcer recommend SB000006A00 change to SB000006A100.2

For Thermal 0.2 Del H4 03/24 ERPG#37

For +5VS rising time 0.2 PG#38 R1103 change to 47K 03/24 ER

For Crystal EA 0.2 C1634 change to 12P & C1633 change to 15P 03/24 ER

For Crystal EA

For EMI request 0.2 PG#36 R1033 change to SM01000DI00

For EMI request 0.2 PG#28 L38,L39,L40,L41 change to SM070001S00 03/24 ER

For EMI request 03/24D1,D2,D3,D6 change to installPG#270.2 ER

For Crystal EA 0.2 PG#13 C1205,C1206 change to 10P 03/24 ER

For AI charge 0.2 PG#36

For AMD spec 0.2 PG#27 R1642 & R1646 change to 4.6K ohm 03/29 ER

4

5HY 3* 0RGLI\/LVW 'DWH 3KDVH)L[HG,VVXH,WHP

03/15

Add U2 & U56For AI charge function

PG#34

0.11

PG#32

0.11

Change SW5,SW6 to 100g switch for ME.0.11 PG#37 03/15 ER

0.11 PG#32 03/15 ER

Change R1584 to 200 ohm. Change R1586,R1588,R1591,R1592,R1593 to 100 ohm

Add R469 to +1.5VS.

Swap Q16.1 & Q16.3, R627 unmount.

R1021,R1022 change to install.0.2 PG#36For EC SMBUS 03/24 ER

SE100105Z80 change to SE000000K80 03/24 ER0.2

0.2For Sourcer recommend

SE103225Z80 change to SE000008880

PG#29

0.2

C1200 & C1201 change to 12P

PG#13

C353 change to 15P & C354 change to 12P

PG#19

R1055 change to 33 ohm

U2 reserve CEN# to EC 03/25 ER

PG#34

curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/

06/30 2011/12/31

ompal Secret Data

C

Deciphered Date

2

03/15

03/15Change LED1 to Green color.

03/19

03/19ERER

03/24 ER

Ti

Size Document Number Rev

Custom

Date: Sheet

ERPG#260.11For AMD reuqest Translator change to ANX3110

ER

Co

mpal Electronics, Inc.

tle

mpal Electronics, Inc.

PIR

HW-

BL50 LA-7551P

Q

1

51 53Wednesday, April 27, 2011

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1.0

5

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



D D













For share ROM reuqest

For EMI reuqest 0.2 PG#34 D5 change to SC300001Y00 (YSCLAMP0524P) 03/29 ER

For Crystal vendor recommend 0.21 PG#13 Y4 change to SJ100007N00 (32.768K 7PF) 04/07 PR

For EMI recommend PG#29 TS1 change to SP050006F00 (IH-160) 04/07

For discharge EA PG#38 R1127 change from 470 ohm to 33 ohm 04/07

For leakage current PG#27 R1644,R1645,Q101 change to install

For EMI recommend PG#29 C1636 change from 1000P to 120P 04/08





C C











Reserve PX_EN signal 0.21 PG#36 04/18 PRReserve signal PX_EN to EC pin 74

Swap JDIMM1 & JDIMM2 location 0.21

Do not use for MP 0.21 PG#35 04/18 PRDel SW3 SW4

Change Boarrd ID to PR10 0.21 PG#37 Change R1036 to 18k 04/18 PR

For DFB request del co-lay schematiic 0.21 PG#34 Del R672~R675, R664~R667 04/18 PR

For EMI request 0.22 PG#29 ADD D7 04/19 PR







For Customer change FCH P/N 1.0

For ESD request 1.0 PG#32

5HY 3* 0RGLI\/LVW 'DWH 3KDVH)L[HG,VVXH,WHP

0.2 PG#15

0.21

0.21For thermal recommend PG#19 Add R78, R79, R80, R82

U28,R626,R934,R935,R35 change to Un-install

PG#16

R921 change un-install & U910 change to install

R4,R31 change to un-install

PG#11

Follow ME BOM 04/18 PR

PG#12

PG#13For EMI request 1.0 unstuff C1193 04/25 PR

PG#13

location U25, for M2 change to SA000042C80,

~17

M3 change to SA000043ID0

R628,R629,R678,R679,R680,R681 change from 0ohm to 33ohm & Add 1uF for C560,C568,C569,C570,C573,C571

03/29

03/29 ER

04/07

04/18 PR

04/25 PR

04/27 PR

ERPG#300.2For EMI reuqest R1555,R1556,R1557,R1558 change to 0.1uf

PR



B B

















A A

ecurity Classification

S

sued Date

Is

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AN

AN DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

06/30 2011/12/31

2010/

C

ompal Secret Data

Deciphered Date

mpal Electronics, Inc.

Co

Ti

Size Document Num ber Rev

Custom

Date: Sh eet

2

Date: Sh eet

Co

tle

HW-PIR

50 LA-7551P

QBL

1

1.0

52 53Wednesday, April 27, 2011

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03/15 04/25

03/15

03/17

03/19

03/22

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PRAs picture1.0For MP cost down



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







A A





curity Classification

Se

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/

06/30 2011/12/31

ompal Secret Data

C

Deciphered Date

Co

mpal Electronics, Inc.

Ti

tle

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

mpal Electronics, Inc.

PIR

HW-

BL50 LA-7551P

Q

1

53 53Wednesday, April 27, 2011

of

1.0

Compal LA-7551P QBL50, K43T, K43TA, K43TK, K43TY Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual