COMPAL LA-7531P Schematics

A

1 1

B

C

D

E

2 2

Compal Confidential

QAZ00 (Shuriken 13.3) M/B Schematics Document

Intel Sandy Bridge ULV Processor with DDRIII + Cougar Point PCH SFF

3 3

LA-7531P

Date : 2011/04/10 Version 0.1 modify

4 4

Security Classification

2010/08/03

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2010/08/03

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-7531P

0.1

of

145Sunday, April 10, 2011

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145Sunday, April 10, 2011

A

B

C

D

E

Memory BUS(DDRIII)

Compal Confidential

1 1

Model Name :QAZ00 Shuriken 13.3

Sandy & Ivy Bridge

Intel

1.5V DDRIII 1066/1333/1600 for CR

1.5V DDRIII 1066/1333 for HR

Channel A

SODIMM SP07000NN00

File Name : LA-7531P

SA000042410

eDP (Reserved)

Page 11

ULV Processor

2011/04/10

FCBGA 1023

Page 4~10

DMI x4FDI x8

100MHz

1GB/s x4

USB 3.0 x4

HDMI Conn.

Page 20

LVDS Conn.

Page 23

100MHz

2.7GT/s

LVDS(UMA)

Intel

HDMI(UMA)

2 2

Card Reader

LAN(Gbe) RTL8111E-VL

RTS5209

Page 21

Page 25

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

X1X1

X1 X1

MINI Card x1

WLAN

Page 22

JMINI3

MINI Card x1

WWAN (3G) mSATA

Page22

X1

SATA x 6 (GEN1

1.5GT/S ,GEN2 3GT/S)

mSATA(MINI Card) SATA Conn.

Page 24

JMINI1JMINI2

X1X1

100MHz

USB 2.0 Bus

CP & PP -M

SA000043Z00

PCH SFF

1017 pin BGA

Page 12~19

LPC BUS

33MHz

RJ45

3 3

Page 21

PS2

ENE KB930 /9012

Page 27

USB 2.0 x14

HD Audio

SPI

BIOS SPI ROM x1, 4MB,U48

USB 2.0 or

3.0 X1

Power USB 1W

X1

3.3V 24MHz

Page 12

X1

3.3V 48MHz

HDA Codec

ALC269Q

Page 29

Mic1 (Analog)

Page 29

CMOS Camera

Page 23

X1

USB 2.0 X1

AUDIO HP & MIC

Power Button

Page 26

LS-7531P

Power Button

Page 28

SMBus SPI

Touch Pad

EC ROM

-SPI

Page 27

HID Sensor

Int.KBD

Page 28

LEDs

4 4

A

B

LS-7532P

Page 28

Security Classification

2009/08/01 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/01 2010/05/28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

LA-7531P

E

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245Sunday, April 10, 2011

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245Sunday, April 10, 2011

of

245Sunday, April 10, 2011

0.1

A

B

C

D

E

QAZ00 (LA-7531P Ver:0.1)

Voltage Rails

S1

Power Plane Description

VIN

BATT+

B+

1 1

+CPU_CORE

+VGFX_CORE Core voltage for UMA graphic

+0.75VS

+1.05VS_VCCP

+VCCP

+1.5V

+1.5VS

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

+0.75VP to +0.75VS switched power rail for DDR terminator

+V1.05SP to +1.05VS_VCCP switched power rail for CPU

+VCCP (1.05V ) power for PCH

+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)

+1.5VS switched power rail

S3 S5

N/A N/A N/A

N/AN/AN/A

ON

ON ON

ON

OFF

OFF OFF

OFF

OFF OFF

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

OFF

ON ON

ON

OFF

LOW

OFF

+1.8VS

+3VALW

+3VALW_EC

+LAN_IO

+3V_PCH

+3VS

+5VALW

+5V_PCH

2 2

3 3

+5VS

+VSB

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMBCLK PCH_SMBDATA PCH

PCH_SMLCLK PCH_SMLDATA

(+5VALW ) to 1.8V switched power rail to PCH & GPU

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +LAN_IO power rail for LAN

+3VALW to +3V_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5V_PCH power rail for PCH (Short resister)

+5VALW to +5VS switched power rail OFFONOFF

B+ to +VSB always on power rail for sequence control

RTC power

2011/04/07 Modify

SOURCE

KB930

PCH

BATT

V X

MIINI1

X

XX

MINI2

MINI3

SODIMM

XX

VV V

X

V

XX

X

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

None None

10/100/1G LAN

CARD READER

OFF

ON

ON ON ON*

ON ON

ON

ON ON

ON

OFF

ON ON*

ON*

OFF

ON ON*

ON*

ON ON*

ONON

EC_SMB_CK2

PCH_SMBDATA

PCH_SMBCLK

PCH_SMBDATA

XX

O

V

VO

X

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

X

None

EC SM Bus1 address

Device

Smart Battery

Address

0001 011X b

PCH SM Bus address

Device Address

DDR DIMM0

Mini Card1

Mini Card2

Mini Card3

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

1010 0000b

DESTINATION

PCH_LPBACK

PCI_LPC

None

EC SM Bus2 address

Device

PCH (Reserve)

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

Address

1010 0110b

DESTINATION

m-SATA,JMINI1

m-SATA,JMINI2

None

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

2011/04/09 Check

2 External USB Port

0 1

USB/B (Right Side)

2 3

Camera

4

Mini Card(WLAN)

5

WWAN (3G)

6 7

mSATA

8 9

USB/B (Right Side)

10 11 12 13

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

4 4

CLKOUT_PCIE5

MINI CARD WLAN

None

CLKOUTFLEX3

Symbol Note :

: means Digital Ground

None

UMA V XX

X

HDMI@@Option EMI@

X

USB 3.0 Port

1 2 3

2 External USB Port

USB/B (Right Side)

4

NoneCLKOUT_PCIE6

: means Analog Ground

CLKOUT_PCIE7 None

Security Classification

CLKOUT_PEG_B

A

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/08/01 2010/05/28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-7531P

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1

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

+V1.05S_VCCP

D D

24.9_0402_1%

UCPU1A

PEG_ICOMPI

DMI_CRX_PTX_N014 DMI_CRX_PTX_N114 DMI_CRX_PTX_N214 DMI_CRX_PTX_N314

DMI_CRX_PTX_P014 DMI_CRX_PTX_P114 DMI_CRX_PTX_P214 DMI_CRX_PTX_P314

DMI_CTX_PRX_N014 DMI_CTX_PRX_N114 DMI_CTX_PRX_N214 DMI_CTX_PRX_N314

DMI_CTX_PRX_P014 DMI_CTX_PRX_P114 DMI_CTX_PRX_P214 DMI_CTX_PRX_P314

C C

+V1.05S_VCCP

12

RC2

24.9_0402_1%

eDP_COMPIO and ICOMPO signals should be shorted near balls

B B

and routed with typical impedance <25 mohms

FDI_CTX_PRX_N014 FDI_CTX_PRX_N114 FDI_CTX_PRX_N214 FDI_CTX_PRX_N314 FDI_CTX_PRX_N414 FDI_CTX_PRX_N514 FDI_CTX_PRX_N614 FDI_CTX_PRX_N714

FDI_CTX_PRX_P014 FDI_CTX_PRX_P114 FDI_CTX_PRX_P214 FDI_CTX_PRX_P314 FDI_CTX_PRX_P414 FDI_CTX_PRX_P514 FDI_CTX_PRX_P614 FDI_CTX_PRX_P714

FDI_FSYNC014 FDI_FSYNC114

FDI_INT14

FDI_LSYNC014 FDI_LSYNC114

EDP_HPD#23

EDP_AUXN23 EDP_AUXP23

EDP_TXN023 EDP_TXN123

PAD @

T1

PAD @

T2

EDP_TXP023 EDP_TXP123

PAD @

T3

PAD @

T4

EDP_COMP

EDP_TXN2 EDP_TXN3

EDP_TXP2 EDP_TXP3

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

SANDY-BRIDGE_BGA1023~D

DMI Intel(R) FDI DP

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS -- GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_COMP

RC1

12

impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

A A

Security Classification

2010/04/26 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2010/04/26 2010/05/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-7531P

1

of

445Sunday, April 10, 2011

of

445Sunday, April 10, 2011

of

445Sunday, April 10, 2011

0.1

5

4

3

2

1

+3VS

D D

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

SM_DRAMPWROK

D44

RESET#

PLT_RST#

PLT_RST#15,21,25,27

This pin is for compability with future platforms. A pull up resistor to VCCIO is required if connected to the DF_TVS strap on the PCH.

H_SNB_IVB#15

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present

+V1.05S_VCCP

C C

B B

RC8 62_0402_5%RC8 62_0402_5%

RC11 10K_0402_5%RC11 10K_0402_5%

Processor Pullups

12

H_PROCHOT#

H_CPUPWRGD_R

H_PECI16,27 H_DRAMRST# 6

H_PROCHOT#27

H_THRMTRIP#16

H_PM_SYNC14

H_CPUPWRGD16

1 2

RC9 0_0402_5%RC9 0_0402_5%

RC10 56_0402_5%RC10 56_0402_5%

RC12 0_0402_5%RC12 0_0402_5%

RC13 0_0402_5%RC13 0_0402_5%

1 2

RC18 130_0402_5%RC18 130_0402_5%

1 2

RC7 10K_0402_5%@RC7 10K_0402_5%@

1 2

RC16

0_0402_5%

1 2

T5PAD@T5PAD

@

H_PECI_ISO

H_PROCHOT#_R

H_THEMTRIP#_R

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

BE45

5

1

NC

2

A

3

Buffered reset to CPU

1

CC1

0.1U_0402_16V4Z

2

UC1

P

G

BUFO_CPU_RST# BUF_CPU_RST#

4

Y

SN74LVC1G07DCKR_SC70-5

MISC THERMAL PWR MANAGEMENT

+V1.05S_VCCP

12

RC3

RC3 75_0402_5%

75_0402_5%

43_0402_1%

1 2

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

RC4

BCLK#

BCLK_ITP

BCLK_ITP#

PRDY# PREQ#

TRST#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

BCLK

TCK TMS

TDI

TDO

DBR#

12

@

RC6

RC6 0_0402_5%

0_0402_5%

J3 H2

AG3 AG1

N59 N58

AT30

BF44 BE43 BG43

N53 N55

L56 L55 J58

M60 L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#_R

XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R XDP_BPM#7_R

CLK_CPU_DMI 13 CLK_CPU_DMI# 13

CLK_CPU_DPLL 13 CLK_CPU_DPLL# 13

CLK_RES_ITP 13 CLK_RES_ITP# 13

RC17 0_0402_5%RC17 0_0402_5%

1 2

XDP_DBRESET#

RC19 0_0402_5%@RC19 0_0402_5%@

1 2

RC20 0_0402_5%@RC20 0_0402_5%@

1 2

RC21 0_0402_5%@RC21 0_0402_5%@

1 2

RC22 0_0402_5%@RC22 0_0402_5%@

1 2

RC5 1K_0402_5%RC5 1K_0402_5%

circuit check 10k

XDP_DBRESET# 14

12

CFG12 7 CFG13 7 CFG14 7 CFG15 7

+3VS

SANDY-BRIDGE_BGA1023~D

Follow DG 0.71

CC2

0.1U_0402_16V4Z

SYS_PWROK14

PM_DRAM_PWRGD14

+3VS

200_0402_5%

A A

5

CC2

RC27

0_0402_5%

1 2

RC28

1 2

+3VALW

1

2

Part Number = SA00003Y000

UC2

UC2 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

5

1

P

B

2

O

A

G

3

SUSP31,40

PM_SYS_PWRGD_BUF

4

SUSP

+1.5V_CPU_VDDQ

12

RC25

RC25 200_0402_5%

200_0402_5%

12

@

RC29

RC29 39_0402_5%

39_0402_5%

13

D

@

QC1

2

G

QC1 2N7002_SOT23

2N7002_SOT23

S

4

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

RC23 140_0402_1%RC23 140_0402_1%

RC24 25.5_0402_1%

SD00000X700

RC26 200_0402_1%RC26 200_0402_1%

12

PU/PD for JTAG signals

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

RC30 51_0402_5%RC30 51_0402_5%

RC31 51_0402_5%RC31 51_0402_5%

RC32 51_0402_5%RC32 51_0402_5%

RC33 51_0402_5%RC33 51_0402_5%

RC34 51_0402_5%RC34 51_0402_5%

12

+V1.05S_VCCP

Security Classification

2010/4/26 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/4/26 2010/05/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet

LA-7531P

of

545Sunday, April 10, 2011

of

545Sunday, April 10, 2011

of

1

545Sunday, April 10, 2011

0.1

5

UCPU1C

AG6

AJ6

AP11

AL6

AJ10

AJ8 AL8 AL7

AR11

AP6 AU6 AV9 AR6 AP8

AT13

AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45

AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54

AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36 BA28

BE39 BD39

AT41

UCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

DDR_A_D[0..63]11

D D

C C

DDR_A_BS011

B B

DDR_A_BS111 DDR_A_BS211

DDR_A_CAS#11 DDR_A_RAS#11 DDR_A_WE#11

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

4

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 11 M_CLK_DDR#0 11 DDR_CKE0_DIMMA 11

M_CLK_DDR1 11 M_CLK_DDR#1 11 DDR_CKE1_DIMMA 11

DDR_CS0_DIMMA# 11

DDR_CS1_DIMMA# 11

M_ODT0 11 M_ODT1 11

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

3

AL4

AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13 BF12

BF8

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59

AM60

AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

UCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

1

SANDY-BRIDGE_BGA1023~D

+1.5V

RC35

@RC35

@

0_0402_5%

1 2

D

S

D

H_DRAMRST#5

RC38

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH7,13

5

RC39

0_0402_5%

1 2

RC38

DRAMRST_CNTRL

S

G

1 2

DDR3_DRAMRST#_RH_DRAMRST#

13

QC2

QC2 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

2

1

CC3

0.047U_0402_16V4Z

2

1K_0402_5%

RC36

12

1 2

RC37

RC37 1K_0402_5%

1K_0402_5%

4

DDR3_DRAMRST# 11

Security Classification

2010/04/26 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/04/26 2010/05/28

Compal Secret Data

Deciphered Date

SANDY-BRIDGE_BGA1023~D

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-7531P

1

645Sunday, April 10, 2011

0.1

5

4

3

2

1

CFG Straps for Processor

QC7

@

SB000002X00

13

D

BSS138W-7-F_SOT323-3

2

G

D D

+V_DDR_REFA

1 2

RC15

G

S

0_0402_5%~D@

RC14

1K_0402_1%

@

12

DRAMRST_CNTRL_PCH 6,13

+V_DDR_REFA_R

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

For Chief River only

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

UCPU1E

T9T9 T6T6 T10T10 T11T11

C C

+CPU_CORE

+VGFX_CORE

RC46

1K_0402_1%

B B

1K_0402_1%

@

RC44 49.9_0402_1%RC44 49.9_0402_1%

RC45 49.9_0402_1%RC45 49.9_0402_1%

CPU_RSVD6 CPU_RSVD7

12

RC47

RC47 1K_0402_1%

1K_0402_1%

@

RC42 49.9_0402_1%RC42 49.9_0402_1%

RC43 49.9_0402_1%RC43 49.9_0402_1%

1 2

12

T12T12 T13T13 T7T7 T8T8 T14T14 T15T15

T16T16

CFG125 CFG135 CFG145 CFG155

T17T17

T18T18

1 2

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

VCC_VAL_SENSE

12

VSSAXG_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RESERVED

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

+V_DDR_REFA_R

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

12

RC40

RC40 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

@RC48

@

1K_0402_1%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

RC48

12

RC41

RC41 1K_0402_1%

1K_0402_1%

@

12

@RC49

@

1K_0402_1%

12

RC50

@RC50

@

1K_0402_1%

RC49

SANDY-BRIDGE_BGA1023~D

PEG DEFER TRAINING

1: (Default) PEG Train immediately following

CFG7

A A

Security Classification

2010/04/26 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2010/04/26 2010/05/28

Compal Secret Data

Deciphered Date

*

xxRESETB de assertion

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-7531P

1

745Sunday, April 10, 2011

0.1

of

5

D D

+CPU_CORE

,ŝŐŚͲ&ƌĞƋƵĞŶĐǇĞĐŽƵƉůŝŶŐ

C C

B B

CC55

2.2U_0402_6.3V6M

CC55

2.2U_0402_6.3V6M

1

2

CC61

2.2U_0402_6.3V6M

CC61

2.2U_0402_6.3V6M

1

2

CC65

2.2U_0402_6.3V6M

CC65

2.2U_0402_6.3V6M

1

2

CC69

2.2U_0402_6.3V6M

CC69

2.2U_0402_6.3V6M

1

2

CC56

2.2U_0402_6.3V6M

CC56

2.2U_0402_6.3V6M

1

2

CC62

2.2U_0402_6.3V6M

CC62

2.2U_0402_6.3V6M

1

2

CC66

2.2U_0402_6.3V6M

CC66

2.2U_0402_6.3V6M

1

2

CC70

2.2U_0402_6.3V6M

CC70

2.2U_0402_6.3V6M

1

2

CC57

2.2U_0402_6.3V6M

CC57

2.2U_0402_6.3V6M

1

2

CC63

2.2U_0402_6.3V6M

CC63

2.2U_0402_6.3V6M

1

2

CC67

2.2U_0402_6.3V6M

CC67

2.2U_0402_6.3V6M

1

2

CC71

2.2U_0402_6.3V6M

CC71

2.2U_0402_6.3V6M

1

2

4

SV type CPU

+CPU_CORE

CC58

2.2U_0402_6.3V6M

CC58

2.2U_0402_6.3V6M

1

2

CC64

2.2U_0402_6.3V6M

CC64

2.2U_0402_6.3V6M

1

2

CC68

2.2U_0402_6.3V6M

CC68

2.2U_0402_6.3V6M

1

2

CC72

2.2U_0402_6.3V6M

CC72

2.2U_0402_6.3V6M

1

2

53A

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42

G42

H25 H26 H28 H29 H32 H34 H35 H37 H38 H40

J25 J26 J28 J29 J32 J34 J35 J37 J38 J40

J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

UCPU1F

VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76]

3

CORE SUPPLY

POWER

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

18A

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

+1.05VS_VCCPQ

AM25 AN22

2

10U_0603_6.3V6M

CC4

CC26

CC32

CC45

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

CC16

CC27

CC33

CC46

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

CC17

CC28

CC34

CC47

10U_0603_6.3V6M

1

CC18

2

1U_0402_6.3V6K

1

CC29

2

1U_0402_6.3V6K

1

CC35

2

1U_0402_6.3V6K

1

CC48

2

Cap quantity follow 43890_HR_CHKLST_Rev07

+V1.05S_VCCP

RC51

1 2

0_0805_5%

VCCP_PWRCTRL_R

choose low or high

+V1.05S_VCCP +V1.05S_VCCP

RC54

1 2

0_0805_5%

1 2

CC73 1U_0402_6.3V6KCC73 1U_0402_6.3V6K

@

10K_0402_5%

1 2

RC53

12

RC52

RC52 75_0402_5%

75_0402_5%

12

RC55

RC55 130_0402_5%

130_0402_5%

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

Voltage selection for VCCIO: For Huron River platforms, this pin must be pulled high on the motherboard.

10U_0603_6.3V6M

1

CC5

2

1U_0402_6.3V6K

1

CC30

2

1U_0402_6.3V6K

1

CC36

2

1U_0402_6.3V6K

1

CC49

2

+V1.05S_VCCP

12

1

CC6

2

CC31

1

CC37

2

1

CC50

2

RC56

RC56 75_0402_5%

75_0402_5%

10U_0603_6.3V6M

1U_0402_6.3V6K

CC19

CC38

CC51

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

CC7

CC39

CC52

10U_0603_6.3V6M

1

CC8

2

1U_0402_6.3V6K

1

CC40

2

1U_0402_6.3V6K

1

CC53

2

+V1.05S_VCCP

10U_0603_6.3V6M

1

CC9

2

1U_0402_6.3V6K

1

CC41

2

1U_0402_6.3V6K

1

CC54

2

1

H_CPU_SVIDALRT#

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

A A

SANDY-BRIDGE_BGA1023~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

VSS_SENSE_VCCIO

3

A44

H_CPU_SVIDCLK

B43

H_CPU_SVIDDAT

C44

VCCSENSE_R

F43

VSSSENSE_R

G43

VCCIO_SENSE_R

AN16

VSS_SENSE_VCCIO

AN17

2010/04/26 2010/05/28

RC61 0_0402_5%RC61 0_0402_5%

1 2

RC62 0_0402_5%RC62 0_0402_5%

1 2

RC63

1 2

10_0402_1%

RC65 0_0402_5%RC65 0_0402_5%

12

RC66

RC66 10_0402_1%

10_0402_1%

Compal Secret Data

Deciphered Date

10_0402_1%

1 2

RC57 43_0402_1%RC57 43_0402_1%

1 2

RC58 0_0402_5%RC58 0_0402_5%

1 2

RC59 0_0402_5%RC59 0_0402_5%

+V1.05S_VCCP

VCCIO_SENSE 38,39 VSS_SENSE_VCCIO 38,39

2

VR_SVID_ALRT# 43 VR_SVID_CLK 43 VR_SVID_DAT 43

+CPU_CORE

1 2

RC60 100_0402_1%RC60 100_0402_1%

VCCSENSE 43 VSSSENSE 43

12

RC64

Place the PU

100_0402_1%

resistors close to VR

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-7531P

Place the PU resistors close to CPU

of

845Sunday, April 10, 2011

of

845Sunday, April 10, 2011

of

1

845Sunday, April 10, 2011

0.1

5

4

3

2

1

+1.5V_CPU_VDDQ +1.5V

CC74 0.1U_0402_10V7KCC74 0.1U_0402_10V7K

CC75 0.1U_0402_10V7KCC75 0.1U_0402_10V7K

12

Can connect to GND if motherboard onlyɄɄɄɄ supports external graphics and if GFX VR is not stuffed in a common motherboard design,

VAXG can be left floating in a commonɄɄɄɄ motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

10U_0603_6.3V6M

CC99

+1.5V_CPU_VDDQ

12

RC68

RC68 100_0402_1%

100_0402_1%

12

RC69

RC69 100_0402_1%

100_0402_1%

1

+

CC100

330U_D2_2V_Y

2

RC71

RC71 470_0603_5%

470_0603_5%

1 2

13

D

2

G

S

RUN_ON_CPU1.5VS3#

QC6

QC6 2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

UCPU1G

D D

+VGFX_CORE

Vaxg

1U_0402_6.3V6K

CC107

CC108

CC109

1

C C

1

2

1

2

CC109

1

2

CC110

1

2

CC111

1U_0402_6.3V6K

CC112

1

2

1

2

1U_0402_6.3V6K

CC113

1

2

CC114

1U_0402_6.3V6K

CC115

CC116

1

2

CC116

1

2

1U_0402_6.3V6K

CC117

1

2

26A

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58

V59 W50 W51 W52 W53 W55 W56 W61

Y48

Y61

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

POWER

GRAPHICS

POWER

+V_SM_VREF_CNT

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22]

DDR3 - 1.5V RAILS

VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

AY43

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

CPU1.5V_S3_GATE27

SUSP#27,31,37,38,39

1U_0402_6.3V6K

CC85

CC86

1

2

RC74

0_0402_5%

1 2

RC75

@RC75

@

0_0402_5%

1 2

+1.5V_CPU_VDDQ

12

RC76

RC76 0_0603_5%

0_0603_5%

+V_SM_VREF should have 20 mil trace width

1

CC79

1U_0402_6.3V6K

CC90

CC79

2

RUN_ON_CPU1.5VS3

1U_0402_6.3V6K

CC91

CC92

1

2

+VSB

5

1

2

+1.5V +1.5V_CPU_VDDQ

12

RC70

RC70 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

3

QC5B

QC5B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

330K_0402_5%

0.1U_0402_16V4Z

1U_0402_6.3V6K

CC87

1

2

+3VALW

2

1U_0402_6.3V6K

CC89

CC88

1

2

12

RC72

RC72 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3#

61

QC5A

QC5A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

RC67

0_0402_5%

12

2

3

QC3

@QC3

@

AP2302GN-HF_SOT23-3

1

+V_SM_VREF

+1.5V_CPU_VDDQ

5A

10U_0603_6.3V6M

1

CC93

CC94

2

+1.5V_CPU_VDDQ Source

1

2

RC73

10U_0603_6.3V6M

1

CC95

2

QC4

AO4728L_SO8

8 7 6 5

12

CC96

10U_0603_6.3V6M

1

CC97

2

4

1

CC118

0.1U_0402_16V4Z

2

10U_0603_6.3V6M

1

CC98

2

1 2 3

Follow DG 0.71 page 6

3

AM28 AN26

BC43 BA43

VCCSA_SENSE

U10

D48 D49

1U_0402_6.3V6K

1 2

CC119

1 2

RC78 0_0402_5%@RC78 0_0402_5%@

0_0402_5%

1 2 1 2

0_0402_5%

VCCSA_VID0

RC79

VCCSA_VID1

RC80

2010/04/26 2010/05/28

VCCSA_VID0 41 VCCSA_VID1 41

Compal Secret Data

Deciphered Date

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.80 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

LA-7531P

1

0.1

of

945Sunday, April 10, 2011

of

945Sunday, April 10, 2011

of

945Sunday, April 10, 2011

SENSE

LINES

SENSE

B B

+1.8VS

1 2

A A

5

RC77

0_0805_5%

+VCCSA

VCC_AXG_SENSE43

VSS_AXG_SENSE43

+1.8VS_VCCPLL

CC121

1U_0402_6.3V6K

CC121

1

2

CC120

1U_0402_6.3V6K

CC129

1

2

1

+

2

CC130

330U_D2_2VM_R6M

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CC131

1U_0402_6.3V6K

1

2

+VCCSA

1

2

1U_0402_6.3V6K

CC132

CC122

1U_0402_6.3V6K

CC122

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CC133

1

2

4

6A

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

SANDY-BRIDGE_BGA1023~D

LINES

1.8V RAIL

SA RAIL

SENSE LINES

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

UCPU1H

3

2

1

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

D D

C C

B B

A53

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AJ7

AK1

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS[10] VSS[11]

A9

VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G48

VSS[221]

G51

VSS[222]

G6

VSS[223]

G61

VSS[224]

H10

VSS[225]

H14

VSS[226]

H17

VSS[227]

H21

VSS[228]

H4

VSS[229]

H53

VSS[230]

H58

VSS[231]

J1

VSS[232]

J49

VSS[233]

J55

VSS[234]

K11

VSS[235]

K21

VSS[236]

K51

VSS[237]

K8

VSS[238]

L16

VSS[239]

L20

VSS[240]

L22

VSS[241]

L26

VSS[242]

L30

VSS[243]

L34

VSS[244]

L38

VSS[245]

L43

VSS[246]

L48

VSS[247]

L61

VSS[248]

M11

VSS[249]

M15

VSS[250]

SANDY-BRIDGE_BGA1023~D

VSS

VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_NCTF_10

NCTF

VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

SANDY-BRIDGE_BGA1023~D

A A

Security Classification

2010/04/26 2010/05/28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2010/04/26 2010/05/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

LA-7531P

1

0.1

of

10 45Wednesday, April 06, 2011

of

10 45Wednesday, April 06, 2011

of

10 45Wednesday, April 06, 2011

5

4

3

2

1

DDR3 SO-DIMM A

+V_DDR_REFA

+1.5V +1.5V

3.56A@+1.5V

JDDRL

D D

DDR_A_D[0..63]6

DDR_A_DQS[0..7]6

DDR_A_DQS#[0..7]6

DDR_A_MA[0..15]6

All VREF traces should have 10 mil trace width

0.1U_0402_16V7K

0.1U_0402_16V7K CD1

CD1

1

2

2.2U_0603_10V6K

2.2U_0603_10V6K CD2

CD2

1

2

Delete DDR_A_DM[0..7]

+1.5V

RD1

RD1 1K_0402_1%

1K_0402_1%

RD2

RD2 1K_0402_1%

1K_0402_1%

C C

12

+V_DDR_REFA

12

DDR_CKE0_DIMMA6

DDR_A_BS26

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

CD4

1U_0402_6.3V6K

CD4

CD3

B B

1U_0402_6.3V6K

1

2

CD5

CD6

1U_0402_6.3V6K

1

2

CD7

CD8

10U_0603_6.3V6M

CD8

10U_0603_6.3V6M

1

2

CD9

10U_0603_6.3V6M

CD9

10U_0603_6.3V6M

1

2

M_CLK_DDR06 M_CLK_DDR#06

DDR_A_BS06

DDR_A_WE#6 DDR_A_CAS#6

DDR_CS1_DIMMA#6

Layout Note: Place near JDIMM1

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.5V

10U_0603_6.3V6M

CD12

CD13

1

2

CD13

1

2

10U_0603_6.3V6M

CD15

CD14

1

2

10U_0603_6.3V6M

CD16

CD17

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD18

CD18

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD19

CD19

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD20

CD20

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K CD21

CD21

1

+

2

CD22

330U_D2E_2.5VM_R6M+CD22

330U_D2E_2.5VM_R6M

+3VS

2.2U_0603_10V6K

1

2

+V_DDR_REFA

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

RD5 10K_0402_5%RD5 10K_0402_5%

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K CD24

CD24

CD23

1

2

12

RD6

10K_0402_5%

RD6

10K_0402_5%

DDR3 SO-DIMM A

A A

JDDRL

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A621-U4SG-7H

Part Number = SP07000NN00

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

RESET#

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1

VDD2

A15 A14

VDD4

A11

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_CKE1_DIMMA

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6 A4

A2 A0

G2

92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS

0.6A@+0.75VS

M_CLK_DDR1 6 M_CLK_DDR#1 6

DDR_A_BS1 6 DDR_A_RAS# 6

DDR_CS0_DIMMA# 6 M_ODT0 6

M_ODT1 6

DDR3_DRAMRST# 6

DDR_CKE1_DIMMA 6

0.1U_0402_16V7K

2.2U_0603_10V6K

CD10

1

2

1

CD25220P_0402_50V7K

CD26220P_0402_50V7K

@

2

+VREF_CA

CD11

+1.5V

RD3

RD3 1K_0402_1%

1K_0402_1%

RD4

RD4 1K_0402_1%

1K_0402_1%

PCH_SMBDATA 13,22,24,27 PCH_SMBCLK 13,22,24,27

12

TOP SLOT

LA-6961P

Security Classification

2010/04/26 2011/04/26

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/04/26 2011/04/26

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet

DDRIII DIMM

LA-7531P

1

11 45Sunday, April 10, 2011

of

0.1

5

PCH_RTCX1

1

CH3

CH3 18P_0402_50V8J

18P_0402_50V8J

2

1 2

RH119 33_0402_5%RH119 33_0402_5%

1 2

RH120 33_0402_5%RH120 33_0402_5%

1 2

RH121 33_0402_5%RH121 33_0402_5%

HDA_SDOUT_AUDIO29

RH128

PCH_RTCX2

HDA_SYNC_R

HDA_SDO27

12

@RH 129

@

200_0402_5%

12

100_0402_1%

+RTCVCC

HDA_BIT_CLK

HDA_RST#

RH129

RH135

+RTCVCC

RH116

CH4

1U_0603_10V4Z

1 2

RH117 20K_0402_5%RH117 20K_0402_5%

1 2

RH118 20K_0402_5%RH118 20K_0402_5%

CH5

1U_0603_10V4Z

QH1

S

SB000002X00

BSS138W-7-F_SOT323-3

1 2

RH122 0_0402_5%@RH122 0_0402_5%@

1 2

RH123 0_0402_5%

1 2

RH125 33_0402_5%RH125 33_0402_5%

1 2

1M_0402_5%

1

12

CMOS

CLRP1

SHORT PADS

2

1

12

CLRP2

SHORT PADS

2

ME CMOS

CLP1 & CLP2 place near DIMM

+3VS

G

2

HDA_SYNC

13

D

@

HDA_SDOUT

HDA_SPKR29

HDA_SDIN029

SM_INTRUDER#

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

1 2

RH115 10M_0402_5%RH115 10M_0402_5%

32.768KHZ_12.5PF_Q13MC14610002

18P_0402_50V8J

1

CH2

D D

C C

B B

2

far away hot spot

HDA_BITCLK_AUDIO29

HDA_RST_AUDIO#29

HDA_SYNC_AUDIO29

+3V_PCH +3V_PCH+3V_PCH

12

RH127

@RH127

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH133

100_0402_1%

YH1

1

2

OSC

4

OSC

NC3NC

12

@RH128

@

200_0402_5%

12

RH134

RH134 100_0402_1%

100_0402_1%

SPI ROM FOR ME ( 4MByte )

+3V_PCH

RH141

@ RH141

@

3.3K_0402_5%

1 2

RH142 0_0402_5%RH142 0_0402_5%

1 2

PCH_SPI_SO PCH_SPI_SO_R

+3V_PCH

PCH_JTAG_TCK

12

RH15051_0402_5% RH15051_0402_5%

A A

@

CH1

22P_0402_50V8J

12

@

RH151

1 2

33_0402_5%

PCH_SPI_CLK

RH143 0_0402_5%RH143 0_0402_5%

1 2

RH145 3.3K_0402_5%RH145 3. 3K_0402_5%

Reserve for EMI please close to U48

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

4

UH1A

A19

RTCX1

C19

RTCX2

F19

RTCRST#

A23

SRTCRST#

K22

INTRUDER#

C21

INTVRMEN

H35

HDA_BCLK

H37

HDA_SYNC

N1

SPKR

F35

HDA_RST#

D36

HDA_SDIN0

B36

HDA_SDIN1

C35

HDA_SDIN2

A35

HDA_SDIN3

K37

HDA_SDO

K35

HDA_DOCK_EN# / GPIO33

M35

HDA_DOCK_RST# / GPIO13

M17

JTAG_TCK

M15

JTAG_TMS

U12

JTAG_TDI

M12

JTAG_TDO

AD12

SPI_CLK

AB8

SPI_CS0#

AB6

SPI_CS1#

W8

SPI_MOSI

Y2

SPI_MISO

COUGAR-POINT-SFF_BGA1017~D

Part Number = SA000043Z00

SPI ROM FOR ME ( 4MByte )

UH2

1

CS# DO WP# GND

VCC

HOLD#

CLK

DI

2 3 4

W25Q32BVSSIG_SO8

SPI BIOS Pinout

(1)CS# (5)DIO (2)DO (6)CLK (3)WP# (7)HOLD# (4)GND (8)VCC

W25X32

RTCIHDA

JTAG

SPI

8

PCH_SPI_HOLD#

7

PCH_SPI_CLK_R

6 5

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN

SATA3

SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

RH146 0_0402_5%RH146 0_0402_5%

1 2

RH147 0_0402_5%RH147 0_0402_5%

LPC_AD0

A37

LPC_AD1

A39

LPC_AD2

C39

LPC_AD3

C37

LPC_FRAME#

K40

H40 F37

SERIRQ

Y4

AN3 AN1 AU3 AU1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB10

AB12

AF10

AF12

AH4

W10

M2

R1

12 12

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED#

PCH_GPIO21

BBS_BIT0_R

RH144 3.3K_0402_5%RH144 3.3K_0402_5%

PCH_SPI_CLK

PCH_SPI_SIPCH_SPI_SI_R

3

LPC_AD0 27 LPC_AD1 27 LPC_AD2 27 LPC_AD3 27

LPC_FRAME# 27

SERIRQ 27

T19 PAD~D@ T 19 PAD~D@ T20 PAD~D@ T 20 PAD~D@ T21 PAD~D@ T 21 PAD~D@ T22 PAD~D@ T 22 PAD~D@

T23 PAD~D@ T 23 PAD~D@ T24 PAD~D@ T 24 PAD~D@ T25 PAD~D@ T 25 PAD~D@ T26 PAD~D@ T 26 PAD~D@

T27 PAD~D@ T27 PAD~D@ T28 PAD~D@ T 28 PAD~D@ T29 PAD~D@ T 29 PAD~D@ T30 PAD~D@ T 30 PAD~D@

T31 PAD~D@ T 31 PAD~D@ T32 PAD~D@ T 32 PAD~D@ T33 PAD~D@ T 33 PAD~D@ T34 PAD~D@ T 34 PAD~D@

1 2

RH130 37.4_0402_1%RH130 37.4_0402_1%

1 2

RH132 49.9_0402_1%

1 2

RH137 750_0402_1%

T39T39

T35 PAD~D@ T 35 PAD~D@

+3V_PCH

1

CH6

0.1U_0402_16V4Z

2

Place CH95 close to PCH.

+1.05VS_VCC_SATA

+1.05VS_SATA3

RTC Battery

20mils

+RTCVCC

1

2

CH7

CH7 1U_0603_10V4Z

1U_0603_10V4Z

SATA_PRX_DTX_N0 24 SATA_PRX_DTX_P0 24 SATA_PTX_DRX_N0 24 SATA_PTX_DRX_P0 24

SATA_PRX_DTX_N1 22 SATA_PRX_DTX_P1 22 SATA_PTX_DRX_N1 22 SATA_PTX_DRX_P1 22

HDA_SDO

ME debug mode , this signal has a weak internal PD

+RTCBATT

DH1

W=20mils

3

BAS40-04_SOT23-3

2

mSATA PAGE24

Combo MMAX & mSATA mini Card

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

HDA_SYNC

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_SYNC

RH148

RH148 1K_0402_5%

1K_0402_5%

1 2 1

W=20mils

20mils

10mils

+CHGRTC

2

W=20mils

PCH_INTVRMEN

INTVRMEN

*

SERIRQ

PCH_GPIO21

SATA_LED#

HDA_SDOUT

RH149 1K_0402_5% RH149 1K_0402_5%

RH124 330K_0402_5%RH124 330K_0402_5%

RH126 330K_0402_5%@RH126 330K_0402_5%@

烉

Integrated VRM enable

H

烉

Integrated VRM disable

L

RH131 10K_0402_5%RH131 10K_0402_5%

RH136 10K_0402_5%RH136 10K_0402_5%

RH138 10K_0402_5%RH138 10K_0402_5%

HDA_SPKR

RH139 1K_0402_5%@RH139 1K_0402_5%@

RH140 1K_0402_5%@RH140 1K_0402_5%@

Low = Disabled

*

High = Enabled

LOW=Default HIGH=No Reboot

*

12

+3V_PCH

12

1

+RTCVCC

12

+3VS

12

+3VS

12

+3V_PCH

Security Classification

2010/07/06 2011/07/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/06 2011/07/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-7531P

1

of

12 45Sunday, April 10, 2011

0.1

5

4

3

2

1

RH155 10K_0402_5%RH155 10K_0402_5%

UH1B

PCIE_PRX_DTX_N121

PCIE LAN

PCIE Card Reader

D D

MiniWWAN --->

C C

PCIE_PTX_C_DRX_N322 PCIE_PTX_C_DRX_P322

Giga Lan--->

Card Reader--->

MiniWLAN (Mini Card)--->

B B

XTAL25_IN

12

RH1871M_0402_5% <BOM Structure>RH1871M_0402_5% <BOM Structure>

YH2

1 2

18P_0402_50V8J

25MHZ_20PF_7A25000012

1

CH12

2

A A

CH13

XTAL25_OUT

18P_0402_50V8J

1

<BOM Structure>CH13

2

PCIE_PRX_DTX_P121 PCIE_PTX_C_DRX_N121 PCIE_PTX_C_DRX_P121

PCIE_PRX_DTX_N225 PCIE_PRX_DTX_P225

PCIE_PTX_C_DRX_N225 PCIE_PTX_C_DRX_P225

PCIE_PRX_DTX_N322 PCIE_PRX_DTX_P322

+3V_PCH

CLK_PCIE_LAN#21 CLK_PCIE_LAN21

LAN_CLKREQ#21

CLK_PCIE_CD#25 CLK_PCIE_CD25

CLK_PCIE_MINI1#22 CLK_PCIE_MINI122

MINI1_CLKREQ#22

+3V_PCH

CLK_RES_ITP#5

CLK_RES_ITP5

CH8 0.1U_0402_10V7KCH8 0.1U_0402_10V7K

1 2

CH9 0.1U_0402_10V7KCH9 0.1U_0402_10V7K

1 2

CH83 0.1U_0402_10V7KCH83 0.1U_0402_10V7K

1 2

CH82 0.1U_0402_10V7KCH82 0.1U_0402_10V7K

1 2

CH10 0.1U_0402_10V7KCH10 0.1U_0402_10V7K

1 2

CH11 0.1U_0402_10V7KCH11 0.1U_0402_10V7K

1 2

RH171

1 2

RH2 0_0402_5%RH2 0_0402_5% RH3 0_0402_5%RH3 0_0402_5%

+3VS

+3V_PCH

RH177 10K_0402_5%RH177 10K_0402_5%

CDCLK_REQ#25

RH178 0_0402_5%RH178 0_0402_5% RH179 0_0402_5%RH179 0_0402_5% RH180 10K_0402_5%RH180 10K_0402_5%

RH181 10K_0402_5%RH181 10K_0402_5%

RH182 10K_0402_5%RH182 10K_0402_5%

1 2

RH183 10K_0402_5%RH183 10K_0402_5%

1 2

RH185 10K_0402_5%RH185 10K_0402_5%

1 2

RH189 10K_0402_5%RH189 10K_0402_5%

1 2

RH190 0_0402_5%@RH190 0_0402_5%@ RH191 0_0402_5%@RH191 0_0402_5%@

CLK_PCH_14M

33_0402_5%

10K_0402_5%

RH174 10K_0402_5%RH174 10K_0402_5%

12

RH4 0_0402_5%RH4 0_0402_5% RH5 0_0402_5%RH5 0_0402_5%

12

12 12 12

12

12 12

@

RH193

12

22P_0402_50V8J

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIECLKREQ0#

12 12

PCIE_MINI1# PCIE_MINI1

CLK_BCLK_ITP# CLK_BCLK_ITP

@

CH14

1 2

PCIE_LAN# PCIE_LAN

MINI1CLK_REQ#

GPIO46

PCIE_CD# PCIE_CD

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0# / GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1# / GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2# / GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3# / GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4# / GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5# / GPIO44

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ# / GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6# / GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7# / GPIO46

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

COUGAR-POINT-SFF_BGA1017~D

Part Number = SA000043Z00

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

SMBALERT#

H12

SMBCLK

F17

SMBDATA

F10

DRAMRST_CNTRL_PCH

H22

SML0CLK

K12

SML0DATA

A9

C9

SML1CLK

D12

SML1DATA

C11

L3

J1

M8

PCH_GPIO47

R8

AF44 AF46

BB24

CLK_CPU_DMI_PCH

AY24

AN10

CLK_CPU_DPLL_PCH

AN12

CLKIN_DMI#

BD17

CLKIN_DMI

BF17

CLKIN_DMI2#

BB26

CLKIN_DMI2

AY26

CLKIN_DOT96#

M24

CLKIN_DOT96

K24

CLKIN_SATA#

AK8

CLKIN_SATA

AK6

CLK_PCH_14M

J49

CLK_PCI_LPBACK

E51

XTAL25_IN

W49

XTAL25_OUT

W51

XCLK_RCOMP

AC49

H50

D48

G49

J51

Total device

10K_0402_5%

1 2

DRAMRST_CNTRL_PCH 6,7

20090512 add double mosfet prevent ATI M92 electric leakage

RH8

RH172 0_0402_5%RH172 0_0402_5%

1 2

RH173 0_0402_5%RH173 0_0402_5%

1 2

RH175 0_0402_5%RH175 0_0402_5%

1 2

RH176 0_0402_5%RH176 0_0402_5%

1 2

CLK_PCI_LPBACK 15

1 2

RH184 90.9_0402_1%RH184 90.9_0402_1%

RH1540_0402_5% RH1540_0402_5%

12

+3VALW

EC_LID_OUT# 27

+3V_PCH

CLK_CPU_DMI#CLK_CPU_DMI#_PCH CLK_CPU_DMI

CLK_CPU_DPLL#CLK_CPU_DPLL#_PCH CLK_CPU_DPLL

+1.05VS_VCCDIFFCLKN

CLK_CPU_DMI# 5 CLK_CPU_DMI 5

CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5

SMBCLK

2N7002DW-T/R7_SOT363-6

SMBDATA

6 1

RH192

@

1 2

0_0402_5%

2

QH2A

3

2N7002DW-T/R7_SOT363-6

Reserve for EMI please close to UH1

SMBDATA

SMBCLK

SML0CLK

SML0DATA

SML1CLK

SML1DATA

DRAMRST_CNTRL_PCH

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

+3VS

RH186

2.2K_0402_5%

5

4

QH2B

RH194

@

1 2

0_0402_5%

1 2

RH152 2.2K_0402_5%RH152 2.2K_0402_5%

1 2

RH153 2.2K_0402_5%RH153 2.2K_0402_5%

1 2

RH156 2.2K_0402_5%

1 2

RH157 2.2K_0402_5%

1 2

RH159 2.2K_0402_5%RH159 2.2K_0402_5%

1 2

RH160 2.2K_0402_5%RH160 2.2K_0402_5%

1 2

RH161 10K_0402_5%RH161 10K_0402_5%

RH162 10K_0402_5%RH162 10K_0402_5%

1 2

RH163 10K_0402_5%RH163 10K_0402_5%

1 2

RH164 10K_0402_5%RH164 10K_0402_5%

1 2

RH165 10K_0402_5%RH165 10K_0402_5%

1 2

RH166 10K_0402_5%RH166 10K_0402_5%

1 2

RH167 10K_0402_5%RH167 10K_0402_5%

1 2

RH168 10K_0402_5%RH168 10K_0402_5%

1 2

RH169 10K_0402_5%RH169 10K_0402_5%

1 2

RH170 10K_0402_5%RH170 10K_0402_5%

1 2

+3VS

RH188

2.2K_0402_5%

1 2

PCH_SMBCLK 11,22,24,27

PCH_SMBDATA 11,22,24,27

+3V_PCH

@

RH195

CLK_PCI_LPBACK

Reserve for EMI please close to UH1

5

RH195

33_0402_5%

@

CH15

1 2

12

22P_0402_50V8J

4

Security Classification

2010/07/06 2011/07/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/06 2011/07/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-7531P

1

of

13 45Sunday, April 10, 2011

of

13 45Sunday, April 10, 2011

of

13 45Sunday, April 10, 2011

0.1

5

UH1C

DMI_CTX_PRX_N04 DMI_CTX_PRX_N14 DMI_CTX_PRX_N24 DMI_CTX_PRX_N34

DMI_CTX_PRX_P04 DMI_CTX_PRX_P14 DMI_CTX_PRX_P24 DMI_CTX_PRX_P34

D D

DMI_CRX_PTX_N04 DMI_CRX_PTX_N14 DMI_CRX_PTX_N24 DMI_CRX_PTX_N34

DMI_CRX_PTX_P04 DMI_CRX_PTX_P14 DMI_CRX_PTX_P24 DMI_CRX_PTX_P34

+VCCP

1 2

RH196 49.9_0402_1%RH196 49.9_0402_1%

1 2

RH197 750_0402_1%RH197 750_0402_1%

4mil width and place

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

BL21 BL23

BJ19

BL17

BJ21 BJ23

BL19

BJ17

BD22 BB22 BB19 BB17

BF22 AY22 AY19 AY17

BF19

BD19

BK20

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

within 500mil of the PCH

SUSWARN# SUSACK#_R

SUSACK#27

XDP_DBRESET#5

SYS_PWROK5

C C

B B

A A

PCH_GPIO72

RI#

WAKE#

ACIN

SUSWARN#

PCH_RSMRST#

PCH_PWROK27

PM_DRAM_PWRGD5

PCH_RSMRST#27

SUSWARN#27

PBTN_OUT#27

SYS_PWROK

PCH_PWROK

PCH_APWROK27

PCH_RSMRST# PCH_RSMRST#_R

ACIN27,31,35

RH210 10K_0402_5%RH210 10K_0402_5%

1 2

RH211 10K_0402_5%RH211 10K_0402_5%

1 2

RH212 1K_0402_5%RH212 1K_0402_5%

1 2

RH214 10K_0402_5%@RH214 10K_0402_5%@

1 2

RH216 10K_0402_5%RH216 10K_0402_5%

1 2

RH217 10K_0402_5%RH217 10K_0402_5%

1 2

PCH_PWROK

VGATE27,43

RH223 10K_0402_5%RH223 10K_0402_5%

5

1 2

RH198 0_0402_5%RH198 0_0402_5%

1 2

RH200 0_0402_5%RH200 0_0402_5%

XDP_DBRESET#

1 2

RH202 0_0402_5%RH202 0_0402_5%

1 2

RH203 0_0402_5%RH203 0_0402_5%

RH204 0_0402_5%RH204 0_0402_5%

1 2

RH206 0_0402_5%RH206 0_0402_5%

1 2

RH208 0_0402_5%RH208 0_0402_5%

1 2

RH209 0_0402_5%RH209 0_0402_5%

DH2 CH751H-40PT_SOD323-2DH2 CH751H-40PT_SOD323-2

PCH_GPIO72

+3V_PCH

+3VS

5

1

IN1

2

IN2

3

12

SUSACK#_R

PM_PWROK_R

1 2

PM_DRAM_PWRGD

SUSWARN#_R

PBTN_OUT#_R

ACIN_R

21

RI#

UH3

VCC

GND

MC74VHC1G08DFT2G_SC70-5

OUT

SYS_PWROK

4

SYS_PWROK

F15

SUSACK#

L1

SYS_RESET#

M10

SYS_PWROK

M22

PWROK

G3

APWROK

B12

DRAMPWROK

B20

RSMRST#

C13

SUSWARN#/SUSPWRDNACK/GPIO30

K19

PWRBTN#

H19

ACPRESENT / GPIO31

H10

BATLOW# / GPIO72

F12

RI#

COUGAR-POINT-SFF_BGA1017~D

Part Number = SA000043Z00

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H烉Enable

*

L

RH213 330K_0402_5%

RH215 330K_0402_5%RH215 330K_0402_5%

烉

Disable

4

FDI_CTX_PRX_N0

FDI_INT

WAKE#

SLP_A#

+RTCVCC

@

1 2

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB10

BH12

BK8

BK12

BH8

F22

PCH_DPWROK

A21

WAKE#

D8

T2

G6

D3

F6

K10

D4

C7

A15

BB8

A7

FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

1 2

RH201 0_0402_5%RH201 0_0402_5%

PM_CLKRUN#

SUS_STAT#

SUSCLK

RH205 0_0402_5%

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

CTRL_CLK

CTRL_DATA

LVDS_IBG

PCH_ENVDD

ENBKL

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

SUS_STAT# / GPIO61

System Power Management

@

RH222 2.37K_0402_1%RH222 2.37K_0402_1%

RH224 100K_0402_5%RH224 100K_0402_5%

FDI_RXP6

FDI

FDI_RXP7

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

CLKRUN# / GPIO32

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

+3VS

RH218 8.2K_0402_5%

RH219 2.2K_0402_5%RH219 2.2K_0402_5%

RH221 2.2K_0402_5%RH221 2.2K_0402_5%

1 2

RH225 100K_0402_5%RH225 100K_0402_5%

4

RH199 0_0402_5%

1 2

@

T36 PAD~DT36 PAD~D

12

SLP_A# 27

PM_CLKRUN#

FDI_CTX_PRX_N0 4 FDI_CTX_PRX_N1 4 FDI_CTX_PRX_N2 4 FDI_CTX_PRX_N3 4 FDI_CTX_PRX_N4 4 FDI_CTX_PRX_N5 4 FDI_CTX_PRX_N6 4 FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4 FDI_CTX_PRX_P1 4 FDI_CTX_PRX_P2 4 FDI_CTX_PRX_P3 4 FDI_CTX_PRX_P4 4 FDI_CTX_PRX_P5 4 FDI_CTX_PRX_P6 4 FDI_CTX_PRX_P7 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

PCH_RSMRST#

PCH_DPWROK 27

PCH_PCIE_WAKE# 21,22

SUSCLK_R 27

PM_SLP_S5# 27

PM_SLP_S4# 27

PM_SLP_S3# 27

PM_SLP_SUS# 27

H_PM_SYNC 5

PM_CLKRUN#

3

ENBKL27

PCH_ENVDD23

DPST_PWM23

PCH_LCD_CLK23

PCH_LCD_DATA23

T37PAD~D T37PAD~D

1 2

RH207 0_0402_5%RH207 0_0402_5%

PCH_TXCLK-23 PCH_TXCLK+23

PCH_TXOUT0-23 PCH_TXOUT1-23 PCH_TXOUT2-23

PCH_TXOUT0+23 PCH_TXOUT1+23 PCH_TXOUT2+23

EC Request on 20110309

12

RH308

RH308 10K_0402_5%

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1K_0402_0.5%

2010/07/06 2011/07/06

ENBKL

PCH_LCD_CLK PCH_LCD_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

PCH_TXCLKPCH_TXCLK+

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

CRT_IREF

12

RH220

Compal Secret Data

Deciphered Date

2

UH1D

M44

L_BKLTEN

M42

L_VDD_EN

L49

L_BKLTCTL

L51

L_DDC_CLK

K46

L_DDC_DATA

R42

L_CTRL_CLK

M40

L_CTRL_DATA

AH42

LVD_IBG

AH40

LVD_VBG

AG51

LVD_VREFH

AG49

LVD_VREFL

AK44

LVDSA_CLK#

AK46

LVDSA_CLK

AR46

LVDSA_DATA#0

AN49

LVDSA_DATA#1

AN44

LVDSA_DATA#2

AK40

LVDSA_DATA#3

AR44

LVDSA_DATA0

AN51

LVDSA_DATA1

AN46

LVDSA_DATA2

AK42

LVDSA_DATA3

AH46

LVDSB_CLK#

AH44

LVDSB_CLK

AM50

LVDSB_DATA#0

AL49

LVDSB_DATA#1

AJ51

LVDSB_DATA#2

AH50

LVDSB_DATA#3

AM48

LVDSB_DATA0

AL51

LVDSB_DATA1

AJ49

LVDSB_DATA2

AH48

LVDSB_DATA3

M46

CRT_BLUE

R46

CRT_GREEN

U46

CRT_RED

R49

CRT_DDC_CLK

N49

CRT_DDC_DATA

M50

CRT_HSYNC

N51

CRT_VSYNC

R51

DAC_IREF

T48

CRT_IRTN

COUGAR-POINT-SFF_BGA1017~D

PART_NUMBER = SA000043Z00

2

LVDS

Digital Display Interface

CRT

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

HDMI

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

mDP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DMC

1

AU40 AU42

AR51 AR49

AT50 AT48

W42 R44

AW51 AW49 AY42

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51

T50 U44

AU51 AU49 BE46

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

M48 U42

AU46 AU44 BK44

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-7531P

PCH_DDPB_CLK 20 PCH_DDPB_DAT 20

PCH_DDPB_HPD 20

PCH_DPB_N2 20 PCH_DPB_P2 20 PCH_DPB_N1 20 PCH_DPB_P1 20 PCH_DPB_N0 20 PCH_DPB_P0 20 PCH_DPB_N3 20 PCH_DPB_P3 20

1

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