Compal LA-6843P PWWAE LC-Marseille 10AD, Satellite C660, Satellite C660D Schematic
A
1 1
B
C
D
E
Compal confidential
2 2
LC-Marseille 10AD
PWWAE LA-6843P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M
3 3
2010-08-16 Rev. 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
140Wednesday, September 01, 2010
140Wednesday, September 01, 2010
140Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
Compal Confidential
Model Name : PWWAA
File Name : LA-6843P
1 1
Thermal Sensor Fan Control
ADM1032ARMZ
page 7
page 5
AMD S1G4 CPU
uFCPGA-638 Package
page 5,6,7,8
Hyper Transport Link 2.6GHz
16X16
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333MHZ
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
RTL8105E 10/100M
PCIe port 3
page 24
page 9,10
RJ45
page 24
AMD
CRT
page 16
LCD Conn.
page 17
2 2
A-Link Express II
4X PCI-E
IO/B-- USB Right
USB port 0,1
page 23
Card Reader
USB port 5
3 3
page 25
Int. Camera
USB port 9
WLAN
USB port 8
page 17
page 27
USB
5V 480MHz
USB
5V 480MHz
RS880M
page 11,12,13,14,15
AMD
SB820M
page 18,19,20,21,22
PCIe 4x
1.5V 2.5GHz(250MB/s)
SATA port 0
5V 1.5GHz(150MB/s)
SATA port 1
5V 1.5GHz(150MB/s)
SATA HDD
page 23
SATA ODD
page 23
WLAN
LAN
PCIe port 2
page 23
PCIe port 3
page 24
HD Audio
RTC CKT.
Power On/Off CKT.
page 30
DC/DC Interface CKT.
page 31
Power Circuit DC/DC
4 4
page 31,32,33,34,35
36,37,38,39
A
Power/B
page 30
B
Debug Port
page 29
Touch Pad
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ENE KB926 E0
C
3.3V 33 MHz
LPC BUS
page 28
Int.KBD
page 29page 30
EC ROM
page 29
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
3.3V/1.5V 24MHz
Deciphered Date
Deciphered Date
Deciphered Date
HDA Codec
ALC259
page 26
Int.
MIC CONN
page 17
D
MIC CONN
page 27
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
HP CONN
SPK CONN
page 27
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
E
page 27
240Wednesday, September 01, 2010
240Wednesday, September 01, 2010
240Wednesday, September 01, 2010
B
B
B
5
4
3
2
1
DESIGN CURRENT 0.1A
B+
RT8205EGQW
D D
SUSP
N-CHANNEL
DESIGN CURRENT 0.1A
DESIGN CURRENT 1A
DESIGN CURRENT 3.5A
DESIGN CURRENT 2A
+3VL
+5VL
+3VALW
+5VALW
+5VS
SI4800
WOL_EN#
P-CHANNEL
DESIGN CURRENT 330mA
+3V_LAN
AO-3413
SUSP
N-CHANNEL
SI4800
ENVDD
P-CHANNEL
DESIGN CURRENT 1.5A
DESIGN CURRENT 1A
+3VS
+LCD_VDD
AO-3413
C C
APL5508
PWWAE LC-Marseille AMD
SUSP#
MP2121DQ
DESIGN CURRENT 300mA
DESIGN CURRENT 2.5A
+2.5VS
+1.8VS
POK
RT8209BGQW
N-CHANNEL
VLDT_EN#
DESIGN CURRENT 0.3A
DESIGN CURRENT 3.5A
+1.1VALW
+1.1VS
IRF8113
VR_ON
B B
N-CHANNEL
IRF8113
ISL6265A
VLDT_EN#
DESIGN CURRENT 6A
DESIGN CURRENT 18A
DESIGN CURRENT 18A
DESIGN CURRENT 4A
+NB_CORE
+CPU_CORE0
+CPU_CORE1
+VDDNB
SYSON
RT8209BGQW
SUSP
N-CHANNEL
DESIGN CURRENT 5A
DESIGN CURRENT 1A
+1.5V
+1.5VS
IRF8113
SUSP
APL5331KAC
DESIGN CURRENT 1A
+0.75VS
VR_ON#
A A
5
APL5331KAC
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DESIGN CURRENT 1.5A
3
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+1.05VS
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
340Wednesday, September 01, 2010
340Wednesday, September 01, 2010
340Wednesday, September 01, 2010
1
B
B
B
A
B
C
D
E
Voltage Rails
O : ON
X : OFF
+5VS
+1.5V
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.1VS
+1.05VS
+0.75VS
+VGA_CORE
+VDDNB
+CPU_CORE
1 1
State
power
plane
+B
+3VL
+5VL
+RTCVCC
+5VALW
+3VALW
+1.1VALW
Platform
Danube
@ : just reserve , no build
SB820MR1@ : just reserve for SB820MR1 only
R3@ : just reserve for R3 only
CONN@ : just reserve for Connector only
CAM@ : just reserve for WebCam only
BT@ : just reserve for Blue Tooth only
880MR1@: just reserve for 880MR1 only
8105E_VC@: just reserve for 10/100 LAN VC version only
8105E_VB@: just reserve for 10/100 LAN VBversion only
CPU SB
S1G4 SB820M
NB
RS880M
VGA
NA
Comment
S0
S1
2 2
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
O
O
O
O
O
X
O
O
O
O
X
O
XX
X
OO
OO
X
X
XX X
BTO (Build-To-Order) Option Table
Function
Description
Explain
BTO
Camera
( C )
CAM@
SMBUS Control Table
I2C / SMBUS ADDRESSING
3 3
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
EC SM Bus1 address
Device Address
Smart Battery
EC KB926E0
HEX
16H
0001 011X b
HEX
ADDRESS
1 0 1 0 0 0 0 0A0
1 0 1 0 0 0 1 0A2
EC SM Bus2 address
HEX
Device
EMC1032-1 CPU
EC KB926E0
98H
Address
1001 100X b
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
SCL0
SDA0
SCL1
SDA1
SOURCE
KB926
KB926
RS880M
RS880M
SB820
SB820
BATT
V
CPU
THERMAL
SENSOR
V
SODIMM
I / II
CLK
GEN
VV
WLAN
V
LCD
DDC
ROM
V
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
440Wednesday, September 01, 2010
440Wednesday, September 01, 2010
440Wednesday, September 01, 2010
E
B
B
B
A
+1.1VS
250 mil
1
C1
C1
10U_0805_10V6K
10U_0805_10V6K
1 1
2
1
C2
C2
10U_0805_10V6K
10U_0805_10V6K
2
Near CPU SocketVLDT CAP.
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
1
C5
C5
180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6
180P_0402_50V8J
180P_0402_50V8J
2
C
D
E
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
H_CADOP[0..15]
H_CADON[0..15]
+1.1VS
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
1 2
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CADOP[0..15] <11>
H_CADON[0..15] <11>H_CADIN[0..15]<11>
C7
C7
10U_0805_10V6K
10U_0805_10V6K
< To NB >< From NB >
H_CLKOP0 <11>
H_CLKON0 <11>
H_CLKOP1 <11>
H_CLKON1 <11>
H_CTLOP0 <11>
H_CTLON0 <11>
H_CTLOP1 <11>
H_CTLON1 <11>
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
H_CADIP[0..15]<11>
2 2
H_CLKIP0<11>
H_CLKIN0<11>
H_CLKIP1<11>
H_CLKIN1<11>
H_CTLIP0<11>
3 3
H_CTLIN0<11>
H_CTLIP1<11>
H_CTLIN1<11>
H_CADIP[0..15]
H_CADIN[0..15]
VLDT=500mA
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
+1.1VS
JCPUA
JCPUA
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
HT LINK
HT LINK
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
GND
GND
GND
GND
C1119
C1119
8
7
6
5
2
1
B
2
@
@
C1121
C1121
1000P_0402_25V8J
1000P_0402_25V8J
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+FAN1
JFAN
JFAN
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N
ACES_85204-0300N
CONN@
CONN@
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+3VS
12
R795
R795
10K_0402_5%
10K_0402_5%
2
@
@
C1122
C1122
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
FAN_SPEED1 <28>
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
540Wednesday, September 01, 2010
540Wednesday, September 01, 2010
540Wednesday, September 01, 2010
E
of
B
B
B
+FAN1
1
C1120
C1120
10U_0805_10V4Z
10U_0805_10V4Z
2
4 4
EN_DFAN1<28>
A
10U_0805_10V4Z
10U_0805_10V4Z
U31
U31
1
EN
2
VIN
3
VOUT
4
VSET
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
+1.5V
< DDR2 VREF is 0.5 ratio >
A
B
C
D
E
< Processor DDR3 Memory Interface >
< Close to CPU >
R1
R1
1K_0402_1%
1K_0402_1%
1 2
R2
R2
1 1
1K_0402_1%
1K_0402_1%
1 2
2 2
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
3 3
< To SO_DIMMA >
< To SO_DIMMA >
+MCH_REF
1
C9
C9
0.1U_0402_16V7K
0.1U_0402_16V7K
2
Place them close to CPU within 1"
+1.5V
DDR_A_ODT0<9>
DDR_A_ODT1<9>
DDR_CS0_DIMMA#<9>
DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <10>
DDR_CKE0_DIMMA<9>
DDR_CKE1_DIMMA<9>
DDR_A_CLK0<9>
DDR_A_CLK#0<9>
DDR_A_CLK1<9>
DDR_A_CLK#1<9>
DDR_A_MA[15..0]<9>
DDR_A_BS#0<9>
DDR_A_BS#1<9>
DDR_A_BS#2<9>
DDR_A_RAS#<9>
DDR_A_CAS#<9>
DDR_A_WE#<9>
1
C8
C8
1000P_0402_25V8J
1000P_0402_25V8J
2
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
R5 39.2_0402_1%R5 39.2_0402_1%
1 2
MEM_MA_RST#<9>
VDDR5
VDDR6
VDDR7
VDDR8
VDDR9
+1.05VS+1.05VS
W10
AC10
AB10
< VTT regulator voltage >
AA10
A10
Y10
+MCH_REF
W17
MEM_MB_RST#
B18
DDR_B_ODT0
W26
DDR_B_ODT1
W23
Y26
V26
DDR_CS1_DIMMB#
W25
U22
DDR_CKE0_DIMMB
J25
DDR_CKE1_DIMMB
H26
DDR_B_CLK0
P22
DDR_B_CLK#0
R22
A17
A18
AF18
AF17
DDR_B_CLK1
R26
DDR_B_CLK#1
R25
DDR_B_MA0
P24
DDR_B_MA1
N24
DDR_B_MA2
P26
DDR_B_MA3
N23
DDR_B_MA4
N26
DDR_B_MA5
L23
DDR_B_MA6
N25
DDR_B_MA7
L24
DDR_B_MA8
M26
DDR_B_MA9
K26
DDR_B_MA10
T26
DDR_B_MA11
L26
DDR_B_MA12
L25
DDR_B_MA13
W24
DDR_B_MA14
J23
DDR_B_MA15
J24
DDR_B_BS#0
R24
DDR_B_BS#1
U26
DDR_B_BS#2
J26
DDR_B_RAS#
U25
DDR_B_CAS#
U24
DDR_B_WE#
U23
JCPUB
JCPUB
D10
VDDR1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
C10
VDDR2
B10
VDDR3
AD10
MEM_P
MEM_N VTT_SENSE
MEM_MA_RST#
DDR_A_ODT0
DDR_A_ODT1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
VDDR4
AF10
MEMZP
AE10
MEMZN
H16
MA_RESET_L
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7
AA16
MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
VDDR_SENSE
MEMVREF
MB_RESET_L
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
DDR_B_MA[15..0] <10>
T1PAD T1PAD
MEM_MB_RST# <10>
DDR_B_ODT0 <10>
DDR_B_ODT1 <10>
DDR_CS1_DIMMB# <10>
DDR_CKE0_DIMMB <10>
DDR_CKE1_DIMMB <10>
DDR_B_CLK0 <10>
DDR_B_CLK#0 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
DDR_B_D[63..0]<10>
< From/To SO_DIMMB >
DDR_B_DM[7..0]<10> DDR_A_DM[7..0] <9>
< To SO_DIMMB > < To SO_DIMMA >
DDR_B_DQS0<10>
DDR_B_DQS#0<10>
DDR_B_DQS1<10>
DDR_B_DQS#1<10>
DDR_B_DQS2<10>
DDR_B_DQS#2<10>
DDR_B_DQS3<10>
DDR_B_DQS#3<10>
DDR_B_DQS4<10>
DDR_B_DQS#4<10>
DDR_B_DQS5<10>
DDR_B_DQS#5<10>
DDR_B_DQS6<10>
DDR_B_DQS#6<10>
DDR_B_DQS7<10>
DDR_B_DQS#7<10>
< From/To SO_DIMMB > < From/To SO_DIMMA >
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
JCPUC
JCPUC
MEM:DATA
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MEM:DATA
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
A12
B16
A22
E25
AB26
AE22
AC16
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_D[63..0] <9>
< From/To SO_DIMMA >
DDR_A_DQS0 <9>
DDR_A_DQS#0 <9>
DDR_A_DQS1 <9>
DDR_A_DQS#1 <9>
DDR_A_DQS2 <9>
DDR_A_DQS#2 <9>
DDR_A_DQS3 <9>
DDR_A_DQS#3 <9>
DDR_A_DQS4 <9>
DDR_A_DQS#4 <9>
DDR_A_DQS5 <9>
DDR_A_DQS#5 <9>
DDR_A_DQS6 <9>
DDR_A_DQS#6 <9>
DDR_A_DQS7 <9>
DDR_A_DQS#7 <9>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
640Wednesday, September 01, 2010
640Wednesday, September 01, 2010
640Wednesday, September 01, 2010
E
B
B
B
A
< Filtered PLL Supply Voltage >
12
R10
R10
169_0402_1%
169_0402_1%
+2.5VDDA+2.5VS
+2.5VDDA
1
C14
C14
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
1
+
+
C11
C11
@
@
150U_B2_6.3VM_R45M
150U_B2_6.3VM_R45M
2
1 1
< 200-MHz PLL Reference Clock >
CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>
+1.5V
R22 510_0402_5%R22 510_0402_5%
2 2
R28 1K_0402_5%R28 1K_0402_5%
R27 510_0402_5%R27 510_0402_5%
1 2
R29 1K_0402_5%R29 1K_0402_5%
R30 1K_0402_5%R30 1K_0402_5%
R31 1K_0402_5%R31 1K_0402_5%
R32 1K_0402_5%R32 1K_0402_5%
R33 1K_0402_5%R33 1K_0402_5%
R34 1K_0402_5%R34 1K_0402_5%
R265 1K_0402_5%R265 1K_0402_5%
R35 1K_0402_5%R35 1K_0402_5%
1
C12
C12
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C16
C16
3900P_0402_50V7K
3900P_0402_50V7K
1 2
C15
C15
3900P_0402_50V7K
3900P_0402_50V7K
1 2
Address:100_1100 Place close to CPU wihtin 1.5"
12
12
12
12
12
12
12
12
12
12
VDDA=300mA
1
C13
C13
3300P_0402_50V7K
3300P_0402_50V7K
2
CPU_TEST25H
CPU_TEST27
CPU_TEST25L
CPU_TEST12
CPU_TEST18
CPU_TEST19
CPU_TEST20
CPU_TEST21
CPU_TEST22
CPU_TEST23
CPU_TEST24
B
+2.5VDDA
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
LDT_RST#
H_PWRGD
LDT_STOP#
R12 1K_0402_5%R12 1K_0402_5%
+1.5V
R14 1K_0402_5%R14 1K_0402_5%
+1.5V
R15 44.2_0402_1%R15 44.2_0402_1%
R16 44.2_0402_1%R16 44.2_0402_1%
+1.1VS
CPU_VDD0_RUN_FB_H<38>
CPU_VDD0_RUN_FB_L<38>
1 2
1 2
1 2
1 2
CPU_SIC
CPU_SID
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST23
CPU_TEST18
CPU_TEST19
CPU_TEST25H
CPU_TEST25L
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
R24 0_0402_5%R24 0_0402_5%
1 2
T2 PADT2 PAD
C
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
VSS
RSVD11
SVC
SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
M11
W18
CPU_SVC
A6
CPU_SVD
A4
< Serial VID Interface clock & data >
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#
AC7
AA8
W7
W8
W9
Y9
H6
G6
E10
AE9
J7
H8
D7
E7
F7
C7
C3
K8
C4
C9
C8
H18
H19
AA7
D5
C5
T3PAD T3PAD
THERMDC_CPU
THERMDA_CPU
T15PAD T15PAD
T16PAD T16PAD
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TDO
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
D
CPU_SVC <38>
CPU_SVD <38>
CPU_VDDNB_RUN_FB_H <38>
CPU_VDDNB_RUN_FB_L <38>
+1.5V
T4PAD T4PAD
T5PAD T5PAD
T6PAD T6PAD
T7PAD T7PAD
CPU_THERMTRIP#_R
R25 80.6_0402_1%R25 80.6_0402_1%
R11 300_0402_5%R11 300_0402_5%
+1.5V
CPU_PROCHOT#
route as differential
as short as possible
testpoint under package
1 2
R7
R7
1K_0402_5%
1K_0402_5%
1 2
12
1 2
R6
R6
10K_0402_5%
10K_0402_5%
B
B
2
Q1
Q1
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
CPU_SVC
CPU_SVD
R13 0_0402_5%@R13 0_0402_5%@
1 2
H_THERMTRIP# <19>
E
1 2
1 2
+1.5V
R191K_0402_5% R191K_0402_5%
R201K_0402_5% R201K_0402_5%
H_PROCHOT# <18>
+1.5VS
R17
R17
300_0402_5%
3 3
LDT_RST#<18>
H_PWRGD<18,38>
4 4
LDT_STOP#<12,18>
300_0402_5%
1 2
LDT_RST#
1
C17
C17
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.5VS
R21
R21
300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C19
C19
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+1.5VS
R18
R18
300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C18
C18
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
A
R40 300_0402_5%R40 300_0402_5%
+1.5V
+1.5V
1 2
R39 220_0402_5%R39 220_0402_5%
1 2
R38 220_0402_5%R38 220_0402_5%
1 2
R37 220_0402_5%R37 220_0402_5%
1 2
R36 220_0402_5%R36 220_0402_5%
1 2
B
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
+1.5V
< HDT Connector >
JP2
JP2
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
SAMTEC_ASP-68200-07
CONN@
CONN@
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
LDT_RST#
C
0.1U_0402_16V7K
0.1U_0402_16V7K
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+3VS
1
C20
C20
Compal Secret Data
Compal Secret Data
Compal Secret Data
C21
C21
1 2
2
@
@
R44
R44
1 2
+3VS
10K_0402_5%
10K_0402_5%
Deciphered Date
Deciphered Date
Deciphered Date
2200P_0402_50V7K
2200P_0402_50V7K
3/30 Change U1 ADM1032 to EMC1402 for cost down
THERMDC_CPU
CPU_THERM#
D
< Thermal Sensor >
U1
U1
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2
8
SMCLK
7
SMDATA
6
ALERT#
5
GND
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
EC_SMB_CK2
EC_SMB_DA2THERMDA_CPU
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EC_SMB_CK2 <28>
EC_SMB_DA2 <28>
1 2
R41 10K_0402_5%
R41 10K_0402_5%
@
@
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
+3VS
740Wednesday, September 01, 2010
740Wednesday, September 01, 2010
740Wednesday, September 01, 2010
E
B
B
B
A
VDD decoupling : +CPU_CORE
+CPU_CORE
1
+
+
C90
C90
@
@
2
1
+
+
C89
C89
2
1
+
+
C25
C25
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
+
+
C24
C24
@
@
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
C45
C45
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C51
C51
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C67
C67
180P_0402_50V8J
180P_0402_50V8J
2
1
C72
C72
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C58
C58
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C43
C43
22U_0805_6.3V6M
22U_0805_6.3V6M
2
A
1
+
+
C26
C26
2
330U_6.3V_M_R15
330U_6.3V_M_R15
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1
Near CPU Socket
1
+
+
C23
C23
@
@
2
330U_6.3V_M_R15
330U_6.3V_M_R15
330U_X_2VM_R6M
330U_X_2VM_R6M
Near CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
+1.5V
1
C44
C44
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+1.5V
2 2
1
C54
C54
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Between CPU Socket and DIMM
+1.5V
1
C64
C64
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Between CPU Socket and DIMM
+1.5V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C66
C66
180P_0402_50V8J
180P_0402_50V8J
2
Between CPU Socket and DIMM
+1.5V
3 3
1
C71
C71
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
+1.05VS
VDDR decoupling.
1
C57
C57
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side
+1.05VS
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side
4 4
+VDDNB decoupling : Northbridge power
+VDDNB
1
C42
C42
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE +CPU_CORE
1
+
+
2
330U_6.3V_M_R15
330U_6.3V_M_R15
1
+
+
2
330U_6.3V_M_R15
330U_6.3V_M_R15
C96
C96
@
@
C95
C95
@
@
1
C35
C35
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+CPU_CORE +CPU_CORE+CPU_CORE
1
C30
C30
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C46
C46
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C52
C52
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C68
C68
180P_0402_50V8J
180P_0402_50V8J
2
1
C34
C34
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C31
C31
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C47
C47
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C53
C53
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C69
C69
180P_0402_50V8J
180P_0402_50V8J
2
1
C48
C48
180P_0402_50V8J
180P_0402_50V8J
2
C56 Co-layout with C75
1
C73
C73
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C59
C59
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C78
C78
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C49
C49
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C60
C60
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C79
C79
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
@
@
C75
C75
1
C61
C61
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C80
C80
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C28
C28
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C32
C32
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
+
+
2
330U_D2E_2.5VM_R6M
330U_D2E_2.5VM_R6M
B
1
C50
C50
180P_0402_50V8J
180P_0402_50V8J
2
+1.5V
1
+
+
C56
C56
2
1
C62
C62
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C81
C81
1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C29
C29
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C33
C33
22U_0805_6.3V6M
22U_0805_6.3V6M
2
390U_2.5V_M_R10
390U_2.5V_M_R10
1
C63
C63
180P_0402_50V8J
180P_0402_50V8J
2
1
C82
C82
180P_0402_50V8J
180P_0402_50V8J
2
1
C36
C36
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
1
C39
C39
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU SocketUnder CPU Socket
1
C70
C70
180P_0402_50V8J
180P_0402_50V8J
2
1
C83
C83
180P_0402_50V8J
180P_0402_50V8J
2
C
1
C37
C37
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C40
C40
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C38
C38
180P_0402_50V8J
180P_0402_50V8J
2
1
C41
C41
180P_0402_50V8J
180P_0402_50V8J
2
C1124 Co-layout with C1125
+1.05VS
+1.05VS
330U_D2E_2.5VM
330U_D2E_2.5VM
@
@
1
C1125
C1125
+
+
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
390U_2.5V_M_R10
390U_2.5V_M_R10
1
C1124
C1124
+
+
2
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+CPU_CORE
+VDDNB
+1.5V
D
JCPUE
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
JCPUF
JCPUF
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
CONN@
CONN@
D
401982
401982
401982
E
840Wednesday, September 01, 2010
840Wednesday, September 01, 2010
840Wednesday, September 01, 2010
E
+CPU_CORE
P8
VDD1_1
P10
VDD1_2
R4
VDD1_3
R7
VDD1_4
R9
VDD1_5
R11
VDD1_6
T2
VDD1_7
T6
VDD1_8
T8
VDD1_9
T10
VDD1_10
T12
VDD1_11
T14
VDD1_12
U7
VDD1_13
U9
VDD1_14
U11
VDD1_15
U13
VDD1_16
U15
VDD1_17
V6
VDD1_18
V8
VDD1_19
V10
VDD1_20
V12
VDD1_21
V14
VDD1_22
W4
VDD1_23
Y2
VDD1_24
AC4
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.5V
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
B
B
B
A
+1.5V +1.5V
JDDRL
+VREF_DQ
1 1
2 2
3 3
4 4
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C84
C84
DDR_CKE0_DIMMA<6>
DDR_CS1_DIMMA#<6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
1000P_0402_25V8J
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C85
C85
1
DDR_A_DQS#1<6>
DDR_A_DQS1<6>
DDR_A_DQS#2<6>
DDR_A_DQS2<6>
DDR_A_BS#2<6>
DDR_A_CLK0<6>
DDR_A_CLK#0<6>
DDR_A_BS#0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6> DDR_A_ODT0 <6>
DDR_A_DQS#4<6>
DDR_A_DQS4<6>
DDR_A_DQS#6<6>
DDR_A_DQS6<6>
+3VS
C91
C91
DDR_A_D0
DDR_A_D1
1
DDR_A_DM0
C10
C10
DDR_A_D2
2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
+0.75VS
1
2
JDDRL
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
TYCO_2-2013289-1
CONN@
CONN@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
B
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
DDR_A_DM1
28
MEM_MA_RST#
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D30
68
DDR_A_D31
70
72
DDR_CKE1_DIMMA
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
88
DDR_A_MA6
90
DDR_A_MA4
92
94
DDR_A_MA2
96
DDR_A_MA0
98
100
DDR_A_CLK1
102
DDR_A_CLK#1
104
106
DDR_A_BS#1
108
DDR_A_RAS#
110
112
DDR_CS0_DIMMA#
114
116
118
DDR_A_ODT1
120
122
124
126
128
DDR_A_D36
130
DDR_A_D37
132
134
DDR_A_DM4
136
138
DDR_A_D38
140
DDR_A_D39
142
144
DDR_A_D44
146
DDR_A_D45
148
150
DDR_A_DQS#5
152
DDR_A_DQS5
154
156
DDR_A_D46
158
DDR_A_D47
160
162
DDR_A_D52
164
DDR_A_D53
166
168
DDR_A_DM6
170
172
DDR_A_D54
174
DDR_A_D55
176
178
DDR_A_D60
180
DDR_A_D61
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D62
192
DDR_A_D63
194
196
198
200
202
204
206
+0.75VS
DDR_A_DQS#0 <6>
DDR_A_DQS0 <6>
MEM_MA_RST# <6>
DDR_A_DQS#3 <6>
DDR_A_DQS3 <6>
DDR_CKE1_DIMMA <6>
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT1 <6>
1
C680
C680
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1000P_0402_25V8J
1000P_0402_25V8J
DDR_A_DQS#5 <6>
DDR_A_DQS5 <6>
DDR_A_DQS#7 <6>
DDR_A_DQS7 <6>
SMB_CK_DAT0 <10,19>
SMB_CK_CLK0 <10,19>
1
C235
C235
2
2
1
0.01U_0402_25V7K
0.01U_0402_25V7K
C
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_MA[0..15]
C351
C351
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
DDR_A_D[0..63] <6>
DDR_A_DM[0..7] <6>
DDR_A_MA[0..15] <6>
+1.5V
R48
R48
1K_0402_1%
1K_0402_1%
+VREF_DQ +VREF_CA
1 2
R49
R49
1K_0402_1%
1K_0402_1%
1 2
< Close to JDDRH & JDDRL >
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C87
C87
1
+0.75VS
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C665
C665
2
C88
C88
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C664
C664
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C640
C640
1
1
C961
C961
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C641
C641
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C642
C642
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C643
C643
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C644
C644
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C645
C645
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
2
C646
C646
1
E
R310
R310
1K_0402_1%
1K_0402_1%
1 2
R315
R315
1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C647
C647
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_A STD H:5.2 mm
<Address: 00>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
940Wednesday, September 01, 2010
940Wednesday, September 01, 2010
940Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
DQ4
DQ5
VSS3
VSS6
DQ6
DQ7
VSS8
DM1
DM2
CKE1
CK1
CK1#
BA1
RAS#
NC2
DM4
DM6
SDA
SCL
VTT2
+1.5V+1.5V
2
DDR_B_D4
4
DDR_B_D5
6
8
DDR_B_DQS#0
10
DDR_B_DQS0
12
14
DDR_B_D6
16
DDR_B_D7
18
20
DDR_B_D12
22
DDR_B_D13
24
26
DDR_B_DM1
28
MEM_MB_RST#
30
32
DDR_B_D14
34
DDR_B_D15
36
38
DDR_B_D20
40
DDR_B_D21
42
44
DDR_B_DM2
46
48
DDR_B_D22
50
DDR_B_D23
52
54
DDR_B_D28
56
DDR_B_D29
58
60
DDR_B_DQS#3
62
DDR_B_DQS3
64
66
DDR_B_D30
68
DDR_B_D31
70
72
DDR_CKE1_DIMMB
74
76
DDR_B_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDR_B_MA14
80
82
DDR_B_MA11
84
DDR_B_MA7
86
88
DDR_B_MA6
90
DDR_B_MA4
92
94
DDR_B_MA2
96
DDR_B_MA0
98
100
DDR_B_CLK1
102
DDR_B_CLK#1
104
106
DDR_B_BS#1
108
DDR_B_RAS#
110
112
DDR_CS0_DIMMB#
114
DDR_B_ODT0DDR_B_CAS#
116
118
DDR_B_ODT1
120
122
124
126
128
DDR_B_D36
130
DDR_B_D37
132
134
DDR_B_DM4
136
138
DDR_B_D38
140
DDR_B_D39
142
144
DDR_B_D44
146
DDR_B_D45
148
150
DDR_B_DQS#5
152
DDR_B_DQS5
154
156
DDR_B_D46
158
DDR_B_D47
160
162
DDR_B_D52
164
DDR_B_D53
166
168
DDR_B_DM6
170
172
DDR_B_D54
174
DDR_B_D55
176
178
DDR_B_D60
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
198
200
202
204
206
+0.75VS
DDR_B_DQS#0 <6>
DDR_B_DQS0 <6>
MEM_MB_RST# <6>
DDR_B_DQS#3 <6>
DDR_B_DQS3 <6>
DDR_CKE1_DIMMB <6>
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1000P_0402_25V8J
1000P_0402_25V8J
1
C683
C683
2
DDR_B_DQS#5 <6>
DDR_B_DQS5 <6>
DDR_B_DQS#7 <6>
DDR_B_DQS7 <6>
SMB_CK_DAT0 <9,19>
SMB_CK_CLK0 <9,19>
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_MA[0..15]
C353
C353
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C352
C352
0.1U_0402_16V4Z
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
+1.5V
2
C666
C666
1
+0.75VS
2
1
DDR_B_D[0..63] <6>
DDR_B_DM[0..7] <6>
DDR_B_MA[0..15] <6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C667
C667
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C676
C676
C675
C675
1
2
C668
C668
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C925
C925
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C669
C669
1
2
C670
C670
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
1
+
+
C86
C86
330U_X_2VM_R6M@
330U_X_2VM_R6M@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C671
C671
1
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C128 Co-layout with C86
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C672
C672
1
+1.5V
1
+
+
C128
C128
390U_2.5V_M_R10
390U_2.5V_M_R10
2
C673
C673
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C674
C674
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C677
C677
1
Place near DIMM2
JDDRH
+VREF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C92
C92
1 1
2 2
3 3
4 4
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C93
C93
C682
C682
2
2
1000P_0402_25V8J
1000P_0402_25V8J
DDR_B_DQS#1<6>
DDR_B_DQS1<6>
DDR_B_DQS#2<6>
DDR_B_DQS2<6>
DDR_CKE0_DIMMB<6>
DDR_B_BS#2<6>
DDR_B_CLK0<6>
DDR_B_CLK#0<6>
DDR_B_BS#0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>
DDR_B_DQS#4<6>
DDR_B_DQS4<6>
DDR_B_DQS#6<6>
DDR_B_DQS6<6>
+3VS
+0.75VS
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_MA13
DDR_CS1_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
JDDRH
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LOTES_AAA-DDR-111-K01
LOTES_AAA-DDR-111-K01
CONN@
CONN@
DQS#0
DQS0
DQ12
DQ13
VSS10
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_B STD H:9.2 mm
<Address: 01>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
10 40Wednesday, September 01, 2010
10 40Wednesday, September 01, 2010
10 40Wednesday, September 01, 2010
E
B
B
B
of
A
1 1
< WLAN >
< LAN >
2 2
< From SB820 : x4 PCIE A-link >
H_CADON[0..15]
3 3
4 4
H_CADOP[0..15] <5>
H_CADON[0..15] <5>
PCIE_PTX_C_IRX_P2<23>
PCIE_PTX_C_IRX_N2<23>
PCIE_PTX_C_IRX_P3<24>
PCIE_PTX_C_IRX_N3<24>
SB_RX0P<18>
SB_RX0N<18>
SB_RX1P<18>
SB_RX1N<18>
SB_RX2P<18>
SB_RX2N<18>
SB_RX3P<18>
SB_RX3N<18>
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CLKOP0<5>
H_CLKON0<5>
H_CLKOP1<5>
H_CLKON1<5>
H_CTLOP0<5>
H_CTLON0<5>
H_CTLON1<5>
1 2
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
0718 Place within 1"
layout 1:2
R60301_0402_1% R60301_0402_1%
B
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
HT_RXCALP
HT_RXCALN
AC24
AC25
AB25
AB24
AA24
AA25
W21
W20
AB23
AA22
M22
M23
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
M8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
Y22
Y23
V21
V20
U20
U21
U19
U18
T22
T23
R21
R20
C23
A24
U3B
U3B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
GFX_RX9P
L8
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
U3A
U3A
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
A5
GFX_TX0P
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
PART 1 OF 6
PART 1 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
HT_TXCALP
HT_TXCALN
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H24
H25
L21
L20
M24
M25
P19
R18
B24
B25
C
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
PCIE_CALRP
PCIE_CALRN
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
H_CLKIP0 <5>
H_CLKIN0 <5>
H_CLKIP1 <5>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
HT_TXCALP
HT_TXCALN
0718 Place within 1"
layout 1:2
H_CLKIN1 <5>
H_CTLIP0 <5>
H_CTLIN0 <5>
H_CTLIP1 <5>H_CTLOP1<5>
H_CTLIN1 <5>
R61 301_0402_1%R61 301_0402_1%
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1%
1 2
R58 2K_0402_1%R58 2K_0402_1%
1 2
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
1 2
D
PCIE_ITX_C_PRX_P2 <23>
PCIE_ITX_C_PRX_N2 <23>
PCIE_ITX_C_PRX_P3 <24>
PCIE_ITX_C_PRX_N3 <24>
SB_TX0P <18>
SB_TX0N <18>
SB_TX1P <18>
SB_TX1N <18>
SB_TX2P <18>
SB_TX2N <18>
SB_TX3P <18>
SB_TX3N <18>
+1.1VS
H_CADIP[0..15] <5>
H_CADIN[0..15] <5>
< Transmitter Calibration Resistor to HT_TXCALN >
E
PCIE PORT LIST
PORT
PCIE-2
< WLAN >
< LAN >
< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND >
< RX Impedance Calibration. Connect to VDDPCIE >
PCIE-3
DEVICE
WLAN
LAN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
11 40Wednesday, September 01, 2010
11 40Wednesday, September 01, 2010
11 40Wednesday, September 01, 2010
E
B
B
B
of
A
+3VS
1 2
+1.8VS
L4 0_0603_5%L4 0_0603_5%
1 1
+1.8VS
1 2
+1.1VS
1 2
+1.8VS
1 2
2 2
+1.8VS
1 2
+1.8VS
1 2
L3
L3
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C142
C142
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
L6
L6
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L2
L2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L5
L5
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L7
L7
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L9
L9
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+AVDD1
1
C144
C144
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+AVDD2
1
C145
C145
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+AVDDQ
1
C148
C148
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_PLLVDD
1
C141
C141
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_HTPVDD
1
C146
C146
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18HTPLL
1
C150
C150
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18PCIEPLL
1
C154
C154
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
UMA_CRT_R<16>
UMA_CRT_G<16>
UMA_CRT_B<16>
UMA_CRT_HSYNC<15,16>
UMA_CRT_VSYNC<15,16>
UMA_CRT_CLK<16>
UMA_CRT_DATA<16>
PLT_RST#<15,18,23,24,28,29>
NB_PWRGD<19>
CPU_LDT_REQ#<18>
HT_REFCLKP<18>
HT_REFCLKN<18>
NB_REFCLK_P<18>
NB_REFCLK_N<18>
CLK_SBSRC_BCLK<18>
CLK_SBSRC_BCLK#<18>
LCD_EDID_CLK<17>
LCD_EDID_DATA<17>
Strap pin
AUX_CAL<15>
B
+AVDD1
+AVDD2
+AVDDQ
R65 715_0402_1%R65 715_0402_1%
1 2
+NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
R66 0_0402_5%R66 0_0402_5%
1 2
NB_LDTSTOP#
NB_REFCLK_P
NB_REFCLK_N
R330 4.7K_0402_5%R330 4.7K_0402_5%
R331 4.7K_0402_5%R331 4.7K_0402_5%
LCD_EDID_CLK
LCD_EDID_DATA
12
12
T10 PADT10 PAD
T8 PADT8 PAD
AVDD=100mA
NB_RESET#
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
C
PART 3 OF 6
PART 3 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
< Dedicated power for the DAC which can affect display quality >
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
LVTM
LVTM
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
HPD(NC)
TESTMODE
LCD_TXOUT0+
A22
LCD_TXOUT0-
B22
LCD_TXOUT1+
A21
LCD_TXOUT1-
B21
LCD_TXOUT2+
B20
LCD_TXOUT-
A20
A19
< LVDS dual channel : channel 1 >
B19
B18
A18
A17
B17
D20
D21
D18
< LVDS dual channel : channel 2 >
D19
LCD_TXCLK+
B16
LCD_TXCLK-
A16
D16
D17
+VDDLTP18
A13
B13
+VDDLT18
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
TMDS_HPD
D9
D10
D12
AE8
AD8
D13
R84 1.8K_0402_5%R84 1.8K_0402_5%
D
UMA_ENBKL
1 2
LCD_TXOUT0+ <17>
LCD_TXOUT0- <17>
LCD_TXOUT1+ <17>
LCD_TXOUT1- <17>
LCD_TXOUT2+ <17>
LCD_TXOUT2- <17>
LCD_TXCLK+ <17>
LCD_TXCLK- <17>
T9PAD T9PAD
0.1U_0402_16V7K
0.1U_0402_16V7K
R71 0_0402_5%@R71 0_0402_5%@
1 2
SUS_STAT# <15,19>
+VDDLTP18
+VDDLT18
C156
C156
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C153
C153
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C157
C157
2
UMA_ENVDD <17>
UMA_ENBKL <28>
UMA_INVT_PWM <17>
< Strap option pin or gate side-port memory IO >
E
L8
L8
L10
L10
+1.8VS
1 2
+1.8VS
1 2
3 3
R68 300_0402_5%R68 300_0402_5%
+1.8VS
4 4
1 2
R366 1K_0402_1%R366 1K_0402_1%
1 2
R987 140_0402_1%R987 140_0402_1%
1 2
R988 150_0402_1%R988 150_0402_1%
1 2
R989 150_0402_1%R989 150_0402_1%
1 2
A
NB_PWRGD
CPU_LDT_REQ#
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
+1.8VS
C1256
C1256
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
2
B
LDT_STOP#<7,18>
1
A
1 2
R981 0_0402_5%
R981 0_0402_5%
B
5
U57
U57
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
@
@
+1.8VS
R980
R980
2.2K_0402_5%
2.2K_0402_5%
1 2
NB_LDTSTOP#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
12 40Wednesday, September 01, 2010
12 40Wednesday, September 01, 2010
12 40Wednesday, September 01, 2010
E
B
B
B
2
U3D
U3D
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
AD16
AE17
AD17
W12
Y12
AD18
AB13
AB18
V14
V15
B B
W14
AE12
AD12
880MR1@
880MR1@
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
RS780M_FCBGA528
RS780M_FCBGA528
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
+1.8VS
+1.1VS
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
1
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
13 40Wednesday, September 01, 2010
13 40Wednesday, September 01, 2010
13 40Wednesday, September 01, 2010
B
B
B
of
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