Compal LA-6832P PHQAA Marseille 10R, Satellite P750, Satellite P775, LA-6832P PHQAA Marseille 10RG Schematic

A

1 1

B

C

D

E

PHQAA

2 2

Marseille 10R/10RG

LA-6832P SchematicREV 0.1

3 3

4 4

Intel Processor(Sandy Bridge) / PCH(Cougar Point)

2010-09-01 Rev 0.3

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/ 03 2012/12/ 31

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

PHQAA LA-6832P M/B

1 45Monday, September 06 , 2010

E

0.1

A

B

C

D

E

Fan Control

Intel CPU

APL5607

page 5

Sandy Bridge

1 1

CRT

page 14

rPGA-989

37.5mm*37.5mm

page 5,6,7,8,9,10

FDI X8

2.7GT/s

DMI X4

5GT/s

LVDS Conn.

page 13

2 2

EC SMBus

HDMI-CEC

page 15

HDMI Conn.

page 15

Intel PCH

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

USB/B Right Left USB

USB port 0,1

page 25

USB

5V 480MHz

PCIeMini Card

USB

5V 480MHz

PCIe 1x

1.5V 5GT/s

WiMax

USB port 13

PCIeMini Card WLAN

PCIe port 2

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

FingerPrinter

USB port 2

page 25

Felica

USB port 9

page 26

USB port 8

page 26

Int. Camera

USB port 11

page 13

PCIeMini Card

page 27

3G/TV#1 TV#2

USB port 12

page 27

PCIeMini Card

page 27

JET

PCIe port 4

page 27

Express Card USB

USB port 4USB port 10

page 27

Express Card PCIe

PCIe port 3

page 27

Cougar Point - M

RJ45

page 28

RTL8105E 10/100M RTL8111E 1G

PCIe port 1

page 28

Cardreader JMB389C

3 3

PCIe port5

page 29

PCIe 1x

1.5V 5GT/s

PCIe 1x

1.5V 5GT/s

FCBGA-989

25mm*25mm

page 16,17,18,19,20,21,22,23,24

LPC BUS

3.3V 33 MHz

HD Audio

TP& Light Pipe/B LS-6061P

Cap Sensor

RTC CKT.

page 16

& Light Sensor/B LS-6062P

LED/B

DC/DC Interface CKT.

page 35

4 4

Power Circuit DC/DC

page 36,37,38,39,40 41,42,43,44

LS-6063P

Audio & USB/B LS-6064P

Finger Printer/B LS-6065P

Power On/Off CKT.

page 34

A

Power/B_FPC DA300006JM0

page 34

page 25

page 26

page 34

SPI ROM (4MB)

page 16

B

Debug Port

page 33

Touch Pad

page 34

ENE KB930

Int.KBD

page 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 32

EC ROM (128KB)

page 33

2010/09/03 2012/12/31

C

SATA port 0

5V 6GHz(600MB/s)

SATA port 2

5V 3GHz(300MB/s)

PCIe 1x

1.5V 5GT/s

MDC 1.5 Conn

CIR

page 32

EC SMBus

Compal Secret Data

Deciphered Date

3.3V 24MHz

page 26

G-Sensor

page 33

SATA HDD

SATA port 1

page 25

SATA ODD

SATA port 4

page 25

USB3.0 TUSB7320

D

PCIe port6

page 30

MIC Conn

page 13

B-CAS

page 26

SIM

page 27

HDA Codec

ALC269

page 31

SPK ConnInt.

page 31

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

PHQAA LA-6832P M/B

JPIO (HP & MIC)

page 25

2 45Monday, September 06, 2010

E

0.1

5

B+

D D

RT8205EGQW

C C

VR_ON

ISL62883HRZ

4

Ipeak=5A, Imax=3.5A, Iocp min=7.9

SUSP#

SY8033BDBC

SUSP

N-CHANNEL

SI4800

Ipeak=5A, Imax=3.5A, Iocp min=7.7

SUSP

N-CHANNEL

SI4800

BCPWON

P-CHANNEL

AO-3413

KB_LED

P-CHANNEL

AO-3413

+5VS

LDO

G9191

ODD_EN#

P-CHANNEL

AO-3413

WOL_EN#

P-CHANNEL

AO-3413

P-CHANNEL

AO-3415

P-CHANNEL

AO-3413

FELICA_PWR

P-CHANNEL

AO-3413

LCD_ENVDD

BT_PWR#

3

DESIGN CURRENT 0.1A

DESIGN CURRENT 5A

DESIGN CURRENT 2A

DESIGN CURRENT 4A

DESIGN CURRENT 0.5A

DESIGN CURRENT 400mA

DESIGN CURRENT 300mA

DESIGN CURRENT 1.6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

D

ESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 180mA

DESIGN CURRENT 0.5A

DESIGN CURRENT 48A

+3VL +5VL

+5VALW

+1.8VS

+5VS

+5VS_L_BCAS

+5VS_LED

+3VS_HDP

+5VS_ODD

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+BT_VCC

+FLICA_VCC

+CPU_CORE

2

1

VTTP_EN

APW7138NITRL

B B

SUSP#

RT8209BGQW

SUSP#

RT8209BGQW

A A

GFXVR_EN

Ipeak=18A, Imax=12.6A, Iocp min=19.8

Ipeak=7A, Imax=4.9A, Iocp min=7.7

AO-3413

Ipeak=15A, Imax=10.5A, Iocp min=16.5

SUSP

N-CHANNEL

FDS6676AS

SUSP

N-CHANNEL

FDS6676AS

SUSP or 0.75VR_EN#

G2992F1U

ADP3211AMNR2G

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROP RIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROP RIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CO NTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2010/09/03 2012/12/31

4

Compal Secret Data

Deciphered Date

DESIGN CURRENT 18A

DESIGN CURRENT 7A

DESIGN CURRENT 15A

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

DESIGN CURRENT 22A

3

+VTT

+1.05VS

+1.5V

+1.5V_CPU

+1.5VS

+0.75VS

+GFX_CORE

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Tree

PHQAA LA-6832P M/B

2

3 45Monday, September 06, 2010

0.1

1

A

B

C

D

E

Voltage Rails

State

S0

S1

S3

S5 S4/AC

power plane

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

PCH SM Bus Address

Power

+3VS

3 3

+3VS

+3VS Clock Generator

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Clock Generator

New Card

WLAN/WIMAX

3G+3VS

( O MEANS ON X MEANS OFF )

+RTCVCC

O

HEX

A0 H

D2 H

B+

O

X

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

+5VL

+3VL

O

X

+5VALW

+3VALW

+VSB

O

X

+1.5V

+5VS

+3VS

+1.8VS

+1.5VS

+1.05VS

+0.75VS

+CPU_CORE

+VGA_CORE

+GFX_CORE

+VTT

+VRAM_1.5VS

+3VS_DGPU

+1.05VS_DGPU

O

X X

X

X X

BTO Option Table

FP@

CPU

Modem

MDC@

Clarksfield with S3 Power Saving

PSM3@

KB Light

CIR

KB Light

CIR

CIR@

KBL@

Function

description

explain

B

TO

Function

OO

description

explain

BTO

UMA

IHDMI@

MINI PCI-E SLOT

3G TV Tuner WIMAX

3G@ TV@ WIMAX@

HDMI

Discrete/ Optimus

DHDMI@

Arrandale Clarksfield

COMMON

HDMI@

SLOT1SLOT2

CEC

CEC@

10/100M Giga

8105E@ 8111E@

Arrandale Clarksfield

M1@ M3@

LAN

LAN Fingerprint Modem CIR KB Light

Fingerprint

X

Power Saving

JMB389C

JMB389@

G-SENSOR

GSENSOR@

PS@NOPS@

New Card

NEW@

SKU

Discrete Optimus

DIS@ OPT@

N11P & N11E N11M

VRAM

8PCS@

N11P@

N11E

N11E@

LVDS

3D Panel

Discrete Optimus

NO3D@

GPU

N11M-GE1N11P

N11MGE1@

OPTFH@3D@

N11M-GE2

N11MGE2@

Camera & Mic

CAM@

N11M-OP1

N11MOP@

Function

description

X

explain

BTO

Function

description

explain

Felica BLUE TOOTH

Felica BLUE TOOTH G-SENSOR

Felica

FELICA@

No Power Saving

BLUE TOOTH

BT@

S3 Power Saving

BTO

Function

description

explain

TO

B

Card reader

JMB385C/389C

JMB385C

JMB385@

EC SM Bus1 Address

Device Address Address

+3VL

4 4

+3VL Cap. Sensor

A

HEX HEX

16 H

0001 0110 bSmart Battery

HEXDevice AddressPower

Virtual I2C

PowerPower

+3VS

+3VS Light Sensor

EC SM Bus2 Address

Device

96 H

1001 0110 bPCH

NVIDIA GPUHDMI-CEC 34 H 0011 0100 b 1001 1010 b

G-Sensor

B

9A H

40 H

52 H

0100 0000 b

0101 0010 b

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

2010/09/03 2012/12/31

SIGNAL

SLP_S3# SLP_S4# SLP_S5#

Compal Secret Data

Deciphered Date

HIGH HIGHHIGH

LOW

HIGH

LOW

LOW LOWLOW

HIGH

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

PHQAA LA-6832P M/B

4 45Monday, September 06, 2010

E

0.1

5

@

PM_DRAM_PWR GD_R

C4871000P_0402_50V7K

12

@

12

D D

+1.05VS_VCCP

R47 62_0402_5%R47 62_0402_5%

R51 10K_0402_5%R51 10K_0402_5%

12

C4881000P_0402_50V7K

H_PWRGOOD

H_PROCHOT#

H_PWRGOOD

H_PROCHOT#<32,37>

H_THERMTRIP#<21>

Remove R14 (o ohm) fo r HW Revi ew demand

H_PM_SYNC< 18>

H_PWRGOOD<21>

C C

+3VALW

0.1U_0402_16V4Z

PM_PWROK<18,32>

DRAMPWROK<18>

B B

1 2

R312

0_0402_5%

2

1

2

R384 0_0402_5%@R384 0_0402_5%@

1 2

U10

U10 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

5

P

B

4

O

A

G

3

SUSP<9,35,42>

PM_SYS_PWRGD_BUF

SUSP

1

C93

0.1U_0402_16V4Z

+1.5V_CPU

12

R340

R340 39_0402_5%

39_0402_5%

@

13

D

Q5

Q5 2N7002_SOT23

2N7002_SOT23

2

G

@

G

@

S

H_SNB_IVB#<20>

12

R339

R339 200_0402_5%

200_0402_5%

4

H_PECI<32>

H_SNB_IVB#

R450

1 2

BUF_CPU_RST#

TP_SKTOCC#

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

H_THERMTRIP#_R

H_PM_SYNC

H_PWRGOOD

PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF

T1 PADT1 PAD

T2 PADT2 PAD

1 2

R454 130_0402_5%R454 130_0402_5%

JCPUB

PROC_SELECT#

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

JTAG & BPM

BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

@

100 MHz

A28 A27

120 MHz

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

CLK_CPU_DMI CLK_CPU_DMI#

CLK_CPU_DPLL CLK_CPU_DPLL#

H_DRAMRST#

SM_RCOMP_0

R1437 140_0402_1%R1437 140_0402_1%

SM_RCOMP_1

R1438 25.5_0402_1%R1438 25.5_0402_1%

SM_RCOMP_2

R1439 200_0402_1%R1439 200_0402_1%

XDP_PRDY#_R XDP_PREQ#_R

XDP_TCK_R XDP_TMS_R XDP_TRST#_R

XDP_TDI_R XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R XDP_BPM#4_R XDP_BPM#5_R XDP_BPM#6_R

2

CLK_CPU_DMI <17> CLK_CPU_DMI# <17>

H_DRAMRST# <7>

12 12 12

R1 0_0402_5%@R1 0_0402_5%@

1 2

R2 0_0402_5%@R2 0_0402_5%@

1 2

R4 0_0402_5%@R4 0_0402_5%@

1 2

R6 0_0402_5%@R6 0_0402_5%@

1 2

R7 0_0402_5%@R7 0_0402_5%@

1 2

R8 0_0402_5%@R8 0_0402_5%@

1 2

R10 0_0402_5%@R10 0_0402_5%@

1 2

R11 0_0402_5%@R11 0_0402_5%@

1 2

R12 0_0402_5%@R12 0_0402_5%@

1 2

R13 0_0402_5%@R13 0_0402_5%@

1 2

R15 0_0402_5%@R15 0_0402_5%@

1 2

R18 0_0402_5%@R18 0_0402_5%@

1 2

R19 0_0402_5%@R19 0_0402_5%@

1 2

R20 0_0402_5%@R20 0_0402_5%@

1 2

R21 0_0402_5%@R21 0_0402_5%@

1 2

R23 0_0402_5%@R23 0_0402_5%@

1 2

Close to CPU side

Stuff R41 and R42 if do not support eDP

DDR3 Compensatio n Signals Layout Note:Plac e these resistors near P rocessor

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7XDP_BPM#7_R

Routed as a sing le daisy chain

1 2

1K_0402_5%

R24 0_0402_5%@R24 0_0402_5%@

1 2

R25 0_0402_5%@R25 0_0402_5%@

1 2

R26 0_0402_5%@R26 0_0402_5%@

1 2

R27 0_0402_5%@R27 0_0402_5%@

1 2

CLK_CPU_DPLL#

CLK_CPU_DPLL

R36

R42 1K_0402_5%R42 1K_0402_5%

R41 1K_0402_5%R41 1K_0402_5%

+3VS

XDP_DBRESET# <18>

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

R28 51_04 02_5%R28 51_0402_5%

R29 51_04 02_5%R29 51_0402_5%

R30 51_04 02_5%R30 51_0402_5%

R31 51_04 02_5%R31 51_0402_5%

R32 51_04 02_5%R32 51_0402_5%

1

1 2

CFG12 <10> CFG13 <10> CFG14 <10> CFG15 <10>

12

+1.05VS_VCCP

JXDP

@JXDP

XDP Connector

Buffered Reset to CPU

+3VS

0.1U_0402_16V4Z

1

C84

PLT_RST# <20,27,28,29,30,32,33>

U3

PLT_RST#

A A

U3

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

5

2

5

VCC

BUFO_CPU_RST# BUF _CPU_RST#

4

OUT

+1.05VS_VCCP

12

R69

R69 75_0402_5%

75_0402_5%

43_0402_1%

1 2

R155

12

R209

R209 0_0402_5%

0_0402_5%

@

4

PBTN_OUT#< 18,32>

VGATE<18,32,43>

CLK_CPU_ITP<17> CLK_CPU_ITP#<17> +1.05VS_VCCP

CFG0<10>

0.1U_0402_10V6K

H_PWRGOOD XDP_CPU_HOOK0 PBTN_OUT# CFG0 VGATE

C8

@

PLT_RST#

1

2

R35 1K_0402_5%@R35 1K_0402_5%@ R152 0_0402_5%@R152 0_0402_5%@ R37 1K_0402_5%@R37 1K_0402_5%@ R451 0_0402_5%@R451 0_0402_5%@

R40 1K_0402_5%

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

1 2 1 2 1 2 1 2

@

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

3

XDP_CPU_HOOK1 XDP_CPU_HOOK2 XDP_CPU_HOOK3 CLK_CPU_ITP CLK_CPU_ITP#

XDP_CPU_HOOK6 XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

@

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

MOLEX 52435-2671

2010/09/03 2012/12/31

EN_DFAN1<32>

Compal Secret Data

Deciphered Date

+FAN1

10mil

+5VS

2

1A

1

C1

C1 10U_0805_10V6K

10U_0805_10V6K

2

FAN Control Circuit

C3

10U_0805_10V6K

U1

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

GND GND GND GND

8 7 6 5

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

1

JFAN

ACES_85204-0300N

1

C6

0.01U_0402_25V7K

@

2

1

JFAN

1

2

3

4

GND

5

GND

R3 10K_0402_5%R3 10K_0402_5%

12

FAN_SPEED1 <32>

5 45Monday, September 06, 2010

+FAN1

2

C4

C4 1000P_0402_50V7K

1000P_0402_50V7K

@

1

Compal Electronics, Inc.

Sandy Bridge_JTAG/XDP/FAN

PHQAA LA-6832P M/B

+3VS

0.1

of

5

4

3

2

1

+1.05VS_VCCP

R34

24.9_0402_1%

JCPUA

D D

DMI_PTX_CRX_N0<18> DMI_PTX_CRX_N1<18> DMI_PTX_CRX_N2<18> DMI_PTX_CRX_N3<18>

DMI_PTX_CRX_P0<18> DMI_PTX_CRX_P1<18> DMI_PTX_CRX_P2<18> DMI_PTX_CRX_P3<18>

DMI_CTX_PRX_N0<18> DMI_CTX_PRX_N1<18> DMI_CTX_PRX_N2<18> DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18> DMI_CTX_PRX_P1<18> DMI_CTX_PRX_P2<18> DMI_CTX_PRX_P3<18>

FDI_CTX_PRX_N0<18> FDI_CTX_PRX_N1<18> FDI_CTX_PRX_N2<18>

C C

+1.05VS_VCCP

B B

+1.05VS_VCCP

FDI_CTX_PRX_N3<18> FDI_CTX_PRX_N4<18> FDI_CTX_PRX_N5<18> FDI_CTX_PRX_N6<18> FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18> FDI_CTX_PRX_P1<18> FDI_CTX_PRX_P2<18> FDI_CTX_PRX_P3<18> FDI_CTX_PRX_P4<18> FDI_CTX_PRX_P5<18> FDI_CTX_PRX_P6<18> FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18> FDI_FSYNC1<18>

FDI_INT<18>

FDI_LSYNC0<18> FDI_LSYNC1<18>

R9 24.9_0402_1%R9 24.9_0402_1%

1 2

R33 10K_0402_5%

@

12

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

EDP_COMP

Reserve R33 for HW Review demand

eDP_COMP signals should be shorted near balls and routed with typical impedance <25m ohm

JCPUA

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5]

DMI

Intel(R) FDI

eDP

PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

@

PEG_COMP

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_DMI/PEG/FDI

PHQAA LA-6832P M/B

6 45Monday, September 06, 2010

1

0.1

of

5

JCPUC

G10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9

AP11

AN11

AL12 AM12 AM11

AL11

AP12 AN12

AJ14 AH14

AL15

AK15

AL14

AK14

AJ15 AH15

AE10

AF10

AE8 AD9

JCPUC

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9] SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27] SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40] SA_DQ[41]

AJ9

SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1]

V6

SA_BS[2]

SA_CAS# SA_RAS#

AF9

SA_WE#

DDR_A_D[0..63]<11>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3

D D

C C

B B

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#< 11>

DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

4

DDRA_CLK0

AB6

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]

SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

DDRA_CLK0#

AA6

DDRA_CKE0

V9

DDRA_CLK1 DDRB_ CLK1

AA5

DDRA_CLK1# DDRB_ CLK1#

AB5

DDRA_CKE1 DDRB_CKE1

V10

AB4 AA4 W9

AB3 AA3 W10

DDRA_SCS0# DDRB_SCS0#

AK3

DDRA_SCS1#

AL3 AG1 AH1

DDRA_ODT0 DDRB_ODT0

AH3

DDRA_ODT1

AG3 AG2 AH2

DDR_A_DQS#0

C4

DDR_A_DQS#1

G6

DDR_A_DQS#2

J3

DDR_A_DQS#3

M6

DDR_A_DQS#4

AL6

DDR_A_DQS#5

AM8

DDR_A_DQS#6

AR12

DDR_A_DQS#7

AM15

DDR_A_DQS0

D4

DDR_A_DQS1

F6

DDR_A_DQS2

K3

DDR_A_DQS3

N6

DDR_A_DQS4

AL5

DDR_A_DQS5

AM9

DDR_A_DQS6

AR11

DDR_A_DQS7

AM14

DDR_A_MA0

AD10

DDR_A_MA1

W1

DDR_A_MA2

W2

DDR_A_MA3

W7

DDR_A_MA4

V3

DDR_A_MA5

V2

DDR_A_MA6

W3

DDR_A_MA7

W6

DDR_A_MA8

V1

DDR_A_MA9

W5

DDR_A_MA10

AD8

DDR_A_MA11

V4

DDR_A_MA12

W4

DDR_A_MA13

AF8

DDR_A_MA14

V5

DDR_A_MA15

V7

3

JCPUD

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9

AA7

AA10

AB8

AB9

JCPUD

C9 A7

C8 A9 A8 D9 D8

G4

F4

F1 G1 G5

F5

F2 G2

J7 J8

K9

J9

J10

K8

K7 M5

N4

N2

N1 M4

N5 M2 M1

R6

DDR_B_D[0..63]<12>

DDRA_CLK0 <11> DDRB_CLK0 <12> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11> DDRA_CLK1# <11> DDRB_CLK1# <12> DDRA_CKE1 <11>

DDRA_SCS0# <11> DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <1 1> DDRB_ODT0 <12> DDRA_ODT1 <1 1> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#< 12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

T9

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

DDR_B_DQS#0

D7

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

DDRB_CLK0# <12>

DDRB_CLK1 <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

Sandy Bridge_rPGA_Rev0p61

R466

0_0402_5%

1 2

@

Q14

D

S

D

S

1 2

13

BSS138_NL_SOT23-3

G

2

1

C140

0.047U_0402_25V6K

2

H_DRAMRST#<5>

R464

4.99K_0402_1%

A A

DRAMRST_CNTRL_PC H<17>

5

4.99K_0402_1%

DRAMRST_CNTRL

1 2

R463 0_0402_5%R463 0_0402_5%

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

@

+1.5V

12

R465

R467

R467 1K_0402_5%

1K_0402_5%

1 2

4

SM_DRAMRST# <11,12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Sandy Bridge_rPGA_Rev0p61

2

@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_DDR3

PHQAA LA-6832P M/B

7 45Monday, September 06, 2010

1

0.1

5

4

3

2

1

+CPU_CORE

D D

C C

B B

A A

JCPUF

94A (Quad Core 45W) 53A (SV 35W)

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p6 1

POWER

PEG AND DDR

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

5

8.5A

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

@

22U_0805_6.3V6M

AH13 AH10

C146

AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11

C147

H14 H12 H11 G14 G13

22U_0805_6.3V6M

G12 F14 F13 F12 F11 E14 E12

Bottom Socket Cavity x 5

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10 A10

R102

R102 0_0402_5%

0_0402_5%

1 2

22U_0805_6.3V6M

1

C143

C144

2

22U_0805_6.3V6M

1

C145

C163

2

22U_0805_6.3V6M

12

R65 0_0402_5%R65 0_0402_5%

1 2

R52 0_0402_5%R52 0_0402_5%

1 2

R105

R105 100_0402_1%

100_0402_1%

@

1 2

@

R70

R70 130_0402_5%

130_0402_5%

+1.05VS_VCCP

Close to CPU

4

TOP Socket Cavity x 7

22U_0805_6.3V6M

1

C136

C141

2

22U_0805_6.3V6M

1

C153

@

2

1 2

R67 43_0402_1%R67 43_0402_1 %

1 2

R63 0_0402_5%R63 0_0402_5%

1 2

R66 0_0402_5%R66 0_0402_5%

VCCIO_SENSE < 42>

C136

C137

2

22U_0805_6.3V6M

1

C160

C152

@

2

22U_0805_6.3V6M

+1.05VS_VCCP+1.05VS_VCCP

12

R68

R68 75_0402_5%

75_0402_5%

+CPU_CORE

@

R64

R64 100_0402_1%

100_0402_1%

1 2

12

R62

R62 100_0402_1%

100_0402_1%

+1.05VS_VCCP Decoupling: 2X 330U (6m ohm), 12X 22U

22U_0805_6.3V6M

1

C135

2

1

C139

@

2

22U_0805_6.3V6M

ESR 9mohm

330U_D2_2V_Y

VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43>

Pull high resistor on VR side

22U_0805_6.3V6M

1

C134

C133

2

22U_0805_6.3V6M

1

C138

C132

@

2

330U_D2_2V_Y

1

+

C11

C10

2

Cl

ose to CPU

VCCSENSE <43> VSSSENSE < 43>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C142

2

22U_0805_6.3V6M

1

2

1

+

C12

2

3

+1.05VS_VCCP

1

2

1

+

2

+CPU_CORE Decoupling: 4

X 470U (4m ohm), 16X 22U, 10X 10U

+CPU_CORE

10U_0805_10V6K

1

C103

2

10U_0805_10V6K

1

C130

2

22U_0805_6.3V6M

10U_0805_10V6K

1

2

10U_0805_10V6K

1

C101

C102

2

10U_0805_10V6K

330U_D2_2V_Y@

10U_0805_10V6K

+CPU_CORE

C159

22U_0805_6.3V6M

1

C151

2

Top Socket Cavity

+CPU_CORE

22U_0805_6.3V6M

1

C158

2

22U_0805_6.3V6M

C150

C128

2

22U_0805_6.3V6M

Co-Lay with C2, C5, C7, C9

+CPU_CORE

470U_D2_2VM_R4.5M

1

+

C891

2 3

1

+

2 3

470U_D2_2VM_R4.5M

1

+

C890

2 3

470U_D2_2VM_R4.5M

9/02 Add C898 3Pin Bulk Cap by Power Demand

9/02 Change C890, C891, C894 from SGA00005R00 to SGA00004X80 for Power demand

Compal Secret Data

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Bottom Socket Cavity

10U_0805_10V6K

C104

1

C105

2

10U_0805_10V6K

1

C106

2

Top Socket Edge

22U_0805_6.3V6M

1

C129

2

22U_0805_6.3V6M

1

C127

2

C894

2

1

C124

2

22U_0805_6.3V6M

1

C120

2

22U_0805_6.3V6M

1

C123

2

22U_0805_6.3V6M

1

C118

2

330U_D2_2V_Y

10U_0805_10V6K

1

C109

2

10U_0805_10V6K

1

C125

2

22U_0805_6.3V6M

10U_0805_10V6K

1

C110

2

1

@

2

1

C111

@

2

10U_0805_10V6K

1

2

10U_0805_10V6K

1

C107

C108

2

10U_0805_10V6K

1

C122

2

22U_0805_6.3V6M

C121

9/02 Remove C126, C131 by Power Demand

22U_0805_6.3V6M

1

C119

2

22U_0805_6.3V6M

1

C117

2

Bottom Socket Edge

+CPU_CORE

330U_D2_2V_Y

@

+

C2

2

330U_D2_2V_Y

Title

Size Document Number Rev

Custom

Date: Sheet of

@

+

C5

C7

2

Compal Electronics, Inc.

Sandy Bridge_POWER-1

PHQAA LA-6832P M/B

1

@

1

+

C9

330U_D2_2V_Y

2

8 45Monday, September 06, 20 10

1

0.1

5

1

+

C113

2

1

C338

2

22U_0805_6.3V6M

1

C346

2

22U_0805_6.3V6M

1

C391

@

2

22U_0805_6.3V6M

ESR 17mohm

330U_2.5V_M_R17

ESR 6mohm

330U_D2_2VM_R6M@

22U_0805_6.3V6M

1

C341

2

22U_0805_6.3V6M

1

C347

2

1

2

+GFX_CORE Decoupling:

X 470U (4m ohm), 12X 22U

2

+GFX_CORE

D D

Bottom Socket Cavity

Top Socket

C C

Cavity

Bottom Socket Edge

Co-lay for Cost Down Plan

330U_D2_2VM_R6M

1

+

C112

@

2

22U_0805_6.3V6M

1

C267

2

22U_0805_6.3V6M

C271

22U_0805_6.3V6M

C266

Bottom Socket Edge

22U_0805_6.3V6M

C343

1

C344

2

22U_0805_6.3V6M

C345

Top Socket Edge

22U_0805_6.3V6M

1

C350

@

2

22U_0805_6.3V6M

C351

@

22U_0805_6.3V6M

C349

@

1

C342

2

22U_0805_6.3V6M

1

C348

2

22U_0805_6.3V6M

+GFX_CORE

1

C873

2

1

2

1

2

+

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

R76

10U_0805_10V6K

B B

A A

12

0_0805_5%

C185

+

@

330U_B2_2.5VM_R15M

1

C186

2

+1.8VS_VCCPLL

1

C206

2

1U_0402_6.3V6K

1

C230

1U_0402_6.3V6K

2

4

JCPUG

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5

33

VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

1.2A

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61

POWER

A

GRAPHICS

1.8V RAIL

VCC_AXG_SENSE_R

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID0

VCCSA_VID1

AK35 AK34

+V_SM_VREF should have 20 mil trace width

+V_SM_VREF_CNT +V_SM_VREF

AL1

SM_VREF

R486

100K_0402_5%

5A

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

Bottom Socket Cavity

6A

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

@

M27 M26 L26 J26 J25 J24 H26 H25

VCCSA_SENSE

H23

VCCSA_VID0

C22 C24

10K_0402_5%

10U_0805_10V6K

VSS_AXG_SENSE_R

12

1

C148

@

0.1U_0402_16V4Z

2

C114

10U_0805_10V6K

1

C447

C100

2

10U_0805_10V6K

R114

1 2

08/18 Reserve R119 to follow CRB 1.0

3

R111

0_0402_5%

2

@

AP2302GN-HF_SOT23-3

1

RUN_ON_CPU1.5VS3

10U_0805_10V6K

1

C115

2

10U_0805_10V6K

1

C476

2

10U_0805_10V6K

Bo

ttom Socket Edge

1 2

0_0402_5% @

R119

10K_0402_5%

+GFX_CORE

12

3

Q2

1

C116

2

10U_0805_10V6K

1

C154

C149

2

10U_0805_10V6K

12

R252

R252 100_0402_1%

100_0402_1%

1

2

+1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U

+1.5V_CPU

10U_0805_10V6K

1

C155

2

+VCCSA Decoupling: 1X 330U (6m ohm), 3X 10U

+VCCSA

Co-lay for Cost Down Plan

VCCSA_SENSE

1 2

R253 0_0402_5%R253 0_0402_5%

1

C477

1 2

1

+

C485

@

R95

@

C485

@

2

330U_D2_2VM_R6M

2

VCCSA_SENSE <41>

VCCSAP_VID1 <41>

+1.5V_CPU +1.5V

C213 0.1U_0402_16V4ZC213 0.1U_0402_16V4Z

C212 0.1U_0402_16V4ZC212 0.1U_0402_16V4Z

C211 0.1U_0402_16V4ZC211 0.1U_0402_16V4Z

C210 0.1U_0402_16V4ZC210 0.1U_0402_16V4Z

1 2

2

R74

Close to CPU

100_0402_1%

1 2

12

R75

R75 100_0402_1%

100_0402_1%

R122

1 2

100_0402_1%

ESR 6mohm

1

+

C180

@

330U_D2_2VM_R6M

2

VCC_AXG_SENSE <43> VSS_AXG_SENSE <43>

ESR 17mohm

Co-lay for Cost Down Plan

+VCCSA

ESR 17mohm

1

+

2

C877

330U_2.5V_M_R17

R449

470_0805_5%

Q46B

SUSP

2N7002DW-T/R7_SOT363-6

5

PJ32

2

112

JUMP_43X118

+1.5VS

@

+1.5V_CPU

8/20 Add PJ32 for Cost down +1.5V to +1.5V_CPU

+1.5V_CPU

1

+

C875

330U_2.5V_M_R17

2

+VCCSAVCCSA_VID0 VCCSA_VID1

1 2 3

4

0

1

1 1

1

C179

C179 10U_0805_10V4K

10U_0805_10V4K

2

0.1U_0402_25V6

C472

0

1

0

PJ30

2

JUMP_43X118

Q33

1

S

2

S

3

S

4

G

FDS6676AS_SO8

1

2

0.90 V

0.80 V

0.75 V

0.65 V

@PJ30

@

112

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

12

R420

R420 820K_0402_5%

820K_0402_5%

+1.5V+1.5V_CPU

1

For Sandy Bridge

R455

1 2

220K_0402_5%

61

Q46A

SUSP

2

2N7002DW-T/R7_SOT363-6

+VSB

SUSP <5,35,42>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge_POWER-2

PHQAA LA-6832P M/B

1

9 45Monday, September 06, 2010

0.1

of

5

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AR25 AR22 AR19 AR16 AR13 AR10

AR7 AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7

AM4

AM3

AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4 AJ25

AT7

VSS11

AT4

VSS12

AT3

VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

D D

C C

B B

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

P9 P8 P6 P5 P3

P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

L33 L30 L27

L9

L8

L6

L5

L4

L3

L2

L1

K35 K32 K29 K26 J34

J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

H9 H8 H7 H6 H5 H4 H3 H2

H1 G35 G32 G29 G26 G23 G20 G17 G11

F34 F31 F29

JCPUI

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

4

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

3

JCPUE

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

CFG0<5>

T5 PADT5 PAD T6 PADT6 PAD T7 PADT7 PAD T11 PADT11 PAD T12 PADT12 PAD T15 PADT15 PAD T18 PADT18 PAD T16 PADT16 PAD T19 PADT19 PAD T21 PADT21 PAD T20 PADT20 PAD

CFG12<5> CFG13<5> CFG14<5> CFG15<5>

T26 PADT26 PAD T27 PADT27 PAD

T22 PADT22 PAD T24 PADT24 PAD T25 PADT25 PAD T23 PADT23 PAD R255

R115

1K_0402_1%

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

CPU_RSVD6 CPU_RSVD7

12

R116

R116 1K_0402_1%

1K_0402_1%

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

SA_DIMM_VREFDQ

B4

RSVD6

D1

RSVD7

SB_DIMM_VREFDQ

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61

RESERVED

RSVD28 RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

RSVD53

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

2

CFG Straps for Processor

(CFG[17:0] internal pull high to VCCIO)

CFG2

12

R254

R254 1K_0402_1%

1K_0402_1%

@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches socket pin map definition

*

CFG2

1

0:Lane Reversed

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

KEY

@

T28 PADT28 PAD

CLK_RES_ITP <17> CLK_RES_ITP# <1 7>

PCIE Port Bifurcation Straps

CFG[6:5]

CFG4

12

R255 1K_0402_1%

1K_0402_1%

@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

1K_0402_1%

R257

12

R256

R256 1K_0402_1%

1K_0402_1%

@

Sandy Bridge_rPGA_Rev0p61

@

Sandy Bridge_rPGA_Rev0p61

@

CFG7

12

R258

R258 1K_0402_1%

1K_0402_1%

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion

CFG7

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

2

0: PEG Wait for BIOS for training

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Sandy Bridge_GND/RSVD/CFG

PHQAA LA-6831P M/B

0.1

10 45Monday, September 06, 2010

1

10 45Monday, September 06, 2010

0.1

5

+VREF_DQA

1

C156

C157

0.1U_0402_16V4Z

2

D D

Close to JDDRL.1

C C

B B

A A

+3VS

C181

DDR_A_BS2<7>

DDRA_CLK0<7> DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

1

C182

2

2.2U_0603_6.3V4Z

1

2

R90

R90 10K_0402_5%

10K_0402_5%

1

2

0.1U_0402_16V4Z

5

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDRA_CLK0 DDRA_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

+0.75VS

12

R91

R91 10K_0402_5%

10K_0402_5%

+1.5V

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-U2SN-7F_204P

@

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

A15 A14

VDD

A11

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

S0#

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A7

A6 A4

A2 A0

NC

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26 28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDRA_CKE1

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100

DDRA_CLK1

102

DDRA_CLK1#

104 106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDRA_SCS0#

114

DDRA_ODT0

116 118

DDRA_ODT1

120 122 124

+VREF_CAA

126 128

DDR_A_D36

130

DDR_A_D37

132 134 136 138

DDR_A_D38

140

DDR_A_D39

142 144

DDR_A_D44

146

DDR_A_D45

148 150

DDR_A_DQS#5

152

DDR_A_DQS5

154 156

DDR_A_D46

158

DDR_A_D47

160 162

DDR_A_D52

164

DDR_A_D53

166 168 170 172

DDR_A_D54

174

DDR_A_D55

176 178

DDR_A_D60

180

DDR_A_D61

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

+0.75VS

206 208

4

DDR3 SO-DIMM A Reverse Type

SM_DRAMRST# <7,12>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_SCS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

C162

C161

close to JDDRL.126

PM_SMBDATA <12,17,27> PM_SMBCLK <12,17,27>

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

3

+VREF_DQA

+VREF_CAA_DIMMA

2010/09/03 2012/12/31

3

+1.5V

12

R80

1K_0402_1%

12

R82

1K_0402_1%

Layout Note: Place near JDDRL

Change C218 to OSCON at DVT

+1.5V

+

C218 390U_2.5V_M_R10

1 2

C166 10U_0603_6.3V6MC166 10U_0603_6.3V6M

1 2

C168 10U_0603_6.3V6MC168 10U_0603_6.3V6M

1 2

C171 10U_0603_6.3V6MC171 10U_0603_6.3V6M

1 2

C174 10U_0603_6.3V6MC174 10U_0603_6.3V6M

1 2

C176 10U_0603_6.3V6MC176 10U_0603_6.3V6M

1 2

C178 10U_0603_6.3V6MC178 10U_0603_6.3V6M

1 2

Compal Secret Data

Deciphered Date

DDR_A_DQS[0..7] <7>

DDR_A_DQS#[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

+VREF_DQA_DIMMA

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

2

+1.5V

12

R79

1K_0402_1%

12

R81

1K_0402_1%

Layout Note: Place near JDDRL1.203 and 204

+1.5V +0.75VS

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

PHQAA LA-6832P M/B

1

C165 10U_0603_6.3V6MC165 10U_0603_6.3V6M

1 2

C169 1U_0402_6.3V6KC169 1U_0402_6.3V6K

12

C172 1U_0402_6.3V6KC172 1U_0402_6.3V6K

12

C175 1U_0402_6.3V6KC175 1U_0402_6.3V6K

12

C177 1U_0402_6.3V6KC177 1U_0402_6.3V6K

12

11 45Monday, September 06, 2010

1

0.1

A

+VREF_DQB

1

C184

C183

2.2U_0603_6.3V4Z

1 1

2

Close to JDDRH.1

DDRB_CKE0<7>

2 2

3 3

4 4

+3VS

2.2U_0603_6.3V4Z

C207

@

DDR_B_BS2<7>

DDRB_CLK0<7> DDRB_CLK0#<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDRB_SCS1#<7>

1

2

1

C208

2

@

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

2

R98

R98 10K_0402_5%

10K_0402_5%

R99

1 2

10K_0402_5%

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDRB_CLK0 DDRB_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDRB_SCS1#

DDR_B_D37 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

A

+0.75VS

+1.5V

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

FOX_AS0A626-UASN-7F_204P

@

VSS

DQ4

DQ5

VSS

DQS0#

DQS0

VSS

DQ6

DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

A15 A14

VDD

A11

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

S0#

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

A7

A6 A4

A2 A0

NC

B

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26 28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44 46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDRB_CKE1

74 76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86 88

DDR_B_MA6

90

DDR_B_MA4

92 94

DDR_B_MA2

96

DDR_B_MA0

98 100

DDRB_CLK1

102

DDRB_CLK1#

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDRB_SCS0#

114

DDRB_ODT0

116 118

DDRB_ODT1

120 122 124

+VREF_CAB

126 128

DDR_B_D32

130

DDR_B_D33

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D50

174

DDR_B_D51

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198

PM_SMBDATA

200

PM_SMBCLK

202 204

206 208

+0.75VS

B

SM_DRAMRST# <7,11>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

C187

Close to JDDRH.126

PM_SMBDATA <11,17,27> PM_SMBCLK <11,17,27>

Reverse Type DDR3 SO-DIMM B

+VREF_DQB

+VREF_CAB_DIMMB

1

C188

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

C

DDR_B_DQS#[0..7] <7>

DDR_B_DQS[0..7] <7>

DDR_B_D[0..63] <7>

DDR_B_MA[0..15] <7>

+1.5V

12

R83

1K_0402_1%

+VREF_DQB_DIMMB

+1.5V

12

R86

1K_0402_1%

12

R94

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V

2010/09/03 2012/12/31

C

@

+

C189 330U_B2_2.5VM_R15M

1 2

C192 10U_0603_6.3V6MC192 10U_0603_6.3V6M

1 2

C194 10U_0603_6.3V6MC194 10U_0603_6.3V6M

1 2

C197 10U_0603_6.3V6MC197 10U_0603_6.3V6M

1 2

C200 10U_0603_6.3V6MC200 10U_0603_6.3V6M

1 2

C202 10U_0603_6.3V6MC202 10U_0603_6.3V6M

1 2

C204 10U_0603_6.3V6MC204 10U_0603_6.3V6M

1 2

Compal Secret Data

Deciphered Date

12

R84

1K_0402_1%

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

D

E

Layout Note: Place near JDDRH.203 and 204

+0.75VS+1.5V

C191 10U_0603_6.3V6MC191 10U_0603_6.3V6M

1 2

C195 1U_0402_6.3V6KC195 1U_0402_6.3V6K

12

C198 1U_0402_6.3V6KC198 1U_0402_6.3V6K

12

C201 1U_0402_6.3V6KC201 1U_0402_6.3V6K

12

C203 1U_0402_6.3V6KC203 1U_0402_6.3V6K

12

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

PHQAA LA-6832P M/B

12 45Monday, September 06, 2010

E

0.1

A

B

C

D

E

F

G

H

R108

100K_0402_5%

2

5

R112

R112 100K_0402_5%

100K_0402_5%

1 2

+3VS

12

0.1U_0402_16V7K

R109

1 2

47K_0402_5%

3

0.01U_0402_25V7K

Q1B

Q1B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

C228

LCDPWR_GATE

C229

+3VS

2

W=80mils

S

G

1

2

Q17

2

AO3413_SOT23

D

1 3

+LCD_VDD

W=80mils

1

C233

0.1U_0402_16V4Z

2

+LCD_VDD

Reserve fo r EMI requ est

150_0603_5%

CAM@

1 2

R78 0_0402_5%

R78 0_0402_5% L55

@L55

@

USB20_P11<20>

1 1

LCD_EDID_CLK<19>

LCD_EDID_DATA<19>

PCH_PWM<19>

INVT_PWM<32>

C

lose to LVDS Connector

1 2

R357 0_0402_5%R357 0_0402_5%

@

1 2

R358 0_0402_5%

LCD_EDID_CLK

LCD_EDID_DATA

LED_PWM

USB20_N11<20>

8/20 Swap USB20_P11 and USB20_N11 for layout request

1

4

WCM-2012-900T_0805

CAM@

1 2

R96 0_0402_5%

2

3

USB20_P11_R

2

USB20_N11_R

3

UMA_ENVDD<19>

150_0603_5%

2N7002DW-T/R7_SOT363-6

12

R107

61

Q1A

UMA_ENVDD

LCD/PANEL BD. Conn.

D84

@D84

CAM@

+3VS

2 2

LCD_TXOUT0+<19>

LCD_TXOUT0-<19>

LCD_TXOUT1+<19>

LCD_TXOUT1-<19>

LCD_TXOUT2+<19> LCD_TXOUT2-<19> LCD_TXCLK+<19>

LCD_TXCLK-<19>

1 2

R388 0_0603_5%

USB20_P11_R USB20_N11_R

W=20mils

+3VS_LVDS_CAM

CAM@

0.1U_0402_16V4Z

1 2

C225

JLVDS

@JLVDS

@

112

3

4

3

5

6

7

8

7 9910 111112

13

14

13

15

16

15

17

18

17

19

20

19

21

22

23

24

23

25

26

27

28

29

30

31

GND1

32

GND2

ACES_87242-3001-09

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

LCD_EDID_CLK LCD_EDID_DATA INT_MIC_CLK INT_MIC_DATA LED_PWM

BKOFF#_R

R103 33_0402_5%R103 33_0402_5%

1 2

R113 10K_0402_5%R113 10K_0402_5%

+LCD_INV

2

3

PACDN042Y3R_SOT23-3

12

@

1

2

INT_MIC_CLK <31> INT_MIC_DATA <31>

BKOFF# <32>

3A

C226

0.1U_0402_16V4Z

+LCD_VDD

1

C227

4.7U_0805_10V4Z

2

For EMI

@

C231

680P_0402_50V7K

1

2

+3VS

1

C232

0.1U_0402_16V4Z

2

+LCD_INV

1

C234

68P_0402_50V8J

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/09/03 2012/12/31

E

68P_0402_50V8J

Compal Secret Data

2

Deciphered Date

L2

FBMA-L11-201209-221LMA30T_0805

1

C235

0.1U_0402_25V6

2

F

B+

12

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LVDS/eDP

PHQAA LA-6832P M/B

G

PHQAA LA-6832P M/B

0.1

13 45Monday, September 06, 2010

H

0.1

A

B

C

D

E

D3

DAN217_ SC59

1 2

1

2

2.2P_0402_50V8C

2

5

P

A2Y

G

3

1 1

UMA_CRT _R<19>

UMA_CRT _G<1 9>

UMA_CRT _B<19>

R138

R140

R139

12

2 2

UMA_CRT _HSYNC<19>

UMA_CRT _VSYNC<19>

12

150_0402_1%

C244 0.1U_0402_16V 4ZC244 0.1U_0402_16V 4Z

SN74AHC T1G125GW_ SOT353-5

150_0402_1%

C238

1 2

1

2

+CRT_VC C

5

P

A2Y

G

3

L3 NBQ100505T-800 Y_0402L3 NBQ100505T-800 Y_0402

L4 NBQ100505T-800 Y_0402L4 NBQ100505T-800 Y_0402

L5 NBQ100505T-800 Y_0402L5 NBQ100505T-800 Y_0402

1

C239

C240

2

2.2P_0402_50V8C

1

4

OE#

+CRT_VC C

U6

SN74AHC T1G125GW_ SOT353-5

1

@D3

@

D4

DAN217_ SC59

3

2

1

C241

2

2.2P_0402_50V8C

R141 10K_0402_5%R141 10K_0402_5%

1

4

OE#

U7

@D4

@

D5

DAN217_ SC59

3

2

1

C242

2

2.2P_0402_50V8C

12

D_CRT_H SYNC

D_CRT_V SYNC

1

C243

@D5

@

3

+3VS

1

2

2.2P_0402_50V8C

1 2

L6 10_040 2_5%L 6 10_0402_5%

1 2

L7 10_040 2_5%L 7 10_0402_5%

CRT_R_L

CRT_G_L

CRT_B_L

C246

@

2

3

+CRT_VC C

HSYNC

VSYNC

1

2

10P_0402_50V8J

If=1A

D6

RB491D_ SOT23-3

1

1.1A_6V_ MINISMDC110F-2

CRT_R_L

CRT_DDC _DAT CRT_G_L

HSYNC CRT_B_L

VSYNC

CRT_DDC _CLK

F1

21

+5VS +CRT_VC C_R +CRT_VC C

1

C245

@

2

10P_0402_50V8J

40 mils

C237

0.1U_040 2_16V4Z

@

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

ALLTO_C 10532-11505-L_ 15P-T

JCRT

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

1

2

@JCRT

@

16

G

17

G

1

CRT CONNECTOR

3 3

+CRT_VC C

+3VS

R153

4.7K_040 2_5%

2

Q205A

UMA_CRT _CLK<19>

UMA_CRT _DATA<19>

33P_040 2_50V8K

4 4

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C282

2

@

2010/09/ 03 2012/12/ 31

C

Q205A

5

2N7002D W-T/R7_SOT3 63-6

Q205B

4

2N7002D W-T/R7_SOT3 63-6

1

C285

C285 33P_040 2_50V8K

33P_040 2_50V8K

2

@

61

3

470P_04 02_50V8J

Compal Secret Data

Deciphered Date

C284

@

1 2

1

2

R159

4.7K_040 2_5%

CRT_DDC _CLK

CRT_DDC _DAT

C283

C283 470P_04 02_50V8J

470P_04 02_50V8J

@

D

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

CRT

PHQAA LA-6832P M/B

14 45Monday, Sep tember 06, 2010

E

of

0.1

5

HDMI CEC Controller

+3VL+3VL

12

R162

10K_0402_5%

CEC@

Q49

CEC@

100K_0402_5%

CEC@

13

D

S

R163

1 2

27K_0402_5%

CEC@

R165

CEC@

HDMI_CECIN

D D

2N7002_SOT23-3

HDMI_CECOUT

21

D9

D9 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

CEC@

12

R581

R581 27K_0402_5%

27K_0402_5%

CEC@

2

G

CEC@

HDMI_CEC

13

D

Q50

2

2N7002_SOT23-3

G

CEC@

S

12

0.1U_0402_16V4Z

4

U16

CEC_XOUT

CEC_XIN

U16

1

P3_5/SSCK/SCL/CMP1_2

2

P3_7/CNTR0#/SSO/TXD1

3

RESET#

4

XOUT/P4_7

5

VSS/AVSS

6

XIN/P4_6

7

VCC/AVCC

8

MODE

9

P4_5/INT0#/RXD1

10

P1_7/CNTR00/INT10#

R5F211A4C33SP-W 4_LSSOP20

Address: 0011010X

EC_SMB_CK1<32,37> CEC_INT# <32>

+3VL

CEC@

12

R169 4.7K_0402_5%

CEC@

12

R171 47K_0402_5%

CEC@

12

R174 47K_0402_5%

CEC@

12

R176 4.7K_0402_5%

C262

1

CEC@

HDMI_CECIN HDMI_HPD_R

2

HDMI_CECOUT

3

P1_6/CLK0/SSI01

P1_5/RXD0/CNTR01/INT11#

P1_4/TXD0

P1_3/KI3#/AN11/TZOUT

P1_2/KI2#/AN10/CMP0_2

P4_2/VREF

P1_1/KI1#/AN9/CMP0_1

P1_0/KI0#/AN8/CMP0_0

P3_3/TCIN/INT3#/SSI00/CMP1_0

P3_4/SCS#/SDA/CMP1_1

CEC@

CEC_INT#

11

CEC_TEST

12

CEC_FSHUPDCEC_RST#

13

CEC_FSHUPD (Pin13)

14

Low= Force to update flash.

+3VL

15

16

17

18

19

20

CEC@

1 2

R168 4.7K_0402_5%

CEC@

1 2

R170 4.7K_0402_5%

CEC@

CEC@ 1 2

C848 1U_0402_6.3V6K

1 2

C263 0.1U_0402_16V4Z

CEC@

HDMI_CLK

HDMI_DATA

EC_SMB_DA1 <32 ,37>

+3VL

2

R166

4.7K_0402_5%

CEC@

HDMI_CLK

HDMI_DATA

+3VL

12

R164

4.7K_0402_5%

CEC@

+3VL

2

3 1

SGD

BSH111_SOT23-3

2

BSH111_SOT23-3

3 1

SGD

Q48

CEC@

Q47

CEC@

1

HDMI_SCLK

HDMI_SDATA

+3VS

C C

2

SGD

3 1

BSH111_SOT23-3

Q19

HDMI@

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D0+

HDMI_R_D0-

HDMI_R_D2-

HDMI_R_D2+

+5VS

2

SGD

UMA_HDMI_CLK<19>

UMA_HDMI_DATA<19>

UMA_DVI_TXC-

CV308 0.1U_0402_16V7K HDMI@CV308 0.1 U_0402_16V7K HDMI@

UMA_HDMI_TXC+<19>

B B

A A

UMA_HDMI_TXC-<19>

UMA_HDMI_TX0+<19>

UMA_HDMI_TX0-<19>

UMA_HDMI_TX1+<19>

UMA_HDMI_TX1-<19>

UMA_HDMI_TX2+<19>

UMA_HDMI_TX2-<19>

5

1 2

CV304 0.1U_0402_16V7K HDMI@CV304 0.1 U_0402_16V7K HDMI@

1 2

CV306 0.1U_0402_16V7K HDMI@CV306 0.1 U_0402_16V7K HDMI@

1 2

CV302 0.1U_0402_16V7K HDMI@CV302 0.1 U_0402_16V7K HDMI@

1 2

CV303 0.1U_0402_16V7K HDMI@CV303 0.1 U_0402_16V7K HDMI@

1 2

CV301 0.1U_0402_16V7K HDMI@CV301 0.1 U_0402_16V7K HDMI@

1 2

CV307 0.1U_0402_16V7K HDMI@CV307 0.1 U_0402_16V7K HDMI@

1 2

CV305 0.1U_0402_16V7K HDMI@CV305 0.1 U_0402_16V7K HDMI@

1 2

UMA_DVI_TXC+

UMA_DVI_TXC-

UMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1+

UMA_DVI_TXD1-

UMA_DVI_TXD2+

UMA_DVI_TXD2-

UMA_DVI_TXC+

UMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1-

UMA_DVI_TXD1+

UMA_DVI_TXD2+

UMA_DVI_TXD2-

4

@

1 2

R157 0_0402_5%

L8

1

4

OCE2012120YZF

@

1 2

R173 0_0402_5%

@

1 2

R175 0_0402_5%

L9

1

4

OCE2012120YZF

@

1 2

R180 0_0402_5%

@

1 2

R182 0_0402_5%

L10

1

4

OCE2012120YZF

@

1 2

R183 0_0402_5%

@

1 2

R187 0_0402_5%

L11

1

4

OCE2012120YZF

@

1 2

R188 0_0402_5%

HDMI@L8

HDMI@

HDMI@L9

HDMI@

HDMI@L10

HDMI@

HDMI@L11

HDMI@

HDMI_R_CK-

2

3

HDMI_R_CK+

HDMI_R_D0+

2

3

HDMI_R_D0-

HDMI_R_D1-

2

3

HDMI_R_D1+

HDMI_R_D2+

2

3

HDMI_R_D2-

Security Classif ication

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMP AL ELECTRONICS , INC. AND CONTAI NS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P ROPERTY OF COMP AL ELECTRONICS , INC. AND CONTAI NS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 1

BSH111_SOT23-3

08/18 Change R19 5, R197, R198, R202, R201, R203, R205 , R206 to SD028 680080 for UMA request

08/13 Change L8, L9 L10, L11 fr om SM070001600 to SM070001310 b y EMI demand

Issued Date

3

+HDMI_5V_OUT

0.1U_0402_16V4Z

12

R185

R184

2.2K_0402_5%

HDMI@

Q18

HDMI@

1 2

R195 680_0402_1%

HDMI@

1 2

R197 680_0402_1%

HDMI@

1 2

R198 680_0402_1%

HDMI@

1 2

R202 680_0402_1%

HDMI@

1 2

R201 680_0402_1%

HDMI@

1 2

R203 680_0402_1%

HDMI@

1 2

R205 680_0402_1%

HDMI@

1 2

R206 680_0402_1%

2010/09/03 2012/12/31

R185

2.2K_0402_5%

HDMI@

HDMI_SCLK

HDMI_SDATA

13

D

Q24

2

2N7002_SOT23-3

G

HDMI@

S

Compal Secret Data

Deciphered Date

+3VL +3VS

+5VL

2

+5VL

2

C264

HDMI@

HDMI_HPD_R

PMEG2010AEH_SOD123

1

HDMI@

R570

R570 100K_0402_5%

100K_0402_5%

HDMI@

D53

2 1

D54

2 1

CEC@

5

P

A2Y

G

3

12

+HDMI_5V_OUT_F

HDMI@

R145

1 2

1K_0402_5%

1

U9

OE#

74AHCT1G125GW_SOT35 3-5

HDMI@

CH751H-40PT_SOD323-2

HDMI@

100K_0402_5%

HDMI_HPD_R

4

HDMI@

R571

2.2K_0402_5%

D55

21

F2

2 1

1.1A_6V_MINISMDC110F- 2

HDMI@

R186

HDMI@

12

1

2

HDMI_HPD_CHDMI_HPD_U

2

C265

0.1U_0402_16V4Z

HDMI@

1

1 2

HDMI_HPD <19,21>

+HDMI_5V_OUT+5VS

C259

HDMI@

0.1U_0402_16V4Z

HDMI Connector

+HDMI_5V_OUT

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

HDMI_HPD_C

HDMI_SDATA HDMI_SCLK

HDMI_CEC HDMI_R_CK-

HDMI_R_CK+ HDMI_R_D0-

HDMI_R_D0+ HDMI_R_D1-

HDMI_R_D1+ HDMI_R_D2-

HDMI_R_D2+

Compal Electronics, Inc.

HDMI Conn./CEC

PHQAA LA-6832P M/B

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

1

JHDMI

TYCO_1939864-1_19P

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

15 45Monday, September 06, 2010

GND GND GND GND

@JHDMI

@

20 21 22 23

of

0.1

5

CMOS Setting, near DDR Door

R292

+RTCVCC

D D

R292 20K_0402_5%

20K_0402_5%

iME Setting.

R293

R293 20K_0402_5%

20K_0402_5%

Integrated SUS 1.05V VRM Enable

PCH_INTVRMEN

+RTCVCC

R117

1 2

R118

1 2

+3VS

+3VALW

HDA_SDO

ME debug mode, this signal has a weak internal pull down Low = Disable (d efault)

*

High = Enable ( flash descripto r security over ide)

C C

HDA_SYNC

This signal has a weak internal pull down

*

H

=>On Die PLL is supplied by 1.5 V L=>On Die PLL is supplied by 1. 8V Need to pull hig h for Huron Riv er platform

B B

@

1 2

R276 1K_0402_5%

1 2

R560 10K_0402_5%R560 10K_0402_5%

AZ_SYNC_HD<31>

PCH_RTCRST#

1 2

PCH_SRTCRST#

1 2

High - Enable In ternal VRs

must be always p ulled high)

(

1M_0402_5%

330K_0402_5%

PCH_SPIDI PCH_SPICLK PCH_SPICS# PCH_SPIDO

SM_INTRUDER#

PCH_INTVRMEN

+3VALW

1 2

R156 33_0402_5%R156 33_0402_5%

R572 0_0402_5%@R572 0_0402_5%@

1 2

R573 0_0402_5%@R573 0_0402_5%@

1 2

R574 0_0402_5%@R574 0_0402_5%@

1 2

R575 0_0402_5%@R575 0_0402_5%@

1 2

R569 0_0603_5%@R569 0_0603_5%@

+3VS +3V_SPI

For MP phase

C247

1U_0402_6.3V6K

C248

1U_0402_6.3V6K

PCH_SPKR

CR_CPPE#

R284 1K_0402_5%R284 1K_0402_5%

AZ_SYNC_R

12

JCOMS @JCOMS @

1 2

JME @JME @

1 2

12

PCH_SPK High = Enabled (No Reboot) Low = Disabled (Default)

AZ_SYNC

12

+5VS

G

2

Q21

13

D

S

D

S

BSS138_NL_SOT23-3

@

1 2

R285 0_0402_5%

DI CLK CS# DO

8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS

0.1U_0402_16V4Z

Socket: SP07000F500/SP07000H900

Please close to U2 PCH

8/ 12 Change R57 2, R573, R574, R575, R569 from @ to mount

U51

1

1OE#

4

2OE#

10

3OE#

13

PCH_SPIDI PCH_SPICLK PCH_SPICS# PCH_SPIDO

+3VS

1

C455

SPI@

0.1U_0402_16V4Z

2

EC_ON<32,34,39>

+3V_SPI

KSI6<32,33,34> KSI5<32,33> KSI3<32,33> KSI7<32,33>

SPIDI

A A

SPICLK SPICS# SPIDO

EC_ON

1

C456

SPI@

0.1U_0402_16V4Z

2

4OE#

2

1A

5

2A

9

3A

12

4A

14

VCC

SN74CBTLV3125PWR_TSSOP14

SPI@

U52

1

1OE#

4

2OE#

10

3OE#

13

4OE#

2

1A

5

2A

9

3A

12

4A

14

VCC

SN74CBTLV3125PWR_TSSOP14

SPI@

GND

3

1B

6

2B

8

3B

11

4B

7

3

1B

6

2B

8

3B

11

4B

7

DI CLK CS# DO

Please close to U2 PCH,and between U2 & U13

8/12 Change U51, U53 P/N form S A00000BJ20 to S A00000CA00

8/30 Change U53 PIN 9 from KSI4 to KSI3

5

4

AZ_BITCLK_HD<31>

AZ_RST_HD#<31>

AZ_SDIN0_HD<31>

AZ_SDOUT_HD<31>

PWRME_CTRL#<32>

C494

CS#

CLK

+5VALW

1 2

8/30 Add R227 100k ohm

SUSP#<27,32,35,40,42>

4

12

C216 15P_0402_50V8JC216 15P_0402_50V8J Y3

Y3

2

3

32.768KHZ_12.5PF_Q13MC14610002

PCH_SPKR<31>

+3VALW

CR_CPPE#<29>

+3V_SPI

1

2

R227 100K_0402_5%

SPI@

100K_0402_5%

1

OSC

NC

4

OSC

NC

12

C205 15P_0402_50V8JC205 15P_0402_50V8J

R286 33_0402_5%R286 33_0402_5%

1 2

R142 33_0402_5%R142 33_0402_5%

1 2

R273 1K_0402_5%

R289 33_0402_5%R289 33_0402_5%

1 2

R580 0_0402_5%R580 0_0402_5%

1 2

4M Byte

U13

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

MX25L3205DM2I-12G SO8

45@

12

EC_ON

R217

SPI@

12

R443

SPI@

3

U2A

R397

@

C86

12

1

@

2

+5VALW

R418

SPI@

10K_0402_5%

1 2

1

C483

SPI@

0.1U_0402_16V4Z

2

+5VALW

R432

SPI@

10K_0402_5%

1 2

1

C482

SPI@

0.1U_0402_16V4Z

2

U2A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGARPOINT_FCBGA989~D

CLK

JTAG

D43

3

2

RB715FGT106_UMD3S PI@

RTCIHDA

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SATA1GP / GPIO19

1

R226

SPI@

100K_0402_5%

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED#

Q65R3@

12

PCH_RTCX1

PCH_RTCX2

12

PCH_RTCRST#

10M_0402_5%

T37 PADT37 PAD

T38 PADT38 PAD

T39 PADT39 PAD

DODI

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

AZ_BITCLKAZ_BITCLK

AZ_SYNC

PCH_SPKR

AZ_RST#AZ_RST#

AZ_SDIN0_HD

AZ_SDOUT

CR_CPPE#

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPICLK

PCH_SPICS#

PCH_SPIDI

PCH_SPIDO

for EMI

10_0402_5%

10P_0402_50V8J

R291

@

12

4

VSS

2

Q

8/30 Change U13 from SA000021A00 to SA00003IN00 due to EOL of SA000021A00

+5VALW

C249

12

SPI@

8

0.1U_0402_16V4Z

3

P

+

1

O

2

-

G

SPI@

LM393DG_SO8

4

U56A

+5VALW

8

U56B

5

P

+

7

O

6

-

G

SPI@

LM393DG_SO8

4

1 2

R442 100K_0402_5%

SPI@

+5VALW

8/12 Add R442, R 443

8/30 Change R442 , R443 from 10k to 100k

8/30 Change U56 Pin3 from KSO6 to +5VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36

FELICA_PWR

K36

SERIRQ

V5

SATA_PRX_C_DTX_N0

AM3

SATA_PRX_C_DTX_P0

AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

AM10 AM8 AP11 AP10

SATA_PRX_C_DTX_N2

AD7

SATA_PRX_C_DTX_P2

AD5 AH5

SATA_PTX_DRX_P2

AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

SATAICOMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

SATA_LED#

P3

CR_WAKE#

V14

PCH_GPIO19

P1

+3VALW

13

D

Q37

2

G

SPI@

G

SPI@

AO3416_SOT23-3

S

Compal Secret Data

Deciphered Date

2

1 2

R279 37.4_0402_1%R279 37.4_0402_1%

1 2

R280 49.9_0402_1%R280 49.9_0402_1%

1 2

R281 750_0402_1%R281 750_0402_1%

+3V_SPI

2

LPC_AD0 <32,33> LPC_AD1 <32,33> LPC_AD2 <32,33> LPC_AD3 <32,33>

LPC_FRAME# <32,33>

FELICA_PWR <26>

SERIRQ <32,33>

SATA_PRX_C_DTX_N0 <25> SATA_PRX_C_DTX_P0 <25> SATA_PTX_DRX_N0 <25> SATA_PTX_DRX_P0 <25>

SATA_PRX_C_DTX_N2 <25> SATA_PRX_C_DTX_P2 <25> SATA_PTX_DRX_N2 <25> SATA_PTX_DRX_P2 <25>

+1.05VS_VCC_SATA

+1.05VS_SATA3

SATA_LED# <34>

CR_WAKE# <29>

PCH_GPIO19 <20>

BOOT BIOS Strap Bit 0

ODD

12

R363

R363 200_0402_5%

200_0402_5%

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI

12

R306

R306 100_0402_1%

100_0402_1%

1 2

R355 51_0402_1%R355 51_0402_1%

Title

Size Document Number Rev

Date: Sheet of

1

SERIRQ

HDD

SATA_LED#

CR_WAKE#

PCH_GPIO19SATA_PTX_DRX_N2

+RTCVCC

C486

0.1U_0402_16V4Z

+3VALW +3VALW+3VALW

12

PCH_JTAG_TCK

Compal Electronics, Inc.

PCH_HDA/JTAG/SATA/SPI/LPC

Custom

PHQAA LA-6832P M/B

R336 10K_0402_5%R336 10K_0402_5%

R334 10K_0402_5%R334 10K_0402_5%

R335 10K_0402_5%R335 10K_0402_5%

3

1

2

R330

R330 200_0402_5%

200_0402_5%

R295

R295 100_0402_1%

100_0402_1%

1

12

R136 10K_0402_5%R136 10K_0402_5%

12

1 2

1

2

+RTCBATT

D13

D13 BAS40-04_SOT23-3

BAS40-04_SOT23-3

+3VL

R278

R278 200_0402_5%

200_0402_5%

1 2

R301

R301 100_0402_1%

100_0402_1%

1 2

16 45Monday, September 06, 2010

+3VS

0.1

5

PCIE_PRX_C_LANTX_N1<28>

LAN

WLAN

D D

JET

Card Reader

USB30

+3VS

C C

B B

+3VALW

A A

PCIE_PRX_C_LANTX_P1<28> PCIE_PTX_C_LANRX_N1<28> PCIE_PTX_C_LANRX_P1<28>

PCIE_PRX_WLANTX_ N2<27> PCIE_PRX_WLANTX_ P2<27> PCIE_PTX_C_WLANR X_N2<27> PCIE_PTX_C_WLANR X_P2<27>

PCIE_PRX_JETTX_N3<27> PCIE_PRX_JETTX_P3<27> PCIE_PTX_C_JETRX_N3<27> PCIE_PTX_C_JETRX_P3<27>

PCIE_PRX_C_CRTX_N4<29> PCIE_PRX_C_CRTX_P4<29> PCIE_PTX_C_CRRX_N4<29> PCIE_PTX_C_CRRX_P4<29>

PCIE_PRX_C_USBTX_N6<30> PCIE_PRX_C_USBTX_P6<30> PCIE_PTX_C_USBRX_N6<30> PCIE_PTX_C_USBRX_P6<30>

R287 10K_0402_5%R287 10K_0402_5%

1 2

R338 10K_0402_5%R338 10K_0402_5%

1 2

R343 10K_0402_5 %R343 10K_0402_5%

1 2

R344 10K_0402_5 %R344 10K_0402_5%

1 2

R345 10K_0402_5 %R345 10K_0402_5%

1 2

R346 10K_0402_5 %R346 10K_0402_5%

1 2

R348 10K_0402_5 %R348 10K_0402_5%

1 2

R351 10K_0402_5 %R351 10K_0402_5%

1 2

CLK_RES_ITP#<10> CLK_RES_ITP<10>

CLK_CPU_ITP#<5> CLK_CPU_ITP<5>

R347 10K_0402_5%R347 10K_0402_5%

1 2

@

R564 10K_0402_5%

1 2

5

CLKREQ_JET#

CLKREQ_WLAN#

CLKREQ_LAN#

CLKREQ_USB30#

C498 0.1U_0402_16V7KC498 0.1U_0402_16V7K C497 0.1U_0402_16V7KC497 0.1U_0402_16V7K

C501 0.1U_0402_16V7KC501 0.1U_0402_16V7K C502 0.1U_0402_16V7KC502 0.1U_0402_16V7K

C505 0.1U_0402_16V7KC505 0.1U_0402_16V7K C503 0.1U_0402_16V7KC503 0.1U_0402_16V7K

C504 0.1U_0402_16V7KC504 0.1U_0402_16V7K C868 0.1U_0402_16V7KC868 0.1U_0402_16V7K

C519 0.1U_0402_16V7KC519 0.1U_0402_16V7K C869 0.1U_0402_16V7KC869 0.1U_0402_16V7K

LAN

WLAN

CLKREQ_WLAN#<27>

JET

CLKREQ_JET#<27>

Card Reader

USB30

CLKREQ_USB30#<30>

PCH_GPIO26

CLKREQ_CR#

PCH_GPIO46

PCH_GPIO56

R233 0_0402_5%@R233 0 _0402_5%@ R282 0_0402_5%@R282 0 _0402_5%@

R352 0_0402_5%R352 0_ 0402_5% R353 0_0402_5%R353 0_ 0402_5%

LVDS_SEL

1 2 1 2

CLKREQ_LAN#<28>

CLK_WLAN#<27> CLK_WLAN<27>

CLK_USB30#<30> CLK_USB30<30>

12 12

CLK_LAN#<28> CLK_LAN<28>

CLK_JET#<27> CLK_JET<27>

CLK_CR#<29> CLK_CR<29>

12 12

LVDS_SEL

Channel

PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1

PCIE_PRX_WLANTX_ N2 PCIE_PRX_WLANTX_ P2 PCIE_PTX_WLANRX_ N2 PCIE_PTX_WLANRX_ P2

PCIE_PRX_JETTX_N3 PCIE_PRX_JETTX_P3 PCIE_PTX_JETRX_N3 PCIE_PTX_JETRX_P3

PCIE_PRX_C_CRTX_N4 PCIE_PRX_C_CRTX_P4 PCIE_PTX_CRRX_N4 PCIE_PTX_CRRX_P4

PCIE_PRX_C_USBTX_N6 PCIE_PRX_C_USBTX_P6 PCIE_PTX_USBRX_N6 PCIE_PTX_USBRX_P6

CLK_LAN# CLK_LAN

CLKREQ_LAN#

CLK_WLAN# CLK_WLAN

CLKREQ_WLAN#

CLK_JET# CLK_JET

CLKREQ_JET#

CLK_CR# CLK_CR

CLKREQ_CR#

PCH_GPIO26

CLK_USB30# CLK_USB30

CLKREQ_USB30#

PCH_GPIO56

LVDS_SEL

PCH_GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITP

H L

Single (Default)

4

U2B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GP IO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GP IO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GP IO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GP IO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GP IO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GP IO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GP IO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989~D

Dual

4

SMBUSController

SML1ALERT# / PC HHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / C LKOUT_BCLK1_N

CLKOUT_DP_P / C LKOUT_BCLK1_P

CLKIN_GND1_N CLKIN_GND1_P

3

EC_LID_OUT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

Q65R3@

Issued Date

E12

PCH_SMBCLK

H14

PCH_SMBDATA

C9

DRAMRST_CNTRL_PC H

A12

PCH_SMLCLK0

C8

PCH_SMLDATA0

G12

PCH_GPIO74

C13

PCH_SMLCLK1

E14

PCH_SMLDATA1

M16

M7

Control Link only for support Intel IAM T.

T11

P10

PCH_GPIO47

M10

AB37 AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

CLK_DPLL#

AM12

CLK_DPLL

AM13

PCH_CLK_DMI#

BF18

PCH_CLK_DMI

BE18

CLKIN_GND1#

BJ30

CLKIN_GND1

BG30

CLK_DOT#

G24

CLK_DOT

E24

CLK_SATA#

AK7

CLK_SATA

AK5

CLK_14M_PCH

K45

CLK_PCILOOP

H45

PCH_X1

V47

PCH_X2

V49

XCLK_RCOMP

Y47

K43

F47

H47

K49

3

R354 90.9_0402_1%R354 90.9_0402_1%

CLK_FLEX0

PCH_48MCLK

CLK_FLEX2

CLK_FLEX3

2010/09/03 2012/12/31

SMBALERT# / GP IO11

SML0ALERT# / GPIO 60

SML1CLK / GPIO58

SML1DATA / GPIO7 5

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N / CKS SCD_N CLKIN_SATA_P / CKS SCD_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

FLEX CLOCKS

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R576

@R576

@

1 2

22_0402_5%

EC_LID_OUT# <32>

DRAMRST_CNTRL_PC H <7>

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

T13 PADT13 PAD T14 PADT14 PAD

CLK_PCILOOP <20>

T29 PADT29 PAD

T31 PADT31 PAD

T33 PADT33 PAD

Compal Secret Data

120 MHz for eDP

From Clock Gen.

+1.05VS_VCCDIFFCLKN

48MCLK_USB30 <3 0>

Deciphered Date

2

R232 2.2K_0402_5%R232 2.2K_0402_5%

+3VALW +3VS

12

R260 2.2K_0402_5%R260 2.2K_0402_5%

12

PCH_SMBDATA

PCH_SMBCLK

R364 2.2K_0402_5%R364 2.2K_0402_5%

12

R385 2.2K_0402_5%R385 2.2K_0402_5%

12

PCH_SMLDATA1

PCH_SMLCLK1

EC_LID_OUT#

DRAMRST_CNTRL_PC H

PCH_GPIO74

PCH_SMLCLK0

PCH_SMLDATA0

PCH_GPIO47

PCH_CLK_DMI# PCH_CLK_DMI

CLKIN_GND1# CLKIN_GND1

CLK_DOT# CLK_DOT

CLK_SATA# CLK_SATA

CLK_14M_PCH

Q3B

3

2

2N7002DW-T/R7_SOT363-6

Q3A

6 1

2N7002DW-T/R7_SOT363-6

Q4B

3

2

2N7002DW-T/R7_SOT363-6

Q4A

6 1

2N7002DW-T/R7_SOT363-6

5

R123 10K_0402_5%R123 10K_0402_5%

R228 10K_0402_5%R228 10K_0402_5%

R234 10K_0402_5%R234 10K_0402_5%

R238 10K_0402_5%R238 10K_0402_5%

R239 10K_0402_5%R239 10K_0402_5%

R251 10K_0402_5%R251 10K_0402_5%

R242 10K_0402_5%R242 10K_0402_5% R243 10K_0402_5%R243 10K_0402_5%

R244 10K_0402_5%R244 10K_0402_5% R245 10K_0402_5%R245 10K_0402_5%

R246 10K_0402_5%R246 10K_0402_5% R247 10K_0402_5%R247 10K_0402_5%

R248 10K_0402_5%R248 10K_0402_5% R249 10K_0402_5%R249 10K_0402_5%

R250 10K_0402_5%R250 10K_0402_5%

R400 4.7K_0402_5%R400 4.7K_0402_5%

R386 4.7K_0402_5%R386 4.7K_0402_5%

4

5

4

1 2

1 2 1 2

1 2

1

PM_SMBDATA <1 1,12,27>

+3VS+3VALW

EC_SMB_DA2 < 32,33,34>

EC_SMB_CK2 <32,33,34>

For EMI

@

CLK_PCILOOP

27P_0402_50V8J

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

@

12

R417 10_0402_5%

R365 1M_0402_5%R3 65 1M_040 2_5%

PCH_X1 PCH_X2

1 2

25MHZ_20PF_7A25000012

1

C506

2

Compal Electronics, Inc.

PCH_PCI-E/SMBUS/CLK

PHQAA LA-6832P M/B

@

C474 22P_0402_50V8J

12

Y2

1

12

1

2

PM_SMBCLK <11,12,27>

+3VALW

C507

27P_0402_50V8J

17 45Monday, September 06, 2010

0.1

5

+3VALW

D D

R316 200_0402_5%R316 200_0402_5%

R218 10K_0402_5%R218 10K_0402_5%

R220 10K_0402_5%R220 10K_0402_5%

R221 10K_0402_5%R221 10K_0402_5%

R127 10K_0402_5%R127 10K_0402_5%

R128 10K_0402_5%R128 10K_0402_5%

R129 10K_0402_5%R129 10K_0402_5%

C C

VGATE<5,32,43>

PM_PWROK<5,32>

Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit

B B

12

PM_PWROK

@

R137 0_0402_5%

PCH_RSMRST#

PM_PWROK

SYS_PWROK

0_0402_5%

@R259

@

1 2

0.1U_0402_16V4Z

1 2

C250

PCH_SUSPWRDN_RSUSACK#

12

DRAMPWROK

PCH_SUSPWRDN_R

RI#

PCH_LOW_BAT#

R259

+3VS

5

U12

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

+1.05VS_PCH

8/30 Reserve R259 For cost down plan

XDP_DBRESET#<5>

DRAMPWROK<5>

PCH_RSMRST#<32>

PCH_SUSPWRDN<32>

PBTN_OUT#<5,32>

ACIN<32,34,38>

1 2

R469 330K_0402_5%R469 330K_0402_5%

CH751H-40PT_SOD323-2

+3VALW

4

DMI_CTX_PRX_N0<6> DMI_CTX_PRX_N1<6> DMI_CTX_PRX_N2<6> DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6> DMI_CTX_PRX_P1<6> DMI_CTX_PRX_P2<6> DMI_CTX_PRX_P3<6>

DMI_PTX_CRX_N0<6> DMI_PTX_CRX_N1<6> DMI_PTX_CRX_N2<6> DMI_PTX_CRX_N3<6>

DMI_PTX_CRX_P0<6> DMI_PTX_CRX_P1<6> DMI_PTX_CRX_P2<6> DMI_PTX_CRX_P3<6>

1 2

R130 49.9_0402_1%R130 49.9_0402_1%

1 2

R160 750_0402_1%R160 750_0402_1%

PM_PWROK

D12

21

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_COMP

RBIAS_CPY

T34PAD T34PAD

1 2

R216 0_0402_5%R216 0_0402_5%

1 2

R320 0_0402_5%R320 0_0402_5%

SUSACK#

XDP_DBRESET#

SYS_PWROK

PM_PWROK_R

DRAMPWROK

PCH_RSMRST#

PCH_SUSPWRDN_R

PBTN_OUT#

PCH_ACIN

PCH_LOW_BAT#

RI#

U2C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989~D

3

FDI_CTX_PRX_N0

BJ14

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Q65R3@

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWVREN

A18

PCH_DPWROK

E22

EC_SWI#

B9

PM_GPIO32

N3

SUS_STAT#

G8

SUSCLK

N14

PM_SLP_S5#

D10

PM_SLP_S4#

H4

PM_SLP_S3#

F4

PM_SLP_A#

G10

PM_SLP_SUS#

G16

H_PM_SYNC

AP14

PCH_GPIO29 PCH_GPIO29

K14

FDI_CTX_PRX_N0 <6> FDI_CTX_PRX_N1 <6> FDI_CTX_PRX_N2 <6> FDI_CTX_PRX_N3 <6> FDI_CTX_PRX_N4 <6> FDI_CTX_PRX_N5 <6> FDI_CTX_PRX_N6 <6> FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6> FDI_CTX_PRX_P1 <6> FDI_CTX_PRX_P2 <6> FDI_CTX_PRX_P3 <6> FDI_CTX_PRX_P4 <6> FDI_CTX_PRX_P5 <6> FDI_CTX_PRX_P6 <6> FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

T17 PADT17 PAD

@

1 2

R566 0_0402_5%

T35 PADT35 PAD

T58 PADT58 PAD

2

EC_SWI# <28,30>

32.768 KHz

PM_SLP_S5# <32>

PM_SLP_S4# <32>

PM_SLP_S3# <32>

H_PM_SYNC <5>

CLK_EC <32>

1

1 2

R222 0_0402_5%R222 0_0402_5%

PCH_RSMRST#PCH_DPWROK

Stuff R222 if do not support DeepSX state

+RTCVCC

DSWVREN

R224 330K_0402_5%R224 330K_0402_5%

R225 330K_0402_5%@R225 330K_0402_5%@

12

DSWVREN must be always pulled high to +RTCVCC

DSWVREN - Internal Deep Sleep 1.05V regulator H

：：：：

Enable

*

L

：：：：

Disable

+3VS

PM_GPIO32

8/18 Change Net name from PM_CLKRUN# to PCH_GPIO32 by HW Review demand

EC_SWI#

R313 8.2K_0402_5%R313 8.2K_0402_5%

1 2

R319 10K_0402_5%R319 10K_0402_5%

1 2

R563 10K_0402_5%@R563 10K_0402_5%@

1 2

+3VALW

H_PM_SYNC

C898 220P_0402_50V7K

1 2

@

9/1 Reserve C894 for ESD requset

D16

2 1

CH751H-40PT_SOD323-2

D14

POK<37,39>

A A

5

D14

CH751H-40PT_SOD323-2

21

PCH_RSMRST#PM_PWROK PCH_RSMRST#

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION O F R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH_DMI/FDI/PM

PHQAA LA-6832P M/B

18 45Monday, September 06, 2010

1

0.1

5

UMA_ENB KL<32> UMA_ENV DD<13>

LCD_EDID_ CLK<13>

D D

12

UMA_ENB KL

LCTL_CL K

LCTL_DA TA

LCD_EDID_ CLK

LCD_EDID_ DATA

UMA_CRT _CLK

UMA_CRT _DATA

UMA_CRT _B

UMA_CRT _G

UMA_CRT _R

1 2

R230 100K_0402_5 %R230 100K_0402_5 %

+3VS

R471 2.2K_0402_5%R4 71 2.2K_04 02_5%

R472 2.2K_0402_5%R4 72 2.2K_04 02_5%

R223 2.2K_0402_5%R2 23 2.2K_04 02_5%

R229 2.2K_0402_5%R2 29 2.2K_04 02_5%

C C

B B

R237 2.2K_0402_5%R2 37 2.2K_04 02_5%

R231 2.2K_0402_5%R2 31 2.2K_04 02_5%

1 2

R240 150_0402_1%R2 40 150_040 2_1%

1 2

R241 150_0402_1%R2 41 150_040 2_1%

1 2

R318 150_0402_1%R3 18 150_040 2_1%

LCD_EDID_ DATA<1 3>

R219 2.37K_0402_1%R219 2.37K_0402_1%

LCD_TXC LK-< 13> LCD_TXC LK+<13>

LCD_TXO UT0-<13 > LCD_TXO UT1-<13 > LCD_TXO UT2-<13 >

LCD_TXO UT0+<13> LCD_TXO UT1+<13> LCD_TXO UT2+<13>

UMA_CRT _B<14> UMA_CRT _G<14 > UMA_CRT _R< 14>

UMA_CRT _CLK<14> UMA_CRT _DATA<14>

UMA_CRT _HSYNC<14> UMA_CRT _VSYNC<14>

PCH_PW M<13>

1 2

4

UMA_ENB KL UMA_ENV DD

PCH_PW M

LCD_EDID_ CLK LCD_EDID_ DATA

LCTL_CL K LCTL_DA TA

LVDS_IBG

T40 PA DT40 PAD

LCD_TXC LKLCD_TXC LK+

LCD_TXO UT0LCD_TXO UT1LCD_TXO UT2-

LCD_TXO UT0+ LCD_TXO UT1+ LCD_TXO UT2+

UMA_CRT _B UMA_CRT _G UMA_CRT _R

UMA_CRT _CLK UMA_CRT _DATA

UMA_CRT _HSYNC UMA_CRT _VSYNC

CRT_IREF

12

R311 1K_0402_0.5%R3 11 1K_040 2_0.5%

U2D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGARP OINT_FCBGA989~D

3

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

Q65R3@

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

2

+3VS

12

R214

R215

2.2K_040 2_5%

HDMI@

HDMI_HPD HDMI_HPD

UMA_HDM I_TX2UMA_HDM I_TX2+ UMA_HDM I_TX1UMA_HDM I_TX1+ UMA_HDM I_TX0UMA_HDM I_TX0+ UMA_HDM I_TXCUMA_HDM I_TXC+

R473 10 0K_0402_5%R47 3 100K_0402 _5%

R524 10 0K_0402_5%R52 4 100K_0402 _5%

R215

2.2K_040 2_5%

HDMI@

12

UMA_HDM I_CLK <1 5> UMA_HDM I_DATA <15 >

HDMI_HPD < 15,21>

UMA_HDM I_TX2- <15> UMA_HDM I_TX2+ <15> UMA_HDM I_TX1- <15> UMA_HDM I_TX1+ <15> UMA_HDM I_TX0- <15> UMA_HDM I_TX0+ <15> UMA_HDM I_TXC- <1 5> UMA_HDM I_TXC+ <1 5>

HDMI

1

12

100K_04 02_5%

100K_04 02_5% R1433

R1433

A A

Security Class ification

2010/09/ 03 2012/12/ 31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/ 03 2012/12/ 31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH_CRT/LVDS/HDMI

PHQAA LA-6832P M/B

1

0.1

19 45Monday, Sep tember 06, 2010

5

D D

+3VS

RP1

8.2K_0804_8P4R_5%

RP2

8.2K_0804_8P4R_5%

RP3

C C

8.2K_0804_8P4R_5%

1 2

R321 8.2K_0402_5%R321 8.2K_0402_5%

1 2

R322 8.2K_0402_5%R322 8.2K_0402_5%

B B

A A

PCI_PIRQC#

18

PCH_GPIO4

27

PCH_GPIO2

36

PCI_PIRQA#

45

8/23 PIN swap for layout request

PCH_GPIO52

18

PCH_GPIO53

27

PCH_GPIO54

36

RF_OFF#

45

PCH_GPIO50

18

PCI_PIRQB#

27

ODD_DA#

36

WL_OFF#

45

PCH_GPIO5

PCI_PIRQD#

RF_OFF#<27>

WL_OFF#<27>

PLT_RST#<5,27,28,29,30,32,33>

CLK_PCI_EC<32> CLK_PCILOOP<17> CLK_PCI_DDR<33>

RF_OFF#

R5371K_0402_5% @ R5371K_0402_5% @

12

PCH_GPIO19

R5381K_0402_5% @ R5381K_0402_5% @

12

PCH_GPIO19 <16>

ODD_DA#<25>

T32 PADT32 PAD

1 2 1 2 1 2

4

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GPIO50 PCH_GPIO52 PCH_GPIO54

RF_OFF# PCH_GPIO53 WL_OFF#

PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5

PCI_PME#

PLT_RST#

CLK_EC_R

R52522_0402_5% R52522_0402_5%

CLK_PCH

R52622_0402_5% R52622_0402_5%

CLK_SIO

R52722_0402_5% R52722_0402_5%

RF_OFF#

0 0 1 1 1

U2E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

RSVD

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGARPOINT_FCBG A989~D

RSVD

PCI

Boot BIOS Strap

PCH_GPIO19 Boot BIOS Loaction

0 1 0

LPC

Reserved

PCI

SPI

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

DF_TVS

EHCI 1

EHCI 2

USB

*

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE

NV_CLE

NV_RCOMP

NV_RB#

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

Q65R3@

3

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AY1

AV10

AT8

AY5 BA2

AT12 BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

NV_CLE

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2

USB20_N0 <25> USB20_P0 <25> USB20_N1 <25> USB20_P1 <25> USB20_N2 <25> USB20_P2 <25>

USB-RIGHT1

USB-RIGHT2

USB-Left1

USB port6 and port7 are disabled on HM65

USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13

USBBIAS

USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 SLP_CHG_M3 SLP_CHG_M4

USB20_N8 <26> USB20_P8 <26> USB20_N9 <27> USB20_P9 <27> USB20_N10 <27> USB20_P10 <27> USB20_N11 <13> USB20_P11 <13> USB20_N12 <27> USB20_P12 <27> USB20_N13 <26> USB20_P13 <26>

1 2

R535 22.6_0402_1%R535 22.6_0402_1%

Within 500 mils

USB_OC#0 <25,32> USB_OC#1 <27,30, 32>

SLP_CHG_M3 <27> SLP_CHG_M4 <27>

Finger Printer

WiMax

TV Tuner #1

Int. Camera

3G/ TV tuner #2

Felica

USB-Right USB-Left & eSATA

2

1

DMI & FDI Termination Voltage

Set to VCC when HIGH

NV_CLE

Set to VSS when LOW

+1.8VS

12

R324

2.2K_0402_5%

NV_CLE

R323 1K_0402_5%R32 3 1K_0402_5%

8/18 Change R324 From 1K to 2.2K by Intel check list demand

H_SNB_IVB#

12

C895 220P_0402_50V7K

1 2

@

H_SNB_IVB# <5>

9/1 Reserve C895 for ESD requset

+3VALW

RP4

SLP_CHG_M4 USB_OC#0 SLP_CHG_M3 USB_OC#4

8/23 PIN swap for layout request

USB_OC#1 USB_OC#2 USB_OC#3

RP4

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

RP5

4 5 3 6 2 7 1 8

10K_0804_8P4R_5%

WL_OFF#

R5361K_0402_5% @ R5361K_0402_5% @

12

5

A16 Swap Override Strap

WL_OFF#

*

4

Low= A16 swap override Enable High= A16 swap override Disable

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH_PCI/USB/NAND

PHQAA LA-6832P M/B

20 45Monday, September 06, 2010

1

0.1

5

4

3

2

1

Q53B

+3VS

3

5

4

+3VS

+3VALW

T74 PADT74 PAD

HDMI_HPD

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

PCH_GPIO1 2

USB30_S MI#

PCH_GPIO1 6

PCH_GPIO1 7

BT_DET#

PCH_GPIO2 7

PCH_GPIO2 8

BT_ON#

PCH_GPIO3 5

ODD_DET ECT#

PCH_GPIO3 7

OPTIMUS_E N#

CIR_EN#

ISDBT_DET

PCH_GPIO4 9

PCH_GPIO5 7

USB30_S MI#

EC_SMI#

PCH_GPIO1 2

PCH_GPIO2 8

PCH_GPIO5 7

BT_ON#

HDMI_HPD

PCH_GPIO1

BT_DET#

OPTIMUS_E N#

ODD_DET ECT#

PCH_GPIO6

PCH_GPIO1 6

EC_SCI#

CIR_EN#

ISDBT_DET

PCH_GPIO4 9

PCH_GPIO1 7

USB30_S MI#

PCH_GPIO3 7

PCH_GPIO2 7

CIR_EN#

ISDBT_DET

PCH_GPIO2 8

1 2

@

1 2

@

1 2

@

CIR@

1 2

R325 1K_0402 _5%@R325 1K_0 402_5%@

1 2

12

R390 1K _0402_5%R390 1K _0402_5%

R558 10 K_0402_5%R558 10K _0402_5%

D D

C C

B B

R556 10 K_0402_5%R556 10K _0402_5%

R557 10 K_0402_5%R557 10K _0402_5%

R549 10 K_0402_5%R549 10K _0402_5%

+3VS

R567 10 K_0402_5%R567 10K _0402_5%

R539 10 K_0402_5%

R540 10 K_0402_5%R540 10K _0402_5%

R542 10 K_0402_5%R542 10K _0402_5%

R554 10 K_0402_5%R554 10K _0402_5%

R545 200K _0402_5%R5 45 200K _0402_5%

R546 10 K_0402_5%R546 10K _0402_5%

R577 10 K_0402_5%R577 10K _0402_5%

R550 10 K_0402_5%R550 10K _0402_5%

R551 10 0K_0402_5%R551 1 00K_0402_5%

R552 10 K_0402_5%

R553 10 K_0402_5%R553 10K _0402_5%

R555 10 K_0402_5%R555 10K _0402_5%

R437 10K_ 0402_5%

R547 10 0K_0402_5%R547 1 00K_0402_5%

R402 10K_ 0402_5%R402 1 0K_0402_5%

R405 10K_ 0402_5%

R328 47K_ 0402_5%R328 4 7K_0402_5%

GPIO28

On-Die PLL Voltage Regulator H: Enable

*

L: Disable

HDMI_HPD<15,19>

EC_SCI#<32>

EC_SMI#<3 2>

USB30_S MI#<30>

BT_ON#<2 7>

ODD_DET ECT#<25>

ISDBT_DET<27>

U2F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

COUGARP OINT_FCBGA989~D

GPIO

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

CPU/MISC

INIT3_3V#

NC_1

NC_2

NC_3

NC_4

NC_5

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

Q65R3@

PECI

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

ODD_EN#

PCH_W L_BT_LED

LOGO_LE D

MAXIC_SEL ECT

GATEA20

KB_RST#

H_PW RGOOD

PCH_THR MTRIP#

ODD_EN# <35>

LOGO_LE D <34>

GATEA20 <32>

KB_RST# <32 >

1 2

R416 390_0402_5%R4 16 390_040 2_5%

This signal has weak internal pull-up, can't be pulled low

H_PW RGOOD < 5>

H_THERM TRIP# <5>

ODD_EN#

GATEA20

KB_RST#

LOGO_LE D

PCH_W L_BT_LED

8/18 Remove PCH PECI by HW Review demand

MAXIC_SEL ECT

MAXIC_SELECT

IC TYPE MAX14550E

8/30 Add MAC IC select function for MAX14550E/14566B co-lay

H_THERM TRIP#

H_PW RGOOD

C896 220P_040 2_50V7K

1 2

@

C897 220P_040 2_50V7K

1 2

@

9/1 Reserve C896, C897 for ESD requset

1 2

R106 10 K_0402_5%R106 10K _0402_5%

1 2

R548 10 K_0402_5%R548 10K _0402_5%

1 2

R559 10 K_0402_5%R559 10K _0402_5%

1 2

R436 10 K_0402_5%R436 10K _0402_5%

1 2

R110 10 K_0402_5%R110 10K _0402_5%

WL_B T_LED#<34>

PCH_W L_BT_LED

2N7002D W-T/R7_SOT3 63-6

14550@

1 2

R444 10 K_0402_5%

1 2

R124 10 K_0402_5%14566@R 124 10K_0402 _5%1456 6@

H L

MAX14566B

GPIO8

Integrated Clock Chip Enable (Removed) H: Disable L: Enable

*

R326 1K _0402_5%@R326 1K _0402_5%@

1 2

A A

Integrated clock enable functionality is achieved by soft-strap The current default is clock enable

5

EC_SMI#

OPTIMUS_EN#

SKU Discrete

4

H L

Optimus

Security Class ification

2010/09/ 03 2012/12/ 31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/ 03 2012/12/ 31

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document N umber Rev

B

Date: Sheet of

Compal Electronics, Inc.

PCH_CPU/GPIO

PHQAA LA-6832P M/B

21 45Monday, Sep tember 06, 2010

1

0.1

5

4

3

2

1

12

L1

R480

0_0805_5%

1 2

+3VS

+1.5VS

+1.05VS_VCCP

+1.8VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_SUS

VCC3_3

VCCADAC

VCCADPLLA

VCCADPLLB

VCCCORE

VCCDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

5

0.001

0.266

0.001

0.08

1.3

0.042

1.05VCCIO 2.925

1.05VCCASW 1.01

3.3VCCSPI 0.02

3.3VCCDSW 0.00 2

1.8 0.19VCCDFTERM

3.3VCCRTC 6 uA

3.3VCCSUS3_3

3.3 / 1.5VCCSusHDA

0.97

0.01

VCCVRM 1.5 0.16

1.05VCCCLKDMI

VCCSSC 1.05

VCCDIFFCLKN 1.05

VCCALVDS 3.3

0.02

0.095

0.055

0.001

1.8VCCTX_LVDS 0.06

POWER

2925mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

20mA

VCCDFTERM

190mA

NAND / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCIO[1]

VCCPNAND[1]

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

VCCSPI

Q65R3@

U48

U47

AK36

AK37

AM37

AM38

AP36

0.01U_0402_25V7K

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

0.01U_0402_25V7K

+VCCA_LVDS

+VCCTX_LVDS

C514

1

C272

0.1U_0402_10V7K

2

+VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS_VCC_DMI

1

C278

0.1U_0402_10V7K

2

1

C281

C281 1U_0402_6.3V6K

1U_0402_6.3V6K

2

C512

0.01U_0402_25V7K

+VCCP_VCCDMI

1

C270

C270 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VS

0.1U_0402_10V7K

1

C288

2

1 2

R541 0_0603_5%R541 0_06 03_5%

C513

+3VS

+VCCAFDI_VRM

R477

0_0805_5%

1 2

+1.8VS

BLM18PG181SN1D_0603

1

C286

C286 10U_0603_6.3V6M

10U_0603_6.3V6M

2

0.1UH_MLF1608DR10KT_10%_1608

1

C256

C256 22U_0805_6.3V6M

22U_0805_6.3V6M

2

+1.05VS_PCH

L12

+3VS

1 2

R474

0_0603_5%

1 2

1

C276

C276 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCP

D D

C C

This pin can be left as NC if O

n-Die VR is enabled (Default)

+1.05VS_PCH

R483 0_0603_5%

B B

PJ31

@PJ31

@

2

112

JUMP_43X118

10U_0603_6.3V6M

This pin can be left as NC if On-Die VR is enabled (Default)

+1.05VS_PCH

C277

10U_0603_6.3V6M

@

12

1U_0402_6.3V6K

1

C269

C274

2

1U_0402_6.3V6K

L22

@ L22

@

1 2

1UH_LB2012T1R0M_20%

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C280

1

2

@

C273

2

1U_0402_6.3V6K

1

2

C279

+3VS

1U_0402_6.3V6K

1

C275

2

C509

@

1

C510

2

1U_0402_6.3V6K

1

C289

2

1U_0402_6.3V6K

+1.05VS_PCH

+VCCAPLLEXP

1

2

1

C511

1U_0402_6.3V6K

2

1

C290

0.1U_0402_10V7K

2

+1.05VS_VCCAPLL_FDI

+1.05VS_PCH

+VCCP_VCCDMI

+1.05VS_PCH +VC CA_DAC

1

2

1

2

+VCCAFDI_VRM

U2G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VCCFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

COUGARPOINT_FCBGA989~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-1

PHQAA LA-6832P M/B

22 45Monday, September 06, 2010

1

0.1

of

5

+3VS

L18

1 2

10UH_LB2012T100MR_20%

D D

+3VS_VCC_CLKF33

1

C301

C301 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C310

C310 1U_0402_6.3V6K

1U_0402_6.3V6K

2

This pin can be left as NC if On-Die VR is enabled (Default)

+1.05VS_PCH

"@" Avoid leakage

This pin can be left as NC if On-Die VR is enabled (Default)

+1.05VS_PCH

C C

+1.05VS_PCH

B B

+1.05VS_PCH

A A

R522

0_0603_5%

R485

0_0603_5%

R521

0_0603_5%

@R521

@

12

1

2

1

2

1

C316

C316 1U_0402_6.3V6K

1U_0402_6.3V6K

2

L20

@L20

@

1 2

10UH_LB2012T100MR_20%

220U_B2_2.5VM_R15

C337

C337 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS_VCCDIFFCLKN

C320

C320 1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

L21

1 2

L19

1 2

C333

+VCCDIFFCLK

+1.05VM_VCCSUS

C302

+1.05VS_VCCDIFFCLKN

@

1

+

2

1

2

+1.05VS_VCCADPLLA

1

C295

1U_0402_6.3V6K

2

+1.05VS_VCCP

1U_0402_6.3V6K

+1.05VS_VCCADPLLB

1

+

C515

2

220U_B2_2.5VM_R15

0.1U_0402_10V7K

+1.05VS_PCH

1U_0402_6.3V6K

R511

1 2

0_0603_5%

C325

4.7U_0603_6.3V6K

+1.05VS_PCH

C318

0.1U_0402_10V7K

1

2

R498

0_0603_5%

+3VALW

C305

0.1U_0402_10V7K

+1.05VS_PCH

1

C323

2

1

C298

C298 1U_0402_6.3V6K

1U_0402_6.3V6K

2

C334

1

2

1

C303

C322

0.1U_0402_10V7K

2

4

@

12

1

2

@

12

1

2

1

C311

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

C294

1U_0402_6.3V6K

2

+VCCRTCEXT

1

+VCCAFDI_VRM

2

+1.05VS_VCCADPLLA

+1.05VS_VCCADPLLB

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+VCCSST

1

0.1U_0402_10V7K

+1.05VM_VCCSUS

C299

2

1

+RTCVCC

2

C327

1U_0402_6.3V6K

+VCCACLK

C324

0.1U_0402_10V7K

+PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS

C300

C300 1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

C312

22U_0805_6.3V6M

2

1

C308

2

+V_CPU_IO

0.1U_0402_10V7K

1

C330

2

1

2

AD49

T16

V12

T38

BH23

AL29

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17 AF33 AF34

AG34

AG33

V16

T17 V19

BJ8

A22

1

C336

0.1U_0402_10V7K

2

POWER

1mA

1010mA

80mA

55mA

95mA

POWER

3mA

Clock and Miscellaneous

CPURTC

U2J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11]

VCCIO[10]

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

VCCRTC

COUGARPOINT_FCBGA989~D

3

119mA

1mA

PCI/GPIO/LPCMISC

SATA USB

10mA

HDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

Q65R3@

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

+1.05VS_PCH

+PCH_V5REF_SUS

+VCCA_USBSUS

+PCH_V5REF_RUN

1 2

C306

0.1U_0402_10V7K

+1.05VS_SATA3

+VCCSATAPLL

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCME_22

+VCCME_23

+VCCME_21

1

C307

0.1U_0402_16V4Z

2

+1.05VS_PCH

1

C328

C328 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VALW

1

C321

0.1U_0402_10V7K

2

1

2

+VCCAFDI_VRM

1

C332

0.1U_0402_10V7K

2

C335 1U_0402_6.3V6K

+3VALW

1

C293

C293 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VS

C297

0.1U_0402_10V7K

+1.05VS_VCC_SATA

1

C331

C331 1U_0402_6.3V6K

1U_0402_6.3V6K

2

R509 0_0603_5%R5 09 0_060 3_5%

R517 0_0603_5%R5 17 0_060 3_5%

R520 0_0603_5%R5 20 0_060 3_5%

+3VALW

@

1 2

+3VS

1

C313

0.1U_0402_10V7K

2

+1.05VS_SATA3

1

C329

C329 1U_0402_6.3V6K

1U_0402_6.3V6K

2

0_0805_5%

12

R491

2

R516

0_0805_5%

+1.05VS_PCH

12

+1.05VS_PCH

12

This pin can be left as NC if On-Die VR is enabled (Default)

L17

@L17

@

1 2

10UH_LB2012T100MR_20%

1

C296

C296 10U_0603_6.3V6M

10U_0603_6.3V6M

@

2

R512

100_0402_5%

+1.05VS_PCH

+5VALW + 3VALW

12

+5VS +3VS

12

R490

1

21

D8

CH751H-40PT_SOD323-2

+PCH_V5REF_SUS

1

C326

0.1U_0603_25V7K

2

21

D7

CH751H-40PT_SOD323-2

+PCH_V5REF_RUN

1

C304

C304 1U_0603_10V6K

1U_0603_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-2

PHQAA LA-6832P M/B

1

23 45Mon day, September 06, 2010

0.1

of

5

U2H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

D D

C C

B B

A A

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

COUGARPOINT_FCBG A989~D

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

Q65R3@

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

3

U2I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

COUGARPOINT_FCBG A989~D

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

Q65R3@

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH_GND

PHQAA LA-6832P M/B

24 45Monday, September 06, 2010

1

0.1

5

SATA HDD Conn.

D D

C C

+5VS

1

2

JHDD

24

GND

23

GND

SANTA_191201-1

Place closely JHDD SATA CONN.

1.2A

C356

C356 10U_0805_10V4Z

10U_0805_10V4Z

GND

GND GND GND

GND

Reserved

GND

1

C357

0.1U_0402_16V4Z

2

1

SATA_PTX_C_DRX_P0

2

A+

A-

B-

B+

V33 V33 V33

V5 V5 V5

V12 V12 V12

3 4 5 6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

1

C358

0.1U_0402_16V4Z

2

Close to JHDD

C369 0.01U_0402_25V7KC369 0.01U_0402_25V7K

1 2

C367 0.01U_0402_25V7KC367 0.01U_0402_25V7K

1 2

C368 0.01U_0402_25V7KC368 0.01U_0402_25V7K

1 2

C370 0.01U_0402_25V7KC370 0.01U_0402_25V7K

1 2

+3VS

+5VS

1

C359

0.1U_0402_16V4Z

2

4

SATA_PTX_DRX_P0 <16> SATA_PTX_DRX_N0 <16>

SATA_PRX_C_DTX_N0 <16>

SATA_PRX_C_DTX_P0 <16>

3

SATA ODD Conn

JODD

15

GND

14

GND

SANTA_206401-1_RV

GND

GND GND

@JODD

@

1

SATA_PTX_C_DRX_P2

2

A+

A-

B-

B+

DP +5V +5V

MD

3 4 5 6 7

8 9 10 11 12 13

SATA_PTX_C_DRX_N2

SATA_PRX_DTX_N2 SATA_PRX_DTX_P2

ODD_DETECT#_R

+5VS_ODD

ODD_DA#_R

USB Board@ Right Side

W=60mils

VOUT VOUT

FLG

+USB_VCCA

8

C361 1000P_0402_50V7KC 361 1000P_0402_50V7K

7 6 5

1

C362

4.7U_0805_10V4Z

2

@

USB_EN#

+5VALW

2.5A

U14

1

GND

2

VIN VIN3VOUT

4

EN

RT9715BGS_SO8

Close to JODD

C378 0.01U_0402_25V7K C378 0.01U_0402_25V 7K

1 2

C377 0.01U_0402_25V7KC377 0.01U_0402_25V7K

1 2

C376 0.01U_0402_25V7KC376 0.01U_0402_25V7K

1 2

C375 0.01U_0402_25V7KC375 0.01U_0402_25V7K

1 2

R561 0_0402_5%R561 0_0402_5%

1 2

R562 0_0402_5%R562 0_0402_5%

For EMI

12

USB_OC#0 <20,32>

ODD_DETECT# <21>

ODD_DA# <20>

USB20_P0<20>

USB20_N0<20>

USB20_P1<20>

USB20_N1<20>

2

SATA_PTX_DRX_P2 <16>

SATA_PTX_DRX_N2 <16>

SATA_PRX_C_DTX_N2 <16> SATA_PRX_C_DTX_P2 <16>

R73 0_0402_5%

@

1 2

L53

1

2

4

WCM-2012-900T_0805

R87 0_0402_5%

R77 0_0402_5%

L54

1

4

WCM-2012-900T_0805

R88 0_0402_5%

4

@

1 2

@

1 2

1

4

@

1 2

3

2

3

SW5

SW5 SMT1-05-A_4P

ODD_DA#_R

+5VS_ODD

1.1A

1

C352

10U_0805_10V4Z

2

USB20_P0_R

2

USB20_N0_R

3

USB20_P1_R

2

USB20_N1_R

3

8/20 Swap USB20_P0, USB20_N0, USB20_P1, USB20_N1 for layout request

SMT1-05-A_4P

1

2

3

4

5

6

Place components closely ODD CONN.

1

C353

10U_0805_10V4Z

2

+5VL

+5VALW

1

2

1 2

R149 0_0402_5%R149 0_0402_5%

@

1 2

R148 0_0402_5%

NBA_PLUG<31>

BACK_SENSE<31>

@

C354

C354 1U_0402_6.3V6K

1U_0402_6.3V6K

HP_R<31>

HP_L<31>

MIC1_L<3 1>

MIC1_R<31>

1

2

+5V_IO USB20_N1_R USB20_P1_R

USB20_N0_R USB20_P0_R

C355

0.1U_0402_16V4Z

W=60mils

+USB_VCCA

1

C360

0.1U_0402_16V4Z

2

JPIO

@JPIO

@

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_85201-2005N

USB Board@ Left Side

Q8

D

S

D

S

+USB_VCCC +USB_VCCB

1 2

+5VALW

R568 100K_0402_5%R 568 100K_0402_5%

B B

USB_EN#<32>

USB_EN#

8/30 Chang e C426 to Aluminum Solid Cap 220u for cost down

R190 0_0402 _5%

L15

USB20_N2<20>

USB20_P2<20>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

2

3

2

WCM-2012-900T_0805

R189 0_0402 _5%

USB20_N2_R

USB20_P2_R

Title

Size Document Number Rev

Date: Sheet of

1 3

AO3413_SOT23

G

2

+USB_VCCC

W=60mils

@

12

4

USB20_N2_R USB20_P2_R

1

@

12

D23

@D23

@

2

3

PJDLC05C_SOT23-3

Compal Electronics, Inc.

SATA-HDD/ODD/USB

PHQAA LA-6832P M/B

C426 220U_6.3V_M _R15

1 2

+

C428 1000P_0402_50V7KC428 1000P_0402_50V7K

1 2

C389 0.1U_0402_16V4ZC 389 0.1U_0402_16V4Z

1 2

JUSB

@JUSB

@

VCC DD+ GND

GND GND GND GND

5 6 7 8

25 45Monday, September 06, 2010

1 2 3 4

ALLTOP C107L8-10405-L

1

0.1

5

Screw cap for ESD request

4

3

2

1

D D

B+

@

C236

@

1

2

1

C268

C489

2

0.1U_0402_25V6

@

1

2

1

C490

2

0.1U_0402_25V6

For EMI

C C

B-CAS Circuit

TV@

1

CB1

0.1U_040 2_16V7K

2

G

2

1

2

12

RB8

+5VS

Inrush current = 0A

S

QB1

QB1 AO3413_ SOT23

AO3413_ SOT23

TV@

D

1 3

+5VS_L_ BCAS

1

CB3

TV@CB3

TV@

4.7U_060 3_6.3V6K

2

+5VS_BC AS +5VS_L_ BCAS

1

CB4

TV@

0.1U_040 2_16V4Z

1

CB5

2

LB1

TV@LB1

TV@

1 2

FBMA-L11 -201209-221LMA 30T_0805

TV@

1U_0402 _6.3V6K

2N7002D W-T/R7_SOT3 63-6

BCPW ON<27>

100K_04 02_5%

BCPW ON

RB7

TV@ RB7

TV@

10K_040 2_5%

RB2

TV@RB2

TV@

5

12

+5VALW

12

3

4

RB5

47K_040 2_5%

TV@

QB2B

TV@

12

TV@

CB2

0.01U_04 02_25V7K

TV@ RB8

TV@

2.2K_040 2_5%

Felica

FELICA_PW R<16>

+5VS

R419

R419 100K_04 02_5%

100K_04 02_5%

FELICA@

1 2

R403 47K_ 0402_5%

13

D

0.01U_04 02_25V7K

S

FELICA@

0.01U_04 02_25V7K

2

G

Q34 2N7002_SOT 23-3

FELICA@

C479

0.1U_040 2_16V7K

FELICA@

C403

FELICA@

2

1

2

1

G

+5VS

1 3

FELICA@

C414

0.1U_040 2_16V4Z

S

Q20

Q20 AO3413_ SOT23

AO3413_ SOT23

D

FELICA@

+FLICA_VC C

C758

0.1U_040 2_16V4Z

FELICA@

JFEL

@JFEL

@

1

2

3

4

5

6

7

G1

8

G2

ACES_87 151-06051

R132

0_0603_ 5%

FELICA@

USB20_N 13 USB20_P 13 FELICA_GN D

12

1

2

USB20_N 13<20> USB20_P 13<20>

B B

BCRSTM<27>

XBCLKM< 27>

A A

+5VS_L_ BCAS

CPLGP1<2 7>

CPLGP1

2N7002D W-T/R7_SOT3 63-6

5

BCRSTM

XBCLKM

RB1

TV@RB1

TV@

1 2

10K_040 2_5%

QB2A

TV@

+5VS_L_ BCAS

5

1

IN1

2

IN2

SN74AHC 1G08DCKR_SC7 0-5

3

5

1

IN1

2

IN2

SN74AHC 1G08DCKR_SC7 0-5

3

RB13 10K_040 2_5%

10K_040 2_5%

61

2

UB1

TV@UB1

TV@

P

B_R_BCR ST

4

O

G

UB2

TV@UB2

TV@

P

B_R_XBC CLK

4

O

G

12

2

B

TV@RB13

TV@

1 2

RB9 10 0_0402_5%

1 2

RB11 100_ 0402_5%

+5VS_L_ BCAS

1 2

RB12

31

E

10K_040 2_5%

QB4

QB4 2SB1197 K_SOT23-3

2SB1197 K_SOT23-3

C

1 2

RB14

1.5K_040 2_5%

TV@

TV@RB12

TV@

TV@RB14

TV@

B_BCRST

B_XBCCL K

4

B_BCRST <27>

B_XBCCL K <27>

BCIO

BCIO < 27>

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Finger printer

R134

1 2

+3VS

2010/09/ 03 2012/12/ 31

3

0_0603_ 5%

1

FP@

C480

0.1U_040 2_16V4Z

FP@

2

Compal Secret Data

Deciphered Date

USB20_N 8<20> USB20_P 8<20>

CM1293A -02SR SOT143-4

2

D82

4

VIN

3

IO2

For ESD

JFP

@JFP

+3VS_FP USB20_N 8 USB20_P 8

FP_GND

12

R133

R133 0_0603_ 5%

FP@D82

FP@

IO1

GND

2

1

0_0603_ 5%

FP@

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

IR/FP/B-CAS/Felica

@

1

2

3

4

5

GND

6

GND

P-TWO _161011-04021

PHQAA LA-6832P M/B

1

0.1

of

26 45Monday, Sep tember 06, 2010

Slot 1 Half PCIe Mini Card-WLAN/ WiMax

+3VALW

+3V_WLAN

0.1U_0402_16V4Z

1

CM1

CM2

2

0.01U_0402_25V7K

CLKREQ_WLAN#< 17>

CLK_WLAN#<17> CLK_WLAN< 17>

PCIE_PRX_WLANTX_N2<17> PCIE_PRX_WLANTX_P2<1 7>

PCIE_PTX_C_WLANRX_N2<17> PCIE_PTX_C_WLANRX_P2<17>

E51_TXD<32> E51_RXD<32>

Debug card using

2

112

PJ27 JUMP_43X79@PJ27 JUMP_43X79@

2

+3VS

PJ26 JUMP_43X79@PJ26 JUMP_43X79@

112

Short PJ27 for Wimax Short PJ26 for WLAN

40 mils

For SED For SED

1

12

C253

CM7

CM3

2

4.7U_0805_10V4Z

R1443

0_0402_5%

1 2

+3V_WLAN

R16

R16 0_0402_5%

0_0402_5%

1 2 1 2

0_0402_5%

0_0402_5% R17

R17

47P_0402_50V8J

@

BT_CTRL_RBT_CTRL

E51_RXD_R

CM7

0.01U_0402_25V7K

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

+3V_WLAN

+1.5VS

0.1U_0402_16V4Z

1

CM8

2

4.7U_0805_10V4Z

JWLAN

@JWLAN

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

GND2

@

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

1 3 5 7 9

FOX_AS0B226-S40N-7F

CM9

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

WLAN&BT Combo module circuits

BT on module

Enable Disable

H L

L H

D24

R327

1 2

1K_0402_5%

21

CH751H-40PT_SOD323-2

BT_ON#<21>

WL_OFF# <20>

PLT_RST# <5,20,28,2 9,30,32,33>

WiMaxWLAN/ WiFi

LED_WIMAX# <34>

+3VS

1

47P_0402_50V8J

2

+1.5VS

BT_CRTL

BT_ON#

**If +3V_WLAN is +3VS, please remove D24

SUSP#<16,32,35,40,42>

12

C254

@

+3V_WLAN

BT_CTRL E51_RXD_R

For isolate Intel Rainbow Peak and Compal Debug Card.

PLT_RST#

PM_SMBCLK <11,12 ,17> PM_SMBDATA <11,12,1 7>

USB20_N9 <20> USB20_P9 <20>

LED_WIMAX#

1 2

RM6 100 K_0402_5%

WIMAX@

8/30 Reserve R1443 for WLAN Mini PCIE Card Pin5

2

G

BT on module

13

D

Q36

2N7002_SOT23-3

S

BT_CTRL

Slot 2 Full PCIe Mini Card- 3G/ TV Tuner Half PCIe Mini Card- JET

J3G

@J3G

PCIE--JET B-CAS

XBCLKM<26>

CLKREQ_JET#<17>

BCRSTM<26> BCPWON<26>

PCIE_PRX_JETTX_N3<17> PCIE_PRX_JETTX_P3<17>

PCIE_PTX_C_JETRX_N3<17> PCIE_PTX_C_JETRX_P3<17>

TMPTU2_SXP<32>

Add BCCDET pull down

BCCDET

0.1U_0402_16V4Z

TV@

1 2

R307 470_0402_5%

1

CM13

3G@

2

CLK_JET#<17> CLK_JET<17>

BCCDET

12

+3VS

DM1

RLZ20A_LL34

3G@

+VCC_SIM SIM_RESET SIM_CLK

CM15

10P_0402_50V8J

3G@

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

FOX_AS0B226-S40N-7F

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

1

2

@

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

GND2

1

CM16

CM16 10P_0402_50V8J

10P_0402_50V8J

2

3G@

+1.5VS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

+3VS

2.75A

UIM_DATA UIM_CLK UIM_RESET COMMON ISDBT_DET RF_OFF# PLT_RST#

USB20_P10_TV USB20_N10_TV

R72 0 _0402_5%3G@R72 0_0402_5%3G @ R85 0 _0402_5%3G@R85 0_0402_5%3G @

LED_WIMAX# CPLGP1

J3GSIM

1

VCC

2

RST

3

CLK

7

NC

MOLEX_47273-0001~ D

1 2 1 2

CPLGP1 <26> TMPTU1_SXP <32 >

B-CAS

@J3GSIM

@

GND

VPP

I/O

NC

+UIM_PWR

ISDBT_DET <21>

RF_OFF# < 20>

R126 0_0402_5 %TV@R126 0_0402_5%TV@

1 2 1 2

R135

USB20_N12 <20> USB20_P12 <20>

4 5 6

8

UIM_VPP SIM_DATA

TV@

0_0402_5%

PM_SMBCLK PM_SMBDATA

USB--3G/TV#1

+UIM_PWR

12

RM2

4.7K_0402_5%

@

1

CM14

CM14 22P_0402_50V8J

22P_0402_50V8J

@

2

+3VS

CM4

0.01U_0402_25V7K

USB--TV#2

USB20_P10 <20> USB20_N10 <20>

120 mils

0.1U_0402_16V4Z

1

CM5

2

4.7U_0805_10V4Z

COMMON

+5VS_BCAS

+UIM_PWR

B_BCRST<26>

B_XBCCLK<26>

For SED

1

CM6

12

C255

C255 47P_0402_50V8J

47P_0402_50V8J

@

2

RM3 0_0 402_5%

3G@

1 2

TV@

1 2

RM7 0_0 402_5%

UIM_VPP

BCIO

Close to J3G

TV@

1 2

RM4 0_0 603_5%

3G@

1 2

RM1 0_0 603_5%

3G@

UIM_RESET SIM _RESET

B_BCRST

UIM_CLK SIM_CLK

B_XBCCLK

UIM_DATA SIM_DATA

BCIO

3G@

1 2

RM5 0_ 0402_5%

TV@

1 2

RM8 0_ 0402_5%

3G@

1 2

RM9 0_ 0402_5%

TV@

1 2

RM10 0_0402_5%

3G@

1 2

RM11 0_0402_5%

TV@

1 2

RM12 0_0402_5%

BCIO <26>

+VCC_SIM

USB Sleep & Charge Auto-Mode Mode3/Mode4

+5VALW +USB_VCCB

USB_CHG_EN#<30,32>

2.5A

U15

1

GND

2

VIN VIN3VOUT

4

EN

RT9715BGS_SO8

VOUT VOUT

TDM

TDP VCC

MAX14566E

CB: SLP_CHG#

STATUS

0 AUTO MODE

1

14566@

R1444

0_0402_5%

1 2

0_0402_5%

0_0402_5% R1445

R1445

@

U2D_DN1 U2D_DP1USB20_DP1_R

@

1

C892

0.1U_0402_16V7K

14566@

2

8

CB

7 6 5

Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM

SLP_CHG_M4

U2D_DN1 <30> U2D_DP1 <30>

+5VALW

SLP_CHG# <32>

SLP_CHG_M4<20>

MAX14566B

CB0 SLP_CHG#

0

0 1

1 X

W=60mils

8 7 6 5

FLG

1

C383

4.7U_0805_10V4Z

@

2

USB_OC#1 <20,30,32>

SLP_CHG_M3<20>

CB1 (CEN#) SLP_CHG_M3

SLP_CHG_M3

USB20_DN1_R<30>

USB20_DP1_R<30>

STATUS

0

AUTO MODE

Force Dedicated charger mode (MODE3)

Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM

14566@

R1441

R1441 0_0402_5%

0_0402_5%

1 2

USB20_DN1_R

MAX14566EETA+_TDFN-EP8_2X2~D

1 2 3 4 9

U5

CEN DM DP GND GND

14566@

9/2 Change U5 Pin8 control pin from SLP_CHG# to SLP_CHG_M4

9/2 Add 14566@ & 14550@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

MAX14550E

CB0 SLP_CHG_M4

0

0 1

1 1

SLP_CHG_M4 USB20_DP1_R USB20_DN1_R

CB1 SLP_CHG_M4

0

U57

1

CB0

2 3 4

11

CB1

DP

TDP

DM

TDM

GND

VCC RDP5RDM GND

MAX14550EETB-T_TDFN10

14550@

8/30 Add MAX14550E

STATUS

AUTO MODE

MODE3

MODE41 0

Pass-Through (USB) Mode: Connect DP/DM to TDP/TDM

SLP_CHG_M3

10

U2D_DP1

9

U2D_DN1

8 7 6

Title

Size Document Number Rev

Date: Sheet of

+5VALW

1

C893

0.1U_0402_16V7K

14550@

2

Compal Electronics, Inc.

PCIe-WLAN/JET/3G/TV/NewCard

PHQAA LA-6832P M/B

Monday, September 06, 201 0

27 45

0.1

A

CL1 0.1U_0402_16V7KCL1 0.1U_0402_16V7K

PCIE_PRX_C_LANTX_P1<17>

PCIE_PRX_C_LANTX_N1<17>

1 1

+3V_LAN

RL24 10K_0402_5%@RL24 10K_0402_5%@

RL25 10K_0402_5%@RL25 10K_0402_5%@

12

RTL8105E

Pin14

+3VS

Pin15

Pin38

12

1K_0402_5%

1K_0402_5% RL6

RL6

@

RL7

15K_0402_5%

2 2

1 2

RL433 0_ 0402_5%RL433 0_0402_5%

WOL_EN

CLKREQ_LAN#

EC_SWI#

RTL8111E

NC

NC 10K o hm PD

1K ohm Pull-high

WOL_ENISOLATE#

Sx Enable Wake up

LOW

1 2

CL2 0.1U_0402_16V7KCL2 0.1U_0402_16V7K

1 2

PCIE_PTX_C_LANRX_P1<17>

PCIE_PTX_C_LANRX_N1<17>

CLKREQ_LAN#<17>

Sx Disable Wake up

+3V_LAN

PLT_RST#<5,20,27,29,30,32,33>

CLK_LAN<17> CLK_LAN#<17>

EC_SWI#<18,30>

S0

HIGH HI GH

CLKREQ_LAN#

PCIE_PRX_LANTX_P1

PCIE_PRX_LANTX_N1

PCIE_PTX_C_LANRX_P1 PCIE_PTX_C_LANRX_N1

RL19 0_0402_5%RL19 0_04 02_5%

PLT_RST#

CLK_LAN CLK_LAN#

LAN_X1

LAN_X2

EC_SWI#

ISOLATE#

RL21 10K_0402_5%8111E@RL21 10K_0402_5%8111E@ RL22 1K_0402_5%RL22 1K_0402_5%

+LAN_VDDREG

12

1 2

ENSWREG

1 2

RL5 2.49K_0402_1%RL5 2.49K_0402_1%

+3VALW TO +3V_LAN

@

2

AO3413_SOT23

CL681

+3VALW

Vgs=-4.5V,Id=3A, Rds<97mohm

2

S

QL51

G

@

2

1

D

1 3

1

2

+3VALW

12

RL147

RL147 100K_0402_5%

100K_0402_5%

@

RL432

@RL432

@

WOL_EN<32>

3 3

1 2

47K_0402_5%

2

CL483

@

0.1U_0402_16V7K

1

2

@

CL482

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

For P/N and footprint P

lease place them to ISPD page

UL1

8105E-VC 10/100M

8105ELDO@

UL4

10/100M transformer

4 4

8105ELDO@

UL1

8105E-VC 10/100M

8105ESWR@

UL4

10/100M transformer

8105ESWR@

PJ29

PJ29 JUMP_43X79

JUMP_43X79

@

2

1

LAN_MDI3LAN_MDI3+

LAN_MDI2LAN_MDI2+

LAN_MDI1LAN_MDI1+

LAN_MDI0LAN_MDI0+

B

22

23

17 18

12

16

25

19 20

43

44

28

26

14 15 38

33

34 35

46

24 49

+3V_LAN

CL682

CL682 1U_0402_6.3V6K

1U_0402_6.3V6K

@

Place CL34 colse to LAN chip

UL1

HSOP

HSON

HSIP HSIN

CLKREQB

PERSTB

REFCLK_P REFCLK_N

CKXTAL1

CKXTAL2

LANWAKEB

ISOLATEB

NC/SMBCLK NC/SMBDATA GPO/SMBALERT

ENSWREG

VDDREG VDDREG

RSET

GND PGND

RTL8111E-GR_QFN48_6X6

8111E@

LED3/EEDO LED1/EESK

FOR EMI ISN TEST DEMAND.

8/30 Add UL3 at DVT

LAN_MDI0+ LAN_MDI0-

LAN_MDI1+ LAN_MDI1-

1

CL34

0.1U_0402_25V4K

2

31 37 40

LED0

30

EECS/SCL

32

EEDI/SDA

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

7

NC/MDIP2

8

NC/MDIN2

10

NC/MDIP3

11

NC/MDIN3

13

DVDD10

29

DVDD10

41

DVDD10

27

DVDD33

39

DVDD33

12

AVDD33

42

AVDD33

47

AVDD33

48

AVDD33

21

EVDD10

3

AVDD10

6

AVDD10

9

AVDD10

45

AVDD10

36

REGOUT

+3V_LAN

CL683

220U_6.3V_M_R16

UL3

1 2 3 4 5 6 7

X'FORM_ NS681680

UL4

1 2 3

4 5

7 8 9

10 11 12

SUPERWORLD_SW G150401

8111E@

RL2 10K_0402_5%RL2 10K_0402_5% RL1 10K_0402_5%RL1 10K_0402_5%

@

8105ELDO@UL3

8105ELDO@

TD+ TDCT NC NC CT RD+ RD-8RX-

TCT1 TD1+ TD1-

TCT2 TD2+ TD2-6MX2-

TCT3 TD3+ TD3-

TCT4 TD4+ TD4-

LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3-

+LAN_VDD10

+3V_LAN

+LAN_EVDD10

+LAN_VDD10

+LAN_REGOUT

60 mils

1

+

2

TX+

TX-

CT NC NC CT

RX+

MCT1

MX1+

MX1-

MCT2

MX2+

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

12 12

1

CL684

CL684 10U_0805_10V6K

10U_0805_10V6K

@

2

RJ45_MIDI0+

16

RJ45_MIDI0-

15 14 13 12 11

RJ45_MIDI1+

10

RJ45_MIDI1-

9

24 23 22

21 20 19

18 17 16

15 14 13

C

+LAN_REGOUT

2.2UH +-5% NLC252018T-2R2J-N

Layout Note: LL1 must be within 200mil to Pin36, CL13,CL9 must be within 200mil to LL1

LL1

2.2UH +-5% NLC252018T-2R2J-N

8105ESWR@

+3V_LAN

LL3

LL3 0_0603_5%

0_0603_5%

8105ESWR@

CL39 1000P_0402_50V7K

12

8111E@

CL40 1000P_0402_50V7K

8111E@

CL41 1000P_0402_50V7KCL41 1000P _0402_50V7K

CL42 1000P_0402_50V7KCL42 1000P _0402_50V7K

1 2

RL11 75_0402_1%

1 2

12

RL12 75_0402_1%

1 2

12

RL13 75_0402_1%RL13 75_0402_1%

1 2

12

RL15 75_0402_1%RL15 75_0402_1%

LL1

8111E@LL1

8111E@

1 2

4.7U_0603_6.3V6K

1 2

LL2 0_0603_5%LL2 0_0603_5%

1U_0402_6.3V6K

1 2

LL3 0_0603_5%8111E@ LL3 0_0 603_5%8111E@

4.7U_0603_6.3V6K

CL28

4.7U_0603_6.3V6K

8105ESWR@

YL1

1 2

25MHZ_20PF_7A25000012

1

CL26

CL26 27P_0402_50V8J

27P_0402_50V8J

2

8111E@

1

CL13

2

8111E@

CL13

4.7U_0603_6.3V6K

8105ESWR@

+LAN_EVDD10+LAN_VDD10

1

CL17

CL18

CL17

2

Close to Pin 21

+LAN_VDDREG

1

CL28

2

8111E@

CL29

0.1U_0402_16V4Z

8105ESWR@

LAN_X2LA N_X1

1

CL27

CL27 27P_0402_50V8J

27P_0402_50V8J

2

D

+LAN_VDD10

1

CL9

0.1U_0402_16V4Z

2

8111E@

CL9

0.1U_0402_16V4Z

8105ESWR@

0.1U_0402_16V4Z

1

CL29

0.1U_0402_16V4Z

2

8111E@

ENSWREG

+3V_LAN

+LAN_VDD10

+3V_LAN

CL3 to CL6 close to Pin 27,39,47,48

L7 to CL8 close to Pin 12,42

C

1 2

CL3 0.1U_0402_16V4ZCL3 0.1U _0402_16V4Z

1 2

CL4 0.1U_0402_16V4ZCL4 0.1U _0402_16V4Z

1 2

CL5 0.1U_0402_16V4ZCL5 0.1U _0402_16V4Z

1 2

CL6 0.1U_0402_16V4ZCL6 0.1U _0402_16V4Z

1 2

CL7 0.1U_0402_16V4Z8111E@ C L7 0.1U_0402_16V4Z8111E@

1 2

CL8 0.1U_0402_16V4Z8111E@ C L8 0.1U_0402_16V4Z8111E@

CL19, CL20,CL21 close to pin 13,29,45, respectively C

L22 close to pin 3, respectively

CL23,CL24,CL25 close to pin 6,9,41, respectively

1 2

CL19 0.1U_0402_16V4 ZC L19 0.1U_0402_16V4Z

1 2

CL20 0.1U_0402_16V4 ZC L20 0.1U_0402_16V4Z

1 2

CL21 0.1U_0402_16V4 ZC L21 0.1U_0402_16V4Z

1 2

CL22 0.1U_0402_16V4 Z8111E@ CL22 0.1U_0402_ 16V4Z8111E@

1 2

CL23 0.1U_0402_16V4 Z8111E@ CL23 0.1U_0402_ 16V4Z8111E@

1 2

CL24 0.1U_0402_16V4 Z8111E@ CL24 0.1U_0402_ 16V4Z8111E@

1 2

CL25 0.1U_0402_16V4 Z8111E@ CL25 0.1U_0402_ 16V4Z8111E@

12

RL4

RL4 0_0402_5%

0_0402_5%

8111E@

12

RL23

RL23 0_0402_5%

0_0402_5%

8105ELDO@

E

RTL8105E-VC RTL8111E-VB PWM Mode

0 ohm

RL4

(Pull High)

NC 0 ohm

RL23

RL4

RL4 0_0402_5%

0_0402_5%

8105ESWR@

LAN Conn.

JLAN

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

RJ45_GND LANGND

RJ45_MIDI0-

RJ45_MIDI0+

1 2

CL36 1000P_1808_3 KV7KCL36 1000P_1808_3KV7K

LL5

1 2

MCK3225201YZF_2P

JLAN

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130451-D

@

AZ5125-02S.R7G_SOT23-3

SHLD1

SHLD2

AZ5125-02S.R7G_SOT23-3

8/30 Reserve DL1 and DL2 for ESD request

1

CL38

4.7U_0603_6.3V6K

2

LAN_R_GND

1

CL37

0.1U_0402_16V4Z

2

RTL8105E-VC

LDO Mode

NC

(Pull Down)

DL1

@

3

9

10

2

DL2

@

1

2

3

1

9/1 Add LL 5 for ISN test by E MI demand

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCIe-LAN-RTL8105E/8111E

PHQAA LA-6832P M/B

E

0.1

28 45Monday, September 06, 2010

0.1

5

CC16 close to pin43

or internal LDO in SD3.0

D D

PCIE_PRX_C_CRTX_N4<17> PCIE_PRX_C_CRTX_P4<17>

PLT_RST#<5,20,27,28,30,32,33>

C C

+VCC_OUT

RC7 10K_0402_5%RC7 10K_0402_5%

RC9 1K_0402_5%RC9 1K_0402_5%

12

1 2

XDWP#_S DWP#

F

CLK_CR#<17> CLK_CR<17>

PCIE_PTX_C_CRRX_N4<17> PCIE_PTX_C_CRRX_P4<17>

CC8 0.1U_0402_16V7KCC8 0.1U_0402_16V7K

1 2

CC9 0.1U_0402_16V7KCC9 0.1U_0402_16V7K

1 2

RC4 100_0402_5%RC4 100_0402_5%

1 2

0.1U_0402_16V4Z

XD_RB#

4

CLK_CR# CLK_CR

PCIE_PTX_C_CRRX_N4 PCIE_PTX_C_CRRX_P4

PCIE_PRX_CRTX_N4 PCIE_PRX_CRTX_P4

RC3 12K _0402_1%RC3 12K_0402_1%

CC16 2.2U_0603_6.3V6KC C16 2.2U_0603_6. 3V6K

CC13

12

1

2

+VCC_OUT

APREXT

12mil

+SDV33_18

CPPE# XD_CD#

MS_CD# SD_CD#

40 mils

CR_LED

JMB389C

UC1

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

43

SDDV/MDIO4

39

TXIN/NC

JMB389

1

XRSTN

2

XTEST

13

CPPE_N

14

CR1_CD2N

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

JMB389-LGAZ0A_LQ FP48_7X7

APVDD

APV18

NC/TAV33

DV33 DV33 DV33 DV18 DV18

MDIO0 MDIO1 MDIO2 MDIO3

MDIO6/4

MDIO5

G/MDIO6

MDIO7 MDIO8

MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14

NC/SPI_SCK

NC/SPI_CSN

NC/SPI_SO

NC/SPI_SI

APGND NC/GND NC/GND NC/GND

3

+1.8VS_OUT

2

0mil

CC1

5 10 36

19 20 44 18 37

XD_SD_MS_D0

48

XD_SD_MS_D1

47

XD_SD_MS_D2

46

XD_SD_MS_D3

45

SDCMD_MSBS_XDW E#

41

SDCLK_MSCLK_XDCE #

42

XDWP#_S DWP#

24

XD_CLE

40

XD_SD_D4

29

XD_SD_D5

28

XD_SD_D6

27

XD_SD_D7

26

XD_RE#

25

XD_RB#

23

XD_ALE

22

30 33 34 35

6 31 32 38

CC3 close to pin 5 CC2 close to CC3 CC1 is near CC3

1

CC2

2

10U_0805_10V4Z

4

0mil

20mil

CC3

2

1000P_0402_50V7K

0.22U_0402_6.3V4K

+3VS

place near pin 19,20 and 44

1 2

CC5 0.1U_0402_16V 4ZCC5 0.1U_0402_16V4Z

1 2

CC6 0.1U_0402_16V4ZCC 6 0.1U_0402_16V4Z

1 2

CC7 0.1U_0402_16V4ZCC 7 0.1U_0402_16V4Z

CC10

0.22U_0402_6.3V4K

CC4 close to pin 10

2

0.1U_0402_16V4Z

+1.8VS_OUT

2

1

CC11 10U_0805_10V4ZCC11 10U_0805_10V4Z

1

CC11 close to pin18

2

For intenal LDO's usage

1

CC4

CC3

CC10 close to pin37

2

+3VS

2

CC12

0.1U_0402_16V4Z

1

CC12 close to pin 36

D3E mode

CR_CPPE#<16>

CR_WAK E#<16>

Power On Strapping setting

Pin name

MDIO7 add-in cardon-board

MDIO14

Vendor review to set @

CR_LED high active

XD_CLE

MDIO7

XD_ALE

MDIO14

High

Description

★

1 2

RC28 10K_0402_5 %@RC28 10K_0402_5%@

1 2

RC26 1K_0402_5%@RC26 1K_0402_5%@

1 2

RC25 200K_0402_5%@RC25 200K_0402_5%@

1

RC31 0_0402_5%RC31 0_0402_5%

1 2

RC6 0_0402_5%RC6 0_040 2_5%

1 2

low

CR_LED low active

CPPE#

SD_CD#

★

+3VS

Add RC24 and RC17 close to UC1 for xD issue

XDWE#SDCMD_MSBS_XDWE#

RC24 22_0402_5%RC 24 22_0402_5%

RC17 22_0402_5%RC 17 22_0402_5%

12

SDCMD_MSBS

5 in 1 Card Reader

B B

A A

SD_CD# XD_C D#

1

CC22

0.1U_0402_16V4Z

QC1

2N7002_SOT23-3

@

2

13

D

S

1

CC23

0.1U_0402_16V4Z

@

2

CR_LEDCON#

RC8 0_0402_5%RC8 0_0402_5%

2

G

RC10

4.7K_0402_5%

@

1 2

5

10U_0805_10V4Z

CR_LEDCON# <34>

12

CR_LED

Confirm sinking 16mA

+VCC_OUT

CC17

1

2

40 mils

1

CC18

0.1U_0402_16V4Z

2

XD_CD# XD_RB# XD_RE# XD_CE# XD_CLE XD_ALE XDWE# XDWP#_S DWP#

XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_SD_D4 XD_SD_D5 XD_SD_D6 XD_SD_D7

4

JREAD

33

XD-VCC

34

XD-CD-SW

1

XD-R/B

2

XD-RE

3

XD-CE

4

XD-CLE

5

XD-ALE

6

XD-WE

7

XD-WP

8

XD-D0

9

XD-D1

26

XD-D2

27

XD-D3

28

XD-D4

30

XD-D5

31

XD-D6

32

XD-D7

TAITW_R015- 211-LM-A_NR

@JREAD

@

14

MS-VCC

MS-SCLK

MS-INS

MS-BS MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3

SD-VCC SD-CLK

SD-CMD SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3

SD-WP-SW

SD-CD-SW

4in1-GND 4in1-GND 4in1-GND 4in1-GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MS_CLK

15

MS_CD#

17

SDCMD_MSBS

21

XD_SD_MS_D0

19

XD_SD_MS_D1

20

XD_SD_MS_D2

18

XD_SD_MS_D3

16

23

SD_CLK

24

SDCMD_MSBS

12

XD_SD_MS_D0

25

XD_SD_MS_D1

29

XD_SD_MS_D2

10

XD_SD_MS_D3

11

XDWP#_S DWP#

35

SD_CD#

36

13 22 37 38

2010/09/03 2012/12/31

3

+VCC_OUT

Compal Secret Data

Deciphered Date

2

SDCLK_MSCLK_XDCE #

RC11 22_0402_5%RC11 22_0402_5 %

1 2

RC12 22_0402_5%RC12 22_0402_5 %

1 2

RC13 22_0402_5%RC13 22_0402_5 %

1 2

Reserved for EMI,close to UC1.42

@

RC14

SD_CLK

MS_CLK

XD_CE#

RC14

1 2

100_0402_5%

@

RC15

1 2

100_0402_5%

@

RC16

1 2

100_0402_5%

100P_0402_50V8J

Reserved for EMI,close to JREAD

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCIe-CardReader JMB389

PHQAA LA-6832P M/B

@

CC19

1 2

100P_0402_50V8J

@

CC20

1 2

@

CC21

1 2

SD_CLK

MS_CLK

XD_CE#

0.1

29 45Monday, September 06, 2010

1

0.1

5

USB30_POK

RT1

+1.5V to +1.05V Transfer

+5VALW+1.5V+ 5VALW +1.5V +1.05V

1U_0603_10V6K

10U_0603_6.3V6M

CT1

CT2

1

2

Vout=0.8(1+10K/32.4K)

D D

1.042 ~ 1.0469 ~ 1.0519V Spec: 0.9975 ~ 1.05 ~ 1.1025

USB30_POK

2

+3V

+3VALW to +3V Transfer

CT20 0.01U_0402_25V7KC T20 0.01U_0402_25V7K

2

1

CT14 0.1U_0402_16V7KCT14 0.1U_0402_16V7K

1

2

1

CT22 0.01U_0402_25V7KC T22 0.01U_0402_25V7K

CT21 0.1U_0402_16V7KCT21 0.1U_0402_16V7K

2

1

2

CT15 0.01U_0402_25V7KC T15 0.01U_0402_25V7K

2

1

2

G

QT2 2N7002_SOT23-3

CT23 0.01U_0402_25V7KC T23 0.01U_0402_25V7K

2

1

SYSON<32,40>

+3V +3VA

LT3

1 2

BLM18AG601SN1D_2P

C C

CT25

10U_0603_6.3V6M

+1.05V

CT19 0.01U_0402_25V7KC T19 0.01U_0402_25V7K

CT17 0.01U_0402_25V7KC T17 0.01U_0402_25V7K

CT18 0.1U_0402_16V7KCT18 0.1U_0402_16V7K

CT16 0.1U_0402_16V7KCT16 0.1U_0402_16V7K

2

1

2

+3V

CT10 0.01U_0402_25V7KC T10 0.01U_0402_25V7K

CT12 0.01U_0402_25V7KC T12 0.01U_0402_25V7K

CT11 0.01U_0402_25V7KC T11 0.01U_0402_25V7K

CT13 0.01U_0402_25V7KC T13 0.01U_0402_25V7K

2

B B

2

1

UT2

5

VIN

VOUT

9

VOUT

VIN

6

VCNTL

7

POK

8

EN

GND

APL5930KAI-TRG_SO8

+3VALW

RT37

RT37 100K_0402_5%

100K_0402_5%

1 2

13

D

S

PCIE_PRX_C_USBTX_P6<17> PCIE_PRX_C_USBTX_N6<17>

PCIE_PTX_C_USBRX_P6<17> PCIE_PTX_C_USBRX_N6<17>

UPD720200A: SMIB Low active

CT24 0.01U_0402_25V7KC T24 0.01U_0402_25V7K

2

USB30_SMI#

1

CT41

0.1U_0402_16V7K

1 2

RT38 47K_0402_5%RT38 47K_0402_5%

0.01U_0402_25V7K

+3V & +1.05V has power sequence timing:

0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms

CLK_USB30<17> CLK_USB30#<17>

PLT_RST#<5,20,27,28,29,32,33>

EC_SWI#<18,28>

CLKREQ_USB30#<17>

USB30_SMI#<21>

For UPD720200: S

MI high active

13

D

Q57

2

G

@

G

@

2N7002_SOT23-3

S

24MHZ_12PF_X5H024000DC1H

RT30

0_0402_5%@RT30

0_0402_5%

@

1 2

+5VALW

FB

CT43

1

2

4.7K_0402_5%

1A

3 4

2

1

+3VALW

2

1

G

2

1

CT29

CT29 CT30

CT30

+3V

@

1 2

RT21 0_0402_5%

@

1 2

RT40 0_0402_5%

YT1

1 2

12P_0402_50V8J

CT37

48MCLK_USB30<17>

1 2

RT2

12

10K_0402_1%

RT3

32.4K_0402_1%

CT42

0.1U_0402_16V4Z

S

QT1

QT1 AO3413_SOT23

AO3413_SOT23

D

1 3

+3V

0.1U_0402_16V7K

12

0.1U_0402_16V7K

12

RT12 0_0402_5%RT12 0_0402_5%

1 2

RT15 10K_0402_5%RT15 10K_0402_5%

+3V

RT16 100_0402_1%@RT16 100_0402_1%@ RT17 10K_0402_5%RT17 10K_0402_5%

+3V

RT180_0402_5% R T180_0402_5%

1 2

RT39 10K_0402_5%RT39 10K_0402_5%

1 2

1SS355TE-17_SOD323-2

1

221

USB30_SMI_R

USB30_SMI#_R

12

RT26

RT26 100_0402_5%

100_0402_5%

12P_0402_50V8J

1

CT38

0_0402_5%

2

12

DT3

@

RT31

1 2

Close to U102.D7 Close to U102.P13

10U_0603_6.3V6M

0.1U_0402_16V7K

CT3

CT4

1

2

PCIE_PRX_USBTX_P6 PCIE_PRX_USBTX_N6

USB30_WAKE#

1 2 1 2 1 2

USB30_SMI_R USB30_SMI#_R

SPI_CLK_USB

1U_0603_10V6K

SPI_CS_USB#

CT44

SPI_SI_USB

1

SPI_SO_USB

2

CLK_48M_USB

0_0402_5%

1 2

1 2 @

@

RT29

RT28

+3V

Place as close as possibile to UU102.N14 and UU102.M14

9/2 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80 (10uF_0603) by sourcer demand

RT32

47K_0402_5%

+3V

1 2

12

RT33

RT33 10K_0402_5%

10K_0402_5%

UT4

1

CS#

2

SO

3

WP#

4

GND

MX25L5121EMC-20G SOP 8P

5

35mA

HOLD#

SCLK

VCC

SI

8 7 6 5

RT35 10K_0402_5%RT 35 10K_0402_5%

1 2

RT36 0_0402_5%RT36 0_0402_5%

1 2

CT39

1 2

SPI_CLK_USB_R SPI_SI_USB

0.1U_0402_16V7K

1 2

0_0402_5%

RT43

A A

SPI_CS_USB# SPI_SO_USB

4

+3VA +3VA

8P_0402_50V8D

CT6

@

1

2

0.01U_0402_25V7K

1

2

CT5

Follow Vendor recommend.

+3V +1. 05V

UT1

D10

F13

F14

VDD33

B2

PECLKP

B1

PECLKN

D2

PETXP

D1

PETXN

F2

PERXP

F1

PERXN

H2

PERSTB

K1

PEWAKEB

K2

PECREQB

J2

AUXDET

J1

PSEL

H1

SMI

P4

SMIB

P5

PONRSTB

M2

SPISCK

N2

SPISCB

N1

SPISI

M1

SPISO

K13

GND

K14

GND

J13

GND

C14

GND

N14

XT1

M14

XT2

P6

CSEL

CSEL=0 CSEL=1

A1

GND

A2

GND

A3

GND

A4

GND

A5

0_0402_5%

GND

A7

GND

A9

GND

A11

GND

A13

GND

A14

GND

B3

GND

B4

GND

B5

GND

B7

GND

B9

GND

B11

GND

B13

GND

B14

GND

C1

GND

C2

GND

C3

GND

C10

GND

C11

GND

SPI_CLK_USB

1 2

Close to UU37.6

SPI_CLK_USBSPI_CLK_USB_R

4

GND

C12

C13

RT34

RT34 0_0402_5%

0_0402_5%

@

GNDD3GNDD4GND

1

0.1U_0402_16V7K

0.1U_0402_16V7K CT7

CT7

2

0.01U_0402_25V7K

L10

VDD33F3VDD33G3VDD33G4VDD33L9VDD33

+3V:200mA

+1

：：：：

24MHz XTAL

：：：：

48MHz Clock

GND

GNDE1GNDE2GND

D11

D12

D13

D14

2

CT40

0.1U_0402_16V7K

1

@

8P_0402_50V8D

CT9

@

1

2

CT8

L13

L14

VDD33

VDD33N4VDD33N5VDD33N6VDD33P3VDD10C4VDD10C5VDD10C6VDD10C7VDD10D5VDD10C8VDD10C9VDD10D8VDD10D9VDD10E3VDD10E4VDD10

.05V:800mA

GND

E13

E14

GNDF4GNDF6GNDF7GNDF8GNDF9GND

GNDG1GNDG2GNDG6GNDG7GNDG8GND

GND

F11

F12

3

1 2

0_0402_5%

LT1

@LT1

@

4

1

WCM-2012-121T_0805

U3RXDN1_R U3RXDN1_R_L

GND

GNDH6GND

GND

GNDH7GNDH8GNDH9GND

G9

H12

G13

G11

G12

WCM-2012-121T_0805

E11

E12

H11

VDD10

VDD10H3VDD10H4VDD10L5VDD10

GNDJ3GNDJ4GNDJ6GNDJ7GNDJ8GNDJ9GND

GND

GNDK3GNDK4GNDL1GNDL2GNDL3GND

J11

J12

UPD720200AF1-DAP-SSA-A

3

1 2

+3VA

K11

K12

L8

VDD10

0_0402_5%

D7

U3AVDO33

U3TXDP2

U3TXDN2

U2DM2

U2DP2

U3RXDP2

U3RXDN2

PPON2 PPON1

U3TXDP1

U3TXDN1

U2DM1

U2DP1

U3RXDP1

U3RXDN1

U2AVSS

U2PVSS

U3AVSS

L4

2

U3RXDP1_R_LU3RXDP1_R

RT4

3

2

RT6

USB20_DN1_R<27>

USB20_DP1_R<27>

P13

U2AVDD10

B6

A6 N8

P8 B8

A8

OCI2#

G14

OCI2B

H13

OCI1B

H14 J14

B10

A10 N10

P10 B12

A12

P12

RREF

N12

N11

D6

P14

GND

P11

GND

P9

GND

P7

GND

P2

GND

P1

GND

N13

GND

N9

GND

N7

GND

N3

GND

M13

GND

M12

GND

M11

GND

M10

GND

M9

GND

M8

GND

M7

GND

M6

GND

M5

GND

M4

GND

M3

GND

L12

GND

L11

GND

L7

GND

L6

GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1 2

OCL1#

USB30PWRON

U3TX_C_DP1

CT32 0.1U_0402_16V4ZCT32 0.1U_0402_16V4Z

U3TX_C_DN1

CT33 0.1U_0402_16V4ZCT33 0.1U_0402_16V4Z

U2D_DN1

U2D_DP1 U3RXDP1_R

U3RXDN1_R

RT22 1.6K_0402_1%RT22 1.6K_0402_1%

1 2

U3TXDN1 U3TXDN1_L

USB20_DN1_R

USB20_DP1_R

RT13 10K_0402_5%RT13 10K_0402_5%

12

U2D_DN1 <27>

U2D_DP1 <27>

200910/9 2010/01/23

1 2

WCM-2012-121T_0805

4

1

LT2

@

1 2

RT9 0_0402_5%RT9 0_0402_5%

1 2

LT4

1

4

WCM-2012-900T_0805@

1 2

RT10 0_0402_5%RT10 0_0402_5%

+3V

U3TXDP1

U3TXDN1

Compal Secret Data

Deciphered Date

2

RT5

0_0402_5%

3

2

RT7

0_0402_5%

2

3

U3TXDP1_LU3TXDP1

3

2

USB20_DN1_L

2

USB20_DP1_L

3

+USB_VCCB

1

+USB_VCCB

W=80mils

4.7U_0805_10V4Z

1

CT26

2

U3TXDP1_L

U3TXDN1_L USB20_DP1_L

USB20_DN1_L U3RXDP1_R_L

U3RXDN1_R_L

USB30PWRON

RT11

0_0402_5%

OCL1#

RT19

0_0402_5%

U3RXDN1_R_L

U3RXDP1_R_L U3TXDN1_L U3TXDP1_L

Title

Size Document Number Rev

Custom

Date: Sheet of

0.1U_0402_16V4Z

1

+

CT31

CT27

2

1000P_0402_50V7K

220U_6.3V_M_R15

9 1 8 3 7 2 6 4 5

@

1 2

1000P_0402_50V7K

JUSB30

SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX-

SANTA_371394-3

1 2 3 4

LXES4XBAA6-027_MSOP8

Compal Electronics, Inc.

PCIe-USB3.0 UPD720200A

10

GND

11

GND

12

GND

13

GND

0_0603_5%

RT41

USB_CHG_EN#

USB_OC#1

DT2

RR+ TT+

@

8

VCC

7

GND

6

D-

5

D+

PHQAA LA-6832P M/B

1

CT28

2

USB_GND

12

0_0603_5%

0_0603_5% RT42

RT42

USB_CHG_EN# <27,32>

USB_OC#1 <20,27, 32>

+USB_VCCB

USB20_DN1_L USB20_DP1_L

30 58Monday, September 06, 2010

CT45 .1U_0402_16V7KCT45 .1U_0402_16V7K

2

1

0.1

5

RA20

+3VS

D D

MIC1_LINE1_R _L

Ext. Mic/LINE IN

MIC1_LINE1_R _R

C C

AZ_RST_ HD#<16>

place close to chip

RA36

0_0402_ 5%

RA39

0_0402_ 5%

For EMI

RA44

100K_04 02_5%

@

RA35

0_0402_ 5%

RA38

0_0402_ 5%

CA11

0.01U_04 02_25V7K

@

+3VS

FBMH160 8HM601-T

RA30

RA30 0_0402_ 5%

0_0402_ 5%

@

RA37

RA37 0_0402_ 5%

0_0402_ 5%

@

12

FBMH160 8HM601-T

CA2

RA1

12

CA8

MIC1_LINE1_R _L

MIC1_LINE1_R _R

INT_MIC_DATA<13>

1 2

CA12 100P_ 0402_50V8JCA12 100P_ 0402_50V8J

1

10U_080 5_10V4Z

2

1

10U_080 5_10V4Z

2

For EMI

RA41

INT_MIC_CLK<13>

CA47 0.1U_060 3_50V7KCA47 0.1U_060 3_50V7K

B B

1 2

CA48 0.1U_060 3_50V7KCA48 0.1U_060 3_50V7K

1 2

CA49 0.1U_060 3_50V7KCA49 0.1U_060 3_50V7K

1 2

CA50 0.1U_060 3_50V7KCA50 0.1U_060 3_50V7K

1 2

RA18 10_0603 _5%RA18 10_0603 _5%

12

FBMA-10-1 00505-301T

1

CA28

CA28 27P_040 2_50V8J

27P_040 2_50V8J

@

2

CAM@

RA42

100K_04 02_5%

INT_MIC_CLK_ R

+5VALW

@

EC_MUTE #

+MIC1_VRE FO_L

4

0.1U_040 2_16V4Z

CA1

0.1U_040 2_16V4Z

CA7

1U_0402 _6.3V6K

CA9

1 2

CA10

1U_0402 _6.3V6K

12

CA224.7U_0805_1 0V4Z CA224 .7U_0805_10V4 Z

INT_MIC_DATA

INT_MIC_CLK_ R

EC_MUTE #

AZ_RST_ HD#

MONO_IN

SENSE_A

1 2

CA15

2.2U_060 3_6.3V4Z

+DVDD_IO

1

+3VS_DV DD

2

35 mA

1

2

23 24

14 15

CA214.7U_0805_1 0V4Z CA214 .7U_0805_10V4 Z

21 22

16 17

2

3

4

11

12

13

18

36

35

31

43 42 49

7

DGND

RA22 4.7K_040 2_5%RA22 4.7K_0402 _5%

12

+PVDD1

JUMP_43 X39

+PVDD2

CA61

46

9

1

DVDD

PVDD139PVDD2

DVDD_IO

LINE1_L LINE1_R

LINE2_L LINE2_R

MIC1_L MIC1_R

MIC2_L MIC2_R

GPIO0/DMIC_DATA

GPIO1/DMIC_CLK

PD#

RESET#

PCBEEP

SENSE A

SENSE B

CBP

CBN

MIC1_VREFO_L

PVSS2 PVSS1 DVSS2 DVSS1

ALC269Q -VB5-GR _QFN48_ 7X7

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L

HP_OUT_R

SDATA_OUT

SDATA_IN

SPDIFO

MONO_OUT

MIC2_VREFO

MIC1_VREFO_R

LDO_CAP

JDREF

CPVEE

AVSS1 AVSS2

600 mA

2

JA1

2

@

1

place close to chip

1

0.1U_040 2_16V4Z

+AVDD

2

6

8 mA

38

CA3

UA1

AVDD125AVDD2

SYNC

BCLK

EAPD

VREF

40 41

45 44

32 33

10

6

5

8

47

48

20

29

30 28

27

19

34

26 37

AC_VREF

AC_JDRE F

CPVEE

10U_080 5_10V4Z

AZ_SDIN0_ HD_R

3

0.1U_040 2_16V4Z

CA57

1

2

AZ_SYNC_H D

AZ_BITCLK _HD

AZ_SDOU T_HD

CA14 2.2U_0603_ 6.3V4ZCA14 2.2U_0603_ 6.3V4Z

1

CA56

2

10U_080 5_10V4Z

1

CA60

@

2

10U_080 5_10V4Z

1

CA4

CA5

2

0.1U_040 2_16V4Z

SPKL+ SPKL-

SPKR+ SPKR-

RA4 75_0402 _1%RA4 75_0402 _1%

RA5 75_0402 _1%RA5 75_0402 _1%

RA6 33_0402 _5%RA6 33_ 0402_5%

AZ_BITCLK _HD

+MIC1_VRE FO_R

RA9 20 K_0402_1%RA 9 20K_0402 _1%

12

1 2

AGND

RA2

12

0_0603_ 5%

RA11

12

0_0603_ 5%

@

0.1U_040 2_16V4Z

1

CA6

2

place close to chip

12

For EMI

@

12

RA1710_0402_5%@RA1710_0402_5%

10P_040 2_50V8J

CA23 10U_0805_ 10V4ZCA23 10U_080 5_10V4Z

1 2

CA17

0.1U_040 2_16V4Z

place close to chip

0.1U_040 2_16V4Z

1

CA44

2

10U_080 5_10V4Z

0.1U_040 2_16V4Z

1

CA59

@

2

10U_080 5_10V4Z

RA3

12

0_0603_ 5%

HP_L <25>

HP_R < 25>

AZ_SYNC_H D <16 >

AZ_BITCLK _HD <16>

AZ_SDOU T_HD <16>

AZ_SDIN0_ HD <16>EC_MUTE #<32>

CA29

@

1 2

1

CA16

2.2U_060 3_6.3V6K

2

@

2

1

Speaker Connector

+5VALW

1

CA43

2

1

CA58

@

2

+5VALW

SPKL+

SPKL-

SPKR+

SPKR-

placement near Audio Codec

RA13

12

0_0603_ 5%

RA14

RA15

RA16

C Beep

E

EC_BEEP #<32 >

CA19

CA20

CA25

CA26

1

10U_080 5_10V4Z@

2

1

10U_080 5_10V4Z@

2

12

1

10U_080 5_10V4Z@

2

1

10U_080 5_10V4Z@

2

12

PCI Beep

PCH_SPK R<16>

Change to AGND for high frequency noise issue

9/1 Change RA12 from 10k to 4.7kohm and CA18 from 0.1uF to 100pF for Beep by A51 demand.

SPK_L1

1

CA24

@ CA24

@

1U_0402 _6.3V6K

2

SPK_L2

SPK_R1

1

CA27

@ CA27

@

1U_0402 _6.3V6K

2

SPK_R2

RA7

1 2

47K_040 2_5%

RA8

1 2

47K_040 2_5%

4.7K_040 2_5%

Beep sound

0.1U_040 2_16V4Z

RA12

1 2

DA7

1

PESD5V0 U2BT_SOT23-3

SPK_L1 SPK_L2 SPK_R1 SPK_R2

DA6

1

PESD5V0 U2BT_SOT23-3

CA13

MONO_IN

1 2

2

CA18

CA18 100P_04 02_50V8J

100P_04 02_50V8J

1

Ext.MIC/LINE IN JACK

RA33

MIC1_LINE1_R _R

MIC1_LINE1_R _L

RA33

1K_0402 _5%

RA32

MIC_SENSE

2N7002D W-T/R7_SOT3 63-6

QA1A

2.2K_040 2_5%

12

2.2K_040 2_5%

61

RA31

12

RA29

12

RA28 100K _0402_5%RA28 100K_ 0402_5%

2

+MIC1_VRE FO_R

+MIC1_VRE FO_L

@DA7

@

2

3

@

2

3

MIC1_R <25>

MIC1_L <2 5>

JSPK

1

2

3

4

ACES_85 204-0400N

@

RA43 10 0K_0402_5%RA43 100K_04 02_5%

Sense Pin Impedance

39.2K

SENSE A

A A

20K

10K

5.1K

39.2K

20K

10K

5

Codec Signals

PORT-I (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

(PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)SENSE B

PORT-H (PIN 20)

Function

Headphone out

Ext. MIC

place close to chip

MIC_SENSE SENSE_A

NBA_PLU G<25>

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RA10 20 K_0402_1%RA10 20K_ 0402_1%

RA21 39 .2K_0402_1%RA21 39.2K_0 402_1%

12

Compal Secret Data

2010/09/ 03 2012/12/ 31

3

Compal Secret Data

Deciphered Date

2

+3VL

RA34 10 0K_0402_5%@RA 34 100K_0402 _5%@

+3VALW

SM_SENS E#<32>

2N7002D W-T/R7_SOT3 63-6

Title

Size Document N umber Rev

Monday, September 06, 2010

Date: Sheet of

3

QA1B

5

4

Compal Electronics, Inc.

HDA-ALC269/HP/MIC

PHQAA LA-6832P M/B

1

31 45

BACK_SE NSE <25>

0.1

5

0.1U_0402_16V4Z

1

C436

0.1U_0402_16V4Z

+3VL

R380 47K_0 402_5%R3 80 47K_0402_5%

R382 47K_0 402_5%R3 82 47K_0402_5%

0.1U_0402_16V4Z

1 2

For EMI

CLK_PCI_EC

12

R377

10_0402_5%

@

D D

+3VL

@

C443

22P_0402_50V8J

@

R378

R378 47K_0402_5%

47K_0402_5%

12

C444 0.1U_0402_16V4ZC444 0.1U_0402_ 16V4Z

1

2

ECRST#

C437

2

GATEA20<21>

KB_RST#<21>

SERIRQ<16,33>

LPC_FRAME#<16,33>

LPC_AD3<16,33> LPC_AD2<16,33> LPC_AD1<16,33> LPC_AD0<16,33>

CLK_PCI_EC<2 0>

PLT_RST#<5, 20,27,28,29,30,33>

EC_SCI#<21>

HDPLOCK<33>

KSO1

KSO2

to avoid EC entry ENE test mode

C C

RP7

+3VL

+3VS

USB_CHG_EN#<27,30>

B B

1 8 2 7 3 6 4 5

2.2K_0804_8P4R_5%

0_0402_5%

1 2

@

1 2

C819 1U_0 402_6.3V6K

@

1 2

C820 180 P_0402_50V8J

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

R1442

PLT_RST#

KSI[0..7]<16,33 ,34>

KSO[0..17]<33, 34>

USB_CHG_EN#_R

SUSP#

Close to EC

CLK_EC<18>

KSI[0..7]

KSO[0..17]

PCH_SUSPWRDN<18>

PWR_SUSP_LED#< 34>

EC_SMB_CK1<1 5,37> EC_SMB_DA1<1 5,37> EC_SMB_CK2<17,33,34> EC_SMB_DA2<17,33,34>

PM_SLP_S3#<18>

EC_SMI#<21>

ESB_CK<34> ESB_DAT<34>

INVT_PWM<13>

FAN_SPEED1<5>

CPSETIN<38>

E51_TXD<27>

E51_RXD<27>

ON/OFFBTN#<34>

NUM_LED#<33>

R565 0_0 402_5%

9/2 Add CPSETIN function in EC_GPIO15 by Power demand

0.1U_0402_16V4Z

1

C438

2

0.1U_0402_16V4Z

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

@

1 2

4

1

C439

2

1000P_0402_50V7K

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC PLT_RST# ECRST# EC_SCI# HDPLOCK

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6

KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9

KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

PM_SLP_S3# SLP_S5# EC_SMI# USB_CHG_EN#_R ESB_CK ESB_DAT PCH_SUSPWRDN INVT_PWM FAN_SPEED1

E51_TXD E51_RXD ON/OFFBTN# PWR_SUSP_LED# NUM_LED#

CRY1 CRY2

2

C440

C441

C441 1000P_0402_50V7K

1000P_0402_50V7K

1

U19

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LPC_FRAME#/LFRAME#

5

LPC_AD3/LAD3

7

LPC_AD2/LAD2

8

LPC_AD1/LAD1

10

LPC_AD0/LAD0

12

CLK_PCI_EC/PCICLK

13

PCIRST#/GPIO05

37

EC_RST#/ECRST#

20

EC_SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/SCL0/GPIO44

78

EC_SMB_DA1/SDA0/GPIO45

79

EC_SMB_CK2/SCL1/GPIO46

80

EC_SMB_DA2/SDA1/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

SUS_PWR_DN_ACK/GPIO0D

25

INVT_PWM/PWM2/GPIO11

28

FAN_SPEED1/FANFB0/GPIO14

29

FANFB1/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLK1

123

XCLK0

+3VL

LPC & MISC

Int. K/B

Int. K/B Matrix

Matrix

9

22

33

VCC

PWM Output

DA Output

PS2 Interface

SPI Device I/F

SPI Flash ROM

SM Bus

GPIO

GND

11

24

+3VL

1 2

0.1U_0402_16V4Z

96

111

125

67

VCC

AVCC

BEEP#/PWM1/GPIO10

ACOFF/FANPWM1/GPIO13

BATT_TEMP/AD0/GPI38

BATT_OVP/AD1/GPI39

AD Input

DAC_BRIG/DA0/GPO3C

EN_DFAN1/DA1/GPO3D

EC_MUTE#/PSCLK1/GPIO4A

USB_EN#/PSDAT1/GPIO4B CAP_INT#/PSCLK2/GPIO4C

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

WOL_EN/SDICLK/GPXIOA01

ME_EN/SDIMOSI/GPXIOA02

LID_SW#/GPXIOD00

GPIO

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

EC_SWI#/GPXIOA06

ICH_PWROK/GPXIOA07

GPO

RF_OFF#/GPXIOA09

PM_SLP_S4#/GPXIOD01

GPI

EC_THERM#/GPXIOD04

PBTN_OUT#/GPXIOD06

EC_PME#/GPXIOD07

GND

AGND

GND

KB930QF-A1_LQFP128_ 14X14

35

69

94

113

3

C442

PWM0/GPIO0F

FANPWM0/GPIO12

ADP_I/AD2/GPI3A

AD3/GPI3B AD4/GPI42 AD5/GPI43

IREF/DA2/GPO3E

DA3/GPO3F

PSDAT2/GPIO4D

SDICS#/GPXIOA00

SPIDI/MISO

SPIDO/MOSI

SPICLK/GPIO58

SPICS#

GPIO40

H_PECI/GPIO41

FSTCHG/GPIO50

PWR_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXIOA05

BKOFF#/GPXIOA08

GPXIOA10 GPXIOA11

ENBKL/GPXIOD02

EAPD/GPXIOD03

SUSP#/GPXIOD05

V18R

KB_LED

21

EC_BEEP#

23

SM_SENSE#

26

ACOFF

27

BATT_TEMPA

63

TMPTU1_SXP

64

ADP_I

65

ADP_V

66

TMPTU2_SXP

75

HDPACT

76

68

EN_DFAN1

70

IREF

71

CHGVADJ

72

EC_MUTE#

83

USB_EN#

84

CAP_INT#

85

H_PROCHOT#_EC

86

TP_CLK

87

TP_DATA

88

VGATE

97

WOL_EN

98

PWRME_CTRL#

99

LID_SW#

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

SPI_CLK

126

SPI_CS#

128

CIR_IN

73

EC_PECI

74

FSTCHG

89

BATT_FULL_LED#

90

CAPS_LED#

91

BATT_CHG_LOW_LED#

92

PWR_ON_LED#

93

SYSON

95

VR_ON

121

ACIN_D

127

PCH_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

TP_LED

103

PM_PWROK

104

BKOFF#

105

HDPINT

106

CAP_RST#

107

SA_PGOOD

108

CEC_INT#

110

UMA_ENBKL

112

USB_OC#1

114

SLP_CHG#

115

SUSP#

116

PBTN_OUT#

117

USB_OC#0

118

+EC_V18R

124

KB_LED < 33> EC_BEEP# < 31>

SM_SENSE# <31>

ACOFF <36,38>

BATT_TEMPA <37> TMPTU1_SXP <27> ADP_I <37,38> ADP_V <38> TMPTU2_SXP <27>

HDPACT <33>

EN_DFAN1 < 5> IREF < 38>

CHGVADJ <38 >

EC_MUTE# < 31>

USB_EN# <25>

CAP_INT# <34>

TP_CLK <34>

TP_DATA <34>

VGATE <5,1 8,43>

WOL_EN <28> PWRME_CTRL# < 16>

LID_SW# <33>

EC_SI_SPI_SO <33> EC_SO_SPI_SI < 33> SPI_CLK <33> SPI_CS# <33>

R461 43_0402_1%R461 43_0402_1%

1 2

FSTCHG <38>

BATT_FULL_LED# <34> CAPS_LED# <33>

BATT_CHG_LOW_LED# <34>

PWR_ON_LED# <34>

SYSON <30,40> VR_ON <43>

PCH_RSMRST# <18> EC_LID_OUT# <1 7> EC_ON <16,34,39>

TP_LED <34>

PM_PWROK <5,18>

BKOFF# <13>

HDPINT <33> CAP_RST# < 34> SA_PGOOD <41>

CEC_INT# <15>

UMA_ENBKL <19>

USB_OC#1 <20,27,30>

SLP_CHG# <27> SUSP# <16,2 7,35,40,42> PBTN_OUT# <5, 18>

USB_OC#0 <20,25>

C448

4.7U_0805_10V4Z

2

VR_HOT#<43>

H_PECI < 5>

H_PROCHOT#_EC

BATT_TEMPA

ACIN_D

+3VL

ACIN_D

R737

0_0402_5%

12

2

G

TV tuner temperature

TMPTU1_SXP

TMPTU2_SXP

H_PROCHOT#_EC

CEC_INT#

CAP_INT#

TP_CLK

TP_DATA

LID_SW#

SYSON

R341 330K_ 0402_5%R341 330K_0402_5%

1 2

1

13

D

Q41

2N7002_SOT23

S

1 2

C445 100P_0402 _50V8JC445 100P_0402_50V8J

1 2

C446 100P_0402 _50V8JC446 100P_0402_50V8J

R754 10K_0 402_5%R754 10K_0402_5%

1 2

R757 10K_0 402_5%R757 10K_0402_5%

1 2

R758 10K_0 402_5%

1 2

R53 100K_0402_5%R53 100K_0402_5%

1 2

R172 4.7K_ 0402_5%R172 4.7K_0402_5%

1 2

R379 4.7K_0402_5%R379 4.7K_0402_5 %

1 2

R381 4.7K_0402_5%R381 4.7K_0402_5 %

1 2

R5 4.7K_0402_5%R5 4.7K_0402_5 %

CH751H-40PT_SOD323-2

SLP_CHG#

SUSP#

VR_ON

12

@

12

+3VALW

12

R38347K_0402_5% R38347K_0402_5%

D21

2 1

R1428 10K_0402_5%R1428 10K_0402_5%

R439 10K_0402_5%@R439 10K_0402_ 5%@

R423 10K_0402_5%R423 1 0K_0402_5%

R462 10K_0402_5%R462 1 0K_0402_5%

C518

C518 47P_0402_50V8J

47P_0402_50V8J

+3VS

+3VL

+5VS

12

H_PROCHOT# < 5,37>

ACIN <18,34, 38>

+3VALW

C818

12

5

U44

0.1U_0402_16V4Z

PM_SLP_S5#<18>

PM_SLP_S4#<18>

A A

1

2

1 2

R342 100 K_0402_5%R342 100K_0402_5%

5

0.1U_0402_16V4Z

P

IN1

IN2

SLP_S5#

4

O

G

SN74AHC1G08DCKR_SC70-5

3

E51_TXD

R389

1 2

10M_0402_5%

1

C449

18P_0402_50V8J

1

2

32.768KHZ_12.5PF_Q 13MC14610002

CRY2CRY1

@

1

C450

Y4

2

OSC4OSC

NC3NC

4

8/12 Change C449, C450, Y4 from @ to mount

18P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2010/09/03 2012/12/31

3

Compal Secret Data

Deciphered Date

2

CIR

CIR_IN

+5VL

Title

Size Document Number Rev

Monday, September 06, 201 0

Date: Sheet of

+5VL

R748

R748 10K_0402_5%

10K_0402_5%

1 2

CIR@

1 2

R750 100 _0805_5%

Compal Electronics, Inc.

+5VL_CIR

C783

4.7U_0805_10V4Z

CIR@

LPC-EC-KB930

PHQAA LA-6832P M/B

1

U45

1

2

3

4

IRM-V538/TR1

CIR@

Vout

VCC

GND

32 45

0.1

SPI Flash (256KB)

+3VL

20mils

1

C451

0.1U_040 2_16V4Z

SPI_CLK<32>

EC_SO_S PI_SI<32>

2

SPI_CS#

SPI_CLK

EC_SO_S PI_SI EC_SI_SPI_SO

SPI_CLK

8/30 Change U22 From SA00003GK00 to SA00003GM10 due to EOL of SA00003GK00

9/06 Change U22 change to SA00003FL10

Keyboard LED

+5VS

12

R587

10K_040 2_5%

KBL@

13

D

Q52

KB_LED<32>

2

G

2N7002_ SOT23-3

KBL@

S

KEYBOARD CONN.

KSI[0..7]

KSO[0..17]

JKB

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

ACES_88 170-3400

@

KSI[0..7] <16,32,34>

KSO[0..17] < 32,34>

JKB34 KSO16

KSO17

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4

CAPS_LE D#

NUM_LED #

1 2

R372 300_ 0402_5%R37 2 300 _0402_5%

R376 300_ 0402_5%R37 6 300 _0402_5%

8

3

7

1

6

5

R394

1 2

10_0402 _5%

@

Q38

Q38 AO3413_ SOT23-3

AO3413_ SOT23-3

D

S

D

S

13

G

2

12

U22

VCC

VSS

W

HOLD

S

C

Q

D

W25X 10BVSNIG_SO8

1 2

C454 10P_0402_50 V8J

For EMI

KBL@

+5VS_LE D

1

C836

0.1U_040 2_16V4Z

2

KBL@

+3VS

CAPS_LE D# < 32>

NUM_LED # <3 2>

4

2

@

EC_SI_SPI_SO < 32>

JBLG

1

2

3

4

5

GND

6

GND

ACES_85 201-0405N

@

+5VS_LE D

For EMI

Close to JKB

KSO16

KSO17

KSO2

KSO1

KSO0

KSO4

KSO3

KSO5

KSO14

KSO6

KSO7

KSO13

KSO8

KSO9

KSO10

KSO11

KSO12

KSO15

KSI7

KSI2

KSI3

KSI4

KSI0

KSI5

KSI6

KSI1

CAPS_LE D#

NUM_LED #

1 2

C401 100P_ 0402_50V8JC4 01 1 00P_0402_50V 8J

1 2

C402 100P_ 0402_50V8JC4 02 1 00P_0402_50V 8J

1 2

C404 100P_ 0402_50V8JC4 04 1 00P_0402_50V 8J

1 2

C405 100P_04 02_50V8JC4 05 100P_04 02_50V8J

1 2

C406 100P_ 0402_50V8JC4 06 1 00P_0402_50V 8J

1 2

C407 100P_04 02_50V8JC4 07 100P_04 02_50V8J

1 2

C408 100P_ 0402_50V8JC4 08 1 00P_0402_50V 8J

1 2

C409 100P_04 02_50V8JC4 09 100P_04 02_50V8J

1 2

C410 100P_04 02_50V8JC4 10 100P_04 02_50V8J

1 2

C411 100P_ 0402_50V8JC4 11 1 00P_0402_50V 8J

1 2

C412 100P_04 02_50V8JC4 12 100P_04 02_50V8J

1 2

C413 100P_ 0402_50V8JC4 13 1 00P_0402_50V 8J

1 2

C415 100P_ 0402_50V8JC4 15 1 00P_0402_50V 8J

1 2

C416 100P_04 02_50V8JC4 16 100P_04 02_50V8J

1 2

C417 100P_ 0402_50V8JC4 17 1 00P_0402_50V 8J

1 2

C418 100P_04 02_50V8JC4 18 100P_04 02_50V8J

1 2

C419 100P_ 0402_50V8JC4 19 1 00P_0402_50V 8J

1 2

C420 100P_ 0402_50V8JC4 20 1 00P_0402_50V 8J

1 2

C421 100P_04 02_50V8JC4 21 100P_04 02_50V8J

1 2

C422 100P_04 02_50V8JC4 22 100P_04 02_50V8J

1 2

C423 100P_ 0402_50V8JC4 23 1 00P_0402_50V 8J

1 2

C424 100P_04 02_50V8JC4 24 100P_04 02_50V8J

1 2

C425 100P_04 02_50V8JC4 25 100P_04 02_50V8J

1 2

C427 100P_04 02_50V8JC4 27 100P_04 02_50V8J

1 2

C429 100P_ 0402_50V8JC4 29 1 00P_0402_50V 8J

1 2

C431 100P_ 0402_50V8JC4 31 1 00P_0402_50V 8J

1 2

C433 100P_ 0402_50V8JC4 33 1 00P_0402_50V 8J

1 2

C435 100P_ 0402_50V8JC4 35 1 00P_0402_50V 8J

Lid SW

+3VALW

U21

U21 APX9132 ATI-TRL_SOT23-3

APX9132 ATI-TRL_SOT23-3

1

C453

0.1U_040 2_16V4Z

2

VDD2VOUT

GND

1

10P_040 2_50V8J

3

C452

LID_SW # <32>SPI_CS#< 32>

1

2

G-Sensor

RG2

@RG 2

@

12

0_0603_ 5%

+5VS +3VS_H DP

1

CG12

1U_0402 _6.3V6K

GSENSOR @

2

+3VS_HD P

HDPINT<32>

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DG1 CH751H-40PT_S OD323-2

UG3

1

VIN

2

GND

3

SHDN#

G9191-33 0T1U_SOT23-5

EC_SMB_ CK2<17,32,34>

HDPINT

+3VS_HD P+3VS

GSENSOR @

21

GSENSOR @UG3

GSENSOR @

5

VOUT

CG14

4

BP

RG3

RG4

RG5

RG6 4.7K_040 2_5%

GSENSOR @

RG7 1K_0402 _5%

GSENSOR @

0.1U_040 2_16V4Z

GSENSOR @

2010/09/ 03 2012/12/ 31

12

@

0.22U_04 02_10V4Z

SELF_TE ST

12

4.7K_040 2_5%GSENSO R@

GXOUT

12

4.7K_040 2_5%GSENSO R@

GXIN

12

4.7K_040 2_5%GSENSO R@

12

1

CG7

2

LPC Debug Port

+3VS_HD P

SELF_TE ST

+3VS_HD P

1

CG13

1U_0402 _6.3V6K

GSENSOR @

2

UG5

1

P3_5/SSCK/SCL/CMP1_2

2

P3_7/CNTR0#/SSO/TXD1

3

RESET#

4

XOUT/P4_7

5

VSS/AVSS

6

XIN/P4_6

7

VCC/AVCC

8

MODE

9

P4_5/INT0#/RXD1

10

1

CG8

GSENSOR @

0.1U_040 2_16V4Z

2

Compal Secret Data

P1_7/CNTR00/INT10#

R5F211B 4D34SP GSENSOR@

Deciphered Date

SERIRQ<16 ,32>

LPC_FRA ME#<16,32>

UG1

2

Vdd1

12

Vdd2

4

ST

6

PD

8

FS

9

Rev

TSH35TR _LGA16

Place UG1 and UG4 on TOP Layer

R392 0_0402_5%R 392 0_0402 _5%

LPC_AD3< 16,32>

LPC_AD1< 16,32>

GSENSOR @UG1

GSENSOR @

Voutx Vouty Voutz

GND1 GND2

Place the PAD under DDR DIMM.

+3VS

H7

1 2

3 5 7

10

NC1

11

NC2

14

NC3

15

NC4

16

NC5

1 13

P1_5/RXD0/CNTR01/INT11#

P3_3/TCIN/INT3#/SSI00/CMP1_0

7

8

9

10

DEBUG_P AD

GSENSOR @

VOUTX

CG1 0 .033U_0402_16 V7K

1 2

VOUTY

CG2 0 .033U_0402_16 V7K

1 2

VOUTZ

P1_6/CLK0/SSI01

P1_3/KI3#/AN11/TZOUT

P1_2/KI2#/AN10/CMP0_2

P1_1/KI1#/AN9/CMP0_1

P1_0/KI0#/AN8/CMP0_0

P3_4/SCS#/SDA/CMP1_1

GSENSOR @

CG3 0 .033U_0402_16 V7K

1 2

GSENSOR @

+3VS_HD P

P1_4/TXD0

P4_2/VREF

Title

Size Document N umber Rev

Date: Sheet of

@H 7

@

56

4

3

2

1

R393

R393 22_0402 _5%

22_0402 _5%

@

1 2 2

C457

C457 22P_040 2_50V8J

22P_040 2_50V8J

1

@

PLT_RST # <5,2 0,27,28,29,30,32>

LPC_AD2 <1 6,32>

LPC_AD0 <1 6,32>

CLK_PCI_D DR <20>

For EMI

Reserve for 2nd Source

CG9 0.1U_0402_16V 4Z

@

CG10 0.1U_0 402_16V4Z

@

CG11 0.1U_ 0402_16V4Z

@

SELF_TE ST

11

12

13

14

VOUTZ

15

16

VOUTX

17

VOUTY

18

19

20

VOUTX

12

VOUTY

12

VOUTZ

12

1 2

10 13

RG9

RG9 47K_040 2_5%

47K_040 2_5%

GSENSOR @

UG4

2

XOUT

3

YOUT

4

ZOUT

9

0G-DET

7

SLEEP# G-SELECT ST

MMA7360 LR2_LGA14

HDPACT <32>

RG10 47K_0 402_5%

GSENSOR @

+3VS_HD P

1

CG6

0.1U_040 2_16V4Z

GSENSOR @

2

EC_SMB_ DA2 <1 7,32,34>

@U G4

@

VDD

NC NC NC NC NC

VSS

HDPLOCK <32>

12

Compal Electronics, Inc.

SPI ROM/LID/Debug/KB/G-Sen

PHQAA LA-6832P M/B

Monday, September 06, 2010

+3VS_HD P

6

1 8 11 12 14

5

33 45

0.1

5

3

For EMI request

4

ACES_85201-040 5N

+3VL

R395

100K_0402_5 %

1 2

1

C458

0.1U_0402_25 V6

@

2

JPOWER

G1 G2

@

ON/OFFBTN#

1

2

3

4

5 6

PWR_ON_LE D#

ON/OFFBTN#

ON/OFFBTN# <32>

EC_ON<16,32 ,39>

R396

10K_0402_5%

1 2

R22 390_0402_5%R22 390_040 2_5%

1 2

ON/OFFBTN#

PWR_ON_LE D#

Power Button

For debug

TOP side

SW3

D D

BTM side

1

2

SMT1-05-A_4P

5

6

61

Q7A

Q7A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

2

+5VALW

4

51_ON# < 36>

D83

2

1

3

PJSOT05C_SOT2 3-3

3

Caps Sensor/Light Sensor Conn.

JCS

@JCS

@

ESB_DAZ ESB_CKZ CAP_INT# CAP_RST#

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

P-TWO_161 021-10021

+5VALW

FBMA-11-100505-30 1T_0402

ESB_DAT< 32>

ESB_CK<32> CAP_INT#<32> CAP_RST#<3 2>

FBMA-11-100505-30 1T_0402

L13

L13 L14

L14

EC_SMB_CK2<17,32,33> EC_SMB_DA2<17,32,33>

+3VL +3VS

1 2 1 2

For EMI

R428

@ R428

ESB_DAZ

ESB_CKZ

@

1 2

100_0402_5 %

@ R427

@

1 2

100_0402_5 %

R427

C260

@C260

@

1 2

100P_0402_5 0V8J

C261

@C261

@

1 2

100P_0402_5 0V8J

2

1

Touchpad & Light Pipe Connector

SW1

3

1

2

4

SMT1-05_4P

5

6

SW4

3

1

2

4

SMT1-05_4P

5

6

TP_CLK< 32> TP_DATA<32>

TP_LED<3 2>

+5VS

KSI6<16,32,33> KSO0<32,33>

5

2N7002DW -T/R7_SOT363-6

3

4

SW_L SW_R

TP_LED# KSI6 KSO0

Q7B

JTPL

@JTPL

@

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

P-TWO_161 021-10021

SW_L

SW_R

8/30 Change SW1, SW4 to SN100002Y00

Screw Hole

H12

H13

H11

H5

H6

DC-IN LED

2

DC_IN

C C

1 3

D

2N7002_SOT2 3-3

G

Q32

S

ACIN <18 ,32,38>

WiMAX LED

WIMAX_LED_GND#

+5VS

WIMAX_LED_GND#

R506

1 2

0_0402_5%

@

R819

12

10K_0402_5%

5

WIMAX@

3

Q156B 2N7002DW -T/R7_SOT363-6

WIMAX@

2

6 1

Q156A

Q156A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

WIMAX@

4

LED_WIMAX# <27>

1

H1

1

H_3P0

@

H_2P7x3P2N

@

H6

H_3P0

@

1

H26

H_2P7N

@

1

H9

H8

H_3P0

@

1

H11

H10

H_3P0

@

1

H13

H14

H_3P0

@

1

H14

H_3P0

@

1

HDD LED

R404

+5VS

10K_0402_5%

HDD_LED#

B B

A A

3

Q9B 2N7 002DW-T/R7_SOT 363-6Q9B 2N70 02DW-T/R7_SOT3 63-6

12

6 1

5

4

1 2

R50 0_0402_5%

5

2

Q9A

Q9A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

@

PWR_SUSP_ LED#<32>

BATT_FULL_LED #<3 2>

BATT_CHG_LOW _LED#<32>

CR_LEDCON#<29>

SATA_LED# <16>

Logo LED

+5VS

HT-SV116BP_W HITE

1 2

R774 120_0402_ 5%R774 120_ 0402_5%

1 2

R776 120_0402_ 5%R776 120_ 0402_5%

HT-SV116BP_W HITE

D22

2 1

D20

LOGO_LED#

5

3

4

2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6 Q6B

Q6B

LOGO_LED <21>

CPU

H22

H23

H21

H20

H_4P2x4P7

H_4P2

@

1

H_4P2x4P7

@

1

H23

H_4P7

@

1

PCB Fedical Mark PAD

FD2@FD2

FD1@FD1

@

LED/B Connector

JLED

@JLED

@

+5VALW

+5VS

WIMAX_LED_GND#

WL_BT_L ED#<21>

PWR_ON_LE D#<32>

WL_BT_L ED# DC_IN PWR_ON_LE D# PWR_SUSP_ LED# HDD_LED# CR_LEDCON# BATT_FULL_LED # BATT_CHG_LOW _LED#

1

2

3

4

5

6

7

8

9

10

11

12

ACES_85201-120 5N

4

13

GND

14

GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPER TY OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPER TY OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2010/09/03 2012/12/31

Compal Secret Data

ISPD

Deciphered Date

1

2

FD4@FD4

FD3@FD3

@

1

U2

Q65R1@U2

Q65R1@

PCH

U2

Q67R1@U2

Q67R1@ PJP1

PCH

U2

Q67R3@U2

Q67R3@

PCH

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR/Cap./TP/LED/LP/LS/Screw

Monday, September 06, 2010

MINI CARD -- 3G

H15

H16

H_3P3

@

1

MINI CARD -- WLAN

H18

H19

H_3P3

@

1

ZZZ

PCB LA-6832P

PJP1

PHQAA LA-6832P M/B

34 45

1

H17

H_3P3

@

1

H_3P3

@

1

45@PJP1

45@

0.1

A

+3VALW TO +3VS

+3VALW +3VS

Q29

1

8

S

D

2

7

S

D

3

6

S

D

4

5

G

1 1

SI4800BDY_SO8

1

C465

2

4.7U_0805_10V4Z

D

0.022U_0402_25V7K

Vgs=10V,Id=9A,Rds=18.5mohm

1

C459

C459 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

12

C466

R412

R412 330K_0402_5%

330K_0402_5%

2

1

C460 4.7U_0805_10V4ZC460 4.7U_0805_10V4Z

2

R409

1 2

61

+VSB

47K_0402_5%

Q10A

SUSP S USP SUSP

2

2N7002DW-T/R7_SOT363-6

R406

470_0805_5%

1 2 3

Q10B

5

4

+5VALW

4.7U_0805_10V4Z

1

2

B

Q30

8

D

7

D

6

D

5

G

D

SI4800BDY_SO8

C467

C

+5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm

+5VS

1

S

2

S

3

S

4

1

12

R413

C468

200K_0402_5%

2

@

0.01U_0402_25V7K

1

C461

C461 1U_0402_6.3V6K

1U_0402_6.3V6K

2

61

4.7U_0805_10V4Z

1

C462

2

R410

1 2

+VSB

47K_0402_5%

Q11A

2

2N7002DW-T/R7_SOT363-6

5

R407

470_0805_5%

1 2 3

Q11B

4

+5VS

For EMI

2

C821

C822

@

1

0.1U_0402_16V4Z

+1.5V

Vgs=10V,Id=14.5A,Rds=6mohm

Q31

8

D

7

D

6

D

5

D

FDS6676AS_SO8

1

C469

2

4.7U_0805_10V4Z

D

+1.5V to +1.5VS

+1.5VS

1

S

2

S

2

3

S

4

G

1

C470

2

0.1U_0402_25V6

C463

C463 1U_0402_6.3V6K

1U_0402_6.3V6K

12

R414

R414 820K_0402_5%

820K_0402_5%

4.7U_0805_10V4Z

C464

1 2

220K_0402_5%

61

2N7002DW-T/R7_SOT363-6

1

2

R411

+VSB

Q12A

2

2N7002DW-T/R7_SOT363-6

E

+1.8VS

R470

R470 470_0805_5%

470_0805_5%

R408

470_0805_5%

1 2 3

Q12B

5

4

1 2

13

D

Q190

2N7002_SOT23-3

S

SUSP

2

G

For S3 CPU Power Saving

+3VALW

R425

R425 100K_0402_5%

100K_0402_5%

1 2

3

Q44B

Q44B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5

4

Q44A

0.75VR_EN

61

2

2 2

3 3

VCCPPWRGD<41,42>

1 2

R158 100K_0402_5%R158 100K_0402_5%

2N7002DW-T/R7_SOT363-6

SUSP

0.75VR_EN# <42>

+5VS_ODD

R457

470_0805_5%

1 2 61

Q53A

2

2N7002DW-T/R7_SOT363-6

ODD_EN#<21>

ODD_EN#

SUSP<5,9,42>

SUSP#<16,27,32,40,42>

S

2N7002_SOT23-3

+3VS

G

Q51

2

+5VALW

R422

R422 100K_0402_5%

100K_0402_5%

1 2

SUSP

61

Q6A

2

2N7002DW-T/R7_SOT363-6

+5VS TO +5VS_ODD

+5VS

R441

R441 10K_0402_5%

10K_0402_5%

R440

1 2

13

1 2

D

47K_0402_5%

+0.75VS

2

C471

0.1U_0402_16V7K

1

2

AO3413_SOT23

C217

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

R421

22_0805_5%

1 2

13

D

Q189

SUSP

2

G

2N7002_SOT23-3

S

+5VS

Vgs=-4.5V,Id=3A,Rds<97mohm

2

S

Q45

C679

Q45

G

2

@

2

1

D

1 3

1

2

+1.05VS_VCCP

R468

R468 470_0805_5%

470_0805_5%

1 2

13

D

2

G

S

PJ28

PJ28 JUMP_43X79

JUMP_43X79

@

1

C680

C680 1U_0402_6.3V6K

1U_0402_6.3V6K

2

Q60

Q60 2N7002_SOT23-3

2N7002_SOT23-3

+5VS_ODD

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/09/03 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet

DC-DC INTERFACE

PHQAA LA-6832P M/B

Monday, September 06, 2010

E

35 45

0.1

of

35 45

A

B

C

D

PreCHG

PR1

PR2

PR5

PR6

PR17

PD2

2

1

3

RB715F_SOT323-3

RTC Battery

@

PBJ1

MAXEL_ML1220T10

SP093MX0000

PD1

LL4148_LL34-2

PR3

100K_0402_5%

2

+-

12

13

DTC115EUA_SC70-3

PR12

1 2

560_0603_5%

PQ2

12

PR4

100K_0402_5%

1 2

560_0603_5%

PD3

RLS4148_LL34-2

12

PR9

PR9 68_1206_5%

68_1206_5%

PC5

0.1U_0603_25V7K

+1.05VS_VCCPP +1.05VS_VCCP+1.8VS+1.8VSP +3VLP +3VL

VIN

12

PC4

100P_0402_50V8J

VS

@

+1.5VP

(16A,640mils ,Via NO.= 32)

2

JUMP_43X118

@ PJ402

@

2

JUMP_43X118

@ PJ403

@

2

JUMP_43X118

(17A,680mils ,Via NO.=34)

JUMP_43X118

PJ152

PJ402

PJ403

VIN

+5VALWP<39>

112

+1.5V

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

ACOFF<32,38 >

PL1

SMB3025500YA_2P

PF1

DC301001M80

@

PJP1

1

+

2

1 1

+

3

-

4

-

SINGA_2DW -0005-B03

PF1

DC_IN_S1 DC_IN_S2

21

10A_125V_451010MRL

12

PC1

1000P_0402_50V7K

SMB3025500YA_2P

1 2

12

PC2

100P_0402_50V8J

12

PC3

1000P_0402_50V7K

VIN

1 2

12

PR8

68_1206_5%

PQ4

TP0610K-T1-E3_SOT23- 3

PD4

RLS4148_LL34-2

100K_0402_1%

1 2

22K_0402_1%

+3VALW

+5VALW

PR11

12

PR10

12

+0.75VSP

2 2

+3VALWP

(5A,200mils ,Via NO.= 10) OCP=8.6A

+5VALWP

3 3

(5A,200mils ,Via NO.= 10) OCP=7.9A

(1.65A,70mils ,Via NO.= 4) OCP=4.2A

BATT+

@

PJ332

2

JUMP_43X118

PJ352

@ PJ352

@

2

JUMP_43X118

PJ182

@ PJ182

@

2

JUMP_43X118

51_ON#<34>

112

TP0610K-T1-E3_SOT23- 3

N1

PC6

0.22U_0603_25V7K

2

JUMP_43X79

(1A,40mils ,Via NO.= 2)

(6A,240mils ,Via NO.= 12)

(100mA,40mils ,Via NO.= 2)

JUMP_43X79

2

JUMP_43X118

2

JUMP_43X39

2

PJ76

@ PJ76

@

112

PJ452

@ PJ452

@

112

PJ333

@ PJ333

@

112

13

12

+0.75VS

+VCCSA+VCCSAP

PQ1

TP0610K-T1-E3_SOT23- 3

2

12

13

2

DTC115EUA_SC70-3

PR13

13

PR7

100K_0402_5%

PQ3

+RTCBATT

B+

PJ2

@

+VSBP +VSB

2

JUMP_43X39

112

(120mA,40mils ,Via NO.= 1)

VL +5VL

(100mA,40mils ,Via NO.= 2)

@ PJ353

@

2

JUMP_43X39

PJ353

PJ502

@

112

+GFX_COREP

(33A,1320mils ,Via NO.=66) OCP=40A

2

JUMP_43X118

PJ503

@ P J503

@

2

JUMP_43X118

112

+GFX_CORE

ACIN

4 4

Precharge detector

Min. typ. Max. H-->L 14.42V 14.74V 15.23V L-->H 15.39V 15.88V 16.39V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2009/04/282009/11/13

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DCIN/VIN DECTOR

NHQAA LA-6831P M/B

D

36 58Monday, September 06, 2010

0.1

A

B

C

D

1 1

@

PJP2

1

2

3

4

5

5 GND GND GND GND

6

7

8

9

10 11 12 13

SUYIN_200045MR009G171ZR

2 2

3 3

EC_SMCA

PR20

100_0402_1%

BATT_S1

BATT_P4 BATT_P5 EC_SMDA

1 2

1

2

VL

PR25

100K_0402_1%

POK<18,39>

1 2

.1U_0402_16V7K

PD5

@ PD5

@

PJSOT24C_SOT23-3

3

PR21

PR21 100_0402_1%

100_0402_1%

1 2

PR26

1 2

0_0402_5%

PC12

@ PC12

@

PF2

21

15A_65V_451015MRL

12

PR14

PR14 1K_0402_1%

1K_0402_1%

PD6

@ PD6

@

PJSOT24C_SOT23-3

2

3

12

PR19

1K_0402_1%

B+

13

2

G

12

1

6.49K_0402_1%

PR24

1 2

22K_0402_1%

D

PQ6

PQ6 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR16

12

PC10

PR23

@

100K_0402_1%

0.22U_0603_25V7K

VMB

12

PC7

1000P_0402_50V7K

+3VLP

BATT_TEMPA <32 >

EC_SMB_DA1 <15,32>

EC_SMB_CK1 <15,32>

PQ5

TP0610K-T1-E3_SOT23- 3

2

13

PL2

SMB3025500YA_2P

1 2

H_PROCHOT#<5,32>

SSM3K7002FU_SC70-3

12

PC11

@PC11

@

0.1U_0603_25V7K

12

PC8

0.01U_0402_25V7K

PQ7

+VSBP

BATT+

13

D

S

+3VS

PR29

100K_0402_1%

2

G

PH1 under CPU botten side :

CPU thermal protection at 95 degree C Recovery at 56 degree C

VL

0.1U_0603_25V7K

1 2

PC9

12

PU1

1

VCC

2

GND

VS_ON<39>

3

OT1

4

OT2

G718TM1U_SOT23-8

TMSNS1

RHYST1

TMSNS2

RHYST2

8

7

6

5

1 2

PR28

8.66K_0402_1%

12

PR15

19.6K_0402_1%

PR18

8.66K_0402_1%

1 2

12

PR22

19.6K_0402_1%

PR27

8.66K_0402_1%

1 2

12

PH1

100K_0402_1%_NCP15W F104F03RC

ADP_I <32, 38>

100K_0402_1%_NCP15W F104F03RC

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2009/04/282009/11/13

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

NHQAA LA-6831P M/B

D

37 58Monday, September 06, 2010

0.1

A

PQ203 AO4435_SO8

65W@

PQ203 AO4435_SO8

75W@

PQ203 AO4407A_SO8

90W@

PQ203

120W@ PQ203

120W@

AO4407A_SO8

VIN

1 1

12

PR210

200K_0402_1%

DTA144EUA_SC70-3

BATT_ON

2 2

3 3

2

61

D

2

G

PQ212A

S

DMN66D0LDW -7_SOT363-6

PACIN

ACOFF<32,36>

8 7

5

PQ210

2

13

PQ211

PQ211 DTC115EUA_SC70-3

DTC115EUA_SC70-3

DMN66D0LDW -7_SOT363-6

PR211

47K_0402_5%

1 2

PQ213

DTC115EUA_SC70-3

ACOFF

1 3

2

1 2 36

4

12

PC210

PQ212B

5

G

13

PQ204 AO4407A_SO8

65W@

PQ204 AO4407A_SO8

75W@

PQ204 AO4407A_SO8

90W@

P2 P3

12

0.1U_0603_25V7K

12

34

D

S

IREF<32>

PQ204

120W@ PQ204

120W@

AO4407A_SO8

1 2 3 6

4

PR212

PR212 200K_0402_1%

200K_0402_1%

PR213

150K_0402_1%

ADP_I<32,37>

PR220

154K_0402_1%

120K_0402_1%

CPSETIN<32>

2N7002W- T/R7_SOT323-3

FSTCHG<32>

PR221

12

8 7

5

PC211

PC211 5600P_0402_25V7K

5600P_0402_25V7K

1 2

PC214

1 2

0.01U_0402_25V7K

12

PC216

2

G

PQ218

10K_0402_1%

6251VREF 6251aclim

0.01U_0402_25V7K

13

D

<32>

S

PR216

100K_0402_1%

PR218

1 2

10K_0402_1%

PC215

1 2

.1U_0402_16V7K

120W@

PR222

1 2

8.25K_0402_1%

CHGVADJ

B

PR215 0.015_1206_1%

120W@

PR215 0.015_1206_1%

90W@

PR215 0.02_1206_1%

75W@

PR215

65W@ PR215

65W@

0.02_1206_1%

1

2

ACSETIN

12

PR217

PC213

1 2

6800P_0402_25V7K

1 2

47K_0402_1%

12

PR234

PR223

120W@ PR234

120W@

120W@ PR223

120W@

26.7K_0402_1%

PR224

1 2

15.4K_0402_1%

@

PC207

B+

4

3

6251VDD

12

PC212

2.2U_0603_6.3V6K

1

2

6251_EN CSON

3

4

5

6251VREF

PR225

31.6K_0402_1%

1 2

6

7

8

9

10

11

12

PR219

26.7K_0402_1%

12

@

12

PC208

PC209

10U_1206_25V6M

RB751V-40_SOD323-2

10_1206_5%

PU200

VDD

DCIN

ACSET

ACPRN

EN

CSON

CELLS

CSOP

ICOMP

CSIN

VCOMP

CSIP

PHASE

ICM

UGATE

VREF

CHLIM

BOOT

ACLIM

VDDP

VADJ

LGATE

PGND

GND

G5209S31U_SSOP24

12

10U_1206_25V6M

HCB2012KF-121T50_0805

VIN

PD201

1 2 12

PR227

DCIN

24

0.1U_0603_25V7K

23

22

21

PR231 20_0402_5%PR231 20_04 02_5%

20

19

1 2

LX_CHG

18

DH_CHG

17

BST_CHG

16

6251VDDP

15

DL_CHG

14

13

PL201

1 2

PreCHG

12

PC217

1000P_0402_25V8J

PC218

12

ACPRN <39>

PR229 20_0402_5%PR229 20_0402_5 %

PC219

0.047U_0402_16V7K

1 2

PR230

PC220

0.1U_0603_25V7K

PR232 2_0402_5 %PR232 2_0402_5%

PR205

1 2

0_0603_5%

PC221

4.7U_0603_6.3V6M

1 2

CSIN

CSIP

PR226

191K_0402_1%

ACSETIN

PR228

14.3K_0402_1%

1 2

20_0402_5%

12

1 2

BST_CHGA

12

0.1U_0603_25V7K

PD202

PD202 RB751V-40_SOD323-2

RB751V-40_SOD323-2

1 2

PR233 4.7_ 0603_5%PR233 4.7_0603_5%

6251VDD

PC205

C

PC231

CSOP

12

6251VDD

D

PQ208 AO4407A_SO890W@ PQ208 AO4407A_SO890W @

4

PQ207 AO4435_SO865W@ PQ207 AO4435_SO865W @

4

PR236

1 2

47K_0402_1%

ACPRN

2N7002W- T/R7_SOT323-3

4

3

8 7

5

8 7

5

12

PC222

2200P_0402_25V7K

PQ216

12

PC202

10U_1206_25V6M

PQ208 AO4407A_SO8

120W@

PQ207 AO4435_SO8

75W@

PQ207 AO4407A_SO8

90W@

PQ207 AO4407A_SO8

120W@

VIN

13

D

2

G

S

@

12

PC203

10U_1206_25V6M

PC204

10U_1206_25V6M

BATT+

12

1 2

PR237

10K_0402_1%

1 2 13

100K_0402_1%

BATT_ON

3 6

1 2 3 6

2

12

PR238

CHGCHG

1

2

0.02_1206_1%

PR235

CHG_B+

12

PC232

4.7U_0805_25V6-K

AO4466_SO8

PC233

PQ202

12

4.7U_0805_25V6-K

PQ215

PQ201

PQ201 AO4466_SO8

AO4466_SO8

PL202

10UH_MSCDRI-104A-10 0M-E_4.6A_20%

PL202

1 2

12

PR206

@ PR206

@

4.7_1206_5%

12

PC206

@PC2 06

@

680P_0603_50V7K

578

3 6

578

3 6

241

DTC115EUA_SC70-3

12

4.7U_0805_25V6-K

VIN

PR241

12

PR240

47K_0402_1%

EN0<39>

PR222 75K_0402_1%

65W@

PR222 24K_0402_1%

75W@

PR222 53.6K_0402_ 1%

90W@

CP mode

Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A

4 4

Vaclim=1.08V(65W) PR222=75k PR223=20k PR45=0.02

Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A

Vaclim=0.736V(75W)

Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A

Vaclim=0.736V(90W)

Iada=0~6.316A(120W) CP= 92%*Iada; CP=5.81A

Vaclim=0.736V(120W)

PR223 20K_0402_1%

65W@

PR223 20K_0402_1%

75W@

PR223 20K_0402_1%

90W@

PR222=24k PR223=20k PR45=0.02

PR222=53.6k PR223=20k PR45=0.015

PR222=8.25k PR223=26.7k PR45=0.015

A

2N7002W- T/R7_SOT323-3

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

CHGVADJ=(Vcell-4)*9.445

Vcell

4V

4.2V

4.35V

CHGVADJ

0V

1.882V

3.2935V

PR244

PQ217

13

D

2

G

S

PR244

10K_0402_1%

1 2

12

PC224

PC224 .1U_0402_16V7K

.1U_0402_16V7K

ACPRN

-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2009/04/28

12

PR242

PR242 10K_0402_1%

10K_0402_1%

13

2

PR241

10K_0402_1%

1 2

PQ214

PQ214 DTC115EUA_SC70-3

DTC115EUA_SC70-3

12

PR243

14.3K_0402_1%

Compal Secret Data

Deciphered Date

C

ACIN <18,32,34>

PACIN

Vin Detector

High Low

18.089V

17.44V

12

PR246

309K_0402_1%

12

PR248

47K_0402_1%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

PR247

10K_0402_1%

1 2

12

PC223

PC223 .1U_0402_16V7K

.1U_0402_16V7K

CHARGER

NHQAA LA-6831P M/B

D

38 58Monday, September 06, 2010

ADP_V <32>

0.1

5

4

3

2

1

2VREF_8205

D D

RT8205_B+

PL331

HCB2012 KF-121T50_080 5

+3VALWP

220U_6.3 V_M

VS

12

PC332

1 2

100K_04 02_1%

PR373

1 2

200K_04 02_1%

12

PC360

10U_120 6_25V6M

1

+

2

PR371

13

PL332

4.7UH_SIL1 045R-4R7PF_6.3A _30%

PL332

1 2

4.7_1206 _5%

@P C336

@

680P_06 03_50V7K

DMN66D0 LDW-7_SOT3 63-6

VL

VS_ON<37 >

2N7002W -T/R7_SOT32 3-3

PQ362

2

G

13

D

S

PR336

@P R336

@

PC336

PR370

100K_04 02_1%

PR372

PQ360A

12

6

578

PQ331

AO4466L _SO8

4

123

786

12

123

61

D

S

12

PC370

42.2K_0402_1%

2.2U_0603_10V6K

0.1U_060 3_25V7K

5

PQ332

4

AO4712L _SO8

ENTRIP1 ENTRIP2

2

G

2

B+

5

G

13

PQ361

PQ361 DTC115E UA_SC70-3

DTC115E UA_SC70-3

B+

C C

Ipeak=6.97A Imax=4.88A F=375KHz

B B

Total Capacitor ??uF, ESR ??mohm

ACPRN<3 8>

A A

12

PC361

4.7U_0805_10V6K

PC335

1 2

499K_04 02_1%

1 2

1U_0402 _6.3V6K

34

D

PQ360B

DMN66D0 LDW-7_SOT3 63-6

S

+3VLP

PR360

PR335

1 2

0_0603_ 5%

EN0<38>

PC362

12

BST_3V

UG_3V

LX_3V

LG_3V

1U_0603 _10V6K

PR362

13K_040 2_1%

1 2

PR363

20K_040 2_1%

1 2

PR337

150K_04 02_1%

1 2

PU330

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

PR361

100K_0402_5%

2VREF_8205

12

PC363

ENTRIP2

6

5

FB2

ENTRIP2

SKIPSEL

EN

14

13

RT8205_B+

4

3

REF

TONSEL

VIN16GND

15

12

PR364

30K_040 2_1%

1 2

PR365

19.1K_04 02_1%

1 2

ENTRIP1

PR357

150K_04 02_1%

1 2

1

2

FB1

ENTRIP1

24

VO1

23

PGOOD

22

BOOT1

21

UGATE1

20

PHASE1

19

LGATE1

NC18VREG5

S IC UP6182C QAG VQFN 24P PW M

17

12

PC364

4.7U_080 5_10V6K

PC365

0.1U_060 3_25V7K

VL

BST_5V

UG_5V

LX_5V

LG_5V

PR355

1 2

0_0603_ 5%

10U_120 6_25V6M

POK <18,37>

PC355

0.1U_060 3_25V7K

1 2

RT8205_B+

12

PC366

PQ352

AO4712L _SO8

6

578

PQ351

4

AO4466L _SO8

123

PL352

4.7UH_SIL1 045R-4R7PF_6.3A _30%

786

5

4

12

123

PL352

1 2

@

PR356

4.7_1206 _5%

@

PC356

PC356 680P_06 03_50V7K

680P_06 03_50V7K

+5VALWP

1

+

PC352

2

Ipeak=3.98A Imax=2.8A F=300KHz Total Capacitor ??uF, ESR ??mohm

220U_6.3V_M+PC352

220U_6.3V_M

EC_ON<1 6,32,34>

2

PQ363

DTC115E UA_SC70-3

5

4

Security Class ification

2009/11/ 13 2009/04/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/11/ 13 2009/04/ 28

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document N umber Rev

Monday, September 06, 2010

Date: Sheet of

3VALWP/5VALWP

NHQAA LA-6831P M/B

1

39 58

0.1

A

1 1

PR160

SYSON<30,32>

+5VALW

2 2

1 2

0_0402_5%

PR161

1 2

100_0603_5%

4.7U_0603_6.3V6K

PC161

12

PC160

.1U_0402_16V7K

12

@

12

PR162

1 2

10K_0402_1%

PR163

PR163 10K_0402_1%

10K_0402_1%

1

PU150

2

TON

EN_SKIP

3

OUT

4

VCC

VFB=0.75V

5

FB

6

PGOOD

B

255K_0402_1%

BST_1.5V

14

15

TP

BST

DH

LX

ILIM

VDD

AGND7PGND

DL

G5603RU1U_TQFN14_3P5X3 P5

8

PR164

1 2

13

12

11

10

9

PR155

1 2

0_0603_5%

DH_1.5V

LX_1.5V

PR157

1 2

10K_0402_1%

DL_1.5V

BST_1.5V-1

PC155

1 2

0.1U_0603_25V7K

+5VALW

PC162

4.7U_0805_10V6K

1 2

578

3 6

578

3 6

241

C

1.5_B+

PQ151

AO4466_SO8

PQ152

PQ152 AO4712_SO8

AO4712_SO8

12

PC163

4.7U_0805_25V6-K

PL152

UMA@ PL152

UMA@

1.8UH_SIL104R-1R8PF_9.5A _30%

12

PR156

@PR1 56

@

4.7_1206_5%

12

PC156

@PC1 56

@

680P_0603_50V7K

HCB2012KF-121T50_0805

12

PC164

4.7U_0805_25V6-K

12

PL151

12

1

+

PC152

PC152 220U_6.3V_M

220U_6.3V_M

2

D

B+

12

PC165

@ PC165

@

680P_0402_50V7K

PC228

PC225

@ PC228

@

@ PC225

@

10U_1206_25V6M

12

+1.5VP

Ipeak=19.6A I

max=13.72A F=294KHz Total Capacitor ??uF, ESR ??mohm

PU180

10

12

PC185

@PC185

@

0.1U_0402_10V7K

PU180

4

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

LX

3

LX

6

FB

NC

1

Issued Date

LX_1.8V

FB=0.6Volt

1UH_FMJ-0630T-1R 0 HF_11A_20%

PR186

PC186

2010/01/25 2009/04/28

12

1 2

4.7_1206_5%

680P_0603_50V7K

PL182

PR183

20K_0402_1%

FB_1.8V

Compal Secret Data

12

PC187

68P_0402_50V8J

12

PR184

10K_0402_1%

Deciphered Date

C

12

+1.8VSP

12

PC183

PC182

22U_0805_6.3VAM

Ipeak=1.308A ILIM = 4A F=1MHz Total Capacitor ??uF, ESR ??mohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.5VP/+1.8VSP

NHQAA LA-6831P M/B

D

40 58Monday, September 06, 2010

0.1

SY8033BDBC_DFN10_3X3

PJ181

@ PJ181

3 3

4 4

A

+5VALW

2

SUSP#<16,27,32,35,42>

@

112

JUMP_43X39

12

PC184

PC184 22U_0805_6.3VAM

22U_0805_6.3VAM

PR181

1 2

0_0402_5%

499K_0402_1%

@

EN_1.8V

PR182

SY8033BDBC_DFN10_3X3

12

B

5

D D

PR460

VCCPPWRGD<35,42>

PR461

100_0402_1%

+5VALW

C C

1 2

4.7U_0805_10V6K

PC461

1 2

0_0402_5%

12

PC460

@PC460

@

.1U_0402_16V7K

PR471

12

1 2

+3VS

10K_0402_1%

SA_PGOOD<32>

FB

1 2

PU450

2

TON

3

OUT

4

VCC

5

FB

6

PGOOD

PR472

@ PR472

@

10K_0402_1%

1

EN_SKIP

15

TP

AGND7PGND

4

PR462

1 2

255K_0402_1%

PR455

BST_VCCSAP

14

BST

G5603RU1U_TQFN14_3P5X3P5

8

PR455

1 2

2.2_0603_5%

13

DH

12

LX

1 2

11

ILIM

10K_0402_1%

10

VDD

9

DL

DH_VCCSAP

LX_VCCSAPVOUT

PR457

DL_VCCSAP

BST_VCCSAP-1

+5VALW

PC455

1 2

0.1U_0603_25V7K

1 2

PC462

4.7U_0805_10V6K

578

3 6

578

3 6

241

PQ451

PQ451 AO4466_SO8

AO4466_SO8

1.8U_D104C-919AS-1R8N_9.5A_30%

12

PQ452

PQ452 AO4712_SO8

AO4712_SO8

3

VCCSAP_B+

12

PC463

4.7U_0805_25V6-K

PL452

1 2

PR456

@ PR456

@

4.7_1206_5%

PC456

@ PC456

@

680P_0603_50V7K

2

PL451

HCB2012KF-121T50_0805

12

PC464

4.7U_0805_25V6-K

12

PC466

PC465

0.1U_0402_25V6

2200P_0402_50V7K

B+

Ipeak=6A Imax=4.2A F=276K Toatal Capacitor ??u

1

ESR=??mohm

+VCCSAP

1

+

PC452

PC452 390U_2.5V_M

390U_2.5V_M

12

PR463

PR463 0_0402_5%

0_0402_5%

12

PR465

PR465 680_0402_1%

680_0402_1%

2

PR464

10_0402_5%

12

VCCSA_SENSE <9>

PR469

10K_0402_1%

1 2

.1U_0402_16V7K

+3VS

12

PR468

PR468 10K_0402_1%

10K_0402_1%

PR470

@ PR470

@

1 2

100K_0402_1%

PMBT2222A_SOT23-3

PQ454

1

2

3

PR473

0_0402_5%

1 2

VCCSAP_VID1 <9>

12

PR466

9.09K_0402_1%

SSM3K7002FU_SC70-3

B B

PQ453

12

13

D

S

PR467

5.1K_0402_1%

2

G

12

PC470

VID1 +VCCSAP

100.8V

0.9V

A A

Security Classification

Issued Date

THIS SHEET OF ENGINE ERING DRAW ING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINE ERING DRAW ING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSF ERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSF ERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSF ERED FROM THE C USTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMENT EX CEPT AS AUTHORIZE D BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZE D BY COMPAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/01/25 2009/04/28

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

+VCCSAP/+1.0VSDGPUP

NHQAA LA-6831P M/B

1

41 58Monday, September 06, 2010

0.1

5

4

3

2

1

+1.5V

1

PJ75

@P J75

@

1

JUMP_43 X79

2

D D

PR282

@P R282

@

0_0402_ 5%

SUSP<5,9,35>

0.75VR_EN#<35>

C C

PR410

0_0402_ 5%

SUSP#<16,27,32,35,40>

PR411

100_060 3_1%

+5VALW

B B

1 2

4.7U_060 3_6.3V6K

PC411

1 2

12

4.02K_04 02_1%

1 2

12

PR413

10K_040 2_1%

PR412

12

PC410

@

.1U_0402 _16V7K

VCCPPW RGD< 35,41>

1 2

PR279

0_0402_ 5%

1 2

PC260

.1U_0402 _16V7K

1 2

12

PU400

2

TON

3

OUT

4

VCC

5

FB

6

PGOOD

PR415

1 2

10K_040 2_1%

PR416

@P R416

@

10K_040 2_1%

2

G

1

EN_SKIP

VFB=0.75V

AGND7PGND

+3VALW

2

4.7U_080 5_6.3V6K

1 2

13

D

PQ260

S

SSM3K7002FU_SC70-3

PR414

255K_04 02_1%

1 2

15

14

TP

BST

13

DH

12

LX

11

ILIM

10

VDD

9

DL

G5603RU 1U_TQFN14_3P 5X3P5

8

PC261

PR280

1K_0402 _1%

PR281

BST_1.05 VS_VCCP

DH_1.05V S_VCCP

LX_1.05V S_VCCP

PR407

1 2

13.7K_04 02_1%

DL_1.05V S_VCCP

12

PC263

1K_0402_1%

For shortage changed

PR405

0_0603_ 5%

1 2

12

.1U_0402_16V7K

PU75

VIN1VCNTL

2

GND

3

VREF

4

VOUT

UP7711U 8 PSOP 8P

+0.75VSP

12

PC262

PC262 10U_080 5_6.3V6M

10U_080 5_6.3V6M

PC405

0.1U_060 3_25V7K

1 2

+5VALW

1 2

PC412

4.7U_080 5_10V6K

6

5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC264

1U_0603 _10V6K

PL401

HCB4532 KF-800T90_181 2

12

1 2

HCB4532 KF-800T90_181 2

1 2

PC415

4.7U_0805_25V6-K

1

+

PC402

PC402 390U_2.5 V_M

390U_2.5 V_M

2

PR420

0_0402_5%

PR421

10_0402 _5%

12

B+

+1.05VS_VCCPP

VCCIO_SEN SE <8 >

1.05VS_B +

5

PQ401

TPCA8030-H_SOP-ADV8-5

4

123

5

4

213

PQ402

TPCA8028-H_SOP-ADVANCE8-5

12

PC413

PC414

4.7U_0805_25V6-K

PL402

PR406

@P R406

@

4.7_1206 _5%

PC406

@ PC406

@

680P_0603_50V7K

PL402

1UH_FDU E1040D-1R0M-P3 _21.3A_20%

12

A A

Security Class ification

2010/01/ 25 2009/04/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/ 25 2009/04/ 28

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Custom

Date: Sheet of

2

Date: Sheet of

+1.05VS_VCCP/+0.75VSP

NHQAA LA-6831P M/B

42 58Monday, Sep tember 06, 2010

1

0.1

5

12

PR530

8.06K_0402_1%

GFX@PR5 30

8.06K_0402_1%

GFX@

12

PR531

@ PR531

@

499K_0402_1%

D D

VR_SVID_DAT<8>

VR_SVID_ALRT#<8>

VR_SVID_CLK<8>

C C

12

PC561

PR542

19.1K_0402_1%

0.033U_0603_16V7

VR_HOT#<32>

0.033U_0603_16V7

12

+1.05VS_VCCPP

1 2

@

PR543

499_0402_1%

PC537

43P_0402_50V8J

12

PR546

B B

@

PR547

1 2

499K_0402_1%

150P_0402_50V8J

@PC575

@

150P_0402_50V8J

PC533

GFX@ PC533

GFX@

150P_0402_50V8J

12

PR539

GFX@PR539

GFX@

18.2K_0402_1%

+3VS

VGATE<5,18,32>

PC538 470P_0402_50V7K@ PC538 470P_0402_50V7K@

PR544

@ PR544

@

1 2

3.83K_0402_1%

8.06K_0402_1%

PC541

33P_0402_50V8J

PC543

12

PC575

12

GFX@ PC531

GFX@

39P_0402_50V7K

12

PC534

GFX@PC534

GFX@

0.047U_0603_16V7K

VR_ON<32>

PR541

1 2

1.91K_0402_1%

12

PC539

1000P_0402_50V7K

12

PR549

316K_0402_1%

PR550

@PR550

@

316K_0402_1%

VCCSENSE<8>

VSSSENSE<8>

5

UGATE1

A A

PHASE1

BOOT1

LGATE1

0.22U_0603_10V7K

PR525

0_0603_5%

4

123

PC525

12

5

12

4

PQ504

213

5

12

PC530

GFX@PC5 30

GFX@

1000P_0402_50V7K

PC531

12

PR533

GFX@ PR533

GFX@

475K_0402_1%

12

PR532

GFX@ PR532

GFX@

422_0402_1%

GFX@ PR534

GFX@

2.55K_0402_1%

12

+1.05VS_VCCPP

12

PC560

1 2

12

PH502 470KB_0402_5%_ERTJ0EV474J@ PH502 470KB_0402_5%_ERTJ0EV474J@

1 2

PR545

@ PR545

@

27.4K_0402_1%

For Turbo mode , PH502 must be changed 470K (b value = 4700)

PR548

499_0402_1%

12

CPU_B+

PQ503

TPCA8030-H_SOP-ADV8-5

4

TPCA8028-H_SOP-ADVANCE8-5

PR537

130_0402_1%

.1U_0402_16V7K

1 2

0_0402_5%

12

470P_0402_50V7K

PR551

3.83K_0402_1%

PC583

4.7U_0805_25V6-K

5

213

PR540

12

PQ506

PC542

12

TPCA8028-H_SOP-ADVANCE8-5

PR538

PC584

12

PC532

GFX@ PC532

GFX@

680P_0402_50V7K

12

PR534

54.9_0402_1%

SVID_SDA

SVID_ALERT#

SVID_SCLK

12

PC585

4.7U_0805_25V6-K

12

PR526

@

4.7_1206_5%

12

PC526

@ PC526

@

680P_0603_50V7K

4

1

VWG

2

IMONG

3

PGOODG

4

SDA

5

ALERT#

6

SCLK

7

VR_ON

8

PGOOD

9

IMON

10

VR_HOT#

11

NTC

12

VW

PC540

@

22P_0402_50V8J

PC567 0.22U_0402_6.3V6KPC567 0.22U_0402_6.3V6K

VSUM-

PC562 0.22U_0402_6.3V6KPC562 0.22U_0402_6.3V6K

PC544 0.22U_0402_6.3V6KPC544 0.22U_0402_6.3V6K

PC545 330P_0402_50V7KPC545 330P_0402_50V7K

PC546 1000P_0402_50V7KPC546 1000P_0402_50V7K

1

12

+

PC568

2

4.7U_0805_25V6-K

PR591

ISEN1

10K_0402_1%

PR592

VSUM+

3.65K_0402_1%

VSUM-

4

PC555 470P_0402_50V7K@PC555 470P_0402_50V7K@

12

PC557

GFX@PC5 57

GFX@

48

46

47

FBG

VSENG

COMPG

ISL95831CRZ-T_TQFN48_6X6

PH501 470KB_0402_5%_ERTJ0EV474JGFX@ PH501 470KB_0402_5%_ERTJ0EV474JGFX@

330P_0402_50V7K

45

RTNG

PR564 27.4K_0402_1%GFX@ PR564 27.4K_0402_1%GFX@

1 2

12

ISPG

ISNG

44

43

ISPG

ISNG

12

GFX@ PC556

GFX@

330P_0402_50V7K

1 2

GFX@ PC558

GFX@

1000P_0402_50V7K

NTCG

42

NTCG

GFX@

3.83K_0402_1%

49

GND

PR563

COMP13FB14ISEN3/ FB215ISEN216ISEN117VSEN18RTN19ISUMN20ISUMP21VDD22VIN23PROG1

ISEN2

ISEN1

ISEN3

12

1

+

PC566

2

68U_25V_M_R0.36

0.36UH_PCMC104T-R36MN1R17_30A_20%

4

3

12

PR593

1_0402_5%

12

330P_0402_50V7K

PC547 3 30P_0402_50V7KPC547 330P_0402_50 V7K

1

+

PC569

PC574

2

@

100U_25V_M

68U_25V_M_R0.36

PL504

1

2

PR594

10K_0402_1%

PR590

10K_0402_1%

12

PC556

12

PC558

PR567

@PR567

@

16.5K_0402_1%

1 2

PHASEG

UGATEG

BOOTG

39

41

40

UGG

PROG2

BOOTG

VDD+

12

PC548

1U_0603_10V6K

PR554

1.24K_0402_1%

12

PC552

@PC552

@

12

+CPU_CORE

ISEN3

12

ISEN2

12

NTCG

LGATEG

37

38

LGG

PHG BOOT2

UG2

PH2

VSSP2

LG2

VDDP

PWM3

LG1

VSSP1

PH1

UG1

BOOT1

PU500

24

PR559

1 2

0_0603_5%

PR558

1_0603_5%

12

PC549

0.22U_0603_10V7K

12

PC550

0.33U_0402_10V6K

PR555

@PR555

@

100_0402_1%

3

UGATEG

VCC_AXG_SENSE <9>

VSS_AXG_SENSE <9>

+5VALW

12

PC559

PR577

PR568

0_0603_5%

1 2

BOOT2

36

UGATE2

35

PHASE2

34

33

LGATE2

32

VDDP+

31

30

LGATE1

29

28

PHASE1

27

UGATE1

26

BOOT1

25

CPU_B+

12

+5VALW

PR557

12

PC551

@ PC551

@

PR557

12

PR556

0.022U_0402_16V7K

0.022U_0402_16V7K 11K_0402_1%

11K_0402_1%

PU501

1U_0603_10V6K

5

VCC

6

FCCM

2

PWM

3

GND

PR569

ISL6208ACRZ-T_QFN8_3X3

0_0603_5%

1 2

12

PC554

2.2U_0603_10V6K

12

PR560

DC@ PR560

DC@

7.87K_0402_1%

VSUM+

12

2.61K_0402_1%

12

PH503

PH503 10K_0402_1%_ERTJ0EG103FA

10K_0402_1%_ERTJ0EG103FA

VSUM-

BOOT

UGATE

PHASE

LGATE

PGND

1 2

PR561

@PR561

@

0_0402_5%

1 2

PR562

0_0603_5%

UGATE3

PHASE3

BOOT3

LGATE3

PHASEG

GFX@ PC505

GFX@

0.22U_0603_10V7K

BOOTG

PR505

GFX@ PR505

GFX@

0_0603_5%

LGATEG

BOOT3

1

UGATE3

8

PHASE3

7

LGATE3

4

9

Connect to +5V c an disable PWM3

+5VALW

PC535

0.22U_0603_10V7K

12

PR535

0_0603_5%

12

PC553

12

PC553

.1U_0402_16V7K

UGATE2

2

4

PC505

12

CPU_B+

5

4

123

5

12

4

213

CPU_B+

5

4

123

PHASE2

BOOT2

LGATE2

0.22U_0603_10V7K

PR515

0_0603_5%

PC515

12

5

12

4

213

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/01/25 2009/04/28

Compal Secret Data

Deciphered Date

2

CPU_B+

5

123

5

4

213

PQ507

TPCA8030-H_SOP-ADV8-5

PQ512

4

12

PC564

PC563

GFX@PC5 64

GFX@

GFX@PC5 63

GFX@

PQ501

4.7U_0805_25V6-K

GFX@PQ 501

GFX@

TPCA8030-H_SOP-ADV8-5

12

PR506

@

4.7_1206_5%

PQ502

GFX@PQ 502

GFX@

12

PC506

@ PC506

@

TPCA8028-H_SOP-ADVANCE8-5

680P_0603_50V7K

12

PC587

PC588

4.7U_0805_25V6-K

12

5

PR536

@

PQ514

12

213

PC536

@ PC536

TPCA8028-H_SOP-ADVANCE8-5

PQ505

TPCA8030-H_SOP-ADV8-5

PQ508

4

@

TPCA8028-H_SOP-ADVANCE8-5

12

PC581

PC580

4.7U_0805_25V6-K

12

5

PR516

@

PQ510

12

213

PC516

@ PC516

TPCA8028-H_SOP-ADVANCE8-5

@

TPCA8028-H_SOP-ADVANCE8-5

1 2

PL501

HCB4532KF-800T90_1812

12

PC565

GFX@PC5 65

GFX@

4.7U_0805_25V6-K

PL502

GFX@ PL502

GFX@

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PR570

GFX@PR570

GFX@

10K_0402_1%

1 2

PR572

GFX@ PR572

GFX@

7.5K_0402_1%

.1U_0402_16V7K

0.01U_0402_16V7K

ISPG

12

PC586

4.7U_0805_25V6-K

ISEN3

4.7_1206_5%

VSUM+

VSUM-

680P_0603_50V7K

12

PC582

4.7U_0805_25V6-K

ISEN2

4.7_1206_5%

VSUM+

VSUM-

680P_0603_50V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

1

4

3

2

PH504 10K_0402_1%_ERTJ0EG103FAGFX@ PH504 10K_0402_1%_ERTJ0EG103FAGFX@

1 2

PR573

GFX@ PR573

GFX@

11K_0402_1%

1 2

PC571

GFX@ PC571

GFX@

1 2

PC573

@PC573

@

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR586

12

10K_0402_1%

PR585

3.65K_0402_1%

1_0402_5%

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR580

12

10K_0402_1%

PR582

3.65K_0402_1%

1_0402_5%

Compal Electronics, Inc.

1

@

PC226

12

PC227

10U_1206_25V6M

+GFX_COREP

1_0402_5%

1 2

PC570

PR574

@ PR574

@

100_0402_1%

1 2

PL505

12

PL503

12

1

2

1

2

1

+

2

12

PC572

@ PC572

@

10K_0402_1%

PC502

GFX@

390U_2.5V_M

470P_0402_50V7K

+5VALW

+CPU_CORE

PR587

PR589

+CPU_CORE

PR581

PR588

43 58Monday, September 06, 2010

12

ISEN2

12

PR571

GFX@PR5 71

GFX@

GFX@ PC570

GFX@

.1U_0402_16V7K

1 2

12

PR575

GFX@PR5 75

GFX@

590_0402_1%

ISNG

PR576 0_0402_5%DISEN@ PR576 0_0402_5%DIS EN@

Connect to +5V c an disable G

FX portion

4

3

12

PR584

4

3

12

PR583

CPU_CORE/GFX

NHQAA LA-6831P M/B

B+

ISEN1

ISEN3

0.1

NO DATE PAGE MODIFICATION LIST PURPOSE

----------------------------------------------------------------------------------------------------------------------------------------

P36-P45 Release2010/04/201

Security Class ification

2009/11/ 13 2009/04/ 28

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/11/ 13 2009/04/ 28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Date: Sheet of

Compal Electronics, Inc.

Power PIR

NHQAA LA-6831P M/B

44 58Monday, Sep tember 06, 2010

0.1

5

4

3

2

1

HW PIR (Product Improve Record)

NWQAA LA-6832P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 GERBER-OUT DATE: 2010/09/03 NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------

Item Date Page Component Solution Request

-----------------------------------------------------------------------------------------------------------------------------------

1) 07/21 Delete 3D@,DHDMI@,DIS@,EDP@,NO3D@,OPT@,UMA@ For low cost Huron River

2) 08/11 Update room

3) 08/11 09 Change R119 change to @

4) 08/12 16 Add R442, R443 For SPI debug circuit

D D

5) 08/12 16 Change R572, R573, R574, R575, R569 from @ to mount For SPI debug circuit

6) 08/12 20 Remove USB20_P3/N3 from PCH Don't need USB20/30 BTO

7) 08/12 30 Remove DT1, JUSB20, RT14, RT20, RT23, RT24 Don't need USB20/30 BTO

8) 08/12 32 Change C449, C450, Y4 from @ to mount

9) 08/13 15 Change L8, L9 L10, L11 from SM070001600 to SM070001310 For EMI demand

10) 08/13 30 Change RT11 to @

11) 08/13 30 Change RT19 to USB30@

12) 08/13 30 Change CT3 from SE000005TN0 to SE000005T80

13) 08/13 30 Remove RT25, RT27 Don't need USB20/30 BTO

14) 08/17 5 Remove R14 For HW Review demand

15) 08/18 6 Reserve R33 For HW Review demand

16) 08/18 9 Reserve R119 To follow CRB 1.0

17) 08/18 11 Remove R92, R89 For HW Review demand

18) 08/18 12 Remove R93, R97 For HW Review demand

19) 08/18 26 Reserve C236, C268, C490 For HW Review demand

20) 08/18 15 Remove R435, R438, R453(0 ohm)

21) 08/18 15 Change R195, R197, R198, R202, R201, R203, R205, R206 to SD028680080

22) 08/18 15 Remove R207 For HW Review demand

23) 08/18 18 Change Net name from PM_CLKRUN# to PCH_GPIO32 For HW Review demand

24) 08/18 20 Change R324 From 1K to 2.2K For Intel check list demand

25) 08/18 21 Remove PCH PECI signal By HW Review demand

26) 08/18 25 Remove C363, C364, C365, C366 By HW Review demand

27) 08/18 30 Change UT4 to SA00004600 For CIC demand

28) 08/18 30 Change USB30@ to always mount Due to no BTO USB20/30.

29) 08/18 27 Remove all new card function

30) 08/20 9 Add PJ32 For Cost down +1.5V to +1.5V_CPU

31) 08/20 13 Swap USB20_P11 and USB20_N11 For layout request

32) 08/20 25 Swap USB20_P0, USB20_N0, USB20_P1, USB20_N1 For layout request

33) 08/23 Update Power schematic

34) 08/23 20 Swap PCI_PIRQC#, PCH_GPIO4, PCH_GPIO2, PCI_PIRQA# For layout request

C C

35) 08/23 20 Swap SLP_CHG_M3, SLP_CHG_M4, USB_OC#0 For layout request

36) 08/30 18 Reserve R259 For cost down plan

37) 08/30 Change USB3.0 Connector For ME demand

38) 08/30 21 Add USB Sleep & Charge MAXIC_Select pin in GPIO71(Remove T73) For MAX14550E/14566B co-lay

39) 08/30 25 Change C426 to Aluminum Solid Cap 220u For cost down

40) 08/30 27 Add USB Sleep & Charge IC: MAX14550E

41) 08/30 28 Add 16pin X’form for cost down, and P/N is SP050006E00 For cost down

42) 08/30 28 Change PWRME_CTRL# from PCH_GPIO33 to HDA_SDO By Intel spec

43) 08/30 16 Change U53 PIN 9 from KSI4 to KSI3

44) 08/30 16 Change R442, R443 from 10k to 100k

45) 08/30 16 Change U56 Pin3 from KSO6 to +5VALW

46) 08/30 16 Add R227 100k ohm

47) 08/30 28 Reserve D85 and D86 For ESD request

48) 08/30 30 Swap U3RXDN1_R, U3RXDN1_R_L, U3RXDP1_R, U3RXDP1_R_L For layout request

49) 08/30 16 Change U13 from SA000021A00 to SA00003IN00 Due to EOL of SA000021A00

50) 08/30 27 Reserve R1443 for WLAN Mini PCIE Card Pin5

51) 08/30 33 Change U22 From SA00003GK00 to SA00003GM10 Due to EOL of SA00003GK00

52) 08/30 34 Change SW1, SW4 to SN100002Y00

53) 09/01 28 Add LL5 for ISN test For EMI demand

54) 09/01 31 Change RA12 from 10k to 4.7kohm and CA18 from 0.1uF to 100pF For Beep by A51 demand.

55) 09/01 32 Add CPSETIN to power For 65W/75W select

56) 09/01 18,20,21 Reserve C894, C895, C896, C897 For ESD request

57) 09/02 08 Remove, add C126, C131 and add C898 3Pin Bulk Cap By Power Demand

58) 09/02 27 Add 14566@ & 14550@

59) 09/02 27 Change U5 Pin8 control pin from SLP_CHG# to SLP_CHG_M4

60) 09/02 33 Change EC ROM size from 256KB(SA00003GM10) to 128KB(SA00003FL10)

61) 09/02 11 Change C165,C166,C168,C171,C174,C176,C178 from SE093106M80 to SE000005T80 For sourcer demand

62) 09/02 12 Change C191,C192,C194,C197,C200,C202,C204 from SE093106M80 to SE000005T80 For sourcer demand

63) 09/02 Change CT25 from SE093106K80 (10uF_0805) to SE000005T80 (10uF_0603) For sourcer demand

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROP RIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROP RIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

200910/9 2010/01/23

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sh eet of

2

Date: Sh eet of

HW-PIR

NHQAA LA-6831P M/B

57 57Monday, September 06, 2010

1

0.1

Compal LA-6832P PHQAA Marseille 10R, Satellite P750, Satellite P775, LA-6832P PHQAA Marseille 10RG Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual