Compal LA-6801P PALB0 Specter (Huron River), Alienware M14x Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-6801P ( DAB00000400 )

46198531L01
46198531L02

PALB0

Dell/Compal Confidential

Schematic Document

2 2

Specter (Huron River)

Sandy Bridge(PGA) + Cougar Point(standard)

DISCRETE VGA N12E-GE-B (optimus)

3 3

4 4

A

B

2010-12-06

Rev: 0.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-6801P

E

1 60Monday, December 06, 2010

0.3

A

B

C

D

E

Compal Confidential

Project Code : PALB0

FFS

e Name : LA-6801P

Fil

1 1

HDMI
Conn.

DP Conn.

P.39

P.38

DP MUX

P.37

LVDS

2 2

Conn.

P.21

CRT Conn.

P.21

HDMI

DisplayPort

DisplayPort

DP (DIS)

DP

GPU
N12E-GE

P.40~45

PEG x16 (DIS)

LVDS

CRT

(UMA)

100MHz

2.7GT/s

DisplayPort

PCI-E x1

Port 3 Port 2 Port 1 Port 4

Mini Card-2

WLAN (Half)

USB[x]

3 3

port4

WWAN (Full)

USB[x]
port5

LAN(GbE)

AR8151-BL1A

RJ45

Card ReaderMini Card-1

RTS5209

P.22 P.23

9 in 1
Socket

DMC/Daughter Board

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

P.32

P.13

P.29

P.33

P.49~59

USB 3.0/2.0

USB 3.0/2.0
Com

P.23P.22

SPI ROM

Port 6

Host Ctrl.

P.27

bo Conns x2

P.27

ENE 3810

P.13 P.31

Intel

Sandy Bridge

Processor

4C 45W SV

rPGA 989 Socket

P.5~10

DMI x4FDI x8

100MHz
5GB/s

Intel

Cougar Point

PCH

BGA 989 Balls

P13~20

P

I

S

P.31

Touch Pad Int.KBD

LPC Bus

ENE KB930

P.35

P.

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MHz

SATA2.0

Port 0

Port 2

Port 4

USB2.0

Port 5

Port 6

HD Audio

Port 8

BIOS ROM

29 P.31

Port 0

Port 2

Fan Control

P.28

204pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

SATA HDD Conn.

SATA ODD Conn.

USB 2.0

( USB Charger )

Digital Camera

Mini Card-1 (WLAN)

( Half )

Mini Card-2 (WWAN)

( Full )

AlienFX/ELC

BT 2.1 /BT 3.0

Audio Codec
ALC665-GR

TI TPA6017A2

Int. Speaker

P.30

CPU XDP
Conn.

P.11,12

P.28

P.28

P.26

P.21

P.32

P.32

P.34~36

P.32

P.24

P.25

P.25

P.6

DMC/Daughter Board

SIM Card

P.32

TPA6211A

sub-woofer conn.

Audio Jack x3

( HeadPhone x2, MIC)

Digital MIC

P.25

P.25

P.25

P.24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-6801P

E

2 60Monday, December 06, 2010

0.3

A

Compal Confidential

Project Code : PALB0

ile Name : LA-6801P

F

B

C

D

E

1 1

LA-6801P M/B

Camera

40 pin

Wire

LCD Panel

Blue Tooth

LS-6801P

LS-6803P

INDICATOR/B

2 2

Led-Wireless

Led-CapsLock

Wire

6 pin

BTB conn.

WLAN WWAN/DMC

80 pin

DMC/B

14 pin

Wire

12 pin

Wire

20 pin

HDD

ODD

LF-6801P

FPC

FFC

20 pin

Wire

6 pin

FFC

12 pin

LS-6802P

TP LED/B

Touch Pad

3 3

FFC

4 pin

Led x 6

Lid

LS-6809P

LOGO LIGHT GUIDE/B

Led x 6

LS-6806P

POWER BUTTON/B

on/off SW

Led x 3

4 pin4 pin

WireWire

LS-6807P

LS-6808P

FRONT LIGHT L/B

Led x 2 Led x 2

4 4

A

FRONT LIGHT R/B

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

D

Date: Sheet of

Title

Size Document Number Rev

Compal Electronics, Inc.

Block Diagram

E

3 60Monday, December 06, 2010

0.3

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SOURCE

KB930

KB930

PCH

PCH

AD_BID

0.168 V

0.375 V 0.503 V
0

0.958 V

1.372 V

1.851 V

2.433 V

MINI2

MINI1 BATT SODIMM

V V

.634 V

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

Thermal
Sensor 1

V V

V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal
Sensor 2

max

FFS VGA

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal
Sensor

V

V V

A

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

DMCVXDP

Charger

V

V

PCB Revision

0.1

0.2

0.3

0.4

0.5

Link

PCH

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

DESTINATION

None

JUSB1 (2.0 Ext Left Side)

Bluetooth

CAMERA

J

MINI1 (WLAN)

JMINI2 (WWAN/DMC)

ELC 8051

None

None

None

None

None

12

CLKOUT

1 1

PCI0

PCI1

PCI2

PCI3

PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

None

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7 None

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN

MINI CARD-2 WWAN

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

None

ODD

None

None

None

Symbol Note :

: means Digital Ground

: means Analog Ground

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

13

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

None

None

DESTINATION

10/100/1G LAN

MINI CARD-2 WWAN/DMC

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-6801P

4 60Monday, December 06, 2010

0.3

5

D D

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>

C C

B B

FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

+VCCP

1 2

RC36 24.9_0402_1%

R1942 10K_0402_5%~D

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

12

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

CONN@

DMI

Intel(R) FDI

eDP

4

+VCCP

12

RC2

24.9_0402_1%

PEG_COMP

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

CC200 220nF_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CC199 220nF_0402_16V7K
CC198 220nF_0402_16V7K
CC197 220nF_0402_16V7K
CC196 220nF_0402_16V7K
CC195 220nF_0402_16V7K
CC194 220nF_0402_16V7K
CC193 220nF_0402_16V7K
CC192 220nF_0402_16V7K
CC191 220nF_0402_16V7K
CC190 220nF_0402_16V7K
CC189 220nF_0402_16V7K
CC188 220nF_0402_16V7K
CC187 220nF_0402_16V7K
CC186 220nF_0402_16V7K
CC185 220nF_0402_16V7K

CC216 220nF_0402_16V7K
CC215 220nF_0402_16V7K
CC214 220nF_0402_16V7K
CC213 220nF_0402_16V7K
CC212 220nF_0402_16V7K
CC211 220nF_0402_16V7K
CC210 220nF_0402_16V7K
CC209 220nF_0402_16V7K
CC208 220nF_0402_16V7K
CC207 220nF_0402_16V7K
CC206 220nF_0402_16V7K
CC205 220nF_0402_16V7K
CC204 220nF_0402_16V7K
CC203 220nF_0402_16V7K
CC202 220nF_0402_16V7K
CC201 220nF_0402_16V7K

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

3

PEG_ICOMPI and R COMPO signals s hould be shorted and routed
with - max lengt h = 500 mils - typical impedanc e = 43 mohms
PEG_ICOMPO signa ls should be ro uted with - max length = 500 mil s

- typical impeda nce = 14.5 mohm s

PEG_GTX_C_HRX_N15 <40>
PEG_GTX_C_HRX_N14 <40>
PEG_GTX_C_HRX_N13 <40>
PEG_GTX_C_HRX_N12 <40>
PEG_GTX_C_HRX_N11 <40>
PEG_GTX_C_HRX_N10 <40>
PEG_GTX_C_HRX_N9 <40>
PEG_GTX_C_HRX_N8 <40>
PEG_GTX_C_HRX_N7 <40>
PEG_GTX_C_HRX_N6 <40>
PEG_GTX_C_HRX_N5 <40>
PEG_GTX_C_HRX_N4 <40>
PEG_GTX_C_HRX_N3 <40>
PEG_GTX_C_HRX_N2 <40>
PEG_GTX_C_HRX_N1 <40>
PEG_GTX_C_HRX_N0 <40>

PEG_GTX_C_HRX_P15 <40>
PEG_GTX_C_HRX_P14 <40>
PEG_GTX_C_HRX_P13 <40>
PEG_GTX_C_HRX_P12 <40>
PEG_GTX_C_HRX_P11 <40>
PEG_GTX_C_HRX_P10 <40>
PEG_GTX_C_HRX_P9 <40>
PEG_GTX_C_HRX_P8 <40>
PEG_GTX_C_HRX_P7 <40>
PEG_GTX_C_HRX_P6 <40>
PEG_GTX_C_HRX_P5 <40>
PEG_GTX_C_HRX_P4 <40>
PEG_GTX_C_HRX_P3 <40>
PEG_GTX_C_HRX_P2 <40>
PEG_GTX_C_HRX_P1 <40>
PEG_GTX_C_HRX_P0 <40>

PEG_HTX_C_GRX_N15 <40>
PEG_HTX_C_GRX_N14 <40>
PEG_HTX_C_GRX_N13 <40>
PEG_HTX_C_GRX_N12 <40>
PEG_HTX_C_GRX_N11 <40>
PEG_HTX_C_GRX_N10 <40>
PEG_HTX_C_GRX_N9 <40>
PEG_HTX_C_GRX_N8 <40>
PEG_HTX_C_GRX_N7 <40>
PEG_HTX_C_GRX_N6 <40>
PEG_HTX_C_GRX_N5 <40>
PEG_HTX_C_GRX_N4 <40>
PEG_HTX_C_GRX_N3 <40>
PEG_HTX_C_GRX_N2 <40>
PEG_HTX_C_GRX_N1 <40>
PEG_HTX_C_GRX_N0 <40>

PEG_HTX_C_GRX_P15 <40>
PEG_HTX_C_GRX_P14 <40>
PEG_HTX_C_GRX_P13 <40>
PEG_HTX_C_GRX_P12 <40>
PEG_HTX_C_GRX_P11 <40>
PEG_HTX_C_GRX_P10 <40>
PEG_HTX_C_GRX_P9 <40>
PEG_HTX_C_GRX_P8 <40>
PEG_HTX_C_GRX_P7 <40>
PEG_HTX_C_GRX_P6 <40>
PEG_HTX_C_GRX_P5 <40>
PEG_HTX_C_GRX_P4 <40>
PEG_HTX_C_GRX_P3 <40>
PEG_HTX_C_GRX_P2 <40>
PEG_HTX_C_GRX_P1 <40>
PEG_HTX_C_GRX_P0 <40>

2

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

Sandy Bridge_rPGA_Rev1p0

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-6801P

1

of

5 60Monday, December 06, 2010

0.3

5

XDP_PREQ#_R
XDP_PRDY#_R

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

CFG10_R

RC130_0402_5%~D @

1 2
1 2

1 2
1 2

1 2

12

RC150_0402_5%~D @

12

RC221K_0402_5%~D
RC230_0402_5%~D

RC241K_0402_5%~D
RC260_0402_5%~D

RC30

CFG11_R

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_XD P
CFD_PWRBTN#_X DP

XDP_HOOK2
SYS_PWROK_XDP

XDP_TCK1
XDP_TCK_R

D D

C C

CFG10<8>
CFG11<8>

H_CPUPWRGD

CFG0<8>

VGATE<15,31,57>

PCH_JTAG_TCK<13>

The resistor
for HOOK2 should be
placed such that the
stub is very sma ll
on CFG0 net

PCH_SMBDATA<11,12,14,28,32>
PCH_SMBCLK<11,12,14,28,32>

0_0402_5%~D @

+VCCP +VCCP

+3VALW

12

@

RC27
1K_0402_5%~D

SYS_PWROK_XDP

4

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

JCPU1B

3

PM_DRAM_PWR GD<15>

PCH_PWROK<15,31>

SYS_PWROK<15>

+3V_PCH

1 2

2

CFG16_R

RC3 0_0402_5%~D@

4

CFG17_R

6
8

CFG0_R

10

CFG1_R

12
14

CFG2_R

16

CFG3_R

18
20

CFG8_R

22

CFG9_R

24
26

CFG4_R

28

CFG5_R

30
32

CFG6_R

34

CFG7_R

36
38

CLK_CPU_ITP

40

CLK_CPU_ITP#

42
44

XDP_RST#_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#_R

54

XDP_TDI

56

XDP_TMS_R

58
60

1 2

RC5 0_0402_5%~D@

1 2

RC7 0_0402_5%~D@

1 2

RC9 0_0402_5%~D@

1 2

RC10 0_0402_5%~D@

1 2

RC12 0_0402_5%~D@

1 2

RC14 0_0402_5%~D@

1 2

RC16 0_0402_5%~D@

1 2

RC17 0_0402_5%~D@

1 2

RC18 0_0402_5%~D@

1 2

RC20 0_0402_5%~D@

1 2

RC21 0_0402_5%~D@

1 2

1 2

RC25 1K_0402_5%~D

RC28 0_0402_5%~D@

1 2

RC31 0_0402_5%~D@

1 2

RC29 0_0402_5%~D@

1 2

+VCCP

0.1U_0402_16V7K~D

1

CC67

2

CFG16 < 8>
CFG17 < 8>

CFG0 <8>
CFG1 <8>

CFG2 <8>
CFG3 <8>

CFG8 <8>
CFG9 <8>

CFG4 <8>
CFG5 <8>

CFG6 <8>
CFG7 <8>

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,31>

PLT_RST#

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

0.1U_0402_16V7K~D

1

CC66

2

Place near JXDP1

0_0402_5%~D

RC4

200_0402_1%

2

RC128

@

RC127

1 2

1 2

0_0402_5%~D

1 2

RC11 0_0402_5%~D

RUN_ON_CPU1.5VS3#<10,33>

PLT_RST#<16,22,23,27,31,32>

+3VS

12

@

RC6

10K_0402_5%~D

D_PWG

1
2

+3VALW

UC1

5

B

VCC

A

4

GND3Y

74AHC1G09GW TSSOP 5P

RUN_ON_CPU1.5VS3#

UC2

1

NC

VCC

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

5

4

1

2

2

G

+3VALW

0.1U_0402_16V7K~D

+1.5V_CPU_VDDQ

CC65

12

RC19
39_0402_1%

1 2

13

D

QC1
SSM3K7002F_SC59-3

S

0.1U_0402_16V7K~D

1

CC68

2

BUFO_CPU_RST#

1

RC8
200_0402_1%

VDDPWRGOOD

RC8
CRB 1.1K
CHECK LIST 0.7 - -> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev --> 200

+VCCP

12

RC32
75_0402_5%

RC33

1 2

43_0402_1%

BUF_CPU_RST#

12

@

RC34
0_0402_5%~D

CLK_CPU_DMI_R

A28

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

BCLK

BCLK#

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H_SNB_IVB#<17>

+VCCP

RC41

RC49

RC53

RC57

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

T1PAD~D @

RC43

62_0402_5%

B B

A A

H_PROCHOT#<31>

1 2

H_THERMTRIP#<17>

H_PM_SYNC< 15>

H_CPUPWRGD<17>

H_PECI<17,31>

VDDPWRGOOD

1 2

56_0402_5%

1 2

0_0402_5%~D

1 2

0_0402_5%~D

1 2

130_0402_1%~D

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

CONN@

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

CLK_CPU_DMI#_R

A27

CLK_CPU_DPLL_R

A16

CLK_CPU_DPLL#_R

A15

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

DDR3 Compensation Signals

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

TCK

XDP_TMS

AR27

TMS

XDP_TRST#

AP30

XDP_TDI_R

AR28

TDI

XDP_TDO_R

AP26

TDO

XDP_DBRESET#_R

AL35

XDP_BPM#0_R

AT28

XDP_BPM#1_R

AR29

XDP_BPM#2_R

AR30

XDP_BPM#3_R

AT30

XDP_BPM#4_R

AP32

XDP_BPM#5_R

AR31

XDP_BPM#6_R

AT31

XDP_BPM#7_R

AR32

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

2010/12/01 2011/12/01

RC37 0_0402_5%~D

1 2

RC38 0_0402_5%~D

1 2

RC39 0_0402_5%~D

1 2

RC40 0_0402_5%~D

1 2

H_DRAMRST# <7>

RC55140_0402_1%

1 2

RC5825.5_0402_1%

1 2

RC60200_0402_1%

1 2

for EMC request, close to CPU 7/26

RC121 0_0402_5%~D

1 2

RC122 0_0402_5%~D

1 2

RC123 0_0402_5%~D

1 2

RC124 0_0402_5%~D

1 2

RC125 0_0402_5%~D

1 2

RC50 0_0402_5%~D

1 2

RC51 0_0402_5%~D

1 2

RC56

1 2

RC59 0_0402_5%~D

1 2

RC61 0_0402_5%~D

1 2

RC62 0_0402_5%~D

1 2

RC63 0_0402_5%~D

1 2

RC64 0_0402_5%~D

1 2

RC65 0_0402_5%~D

1 2

RC66 0_0402_5%~D

1 2

RC67 0_0402_5%~D

1 2

RC68 0_0402_5%~D

1 2

RC69 0_0402_5%~D

1 2

RC70 0_0402_5%~D

1 2

RC71 0_0402_5%~D

1 2

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI
XDP_TDO

close to CPU 7/26

XDP_DBRESET#

0_0402_5%~D

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

CFG12 < 8>
CFG13 < 8>
CFG14 < 8>
CFG15 < 8>

Compal Secret Data

Deciphered Date

2

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>

XDP_DBRESET# <15>

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_DBRESET#

H_CPUPWRGD_R

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-6801P

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

+VCCP

RC4551_0402_5%

RC4651_0402_5%

RC4751_0402_5% @

RC4851_0402_5%

RC5251_0402_5%

RC5451_0402_5%

+3VS

RC421K_0402_5%~D

RC4410K_0402_5%~D

6 60Monday, December 06, 2010

0.3

5

4

3

2

1

JCPU1C

M_CLK_DDR0

DDR_A_D[0..63]<11>

D D

C C

B B

A A

DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>

H_DRAMRST#<6>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_DRAMRST#

4.99K_0402_1%~D

5

RC77

AP11
AN11

AL12
AM12
AM11

AL11

AP12

AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

C5
D5
D3
D2
D6
C6
C2
C3

F10

F8

G10

G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2

M8

N10

N8
N7

M10

M9
N9

M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

V6

AE8
AD9
AF9

12

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

@

1 2

RC74 0_0402_5%~D

QC2

BSS138_SOT23

S

G

2

1

2

DDR SYSTEM MEMORY A

D

DDR3_DRAMRST#_R

13

DRAMRST_CNTRL

CC69
.047U_0402_16V7K~D

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

AH2

RSVD_TP[10]

C4

SA_DQS#[0]

G6

SA_DQS#[1]

J3

SA_DQS#[2]

M6

SA_DQS#[3]

AL6

SA_DQS#[4]

AM8

SA_DQS#[5]

AR12

SA_DQS#[6]

AM15

SA_DQS#[7]

D4

SA_DQS[0]

F6

SA_DQS[1]

K3

SA_DQS[2]

N6

SA_DQS[3]

AL5

SA_DQS[4]

AM9

SA_DQS[5]

AR11

SA_DQS[6]

AM14

SA_DQS[7]

AD10

SA_MA[0]

W1

SA_MA[1]

W2

SA_MA[2]

W7

SA_MA[3]

V3

SA_MA[4]

V2

SA_MA[5]

W3

SA_MA[6]

W6

SA_MA[7]

V1

SA_MA[8]

W5

SA_MA[9]

AD8

SA_MA[10]

V4

SA_MA[11]

W4

SA_MA[12]

AF8

SA_MA[13]

V5

SA_MA[14]

V7

SA_MA[15]

+1.5V

12

RC75
1K_0402_5%~D

1 2

RC76 1K_0402_5%~D

DG 1.0 Figure 61 RC76=1K

4

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

1 2

RC72 0_0402_5%~D

@

1 2

RC73 0_0402_5%~D

M_CLK_DDR0 <11>
M_CLK_DDR#0 <11>
DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL_EC <31>

DDR_B_D[0..63]<12>

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

Compal Secret Data

Deciphered Date

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

Title

Size Document Number Rev

Date: Sheet of

M_CLK_DDR#2

AD2

DDR_CKE2_DIMMB

R9

M_CLK_DDR3

AE1

M_CLK_DDR#3

AD1

DDR_CKE3_DIMMB

R10

AB2
AA2
T9

AA1
AB1
T10

DDR_CS2_DIMMB#

AD3

DDR_CS3_DIMMB#

AE3
AD6
AE6

M_ODT2

AE4

M_ODT3

AD4
AD5
AE5

DDR_B_DQS#0

D7

DDR_B_DQS#1

F3

DDR_B_DQS#2

K6

DDR_B_DQS#3

N3

DDR_B_DQS#4

AN5

DDR_B_DQS#5

AP9

DDR_B_DQS#6

AK12

DDR_B_DQS#7

AP15

DDR_B_DQS0

C7

DDR_B_DQS1

G3

DDR_B_DQS2

J6

DDR_B_DQS3

M3

DDR_B_DQS4

AN6

DDR_B_DQS5

AP8

DDR_B_DQS6

AK11

DDR_B_DQS7

AP14

DDR_B_MA0

AA8

DDR_B_MA1

T7

DDR_B_MA2

R7

DDR_B_MA3

T6

DDR_B_MA4

T2

DDR_B_MA5

T4

DDR_B_MA6

T3

DDR_B_MA7

R2

DDR_B_MA8

T5

DDR_B_MA9

R3

DDR_B_MA10

AB7

DDR_B_MA11

R1

DDR_B_MA12

T1

DDR_B_MA13

AB10

DDR_B_MA14

R5

DDR_B_MA15

R4

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-6801P

1

M_CLK_DDR2

AE2

M_CLK_DDR2 <12>
M_CLK_DDR#2 <12>
DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12>
DDR_CS3_DIMMB# <12>

M_ODT2 <12>
M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

7 60Monday, December 06, 2010

0.3

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

L7

RSVD28

AG7

CFG0<6>
CFG1<6>
CFG2<6>
CFG3<6>
CFG4<6>
CFG5<6>
CFG6<6>
CFG7<6>
CFG8<6>
CFG9<6>

+VCC_CORE

@

RC80
50_0402_1%

C C

+V_DDR_REFA

+V_DDR_REFB

B B

RC82 0_0402_5%~D@

RC83 0_0402_5%~D@

+VCC_GFXCORE_AXG

1 2

1 2
1 2

RC84

1K_0402_1%~D

INTEL 12/28 reco mmand
to add 1k pull d own

VCCP_PWRCTRL<54>

1 2

@

RC79
50_0402_1%

12

VCC_AXG_VAL_SENSE

VCC_VAL_SENSE

12

RC85
1K_0402_1%~D

CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>
CFG16<6>
CFG17<6>

+V_DDR_REFA_R
+V_DDR_REFB_R

1 2

RC88 0_0402_5%~D

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

T19PAD~D @

T25PAD~D @
T26PAD~D @
T27PAD~D @

T30PAD~D @
T32PAD~D @
T33PAD~D @
T34PAD~D @
T35PAD~D @
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T42PAD~D @
T43PAD~D @

T44PAD~D @

H_VCCP_SEL

T49PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

RESERVED

Need PWR add new circuit on 1. 05V(refer CRB)

Sandy Bridge_rPGA_Rev1p0

CONN@

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

KEY

T2 PAD~D@
T3 PAD~D@
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@

T7 PAD~D@
T8 PAD~D@
T9 PAD~D@

T10 PAD~D@
T11 PAD~D@
T12 PAD~D@
T13 PAD~D@

T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T18 PAD~D@

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T24 PAD~D@

T29 PAD~D@T28PAD~D @
T31 PAD~D@

T36 PAD~D@

CLK_RES_ITP <14>
CLK_RES_ITP# <14>

T46 PAD~D@T45PAD~D @
T47 PAD~D@
T48 PAD~D@

T50 PAD~D@

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

12

RC78
1K_0402_1%~D

1:(Default) Norm al Operation; L ane #

CFG2

definition match es socket pin m ap definition

0:Lane Reversed

*

CFG4

12

RC81

@

1K_0402_1%~D

1 : Disabled; No Physical Displ ay Port

*

CFG4

attached to Embe dded Display Po rt

0 : Enabled; An external Displa y Port device is
connected to the Embedded Displ ay Port

CFG6

CFG5

12

12

RC87

@

1K_0402_1%~D

11: (Default) x1 6 - Device 1 fu nctions 1 and 2 disabled

*

10: x8, x8 - Dev ice 1 function 1 enabled ; func tion 2
disabled
01: Reserved - ( Device 1 functi on 1 disabled ; function

2 enabled)

00: x8,x4,x4 - D evice 1 functio ns 1 and 2 enabl ed

CFG7

@

12

RC89

@

1K_0402_1%~D

RC86
1K_0402_1%~D

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

@

RC90

50_0402_1%

A A

INTEL 12/28 reco mmand
to add RC120, RC 121, RC122, RC1 23
Please place as close as JCPU1

5

@

RC91
50_0402_1%

1 2

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

PEG DEFER TRAINING

1: (Default) PEG Train immediat ely

*

CFG7

following xxRESE TB de assertion

0: PEG Wait for BIOS for traini ng

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-6801P

8 60Monday, December 06, 2010

1

of

0.3

5

4

3

2

1

QC=94A
DC=53A

POWER

PEG AND DDR

CORE SUPPLY

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

8.5A

VCCSENSE_R
VSSSENSE_R

PDDG 0.7@P12

1

2

1

2

1

2

130_0402_1%~D

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

22U_0805_6.3VAM~D

CC72

22U_0805_6.3VAM~D

CC92

22U_0805_6.3VAM~D

CC103

12

RC95

RC98 0_0402_5%~D

1 2

RC99 0_0402_5%~D

1 2

VCCIO_SENSE <54>
VSSIO_SENSE <54>

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

2

1

2

1

2

CC74

CC73

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC93

CC94

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC104

CC105

2

RC95 close to CPU

RC94 43_0402_1%

1 2

RC92 0_0402_5%~D

1 2

RC96 0_0402_5%~D

1 2

+VCCP

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC75

2

22U_0805_6.3VAM~D

1

CC95

2

22U_0805_6.3VAM~D

1

CC106

2

22U_0805_6.3VAM~D

1

1

CC76

CC77

2

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

2

1

2

CC97

CC96

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC108

CC107

2

+VCCP

12

+VCC_CORE

12

12

22U_0805_6.3VAM~D

1

CC88

2

22U_0805_6.3VAM~D

1

CC98

2

22U_0805_6.3VAM~D

1

@

CC109

2

RC93
75_0402_5%

RC97
100_0402_1%~D

RC100
100_0402_1%~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC78

2

22U_0805_6.3VAM~D

1

CC99

2

330U_D2_2VM_R6M~D

1

CC110

+

2

Place the PU
resistors close to CPU

VR_SVID_ALRT# <57>
VR_SVID_CLK <57>
VR_SVID_DAT <57>

VCCSENSE <57>
VSSSENSE <57>

22U_0805_6.3VAM~D

1

1

CC79

2

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

CC100

2

2

330U_D2_2VM_R6M~D

1

CC111

+

2

22U_0805_6.3VAM~D

1

CC80

CC81

2

22U_0805_6.3VAM~D

1

CC101

CC102

2

JCPU1F

+VCC_CORE

1

CC70
10U_0805_4VAM~D

2

1

CC89
10U_0805_4VAM~D

2

1

CC114
22U_0805_6.3VAM~D

2

1

CC119
22U_0805_6.3VAM~D

2

1

CC124
22U_0805_6.3VAM~D

2

1

CC129
22U_0805_6.3VAM~D

2

1

+

CC133

2

470U_D2_2VM_R4.5M~D

+VCC_CORE

+VCC_CORE

1

CC85
10U_0805_4VAM~D

2

1

CC82
10U_0805_4VAM~D

2

1

CC113
22U_0805_6.3VAM~D

2

1

CC118
22U_0805_6.3VAM~D

2

1

CC123
22U_0805_6.3VAM~D

2

1

CC128
22U_0805_6.3VAM~D

2

1

+

2

470U_D2_2VM_R4.5M~D

1

+

CC136

2

470U_D2_2VM_R4.5M~D

CC132

D D

C C

B B

A A

1

CC86
10U_0805_4VAM~D

2

1

CC90
10U_0805_4VAM~D

2

1

CC115
22U_0805_6.3VAM~D

2

1

CC120
22U_0805_6.3VAM~D

2

1

CC125
22U_0805_6.3VAM~D

2

1

CC130
22U_0805_6.3VAM~D

2

1

+

CC134

2

470U_D2_2VM_R4.5M~D

1

CC87
10U_0805_4VAM~D

2

1

CC91
10U_0805_4VAM~D

2

1

CC116
22U_0805_6.3VAM~D

2

1

CC121
22U_0805_6.3VAM~D

2

1

CC126
22U_0805_6.3VAM~D

2

1

CC131
22U_0805_6.3VAM~D

2

470U_D2_2VM_R4.5M~D

1

CC71
10U_0805_4VAM~D

2

1

CC83
10U_0805_4VAM~D

2

1

CC117
22U_0805_6.3VAM~D

2

1

CC122
22U_0805_6.3VAM~D

2

1

CC127
22U_0805_6.3VAM~D

2

1

+

CC135

2

1

CC84
10U_0805_4VAM~D

2

+VCC_CORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev1p0

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

LA-6801P

9 60Monday, December 06, 2010

1

0.3

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

B+_BIAS+3VALW

12

RC102
100K_0402_5%~D

1

2

22U_0805_6.3V6M~D

1

2

22U_0805_6.3V6M~D

1

2

1U_0402_6.3V6K~D

CC175

RUN_ON_CPU1.5VS3#

61

QC5A
2N7002DW-7-F_SOT363-6~D

2

22U_0805_6.3V6M~D

CC147

CC146

1

2

22U_0805_6.3V6M~D

CC154

CC155

1

2

@

330U_D2_2.5VM_R6M~D

1

CC176

+

2

33A

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

TBD

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev1p0

CONN@

D D

RC104

@

1

2

1

2

CC157

22U_0805_6.3V6M~D

CC142

22U_0805_6.3V6M~D

CC150

1 2

0_0402_5%~D

1 2

0_0402_5%~D

CC217

0.1U_0402_10V7K~D

22U_0805_6.3V6M~D

CC143

1

1

2

2

22U_0805_6.3V6M~D

CC151

1

1

2

2

10U_0805_4VAM~D

1

CC172

2

RC107

@

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

22U_0805_6.3V6M~D

CC144

1

2

22U_0805_6.3V6M~D

CC152

1

2

+1.8VS_VCCPLL

1U_0402_6.3V6K~D

CC174

CC145

CC153

@

1

2

SUSP#<18,31,33,53,54>

CPU1.5V_S3_GATE<31>

+VCC_GFXCORE_AXG

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC140

CC141

1

1

2

2

22U_0805_6.3V6M~D

C C

B B

22U_0805_6.3V6M~D

CC148

1

2

1

+

CC156

2

470U_D2_2VM_R4.5M~D

+1.8VS

RC109 0_0805_5%~D

CC149

1

2

1

+

2

470U_D2_2VM_R4.5M~D

1 2

12

RC101
100K_0402_5%~D

RUN_ON_CPU1.5VS3

3

QC5B

5

2N7002DW-7-F_SOT363-6~D

4

RUN_ON_CPU1.5VS3# <6,33>

POWER

VSSAXG_SENSE

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

QC3

AO4728L_SO8~D

8
7
6
5

4

0.1U_0603_50V_X7R

12

1

CC139

2

RC105

330K_0402_1%

VCC_AXG_SENSE

AK35

VSS_AXG_SENSE

AK34

+V_SM_VREF should
have 10 mil trace width

+V_SM_VREF_CNT

AL1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

H_FC_C22

C22
C24

1
2
3

1

2

CC138

10U_0805_10V4Z~D

1

2

VCCSA_SEL <55>

12

RC103

RC126

100K_0402_5%~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CC160

2

10U_0805_4VAM~D

1

1

CC167

2

2

RC111

10K_0402_5%~D

20K_0402_5%~D

VCC_AXG_SENSE <57>
VSS_AXG_SENSE <57>

1 2

RC106 0_0402_5%~D@

3

12

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC161

CC163

CC162

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D

1

1

CC169

CC168

2

2

RC120 0_0402_5%~D

12

1

QC4

2

NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC164

CC165

2

2

1

@

+

CC171

CC170

330U_D2_2VM_R6M~D

2

1 2

12

RC110

@

0_0402_5%~D

+V_SM_VREF

1

+

CC166
330U_D2_2VM_R6M~D

2

+VCCSA

VCCSA_SENSE <55>

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

+1.5V_CPU_VDDQ

12

1K_0402_5%~D
RC112

12

1K_0402_5%~D
RC116

@

J8

1 2

PAD-OPEN 4x4m

J8 OPEN

VSSSA_SENSE <55>

+1.5V_CPU_VDDQ +1.5V

add CC181 , CC182, 4 caps ar e all pop.

ollow checklist 1.0 5/24

f

+1.5V

CC182 0.1U_0402_10V7K~D

12

CC184 0.1U_0402_10V7K~D

12

CC181 0.1U_0402_10V7K~D

12

CC183 0.1U_0402_10V7K~D

12

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

LA-6801P

1

10 60Monday, December 06, 2010

0.3

5

+1.5V

CD6

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD11

1

2

1U_0402_6.3V6K~D

1

CD20

2

<BOM Structure>

12

RD1
1K_0402_1%~D

+V_DDR_REFA

12

RD3
1K_0402_1%~D

All VREF traces should
have 10 mil trace width

10U_0603_6.3V6M~D

330U_SX_2VY~D

@

1

CD12

1

2

CD14

CD13

1

+

2

2

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_MA[0..15]<7>

D D

Layout Note:
Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD3

1

1

2

2

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C C

B B

CD7

CD8

1

1

2

2

Layout Note:
Place near JDIMM1.203,204

+0.75VS

1U_0402_6.3V6K~D

1

1

CD17

2

2

1U_0402_6.3V6K~D

CD4

CD5

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD9

CD10

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD19

CD18

2

+V_DDR_REFA

4

RD2 0_0402_5%~D

1 2

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

1

1

CD1

2

2

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

+3VS

CD21

1

1

2

2

+DIMM0_VREF

DDR_A_D0
DDR_A_D1

CD2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

RD6 10K_0402_5%~D

1 2

RD7 10K_0402_5%~D

CD22

+0.75VS

+1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A626-U2SN-7F

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

3

+1.5V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2
A0

VDD

CK1

VDD

BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

+VREF_CA

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

1

CD15

2

PCH_SMBDATA <6, 12,14,28,32>
PCH_SMBCLK <6,12,14,28,32>

DDR3_DRAMRST# <7,12>

+1.5V

1

CD16

2

2

12

RD4
1K_0402_1%~D

12

RD5
1K_0402_1%~D

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-6801P

1

11 60Monday, December 06, 2010

0.3

5

+1.5V

12

RD15
1K_0402_1%~D

+V_DDR_REFB

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

D D

C C

B B

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.5V

10U_0603_6.3V6M~D

CD32

1

2

Layout Note:
Place near JDIMMB.203,204

+0.75VS

CD29

CD28

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD34

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD42

CD43

2

2

Layout Note:
Place near JDIMMB

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD31

CD30

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD36

CD35

1

1

2

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD45

CD44

2

2

10U_0603_6.3V6M~D

@

1

CD38

CD37

1

2

2

12

RD16
1K_0402_1%~D

330U_SX_2VY~D

CD39

+

4

+V_DDR_REFB

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

RD14 0_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

1

CD27

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

12

RD19

10K_0402_5%~D

3

+1.5V

0.1U_0402_16V7K~D

10K_0402_5%~D

+DIMM1_VREF

DDR_B_D0
DDR_B_D1

1

CD26

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

12

RD20

+0.75VS

CD47

CD46

1

1

2

2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4926-0100

O

NN@

C

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+1.5V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

2

DDR3_DRAMRST# <7,11>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

1

1

CD40

2

2

PCH_SMBDATA <6, 11,14,28,32>
PCH_SMBCLK <6,11,14, 28,32>

RD17
1K_0402_1%~D

CD41

+1.5V

12

12

RD18
1K_0402_1%~D

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-6801P

1

12 60Monday, December 06, 2010

0.3

5

PCH_RTCX1

32.768KHZ_12.5PF_Q13MC14610002

1

CH3
18P_0402_50V8J~D

2

1 2

RH27 33_0402_5%

1 2

RH28 33_0402_5%

1 2

RH33 33_0402_5%

1 2

RH275 1M_0402_5%~D

HDA_SDO<31>

12

RH39

@

200_0402_5%

12

RH45
100_0402_1%~D

1 2

RH53 51_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD#

@

12

1 2

CH98

12

@

10P_0402_50V8J~D

PCH_RTCX2

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1 2

RH24 0_0402_5%~D

1 2

RH30 33_0402_5%

12

RH40

@

200_0402_5%

12

RH46

100_0402_1%~D

+3V_PCH

12

@

RH267
10K_0402_5%~D

DP_PCH_HPD

RH268
100K_0402_5%~D

@

1 2

@

RH256

PCH_SPI_CLK_R

33_0402_5%

PCH_SPI_CLK

+RTCVCC

1U_0603_10V4Z

1 2

RH25 20K_0402_5%~D

1 2

RH23 20K_0402_5%~D

1U_0603_10V4Z

QH1BSS138_SOT23

1 2

RH36 0_0402_5%~D

@

1M_0402_5%~D

CMOS

CLRP1

CLRP2

ME CMOS

HDA_SPKR<24>

HDA_SDIN0<24>

DP_PCH_HPD<38>

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

SM_INTRUDER#

RH255 0_0402_5%~D

RH11

CH4

CH5

+5VS

G

2

S

@

HDA_SDOUT

HDA_SDOUT

1 2

1

2

1

2

13

D

PCH_SPI_CLK_R

12

SHORT PADS

12

SHORT PADS

CLP1 & CLP2 place near DIMM

HDA_SYNC

close to UH1

+3V_PCH

@

1 2

1 2

RH58 0_0402_5%~D

PCH_SPI_SO PCH_SPI_SO_R

1 2

RH60 33_0402_5%

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

12

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

RH57

3.3K_0402_5%

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

1 2

RH2 10M_0402_5%

18P_0402_50V8J~D

1

1

CH2

OSC4OSC

2

D D

C C

B B

A A

YH1

NC3NC

2

far away hot spot

HDA_BITCLK_AUDIO<24>

HDA_RST_AUDIO#<24>

HDA_SYNC_AUDIO<24>

HDA_SDOUT_AUDIO<24>

+3V_PCH +3V_PCH+3V_PCH

12

RH38

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH44

100_0402_1%~D

PCH_JTAG_TCK

+3V_PCH

1 2

RH54 3.3K_0402_5%

1 2

RH56 3.3K_0402_5%

CH94

22P_0402_50V8J~D

Reserve for EMI please close to U48

Reserve for RF please close t o UH1

5

4

@

HDA_SDOUT

12

CH103 10P_0402_50V8J~D

@

HDA_BIT_CLK

12

CH97 10P_0402_50V8J~D

Reserve for RF please close t o UH1

ES2@

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CougarPoint_Rev_1p0

SA00003P42L

RTCIHDA

JTAG

SPI

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATA3RCOMPO

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI ROM FOR ME ( 4MByte )

SPI ROM FOR ME
( 4MByte )

U48

1

/CS

2

DO

3

/WP

GND4DIO

W25X32VSSIG_SO8~D

SPI BIOS Pinout

(1)CS# (5)DIO
(2)DO (6)CLK
(3)WP# (7)HOLD #
(4)GND (8)VCC

W25X32

4

/HOLD

8

VCC

PCH_SPI_HOLD#

7

PCH_SPI_CLK_R

6

CLK

5

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

RH63 33_0402_5%

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

1 2

UH1

BD82HM67 QNDK B1

SA00004ED0L

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

PCH_SPI_SIPCH_SPI_SI_R

3

QS@

LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>

LPC_FRAME# <31>

SERIRQ <31>

CH91 0.01U_0402_16V7K~D

1 2

CH90 0.01U_0402_16V7K~D

1 2

CH92 0.01U_0402_16V7K~D

1 2

CH93 0.01U_0402_16V7K~D

1 2

PCH_SATALED# <35>

10K_0402_5%~D

12

+1.05VS_VCC_SATA

+1.05VS_SATA3

1 2

RH41 37.4_0402_1%

1 2

RH43 49.9_0402_1%

1 2

RH48 750_0402_1%~D

RH276

+3V_PCH

1

CH6

0.1U_0402_16V7K~D

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

Issued Date

2

SATA_PRX_DTX_N1 <28>
SATA_PRX_DTX_P1 <28>
SATA_PTX_DRX_N1_C <28>
SATA_PTX_DRX_P1_C <28>

SATA_PRX_DTX_N2 <28>
SATA_PRX_DTX_P2 <28>
SATA_PTX_DRX_N2_RP <28>
SATA_PTX_DRX_P2_RP <28>

HDD1

ODD

PCH_INTVRMEN

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

RTC Battery

DH4

+RTCVCC

W=20mils

1

2

+CHGRTC

2010/12/01 2011/12/01

BAS40-04_SOT23-3

CH95
1U_0603_10V4Z

RH260

0_0603_5%~D

@

Compal Secret Data

Deciphered Date

2

RH31 330K_0402_5%

RH34 330K_0402_5%@

+RTCBATT

RH259
1K_0402_5%~D

1 2
1

W=20mils

+CHGRTC

2

3

W=20mils

RH261

0_0603_5%~D

12

12

@

1

+3VS

SERIRQ

+RTCVCC

12

12

RH29 10K_0402_5%~D

PCH_GPIO21

RH32 10K_0402_5%~D

PCH_SATALED#PCH_INTVRMEN

RH35 10K_0402_5%~D

HDA_SPKR

RH37 1K_0402_5%~D@

*

HDA_SDOUT

RH42 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

HDA_SYNC

This signal has a weak intern al pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for H uron River plat from

HDA_SYNC

RH52 1K_0402_5%~D

12

12

12

12

12

LOW=Default
HIGH=No Reboot

12

+3V_PCH

+3VS

+3V_PCH

+3VLP

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-6801P

1

of

13 60Monday, December 06, 2010

0.3

5

PCIE_PRX_GLANTX_N3<22>

@

CH21

1 2

PCIE_PRX_GLANTX_P3<22>
PCIE_PTX_GLANRX_N3<22>
PCIE_PTX_GLANRX_P3<22>

PCIE_PRX_WANTX_N2<32>

PCIE_PRX_WANTX_P2<32>
PCIE_PTX_WANRX_N2<32>
PCIE_PTX_WANRX_P2<32>

PCIE_PRX_WLANTX_N1<32>

PCIE_PRX_WLANTX_P1<32>
PCIE_PTX_WLANRX_N1<32>
PCIE_PTX_WLANRX_P1<32>

PCIE_PRX_CARDTX_N4<23>

PCIE_PRX_CARDTX_P4<23>
PCIE_PTX_CARDRX_N4<23>
PCIE_PTX_CARDRX_P4<23>

PCIE_PRX_USB3TX_N6<27>

PCIE_PRX_USB3TX_P6<27>
PCIE_PTX_USB3RX_N6<27>
PCIE_PTX_USB3RX_P6<27>

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

USB 3.0 --->

@

CLK_PCH_14M

RH86

33_0402_5%

12

22P_0402_50V8J~D

CH9 0.1U_0402_10V7K~D

1 2

CH14 0.1U_0402_10V7K~D

1 2

CH10 0.1U_0402_10V7K~D

1 2

CH15 0.1U_0402_10V7K~D

1 2

CH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~D

1 2

CH12 0.1U_0402_10V7K~D

1 2

CH13 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~D

1 2

Reserve for EMI please close t o UH1

C C

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH1

RH89

33_0402_5%

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

B B

YH2

25MHZ_18PF_1Y725000CE1A~D

1 2

22P_0402_50V8J~D

1

CH23

2

A A

@

@

CH22

1 2

12

22P_0402_50V8J~D

10/100/1G LAN --->

Card Reader --->

USB 3.0 --->

XTAL25_IN

CH24

1

2

XTAL25_OUT

22P_0402_50V8J~D

12

RH1171M_0402_5%~D

+3V_PCH

CLK_PCIE_LAN#<22>
CLK_PCIE_LAN<22>

LANCLK_REQ#<22>

CLK_PCIE_MINI2#<32>
CLK_PCIE_MINI2<32>

MINI2CLK_REQ#<32>

CLK_PCIE_MINI1#<32>
CLK_PCIE_MINI1<32>

MINI1CLK_REQ#<32>

CLK_PCIE_CD#<23>
CLK_PCIE_CD<23>

CDCLK_REQ#<23>

+3V_PCH

+3V_PCH

CLK_PCIE_USB30#<27>
CLK_PCIE_USB30<27>

+3V_PCH

USB30_CLKREQ#<27>

+3V_PCH

CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>

CLK_RES_ITP#<8>
CLK_RES_ITP<8>

CLK_CPU_ITP#
CLK_CPU_ITP

RH91 10K_0402_5%~D

RH93 0_0402_5%~D
RH94 0_0402_5%~D

RH95 10K_0402_5%~D@

+3VS

RH96 0_0402_5%~D
RH97 0_0402_5%~D
RH100 10K_0402_5%~D

+3VS

RH101 0_0402_5%~D
RH102 0_0402_5%~D
RH103 10K_0402_5%~D

+3V_PCH

RH104 0_0402_5%~D
RH106 0_0402_5%~D
RH107 10K_0402_5%~D

+3V_PCH

RH110 10K_0402_5%~D

RH112 10K_0402_5%~D

RH114 0_0402_5%~D
RH115 0_0402_5%~D
RH116 10K_0402_5%~D

RH118 10K_0402_5%~D

RH119 0_0402_5%~D
RH120 0_0402_5%~D

RH121 0_0402_5%~D@
RH122 0_0402_5%~D@

1 2

1 2
1 2

1 2

1 2

1 2

1 2

12

12
12
12

12
12
12

12
12
12

12
12

12
12

12
12

4

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WANTX_N2
PCIE_PRX_WANTX_P2
PCIE_PTX_WANRX_N2_C
PCIE_PTX_WANRX_P2_C

PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1
PCIE_PTX_WLANRX_N1_C
PCIE_PTX_WLANRX_P1_C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C

PCIE_PRX_USB3TX_N6
PCIE_PRX_USB3TX_P6
PCIE_PTX_USB3RX_N6_C
PCIE_PTX_USB3RX_P6_C

T81PAD~D @
T82PAD~D @

PCIECLKREQ0#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD#
PCIE_CD

CDCLK_REQ#

PEG_B_CLKREQ#

PCIE_USB30#
PCIE_USB30

USB30_CLKREQ#

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

CLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_1p0

ES2@

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_LID_SW_IN#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

CLK_CPU_DPLL#

AM12

CLK_CPU_DPLL

AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

KB_DET#

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

CAM_DET#

DMC_PCH_DET#

BT_DET#

KB_DET#

MEMORY

Total device

+3V_PCH

1 2

RH113 90.9_0402_1%

1 2

RH166 10K_0402_5%~D

1 2

RH109 10K_0402_5%~D

1 2

RH108 10K_0402_5%~D

12

R1791 100K_0402_5%~D

2

EC_LID_OUT#

1 2

RH680_0402_5%~D

@

1 2

RH710_0402_5%~D

DRAMRST_CNTRL_PCH <7>

20090512
add double mosfet prevent
ATI M92 electric leakage

RH141
10K_0402_5%~D

1 2

CLK_PEG_VGA# <40>
CLK_PEG_VGA <40>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>

CLK_PCI_LPBACK <16>

KB_DET# <29>

DMC_PCH_DET# <37>

BT_DET# <32>

CAM_DET# <21>

PEG_A_CLKRQ# <40>

SMBCLK

DMN66D0LDW-7_SOT363-6~D

SMBDATA

+1.05VS_VCCDIFFCLKN

SML1CLK

SML1DATA

+3VS

EC_LID_OUT# <31>

LID_SW_IN# <31,34,35>

2

6 1

QH3A
RH105

@

1 2

0_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

6 1

DMN66D0LDW-7_SOT363-6~D

QH4A

DMN66D0LDW-7_SOT363-6~D

3

1 2

0_0402_5%~D

+3VS

2

3

+3VS

2.2K_0402_5%~D

5

QH3B
RH111

@

QH4B

1

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

LID_SW_IN#

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, pleas e place close to CLK gen
else, please p lace close to P CH

+3VS

RH98

1 2

4

5

4

1 2

RH67 2.2K_0402_5%~D

1 2

RH69 2.2K_0402_5%~D

1 2

RH70 2.2K_0402_5%~D

1 2

RH72 2.2K_0402_5%~D

1 2

RH73 2.2K_0402_5%~D

1 2

RH74 2.2K_0402_5%~D

1 2

R1790 10K_0402_5%~D

@

1 2

RH75 1K_0402_5%~D

RH76 10K_0402_5%~D

1 2

RH78 10K_0402_5%~D

1 2

RH77 10K_0402_5%~D

1 2

RH79 10K_0402_5%~D

1 2

RH80 10K_0402_5%~D

1 2

RH81 10K_0402_5%~D

1 2

RH82 10K_0402_5%~D

1 2

RH83 10K_0402_5%~D

1 2

RH84 10K_0402_5%~D

1 2

RH99

2.2K_0402_5%~D

1 2

PCH_SMBCLK <6,11,12,28,32>

PCH_SMBDATA <6,11,12,28,32>

PCH_SMLCLK <31,51>

PCH_SMLDATA <31,51>

+3V_PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-6801P

1

of

14 60Monday, December 06, 2010

0.3

5

Compal Electronics, Inc.

UH1C

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>

D D

XDP_DBRESET#<6>

C C

PM_DRAM_PWRGD<6>

SUSWARN# SUSACK#_R

B B

GPIO72

RI#

WAKE#

AC_PRESENT

SUSWARN#

PCH_RSMRST#

SYS_PWROK

A A

DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

4mil width and place
within 500mil of the PCH

SUSACK#<31>

PCH_PWROK

PCH_APWROK<31>

PCH_RSMRST#<31>

SUSWARN#<31>

PBTN_OUT#<6,31 >

AC_PRESENT<31>

1 2

RH139 0_0402_5%~D

RH143 10K_0402_5 %~D

1 2

RH145 10K_0402_5 %~D

1 2

RH146 10K_0402_5 %~D

1 2

RH150 10K_0402_5 %~D@

1 2

RH154 10K_0402_5 %~D

1 2

RH159 10K_0402_5 %~D

1 2

RH272 10K_0402_5 %~D

1 2

PCH_PWROK<6,31>

VGATE<6,31,57>

RH124 49.9_0 402_1%

RH125 750_0 402_1%~D

PCH_PWROK

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

1 2

RH127 0_0402_5%~D

RH273 0_0402_5 %~D

RH130 0_0402_5 %~D

RH131 0_0402_5 %~D

RH133 0_040 2_5%~D

RH134 0_040 2_5%~D

RH135 0_040 2_5%~D

RH137 0_040 2_5%~D

DMI_IRCOMP

RBIAS_CPY

1 2

XDP_DBRESET#

@

1 2

1 2

1 2

PM_DRAM_PWRGD

PCH_RSMRST#_R

1 2

1 2

1 2

1 2

GPIO72

+3V_PCH

+3VS

1

CH96

0.1U_0402_16V7K~D

2

1

IN1

2

IN2

SUSACK#_R

SYS_PWROK

PM_PWROK_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

RI#

BC24
BE20
BG18
BG20

BE24
BC20

BJ18
BJ20

AW24
AW20

BB18
AV18

AY24
AY20
AY18
AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

CougarPoint_Rev_1p0

ES2@

DSWODVREN

DSWODVREN

DSWODVREN - On Die DSW VR Enable

*

5

UH7

VCC

SYS_PWROK

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

3

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

RH147 330K_0402 _5%

RH151 330K_0402 _5%@

H：Enable
L：Disable

SYS_PWROK <6>

4

FDI_CTX_PRX_N0

BJ14

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

12

+RTCVCC

AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

1 2

RH132 0_0402_5%~D

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5>
FDI_CTX_PRX_P1 < 5>
FDI_CTX_PRX_P2 < 5>
FDI_CTX_PRX_P3 < 5>
FDI_CTX_PRX_P4 < 5>
FDI_CTX_PRX_P5 < 5>
FDI_CTX_PRX_P6 < 5>
FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5 >

FDI_FSYNC1 <5 >

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

@

RH126 0_0402_5%~D

1 2

RH128 0_0402_5%~D

12

If not using integrated
LAN,signal may be left as NC.

PCH_DPWROK <31>

T76 PAD~D

PM_SLP_S5# <31,34>

PM_SLP_S4# <31>

PM_SLP_S3# <31,34>

PM_SLP_SUS# <31>

H_PM_SYNC <6>

PCH_RSMRST#_R

PCIE_WAKE# <22,31,32>

SUSCLK_R <31>

SUSCLK

Reserve for RF please close to UH1

3

VGA_LVDDEN<21,31>

LVDS_DDC_CLK<21>

LVDS_DDC_DATA<21>

LVDS_ACLK-< 21>
LVDS_ACLK+<21>

LVDS_A0-<21>
LVDS_A1-<21>
LVDS_A2-<21>

LVDS_A0+<21>
LVDS_A1+<21>
LVDS_A2+<21>

LVDS_BCLK-< 21>
LVDS_BCLK+<21>

LVDS_B0-<21>
LVDS_B1-<21>
LVDS_B2-<21>

LVDS_B0+<21>
LVDS_B1+<21>
LVDS_B2+<21>

CRT_B<21>
CRT_G<21>
CRT_R<21>

CRT_DDC_CLK<21>
CRT_DDC_DATA<21>

CRT_HSYNC< 21>
CRT_VSYNC<21>

Can be left NC when IAMT is
not support on the platfrom

CH102

12

@

10P_0402_50V8J~D

+3VS

@

1 2

RH148 2.2K_0402_5%~D

@

1 2

RH152 2.2K_0402_5%~D

1 2

RH155 2.2K_0402_5%~D

1 2

RH157 2.2K_0402_5%~D

1 2

RH248 8.2K_0402_5%~D@

+3VS

RV169 2 .2K_0402_5%~D

1 2

RV170 2 .2K_0402_5%~D

1 2

ENBKL<31>

VGA_PWM<21>

1K_0402_0.5%~D

ENBKL

LVDS_DDC_CLK
LVDS_DDC_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

T203PAD~D

LVDS_ACLK­LVDS_ACLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_BCLK­LVDS_BCLK+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

CRT_B
CRT_G
CRT_R

CRT_DDC_CLK
CRT_DDC_DATA

RH136 33_0402_5%

RH138 33_0402_5%

1 2
1 2

RH140

CRT_DDC_CLK

CRT_DDC_DATA

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

HSYNC
VSYNC

CRT_IREF

12

LVDS_DDC_CLK
LVDS_DDC_DATA

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CougarPoint_Rev_1p0

ES2@

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DMC

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46
P42

AP47

DDPC_AUXN

AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

PCH_DPD_CLK

M43

PCH_DPD_DAT

M36

AT45

DDPD_AUXN

AT43

DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

1 2

RH167 10K_0402_5%~D

1 2

RH144 2.37K_0402_1%~D

1 2

RH149 150_0402_1%~D

1 2

RH153 150_0402_1%~D

1 2

RH156 150_0402_1%~D

1 2

RH158 100K_0402_5%~D

1 2

RH123 100K_0402_5%~D

BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PCH_DMC_HPD

PCH_DPD_N0
PCH_DPD_P0
PCH_DPD_N1
PCH_DPD_P1
PCH_DPD_N2
PCH_DPD_P2
PCH_DPD_N3
PCH_DPD_P3

PM_CLKRUN#

LVDS_IBG

CRT_B

CRT_G

CRT_R

VGA_LVDDEN

ENBKL

1

PCH_DPD_CLK <37>
PCH_DPD_DAT < 37>

PCH_DMC_HPD <37>

PCH_DPD_N0 <37>
PCH_DPD_P0 <37>
PCH_DPD_N1 <37>
PCH_DPD_P1 <37>
PCH_DPD_N2 <37>
PCH_DPD_P2 <37>
PCH_DPD_N3 <37>
PCH_DPD_P3 <37>

DMC
( HDMI )

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-6801P

1

15 60Monday, December 06, 2010

0.3

5

D D

C C

B B

A A

+3V_PCH

12

1 2

@

RH269
10K_0402_5%~D

CARD_HPLUG

RH264
100K_0402_5%~D

@

CLK_PCI_LPBACK<14>

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#

T123P AD~D @

12

T165P AD~D @
T166P AD~D @
T204P AD~D @

+3VS

DGPU_SELECT#
DGPU_PWR_EN

DMC_RADIO_OFF#

WL_OFF#

FFS_INT1
ODD_DA#
DP_CBL_DET
CARD_HPLUG

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

DGPU_SELECT#<37>

DGPU_PWR_EN<33,43,55,56>

DMC_RADIO_OFF#<32>

WL_OFF#<32>

FFS_INT1<28>

ODD_DA#<28>

DP_CBL_DET<38>

CARD_HPLUG<23>

CLK_PCI_LPBACK

CLK_PCI_LPC<31>

CLK_PCI_LPC

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#

DMC_RADIO_OFF#
DGPU_SELECT#
DGPU_PWR_EN
FFS_INT1

PCI_PIRQA#

ODD_DA#

DGPU_HOLD_RST#

RH164 22_0402_5%
RH165 22_0402_5%

1 2

RPH3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RPH4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RPH5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RH173 10K_0402_5%~D

1 2

BG26

BJ26

BH25

BJ16
BG16
AH38
AH37
AK43
AK45

C18
N30

H3

AH12

AM4
AM5

Y13
K24

L24
AB46
AB45

B21

M20
AY16
BG46

BE28
BC30
BE32

BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28

AW30

K40
K38
H38

G38

C46
C44
E40

D47
E42
F46

G42
G40

C42
D44

K10

C6

H49
H43
J48
K42
H40

CougarPoint_Rev_1p0

ES2@

10K_0402_5%~D

PLT_RST#<6,22,23,27,31,32>

4

UH1E

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

@

RH169

+3VS

RSVD

1 2

PCI

USB

12

RH171
100K_0402_5%~D

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

@

1 2

RH168 0_0402_5%~D

+3VS

5

UH5

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8

AY5
BA2

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

NV_ALE

USB20_N9
USB20_P9
USB20_N8
USB20_P8
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

USBRBIAS

USB_OC2#
USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
USB_OC0#
USB_OC5#
USB3_SMI#
USB_OC6#

PCH_PLTRST#

3

USB20_N9 <26>
USB20_P9 <26>
USB20_N8 <32>
USB20_P8 <32>
USB20_N3 <21>
USB20_P3 <21>
USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>
USB20_N6 <34>
USB20_P6 <34>

Within 500 mils

1 2

RH163 22.6_0402_1%

USB/B

Bluetooth

Camera

Mini Card(WLAN)

Mini Card(Mini2)

ELC LED

PLTRST_VGA#<40>

USB_OC2# <26>

1.5VDDR_VID0 <53>

1.5VDDR_VID1 <53>

USB3_SMI# <27>

12

100_0402_5%~D

100K_0402_5%~D

(For USB Port 9)

1 2

RH254 0_0402_5%~D@

RH170

4

Y

12

RH172

+3VS

5

UH6

2

P

B

DGPU_HOLD_RST#

1

A

G

SN74AHC1G08DCKR_SC70-5

3

2

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floa ting)

NV_ALE

RH160 1K_0402_5%~D@

1 2

USB_OC0#
USB_OC2#
USB3_SMI#
USB_OC5#

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
USB_OC6#

1 2

RH265 0_0402_5%~D@

1 2

RH266 0_0402_5%~D

*

RPH1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

RPH2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

DGPU_PWROK

PCH_PLTRST#

1

+1.8VS

+3V_PCH

DGPU_PWROK <17,38,39,55,56>

CH99

CLK_PCI1

12

@

10P_0402_50V8J~D

Reserve for RF please close to UH1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-6801P

1

16 60Monday, December 06, 2010

0.3

5

+3V_PCH

12

RH270
10K_0402_5%~D

HDMI_PCH_HPD# GPIO6

D D

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage regulator enabl e

*

L：On-Die PLL Voltage Regulator d isable

RH177 1K_0402_5%~D@

PCH_GPIO37

C C

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage
(DC Coupling Mode)

+3VS

RH181 1K_0402_5%~D@

RH182

1 2

1 2

12

PCH_GPIO28

10K_0402_5%~D

PCH_GPIO37

PCH_GPIO37

GPIO27

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

RH186 10K_0402_5%~D@

B B

High: CRT Plugged

A A

CRT_DET#<21>

1 2

CRT_DET

QH5

SSM3K7002F_SC59-3

5

PCH_GPIO27

+3VS

2

G

RH198
10K_0402_5%~D

1 2

13

D

S

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

4

CRT_DET

DGPU_EDIDSEL#<37>

EC_SCI#<31>

EC_SMI#<31>

BT_RADIO_DIS#<32>

HDMI_PCH_HPD#<39>

DGPU_PWROK<16,38,39,55,56>

BT_ON#<32>

ODD_DETECT#<28>

FFS_INT2<28>

HDD_DETECT#<28>

4

DGPU_EDIDSEL#

EC_SCI#

EC_SMI#

BT_RADIO_DIS#

HDMI_PCH_HPD#

GPIO16

DGPU_PWROK

PCH_GPIO22

PCH_GPIO27

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

FFS_INT2

GPIO49

HDD_DETECT#

UH1F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_Rev_1p0

ES2@

GPIO

3

ODD_EN#

C40

GPIO69

B41

C41

A40

P4

A20GATE

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PECI

NC_1

Issued Date

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

3

ODD_EN# <28>

T126 P AD~D@

@

1 2

RH1750_0402_5%~D

KB_RST# <31>

H_CPUPWRGD <6>

1 2

2010/12/01 2011/12/01

RH176390_0402_5%

H_PECI <6,31>

H_THERMTRIP#

12

@

RH178
10K_0402_5%~D

Compal Secret Data

2

+3VS

RH174
10K_0402_5%~D

1 2

H_THERMTRIP# <6>

INIT3_3V

This signal has weak internal
P

U, can't pull lo w

Deciphered Date

2

GATEA20 <31>

CRT_DET#

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

PCH_GPIO22

GPIO35

GPIO49

PCH_GPIO38

PCH_GPIO39

GPIO6

DGPU_EDIDSEL#

ODD_EN#

HDD_DETECT#

EC_SMI#

1

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

+1.8VS

12

RH161

2.2K_0402_5%~D

12

RH1621K_0402_5%~D

H_SNB_IVB# <6>

CLOSE TO THE BRA NCHING POINT

RH161 and RH162
Follow CRB FAB2 setting

+3VS

RH180 10K_0402_5%~D

1 2

+3V_PCH

10K_0402_5%~D

1 2

RH187

10K_0402_5%~D

1 2

RH188

10K_0402_5%~D

1 2

RH190

+3VS

10K_0402_5%~D@

1 2

RH192

200K_0402_5%

1 2

RH193

10K_0402_5%~D

1 2

RH274

8.2K_0402_5%~D

1 2

RH195

10K_0402_5%~D

1 2

RH196

10K_0402_5%~D

1 2

RH197

10K_0402_5%~D

1 2

RH257

10K_0402_5%~D

1 2

RH258

10K_0402_5%~D

1 2

RH262

10K_0402_5%~D

1 2

RH263

10K_0402_5%~D

1 2

RH271

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-6801P

1

17 60Monday, December 06, 2010

0.3

of

5

4

3

2

1

+1.05VS

@

J10

12

PAD-OPEN 4x4m

D D

+1.05VS

+1.05VS

+VCCAPLLEXP_R

@

RH201 0_0603_5%~D

12

1

2

RH200 0_0603_5%~D

1 2

1UH_LB2012T1R0M_20%~D

Place CH40 Near BJ22 pin

+1.05VS

12

RH203

0_0805_5%~D

C C

+3VS

+1.05VS

B B

12

RH206
0_0805_5%~D

+3VS_VCCA3GBG

1

CH44

0.1U_0402_10V7K~D

2

Place CH53 Near BG6 pin

@

RH208 0_0603_5%~D

12

1

1

CH37

2

2

10U_0805_4VAM~D

1

CH46

2

@

1

CH28

CH27

2

10U_0805_4VAM~D

12

LH3

@

+1.05VS_VCC_EXP

1

CH39

CH38

2

1U_0402_6.3V6K~D

+1.05VS

1U_0402_6.3V6K~D

+1.05VS_VCCCORE

1

CH25

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCDPLLEXP

1

2

@

1

1

CH40

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCAPLL_FDI

RH209

+1.05VS_VCCDPLL_FDI

1 2

0_0805_5%~D

+VCCP_VCCDMI

1

CH26

2

1U_0402_6.3V6K~D

+VCCAPLLEXP

CH35

10U_0805_4VAM~D

CH41

1U_0402_6.3V6K~D

+VCCAFDI_VRM

UH1G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CougarPoint_Rev_1p0

ES2@

2925mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1

mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

20mA

VCCDFTERM[1]

190mA

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

1

CH29

2

+VCCTX_LVDS

CH32

0.01U_0402_16V7K~D

1

CH36

0.1U_0402_10V7K~D

2

1

CH45

2

1

2

1

CH30

2

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

Near AP43

1

2

RH202

1 2

0_0805_5%~D

+VCCP_VCCDMI

1 2

0_0805_5%~D

1

CH43
1U_0402_6.3V6K~D

2

+VCCPNAND

0.1U_0402_10V7K~D
RH210

1 2

0_0805_5%~D

CH47
1U_0402_6.3V6K~D

LH1

BLM18PG181SN1_0603~D

1

CH31
10U_0805_4VAM~D

2

RH199 0_0805_5%

1 2

CH34

1

CH33

0.01U_0402_16V7K~D

2

RH205

1 2

RH207 0_0805_5%~D

+3V_PCH

1

22U_0805_6.3V6M~D

2

+3VS

+1.05VS

+3VS

12

LH2

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

RH204

1 2

1

0_0805_5%~D

CH42

2

1U_0402_6.3V6K~D

+1.8VS

+3VS

+1.8VS

12

+1.05VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

+3VALW

1

1U_0402_6.3V6K~D

A A

5

C432

SUSP#<10,31,33,53,54>

4

2

SUSP#

U47

1

VIN

3

EN

RT9013-15GB_SOT23-5

+1.5VS +VCCAFDI_VRM

RH211

+VCCAFDI_VRM

12

0_0603_5%~D

VOUT

GND

5
4

NC

2

RH212

0_0603_5%~D

@

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

LA-6801P

1

18 60Monday, December 06, 2010

0.3

VCCVRM = 1 60mA detal waiting f or newest spec

5

4

3

2

1

+1.05VS

+3V_PCH

+3V_DSW

D D

+1.05VS

PCH_VREG_EN#<31>

C C

+3VS

RH216

@

1 2

0_0805_5%~D

+3VALW +3V_DSW

QH6
AO3419L_SOT23-3

S

G

2

1 2

RH214 0_0603_5%~D

1 2

RH221 0_0603_5%~D@

LH4

@

D

13

10UH_LBR2012T100M_20%~D

1 2

10U_0805_10V4Z~D

@

1

+1.05VS

CH49

2

+1.05VS

1 2

RH225 0_0805_5%~D

+VCCAPLL_CPY +3VS_VCC_CLKF33

1

CH48

0.1U_0402_10V7K~D

2

0.1U_0402_10V7K~D

1 2

RH219 0_0603_5%~D

@

RH213 0_0603_5%~D

CH51

@

1

CH57

2

22U_0805_6.3V6M~D

1

CH60

2

1U_0402_6.3V6K~D

5/18 delete RH229

LH5

+3VS_VCC_CLKF33_R

1 2

RH2300_0805_5 %~D

+1.05VS

B B

A A

+1.05VS

@

RH234 0_0603_5%~D

+1.05VS

+1.05VS

+1.05VS

1 2

RH247

12

RH235 0_0603_5%~D

+1.05VS

+VCCA_DPLL_L

0_0805_5%~D

12

5

10UH_LBR2012T100M_20%~D

1 2

+1.05VM_VCCSUS

1

CH72

1U_0402_6.3V6K~D

2

RH237 0_0603_5%~D

RH239 0_0603_5%~D

1 2

RH242 0_0603_5%~D

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

12

12

LH7

1 2

1 2

LH8

+3VS_VCC_CLKF33

1

CH66

2

10U_0805_10V4Z~D

+1.05VS_VCCDIFFCLKN

1

CH74
1U_0402_6.3V6K~D

2

1

CH77
1U_0402_6.3V6K~D

2

+V_CPU_IO

1

CH79

4.7U_0603_6.3V6K~D

2

1

+

CH86

2

1

CH67

2

1U_0402_6.3V6K~D

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

1

CH78

0.1U_0402_10V7K~D

2

1

CH80

2

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

1

CH87

2

1U_0402_6.3V6K~D

220U_B2_2.5VM_R35M~D

1

CH71

0.1U_0402_10V7K~D

2

1

2

0.1U_0402_10V7K~D

1

1

+

CH88

2

2

220U_B2_2.5VM_R35M~D

CH81

0.1U_0402_10V7K~D

CH89

12

1

2

1

CH58

2

22U_0805_6.3V6M~D

1

CH61

2

1U_0402_6.3V6K~D

+VCCRTCEXT

1

@

CH76
1U_0402_6.3V6K~D

2

+RTCVCC

1U_0402_6.3V6K~D

4

+VCCACLK

+VCCPDSW

+PCH_VCCDSW

+VCCAPLL_CPY_PCH

+VCCDPLL_CPY

+VCCSUS1

1

@

CH54
1U_0402_6.3V6K~D

2

+1.05VM_VCCASW

1

CH62

2

1U_0402_6.3V6K~D

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCSST

+1.05VM_VCCSUS

1

1

CH82

2

CH83

2

0.1U_0402_10V7K~D

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

1

2

0.1U_0402_10V7K~D

CH84

1U_0402_6.3V6K~D

CougarPoint_Rev_1p0

ES2@

POWER

N26

VCCIO[29]

P26

119mA

PCI/GPIO/LPCMISC

SATA USB

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLSATA

10mA

VCCSUSHDA

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

1mA

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

3

mA

1010mA

Clock and Miscellaneous

80mA

80mA

55mA

95mA

1mA

CPURTC

HDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

+1.05VS_VCCUSBCORE

1

CH50
1U_0402_6.3V6K~D

2

+3V_VCCPUSB

1

CH52

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS_1

+PCH_V5REF_RUN

+3V_VCCPSUS

1

CH63
1U_0402_6.3V

2

+3VS_VCCPPCI

+VCC3_3_2

+1.05VS_VCC_SATA

+VCCME_22

+VCCME_23

+VCCME_21

+VCCSUSHDA

1

CH850.1U_0402_10V7K ~D

2

+VCCAFDI_VRM

+VCCAFDI_VRM

Compal Secret Data

RH220 0_0603_5%~D

+3V_VCCAUBG

1

CH53

2

0.1U_0402_10V7K~D

RH223 0_0603_5%~D

0.1U_0402_10V7K~D

+3VS_VCCPCORE

RH232

1

2

+1.05VS_VCC_SATA

12

0_0603_5%~D

CH69

0.1U_0402_10V7K~D

+1.05VS_SATA3

+VCCSATAPLL

RH240 0_0603_5%~D

RH241 0_0603_5%~D

RH243 0_0603_5%~D

12

@

RH246

150_0402_1%~D

Deciphered Date

12

RH217 0_0603_5%~D

0.1U_0402_10V7K~D

1

2

1

2

+3VS

1

2

12

RH218 0_0603_5%~D

12

RH224 0_0603_5%~D

12

12

12

12

CH59

RH226
0_0603_5%~D

12

RH228 0_0805_5%~D

CH65

0.1U_0402_10V7K~D

RH231 0_0603_5%~D

1

CH68

0.1U_0402_10V7K~D

2

+1.05VS_SATA3

1

2

RH238

12

0_0805_5%~D

CH75

+1.05VS

1U_0402_6.3V6K~D

12

RH244 0_0603_5%~D

1 2

RH245 180_0402_1%@

2

+1.05VS

+3V_PCH

12

+1.05VS

+3V_PCH

12

RH233

0_0805_5%~D
CH70
1U_0402_6.3V6K~D

+1.05VS

VCC3_3 = 2 66mA detal waiting f or newest spec

CCDMI = 42 mA detal w aiting for newest s pec

V

QH7
AO3419L_SOT23-3

D

S

12

100_0402_5%~D

100_0402_5%~D

G

2

RH222

RH227

@

RH236

0_0805_5%~D

13

1

2

+3V_PCH+5V_PCH

12

+3VS+5VS

12

12

Compal Electronics, Inc.

1

PCH_PWR_EN#<33>

+3V_PCH

+VCCA_USBSUS

+3V_PCH

+3VS

+3VS

12

12

+1.05VS

LH6

@

10UH_LBR2012T100M_20%~D

1 2

1

CH73

@

10U_0805_10V4Z~D

2

+3V_PCH

+3V_PCH

RH215

0_0603_5%~D

1

CH55

2

@

1U_0402_6.3V6K~D

+VCCSATAPLL_R

Place CH80 Near AK1 pin

If it support 3.3V audio signals
POP:RH228
Depop RH233/RH234

If it support 1.5V audio signals
POP:RH233/RH234
Depop R228

Title

PCH (7/8) PWR

Size Document Number Rev

LA-6801P

Date: Sheet

+5V_PCH+5VALW

12

R22

C8

20K_0402_5%~D

0.1U_0402_10V7K~D

21

DH2
RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

1

CH56

0.1U_0603_25V7K

2

21

DH3
RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

1

CH64
1U_0603_10V6K~D

2

+1.05VS

19 60Monday, December 06, 2010

0.3

of

5

AA17

AA33
AA34
AB11
AB14
AB39

AB43

AC19

AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD4
AD40
AD42
AD43
AD45
AD46

AD8

AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38

AF42
AF46

AG19

AG2
AG31
AG48
AH11

AH3
AH36
AH39
AH40
AH42
AH46

AH7

AJ19
AJ21
AJ24
AJ33
AJ34

AK12

H5

AA2
AA3

AB4

AB5
AB7

AE2
AE3

AF4

AF5
AF7
AF8

AK3

ES2@

UH1H

VSS[0]

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

CougarPoint_Rev_1p0

D D

C C

B B

A A

5

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

4

3

UH1I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

CougarPoint_Rev_1p0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

ES2@

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

2

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

2

1

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (8/8) VSS

LA-6801P

1

20 60Monday, December 06, 2010

0.3

5

C R T

LU6 BLM18BB470SN1D_2P~D

CRT_R<15>

CRT_G<15>

D D

CRT_B<15>

CRT_DDC_DATA<15>

VGA_LVDDEN<15,31>

BKOFF#<31>

EC_INV_PWM<31>

CRT_DDC_CLK<15>

EC_ENVDD<31>

VGA_PWM<15>

+3VS

0.1U_0402_16V7K~D

C C

B B

A A

CU56

10P_0402_50V8J~D

12

@

EC_ENVDD

BKOFF# DISPOFF#

CH751H-40PT_SOD323-2~D

SN74AHC1G08DCKR_SC70-5

1

CV367

2

5

1 2

LU7 BLM18BB470SN1D_2P~D

1 2

LU8 BLM18BB470SN1D_2P~D

1 2

CU57

10P_0402_50V8J~D

CU58

10P_0402_50V8J~D

12

12

@

@

+3VS +CRT_VCC+3VS +CRT_VCC+3VS

2.2K_0402_5%~D
R370

R1834

2.2K_0402_5%~D

1 2

1 2

G

S

SSM3K7002FU_SC70-3~D

D37

2

1

3

BAT54C-7-F_SOT23~D

+3VS

12

R382

D69

+3VS +3VS

1

IN1

2

IN2

R944

@

0_0402_5%~D

R1837

@

0_0402_5%~D

+LCDVDD

4.7K_0402_5%~D

21

5

U54

P

4

O

G

3

12

12

0.1U_0402_16V7K~D

CV369

CV368

1

2

G

2

S

2

PMF3800SN_SC70-3

13

D

Q287

PMF3800SN_SC70-3

+LCDVDD +5VALW

1 2
13

D

Q288

S

R380

10K_0402_5%~D

12

R394

@

10K_0402_5%~D

INV_PWM

10U_0805_10V4Z~D

1

2

R366

150_0402_1%~D

12

13

D

Q286

R1847
100_0402_5%~D

2

G

12

2

150_0402_1%~D

12

1 2

G

R1832

12

R371

2.2K_0402_5%~D

1 2

13

CRT_R_C

CRT_G_C

CRT_B_C

R1833

150_0402_1%~D

1

2

2.2K_0402_5%~D

1 2

CRT_DDC_DATA_C

CRT_DDC_CLK_C

R377
47K_0402_5%

D

Q290
BSS138_SOT23~D

S

22P_0402_50V8J~D

@

R372

R378
56K_0402_5%

4

CU550.1U_0402_16V7K~D

12

L31 BLM18BB470SN1D_2P~D

L32 BLM18BB470SN1D_2P~D

L103 BLM 18BB470SN1D_2P~D

22P_0402_50V8J~D

22P_0402_50V8J~D

C537

C539

C538

1

1

2

2

@

@

1 2

1 2

1 2

CRT_HSYNC<15>

CRT_VSYNC<15>

CRT_R_L

CRT_G_L

CRT_B_L

For EMI

W=60mils

+3VS

S

AO3419L_SOT23-3

G

2

C549

0.47U_0402_16V4Z~D

1 3

EN_INVPWR<31>

+LCDVDD

C1748

0.1U_0402_16V7K~D

EN_CAM<31>

Q289

4.14

D

+LCDVDDVGA_LVDDEN

1

C1869

4.7U_0805_10V4Z~D

2

2

1

W=60mils

+LCDVDD

+5VS

2

G

1

2

R2005
0_0402_5%~D

R2006
0_0402_5%~D

12

13

12

1

2

D66

1

2

C540

10P_0402_50V8J~D

+CRT_VCC

3

@

+CRT_VCC

D15

DAN217_SC59-3

1

2

3

C541

10P_0402_50V8J~D

12

1

5

P

4

OE#

A2Y

G

U625

74AHCT1G125GW_SOT353-5

3

1

5

P

4

OE#

A2Y

G

U626
74AHCT1G125GW_SOT353-5

3

B+ +INV_PWR_SRC

DAN217_SC59-3

+3VS

12

@

C545

0.1U_0402_16V7K~D

1 2

C546

0.1U_0402_16V7K~D

1 2

CRT_VSYNC

60mil

C1126

1000P_0402_50V7K~D

1

+LCDVDD_R

D50

6

5

4

IP4223CZ6_SO6-6

S

G

V I/O

V BUS

V I/O

2

2

2

G

V I/O

Ground

V I/O

Q47

D

13

C551

0.1U_0402_16V7K~D

12

12

@

DMIC_CLK USB20_N3

DMIC0

SI2301CDS-T1-GE3_SOT23-3

R1653
100K_0402_5%~D

D

Q42
SSM3K7002F_SC59-3

S

EN_CAM# control circuit

4

D67
DAN217_SC59-3

1

2

C542

10P_0402_50V8J~D

12

@

R373

10K_0402_5%~D

1 2

R1835 0_0805_5%~D@

B+

R1242

100K_0402_5%~D

12

PWR_SRC_ON

12

R1243
100K_0402_5%~D

13

D

Q71
SSM3K7002FU_SC70-3~D

S

1

2

USB20_P3

3

+3VS_CAM+3VS

3

+5VS

2 1
3

W=40mils

3

1 2

Q70
SI3457BDV-T1-E3_TSOP6~D

S

4 5

G

3

BAT1000-7-F_SOT23-3~D

D_CRT_HSYNC HSYNC_LCRT_HSYNC

D_CRT_VSYNC

D

6

2
1

INV_PWM INV_PWM_R

1 2

1 2

+INV_PWR_SRC_R

1

C1127

0.1U_0603_50V_X7R

2

0_0402_5%~D

R1160

R1161

60mil

R1948

D68

NC

CRT_DET#<17>

0_0603_5%~D

0_0603_5%~D

R2015 0_0805_5%~D

1 2

FV3

1.1A_6VDC_FUSE

R2012

CRT_R_L

CRT_DDC_DATA_C
CRT_G_L

HSYNC_L
CRT_B_L

VSYNC_L

CRT_DDC_CLK_C

LVDS_DDC_CLK<15>
LVDS_DDC_DATA<15>

USB20_P3<16>
USB20_N3<16>
CAM_DET#<14>

DMIC0<24>

W=60mils

W=60mils

12

1

CU63
680P_0402_50V7K~D

2

21

0_1206_5%~D

12

@

T83PAD~D @

1

2

5P_0402_50V8C

5P_0402_50V8C @

+INV_PWR_SRC

W=40mils

100K_0402_5%~D

100P_0402_50V8J~D

VSYNC_L

C547

15P_0402_50V8J~D

+INV_PWR_SRC

INV_PWM_R
DISPOFF#
USB20_P3
USB20_N3
CAM_DET#
DMIC_CLK_R

DMIC0

+3VS_CAM

+3VS
+LCDVDD

1

2

C543

15P_0402_50V8J~D

@
1 2

1 2

2

+CRT_VCC+R_CRT_VCC

R1857

1

2

C548

C1133

C1132

12

1

C535

0.1U_0402_16V7K~D

2

LVDS_A0-<15>
LVDS_A0+<15>

LVDS_A1-<15>
LVDS_A1+<15>

LVDS_A2-<15>
LVDS_A2+<15>

LVDS_ACLK-<15>
LVDS_ACLK+<15>

LVDS_B0-<15>
LVDS_B0+<15>

LVDS_B1-<15>
LVDS_B1+<15>

LVDS_B2-<15>
LVDS_B2+<15>

LVDS_BCLK-<15>
LVDS_BCLK+<15>
LCD_TEST<31>

R3790_0402_5%~D
R1836 0_0402_5%~D

DMIC_CLK<24>

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

close to JLVDS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

JCRT1

16

G

17

G

SUYIN_070546HR015M25CZR

CONN@

+LCDVDD_R

LVDS_A0­LVDS_A0+

LVDS_A1­LVDS_A1+

LVDS_A2­LVDS_A2+

LVDS_ACLK­LVDS_ACLK+

LVDS_B0­LVDS_B0+

LVDS_B1­LVDS_B1+

LVDS_B2­LVDS_B2+

LVDS_BCLK­LVDS_BCLK+

LCD_TEST

EDID_CLK_LCD

12

EDID_DATA_LCD

12

1

+INV_PWR_SRC

R2014

100K_0402_5%

@

Q305A

+5VALW

@

2

12

@

12

61

R2013
820_0805_1%

3

@

Q305B

5

4

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

Discharg Circuit

LVDS Conn.

JLVDS

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

JAE_FI-G40SB-VF25-R2000-DT~D

CONN@

R1949

0_0402_5%~D

DMIC_CLK_RDMI C_CLK

12

1

CU64

@

470P_0402_50V7K~D

2

Title

VGA / LVDS /camera conn.

Size Document Number Rev

LA-6801P

Date: Sheet

5P_0402_50V8C

5P_0402_50V8C

41

G1

42

G2

43

G3

44

G4

45

G5

46

G6

47

G7

48

G8

49

G9

50

G10

51

G11

Compal Electronics, Inc.

1

C1134

1 2

C1135

1 2

LVDS_BCLK-

@

LVDS_BCLK+

@

0.3

of

21 60Monday, December 06, 2010

5

PCIE_PRX_GLANTX_P3_C

PCIE_PRX_GLANTX_P3<14>

PCIE_PRX_GLANTX_N3<14>

PCIE_PTX_GLANRX_P3<14>

PCIE_PTX_GLANRX_N3<14>

CLK_PCIE_LAN<14>

CLK_PCIE_LAN#<14>

LANCLK_REQ#<14>

D D

25MHz_12P_X5H025000FC1H-H

PLT_RST#<6,16,23,27,31,32>

PCIE_WAKE#<15,31,32>

YL1

1 2

1

CL18
15P_0402_50V8J~D

2

RL15

0_0402_5%~D

1 2

LAN_X2

1

CL19
15P_0402_50V8J~D

2

12

CL2 0.1U_0402_16V7K~D

12

CL1 0.1U_0402_16V7K~D

12

RL12 0_0402_5%~D

1 2

PCIE_PRX_GLANTX_N3_C

PCIE_PTX_GLANRX_N3

CLK_PCIE_LAN

CLK_PCIE_LAN#

CLKREQ_LAN#_R

PLT_RST#

PCIE_WAKE#

LAN_ACTIVITY

RL16

5.1K_0402_1%~D

Version A will be fail on 802.3a
need to update to Version B

LAN_X1
LAN_X2_R

LAN_LINK#_R
LAN_LED2#_R

30

29

35

36

33

32

4

2

3

25
26

28
27
41

7
8

38
39
23

UL1

TX_P

TX_N

RX_P

RX_N

REFCLK_P

REFCLK_N

CLKREQ#

PERST#

WAKE#

SMCLK
SMDATA

TEST_RST
TESTMODE
GND

XTLO
XTLI

LED_0
LED_1
LED_2

AR8151-BL1A

4

Atheros
AR8151 AL1A

TRXP0
TRXN0
TRXP1
TRXN1
TRXP2
TRXN2
TRXP3
TRXN3

AVDDL
AVDDL
AVDDL
AVDDL

AVDDL_REG

AVDDH
AVDDH

AVDDH_REG

DVDDL

DVDDL_REG

VDD33

VDDCT

RBIAS

3

LAN_MDIP0

11
12
14
15
17
18
20
21

13
19
31
34
6

16
22
9

24
37

1

40

LX

5

10

RL2 49.9_0402_1%

LAN_MDIN0

RL1 49.9_0402_1%

LAN_MDIP1

RL3 49.9_0402_1%

LAN_MDIN1

RL4 49.9_0402_1%

LAN_MDIP2PCIE_PTX_GLANR X_P3

RL5 49.9_0402_1%

LAN_MDIN2

RL7 49.9_0402_1%

LAN_MDIP3

RL8 49.9_0402_1%

LAN_MDIN3

RL9 49.9_0402_1%

+AVDDH

+DVDDL

W=40mils

+LAN_IO

+LX

+VDDCT

+RBIAS

RL14

1 2

2.37K_0402_1%~D

12
12
12
12
12
12
12
12

+LAN0

CL3 1000P_0402_50V7K~D

1 2

CL4 0.1U_0402_16V7K~D

1 2

+LAN1

CL5 1000P_0402_50V7K~D

1 2

CL6 0.1U_0402_16V7K~D

1 2

+LAN2

CL7 1000P_0402_50V7K~D

1 2

CL8 0.1U_0402_16V7K~D

1 2

+LAN3

CL9 1000P_0402_50V7K~D

1 2

CL10 0.1U_0402_16V7K~D

1 2

close to Lan chip 1000p reserved for EMI

2.2UH +-20% 1225AS-H-2R2M-P2 1.3A

+LX

W=40mils

LL1

+VDDCT

1 2

CL11

close to Lan pin40

1

CL12

2

1000P_0402_50V7K~D

1

2

CL13

10U_0603_6.3V6M~D

W=40mils

1

2

CL14

0.1U_0402_16V7K~D

1

2

close to Lan pin5

PLT_RST#

PCIE_WAKE#+AVDDL

2

1 2

1 2

CLKREQ_LAN#_R

+LAN_IO

12

RL6

4.7K_0402_5%~D@

RL10

4.7K_0402_5%~D@

RL11

1 2

RL13

0_0402_5%~D

+LAN_IO

4.7K_0402_5%~D

1

W=20mils

+DVDDL

1

1

1

CL15

2

0.1U_0402_16V7K~D
1U_0603_10V6K~D

CL17

CL16

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

close to Lan pin24close to Lan pin37

W=40mils

C C

1U_0402_6.3V6K~D

B+_BIAS

+3VALW

RL18

RL28

10K_0402_5%~D

EN_WOL#<31>

MURATA_BLM18AG601SN1D_0603

B B

close to LL2

470K_0402_5%~D

1 2

1 2

13

D

2

G

S

LL2

12

1

CL40

2

+3VALW

CL20

EN_WOL

QL2
SSM3K7002FU_SC70-3

+VDDCT_L+VDDCT

LAN_MDIP3
LAN_MDIN3

LAN_MDIP2
LAN_MDIN2

LAN_MDIP1
LAN_MDIN1

LAN_MDIP0
LAN_MDIN0

TIMAG: S X'FORM_ IH-160 LAN , SP050006F00

BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00

2

CL41

CL42

@

1

1U_0603_10V6K~D

1000P_0402_50V7K~D

1

2

1

2

2

CL43

@

1

0.1U_0402_16V7K~D

QL1

D

6

2
1

G

RL19

TS1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

350UH_GST5009-CLF

1

CL44

2

1000P_0402_50V7K~D

S

+LAN_IO_R

45

SI3456BDV-T1-E3 1N TSOP6

3

1 2

1.5M_0402_5%~D

RJ45_CT3

24

MCT1

RJ45_MDI3+

23

MX1+

RJ45_MDI3-

22

MX1-

RJ45_CT2

21

MCT2

RJ45_MDI2+

20

MX2+

RJ45_MDI2-

19

MX2-

RJ45_CT1

18

MCT3

RJ45_MDI1+

17

MX3+

RJ45_MDI1-

16

MX3-

RJ45_CT0

15

MCT4

RJ45_MDI0+

14

MX4+

RJ45_MDI0-

13

MX4-

2

1

CL45

CL46

@

1

2

0.1U_0402_16V7K~D
1000P_0402_50V7K~D

R2016

1

2

@

0.1U_0402_16V7K~D

1 2

0_0805_5%~D

CL36

0.1U_0402_25V6

2

CL47

1

1000P_0402_50V7K~D

1

CL48

2

W=40mils

CL31

1 2

75_0402_1%~D

1 2

75_0402_1%~D

1 2

75_0402_1%~D

1 2

75_0402_1%~D

0.1U_0402_16V7K~D

+LAN_IO

RL21

RL22

RL23

RL24

1

CL32

2

1000P_0402_50V7K~D

close to Pin 1

1A

1

CL33

2

0.1U_0402_16V7K~D

2

CL39
1000P_1808_3KV7K~D

1

W=20mils W=20mils

1

1

CL34

2

1U_0603_10V6K~D

1

CL35

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

+AVDDH +AVDDL

1

CL21

2

close to Lan pin16close to Lan pin9

1

CL22

1U_0603_10V6K~D

1

CL23

2

2

0.1U_0402_16V7K~D

1

CL24

2

0.1U_0402_16V7K~D

close to Lan pin22

RJ45_MDI0+

RJ45_MDI0-

RJ45_MDI1+

RJ45_MDI2+

RJ45_MDI2-

RJ45_MDI1-

RJ45_MDI3+

RJ45_MDI3-

JLAN1

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

FOX_JM36113-P2651-7F~D

CONN@

close to Lan pin6 close to Lan pin31

1

CL25

0.1U_0402_16V7K~D

1

CL27

CL26

2

2

0.1U_0402_16V7K~D

1U_0603_10V6K~D

close to Lan pin34

RL26 470_0402_5%~D

RL27 130_0402_1%~D

LAN_LED2#

9

LDE_ORANGE-

LDE_GREEN-

LED_YELLOW+

LED_YELLOW-

SHLD1

SHLD2

15

16

A2

NC

10

11

12

13

14

LAN_LINK#

LAN_LED_VCC1

LAN_ACTIVITY_R

1

CL28

2

0.1U_0402_16V7K~D

12

12

CL49 470P_0402_50V7K

1 2

CL38 470P_0402_50V7K

0_0402_5%~D

RL25 330_0402_5%

1

2

RL20

close to Lan pin19

1

CL29

2

0.1U_0402_16V7K~D

close to Lan pin13

LAN_LED2#_R

LAN_LINK#_R

12

12

LAN_ACTIVITY

12

0.1U_0402_16V7K~D

+LAN_IO

1

CL30

2

0.1U_0402_16V7K~D

close to TS1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

GLAN AR8151 AL1A/ RJ45

LA-6801P

1

22 60Monday, December 06, 2010

of

0.3

5

Zdiff = 100 ohm

PCIE_PTX_CARDRX_P4<14>

PCIE_PTX_CARDRX_N4<14>

CLK_PCIE_CD<14>

CLK_PCIE_CD#<14>

D D

PCIE_PRX_CARDTX_P4<14>

PCIE_PRX_CARDTX_N4<14>

10U_0603_6.3V6M~D

Removed CR17

22P_0402_50V8J~D

C C

PCIE_PTX_CARDRX_P4

PCIE_PTX_CARDRX_N4

+ODR_PWR

1

12

CR19

CR28

0.1U_0402_10V7K~D

2

SD_D1_R SD_D1

SD_D0_R SD_D0

CR25

SD_CLK_R SD_CLK

1 2

@

Reserved

CLK_PCIE_CD

CLK_PCIE_CD#

CR24 4.7U_0603_6.3V6K~D

1 2

PCIE_PRX_CARDTX_P4_CPCIE_PRX_CARDTX_P4

1 2

CR15 0.1U_0402_10V7K~D

PCIE_PRX_CARDTX_N4_CPCIE_PRX_CARDTX_N4

1 2

CR16 0.1U_0402_10V7K~D

1 2

CR22 0.1U_0402_10V7K~D

+3VS_CR

DV33_18

1

CR23

0.1U_0402_10V7K~D

SP1_SDD7_XDRDY

2

SP2_SDD6_XDRE#

SP3_SDD5_XDCE#

SP4_SDD4_XDWE#

1 2

RR20 0_0402_5%~D

1 2

RR19 0_0402_5%~D

1 2

RR23 33_0402_1%

1 2

RR24 0_0402_5%~D

1 2

RR21 0_0402_5%~D

1

HSIP

2

HSIN

3

REFCLKP

4

REFCLKN

AV12

5

AV12

6

HSOP

7

HSON

8

GND

DV12

9

DV12

10

Card1_3V3

11

3V3_IN

12

Card2_3V3

XD_CD#

13

XD_CD#

14

DV33_18

15

GND

16

SP1

17

SP2

18

SP3

19

SP4

20

SD_D1

21

SD_D0

22

SD_CMDSD_CMD_R

SD_D3SD_D3_R

SD_CLK

23

SD_CMD

24

SD_D3

RTS5209-GR_LQFP48_7X7

R2017

U135

1 2

0_0805_5%~D

4

+3VS_CR

R1563

RREF

RREF

3V3_IN

CLK_REQ#

PERST#

EEDO

EECS

EESK

GPIO/EEDI

MS_INS#

SD_CD#

SP15

SP14

SP13

SP12

SP11

SP10

DV12_S

SD_D2

48

47

CDCLK_REQ#

46

PLT_RST#

45

44

CARD_HPLUG_R CARD_HPLUG

43

42

41

MS_INS#

40

SD_CD#

39

SP15_SDWP_XDD7

38

SP14_MSCLK_XDD6

37

SP13_MSD7_XDD5

36

SP12_MSD3_XDD4

35

SP11_MSD6_XDD3

34

SP10_MSD2_XDD2

33

SP9_MSD0_XDD1

32

SP9

SP8_MSD4_XDD0

31

SP8

SP7_MSD1_XDWP#

30

SP7

SP6_MSD5_XDALE

29

SP6

SP5_MSBS_XDCLE

28

SP5

DV12_S

27

26

GND

SD_D2 SD_D2_R

25

+3VS_CR+3VS_CR+3VS

12

6.2K_0402_1%~D

CDCLK_REQ# <14>

PLT_RST# <6,16,22,27,31,32>

@

1 2

RR25 0_0402_5%~D

RR22 change to 0Ω

1 2

RR22 0_0402_5%~D

1 2

CR21

SP14_MSCLK_XDD6_R

CR20

1 2

4.7U_0603_6.3V6K~D

0.1U_0402_10V7K~D

1 2

RR12 0_0402_5%~D

CR27

12

0.1U_0402_10V7K~D

2

CR26
22P_0402_50V8J~D

1

@

3

CARD_HPLUG <16>

+ODR_PWR

12

RR3

For ver:ES2-B0

Place CR3 close to socket pin 22

Place CR4 close to socket pin 11

Place CR5 close to socket pin 11

Place CR6 close to socket pin 18

CR4

1

CR3

2

10K_0402_5%~D

0.1U_0402_10V7K~D

2

CR6

CR5

1

1

12

2

2

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

JREAD

CONN@

22

SP8_MSD4_XDD0
SP9_MSD0_XDD1

B B

A A

SP10_MSD2_XDD2
SP11_MSD6_XDD3
SP12_MSD3_XDD4
SP13_MSD7_XDD5
SP14_MSCLK_XDD6
SP15_SDWP_XDD7

SP4_SDD4_XDWE#
SP7_MSD1_XDWP#
SP6_MSD5_XDALE
XD_CD#
SP1_SDD7_XDRDY
SP2_SDD6_XDRE#
SP3_SDD5_XDCE#
SP5_MSBS_XDCLE

5

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP GND

42

SD CD/WP GND

T-SOL_144-1300002600_NR

SD4-VDD
MS9-VCC

SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3

SD2-CMD

SD-CD

SD-WP

SD6-VSS

SD3-VSS

MS8-SCLK

MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3

MS6-INS

MS2-BS

MS1-VSS

MS10-VSS

11
18

9
4
3
21
19
16
1
2

6
13

17
10
8
12
15
14
7
5
20

+ODR_PWR+ODR_PWR

SD_CLK_R
SD_D0_R
SD_D1_R
SD_D2_R
SD_D3_R
SD_CMD_R
SD_CD#
SP15_SDWP_XDD7

SP14_MSCLK_XDD6_R
SP9_MSD0_XDD1
SP7_MSD1_XDWP#
SP10_MSD2_XDD2
SP12_MSD3_XDD4
MS_INS#
SP5_MSBS_XDCLE

4

Reserve for EMI please close to JREAD1

@

RR8

1 2

33_0402_5%

Reserve for EMI
please close to JREAD1

@

RR11

1 2

33_0402_5%

1

CR18
22P_0402_50V8J~D@

2

@

CR14

12

22P_0402_50V8J~D

Co-lay connector for 2nd. 2010/11/26

+ODR_PWR

SP8_MSD4_XDD0
SP9_MSD0_XDD1
SP10_MSD2_XDD2
SP11_MSD6_XDD3
SP12_MSD3_XDD4
SP13_MSD7_XDD5
SP14_MSCLK_XDD6
SP15_SDWP_XDD7

SP4_SDD4_XDWE#
SP7_MSD1_XDWP#
SP6_MSD5_XDALE
XD_CD#
SP1_SDD7_XDRDY
SP2_SDD6_XDRE#
SP3_SDD5_XDCE#
SP5_MSBS_XDCLE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

JREAD1

24

XD-VCC

32

XD-D0

31

XD-D1

30

XD-D2

29

XD-D3

28

XD-D4

27

XD-D5

26

XD-D6

25

XD-D7

35

XD-WE

34

XD-WP

36

XD-ALE

41

XD-CD

40

XD-R/-B

39

XD-RE

38

XD-CE

37

XD-CLE

33

XD-GND

42

XD-GND

43

GND

44

GND

ALPS_SCDG4B0102_NR

2

CONN@

SD-VDD/MMC-VDD

MS-VCC

MMC-CLK/SD-CLK

MMC-DAT/SD-DAT0

SD-DAT1

SD-DAT2
MMC-RSV/SD-DAT3
SD-CMD/MMC-CMD

SD-CD

SD-WP

SD-CD

MS-SCLK

MS-SDIO/DATA0

MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS
MS-VSS
MS-VSS

SD-VSS/MMC-VSS1
SD-VSS/MMC-VSS2
SD-VSS/MMC-VSS2

+ODR_PWR

12
19

SD_CLK_R

10

SD_D0_R

4

SD_D1_R

3

SD_D2_R

22

SD_D3_R

20

SD_CMD_R

17

SD_CD#

1

SP15_SDWP_XDD7

2
5

SP14_MSCLK_XDD6_R

18

SP9_MSD0_XDD1

11

SP7_MSD1_XDWP#

9

SP10_MSD2_XDD2

13

SP12_MSD3_XDD4

16

MS_INS#

15

SP5_MSBS_XDCLE

8
6
21

14
23
7

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Card Reader RTS5209

LA-6801P

1

23 60Monday, December 06, 2010

0.3

5

D D

C7

BEEP#<31>

HDA_SPKR<13>

+3VS

close to U2, 7/26

C C

4.7K_0402_1%~D

B B

12

R1792

HDA_RST_AUDIO#

C46

1

0.1U_0402_16V7K~D

2

1 2

R13 0_0805_5%~D

1 2

R15 0_0805_5%~D

1 2

R17 0_0805_5%~D

5/6 ADD

5/30 change +1.5vs to +3vs

1 2

1U_0402_6.3V6K~D

C1870

1 2

1U_0402_6.3V6K~D

R4

1 2

560_0402_5%

R5

1 2

560_0402_5%

10K_0402_5%~D

1 2

R14 0_0805_5%~D

1 2

R16 0_0805_5%~D

1 2

R18 0_0805_5%~D

2

B

12

R6

DMIC_CLK<21>

DMIC0<21>

4

+VDDA

12

R1
10K_0402_5%~D

1 2

12

C1 1U_0402_6.3V6K~D
R2
10K_0402_5%~D

1

C

Q1

E

2SC2411K_SOT23

3

D1
CH751H-40PT_SOD323-2

2 1

MIC1_PLUG#<25>
LINE2_PLUG#<25>
MIC2_PLUG#<25>

1 2

1 2

R110 0_0 402_5%~D

C6

1 2

1U_0402_6.3V6K~D

1 2

R3 1.3K_0402_1%

+VDDA

MONO_IN

1 2

FBMA-L11-160808-800LMT_0603

Close to codec

MIC1_L<25>

MIC1_R<25>

Place close to Codec

L102 FBMA -10-100505-301T 0402

MIC1_L

MIC1_R

HDA_RST_AUDIO#<13>

HDA_SYNC_AUDIO<13>

HDA_SDOUT_AUDIO<13>

R9 20 K_0402_1%~D

1 2

R10 39 .2K_0402_1%

R11 20K_0402_1%~D

1 2

Reserve for EMI

C120 15P _0402_50V8J~D@

C119 15P _0402_50V8J~D@

1

1

2

2

+5VS

L4

C9

10U_0805_10V4Z~D

1 2

C16 4.7U_0603_6.3V6M

1 2

C17 4.7U_0603_6.3V6M

12

EC_EAPD#<31>

3

L1

1 2

FBMA-L11-201209-221LMA30T_0805

L2

1 2

FBMA-L11-201209-221LMA30T_0805

HD Audio Codec

+AVDD_HDA

1

2

40mil

1

C10

0.1U_0402_16V7K~D

2

12

C132.2U_0603_6.3V6K~D

12

C142.2U_0603_6.3V6K~D

U2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

29

CBP

30

CBN

31

CPVEE

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

45

SPDIFO2

13

SENSE A

36

SENSE B

47

EAPD

48

SPDIFO1

44

DMIC-CLK3/4

46

DMIC_CLK1/2

3

GPIO1/DMIC-3/4

2

GPIO0/DMIC-1/2

4

DVSS

7

DVSS

+5VAMP

1

C2

10U_0805_10V4Z~D

2

38

AVDD125AVDD2

LINE2-OUT-R

LINE2-OUT-L

MIC2-VREFO

LINE2-VREFO

LINE1-VREFO

MIC1-VREFO

ALC665-GR_LQFP48_7X7

1

C3

0.1U_0402_16V7K~D

2

9

1

DVDD

DVDD_IO

SURR_L

SURR_R

MIC2-OUT-L

MIC2-OUT-R

NC

BITCLK

SDATA_IN

LINE1-L

LINE1-R

VREF

JDREF

MONO-OUT

AVSS1
AVSS2

60mil

20mil

1

C47

0.1U_0402_16V7K~D

2

20mil

1

C11

0.1U_0402_16V7K~D

2

AMP_LEFT

39

AMP_RIGHT

41

35

33

32

34

For EMI

43

6

HDA_SDIN0_AUDIOMONO_IN

8

23

24

19

20

18

10mil

28

27

40

37

26
42

U1

1

IN

2

GND

3

SHDN

G9191-475T1U_SOT23-5

L14

+1.5VS_DVDD

1 2

FBMA-L11-160808-800LMT_0603

1

C48

R2003
0_0402_5%~D

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

R7 0_0402_5%~D

CODEC_VREF

L5

1 2

+3VS_DVDD

1 2

FBMA-L11-160808-800LMT_0603

1

C12

2

1 2

1 2

R8 33_0402_5%

MIC1_VREFO

12

R12
20K_0402_1%~D

2

5

OUT

4

BYP

0.01U_0402_16V7K~D

@

+1.5VS

+3VS

AMP_LEFT <25>

AMP_RIGHT <25>

MIC2-OUT_L <25>

MIC2-OUT_R <25>

LINE2-OUT_R <25>

LINE2-OUT_L <25>

1 2

10mil

1

C20

0.1U_0402_16V7K~D

2

Close to codec

MONO_OUT <25>

(output = 300 mA)

40mil

1

1

2

C15
22P_0402_50V8J~D

HDA_BITCLK_AUDIO <13>

HDA_SDIN0 <13>

1

C19
10U_0805_10V4Z~D

2

@

2

C5

+VDDA

4.75V

C4

4.7U_0805_10V4Z~D

1

GND GNDA GND GNDA

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Codec ALC665

LA-6801P

1

24 60Monday, December 06, 2010

0.3

5

+5VAMP +5VAMP

GAIN0 GAIN1
0 0 6dB
0 1 10dB
1 0 15.6dB
1 1 21.6dB

D D

FFC=153HZ

C26

0.47U_0603_16V4Z

@

R1986

1 2

1 2

C28

0.47U_0603_16V4Z

390_0402_5%

C1929 0.033U_0603_25V7M~D

1 2

+5VAMP

12

10K_0402_5%~D

AMP_LEFT<24>

AMP_RIGHT<24>

C C

AMP_LEFT AMP_RIGHT

B B

1 2

C1928 0.015U_0402_16V7K

4.7K_0603_1%

either one option.

MONO_OUT<24>

AMP_LEFT<24>

A A

AMP_RIGHT<24>

R1990 1K_0603_1%

R1991 1K_0402_1%~D

AMP_LEFT

AMP_RIGHT AMP_RIGHT_RR

5

AMP_LEFT_C-1

AMP_RIGHT_C-1

R28

R1984

1 2

1 2

1 2

@

@

1 2

100K_0402_1%~D

@

1 2

100K_0402_1%~D

R23

100K_0402_1%

1 2

R26
100K_0402_1%

@

1 2

C29 0.1U_0402_16V7K~D

C32 0.1U_0402_16V7K~D

12

12

R29

390_0402_5%

1 2

C1926 0.015U_0402_16V7K

R1980 12K_0402_5%~D

1 2

+5VAMP

U634A

3

+

OUT

2

-

12

R1988
10K_0402_5%~D

SPK_MUTE#<31>

0_0402_5%~D

C1937

1

12

C1936

2

R1994

R1997

R2000

10K_0402_1%~D @

R2001

10K_0402_1%~D @

R24
100K_0402_1%

@

1 2

R27

100K_0402_1%

1 2

AMP_LEFT_C

1 2

AMP_RIGHT_C

1 2

4

P

1

G

1U_0603_16V6K~D

TLV2464_TSSOP14@

11

C1889

0.47U_0603_16V4Z

1 2

C1888

0.47U_0603_16V4Z

1 2

220nF_0402_16V7K

@

C1940

1 2

1U_0603_16V6K~D

+5VAMP

12

12

GAIN1GAIN0

0.1U_0603_25V7K

C1932

1 2

+3VS

W=20mil

12

R1863
47K_0402_1%

C30

@

AMP_LEFT_C AMP_RIGHT_C

1 2

R1879 3.48K_0603_1%

1 2

R1861 3.48K_0603_1%

R1993

@

1 2

100K_0402_1%~D

9

-

10

+

U634C

@

GAIN0

GAIN1

1

1

2

2

AMP_LEFT_RRAMP_LEFT_R

AMP_RIGHT_RRAMP_RIGHT_R

20K_0402_1%~D

1U_0603_16V6K~D

MONO_OUT

11

TLV2464_TSSOP14

G

8

OUT

P

4

+5VAMP

4

+5VAMP

W=40mil

C21

0.1U_0402_16V7K~D

U3

16

VDD

6

PVDD

15

PVDD

2

GAIN0

3

GAIN1

5

LIN-

17

RIN-

9

LIN+

7

RIN+

C31

0.1U_0603_25V7K

R2002

@

1 2

2

C1945

1

@

1 2

R1992 0_0603_5%

@

R1995

1 2

1K_0402_1%~D

@

4

1

1

C27

4.7U_0805_10V4Z

2

2

TPA6017A2PWPR_TSSOP20

1 2

C1930 0. 015U_0402_16V7K

@

4.7K_0603_1%

3

4

1

2

1

C1887

0.22U_0603_25V7K~D

2

1 2

1U_0603_16V6K~D

12

NC

19

SHUTDOWN

8

LOUT-

14

ROUT-

4

LOUT+

18

ROUT+

1

GND

11

GND

13

GND

20

GND

21

GND

10

BYPASS

C19310.033U_0603_25V7M~D

1 2

12

R1987

1 2

C1934 0.012U_0603_50V7K~D

1 2

C1935 0.012U_0603_50V7K~D

6

U633

IN+

VDD

VO+

IN-

SHUTDOWN

VO-

BYPASS

GND

7

9

@

1U_0603_16V6K~D

R1996

@

1K_0402_1%~D

2

C1942

@

1

+3VS

W=20mil

12

R25
47K_0402_1%

SPKL-

SPKR-

SPKL+

SPKR+

1

C41

2.2U_0603_10V7K~D

2

+5VAMP

R1985

1 2

10K_0402_5%~D

@

@

GND

TPA6211A1DGNRG4_MSOP8

C1939

1 2

+5VAMP

W=40mil

1

C1886

0.1U_0402_16V7K~D

2

5

8

+5VAMP

4

U634D

12

P

+

OUT

13

-

G

TLV2464_TSSOP14@

11

12

3

SPK_MUTE# <31>

1 2

C1927 0.015U_0402_16V7K

R1981 12K_0402_5%~D

1 2

+5VAMP

4

U634B

5

P

+

7

OUT

6

-

G

1U_0603_16V6K~D

TLV2464_TSSOP14@

11

R1989
10K_0402_5%~D

1

C1885

4.7U_0805_10V4Z

2

SUB_L+
SUB_R-

C1941

@

14

1 2

1U_0603_16V6K~D

3

2

LINE2-OUT_L<24>

LINE2-OUT_R<24>

LINE2_PLUG#<24>

MIC2-OUT_L<24>

MIC2-OUT_R<24>

MIC2_PLUG#<24>

C1933

@

1 2

MIC1_L<24>

MIC1_R<24>

MIC1_PLUG#<24>

JWFER2

1

1

2

2

MOLEX_53261-0271~D

CONN@

R1998

@

1 2

20K_0402_1%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

1 2

R30 56.2_0603_1%

1 2

R31 56.2_0603_1%

R33 75_0402_1%

1 2

R32 75_0402_1%

1 2

For ESD
I

/O status:
a. input/output mount 75 ohm
b. input only mount 1K ohm

R36 75_0402_1%

1 2

1 2

R37 75_0402_1%

2010/12/01 2011/12/01

Compal Secret Data

1 2

L6 BLM15AG121SN1D_L0402_2P

1 2

L7 BLM15AG121SN1D_L0402_2P

1

C33

@

10P_0402_50V8J

MIC2_OUT_L_1

1 2

L8 BLM15AG121SN1D_L0402_2P

MIC2_OUT_R_1 MIC2_OUT_R_R

1 2

L9 BLM15AG121SN1D_L0402_2P

1

C35

@

220P_0402_50V8J

MIC1_L_1 MIC1_L_R

1 2

L10 BLM15AG121SN1D_L0402_2P

MIC1_R_1 MIC1_R_R

1 2

L11 BLM15AG121SN1D_L0402_2P

20mil

SPKL+

R19 0_0603_5%

SPKL-

R21 0_0603_5%

SPKR+

R20 0_0603_5%
R1848 0_0603_5%

2

MIC1_VREFO MIC1_VREFO

2.2K_0402_5%

@

220P_0402_50V8J

1 2
1 2
1 2
1 2

1

C34

@

2

2

10P_0402_50V8J

1

C36

@

2

220P_0402_50V8J

12

12

R35

R34

1

1

@

C39

2

2

2

1

PJDLC05C_SOT23-3

Deciphered Date

2

1

LINE Out/Headphone Out

JHP1

LINE2_LLIN E2_OUT_L_1

LIEN2_RLINE2_OUT_R_1

2

3

D5

@

1

PJDLC05C_SOT23-3

3

1

2
5

6

SHLD1

4

SINGA_2SJ2285-112252

CONN@

LINE Out/Headphone Out

JHP2

3

1

2
5

6

SHLD1

4

SINGA_2SJ2285-112252

CONN@

2

3

1

MIC2_OUT_L_R

D6

PJDLC05C_SOT23-3

@

MIC JACK

2.2K_0402_5%

2

C40

220P_0402_50V8J

3

D7

@

1

PJDLC05C_SOT23-3

JHP3

3

1

2
5

6

SHLD1

4

SINGA_2SJ2285-112252

CONN@

Int. Speaker Conn.

SPK_L+
SPK_L­SPK_R+
SPK_R-SPKR-

C22

3

2

3

D2

D4

PJDLC05C_SOT23-3

1

For ESD

Title

Amp TPA6017/subwoofer/ Audio Jack

Size Document Number Rev

LA-6801P

Date: Sheet of

1

220P_0402_50V8J

C23

1

2

220P_0402_50V8J

C24

1

2

220P_0402_50V8J

C25

1

220P_0402_50V8J

2

2

Compal Electronics, Inc.

1

25 60Monday, December 06, 2010

JSPK

1

1

2

2

3

3

4

4

5

GND

6

GND

MOLEX_53780-0470

CONN@

0.3

A

Power share

1 1

PWRSHARE_EN#
SW_USB20_N9
SW_USB20_P9

2 2

U30

1

CEN

2

DM

3

DP

4

GND

9

GND

MAX14566EETA+_TDFN-EP8_2X2~D

TDM

TDP

VCC

CB

8
7
6
5

PWRSHARE_OE#

+5VALW

2

C261

0.1U_0402_16V7K~D

1

USB20_N9 <16>
USB20_P9 <16>

B

CB Function

auto detection charger identification active

L

DP/DM=TDP/TDM

H

12

R203
100K_0402_5%~D

PWRSHARE_OE# <31 >

PWRSHARE_EN#

12

C

+5VALW

R1941

10K_0402_1%~D

12

@

PWRSHARE_EN#

PWRSHARE_EN_EC#<31>

R2004

10K_0402_1%~D

1 2

R2007 10K_0402_5%~D

1

221

D71

1SS355TE-17_SOD323-2

SW_USB20_P9

SW_USB20_N9

D

+5VALW

1

1

C262

C263

10U_1206_16V4Z

0.1U_0402_16V7K~D

2

2

@

R262 0_0402_5%~D

1 2

L40

1

1

4

4

WCM2012F2S-900T04 _0805

R222 0_0402_5%~D

1 2

@

2.0A

U29

1

GND

2
3
4

2

3

OC1#

IN

OUT1

EN1#

OUT2

EN2#

OC2#

TPS2062ADR_SO8~D

2

3

+5V_CHGUSB

8
7
6
5

USB20_P9_CONN

USB20_N9_CONN

L40 close to JUSB1

E

USB_OC2# <16>

+5VALW

3 3

4 4

A

AZC099-04SPR7G_SOT23

6

I/O 4

5

VDD

4

I/O 3

D26

B

1

I/O 1

2

GND

3

I/O 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_P9_CONN
USB20_N9_CONN

Compal Secret Data

2010/12/01 2011/12/01

C

USB CONN

+5V_CHGUSB

Deciphered Date

JUSB1

1

GND

2

USB_P

3

USB_N

4

VCC

5

GND

6

GND

7

GND

8

GND

SUYIN_020173MR004S52KZL

CONN@

D

close to JUSB1

+5V_CHGUSB

2.0A

1

+

2

150U_B2_6.3VM_R35M

1

C303

Size Docum ent Number Rev

Date: Sheet of

Title

C265

2

0.1U_0402_16V7K~D

Compal Electronics, Inc.

USB conn.

LA-6801P

E

0.3

26 60Monday, December 06, 2010

5

4

3

2

1

+1.5V_3.0+5VALW

10U_0603_6.3V6M~D

1U_0603_10V6K~D

CI41

1

1

2

D D

C C

B B

USB3_SMI#<16>

+3V

A A

10K_0402_1%~D

RI46

1 2

SPI_CLK_USB
USB_SO_SPI_SI

.1U_0402_16V7K~D

CI75

1

2

UI8

8

VCC

7

NC

6

SCLK

5

SI

MX25L5121EMC-20G_SO8

1

CS#

2

SO

3

WP#

4

GND

2

Vout=0.8(1+10K/32.4K)

1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05 ~ 1.1025

CLK_PCIE_USB30<14>
CLK_PCIE_USB30#<14>

PCIE_PRX_USB3TX_P6<14>
PCIE_PRX_USB3TX_N6<14>

PCIE_PTX_USB3RX_P6<14>
PCIE_PTX_USB3RX_N6<14>

RI38 10K_0402_1%~D

+3V

1 2

1

DI3

1SS355TE-17_SOD323-2

USB30_CLKREQ#<14>

+3V

2

G

@

1 3

D

S

QI3

SSM3K7002FU_SC70-3

1 2

RI59 0_0402_5%~D

+3V

10K_0402_1%~D

47K_0402_5%

RI44

RI45

1 2

1 2

SPI_CS_USB#

USB_SI_SPI_SO

+1.5V to +1.05V Transfer

+5VALW

+1.5V_3.0

CI42

+5VALW

RI23 5.1K_0402_1%

6
5
9

SYSON

8

12

7

APL5930KAI-TRG_SO8

UI6

+3VALW to +3V Transfer

+3V_3.0 +3V

3

SYSON<31,33,53>

@

221

+3V

1 2

@

1 3

RI58
10K_0402_5%~D

USB3_SMI#_R

12P_0402_50V8J~D

CI39

4

2

CLK_PCIE_USB30
CLK_PCIE_USB30#

CI67 .1U_0402_16V7K~D
CI68 .1U_0402_16V7K~D

PCIE_PTX_USB3RX_P6
PCIE_PTX_USB3RX_N6

PLT_RST#<6,16,22,23,31,32>

USB_PCIE_WAKE#<31>

USB3_SMI#_R

1 2

CI71

1U_0603_10V6K~D

+3V

2

G

1 3

D

S

QI1

SSM3K7002FU_SC70-3~D

+3V

+3V

@

2

G

1 2

D

S

QI2

SSM3K7002FU_SC70-3

YI1

1 2

24MHZ_12PF_X5H024000DC1H

1

2

VCNTL
VIN

VOUT

VIN

VOUT

EN
POK

GND

1

UI7

VIN

VOUT

VIN/CE

VOUT

GND

RT9701-PB_SOT23-5

1 2
1 2

+3V

+3V

+3V

RI40

10K_0402_1%~D

1 2

CLKREQ_USB3

RI57
10K_0402_5%~D

PCIE_WAKE#_USB3USB_PCIE_WAKE#

USB3_XT2_R

FB

RI30 0_0402_5%~D

1A

3
4

RI24

2

1 2

10K_0402_1%~D

12

RI26

32.4K_0402_1%~D

1
5

0.2A

PCIE_PRX_USB3TX_C_P6
PCIE_PRX_USB3TX_C_N6

RI29 0_0402_5%~D

1 2

1 2

USB3_XT1
USB3_XT2

12

RI20

100_0402_5%

12P_0402_50V8J~D

1

2

PCIE_WAKE#_USB3

RI33 10K_0402_1%~D

RI35 10K_0402_1%~D
RI36 0_0402_5%~D@
RI37 0_0402_5%~D

SPI_CLK_USB
SPI_CS_USB#
USB_SO_SPI_SI
USB_SI_SPI_SO

CI40

CLKREQ_USB3

1 2

RI34 100_0402_1%~D@

1 2
1 2
1 2
1 2

1 2

RI39 0_0402_5%~D

+3V

0_0402_5%~D

12

RI43

@

0_0402_5%~D

RI48

1 2

Place as close as
possibile to
UI5.N14 and UI5.M14

+1.05V

1

2

USB3_XT1
USB3_XT2

1 2

+1.5V

RI21 0_0603_5%~D

1 2

+1.5VS

10U_0603_6.3V6M~D

CI64

RI22 0_0603_5%~D@

+3VALW

UI5

B2
B1

D2
D1

F2
F1

H2
K1
K2

J2

J1
H1
P4

P5

M2
N2
N1
M1

K13
K14

J13

C14

N14
M14

P6

A1
A2
A3
A4
A5
A7
A9

A11
A13
A14

B3
B4
B5
B7
B9

B11
B13
B14

C1
C2
C3

C10
C11

1 2

RI25 0_0603_5%~D

1 2

+3VS

RI27 0_0603_5%~D@

GND

GND

D14

+1.05V

L10

GNDE1GNDE2GND

L13

VDD33

GND

E13

E14

0_0805_5%

1 2

L14

VDD33

8/11 update

GNDF4GNDF6GNDF7GNDF8GNDF9GND

+3V

D10

F13

F14

VDD33

VDD33

VDD33

VDD33F3VDD33G3VDD33G4VDD33L9VDD33

PECLKP

SPEC Max:+3V---200mA;+1.05V---800mA

PECLKN

Idle mode:0.489W:

PETXP
PETXN

+3V---43mA;+1.05V---328mA
D3 mode:0.066W:

PERXP
PERXN

+3V---5.4mA;+1.05V---45mA

PERSTB
PEWAKEB
PECREQB

AUXDET
PSEL

PCI Express/ExpressCard select signal

SMI

1

:others

SMIB

0:Express Card or Mini card

PONRSTB

SPISCK
SPISCB
SPISI
SPISO

GND
GND
GND

GND

XT1
XT2

P/N: SA000048H0L (S IC UPD720200AF1-DAP-A FBGA 176P USB3.0)
A version

CSEL

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GNDD3GNDD4GND

GND

C12

C13

D11

D12

D13

UPD720200AF1DAPA_FBGA176P-NH~D

Close to UI5.D7 Close to UI5.P13

+1.5V_3.0

+3V_3.0

RI28

VDD33N4VDD33N5VDD33N6VDD33P3VDD10C4VDD10C5VDD10C6VDD10C7VDD10D5VDD10C8VDD10C9VDD10D8VDD10D9VDD10E3VDD10E4VDD10

+3VA +3VA

0.01U_0402_16V7K~D

.1U_0402_16V7K~D

CI43

1

1

2

2

+1.05VR

Can be attach to EC, either.

As short as possible

GNDG1GNDG2GNDG6GNDG7GNDG8GND

GND

GNDH6GND

GND

GND

F11

F12

GNDH7GNDH8GNDH9GND

G9

G13

G11

G12

CI44

1

2

H12

8P_0402_50V8D~D

@

1

CI45

2

E11

E12

VDD10

VDD10H3VDD10H4VDD10L5VDD10

GNDJ3GNDJ4GNDJ6GNDJ7GNDJ8GNDJ9GND

.1U_0402_16V7K~D

J11

CI46

GND

J12

0.01U_0402_16V7K~D

CI47

1

2

H11

K11

K12

L8

VDD10

VDD10

GNDK3GNDK4GNDL1GNDL2GNDL3GND

8P_0402_50V8D~D

@

1

CI48

2

+3VA +3V

D7

P13

VDD10

U2AVDD10

U3AVDO33

U3TXDP2

U3TXDN2

U2DM2

U2DP2

U3RXDP2

U3RXDN2

OCI2B
OCI1B

PPON2
PPON1

U3TXDP1

U3TXDN1

U2DM1

U2DP1

U3RXDP1

U3RXDN1

RREF

U2AVSS

U2PVSS

U3AVSS

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

L4

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

CI49

CI50

1

1

2

2

LI1

BLM18AG601SN1D_2P

1 2

.1U_0402_16V7K~D

U3TX_C_DP2

B6

U3TX_C_DN2

A6

U2DN2_L

N8

U2DP2_L

.1U_0402_16V7K~D

P8

U3RXDP2_L

B8

U3RXDN2_L

A8

OCI2B

RI31 10K_0402_5%~D

G14

OCI1B

RI32 10K_0402_5%~D

H13

H14
J14

.1U_0402_16V7K~D

B10

U3TX_C_DN1

A10

U2DN1_L

N10

U2DP1_L

.1U_0402_16V7K~D

P10

U3RXDP1_L

B12

U3RXDN1_L

A12

RI41

1 2

P12
N12

N11

D6

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

0.01U_0402_16V7K~D

CI51

1

1

2

2

CI66

1 2

1 2

CI69

1 2
1 2

CI70

1 2

1 2

CI72

1.6K_0402_1%~D

+USB3_VCCA

U3TXDP2

U3TXDN2
U2DP2

U2DN2
U3RXDP2

U3RXDN2

+USB3_VCCB

U3TXDP1

U3TXDN1
U2DP1

U2DN1

U3RXDP1

U3RXDN1

0.01U_0402_16V7K~D

CI52

+3VA

10U_0603_6.3V6M~D

1

2

U3TXDP2_L

U3TXDN2_L

U3TXDP1_LU3TX_C_DP1

U3TXDN1_L

1

2

+1.05VR+3V

CI54

For EMI request

3 4

DLW21SN670HQ2L_4P

3 4

DLW21SN670HQ2L_4P

3

2

For ESD request

DI1

1

R-

2

R+

3

T-

4

T+

LXES4XBAA6-027_MSOP8

CI73

.1U_0402_16V7K~D

1 2

CI74

.1U_0402_16V7K~D

1 2

CONN@

GND
GND
GND

CONN@

GND
GND
GND

0.01U_0402_16V7K~D

1

2

LI2

LI4

LI6

3

2

WCM-2012-670T_4P

USB_PWR_EN#

10
11
12
13

10
11
12
13

.1U_0402_16V7K~D

0.01U_0402_16V7K~D

CI55

CI56

1

1

2

2

12

U3RXDP2U3RXDP2_L

12

4

4

1

1

+USB3_VCCA

8

VCC

7

GND

6

D-

5

D+

+5VALW +USB3_VCCA

+5VALW

RI49 0_0603_5%~D

RI50 0_0603_5%~D

USBGND1

CI77 .1U_0402_16V7K~D

RI51 0_0603_5%~D

RI52 0_0603_5%~D

USBGND2

CI78 .1U_0402_16V7K~D

.1U_0402_16V7K~D

0.01U_0402_16V7K~D

CI53

1

2

U3TXDP2_L U3TXDP2

CI65

U3TXDN2_L U3TXDN2 U3TXDP1_L U3TXDP1

U3RXDN2_L U3RXDN2

U2DP2_L

+3V

U2DN2_L

U3RXDN2
U3RXDP2
U3TXDN2
U3TXDP2

USB_PWR_EN#<31>

JUSB3

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND
D-2GND

6

SSRX+

4

GND

5

SSRX-

SUYIN_020053GR009M2106L

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND
D-2GND

6

SSRX+

4

GND

5

SSRX-

SUYIN_020053GR009M2106L

.1U_0402_16V7K~D

.1U_0402_16V7K~D

CI57

CI58

1

1

2

2

U3TXDN1_L

U3RXDP1_L U3RXDP1

U2DP2

U2DP1_L

U2DN2

U2DN1_L

U3RXDN1
U3RXDP1

U2DN2

U3TXDN1

U2DP2

2.0A

UI3

1

GND

OC1#

2

IN

OUT1

3

OUT2

EN1#

4

OC2#

EN2#

TPS2062ADR_SO8~D

2.0A

UI4

1

GND

OC1#

2

IN

OUT1

3

OUT2

EN1#

4

OC2#

EN2#

TPS2062ADR_SO8~D

For ESD request

1 2

1 2

1 2

For ESD request

1 2

1 2

1 2

0.01U_0402_16V7K~D

CI59

CI60

1

2

For EMI request

3 4

3 4

3

2

For ESD request

DI2

1
2
3
4

LXES4XBAA6-027_MSOP8

8
7
6
5

+USB3_VCCB

8
7
6
5

0.01U_0402_16V7K~D

1

2

LI3

DLW21SN670HQ2L_4P

LI5

DLW21SN670HQ2L_4P

LI7

3

2

WCM-2012-670T_4P

R­R+
T­T+

0.01U_0402_16V7K~D

CI61

CI62

1

2

VCC
GND

D­D+

W=60mils

RI42

10K_0402_5%~D

1 2

W=60mils

RI47

10K_0402_5%~D

1 2

+USB3_VCCA

150U_B2_6.3VM_R35M

1

+

2

+USB3_VCCB

150U_B2_6.3VM_R35M

1

+

2

1

2

4

1

8
7
6
5

CI28

CI30

0.01U_0402_16V7K~D

CI63

U3TXDN1

12

U3RXDN1U3RXDN1_L

12

U2DP1

4

U2DN1

1

+USB3_VCCB

U2DN1
U2DP1U3TXDP1

OCI2B

OCI1B

10U_0603_6.3V6M~D

CI29

1

2

10U_0603_6.3V6M~D

CI31

1

2

Pin compare table for support USB remote wakeup or no

CSEL(Pin P6)

Tied to GND

pull high
to VDD33

5

Support USB
remote wakeup

Not support USB
remote wakeup

AUXDET(Pin J2)

pull high
10k to VDD33

Tied to GND

t

CLK

Must use 24MHz crystal: mount
Y1,R19,C40,C41

Can use either 48MHz or 24MHz When
use 48MHz clock: mount R22,R25

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

USB conn.

Size Document Number Rev

LA-6801P

Date: Sheet of

1

27 60Monday, December 06, 2010

0.3

A

SATA_PTX_DRX_P1_C<1 3>
SATA_PTX_DRX_N1_C<13>

SATA_PRX_DTX_N1<13 >
SATA_PRX_DTX_P1<13 >

1 1

RS13 0_ 0402_5%~D@
RS14 0_ 0402_5%~D@

RS15 0_ 0402_5%~D@
RS16 0_ 0402_5%~D@

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

Free Fall Sensor

FFS_INT1 connect to PCH GPIO & EC
discuss with BIOS to use whic h pin

2 2

B

SATA_PTX_DRX_P1_B

12

SATA_PTX_DRX_N1_B

12

SATA_PRX_DTX_N1_B

12

SATA_PRX_DTX_P1_B

12

RS18 0_0 402_5%~D

1 2

RS20 5.1K _0402_1% ~D

1 2

RS23 2.7K _0402_5% ~D

1 2

CS33 0.01 U_0402_16V7K ~D

1 2

CS35 0.01 U_0402_16V7K ~D

1 2

+3VS

0.1U_0402_16V7K~D

C189

C190

1

1

2

2

FFS_INT1<16>
FFS_INT2<17>

PCH_SMBDATA<6,11,12,14 ,32>

PCH_SMBCLK<6,11,12,14,32>

SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C

SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C

10U_0805_10V4Z~D

FFS_INT1
FFS_INT2

RS33 0_ 0402_5%~D@
RS31 0_ 0402_5%~D@

RS30 0_ 0402_5%~D@
RS32 0_ 0402_5%~D@

C

SATA_PTX_DRX_P1_RC1 +5VS_HDD2

12

SATA_PTX_DRX_N1_RC1

12

SATA_PRX_DTX_N1_RC

12

SATA_PRX_DTX_P1_RC

12

US2

6

10

DNC

VDD3P3

16

20

DNC

VDD3P3

3

13

A_EN#

B_EN#

A2_EQ

17

A_EQ

A2_EM

18

A_EM

A2_OS B2_OS

19

A_OS

1

AI+

2

AI-

4

BO-

5

BO+

21

EP

PI3EQX6701Z DEX_TQFN20_4X4~D

U19

DE351DLTR

1

VDD_IO

6

VDD

8

INT 1
INT 29GND

12

SDO

13

SDA / SDI / SDO

14

SCL / SPC

7

CS

DE351DLTR_LGA14 _3X5

B2_EQ

7

B_EQ

B2_EM

8

B_EM

9

B_OS

SATA_PTX_DRX_P1_RC

15

AO+

SATA_PTX_DRX_N1_RC

14

AO-

SATA_PRX_DTX_N1_RC

12

BI-

SATA_PRX_DTX_P1_RC

11

BI+

2

GND

4

GND

5

GND

10

+3VS

3

RSVD

11

RSVD

+3VS

1

@

2

CS27

0.1U_0402_1 6V7K~D

D

RS19 0_0 402_5%~D

12

RS21 5.1K _0402_1% ~D

12

RS24 2.7K _0402_5% ~D

12

CS30 0.01U_0402_16V7K~D

1 2

CS32 0.01U_0402_16V7K~D

1 2

SATA_PTX_DRX_P1_RC1
SATA_PTX_DRX_N1_RC1

E

+3VS

1

CS19

0.1U_0402_1 6V7K~D

2

JHDD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

21

17

GND1

22

18

GND2

23

19

GND3

24

20

GND4

FOX_GS12201 -1011-9F

CONN@

JHDD1

GND2
GND1

20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

HRS_FH28E-20S-0. 5SH(11)

CONN@

0.1U_0402_1 6V7K~D

1

CS20

2

1000P_040 2_50V7K~D

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

FFS_INT2_CONN

18
19
20

22
21

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

F

1

CS21

2

1U_0402_6.3 V6K~D

SATA_PTX_DRX_P1_RC1
SATA_PTX_DRX_N1_RC1

SATA_PRX_DTX_N1_RC1
SATA_PRX_DTX_P1_RC1

+3VS_VCC3.3

HDD_DETECT#

+5VS_HDD2

SATA_PTX_DRX_P1_RC1
SATA_PTX_DRX_N1_RC1

SATA_PRX_DTX_N1_RC1
SATA_PRX_DTX_P1_RC1

+3VS_VCC3.3

HDD_DETECT#

+5VS_HDD2

FFS_INT2_CONN

SATA_PRX_DTX_N1_RC

12

SATA_PRX_DTX_P1_RC

12

G

1

CS22

2

RS22

0.022_080 5_1%

10U_0805_10 V4Z~D

1

CS23

2

RS17

12

0.022_080 5_1%

12

0.01U_0402_ 16V7K~D

CS26

CS28

0.01U_0402_ 16V7K~D

+3VS

HDD_DETECT# <17>

+5VS

* The notice for Layout(12/06) :

JHDD1 has to co-lay with JHD D
Because of the JHDD1's footp rint
is larger than JHDD,
ME need to relocated HDD
connector base on JHDD1

* Layout

注注注注注注注注注注注注注注注注

(12/06):

新新新新新新新新

JHDD1

必必必必必必必必必必必必

JHDD1

JHDD co-lay

的的的的

footprint

但但但但但但但但但但但但但但但但

JHDD

來來來來來來來來來來來來, 所所所所所所所所所所所所所所所所ME所所所所

的的的的

size

重重重重新新新新重重重重重重重重重重重重重重重重

比比比比

JHDD1

H

21

D24

SDM10U45-7_SOD5 23-2~D

US3

7

VCC6EN

18

VCC10CAD
VCC

1

AINP

VCC

2

AINM

4

BOUTM

5

BOUTP

AOUTP

3

AOUTM

GND

13

GND

17

BINP

GND

19

GND

BINM

21

EP

MAX4951BECTP+TGH7_TQFN20_ 4X4~D

@

SATA_PTX_DRX_P2_RP
SATA_PTX_DRX_N2_RP

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2

RS34

1 2

0_1206_5% ~D

+5VS

12

R159

@

100K_0402 _5%~D

+3VS

@

HDD_DEW2

HDD_DEW1

16
20

HDD_PE1

9

PA

HDD_PE2

8

PB

SATA_PTX_DRX_P2_P

15

SATA_PTX_DRX_N2_P

14

SATA_PRX_DTX_P2_P

11

SATA_PRX_DTX_N2_P

12

RS35 0_ 0402_5%~D

12

RS37 0_ 0402_5%~D

12

RS39 0_ 0402_5%~D

12

RS41 0_ 0402_5%~D

12

1U_0402_6.3 V6K~D

B+_BIAS

2

ODD_EN#<17>

C

1

2

G

0.01U_0402_16V7K~D

@

CS47

1 2

13

D

S

0.1U_0402_16V7K~D

1

CS48

2

SATA_PTX_DRX_P2_B
SATA_PTX_DRX_N2_B

SATA_PRX_DTX_N2_B
SATA_PRX_DTX_P2_B

+5VS

1

CS41

2

RS26
470K_0402 _5%~D

QS2
SSM3K7002FU_S C70-3

ODD_EN

0_0402_5%~D

12

RS43

@

@

10K_0402_5%~D

12

@

RS47

6

2
1

+3VS

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

12

@

@

RS46

RS45

RS44

1 2

1 2

10K_0402_5%~D

0_0402_5%~D

0_0402_5%~D

12

12

12

@

@

@

RS49

RS50

RS48

RS36 0_0 402_5%~D

12

RS38 0_0 402_5%~D

12

RS40 0_0 402_5%~D

12

RS42 0_0 402_5%~D

12

QS1

D

S

+5VS_ODD_R

45

SI3456BDV-T1-E3 1N TSOP6

G

3

RS27

1

CS46

2

1 2

1.5M_0402_5%~D

D

MAXIM TI

main 2nd

P/N

RS43 RS44

SA00003LH1L SA00003ZX0L

pop depop

RS47 RS48 popdepop

RS53 RS54 pop depop

SATA_PTX_DRX_P2_C
SATA_PTX_DRX_N2_C

SATA_PRX_DTX_N2_P
SATA_PRX_DTX_P2_P

+5VS_ODD

RS25

@

1 2

0_1206_5% ~D

Security Classification

Issued Date

0.1U_0402_25V6

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIE TARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMP AL ELECTRONICS, INC.

2010/12/01 2011/12/01

E

SATA_PTX_DRX_P2_P
SATA_PTX_DRX_N2_P

SATA_PRX_DTX_N2_P
SATA_PRX_DTX_P2_P

ODD_DETECT#<17>

ODD_DA#<16>

Compal Secret Data

Deciphered Date

CS51 0.01U_0402_16V7K~D
CS52 0.01U_0402_16V7K~D@

CS44 0.01U_0402_16V7K~D
CS45 0.01U_0402_16V7K~D

RS28 0_0 402_5%~D

RS29

F

@

1 2
1 2

1 2

1 2

+5VS_ODD

Placea caps. near ODD CONN.

+5VS_ODD

1000P_040 2_50V7K~D

1

CS37

2

0.1U_0402_1 6V7K~D

1

2

CS38

1

CS39

2

1U_0402_6.3 V6K~D

10U_0805_10 V4Z~D

1

CS40

2

SATA ODD Conn.

JODD1

28

SATA_PTX_DRX_P2_C

12

SATA_PTX_DRX_N2_C

12

SATA_PRX_DTX_N2_C
SATA_PRX_DTX_P2_C

ODD_DETECT#_R

+5VS_ODD

ODD_DA#_R

0_0402_5% ~D

Title

FFS /HDD/ ODD Connector

Size Document Number Rev

LA-6801P

Date: Sheet of

G

272728

26

252526

24

232324

22

212122

20

191920

18

171718

16

151516

14

131314

12

111112

9

10

9

10

7

8

7

8

5

6

5

6

3

4

3

4

1

2

1

2

E-T_6900-Q14N-00 R

CONN@

Compal Electronics, Inc.

28 60Monday, December 06 , 2010

H

+3VS

G

2

FFS_INT2 FFS_INT2_CO NN

13

D

S

Q23

SSM3K7002FU_S C70-3~D

3 3

SATA_PTX_DRX_P2_RP<13>
SATA_PTX_DRX_N2_RP<13 >

A

CS49 0.01 U_0402_16V7K ~D@
CS50 0.01 U_0402_16V7K ~D@

SW4

SMT1-05-A_4P

214

5

6

@

Reserve for te st
Zero Power ODD

SATA_PRX_DTX_N2<13 >
SATA_PRX_DTX_P2<13 >

4 4

SATA_PTX_DRX_P2_RP
SATA_PTX_DRX_N2_RP

10K_0402_5%~D

@

RS51

0_0402_5%~D

RS53

ODD_DA#_R

SATA_PRX_DTX_N2_RP
SATA_PRX_DTX_P2_RP

+3VS

HDD_EQ1

HDD_EQ2

10K_0402_5%~D

12

@

RS52

0_0402_5%~D

12

RS54

@

B

+5VS +5 VS_ODD

12
12

12

12

@

3

0.3

A

B

C

D

E

ON/OFF switch

TOP Side

1 1

2 2

Test Only

3 3

4 4

SW6

SMT1-05-A _4P

1

2

@

5

6

Bottom Side

SW5

SMT1-05-A _4P

1

2

5

6

@

FD1

@

1

FIDUCIAL_C40 M80

H63

H_2P0N

@

1

H39

H_3P3

@

1

H32

H_3P8

@

1

H46

H_3P0

H_3P0

@

1

3

4

3

4

H40

H_3P3

H33

H_3P8

H42

H_2P7

H48

1

H_3P9x1P9 N

1

1

1

@

FD2

1

FIDUCIAL_C40 M80

H64

@

1

H58

H_3P3

@

@

1

H34

H_3P8

@

@

1

H43

H_2P7

@

@

1

H49

H_3P0

H_3P0

@

1

A

Power Button

ON/OFFBT N#

1

C326

0.1U_040 2_25V6

2

ON/OFFBT N# <35>

EC_ON<31,52>

@

FIDUCIAL_C40 M80

H59

H60

H_3P3

H_3P3

@

@

1

1

H35

H36

H_3P8

H_3P8

@

@

1

1

H45

H_2P7

@

1

H51

H_2P7

@

1

H50

H44

H_3P0

H_3P0

@

@

1

1

FD3

H61

H_3P3

H37

H_3P8

H41

1

2

EC_ON

10K_040 2_5%~D

@

1

@

1

H38

H_3P8

@

1

H47

H_2P7

@

3

D28

PSOT24C _SOT23

1

R264

FIDUCIAL_C40 M80

@

1

@

1

1

DAN202U T106_SC70-3

1 2

FD4

@

1

D27

ZZZ1

PCB-MB

2

3

2

G

B

+3VALW

R263

100K_04 02_5%~D

1 2

13

D

Q24

SSM3K70 02F_SC59-3

S

CLIP1
EMI_CLIP @

CLIP2
EMI_CLIP @

CLIP3
EMI_CLIP @

ON/OFF <31>

GND

GND

GND

C1918 10 0P_0402_50V8 J~D

1 2

KSO15

KSO14

KSO13

KSO12

51ON# <5 0>

KSI[0..7]

KSO[0..16]

1

1

1

KSI[0..7] <31>

KSO[0..16] <31>

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/ 01 2011/12/ 01

C

KSI0

KSO11

KSO10

KSI1

KSI2

KSO9

KSI3

KSO8

KB_DET#<14 >

Compal Secret Data

C306 100P_0 402_50V8J~D

1 2

C304 100P_0 402_50V8J~D

1 2

C312 100P_0 402_50V8J~D

1 2

C308 100P_0 402_50V8J~D

1 2

C328 100P_0 402_50V8J~D

1 2

C327 100P_0 402_50V8J~D

1 2

C314 100P_0 402_50V8J~D

1 2

C316 100P_0 402_50V8J~D

1 2

C318 100P_0 402_50V8J~D

1 2

C320 100P_0 402_50V8J~D

1 2

C322 100P_0 402_50V8J~D

1 2

C324 100P_0 402_50V8J~D

1 2

KB detect pin

KB_DET#

Deciphered Date

INT_KBD Conn.

KSO10
KSO11
KSO9
KSO14
KSO13
KSO15
KSO16
KSO12
KSO0
KSO2
KSO1
KSO3
KSO8
KSO6
KSO7
KSO4
KSO5
KSI0
KSI3
KSI1
KSI5
KSI2
KSI4
KSI6
KSI7

D

KB_DET#KSO16

KSO7

KSO6

KSO5

KSO4

KSO3

KSI4

KSO2

KSO1

KSO0

KSI5

KSI6

KSI7

C434 100P_0 402_50V8J~D

1 2

C310 100P_0 402_50V8J~D

1 2

C305 100P_0 402_50V8J~D

1 2

C307 100P_0 402_50V8J~D

1 2

C309 100P_0 402_50V8J~D

1 2

C311 100P_0 402_50V8J~D

1 2

C313 100P_0 402_50V8J~D

1 2

C315 100P_0 402_50V8J~D

1 2

C317 100P_0 402_50V8J~D

1 2

C319 100P_0 402_50V8J~D

1 2

C321 100P_0 402_50V8J~D

1 2

C323 100P_0 402_50V8J~D

1 2

C325 100P_0 402_50V8J~D

1 2

CONN@

TYCO_3-2041 084-0

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

JKB

Size Doc ument Number Rev

Date: Sheet of

32

GND

31

GND

Title

Compal Electronics, Inc.

PWRBTN/SCREWH/KB

LA-6801P

0.3

29 60Monday, December 0 6, 2010

E

5

4

3

2

1

System Thermal Sensor 1

D D

C

1

C1814

@

100P_0402_50V8J~D

C C

100P_0402_50V8J~D

2

1

C1871

@

2

2

B

E

Q283

3 1

MMBT3904WT1G_SC70-3~D

C

2

B

E

Q279

3 1

MMBT3904WT1G_SC70-3~D

Diode circuit s used for skin temp sensor
(placed between CPU and VGA).
Place C1814 close to Q283 as possible.

MAINPWON<52,59>

REMOTE_P1SENSOR_DIODE_P1

1

C1815
470P_0402_50V7K

2

+3VS

REMOTE_P2SENSOR_DIODE_P2

1

C1873
470P_0402_50V7K

2

+3VS

+3VS

R1796 0_0402_5%~D

1 2

SENSOR_DIODE_N1 REMOTE_N1

Diode circuit s used for skin temp sensor
(placed around DIMM).
Place C1871 close to Q279 as possible.

SENSOR_DIODE_N2 REMOTE_N2

R1797 0_0402_5%~D

1 2

R1851 0_0402_5%~D

1 2

R1853 0_0402_5%~D

1 2

MAINPWON<52,59>

+3VS

1

2

C1816

0.1U_0402_10V7K~D

1 2

R1798 4.7K_0402_1%~D

D

S

1 3

Q303
SSM3K7002FU_SC70-3~D

G

2

+3VS

System Thermal Sensor 2

+3VS

1

2

C1872

0.1U_0402_10V7K~D

1 2

R1856 6.8K_0402_1%~D

D

S

1 3

Q304
SSM3K7002FU_SC70-3~D

G

2

U615

1

VDD

2

DP

3

DN

THERM#/ADDR4GND

EMC1412-A-ACZL-TR_MSOP8

U627

1

VDD

2

DP

3

DN

THERM#/ADDR4GND

EMC1412-A-ACZL-TR_MSOP8

SMDATA

SMDATA

SMCLK

ALERT

SMCLK

ALERT

8

7

6

5

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <3 1,45,58>

EC_SMB_DA2 <3 1,45,58>

SYSTEM_FAN_PWM<31>

SYSTEM_FAN_FB<31>

EC_SMB_CK2 <3 1,45,58>

EC_SMB_DA2 <3 1,45,58>

SYSTEM_FAN_PWM
SYSTEM_FAN_FB

+3VS

10K_0402_5%~D

R1801

R1800

1 2

1 2

10K_0402_5%~D

10K_0402_5%~D

2 1

D65
CH751H-40PT_SOD323-2~D

R1802

+5VS

+5VS_FAN

1 2

R2018
0_0805_5%~D

1 2

2.2U_0603_6.3V6K~D

12

C1923

JFAN1

1

1

2

2

3

3

G5

4

4

G6

MOLEX_53398-0471

CONN@

5
6

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

FAN Controller

LA-6801P

1

0.3

of

30 60Monday, December 06, 2010

5

4

3

2

1

+3VALW

1 2

+3VS

D D

+3VALW

R229 2.2K_0402_5%~D

+3VS

R244 2.2K_0402_5%~D

R247 2.2K_0402_5%~D

VR_HOT#<50,57>

H_PROCHOT#<6>

R230 2.2K_0402_5%~D

R231 47K_0402_5%

R232 47K_0402_5%

10/1 ENE Recommand

R238 10K_0402_5%~D

R239 1K_0402_1%~D

R241 10K_0402_5%~D

R242 4.7K_0402_5%~D

R243 4.7K_0402_5%~D

R1952 10K_0402_5%~D

R2019 10K_0402_5%~D

1 2

1 2

C C

B B

A A

1 2

R217 10K_0402_5%~D

1 2

R218 10K_0402_5%~D

1 2

R1943 10K_0402_5%~D

C284

22P_0402_50V8J~D@

12

CLK_PCI_LPC<16>

R221 47K_0402_5%

+3VALW

C285 0.1U_0402_16V7K~D

EC_SMB_CK1

1 2

EC_SMB_DA1

1 2

KSO1

1 2

KSO2

1 2

EC_MUTE

@

1 2

EC_SMI#

@

1 2

SPK_MUTE#

@

1 2

EC_ESB_CLK

1 2

EC_ESB_DAT

1 2

LID_SW_IN#

1 2

PCIE_WAKE#_R

@

1 2

EC_SMB_CK2

EC_SMB_DA2

R265
0_0402_5%~D

1 2

H_PROCHOT# H_PROCHOT#_EC

SN74LVC1G06DCKR_SC70-5

1

2

C1944
47P_0402_50V

5

Y4A

BKOFF#

EC_SCI#

M_THERMAL#

R226 33_0402_5%@

12

12

EC_SMB_CK2 <30,45,58>

EC_SMB_DA2 <30,45,58>

+3VS

1

2

5

U635

P

2

G3NC

1

R216
0_0805_5%~D

12

PCH_SMLCLK<14,51>
PCH_SMLDATA<14,51>

PM_SLP_S3#<15,34>
PM_SLP_S5#<15,34>

EC_ESB_CLK

SUSCLK_R<15>

C1943

0.1U_0402_16V7K~D

R1999
100K_0402_5%~D

1 2

C297

0.1U_0402_16V7K~D

1 2

R258 0_0402_5%~D

1 2

R259 0_0402_5%~D

1 2

R260 0_0402_5%~D

0.1U_0402_16V7K~D

PCH_DPWROK<15>

1 2
1 2

1 2
1 2

R252 0_0402_5%~D

1 2

SYSTEM_FAN_FB<30>

PCH_PWR_EN<33>

USB_PWR_EN#<27>

+3VALW

20mils

1

2

0.1U_0402_16V7K~D

1

1

C276

C277

2

2

GATEA20<17>
KB_RST#<17>

SERIRQ<13>

LPC_FRAME#<13>

LPC_AD3<13>
LPC_AD2<13>
LPC_AD1<13>
LPC_AD0<13>

PLT_RST#<6,16,22,23,27,32>

EC_SCI#<17>
EN_CAM<21>

EC_SMB_CK1<59>
EC_SMB_DA1<59>

R245 0_0402_5%~D
R246 0_0402_5%~D

R249 0_0402_5%~D
R250 0_0402_5%~D

EC_SMI#<17>

PS_ID<50>

SUSWARN#<15>

EC_INV_PWM<21>

EC_TX<32>
EC_RX<32>

ON/OFF<29>

SUSACK#<15>

R253 0_0402_5%~D

SPI ROM

SPI_FSEL#FSEL#

SPI_CLK_RSPI_CLK

0.1U_0402_16V7K~D

1

1

C278

2

2

0.1U_0402_16V7K~D

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
EN_CAM

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

PCH_DPWROK

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#_R
PM_SLP_S5#_R
EC_SMI#
PS_ID
EC_ESB_CLK_R
EC_ESB_DAT
SUSWARN#

SYSTEM_FAN_FB
PCH_PWR_EN
EC_TX
EC_RX
ON/OFF
SUSACK#
USB_PWR_EN#

1 2

R1979
100K_0402_5%~D

1 2

U36

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

D

MX25L1005AMC-12G SOP 8P

2

C279

1

1000P_0402_50V7K~D

EC_CRY1
EC_CRY2

256KB

4

2

Q

4

2

C280

C281

1000P_0402_50V7K~D

1

U34

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

SP07000F500 S SOCKET WIESON G6179-100000 8P
SPIFLASH
WIESO_G6179-100000_8P

SPI_CLK_R

Reserve for EMI please close to U36

1 2

R261 0_0402_5%~D

+3VALW_EC

LPC & MISC

Int. K/B
Matrix

EC test PSID

L43
FBMA-L11-160808-800LMT_0603

1 2

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

@

R257

12

33_0402_5%

22P_0402_50V8J~D

FRD#SPI_SOSPI_FWR#FWR#

+EC_VCCA

1

2

ECAGND

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03

EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

AGND

KB930QF A1 LQFP 128P

69

20mil

L44

ECAGND

FBMA-L11-160808-800LMT_0603

@

C296

1 2

C282

0.1U_0402_16V7K~D

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

V18R

12

3

KSI[0..7]

KSO[0..16]

BEEP#
SYSTEM_FAN_PWM
ACOFF

BATT_TEMP
PM_SLP_SUS#
ADP_I
AD_BID0

IMON

AC_SEL
IREF
CHGVADJ

EC_MUTE_R
PWRSHARE_EN_EC#
AC_PRESENT
H_PROCHOT#_EC
TP_CLK
TP_DATA

VGATE
EN_WOL#
HDA_SDO
LID_SW_IN#

R234 33_0402_5%

R_SPI_CLK

R237 33_0402_5%

PCH_VREG_EN#
EC_PECI
FSTCHG
BATT_CHG_LED#
CAPS_LED#
BATT_LOW_LED#
EN_INVPWR
SYSON
VR_ON
ACIN

PCH_RSMRST#
EC_LID_OUT#
EC_ON
3S/4S#
PCH_PWROK
BKOFF#
CPU1.5V_S3_GATE
PCH_APWROK
SA_PGOOD

PM_SLP_S4#
ENBKL
EC_EAPD#
M_THERMAL#
SUSP#
PBTN_OUT#
PCIE_WAKE#_R

+V18R

KSI[0..7] <29>

KSO[0..16] <29>

BEEP# <24>

SYSTEM_FAN_PWM <30>

ACOFF <50,51>

PM_SLP_SUS# <15>
ADP_I <50,51>

IMON <57>

AC_SEL <50>
IREF <51>

CHGVADJ <51>

R228 0_0402_5%~D

12

PWRSHARE_EN_EC# < 26>
AC_PRESENT <15>

TP_CLK <35>
TP_DATA <35>

VGATE <6,15,57>

EN_WOL# <22>
HDA_SDO <13>
LID_SW_IN# <14,34,35>

1 2

R236 33_0402_5%

1 2

1 2

PCH_VREG_EN# <19>

FSTCHG <51>
BATT_CHG_LED# <34>
CAPS_LED# <35>
BATT_LOW_LED# <34>

EN_INVPWR <21>
SYSON <27,33,53>
VR_ON < 57>

ACIN <34,51>

12

C550 100P_0402_50V8J~D

1

C293

4.7U_0805_10V4Z~D

2

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

1 2

R1944 0_0402_5%~D

1 2

R2020 0_0402_5%~D

Issued Date

PCH_RSMRST# <15>

EC_LID_OUT# <14>
EC_ON < 29,52>

3S/4S#
PCH_PWROK <6,15>
BKOFF# <21>
CPU1.5V_S3_GATE <10>

PCH_APWROK <15>

SA_PGOOD <55>

PM_SLP_S4# < 15>

ENBKL <15>

EC_EAPD# <24>

SUSP# <10,18,33,53,54>
PBTN_OUT# <6,15>

ECAGND

12

C286 100P_0402_50V8J~D

BATT_TEMP <59>

SPK_MUTE#

13

D

EC_MUTE

FRD#
FWR#
SPI_CLK
FSEL#

1 2

R240 43_0402_1%

Please place R240 close
to EC with in 750mil

PCIE_WAKE# <15,22,32>

USB_PCIE_WAKE# <27>

CP_SEL<51>

CPU_SEL<57>

EMC_ALERT#<51>

Dyn_Turbo_Sel<50>

DRAMRST_CNTRL_EC<7>

+3VALW

12

R248
47K_0402_5%

RST#

2

C292

0.1U_0402_16V7K~D

1

2010/12/01 2011/12/01

SSM3K7002F_SC59-3

2

Q21

G

S

EC_ESB_CLK

RST#

EC_ESB_DAT

Dyn_Turbo_Sel

VGA_LVDDEN<15,21>

Compal Secret Data

Deciphered Date

2

H_PECI <6,17>

SPK_MUTE# <25>

Reserve for RF please close to U34

U620

1

ESB_CLK

2

GPIO00

3

RST#

4

ESB_DAT

5

GPIO01

6

GPIO02

7

GPIO03

8

GPIO04

9

GPIO05

10

GPIO06

11

GPIO07/CAS_CLK

12

GND

KC3810_QFN24_4X4

Board ID

TP_CLK

TP_DATA

27P_0402_50V8J~D

EC_MUTE

R_SPI_CLK

EC_ESB_CLK_R

+3VALW

R219
100K_0402_5%~D

Ra

1 2

AD_BID0

1

R225

Rb

18K_0402_5%~D

1 2

Analog Board ID definition,
Pl

ease see page 4.

EC_CRY1

@

1

C287

2

@

X1

32.768KHZ_12.5PF_Q13MC14610002

1 2

R233 10K_0402_5%~D

CH100

12

@

10P_0402_50V8J~D
CH101

12

@

10P_0402_50V8J~D

TEST_EN#

GPIO08/CAS_DAT

GPIO0A

GPIO0B

GPIO0C/PWM0

GPIO0D/PWM1

GPIO0E/PWM2

GPIO0F/PWM3

GPIO10/ESB_RUN#

GPIO11/BaseAddOpt

25

Title

Size Document Number Rev

Date: Sheet of

C283

2

0.1U_0402_16V7K~D

+5VS

12

R2234.7K_0402_5%~D

12

R2244.7K_0402_5%~D

EC_CRY2

1

C288

1

27P_0402_50V8J~D

2

@

OSC4OSC

NC3NC

2

13

GPIO09

VCC

GND

14

15

16

17

18

19

20

21

22

23

24

PWRSHARE_OE#

60 mil

1

C294

2

+3VALW

0.1U_0402_16V7K~D

EC_ENVDD <21>

EN_TPLED# <35>

Compal Electronics, Inc.

EC ENE-KB930/ ENE3810

LA-6801P

1

PWRSHARE_OE# < 26>

WLES ON/OFF LED# <35>

LCD_TEST <21>

3V_F347_ON <34>

31 60Monday, December 06, 2010

0.3

A

B

C

D

E

BlueTooth

+3VS

@

CU1

0.1U_0402_16V7K~D

BT_ON#

1 1

BT_ON#<17>

1 2

RU1 10K_0402_5%~D

CU3

0.1U_0402_16V7K~D

To DMC PCB connector

2 2

PCIE_WAKE#<15,22,31>

PCIE_PRX_WLANTX_N1<14>

PCIE_PRX_WLANTX_P1<14>

PCIE_PTX_WLANRX_N1<14>
PCIE_PTX_WLANRX_P1<14>

DMC_DAT_AUXN_CONN<37>
DMC_CLK_AUXP_CONN<37>

DP_DMC_ML2N_RCC<37>
DP_DMC_ML2P_RCC<37>

DP_DMC_ML0N_RCC<37>
DP_DMC_ML0P_RCC<37>

3 3

PCIE_WAKE#
COEX2
COEX1

WL_OFF#<16>

MINI1CLK_REQ#<14>

CLK_PCIE_MINI1#<14>

CLK_PCIE_MINI1<14>

BT_RADIO_DIS#

EC_TX<31>
EC_RX<31>

DMC_DET#<37>

MINI2CLK_REQ#<14>

330U_D2E_6.3VM_R25~D

WL_OFF#

DMC_DET#

DMC_DAT_AUXN_CONN
DMC_CLK_AUXP_CONN

DP_DMC_ML2N_RCC
DP_DMC_ML2P_RCC

DP_DMC_ML0N_RCC
DP_DMC_ML0P_RCC

+3VS

1

1

+

C1946

Reserve for RF please
close to JWDB1

@

2

2

C1924
47P_0402_50V

JWDB1

82

G2

80

Reserved

78

Reserved

76

Reserved

74

Reserved

72

VPP_Test

70

SDIO_PWR#_BLT

68

SDIO_RST#_BLT

66

SDIO_CMD_BLT

64

VSS

62

SDIO_CLK_BLT

60

VSS

58

Ser_TX

56

Ser_RX

54

VSS

52

BLT_USB2_BioMetric+

50

BLT_USB2_BioMetric-

48

VSS

46

VSS

44

VDD 3.3v

42

VDD 3.3v

40

VDD 3.3v

38

VDD 3.3v

36

VSS

34

VSS

32

M_Clk

30

VSS

28

I2S_BCLK

26

I2S_DOUT

24

I2S_DIN

22

I2S_LRC

20

VSS

18

NC

16

BLT_LED_1#

14

VSS

12

NC

10

NC

8

VSS

6

LID_Cl#

4

BLT_Sus#

2

VSS

CONN@

SDIO_GPIO2_BLT
SDIO_GPIO1_BLT

BLT_USB3_HOST+

BLT_USB3_HOST-

BLT_USB1_WWAN_Data+

BLT_USB1_WWAN_Data-

BLT_USB_Port1_Dir

HRS_DF12(3.0)-80DP-0.5V86

Reserved
Reserved
Reserved
Reserved

SDIO_D3_BLT
SDIO_D2_BLT
SDIO_D1_BLT
SDIO_D0_BLT

VDD 3.3v
VDD 3.3v
VDD 3.3v
VDD 3.3v

RST_BLT#

SMBALERT_1

SMBDATA_1

SMBCLK_1

eDP_CH1_p
eDP_CH1_n

Radio_disable#

PAID_IN

81

G1

79
77
75
73
71
69
67
65
63
61
59

VSS

57
55
53

VSS

51
49
47

VSS

45

VSS

43
41
39
37
35

VSS

33

VSS

31

VSS

29
27
25
23
21
19

VSS

17

NC

15

NC

13

VSS

11
9
7

VSS

5
3
1

VSS

DMC_RADIO_OFF#

UICC_VPP

UICC_RESET

UICC_DATA

UICC_CLK

DP_DMC_HPD

DP_DMC_ML3N_RCC
DP_DMC_ML3P_RCC

DP_DMC_ML1N_RCC
DP_DMC_ML1P_RCC

1

C1925

@

47P_0402_50V

2

Reserve for RF please
close to JWDB1

PLT_RST# <6,16,22,23,27,31>

PCH_SMBCLK <6,11,12, 14,28>
PCH_SMBDATA <6, 11,12,14,28>

USB20_N4 <16>
USB20_P4 <16>

DMC_RADIO_OFF# <16>

+UICC_PWR

USB20_N5 <16>
USB20_P5 <16>
DP_DMC_HPD <37>

DP_DMC_ML3N_RCC <37>
DP_DMC_ML3P_RCC <37>

DP_DMC_ML1N_RCC <37>
DP_DMC_ML1P_RCC <37>

PCIE_PTX_WANRX_P2 <14>
PCIE_PTX_WANRX_N2 < 14>

PCIE_PRX_WANTX_P2 <14>
PCIE_PRX_WANTX_N2 < 14>

CLK_PCIE_MINI2# <14>
CLK_PCIE_MINI2 <14>

+1.5VS

+UICC_PWR +UICC_PWR+UICC_PWR

R88
10K_0402_5%~D

@

1 2

BT_DET#<14>

BT_RADIO_DIS#<17>

USB20_N8<16>
USB20_P8<16>

UICC_RESET UICC_VPP

COEX1

BT_RADIO_DIS#
COEX2PLT_RST#

33P_0402_50V8J~D

10K_0402_5%~D

12

C192

1

2

SIM card board 4.7uF change to 1uF
for Tiger dete ct issue.

1

C428

1U_0402_6.3V6K~D

2

+3VS

1

CU2

1U_0603_10V4Z

S

QU1

D

AO3419L_SOT23-3

1 3

W=40mils

1

2

0.1U_0402_16V7K~D

+3VS_BT

0.1U_0402_16V7K~D

2

12

CU5

RU2
300_0603_5%

13

D

2

G

S

C191

1 2

JBT

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

13

11

G1

12

14

12

G2

LOTES_YBA-WTB-015-K01~D

CONN@

G

2

CU4

4.7U_0805_10V4Z~D

100P_0402_50V8J~D

@

R167

C193

1

2

SIM Connector

JSIM1

CONN@

1

VCC

2

RST

3

CLK

4

NC

MOLEX_475531001~D

GND

VPP

I/O

NC
GND
GND

1

C429

@

4.7U_0603_6.3V6K~D

2

5
6
7
8
9
10

UICC_DATAUICC_CLK

1

C430

0.1U_0402_16V7K~D

2

+3VS_BT

QU2
SSM3K7002F_SC59-3

@

12

R95
10K_0402_5%~D

U41

Reserve for SIM card does not meet
rise time and pull-up is needed.

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

D

UICC_VPP

3

CH2

2

Vn

1

CH1

CM1293A-04SO_SOT23-6

For ESD

Title

Mini Card -WLAN / DMC / BT

Size Document Number Rev

LA-6801P

Date: Sheet of

UICC_DATA

6

CH3

5

Vp

UICC_RESETUICC _CLK

4

CH4

1

C431

0.1U_0402_16V7K~D

2

Compal Electronics, Inc.

E

32 60Monday, December 06, 2010

+UICC_PWR

0.3

A

+5VALW to +5VS

+5VALW

Q26
SI4800BDY-T1-E3_SO8

8

1

C335
10U_0805_10V4Z~D

2

1 1

B+_BIAS

DMN66D0LDW-7_SOT363-6~D

1 2

R270
102K_0402_1%

SUSP

1

2

C336
10U_0805_10V4Z~D

0_0402_5%~D

3

Q285B

5

4

7

5

4

R271

1

2

0.1U_0603_50V_X7R

C340

1
2
36

+5VS

10U_0805_10V4Z~D

1

C337

2

@

R273
0_0402_5%~D

1U_0603_10V4Z

1

C338

2

Q285A

R267
470_0603_5%

1 2

+5VS_D

61

DMN66D0LDW-7_SOT363-6~D

B

SUSP

2

C

D

+5VALW

R1934
100K_0402_5%~D

1 2

DGPU_PWR_EN#

R1938
100K_0402_5%~D

21

D22CH751H-40PT_SOD323-2

12

@

13

D

2

G

Q294

S

SSM3K7002F_SC59-3

SUSP#<10,18,31,53,54>

DGPU_PWR_EN<16,43,55,56>

E

+3VALW to +3V_PCH

1 2

R280
102K_0402_1%

B+_BIAS

R1945

2

G

Q34

+3VALW

1

C350
10U_0805_10V4Z~D

2

2

G

10U_0805_10V4Z~D

12

1

2

R1946

1 2

13

D

Q297

PMF3800SN_SC70-3

S

13

D

S

+1.05VS

C1919

470_0402_5%

SYSON#

JP3

112

JUMP_43X79

Q41

SI4800BDY-T1-E3_SO8

8
7

5

R277

0_0402_5%~D

Q31
SSM3K7002F_SC59-3

U632

SI4634DY-T1-E3_SO8~D

8
7
6
5

12

R1947

2M_0402_5%~D

+3V

12

R294

470_0402_5%

+3V_USB

13

D

2

G

S

@

2

1
2
36

4

0.1U_0603_50V_X7R

1

C355

2

+1.05VSDGPU

8A

1
2
3

4

1

C1922

0.1U_0402_25V6

2

Q36

SSM3K7002FU_SC70-3

+3V_PCH

40mil

1

C351
10U_0805_10V4Z~D

2

@

R282
0_0402_5%~D

C1920

0.1U_0402_16V7K~D

1

1

2

2

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

C1921

10U_0805_10V4Z~D

Issued Date

1

C352
1U_0603_10V4Z

2

DGPU_PWR_EN# DGPU_PWR_EN#

RUN_ON_CPU1.5VS3#<6,10>

2010/12/01 2011/12/01

Compal Secret Data

+1.5VSDGPU +1. 05VSDGPU

12

R1939

470_0402_5%

61

Q296A

2

2N7002DW-7-F_SOT363-6

12

R292
220_0402_5%~D

+1.5V_CPU_VDDQ_CHG

SSM3K7002FU_SC70-3~D

13

D

Q37

2

G

S

Deciphered Date

D

PCH_PWR_EN<31>

470_0402_5%

+0.75VS+1.5V_CPU_VDDQ

2

G

12

R1940

3

Q296B

5

4

2N7002DW-7-F_SOT363-6

R286

10K_0402_5%~D

1 2

12

R293
22_0603_5%~D

+DDR_CHG

SSM3K7002FU_SC70-3~D

13

D

Q38

S

Title

Size Document Number Rev

Date: Sheet of

SUSP#<10,18,31,53,54>

R291
100K_0402_5%~D

PCH_PWR_EN#<19>

@

R290
100K_0402_5%~D

SYSON<27,31,53>

R300
100K_0402_5%~D

Compal Electronics, Inc.

DC/DC Interface

LA-6801P

12

PCH_PWR_EN#

2

G

0.1U_0603_50V_X7R

12

1

@

2

SYSON#

1

12

2

E

SUSP

1

2

+5VALW+3VALW

C359

2

0.1U_0603_50V_X7R

G

@

C361

+5VALW

2

G

0.1U_0603_50V_X7R

@

C360

12

R287
100K_0402_5%~D

13

D

Q32
SSM3K7002F_SC59-3

S

+5VALW

12

R295
100K_0402_5%~D

13

D

Q35
SSM3K7002F_SC59-3

S

12

R288
100K_0402_5%~D

13

D

Q33
SSM3K7002F_SC59-3

S

33 60Monday, December 06, 2010

0.3

+3VALW to +3VS

+3VALW

Q27

SI4800BDY-T1-E3_SO8

8
7

5

C346
10U_0805_10V4Z~D

13

D

2

G

S

+1.5V To +1.5VS

+1.5V +1.5VS

R284

1 2

10K_0402_5%~D

470_0402_5%

SUSP

A

R276

0_0402_5%~D

Q30
SSM3K7002F_SC59-3

U20

SI4634DY-T1-E3_SO8~D

8
7
6
5

0.1U_0603_50V_X7R

1

2

12

R297

+VCCP_D

3

Q4B

5

4

2N7002DW-7-F_SOT363-6

4

1

2

C358

PCH_PWR_EN#

B+_BIAS

2

G

R296

Q4A

2

1 2

R279
102K_0402_1%

SUSP

12

R283
100K_0402_5%~D

13

D

Q40

SSM3K7002FU_SC70-3

S

+1.5VS

12

+1.5VS_D

61

2N7002DW-7-F_SOT363-6

1

2

1

C345
10U_0805_10V4Z~D

2

B+_BIAS

2 2

SUSP

3 3

470_0402_5%

4 4

SUSP SUSP

1
2
36

0.1U_0603_50V_X7R

C354

4

@

R285
0_0402_5%~D

@

R281
0_0402_5%~D

1
2
3

@

R298

470_0402_5%

Q5A

2

+3VS

1

C347
10U_0805_10V4Z~D

2

10U_0805_10V4Z~D

C356

1

2

+3V_PCH

12

+3V_D

61

1

C348
1U_0603_10V4Z

2

0.1U_0402_16V7K~D

C357

1

2

+3VS+VCCP

12

R299

470_0402_5%

+3VS_D

3

Q5B

5

2N7002DW-7-F_SOT363-6

4

2N7002DW-7-F_SOT363-6

B

1

C349
10U_0805_10V4Z~D

2

B+_BIAS

PCH_PWR_EN#

+1.05V to +1.05VSDGPU Transfer

330K_0402_5%

DGPU_PWR_EN#

+1.5V

12

R289

470_0402_5%

+1.5V_D

13

2

G

D

SSM3K7002FU_SC70-3

S

SYSON#

5

R1569 0_0603_5%~D

1

2

R1572
0_0603_5%~D

R1575
0_0603_5%~D

1U_0805_10V7

1

C1706

0.1U_0402_16V7K~D

2

C1711

+3.3V_F347

2

G

+3.3V_F347

2

G

+3.3V_F347

2

G

1

2

C1705

1U_0805_10V7

D D

C C

B B

+5VALW

BATT_CHG_LED#<31>

+5VS

1 2

1 2

@

PM_SLP_S3#<15,31>

ACIN<31,51>

1 2

W=40mils

+3.3V_F347

1

C1712

0.1U_0402_16V7K~D

2

JP1

1

1

2

2

3

5

3

G1

4

6

4

G2

MOLEX_53398-0471~D

CONN@

12

R1586
100K_0402_1%~D

SLP_S3

13

D

Q210
SSM3K7002F_SC59-3

S

12

R1588
100K_0402_1%~D

ACIN#

13

D

Q213
SSM3K7002F_SC59-3

S

12

R1592
100K_0402_1%~D

CHRG_STATE

13

D

Q216
SSM3K7002F_SC59-3

S

0.1U_0402_16V7K~D

+5VALW_VBUS

1 2

R1577
1K_0402_1%~D

+3.3V_F347

C1707

BATT_LOW_LED#<31>

1

2

USB20_P6<16>
USB20_N6<16>

1

2

PM_SLP_S5#<15,31>

+3.3V_F347

1

2

C1719

0.1U_0402_16V7K~D

@

+3.3V_F347_VDD

2

C1708
22P_0402_50V8J~D

1

C1715

0.1U_0402_16V7K~D

1

@

2

C1720

0.1U_0402_16V7K~D

1

@

2

3V_F347_ON<31>

0.1U_0402_16V7K~D

C1716

@

1

2

4

USB20_P6
USB20_N6

0.1U_0402_16V7K~D

1

2

C1721

0.1U_0402_16V7K~D

@

@

1

2

C1717

2

2

1

2

C1722

0.1U_0402_16V7K~D

@

+3.3V_F347

G

+3.3V_F347

G

U602

6

VDD

4

D+

5

D-

7

REGIN

8

VBUS

9

RST#/C2CK

10

P3.0/C2D

18

P2.0

17

P2.1

16

P2.2

15

P2.3

14

P2.4

13

P2.5

12

P2.6
P2.711GND

C8051F347-GQ_LQFP32_7X7

C1718

0.1U_0402_16V7K~D

@

12

R1587
100K_0402_1%~D

SLP_S5

13

D

Q211
SSM3K7002F_SC59-3

S

12

R1664
100K_0402_1%~D

BATT_LOW_LED

13

D

Q249
SSM3K7002F_SC59-3

S

12

R1593
100K_0402_1%~D

4.7K_0402_1%~D

SPI_MOCLK

2

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

2

G

SPI_MOSO

1

SPI_MOSI

32

SPI_MOCS#

31

I2C_DAT

30

I2C_CLK

29

C1710 0.1U_0402_16V7K~D@

28
27

26
25
24
23
22
21
20
19

3

+3VALW B+_BIAS

12

13

D

S

1 2

SLP_S3
CHRG_STATE
ACIN#
LID_SW_IN#

BATT_LOW_LED

SLP_S5

C1713 0.1U_0402_16V7K~D@

1 2

C1714 0.1U_0402_16V7K~D@

1 2

+3VALW +3.3V_F347

R1590
100K_0402_1%~D

Q215
SSM3K7002F_SC59-3

J11

2

JUMP_43X118

SI3456BDV-T1-E3 1N TSOP6

6

2
1

R1591
100K_0402_1%~D

1 2

2

G

+3.3V_F347+3.3V_F347

R1570

@

112

Q212

D

G

3

13

12

12

LID_SW_IN# <14,31,35>

S

45

1

C1726

0.1U_0402_25V6

2

D

Q214
SSM3K7002F_SC59-3

S

3

R1571

4.7K_0402_1%~D

4.7U_0603_6.3V6K~D

R1951

I2C_DAT <35,36>
I2C_CLK <35,36>

1 2

1K_0402_5%~D

1

C1725

2

12

1

2

1M_0402_5%~D

R1576

10K_0402_5%~D

12

R1589
100K_0402_1%~D

C1727

0.1U_0402_25V6

2

+3.3V_F347

8
6
5

SI

2

1

2

+3.3V_F347+3.3V_F347 +3.3V_F347

R1583 15_0402_5%
R1584 15_0402_5%
R1585 15_0402_5%

C1724
22P_0402_50V8J~D

R1581

12

12

R1582

10K_0402_5%~D

12

R1580
10K_0402_5%~D

SPI_MOCS#

U604

1

CE#

3

WP#

7

HOLD#

4

VSS

EN25F80-75HCP_SOP8

VDD
SCK

SO

+3.3V_F347 beh avior

STATE

AC IN

BAT only

S0 S3 S4 S5

ON ON ON ON

ON ON OFF OFF

MAXIM - LED
MAXIM - GPIO 0100 001b
I2C EEPROM

AC mode batter y full in S5:t urn off ELC co ntroller

1 2
1 2
1 2

1

C1723

0.1U_0402_16V7K~D

2

SPI_MOCLK
SPI_MOSI
SPI_MOSO

SMBUS ADDRESSDEVICE
0100 000b

1010 000b

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ELC (1)/STATUS CONN

LA-6801P

1

34 60Monday, December 06, 2010

0.3

5

4

3

2

1

7313_INT#<36>

Touchpad LED CONN

+3.3V_F347

R1595

1 2

12

4.7K_0402_1%~D

D D

4.7K_0402_1%~D

C C

R1594

4.7K_0402_1%~D

12

12

R1596

4.7K_0402_1%~D

+3.3V_F347

12

R1598

4.7K_0402_1%~D

R1597

7313_INT#<36>

12

R1599

4.7K_0402_1%~D

12

R1601

4.7K_0402_1%~D

I2C_CLK<34,36>
I2C_DAT<34,36>

12

R1600

4.7K_0402_1%~D

L/R Headlight, Logo

I2C_CLK
I2C_DAT

AD0_0

AD0_1

AD0_2

U605

22

INT#/O16

19

SCL

20

SDA

18

AD0

23

AD1

24

AD2

14

P12

15

P13

16

P14

17

P10

P15

P11

GND9GND

MAX7313ATG+T_TQFN24_4X4

TP_LED_R_DRV#
TP_LED_G_DRV#
TP_LED_B_DRV#

7313_INT#

CAP, Media, Eyes, Rim

U608

I2C_CLK
I2C_DAT

AD2_0
AD2_1
AD2_2

HDD_R_7313#
HDD_G_7313#
HDD_B_7313#

22

19
20

18
23
24

14
15
16
17

MAX7313ATG+T_TQFN24_4X4

INT#/O16

SCL
SDA

AD0
AD1
AD2

P12
P13
P14
P15

GND9GND

21

V+

1

P0

2

P1

3

P2

4

P3

5

P4

6

P5

7

P6

8

P7

10

P8

11

P9

12

P10

13

P11

25

V+

P0
P1
P2
P3
P4
P5
P6
P7
P8
P9

check with EC

+5VS

12

R1602
100K_0402_5%~D

SATA_LED_ACT

13

2

G

D

Q235
SSM3K7002F_SC59-3

S

PCH_SATALED#<13>

B B

PCH_SATALED#

21

LSPK_LED_R_DRV#

1

LSPK_LED_G_DRV#

2

LSPK_LED_B_DRV#

3

RSPK_LED_R_DRV#

4

RSPK_LED_G_DRV#

5

RSPK_LED_B_DRV#

6
7
8
10

LOGO_LED_R_DRV#

11

LOGO_LED_G_DRV#

12

LOGO_LED_B_DRV#

13
25

+3.3V_F347

LED_R_7313#_1
LED_G_7313#_1
LED_B_7313#_1

PWR_R_7313#
PWR_G_7313#
PWR_B_7313#

2

G

2

G

2

G

+3.3V_F347

5/18 delete

1

2

HDD_B

13

D

Q233
SSM3K7002F_SC59-3

S

HDD_B_7313#

HDD_R

13

D

Q234
SSM3K7002F_SC59-3

S

HDD_R_7313#

HDD_G

13

D

Q225
SSM3K7002F_SC59-3

S

HDD_G_7313#

1

C1728

0.1U_0402_16V7K~D

2

C1733

0.1U_0402_16V7K~D

LID_SW_IN#<14,31,34>

LID_SW_IN#

LID_SW

2

G

close to JTPMB 7/26

TP_CLK
TP_DATA

2

3

D70
PJDLC05C_SOT23-3

1

+5VALW

12

R1603
100K_0402_5%~D

LID_SW

13

D

Q232

2

SSM3K7002F_SC59-3

G

S

SATA_LED_ACT

13

D

Q224
SSM3K7002F_SC59-3

S

0.1U_0402_16V7K~D

+5VS

C605

WLES ON/OFF LED#<31>

0.1U_0402_16V7K~D

+3VALW

+3VS

TP_DATA<31>
TP_CLK<31>

CAPS_LED#< 31>

C603

TP_DATA
TP_CLK
LID_SW_IN#
TP_LED_R_DRV#
TP_LED_G_DRV#
TP_LED_B_DRV#

LSPK_LED_R_DRV#
LSPK_LED_G_DRV#
LSPK_LED_B_DRV#
RSPK_LED_R_DRV#
RSPK_LED_G_DRV#
RSPK_LED_B_DRV#

CAPS_LED#

+5VS_TP_LED

+5VS

2

+5VS

2

JTPMB

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

GND1

22

GND2

HRS_FH28E-20S-0.5SH(11)

CONN@

12

R1976

100K_0402_5%~D

WLAN_BT_LED

61

12

100K_0402_5%~D

61

5

Q301A
2N7002DW-7-F_SOT363-6~D

R1978

CAPS_LED

Q302A
2N7002DW-7-F_SOT363-6~D

+5VS

12

R1975

100K_0402_5%~D

WLAN_BT_LED_A#

3

Q301B
2N7002DW-7-F_SOT363-6~D

4

+5VS

12

R1977

100K_0402_5%~D

3

5

Q302B
2N7002DW-7-F_SOT363-6~D

4

4.7K_0402_1%~D

LOGO_LED_R_DRV#

4.7K_0402_1%~D

LOGO_LED_G_DRV#

CAPS_LED_A#

4.7K_0402_1%~D

LOGO_LED_B_DRV#

Indicator CONN

C1729

0.1U_0402_16V7K~D

LED_R_7313#_1
LED_B_7313#_1
LED_G_7313#_1
CAPS_LED_A#
WLAN_BT_LED_A#

+5VS

12

+5VS

R1969

4.7K_0402_1%~D

12

LOGO_LED_R_DRV

R1970

61

Q298A

2

2N7002DW-7-F_SOT363-6~D

+5VS

12

+5VS

R1971

4.7K_0402_1%~D

12

LOGO_LED_G_DRV

R1972

61

Q299A

2

2N7002DW-7-F_SOT363-6~D

+5VS

12

+5VS

R1973

4.7K_0402_1%~D

12

LOGO_LED_B_DRV

R1974

61

Q300A

2

2N7002DW-7-F_SOT363-6~D

+5VS

1

2

LOGO_LED_R_DRV_1#

3

5

4

LOGO_LED_G_DRV_1#

3

5

4

LOGO_LED_B_DRV_1#

3

5

4

JCAP

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

TYCO_2041183-6

CONN@

Q298B
2N7002DW-7-F_SOT363-6~D

Q299B
2N7002DW-7-F_SOT363-6~D

Q300B
2N7002DW-7-F_SOT363-6~D

MAX7313AD2 AD1 AD0Reference

U605

U608

A A

0 1 0

0 1 1

5

L/R Headlight , Logo, TP

Num, CAP , SCR
EJECT, REV, PLAY/PAUSE
FFWD, Vol_DWN, Vol_UP
Wireless ON/OFF
AWCC Button
Alien Adrenaline
Power Button Eyes
Power Button Rim

EN_TPLED#<31>

SSM3K7002FU_SC70-3

4

R173

470K_0402_5%~D

2

G

Q44

B+_BIAS

0.1U_0402_16V7K~D

1 2

EN_TPLED

13

D

S

C1746

SI3456BDV-T1-E3 1N TSOP6

D

6

2
1

1

Q45

G

3

2

12

R1654
2M_0402_5%~D

1

2

Touchpad LED circuit

+5VS_TP_LED+5VS

S

45

C185

0.1U_0402_25V6

3

1U_0603_10V4Z

1

C184

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

LOGO Board CONN

+5VS

1

C1732

0.1U_0402_16V7K~D

2

LID_SW
LOGO_LED_R_DRV_1#
LOGO_LED_G_DRV_1#
LOGO_LED_B_DRV_1#

2010/12/01 2011/12/01

JLOGO

20mil

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

TYCO_0-1775737-6

CONN@

Compal Secret Data

Deciphered Date

2

PWR BTN Board CONN

+5VS

JBTN

1

ON/OFFBTN#<29>

+5VALW

Title

Size Document Number Rev

Date: Sheet

ON/OFFBTN#
HDD_R
HDD_G
HDD_B

LID_SW
PWR_R_7313#
PWR_G_7313#
PWR_B_7313#

Compal Electronics, Inc.

ELC (2)

LA-6801P

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

G1

14

G2

FCI_10089708-012010-LF

CONN@

1

35 60Monday, December 06, 2010

0.3

of

5

4

3

2

1

K/B Backlight CONN

CONN@

TYCO_1-2041070-6~D

18

GND

17

GND

16

16

15

D D

+3.3V_F347

7313_INT#<35>

12

12

R1606

R1605

12

R1608

4.7K_0402_1%~D

KB_LED_R1_DRV#

4.7K_0402_1%~D

KB_LED_G1_DRV#

4.7K_0402_1%~D

KB_LED_B1_DRV#

4.7K_0402_1%~D

KB_LED_B3_DRV#

4.7K_0402_1%~D

I2C_CLK<34,35>

I2C_DAT<34,35>

12

R1609

4.7K_0402_1%~D

+3VS

R1613

+3VS

R1619

+3VS

R1625

+3VS

R1631

4.7K_0402_1%~D

4.7K_0402_1%~D

C C

B B

K/B Backlight

AD2 AD1 AD0
0 0 1

I2C_CLK

AD3_0
AD3_1
AD3_2

+3VS

12

R1612

12

12

12

12

4.7K_0402_1%~D

KB_LED_R1_DRV

3

Q277B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1618

4.7K_0402_1%~D

KB_LED_G1_DRV

3

Q271B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1624

4.7K_0402_1%~D

KB_LED_B1_DRV

3

Q273B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1630

4.7K_0402_1%~D

KB_LED_B3_DRV

3

Q278B
DMN66D0LDW-7_SOT363-6~D

5

4

U609

22

INT#/O16

V+

19

P0

SCL

20

P1

SDA

P2

18

P3

AD0

23

P4

AD1

24

P5

AD2

P6

14

P7

P12

15

P8

P13

16

P9

P14

17

P10

P15

P11

GND9GND

MAX7313ATG+T_TQFN24_4X4

2

2

2

2

+3.3V_F347

21

KB_LED_R1_DRV#

1

KB_LED_G1_DRV#I2C_DAT

2

KB_LED_B1_DRV#

3

KB_LED_R2_DRV#

4

KB_LED_G2_DRV#

5

KB_LED_B2_DRV#

6

KB_LED_R3_DRV#

7

KB_LED_G3_DRV#

8

KB_LED_B3_DRV#

10

KB_LED_R4_DRV#

11

KB_LED_G4_DRV#

12

KB_LED_B4_DRV#

13
25

KB_LED_R1_DRV#_A#

61

Q277A
DMN66D0LDW-7_SOT363-6~D

KB_LED_G1_DRV#_A#

61

Q271A
DMN66D0LDW-7_SOT363-6~D

KB_LED_B1_DRV#_A#

61

Q273A
DMN66D0LDW-7_SOT363-6~D

KB_LED_B3_DRV#_A#

61

Q278A
DMN66D0LDW-7_SOT363-6~D

4.7K_0402_1%~D

KB_LED_R2_DRV#

4.7K_0402_1%~D

KB_LED_G2_DRV#

4.7K_0402_1%~D

KB_LED_B2_DRV#

4.7K_0402_1%~D

KB_LED_R3_DRV#

4.7K_0402_1%~D

KB_LED_G3_DRV#

R1607

+3VS

12

+3VS

R1611

+3VS

R1617

+3VS

R1623

+3VS

R1629

+3VS

12

R1604

4.7K_0402_1%~D

KB_LED_R2_DRV

3

Q262B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1610

12

12

12

12

4.7K_0402_1%~D

KB_LED_G2_DRV

3

Q282B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1616

4.7K_0402_1%~D

KB_LED_B2_DRV

3

Q267B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1622

4.7K_0402_1%~D

KB_LED_R3_DRV

3

Q268B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1628

4.7K_0402_1%~D

KB_LED_G3_DRV

3

Q269B
DMN66D0LDW-7_SOT363-6~D

5

4

KB_LED_R2_DRV#_A#

61

Q262A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_G2_DRV#_A#

61

Q282A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_B2_DRV#_A#

61

Q267A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_R3_DRV#_A#

61

Q268A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_G3_DRV#_A#

61

Q269A
DMN66D0LDW-7_SOT363-6~D

2

4.7K_0402_1%~D

KB_LED_R4_DRV#

4.7K_0402_1%~D

KB_LED_G4_DRV#

4.7K_0402_1%~D

KB_LED_B4_DRV#

+5VS

0.5A_13.2V_NANOSMDC050F-13.2-2

+3VS

R1615

+3VS

R1621

+3VS

R1627

KB_LED_R1_DRV#_A#
KB_LED_G1_DRV#_A#
KB_LED_B1_DRV#_A#
KB_LED_R2_DRV#_A#
KB_LED_G2_DRV#_A#
KB_LED_B2_DRV#_A#
KB_LED_R3_DRV#_A#
KB_LED_G3_DRV#_A#
KB_LED_B3_DRV#_A#
KB_LED_R4_DRV#_A#
KB_LED_G4_DRV#_A#
KB_LED_B4_DRV#_A#

F3

21

+3VS

12

R1614

4.7K_0402_1%~D

12

12

12

KB_LED_R4_DRV

3

Q264B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1620

4.7K_0402_1%~D

KB_LED_G4_DRV

3

Q265B
DMN66D0LDW-7_SOT363-6~D

5

4

+3VS

12

R1626

4.7K_0402_1%~D

KB_LED_B4_DRV

3

Q266B
DMN66D0LDW-7_SOT363-6~D

5

4

14
13
12
11
10

9
8
7
6
5
4
3
2
1

KB_LED_R4_DRV#_A#

61

Q264A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_G4_DRV#_A#

61

Q265A
DMN66D0LDW-7_SOT363-6~D

2

KB_LED_B4_DRV#_A#

61

Q266A
DMN66D0LDW-7_SOT363-6~D

2

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

JKBBL1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

ELC (3)

LA-6801P

1

of

36 60Monday, December 06, 2010

0.3

5

PCH/GPU DDC SW for DMC

+3VS

1 2

R1862 1.5K_0402_5%~D@

1 2

R1864 1.5K_0402_5%~D@

D D

DMC_PCH_DET#<14>

C C

VGA_DPD_P0<44>
VGA_DPD_N0<44>
VGA_DPD_P1<44>

B B

VGA_DPD_N1<44>
VGA_DPD_P2<44>
VGA_DPD_N2<44>
VGA_DPD_P3<44>
VGA_DPD_N3<44>

PCH_DPD_P0<15>
PCH_DPD_N0<15>
PCH_DPD_P1<15>
PCH_DPD_N1<15>
PCH_DPD_P2<15>
PCH_DPD_N2<15>
PCH_DPD_P3<15>
PCH_DPD_N3<15>

A A

PCH_DPD_CLK

PCH_DPD_DAT

VGA_DPD_AUXP/DDC<44>
VGA_DPD_AUXN/DDC<44>

+3VS_DELAY

C1894 0.1U_0402_10V6K~D@
C1895 0.1U_0402_10V6K~D@
C1896 0.1U_0402_10V6K~D@
C1897 0.1U_0402_10V6K~D@
C1900 0.1U_0402_10V6K~D@
C1901 0.1U_0402_10V6K~D@
C1902 0.1U_0402_10V6K~D@
C1903 0.1U_0402_10V6K~D@

C1904 0.1U_0402_16V7K~D
C1905 0.1U_0402_16V7K~D
C1906 0.1U_0402_16V7K~D
C1907 0.1U_0402_16V7K~D
C1908 0.1U_0402_10V7K~D
C1909 0.1U_0402_10V7K~D
C1910 0.1U_0402_10V7K~D
C1911 0.1U_0402_10V7K~D

VGA_DMC_HPD<44>

PCH_DPD_CLK<15>
PCH_DPD_DAT<15>
PCH_DMC_HPD<15>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

0_0402_5%~D

1 2

@

R1883

+3VS_DELAY

VGA_DPD_AUXP/DDC

1 2

R1867 1.5K_0402_5%~D@

R1865 1.5K_0402_5%~D@

PCH_DPD_CLK
PCH_DPD_DAT DMC_DET#

DGPU_EDIDSEL#<17>

SEL

0

1

100K_0402_5%~D

@

R1878

1 2

1 2

VGA_DPD_AUXP/DDC
VGA_DPD_AUXN/DDC

R1869 10K_0402_5%~D@

R1870 10K_0402_5%~D@

A0 B0 C0 D0

A1 B1 C1 D1

S

G

2

D

1 3

@

499_0402_1%~D

499_0402_1%~D

R1900

R1901

1 2

@

R1920 680_0402_1%~D

12

+3VS

VGA_DPD_AUXN/DDC

12

12

DGPU_EDIDSEL#

Y

2N7002_SOT23

Q291

499_0402_1%~D

499_0402_1%~D

R1903

R1902

1 2

1 2

@

@

R1921 680_0402_1%~D

R1922 680_0402_1%~D

12

12

499_0402_1%~D

R1905

R1904

1 2

1 2

@

@

R1923 680_0402_1%~D

R1924 680_0402_1%~D

12

12

0_0402_5%~D

1 2

R1929

R1930

100K_0402_5%~D

PCH_DPD_CLK

PCH_DPD_DAT

PCH_DMC_HPD

499_0402_1%~D

R1906

1 2

@

R1925 680_0402_1%~D

12

12

U630

2

IA0

5

IB0

11

IC0

14

ID0

3
6

IB1

10

IC1

13

ID1

1

SEL

15

EN#

PI5C3257QEX_QSOP16

@

1 2

1 2

1 2

1 2

499_0402_1%~D

499_0402_1%~D

R1907

1 2

1 2

@

@

R1926 680_0402_1%~D

12

12

13

D

2

G

Q293

S

2N7002_SOT23

4

+3VS

16

VCC

4

YA

7

YB
YC9IA1

12

YD

8

GND

R2008 0_0402_5%~D

R2009 0_0402_5%~D

R2010 0_0402_5%~D

R2011 0_0402_5%~D

@

0.1U_0402_16V7K~D

1

C1883

2

DP_DMC_AUXP
DP_DMC_AUXN

DMC_HPD

DP_DMC_AUXP

DP_DMC_AUXN

DMC_HPD

DMC_DET#DMC_PCH_DET#

@

0.1U_0402_16V7K~D

1

C1884

2

DMC_DET# <32>

DMC_DAT_AUXN_CONN<32>
DMC_CLK_AUXP_CONN<32>

PCH/GPU AUX&LANE SW for DMC

6/5 change C18 8, C1162 0805 to 0603

VGA_DPD_SW_P0
VGA_DPD_SW_N0
VGA_DPD_SW_P1
VGA_DPD_SW_N1
VGA_DPD_SW_P2
VGA_DPD_SW_N2
VGA_DPD_SW_P3
VGA_DPD_SW_N3

PCH_DPD_SW_P0
PCH_DPD_SW_N0
PCH_DPD_SW_P1
PCH_DPD_SW_N1
PCH_DPD_SW_P2
PCH_DPD_SW_N2
PCH_DPD_SW_P3
PCH_DPD_SW_N3

R1927 680_0402_1%~D

+1.5VS_DMC

10U_0603_6.3V6M~D

1

2

@

0.1U_0402_16V7K~D

C1912

22
23
24
25
26
27
28
29

31
32
33
34
35
36
37
38

39
41
21
19
17
13
10

5
1

C1913

1

2

@

U631

D3-_B
D3+_B
D2-_B
D2+_B
D1-_B
D1+_B
D0-_B
D0+_B

D3-_A
D3+_A
D2-_A
D2+_A
D1-_A
D1+_A
D0-_A
D0+_A

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PI3HDMI412FT-BZHE_TQFN42_9X3P5

@

42

VDD

40

VDD

30

VDD

20

VDD

18

VDD

16

VDD

8

VDD

2

VDD

DMC_SW_P0

15

D3-

DMC_SW_N0

14

D3+

DMC_SW_P1

12

D2-

DMC_SW_N1

11

D2+

DMC_SW_P2

7

D1-

DMC_SW_N2

6

D1+

DMC_SW_P3

4

D0-

DMC_SW_N3

3

D0+

DMC_DGPU_SELECT#

9

SEL

43

GND_PAD

+1.5VS_DMC +VCCAFDI_VRM

R1932

@

12

0_0603_5%~D

10U_0603_6.3V6M~D

1

2

+1.5VS_DMC

C1898

@

3

DMC Redriver

+3VS

1 2

R1866 1.5K_0402_5%~D

1 2

R1868 1.5K_0402_5%~D

1 2

RV17 4.7K_0402_5%~D@

1 2

RV16 4.7K_0402_5%~D@

+5VS

12

12

R1873

R1872

1.5K_0402_5%~D

1.5K_0402_5%~D

+3VS

+3VS

C1899

0.1U_0402_16V7K~D

2

@

1

R1911 0_0402_5%~D@

1 2

R1912 0_0402_5%~D@

1 2

R1913 0_0402_5%~D@

1 2

R1915 0_0402_5%~D@

1 2

R1916 0_0402_5%~D@

1 2

R1917 0_0402_5%~D@

1 2

R1918 0_0402_5%~D@

1 2

R1919 0_0402_5%~D@

1 2

DP_DMC_AUXN

DP_DMC_AUXP

DMC_SDA_CTL

DMC_SCL_CTL

DP_DMC_ML0P
DP_DMC_ML0N
DP_DMC_ML1P
DP_DMC_ML1N
DP_DMC_ML2P
DP_DMC_ML2N
DP_DMC_ML3P
DP_DMC_ML3N

+3VS

R1871 4.7K_0402_5%~D

1 2

+3VS

DMC_DAT_AUXN_CONN
DMC_CLK_AUXP_CONN

R1874 4.7K_0402_5%~D

1 2

R1875 4.7K_0402_5%~D@

1 2

R1876 4.7K_0402_5%~D

1 2

1 2

DP_DMC_ML0P
DP_DMC_ML0N
DP_DMC_ML1P
DP_DMC_ML1N
DP_DMC_ML2P
DP_DMC_ML2N
DP_DMC_ML3P
DP_DMC_ML3N

DP_DMC_HPD

DMC_SDA_CTL
DMC_SCL_CTL

R1877
499_0402_1%~D

PCH_DPD_SW_P0
PCH_DPD_SW_N0

PCH_DPD_SW_P1

PCH_DPD_SW_P2
PCH_DPD_SW_N2

PCH_DPD_SW_P3
PCH_DPD_SW_N3

2

Close to U158 VCC pins

33

46

11

15

GND15GND2

12

21

VCC1

VCC2

GND424GND631GND5

GND3

27

18

VCC4

VCC540VCC6

VCC3

GND7

GND837GND9

36

43

49

DP_DMC_R_ML0P
DP_DMC_R_ML0N

DP_DMC_R_ML1P
DP_DMC_R_ML1N

DP_DMC_R_ML2P
DP_DMC_R_ML2N

DP_DMC_R_ML3P
DP_DMC_R_ML3N

C1879

0.01U_0402_16V7K~D

23

OUT1p

22

OUT1n

20

OUT2p

19

OUT2n

17

OUT3p

16

OUT3n

14

OUT4p

13

OUT4n

7

HPD

29

SDAZ

28

SCLZ

GND10

PS121QFN48G_QFN48_7X7

R1954 0_0402_5%~D
R1956 0_0402_5%~D

R1958 0_0402_5%~D
R1960 0_0402_5%~D

R1962 0_0402_5%~D
R1964 0_0402_5%~D

R1966 0_0402_5%~D
R1968 0_0402_5%~D

U629

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN#

32

DMC_OE#

1

2

NC/DDCBUF_EN#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG1

35

SCL_CTL/CFG0

DMC_PC0

3

I2C_ADDR0/PC0

DMC_PC1

4

I2C_ADDR1/PC1

DMC_PC1

1

GND/PC2

6

REXT

10

CEXT

C1893

2.2U_0402_6.3V6M~D

R1953 0_0402_5%~D

1 2

R1955 0_0402_5%~D

1 2

R1957 0_0402_5%~D

1 2

R1959 0_0402_5%~D

1 2

R1961 0_0402_5%~D

1 2

R1963 0_0402_5%~D

1 2

R1965 0_0402_5%~D

1 2

R1967 0_0402_5%~D

1 2

Close to U631 Close to U629

+3VS

12

R931

100K_0402_1%~D

DMC_OE#

13

D

Q292

2N7002_SOT23

DMC_DGPU_SELECT#

+3VS

@

S

12

12

DP_DMC_HPD

2

G

R1928
36K_0402_1%

R1933
680K_0402_1%@

R1931

1 2

30K_0402_1%

@

1

1

2

2

C1880

0.1U_0402_16V7K~D

DMC_HPD

DP_DMC_AUXN
DP_DMC_AUXP

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

DP_DMC_HPD <32>

1

2

C1881

C1882

0.1U_0402_16V7K~D

DP_DMC_ML0P_RCC
DP_DMC_ML0N_RCC
DP_DMC_ML1P_RCC
DP_DMC_ML1N_RCC

DP_DMC_ML2P_RCC
DP_DMC_ML2N_RCC
DP_DMC_ML3P_RCC
DP_DMC_ML3N_RCC

DGPU_SELECT# <16>

+3VS

0.01U_0402_16V7K~D

1

2

DP_DMC_ML0P
DP_DMC_ML0N

DP_DMC_ML1P
DP_DMC_ML1NPCH_DPD_SW_N1

DP_DMC_ML2P
DP_DMC_ML2N

DP_DMC_ML3P
DP_DMC_ML3N

1

DP_DMC_ML0P_RCC <32>
DP_DMC_ML0N_RCC <32>
DP_DMC_ML1P_RCC <32>
DP_DMC_ML1N_RCC <32>
DP_DMC_ML2P_RCC <32>
DP_DMC_ML2N_RCC <32>
DP_DMC_ML3P_RCC <32>
DP_DMC_ML3N_RCC <32>

Source

ChanelAUX_SEL/SEL1&2

0

1

5

4

GPUA

PCH

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

DMC MUX/Redriver

LA-6801P

1

37 60Monday, December 06, 2010

of

0.3

5

DP Redriver

1

CV1

0.1U_0402_16V7K~D

D D

DISP_A0P_VGA
DISP_A0N_VGA

DISP_A1P_VGA
DISP_A1N_VGA

DISP_A2P_VGA
DISP_A2N_VGA

DISP_A3P_VGA
DISP_A3N_VGA

C C

DISP_A0P_VGA_C
DISP_A0N_VGA_C

DISP_A1P_VGA_C
DISP_A1N_VGA_C

DISP_A2P_VGA_C
DISP_A2N_VGA_C

DISP_A3P_VGA_C
DISP_A3N_VGA_C

DISP_AUXP_C
DISP_AUXN_C

DISP_HPD_SINK DP_HPD_CDISP_HPD_SINK_R

B B

CV10 0.1U_0402_10V6K~D
CV12 0.1U_0402_10V6K~D

CV7 0.1U_0402_10V6K~D
CV9 0.1U_0402_10V6K~D

CV14 0.1U_0402_10V6K~D
CV16 0.1U_0402_10V6K~D

CV22 0.1U_0402_10V6K~D
CV18 0.1U_0402_10V6K~D

DISP_A0P_VGA<44>
DISP_A0N_VGA<44>
DISP_A1P_VGA<44>
DISP_A1N_VGA<44>
DISP_A2P_VGA<44>
DISP_A2N_VGA<44>
DISP_A3P_VGA<44>
DISP_A3N_VGA<44>

DISP_AUXP<44>

DISP_AUXN<44>

RV171 0_0402_5%~D@
RV173 0_0402_5%~D@

RV175 0_0402_5%~D@
RV177 0_0402_5%~D@

RV179 0_0402_5%~D@
RV181 0_0402_5%~D@

RV183 0_0402_5%~D@
RV185 0_0402_5%~D@

RV187 0_0402_5%~D@
RV189 0_0402_5%~D@

RV191 0_0402_5%~D@

12
12

12
12

12
12

12
12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

DISP_A0P_VGA

DISP_A0N_VGA

DISP_A1P_VGA

DISP_A1N_VGA

DISP_A2P_VGA

DISP_A2N_VGA

DISP_A3P_VGA

DISP_A3N_VGA

DISP_AUXP

DISP_AUXN

DISP_A0P_VGA_C
DISP_A0N_VGA_C

DISP_A1P_VGA_C
DISP_A1N_VGA_C

DISP_A2P_VGA_C
DISP_A2N_VGA_C

DISP_A3P_VGA_C
DISP_A3N_VGA_C

DP_HPD_C

CAB_DET_SINK
DISP_HPD_SINK

DISP_A0P_R
DISP_A0N_R

DISP_A1P_R
DISP_A1N_R

DISP_A2P_R
DISP_A2N_R

DISP_A3P_R
DISP_A3N_R

DISP_AUXP_R
DISP_AUXN_R

GPU DDC Dongle SW for DP

CAB_DET_SINK#
DISP_AUXP

CAB_DET_SINK#
DISP_AUXN

DISP_DAT_AUXN_CONN

Dongle

A A

UV19

1
2

3

4
5

6

7

PI3C3125LEX_TSSOP14~D

BE0
A0

B0

BE1
A1

B1

GND

VCC

BE3

BE2

14
13

12

A3

11

B3

10

9

A2

8

B2

2

36

UV1

1

D0+

2

VCC33

D0-

3

D1+

4

D1-

6

D2+

7

D2-

9

D3+

10

D3-

12

CAD

13

HPDSRC

14

CAD_SINK

15

HPD_SINK

16

NC

RV172 0_0402_5%~D@

1 2

RV174 0_0402_5%~D@

1 2

RV176 0_0402_5%~D@

1 2

RV178 0_0402_5%~D@

1 2

RV180 0_0402_5%~D@

1 2

RV182 0_0402_5%~D@

1 2

RV184 0_0402_5%~D@

1 2

RV186 0_0402_5%~D@

1 2

RV188 0_0402_5%~D@

1 2

RV190 0_0402_5%~D@

1 2

RV192 0_0402_5%~D@

1 2

+3VS_DELAY

CV535 0.1U_0402_10V6K~D

CAB_DET_SINK

DISP_AUXP_C

CAB_DET_SINK

4

+1.5VS+3VS

5

11

17

21

29

VDD15

VDD15

VDD15

VDD15

VDD15

AUX_SINK+

GND

GND

GND

GND

PI2EQXDP101ZFEX_TQFN36_6X5

8

18

24

37

28

D0+A

27

D0-A

26

D1+A

25

D1-A

23

D2+A

22

D2-A

20

D3+A

19

D3-A

31
30

AUX_SINK-

33

AUXSRC+

32

AUXSRC-

35

DDCSDA

34

DDCSCL

DISP_A0P
DISP_A0N

DISP_A1P
DISP_A1N

DISP_A2P
DISP_A2N

DISP_A3P
DISP_A3N

DISP_CLK_AUXP_CONN

DISP_DAT_AUXN_CONN

12

CV525 0.1U_0402_10V6K~D

12

CV526 0.1U_0402_10V6K~D

12

Normal

CV2

0.1U_0402_16V7K~D

1

2

DISP_A0P_C
DISP_A0N_C

DISP_A1P_C
DISP_A1N_C

DISP_A2P_C
DISP_A2N_C

DISP_A3P_C
DISP_A3N_C

DISP_AUXPDISP_CLK_AUXP_CONN

DISP_AUXNDISP_AUXN_C

3

CV3

0.1U_0402_16V7K~D

CV4

0.1U_0402_16V7K~D

1

1

2

2

10

9

7

6

10

9

7

6

DISP_A0N

DISP_A0P

DISP_A1P

DISP_A1N

DISP_A3P

DISP_A3N

DISP_A2N

DISP_A2P

DISP_A0P
DISP_A0N

DISP_A1P
DISP_A1N

DISP_A2P
DISP_A2N

DISP_A3P
DISP_A3N

DISP_AUXN_C
DISP_AUXP_C

DISP_AUXN
DISP_AUXP

DP_CBL_DET<16>

+3VS_DELAY

2K_0402_5%~D

12

@

100K_0402_5%~D

12

+3VS

RV281

RV272

100K_0402_5%~D

12

RV268

100K_0402_5%~D

12

RV270

2K_0402_5%~D

12

@

100K_0402_5%~D

12

DP_CBL_DET

CAB_DET_SINK#

Close connect

2N7002_SOT23

RV282

RV271

CV5 0.1U_0402_10V6K~D
CV8 0.1U_0402_10V6K~D

CV13 0.1U_0402_10V6K~D
CV15 0.1U_0402_10V6K~D

CV17 0.1U_0402_10V6K~D
CV23 0.1U_0402_10V6K~D

CV19 0.1U_0402_10V6K~D
CV24 0.1U_0402_10V6K~D

DISP_CLK_AUXP_CONN
DISP_DAT_AUXN_CONN

DV2

DISP_A0N

DISP_A0P

DISP_A1P

DISP_A1N

@

1

2

4

5

3

8

RCLAMP0524P.TCT~D

Place close JDP1

DV1

DISP_A3P

DISP_A3N

DISP_A2N

DISP_A2P

@

1

2

4

5

12
12

12
12

12
12

12
12

3

8

RCLAMP0524P.TCT~D

07/29/2010
DP HPD for OPT DGPU output

RV239

DGPU_PWROK<16,17,39,55,56>

10K_0402_5%~D

0_0402_5%~D

DP_HPD_C

12

RV280

1

12

2

SN74AHC1G08DCKR_SC70-5

+3VS

5

UV17

P

IN1

O

IN2

G

3

1 2

0_0402_5%~D

RV240

@

CV506

0.1U_0402_16V7K~D

1 2

DP_HPD

4

DP_PCH_HPD<13>

QV14

2

RV231

1 2

0_0402_5%~D

+3VS

12

13

D

S

DP_HPD <44>

1

Co-lay

FV1

+3VS

100K_0402_5%~D

RV267

2

G

RV269

1 2

1.5A_6V_1206L150PR~D

RV3 0_1206_5%~D@

DISP_HPD_SINK
DISP_A0P
CAB_DET_SINK
DISP_A0N
DISP_CEC

DISP_A1P
DISP_A3P
DISP_A1N
DISP_A3N

DISP_A2P
DISP_CLK_AUXP_CONN
DISP_A2N
DISP_DAT_AUXN_CONN

12

12

RV4

1M_0402_5%~D

1M_0402_5%~D

PMBT3904_SOT23

RV234 0_0402_5%~D

1 2

6/5 change C61 0805 to 0603

+3VS_DP

CV6

10U_0603_6.3V6M~D

1

12

+3VS

QV9

RV6 1M_0402_5%~D

12

@

1

C

2

B

E

3

12

RV235
10K_0402_5%~D

2

CV28 0.1U_0402_10V6K~D

CV27 22U_0805_6.3V6M~D

1

1

2

2

RV233

150K_0402_5%

1 2

1

2

RV5 5.1M_0402_5%

12

CV11

0.1U_0402_16V7K~D

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

FOX_3V112M3-RH3HH7-7H

DISP_HPD_SINK

1
2
3
4
5
6
7
8
9

JMDP1

GND

LANE0_P

LANE0_N

GND

LANE1_P

LANE1_N

GND

LANE2_P

LANE2_N

GND

GROUND

CONN@

HPD

CONFIG1

CONFIG2

GND

LANE3_P

LANE3_N

GND

AUXCH_P

AUXCH_N

DP_PWR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/12/01 2011/12/01

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Mini Display Port

LA-6801P

38 60Monday, December 06, 2010

1

0.3

+3VS_DELAY

+3VS

HDMI_DDC_DATA

HDMI_DDC_CLK

HDMI_SDA_CTL

HDMI_SCL_CTL

CV516 0.1U_0402_10V7K~D

12

CV517 0.1U_0402_10V7K~D

12

CV518 0.1U_0402_10V7K~D

12

CV519 0.1U_0402_10V7K~D

12

CV520 0.1U_0402_10V7K~D

12

CV521 0.1U_0402_10V7K~D

12

CV522 0.1U_0402_10V7K~D

12

CV523 0.1U_0402_10V7K~D

12

RV25 4.7K_0402_5%~D

+3VS

RV31 4.7K_0402_5%~D
RV32 4.7K_0402_5%~D@

RV33 4.7K_0402_5%~D

+3VS

1 2

RV281.5K_0402_5%~D

12

RV291.5K_0402_5%~D

12

1 2
1 2

1 2

HDMI_R_HPLUG

HDMI_OE#

DDC_DAT_HDMI

DDC_CLK_HDMI

HDMI_SDA_CTL
HDMI_SCL_CTL

RV36
499_0402_1%~D

1 2

HDMI_A3P_C_VGA
HDMI_A3N_C_VGA
HDMI_A0P_C_VGA
HDMI_A0N_C_VGA
HDMI_A1P_C_VGA
HDMI_A1N_C_VGA
HDMI_A2P_C_VGA
HDMI_A2N_C_VGA

1 2

RV12 4.7K_0402_5%~D

1 2

RV13 4.7K_0402_5%~D

1 2

RV14 4.7K_0402_5%~D@

1 2

RV15 4.7K_0402_5%~D@

HDMI_A3P_VGA<44>
HDMI_A3N_VGA< 44>
HDMI_A0P_VGA<44>
HDMI_A0N_VGA< 44>
HDMI_A1P_VGA<44>
HDMI_A1N_VGA< 44>
HDMI_A2P_VGA<44>
HDMI_A2N_VGA< 44>

B B

+5VS

2

PC0
PC1

PC2

1

CV47

2.2U_0402_6.3V6M~D

2

UV2

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN#

32

NC/DDCBUF_EN#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG1

35

SCL_CTL/CFG0

3

I2C_ADDR0/PC0

4

I2C_ADDR1/PC1

1

GND/PC2

6

REXT

10

CEXT

Place close JHDMI1

1

2

CV33

CV34

0.1U_0402_16V7K~D

1

@

CV530
10P_0402_50V8J~D

2

+3VS

1

2

0.01U_0402_16V7K~D

HDMI_DDC_DATA < 44>
HDMI_DDC_CLK <44>

TMDS_TXCN

TMDS_TXCP

TMDS_TX0N TMDS_L_TX0N

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

Close to U158 VCC pins

1

1

33

46

11

15

21

VCC4

VCC540VCC6

VCC1

VCC2

VCC3

OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
OUT4p
OUT4n

SDAZ
SCLZ

GND7

GND424GND631GND5

GND3

GND15GND2

GND837GND9

GND10

PS121QFN48G_QFN48_7X7

36

27

18

12

43

49

HPD

CV31

0.01U_0402_16V7K~D

23
22
20
19
17
16
14
13

7

29
28

2

2

CV32

0.1U_0402_16V7K~D

TMDS_TXCP
TMDS_TXCN
TMDS_TX0P
TMDS_TX0N
TMDS_TX1P
TMDS_TX1N
TMDS_TX2P
TMDS_TX2N

HDMI_HPD_C

HDMI_DDC_DATA

HDMI_DDC_CLK

RV21 0_0402_5%~D@

1 2

LV1

1

1

4

4

MURATA DLW21SN 900HQ2L

RV27 0_0402_5%~D@

1 2

RV30 0_0402_5%~D@

1 2

LV2

1

1

4

4

MURATA DLW21SN 900HQ2L

@

RV34 0_0402_5%~D

1 2

RV35 0_0402_5%~D@

1 2

LV3

1

1

4

4

MURATA DLW21SN 900HQ2L

RV37 0_0402_5%~D@

1 2

RV38 0_0402_5%~D@

1 2

LV4

1

1

4

4

MURATA DLW21SN 900HQ2L

RV39 0_0402_5%~D@

1 2

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

TMDS_L_TXCN

TMDS_L_TXCP

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX2N

TMDS_L_TX2P

1

+5VS

BAT1000-7-F_SOT23-3~D

W=40mils

DV3

2 1
3

NC

@

RV10 0_1206_5%~D

12

FV2

1.5A_6V_1206L150PR~D

12

HDMI_HPLUG

DDC_DAT_HDMI
DDC_CLK_HDMI

TMDS_L_TXCN

TMDS_L_TXCP
TMDS_L_TX2N

TMDS_L_TX2P
TMDS_L_TX1N

TMDS_L_TX1P
TMDS_L_TX0N

TMDS_L_TX0P

+VDISPLAY_VCC

CV29

1

1

CV30

2

2

0.1U_0402_10V7K~D

10U_0603_6.3V6M~D

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11
10

9
8
7
6
5
4
3
2
1

GND

CK_shield

GND

CK+

GND

D0-

GND
D0_shield
D0+
D1­D1_shield
D1+
D2­D2_shield
D2+

SUYIN_100042MR019S153ZL

CONN@

20
21
22
23

HDMI_A3P_C_VGA
HDMI_A3N_C_VGA

HDMI_A0P_C_VGA
HDMI_A0N_C_VGA

HDMI_A1P_C_VGA
HDMI_A1N_C_VGA

HDMI_A2P_C_VGA
HDMI_A2N_C_VGA

HDMI_DDC_DATA
HDMI_DDC_CLK

HDMI_HPLUG HDMI_HPD_CHDMI_HPLUG_R

RV253

RV247

499_0402_1%~D

RV248

499_0402_1%~D

12

@

@

+3VS_DELAY

12

499_0402_1%~D

RV249

12

@

RV250

499_0402_1%~D

499_0402_1%~D

RV251

12

12

@

@

0_0402_5%~D

1 2

RV254

RV255

100K_0402_5%~D

@

A A

RV246

499_0402_1%~D

RV252

499_0402_1%~D

499_0402_1%~D

12

12

@

@

@

2

G

12

@

@

12

13

D

QV13

S

2N7002_SOT23

RV193 0_0402_5%~D@

1 2

RV195 0_0402_5%~D@

1 2

RV197 0_0402_5%~D@

1 2

RV199 0_0402_5%~D@

1 2

RV201 0_0402_5%~D@

1 2

RV203 0_0402_5%~D@

1 2

RV205 0_0402_5%~D@

1 2

RV207 0_0402_5%~D@

1 2

RV209 0_0402_5%~D@

1 2

RV211 0_0402_5%~D@

1 2

RV213 0_0402_5%~D@

1 2

2

TMDS_TXCP_R
TMDS_TXCN_R

TMDS_TX0P_R
TMDS_TX0N_R

TMDS_TX1P_R
TMDS_TX1N_R

TMDS_TX2P_R
TMDS_TX2N_R

DDC_DAT_HDMI_R DDC_DAT_HDMI
DDC_CLK_HDMI_R

07/29/2010
HDMI HPD for OPT DGPU output

DGPU_PWROK<16,17,38,55,56>

HDMI_HPD_C

RV194 0_0402_5%~D@

1 2

RV196 0_0402_5%~D@

1 2

RV198 0_0402_5%~D@

1 2

RV200 0_0402_5%~D@

1 2

RV202 0_0402_5%~D@

1 2

RV204 0_0402_5%~D@

1 2

RV206 0_0402_5%~D@

1 2

RV208 0_0402_5%~D@

1 2

RV210 0_0402_5%~D@

1 2

RV212 0_0402_5%~D@

1 2

RV214 0_0402_5%~D@

1 2

RV244

0_0402_5%~D

1

12

2

SN74AHC1G08DCKR_SC70-5

1 2

+3VS

IN1

IN2

0_0402_5%~D

RV245

5

P

G

3

CV507

0.1U_0402_16V7K~D

1 2

UV18

HDMI_HPD

4

O

@

TMDS_TXCP
TMDS_TXCN

TMDS_TX0P
TMDS_TX0N

TMDS_TX1P
TMDS_TX1N

TMDS_TX2P
TMDS_TX2N

DDC_CLK_HDMI

HDMI_HPD <44>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

HDMI_PCH_HPD#<17>

2010/12/01 2011/12/01

Compal Secret Data

RV273

10K_0402_5%~D@

R1950

10K_0402_5%~D

HDMI_OE#

Deciphered Date

+3VS

12

13

D

QV1

S

2N7002_SOT23

+3VS

12

13

D

QV10

S

2N7002_SOT23

2

G

HDMI_R_HPLUG HDM I_HPLUG

1

12

RV9

2

100K_0402_5%~D

2

G

+3VS

RV7

1K_0402_5%~D

DV4
BAV99-7-F_SOT23-3

@

3

1

LV17
MBK1608221YZF_2P

1 2

12

Title

Size Document Number Rev

Custom

Date: Sheet of

1

CV524
220P_0402_50V8J

2

Compal Electronics, Inc.

HDMI

LA-6801P

39 60Monday, December 06, 2010

0.3

5

4

3

2

1

+PEX_VDD_SVDD

+PEX_SVDD33

1

CV527

@

2

1U_0402_6.3V6K~D

200_0402_1%

+PEX_PLLDVDD

RV45

1 2

10K_0402_5%~D

1 2

2.49K_0402_1%

PLACE NEAR BALLS

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

RV82 0_0402_5%~D

@

12

RV276 0_0402_5%~D

12

12

RV44

1 2

PLACE NEAR BALLS

RV46

1

CV62

CV48

2

0.1U_0402_16V7K~D

1

CV54

CV55

2

0.1U_0402_16V7K~D

PLACE NEAR BALLS

12

+1.05VSDGPU

PLACE NEAR BGA

Nvidia recommend 08/11

+NVVDD_SENSE <56>

GND_SENSE <56>

1

CV92

2

4.7U_0603_6.3V6M

UV3A

AW18

PLTRST_VGA#<16>

CLK_PEG_VGA<14>

PEG_GTX_C_HRX_P0<5>

PEG_GTX_C_HRX_N0<5>

D D

C C

B B

PEG_HTX_C_GRX_P0<5>
PEG_HTX_C_GRX_N0<5>

PEG_GTX_C_HRX_P1<5>

PEG_GTX_C_HRX_N1<5>

PEG_HTX_C_GRX_P1<5>
PEG_HTX_C_GRX_N1<5>

PEG_GTX_C_HRX_P2<5>

PEG_GTX_C_HRX_N2<5>

PEG_HTX_C_GRX_P2<5>
PEG_HTX_C_GRX_N2<5>

PEG_GTX_C_HRX_P3<5>

PEG_GTX_C_HRX_N3<5>

PEG_HTX_C_GRX_P3<5>
PEG_HTX_C_GRX_N3<5>

PEG_GTX_C_HRX_P4<5>

PEG_GTX_C_HRX_N4<5>

PEG_HTX_C_GRX_P4<5>
PEG_HTX_C_GRX_N4<5>

PEG_GTX_C_HRX_P5<5>

PEG_GTX_C_HRX_N5<5>

PEG_HTX_C_GRX_P5<5>
PEG_HTX_C_GRX_N5<5>

PEG_GTX_C_HRX_P6<5>

PEG_GTX_C_HRX_N6<5>

PEG_HTX_C_GRX_P6<5>
PEG_HTX_C_GRX_N6<5>

PEG_GTX_C_HRX_P7<5>

PEG_GTX_C_HRX_N7<5>

PEG_HTX_C_GRX_P7<5>
PEG_HTX_C_GRX_N7<5>

PEG_GTX_C_HRX_P8<5>

PEG_GTX_C_HRX_N8<5>

PEG_HTX_C_GRX_P8<5>
PEG_HTX_C_GRX_N8<5>

PEG_GTX_C_HRX_P9<5>

PEG_GTX_C_HRX_N9<5>

PEG_HTX_C_GRX_P9<5>
PEG_HTX_C_GRX_N9<5>

PEG_GTX_C_HRX_P10<5>
PEG_GTX_C_HRX_N10<5>

PEG_HTX_C_GRX_P10<5>
PEG_HTX_C_GRX_N10<5>

PEG_GTX_C_HRX_P11<5>
PEG_GTX_C_HRX_N11<5>

PEG_HTX_C_GRX_P11<5>
PEG_HTX_C_GRX_N11<5>

PEG_GTX_C_HRX_P12<5>
PEG_GTX_C_HRX_N12<5>

PEG_HTX_C_GRX_P12<5>
PEG_HTX_C_GRX_N12<5>

PEG_GTX_C_HRX_P13<5>
PEG_GTX_C_HRX_N13<5>

PEG_HTX_C_GRX_P13<5>
PEG_HTX_C_GRX_N13<5>

PEG_GTX_C_HRX_P14<5>
PEG_GTX_C_HRX_N14<5>

PEG_HTX_C_GRX_P14<5>
PEG_HTX_C_GRX_N14<5>

PEG_GTX_C_HRX_P15<5>
PEG_GTX_C_HRX_N15<5>

PEG_HTX_C_GRX_P15<5>
PEG_HTX_C_GRX_N15<5>

CLK_PEG_VGA#<14>

CV51220nF_0402_16V7K

12

CV52220nF_0402_16V7K

12

CV66220nF_0402_16V7K

12

CV53220nF_0402_16V7K

12

CV60220nF_0402_16V7K

12

CV61220nF_0402_16V7K

12

CV68220nF_0402_16V7K

12

CV69220nF_0402_16V7K

12

CV70220nF_0402_16V7K

12

CV71220nF_0402_16V7K

12

CV72220nF_0402_16V7K

12

CV73220nF_0402_16V7K

12

CV74220nF_0402_16V7K

12

CV76220nF_0402_16V7K

12

CV78220nF_0402_16V7K

12

CV79220nF_0402_16V7K

12

CV80220nF_0402_16V7K

12

CV81220nF_0402_16V7K

12

CV82220nF_0402_16V7K

12

CV83220nF_0402_16V7K

12

CV84220nF_0402_16V7K

12

CV85220nF_0402_16V7K

12

CV86220nF_0402_16V7K

12

CV87220nF_0402_16V7K

12

CV88220nF_0402_16V7K

12

CV89220nF_0402_16V7K

12

CV90220nF_0402_16V7K

12

CV91220nF_0402_16V7K

12

CV95220nF_0402_16V7K

12

CV97220nF_0402_16V7K

12

CV98220nF_0402_16V7K

12

CV99220nF_0402_16V7K

12

12

RV40 0_0402_5%~D

VGA_CLKREQ#_R

PEG_GTX_HRX_P0

PEG_GTX_HRX_N0

PEG_GTX_HRX_P1

PEG_GTX_HRX_N1

PEG_GTX_HRX_P2

PEG_GTX_HRX_N2

PEG_GTX_HRX_P3

PEG_GTX_HRX_N3

PEG_GTX_HRX_P4

PEG_GTX_HRX_N4

PEG_GTX_HRX_P5

PEG_GTX_HRX_N5

PEG_GTX_HRX_P6

PEG_GTX_HRX_N6

PEG_GTX_HRX_P7

PEG_GTX_HRX_N7

PEG_GTX_HRX_P8

PEG_GTX_HRX_N8

PEG_GTX_HRX_P9

PEG_GTX_HRX_N9

PEG_GTX_HRX_P10

PEG_GTX_HRX_N10

PEG_GTX_HRX_P11

PEG_GTX_HRX_N11

PEG_GTX_HRX_P12

PEG_GTX_HRX_N12

PEG_GTX_HRX_P13

PEG_GTX_HRX_N13

PEG_GTX_HRX_P14

PEG_GTX_HRX_N14

PEG_GTX_HRX_P15

PEG_GTX_HRX_N15

AV18

AT19
AU19

AW19

AV19

BB18
BB19

AW20

AY20

BA19
AY19

AW21

AV21

BA21
AY21

AT22
AU22

BB21
BB22

AW22

AV22

BA22
AY22

AY23

AW23

BA24
AY24

AW24

AV24

BB24
BB25

AW25

AV25

BA25
AY25

AW26

AY26

BA27
AY27

AW27

AV27

BB27
BB28

AT28
AU28

BA28
AY28

AW28

AV28

BA30
AY30

AY29

AW29

BB30
BB31

AW30

AV30

BA31
AY31

AW31
AW32

BA33
BB33

AY32
AY33

BB34
BA34

PEX_RST

PEX_CLKREQ

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

PEX_IOVDD

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_PLLVDD

TESTMODE

PEX_TERMP

AR19
AR26
AR27
AR28
AT18

2200mA

AR22
AR23
AR24
AR25
AT20
AT21
AT25
AT27
AU18
AU21
AU25

AR18

AR17

RV42 0_0402_5%~D

AN37

RV43 0_0402_5%~D

AP38

AT24
AU24

AR21

AN3

AU27

1

CV63

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CV67

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CV77

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

PLACE NEAR BGA

1

CV93

2

1U_0402_6.3V6K~D

PLACE NEAR BGA

1

1

CV49

CV64

2

2

4.7U_0603_6.3V6M

1

1

CV57

CV56

2

2

4.7U_0603_6.3V6M

PLACE NEAR BGA

1

1

CV75

CV508

2

2

4.7U_0603_6.3V6M

BLM18PG121SN1D_0603

1

CV94

2

0.1U_0402_16V7K~D

1

CV50

2

10U_0603_6.3V6M~D

1

CV58

2

10U_0603_6.3V6M~D

RV41 0_0402_5%~D

LV5

12

12

1

2

22U_0805_6.3V6M~D

1

2

22U_0805_6.3V6M~D

120mA

CV65

CV59

120mA

+1.05VSDGPU

1U_0402_6.3V6K~D

1

CV96

2

+1.05VSDGPU

+1.05VSDGPU

+3VS_DELAY

N12E-GE_BGA1328~D

+3VS_DELAY

+3VS_DELAY

2

G

A A

PEG_A_CLKRQ#<14>

5

1 3

D

2N7002_SOT23-3

QV3

RV52

0_0402_5%~D

@

S

12

RV47

2.2K_0402_5%~D

VGA_CLKREQ#_R

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

N12E(1/6)_PCIE

LA-6801P

1

of

40 60Monday, December 06, 2010

0.3

5

4

3

2

1

MDA[0..63]<46>

D D

C C

DQMA#[7..0]< 46>

QSA[7..0]<46>

B B

QSA#[7..0]<46>

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

+1.5VSDGPU

12

RV62

1.33K_0402_1%~D

1.33K_0402_1%~D

A A

RV63

Rt

1

CV106

0.01U_0402_25V7K~D

2

@

+FB_VREF

12

@

Rb

@

P39

FBA_D0

R37

FBA_D1

R39

FBA_D2

R38

FBA_D3

T38

FBA_D4

T39

FBA_D5

U39

FBA_D6

V39

FBA_D7

M37

FBA_D8

N39

FBA_D9

M36

FBA_D10

M38

FBA_D11

K38

FBA_D12

K37

FBA_D13

L36

FBA_D14

K36

FBA_D15

K40

FBA_D16

K41

FBA_D17

J42

FBA_D18

K42

FBA_D19

M42

FBA_D20

N40

FBA_D21

N41

FBA_D22

N42

FBA_D23

V41

FBA_D24

U40

FBA_D25

V42

FBA_D26

V40

FBA_D27

R42

FBA_D28

R41

FBA_D29

P40

FBA_D30

R40

FBA_D31

AH39

FBA_D32

AH36

FBA_D33

AH38

FBA_D34

AH37

FBA_D35

AG39

FBA_D36

AF39

FBA_D37

AE39

FBA_D38

AE38

FBA_D39

AL39

FBA_D40

AL37

FBA_D41

AL36

FBA_D42

AL38

FBA_D43

AP39

FBA_D44

AR40

FBA_D45

AT41

FBA_D46

AT40

FBA_D47

AP40

FBA_D48

AP42

FBA_D49

AT42

FBA_D50

AP41

FBA_D51

AM40

FBA_D52

AL40

FBA_D53

AL42

FBA_D54

AL41

FBA_D55

AG41

FBA_D56

AG40

FBA_D57

AF40

FBA_D58

AG42

FBA_D59

AJ40

FBA_D60

AK41

FBA_D61

AK40

FBA_D62

AK42

FBA_D63

R36

FBA_DQM0

K39

FBA_DQM1

M41

FBA_DQM2

T40

FBA_DQM3

AE37

FBA_DQM4

AN38

FBA_DQM5

AN40

FBA_DQM6

AH40

FBA_DQM7

T37

FBA_DQS_WP0

M39

FBA_DQS_WP1

M40

FBA_DQS_WP2

T42

FBA_DQS_WP3

AG37

FBA_DQS_WP4

AN39

FBA_DQS_WP5

AN42

FBA_DQS_WP6

AH41

FBA_DQS_WP7

T36

FBA_DQS_RN0

L39

FBA_DQS_RN1

L40

FBA_DQS_RN2

T41

FBA_DQS_RN3

AG38

FBA_DQS_RN4

AM39

FBA_DQS_RN5

AN41

FBA_DQS_RN6

AH42

FBA_DQS_RN7

V5

FB_VREF

N12E-GE_BGA1328~D

UV3B

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_DEBUG0
FBA_DEBUG1

FBA_WCK01
FBA_WCK01
FBA_WCK23
FBA_WCK23
FBA_WCK45
FBA_WCK45
FBA_WCK67
FBA_WCK67

FBA_PLL_AVDD

MAA2 MAA3 MAA5

12

RV50
10K_0402_5%~D

12

RV55
10K_0402_5%~D

MAA0

W36
W37

MAA2

W38

MAA3

W39

MAA4

W40

MAA5

W42

MAA6

W41

MAA7

Y40

MAA8

Y38

MAA9

AA39

MAA10

AA38

MAA11

AA37

MAA12

AA40

MAA13

AA41

MAA14

AA42

MAA15

AB40

MAA16

AD38
AD39

MAA18

AC39

MAA19

AB38

MAA20

AE40

MAA21

AE42

MAA22

AE41

MAA23

AD42

MAA24

AB39

MAA25

AB37

MAA26

AC36

MAA27

AB36

MAA28

AD40

MAA29

AC41

MAA30

AB41
AB42

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

Y36
AE36

V37
V36
AD36
AD37

N38
N37
N36
P36
AK37
AK38
AK36
AJ36

1 2

RV58 60.4_0402_1%~D

1 2

RV60 60.4_0402_1%~D

CLKA0
CLKA0#
CLKA1
CLKA1#

+FB_PLLAVDD

AA35

12

RV51
10K_0402_5%~D

MAA18MAA19

12

RV56
10K_0402_5%~D

12

RV54
10K_0402_5%~D

MDB[0..63]<47>

MAA[0..31] <46>

DQMB#[7..0]< 47>

+1.5VSDGPU

QSB[7..0]<47>

CLKA0 <46>
CLKA0# <46>
CLKA1 <46>
CLKA1# <46>

QSB#[7..0]<47>

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

+1.05VSDGPU

BLM18PG330SN1D_0603

1

CV102

2

10U_0603_6.3V6M~D

LV6

12

1

@

CV105

2

1U_0402_6.3V6K~D

300mA

1

1

CV100

CV101

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

UV3C

D22

FBB_D0

D24

FBB_D1

E22

FBB_D2

D23

FBB_D3

G24

FBB_D4

G25

FBB_D5

E25

FBB_D6

F25

FBB_D7

D20

FBB_D8

E21

FBB_D9

D21

FBB_D10

F21

FBB_D11

G18

FBB_D12

F18

FBB_D13

D18

FBB_D14

E18

FBB_D15

A18

FBB_D16

A19

FBB_D17

B18

FBB_D18

C20

FBB_D19

B21

FBB_D20

A21

FBB_D21

A22

FBB_D22

C22

FBB_D23

B27

FBB_D24

C25

FBB_D25

A27

FBB_D26

C26

FBB_D27

B24

FBB_D28

C24

FBB_D29

B22

FBB_D30

C23

FBB_D31

F35

FBB_D32

E37

FBB_D33

C38

FBB_D34

D37

FBB_D35

E34

FBB_D36

C35

FBB_D37

C34

FBB_D38

D34

FBB_D39

H37

FBB_D40

F38

FBB_D41

E40

FBB_D42

F39

FBB_D43

H40

FBB_D44

J39

FBB_D45

J38

FBB_D46

J40

FBB_D47

G41

FBB_D48

G42

FBB_D49

J41

FBB_D50

G40

FBB_D51

D41

FBB_D52

D42

FBB_D53

C41

FBB_D54

D40

FBB_D55

B36

FBB_D56

C36

FBB_D57

A36

FBB_D58

A37

FBB_D59

C39

FBB_D60

A39

FBB_D61

C40

FBB_D62

B40

FBB_D63

G23

FBB_DQM0

F19

FBB_DQM1

C21

FBB_DQM2

B25

FBB_DQM3

E36

FBB_DQM4

H39

FBB_DQM5

F42

FBB_DQM6

B39

FBB_DQM7

F24

FBB_DQS_WP0

E19

FBB_DQS_WP1

C19

FBB_DQS_WP2

A25

FBB_DQS_WP3

D36

FBB_DQS_WP4

G38

FBB_DQS_WP5

F41

FBB_DQS_WP6

C37

FBB_DQS_WP7

E24

FBB_DQS_RN0

D19

FBB_DQS_RN1

B19

FBB_DQS_RN2

A24

FBB_DQS_RN3

D35

FBB_DQS_RN4

G39

FBB_DQS_RN5

F40

FBB_DQS_RN6

B37

FBB_DQS_RN7

N12E-GE_BGA1328~D

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_DEBUG0
FBB_DEBUG1

FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1

FBB_WCK01
FBB_WCK01
FBB_WCK23
FBB_WCK23
FBB_WCK45
FBB_WCK45
FBB_WCK67
FBB_WCK67

FBB_PLL_AVDD

MAB0

F27
G28

MAB2

G29

MAB3

E28

MAB4

C27

MAB5

A28

MAB6

B28

MAB7

C28

MAB8

D28

MAB9

F28

MAB10

D30

MAB11

E30

MAB12

C29

MAB13

B30

MAB14

A30

MAB15

C30

MAB16

D33
D32

MAB18

F31

MAB19

D31

MAB20

B34

MAB21

A34

MAB22

C33

MAB23

A33

MAB24

E31

MAB25

G32

MAB26

F30

MAB27

E29

MAB28

B32

MAB29

C31

MAB30

B31
A31

G27

RV59 60.4_0402_1%~D

E33

RV61 60.4_0402_1%~D

CLKB0

E27

CLKB0#

D27

CLKB1

G33

CLKB1#

F33

G22
F22
G20
G21
G34
G35
J36
H36

+FB_PLLAVDD

H30

12

RV48
10K_0402_5%~D

12

RV53
10K_0402_5%~D

MAB19

1 2
1 2

1

CV104

2

0.1U_0402_16V7K~D

MAB3MAB2

MAB18MAB5

12

12

12

RV64
10K_0402_5%~D

MAB[0..31] <47>

+1.5VSDGPU

CLKB0 <47>
CLKB0# <47>
CLKB1 <47>
CLKB1# <47>

RV49
10K_0402_5%~D

RV57
10K_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

N12E(2/6)_MemoryA/B

LA-6801P

1

41 60Monday, December 06, 2010

0.3

5

4

3

2

1

MAC3MAC2

MAC19MAC18

MAC[0..31] <48>

12

RV68
10K_0402_5%~D

12

RV67
10K_0402_5%~D

MAC5

12

RV65
10K_0402_5%~D

12

RV66
10K_0402_5%~D

12

RV81
10K_0402_5%~D

CLKC0 <48>
CLKC0# <48>
CLKC1 <48>
CLKC1# <48>

+1.5VSDGPU

MDC[0..63]<48>

D D

C C

DQMC#[7..0]<48>

QSC[7..0]<48>

B B

QSC#[7..0]<48>

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

QSC0
QSC1
QSC2
QSC3
QSC4
QSC5
QSC6
QSC7

QSC#0
QSC#1
QSC#2
QSC#3
QSC#4
QSC#5
QSC#6
QSC#7

M6
N4
M7
M5

K5
K6
L7
K7

P4
R6
R4
R5

T5

T4
U4

T6
U3

T1

V3

T2
R3

P3
N1
N2

J2

K3

J3

J1
M3
M2
N3
M1

F12
D13

G12

E12
E10

F10
G11
G10

D14

F15

D15

E15

E16

D16

D17

F16

C17

A16

C18

B16

C15

C14

A13

B13

B9

C10

C9

A9
C12
B12
C13
A12

K4

R7

T3

L3
D10

G15

C16
C11

L4

U7
R1

K1
D11

G17

A15
B10

M4

T7

R2

K2
D12

G16

B15
A10

UV3D

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

GND_REF
GND_REF

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

FBC_DEBUG0
FBC_DEBUG1

FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1

FBC_WCK01
FBC_WCK01
FBC_WCK23
FBC_WCK23
FBC_WCK45
FBC_WCK45
FBC_WCK67
FBC_WCK67

C3
E5

MAC0

H5
G4

MAC2

G5

MAC3

F4

MAC4

G2

MAC5

G1

MAC6

G3

MAC7

F1

MAC8

J5

MAC9

E3

MAC10

H6

MAC11

C2

MAC12

F3

MAC13

E2

MAC14

D1

MAC15

D2

MAC16

E8
D7

MAC18

E7

MAC19

D6

MAC20

B7

MAC21

A7

MAC22

C7

MAC23

A6

MAC24

E9

MAC25

C5

MAC26

F8

MAC27

B3

MAC28

C6

MAC29

B5

MAC30

A4
B4

J6

1 2

RV72 60.4_0402_1%~D

F9

1 2

RV73 60.4_0402_1%~D

CLKB0

H3

CLKB0#

H4

CLKB1

C8

CLKB1#

D8

P7
N7
N5
N6
G14
G13
E13
F13

A2

FBVDDQ

A3

FBVDDQ

AA36

FBVDDQ

AB35

FBVDDQ

AC38

FBVDDQ

AD35

FBVDDQ

AD41

FBVDDQ

AE35

FBVDDQ

AF35

FBVDDQ

AF36

FBVDDQ

AG35

FBVDDQ

AG36

FBVDDQ

AH35

FBVDDQ

AK35

FBVDDQ

AL35

FBVDDQ

B1

FBVDDQ

B2

FBVDDQ

B29

FBVDDQ

B33

FBVDDQ

B6

FBVDDQ

C1

FBVDDQ

C4

FBVDDQ

D26

FBVDDQ

D3

FBVDDQ

D4

FBVDDQ

D5

FBVDDQ

D9

FBVDDQ

E32

FBVDDQ

E4

FBVDDQ

E6

FBVDDQ

F2

FBVDDQ

F5

FBVDDQ

F6

FBVDDQ

F7

FBVDDQ

G19

FBVDDQ

G30

FBVDDQ

G6

FBVDDQ

G8

FBVDDQ

G9

FBVDDQ

H10

FBVDDQ

H12

FBVDDQ

H13

FBVDDQ

H15

FBVDDQ

H16

FBVDDQ

H18

FBVDDQ

H19

FBVDDQ

N12E-GE_BGA1328~D

UV3E

FB_CALTERM_GND

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

FBVDDQ_PROBE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

+1.5VSDGPU

+FB_PLLAVDD

FBC_PLL_AVDD

N12E-GE_BGA1328~D

H8

1

CV142

2

0.1U_0402_16V7K~D

+1.5VSDGPU+1.5VSDGPU

H22
H24
H25
H26
H27
H28
H29
H31
H32
H33
H34
H7
H9
J35
J4
J7
J8
K35
K8
M35
M8
N35
N8
R35
R8
T35
T8
U35
V35
V38
W35
Y35
H21
Y41

V8

1 2

V6

RV69 40.2_0402_1%~D

1 2

V7

RV70 40.2_0402_1%~D

1 2

V4

RV71 60.4_0402_1%~D

1

CV125

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV129

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV151

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

1

CV107

CV110

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV113

CV114

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV120

CV119

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

T205 PAD~D@

+1.5VSDGPU

1

CV126

2

1

CV130

2

1

CV152

2

1

1

CV128

CV127

2

2

0.1U_0402_16V7K~D

22U_0805_6.3V6M~D

1

1

CV131

2

0.1U_0402_16V7K~D

1

CV153

2

0.1U_0402_16V7K~D

1

CV132

CV133

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CV154

2

22U_0805_6.3V6M~D

1

CV108

CV111

2

2

0.1U_0402_16V7K~D

1

CV115

2

0.1U_0402_16V7K~D

1

CV121

2

0.1U_0402_16V7K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CV116

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CV122

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

1

2

CV112

CV109

2

4.7U_0603_6.3V6M

1

1

2

CV117

CV118

2

4.7U_0603_6.3V6M

1

1

CV123

2

CV124

2

4.7U_0603_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

N12E(3/6)_MemoryC

LA-6801P

1

42 60Monday, December 06, 2010

0.3

5

NVVDD DCPLNG Follows GF106 NVVDD Decap Guidelines DT

UV3F

AA12

VDD

AA14

VDD

AA16

VDD

AA18

VDD

AA21

VDD

AA23

VDD

AA25

VDD

AA27

VDD

AB11

VDD

AB13

VDD

AB15

D D

C C

B B

A A

VDD

AB17

VDD

AB19

VDD

AB20

VDD

AB22

VDD

AB24

VDD

AB26

VDD

AB28

VDD

AC12

VDD

AC14

VDD

AC16

VDD

AC18

VDD

AC21

VDD

AC23

VDD

AC25

VDD

AC27

VDD

AD11

VDD

AD13

VDD

AD15

VDD

AD17

VDD

AD19

VDD

AD20

VDD

AD22

VDD

AD24

VDD

AD26

VDD

AD28

VDD

AE12

VDD

AE14

VDD

AE16

VDD

AE18

VDD

AE21

VDD

AE23

VDD

AE25

VDD

AE27

VDD

AF11

VDD

AF13

VDD

AF15

VDD

AF17

VDD

AF19

VDD

AF20

VDD

AF22

VDD

AF24

VDD

AF26

VDD

AF28

VDD

AG12

VDD

AG14

VDD

AG16

VDD

AG18

VDD

AG21

VDD

AG23

VDD

AG25

VDD

AG27

VDD

AH11

VDD

AH13

VDD

AH15

VDD

AH17

VDD

AH19

VDD

AH20

VDD

AH22

VDD

AH24

VDD

AH26

VDD

AH28

VDD

AM35

VDD

AN35

VDD

AN36

VDD

AP35

VDD

AP36

VDD

AP37

VDD

AR29

VDD

AR30

VDD

AR31

VDD

AR32

VDD

AR33

VDD

AR34

VDD

AR35

VDD

AR36

VDD

AR37

VDD

AR38

VDD

AT30

VDD

AT31

VDD

AT32

VDD

AT33

VDD

AT34

VDD

AT35

VDD

AT36

VDD

AT37

VDD

AT38

VDD

AT39

VDD

AU30

VDD

AU31

VDD

AU33

VDD

AU34

VDD

AU35

VDD

AU36

VDD

AU37

VDD

AU38

VDD

AU39

VDD

AU40

VDD

AU41

VDD

AU42

VDD

AV32

VDD

AV33

VDD

AV34

VDD

AV35

VDD

AV36

VDD

AV37

VDD

AV38

VDD

AV39

VDD

AV40

VDD

AV41

VDD

AW33

VDD

AW34

VDD

AW35

VDD

N12E-GE_BGA1328~D

+VGA_CORE+VGA_CORE

AW36

VDD

AW37

VDD

AW38

VDD

AW39

VDD

AW40

VDD

AW41

VDD

AW42

VDD

AY34

VDD

AY35

VDD

AY36

VDD

AY37

VDD

AY38

VDD

AY39

VDD

AY40

VDD

AY41

VDD

AY42

VDD

BA35

VDD

BA36

VDD

BA37

VDD

BA38

VDD

BA39

VDD

BA40

VDD

BA41

VDD

BA42

VDD

BB36

VDD

BB37

VDD

BB39

VDD

BB40

VDD

BB41

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

L19

VDD

L20

VDD

L22

VDD

L24

VDD

L26

VDD

L28

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

M21

VDD

M23

VDD

M25

VDD

M27

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

N19

VDD

N20

VDD

N22

VDD

N24

VDD

N26

VDD

N28

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

P21

VDD

P23

VDD

P25

VDD

P27

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

R19

VDD

R20

VDD

R22

VDD

R24

VDD

R26

VDD

R28

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

T21

VDD

T23

VDD

T25

VDD

T27

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

U19

VDD

U20

VDD

U22

VDD

U24

VDD

U26

VDD

U28

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

V21

VDD

V23

VDD

V25

VDD

V27

VDD

W11

VDD

W13

VDD

W15

VDD

W17

VDD

W19

VDD

W20

VDD

W22

VDD

W24

VDD

W26

VDD

W28

VDD

Y11

VDD

Y13

VDD

Y15

VDD

Y17

VDD

Y19

VDD

Y20

VDD

Y22

VDD

Y24

VDD

Y26

VDD

Y28

VDD

+VGA_CORE

DGPU_PWR_EN<16,33,55,56>

0.1uF - X5R 0402 x 16 under chip

1

CV190

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV181

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV188

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

uF - X5R 0402 x 15 under chip

1

CV212

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CV200

2

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

1

CV219

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV236

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CV226

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1 2

RV227 1K_0402_5%~D

CV499

1

CV209

2

1

CV182

2

1

CV203

2

1

CV214

2

1

CV201

2

1

CV222

2

1

CV243

2

1

CV227

2

1

2

5

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

1U_0402_6.3V6K~D

1

2

4.7U_0603_6.3V6M

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

2

0.1U_0402_16V7K~D

4

1

CV185

CV194

2

0.1U_0402_16V7K~D

1

CV183

CV186

2

0.1U_0402_16V7K~D

1

CV215

CV189

2

0.1U_0402_16V7K~D

SPARE/TEST

1

CV196

CV195

2

1U_0402_6.3V6K~D

1

CV208

CV202

2

10U_0805_6.3V6M

1

CV218

CV224

2

0.1U_0402_16V7K~D

1

CV245

CV235

2

0.1U_0402_16V7K~D

1

CV228

CV229

2

0.1U_0402_16V7K~D

+3VALW

RV225
100K_0402_5%~D

1 2

1 2

RV278 1K_0402_5%~D

61

QV16A
DMN66D0LDW-7_SOT363-6~D

4

1

CV216

2

0.1U_0402_16V7K~D

1

CV180

2

0.1U_0402_16V7K~D

1

CV191

2

0.1U_0402_16V7K~D

1

CV210

2

1U_0402_6.3V6K~D

1

CV204

2

10U_0805_6.3V6M

1

CV221

2

0.1U_0402_16V7K~D

1

CV242

2

0.1U_0402_16V7K~D

1

CV230

2

0.1U_0402_16V7K~D

1

1

CV179

CV187

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV213

CV184

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV192

CV211

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV198

CV197

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

+

CV205

CV206

2

2

22U_0805_6.3V6M~D

470U_D2E_2.5VM_R9M~D

1

1

CV220

CV223

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV241

CV244

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

1

CV232

CV231

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+3VS +3VS_DELAY

@

1 2

RV277 0_0805_5%~D

QV5 AO3419L_SOT23-3

123

1

2

DGS

CV528

10U_0805_6.3V6M

3VS_Dgate

0.1U_0402_16V7K~D

1

CV513

2

3

UV3G

AJ39

NC

AK39

NC

AT9

NC

AU12

NC

D25

NC

F34

NC

J37

NC

N12E-GE_BGA1328~D

1

CV193

2

0.1U_0402_16V7K~D

1

CV199

2

1U_0402_6.3V6K~D

1

+

CV207

2

470U_D2E_2.5VM_R9M~D

1

CV217

2

0.1U_0402_16V7K~D

1

CV225

2

0.1U_0402_16V7K~D

1

CV233

2

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

AA8
AB8
AC8
AD8
AE8
AF8
Y8
AR16

A40
AA15
AA17
AA19
AA20
AA22
AA24
AA26
AA28
AB12
AB14

A41
AB16
AB18
AB21
AB23
AB25
AB27

AC11
AC13
AC15
AC17

AA11

AC19

AC2

AC20
AC22
AC24
AC26
AC28
AC35
AC40

AC5
AA13

AC7

AD12
AD14
AD16
AD18
AD21
AD23
AD25
AD27

AE11
AE13
AE15
AE17
AE19
AE20
AE22
AE24
AE26
AE28
AF12
AF14
AF16
AF18

AF2
AF21
AF23
AF25
AF27
AF38
AF41

AF5

AF7

AG11
AG13
AG15
AG17

Y7

N12E-GE_BGA1328~D

0.4mm

1

1

CV170

CV171

2

2

0.1U_0402_16V7K~D

UV3I

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

AG19

GND

AG20

GND

AG22

GND

AG24

GND

AG26

GND

AG28

GND

AH12

GND

AH14

GND

AH16

GND

AH18

GND

AH21

GND

AH23

GND

AH25

GND

AH27

GND

AJ2

GND

AJ35

GND

AJ38

GND

AJ41

GND

AM2

GND

AM36

GND

AM38

GND

AM41

GND

AR2

GND

AR20

GND

AR39

GND

AR41

GND

AT11

GND

AT14

GND

AT17

GND

AT23

GND

AT26

GND

AT29

GND

AT5

GND

AT8

GND

AV11

GND

AV14

GND

AV17

GND

AV2

GND

AV20

GND

AV23

GND

AV26

GND

AV29

GND

AV31

GND

AV5

GND

AV8

GND

AY1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

B35

GND

B38

GND

B41

GND

B42

GND

B8

GND

BA1

GND

BA11

GND

BA14

GND

BA17

GND

BA2

GND

BA20

GND

BA23

GND

BA26

GND

BA29

GND

BA32

GND

BA5

GND

BA8

GND

BB2

GND

Y5

GND

1

1

CV172

2

2

0.1U_0402_16V7K~D

PLACE NEAR BALLS

2

CV173

1

CV174

2

0.1U_0402_16V7K~D

BB3
C32
C42
D29
D38
D39

E11
E14
E17
E20
E23
E26
E35
E38
E39
E41
F36

F37
G26
G31
G36
G37

G7
H11
H14
H17

H2
H20
H23
H35
H38
H41

L12
L14
L16
L18

L2
L21
L23
L25
L27
L35
L38
L41

L5

L8

M11
M13
M15
M17
M19
M20
M22
M24
M26
M28
N12
N14
N16
N18
N21
N23
N25
N27

P11
P13
P15
P17
P19

P2

AT6

N12E-GE_BGA1328~D

+3VS_DELAY_VDD34

UV3J

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1

+3VS_DELAY

12

CV176

1

CV177

2

4.7U_0603_6.3V6M

1

1

CV175

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

P20

GND

P22

GND

P24

GND

P26

GND

P28

GND

P35

GND

P38

GND

P41

GND

P5

GND

P8

GND

R12

GND

R14

GND

R16

GND

R18

GND

R21

GND

R23

GND

R25

GND

R27

GND

T11

GND

T13

GND

T15

GND

T17

GND

T19

GND

T20

GND

T22

GND

T24

GND

T26

GND

T28

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U21

GND

U23

GND

U25

GND

U27

GND

U36

GND

U38

GND

U41

GND

U5

GND

U8

GND

V11

GND

V13

GND

V15

GND

V17

GND

V19

GND

V20

GND

V22

GND

V24

GND

V26

GND

V28

GND

W12

GND

W14

GND

W16

GND

W18

GND

W21

GND

W23

GND

W25

GND

W27

GND

Y12

GND

Y14

GND

Y16

GND

Y18

GND

Y2

GND

Y21

GND

Y23

GND

Y25

GND

Y27

GND

Y39

GND

AT7

GND

1

CV178

2

4.7U_0603_6.3V6M

PLACE NEAR BGA

RV74 0_0402_5%~D

0.1U_0402_16V7K~D

+IFPE_IOVDD

+IFPEF_PLLVDD

+IFPF_IOVDD

470_0603_5%

1

RV226

CV529

2

10U_0805_6.3V6M

DMN66D0LDW-7_SOT363-6~D

QV16B

1 2

34

3VS_Dgate

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

UV3H

AJ4

PD_AJ4

AJ5

PD_AJ5

AJ7

PD_AJ7

AK4

PD_AK4

AK5

PD_AK5

AK6

PD_AK6

AK7

PD_AK7

AL4

PD_AL4

AL5

PD_AL5

AL6

PD_AL6

AL7

PD_AL7

N12E-GE_BGA1328~D

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

AM4

PD_AM4

AM5

PD_AM5

AM7

PD_AM7

AN4

PD_AN4

AN5

PD_AN5

AN6

PD_AN6

AN7

PD_AN7

AP5

PD_AP5

AP6

PD_AP6

AP7

PD_AP7

AP8

PD_AP8

AR6

PD_AR6

AR7

PD_AR7

AR8

PD_AR8

Title

Size Document Number Rev

C

Date: Sheet of

+IFPC_IOVDD

Compal Electronics, Inc.

N12E(4/6)_Power/GND

LA-6801P

1

+IFPC_PLLVDD

43 60Monday, December 06, 2010

0.3

5

UV3K

IFPAB_RSET

@

12

RV75 1K_0402_1%~D

RV221 10K_0402_5%~D

D D

RV222 10K_0402_5%~D

AR15

IFPAB_RSET

AT12

12

12

AR11

AR12

IFPAB_PLLVDD

IFPA_IOVDD

IFPB_IOVDD

N12E-GE_BGA1328~D

C C

IFPC_RSET

12

RV77 1K_0402_1%~D

+IFPC_PLLVDD

+IFPC_IOVDD

AU8

AN8

AM8

UV3L

IFPC_RSET

IFPC_PLLVDD

IFPC

IFPC_IOVDD

DVI/HDMI DP

I2CW_SDA
I2CW_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

N12E-GE_BGA1328~D

UV3M

IFPD_RSET

@

12

B B

RV79 1K_0402_1%~D

12

RV223 10K_0402_5%~D

12

RV224 10K_0402_5%~D

AU9

IFPD_RSET

AR10

IFPD_PLLVDD

AR9

IFPD_IOVDD

N12E-GE_BGA1328~D

IFPD

DVI/HDMI

I2CW_SDA
I2CW_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

IFPA_TXC
IFPA_TXC

IFPA_TXD0
IFPA_TXD0

IFPA_TXD1
IFPA_TXD1

IFPA_TXD2
IFPA_TXD2

IFPA_TXD3
IFPA_TXD3

IFPB_TXC
IFPB_TXC

IFPB_TXD4
IFPB_TXD4

IFPB_TXD5
IFPB_TXD5

IFPB_TXD6
IFPB_TXD6

IFPB_TXD7
IFPB_TXD7

IFPC_AUX
IFPC_AUX

DP

IFPD_AUX
IFPD_AUX

GPIO0

IFPC_L3
IFPC_L3

IFPC_L2
IFPC_L2

IFPC_L1
IFPC_L1

IFPC_L0
IFPC_L0

GPIO1

IFPD_L3
IFPD_L3

IFPD_L2
IFPD_L2

IFPD_L1
IFPD_L1

IFPD_L0
IFPD_L0

GPIO19

4

AW13
AV13

AT10
AU10

AW10

+3VS_DELAY

AV10

AW11
AY11

AW12
AV12

AY18
BA18

BA13
AY13

BA15
AY15

BB15
BB16

AY16
BA16

AB4

AU6
AV6

AU7
AV7

AW6
AW7

AY8
AW8

AW9
AV9

AD2

AV3
AW3

BB9
BB10

BA10
AY10

BA12
AY12

BB12
BB13

AG5

1U_0402_6.3V6K~D

+1.05VSDGPU

1U_0402_6.3V6K~D

+1.05VSDGPU

1U_0402_6.3V6K~D

RV130

100K_0402_5%~D

RV274

BLM18PG331SN1D_2P~D

1 2

LV8

1

CV510

@

2

BLM18PG221SN1D_2P~D

1 2

LV12

1

CV257

@

2

BLM18PG221SN1D_2P~D

1 2

LV13

1

CV262

@

2

HDMI_DDC_DATA <39>
HDMI_DDC_CLK <39>

HDMI_A3N_VGA <39>
HDMI_A3P_VGA <39>

HDMI_A2N_VGA <39>
HDMI_A2P_VGA <39>

HDMI_A1N_VGA <39>
HDMI_A1P_VGA <39>

HDMI_A0N_VGA <39>
HDMI_A0P_VGA <39>

HDMI_HPD <39>

12

+3VS_DELAY

BLM18PG331SN1D_2P~D

1

CV405

@

2

1U_0402_6.3V6K~D

+1.05VSDGPU

BLM18PG221SN1D_2P~D

1

CV410

@

2

12

1U_0402_6.3V6K~D

1

2

4.7U_0603_6.3V6M

1

2

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

1 2

LV14

1 2

LV15

CV238

CV258

CV263

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

440mA

1

2

1U_0402_6.3V6K~D

285mA

1

2

4.7U_0603_6.3V6M

285mA

1

2

4.7U_0603_6.3V6M

1

CV406

2

1

CV411

2

CV239

CV259

CV264

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

220mA

1

CV407

2

4.7U_0603_6.3V6M

285mA

1

CV412

2

4.7U_0603_6.3V6M

CV509

+IFPE_IOVDD

CV403

+IFPF_IOVDD

CV404

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

3

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

CV408

2

1

CV413

2

+IFPEF_PLLVDD

CV240

+IFPE_IOVDD

CV261

+IFPF_IOVDD

CV266

0.1U_0402_16V7K~D

+IFPC_IOVDD

0.1U_0402_16V7K~D

1

CV234

2

0.1U_0402_16V7K~D

+IFPC_PLLVDD

1

CV409

2

+IFPC_IOVDD

1

CV414

2

+IFPEF_PLLVDD

+IFPC_PLLVDD

1

CV511

2

0.1U_0402_16V7K~D

12

RV761K_0402_1%~D

+IFPE_IOVDD

+IFPF_IOVDD

UV3N

AK8

IFPEF_PLLVDD

AU5

IFPEF_RSET

AJ8

IFPE_IOVDD

AL8

IFPF_IOVDD

N12E-GE_BGA1328~D

12

RV7810K_0402_5%~D

12

RV80 10K_0402_5%~D

2

IFPE

IFPF

AR14

DACA_VDD

AT15

DACA_VREF

AT16

DACA_RSET

N12E-GE_BGA1328~D

AR13

DACB_VDD

AU13

DACB_VREF

AT13

DACB_RSET

N12E-GE_BGA1328~D

I2CY_SDA
I2CY_SCL

TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPD_E HPD_E

TXD3
TXD3

TXD4
TXD4

TXD5
TXD5

UV3O

UV3P

I2CY_SDA
I2CY_SCL

TXCTXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

I2CZ_SDA
I2CZ_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPD_F

DPDVI-DL DVI-SL/HDMI

IFPE_AUX
IFPE_AUX

IFPE_L3
IFPE_L3

IFPE_L2
IFPE_L2

IFPE_L1
IFPE_L1

IFPE_L0
IFPE_L0

GPIO15

IFPF_AUX
IFPF_AUX

IFPF_L3
IFPF_L3

IFPF_L2
IFPF_L2

IFPF_L1
IFPF_L1

IFPF_L0
IFPF_L0

GPIO21

I2CA_SCL
I2CA_SDA

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

I2CB_SCL
I2CB_SDA

DACB_HSYNC

DACB_VSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

AY2
BA3

BA4
BB4

AY3
AY4

AW4
AV4

AY5
AW5

AB5

AW1
AW2

AY6
BA6

BB6
BB7

AY7
BA7

BA9
AY9

AE4

AK2
AK1

AU16
AV16

AW17

AY17

AW16

AH2
AH3

AV15
AU15

AW15

AY14

AW14

1

DP_HPD

I2CA_SCL
I2CA_SDA

I2CB_SCL
I2CB_SDA

VGA_DPD_AUXN/DDC <37>
VGA_DPD_AUXP/DDC <37>

VGA_DPD_N3 <37>
VGA_DPD_P3 <37>

VGA_DPD_N2 <37>
VGA_DPD_P2 <37>

VGA_DPD_N1 <37>
VGA_DPD_P1 <37>

VGA_DPD_N0 <37>
VGA_DPD_P0 <37>

VGA_DMC_HPD <37>

12

RV127

100K_0402_5%~D

DISP_AUXN <38>
DISP_AUXP <38>

DISP_A3N_VGA <38>
DISP_A3P_VGA <38>

DISP_A2N_VGA <38>
DISP_A2P_VGA <38>

DISP_A1N_VGA <38>
DISP_A1P_VGA <38>

DISP_A0N_VGA <38>
DISP_A0P_VGA <38>

DP_HPD <38>

12

RV129

100K_0402_5%~D

I2CB_SCL <58>

I2CB_SDA <58>

+3VS_DELAY

100K_0402_5%~D

RV256 2.2K_0402_5%~D

RV257 2.2K_0402_5%~D

A A

RV258 2.2K_0402_5%~D

RV259 2.2K_0402_5%~D

1 2

1 2

1 2

1 2

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

N12E(5/6)_DP/HDMI

LA-6801P

1

44 60Monday, December 06, 2010

0.3

5

4

3

2

1

+1.05VSDGPU

LV16

1 2

BLM18PG330SN1D_0603

1

@

UV3Q

D D

AA7

MIOACAL_PD_VDDQ

AB7

MIOACAL_PU_GND

W8

MIOA_VREF

0_0402_5%~D

RV279

12

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

V1
V2
W1
W2
W3
Y3
AA2
AA1
AA3
AB1
AB2
AB3

CV512

2

10U_0603_6.3V6M~D

@

W5

MIOA_CTL3

W7

MIOA_HSYNC

W6

MIOA_VSYNC

W4

MIOA_DE

MIOA_CLKIN

Y4
AA4
AA5

10K_0402_5%~D

12

RV260

MIOA_CLKOUT
MIOA_CLKOUT

N12E-GE_BGA1328~D

C C

UV3R

AH6

BBIASN_NC

AH5

BBIASP_NC

STRAP0

AT1

STRAP1
STRAP2

1 2

RV103 40.2K_0402_1%~D

1 2

RV104 40.2K_0402_1%~D

B B

STRAP0

AT2

STRAP1

AT3

STRAP2

AP4

MULTISTRAP_REF0_GND

AR5

MULTISTRAP_REF1_GND

N12E-GE_BGA1328~D

ROM_CS

ROM_SI

ROM_SO

ROM_SCLK

I2CH_SCL
I2CH_SDA

BUFRST

PGOOD_OUT_NC

ROM_CS#

AR3

ROM_SI

AP1

ROM_SO

AP3
AP2

I2CH_SCL

AG2

I2CH_SDA

AG1

AG7

AH4

10K_0402_5%~D

AJ3

CEC

RV100

10K_0402_5%~D @

1 2

ROM_SCLK

1

CV531
68P_0402_50V8J~D

2

RV261

1 2

+3VS_DELAY

+3VS_DELAY

+3VS_DELAY

VGA Thermal Sensor ADM1032ARMZ

+3VS_DELAY

Closed to GPU

GPU_THERMAL_D+ EC_SMB_DA2_PX

GPU_THERMAL_D-

A A

2200P_0402_50V7K

1 2

RV110 4.7K_0402_5%~D

0.1U_0402_16V7K~D

CV276

1 2

+3VS_DELAY

5

+3VS_DELAY

CV275

2

1

UV4

1

2

3

ADM1032ARMZ-2REEL_MSOP8

Address:100_1101

VDD

SCLK

D+

SDATA

ALERT#

D-

THERM#4GND

2.2K_0402_5%~D

RV109

4.7K_0402_5%~D

1 2

8

7

6

5

EC_SMB_CK2_PX

THM_ALERT#

1

CV533
10P_0402_50V8J~D

2

EC_SMB_CK2_PX

EC_SMB_DA2_PX

@

4

RV105

+3VS_DELAY

12

12

RV106

2.2K_0402_5%~D

+3VS_DELAY

2

QV4A

DMN66D0LDW-7_SOT363-6~D

I2CC_SCL

1 2

RV111 2.2K_0402_5%~D

RV112 2.2K_0402_5%~D

RV113 2.2K_0402_5%~D

RV114 2.2K_0402_5%~D

1 2

1 2

1 2

I2CC_SDA

I2CH_SCL

I2CH_SDA

61

4

DMN66D0LDW-7_SOT363-6~D

Straps

5

QV4B

10U_0603_6.3V6M~D

Spare/Test

150mA

1

CV267

2

1

CV269

2

0.1U_0402_16V7K~D

NOT FOR PRODUCTION

FOR LAB TEST ONLY

+GPU_PLLVDD

Place close to balls

0.3mm

0.3mm

1

CV270

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.3mm

1

1

CV271

CV272

2

2

0.1U_0402_16V7K~D
RV88

10K_0402_5%~D

12

18P_0402_50V8J~D

STRAP0
STRAP1
STRAP2
ROM_SI
ROM_SO
ROM_SCLK

@

1 2

RV90 5.1K_0402_5%

1 2

RV92 35.7K_0402_1%

@

1 2

RV94 15K_0402_1%~D

X76@

1 2

RV96 15K_0402_5%~D

1 2

RV98 10K_0402_1%~D

1 2

RV101 15K_0402_1%~D

MULTI LEVEL STRAPS

1 2

RV91 45.3K_0402_1%

@

1 2

RV93 10K_0402_1%~D

1 2

RV95 30K_0402_1%

@

1 2

RV97 5.1K_0402_1%~D

@

1 2

RV99 5.1K_0402_1%~D

@

1 2

RV102 15K_0402_1%~D

+3VS_DELAY

strap0

strap1

strap2

ROM_SI

ROM_SO

ROM_SCLK

64MX16
Samsung

6

4MX16

Hynix

128MX16
Samsung

128MX16
Hynix

SSI --> Hynix

UV3T

GPU_THERMAL_D-

GPU_THERMAL_D+

12

@

RV264

10K_0402_5%~D

EC_SMB_CK2 <30,31,58>

3

EC_SMB_DA2 <30,31,58>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

AT4

THERMDN

AR4

THERMDP

AL2

JTAG_TCK

AM3

JTAG_TMS

AN2

JTAG_TDI

AN1

JTAG_TDO

AL3

12

RV265

JTAG_TRST

10K_0402_5%~D

N12E-GE_BGA1328~D

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

AH8

PLLVDD

AH7

SP_PLLVDD

AG8

VID_PLLVDD

AU4

XTALSSIN

AU2

XTALIN

N12E-GE_BGA1328~D

XTALIN

ROM_SI

Pull low with
RV96=20K

Pull low with
RV96=15K

Pull low with
RV96=45K

Pull low with
RV96=35K

CV273

UV3S

I2CS_SCL

I2CS_SDA

I2CC_SCL
I2CC_SDA

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO16
GPIO17
GPIO18

GPIO20

GPIO22
GPIO23
GPIO24

YV1

3

2

1

27MHZ_16PF_X7T027000BG1H-V

2

EC_SMB_CK2_PX

AK3

EC_SMB_DA2_PX

AL1

AG3

I2CC_SDA

AH1

AD3
AD4
AC3
AC4
AD5
AD1
AE1
AE5
AD6
AA6
AE2
AE6
AD7

RV230 10K_0402_5%~D

AE7
AE3
AF3

AF4

AB6
AG4
AG6

PACIN<51>

XTALOUTBUFF

AU3

XTALOUT

4

OUT

GND

1

GND

IN

XTALOUT

1

CV274
18P_0402_50V8J~D

2

12

XTAL_OUTBUFFXTAL_SSIN

AU1

+3VS_DELAY

I2CC_SCL

1

@

CV532

2

GPU_VID0
GPU_VID1

RV228 10K_0402_5%~D

1 2

THM_ALERT#

RV229 10K_0402_5%~D

1 2

1 2

10P_0402_50V8J~D

10K_0402_5%~D

AC_BATT

@

RV262

+3VS_DELAY

10K_0402_5%~D

12

RV107

12

RV263

10K_0402_5%~D

12

12

@

RV108

10K_0402_5%~D

+3VS_DELAY

12

+3VS_DELAY

12

RV275

4.7K_0402_1%~D

PACIN#

61

QV15A

2

2N7002DW-7-F_SOT363-6~D

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

LA-6801P

RV266
10K_0402_5%~D

AC_BATT

3

5

QV15B
2N7002DW-7-F_SOT363-6~D

4

N12E(6/6)_GPIO

1

RV89
10K_0402_5%~D

GPU_VID0 <56>
GPU_VID1 <56>

45 60Monday, December 06, 2010

0.3

5

+VREFCA_A1 +VREFCA_A2
+VREFDA_Q1

MDA[0..63]<41>

MAA[0..31]<41>

DQMA#[7..0]<41>

QSA[7..0]<41>

D D

QSA#[7..0]<41>

CLKA0<41>
CLKA0#<41>

C C

RV115
243_0402_1%~OK

MAA9
MAA11
MAA8
MAA25
MAA10
MAA24
MAA22
MAA7
MAA21
MAA6
MAA29
MAA23
MAA28
MAA20
MAA4
MAA14

MAA12
MAA27
MAA26

MAA3

MAA2
MAA0
MAA30
MAA15
MAA13

QSA1

DQMA#2 DQMA#6

QSA#1
QSA#2

MAA5

12

UV5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

4

RV116
243_0402_1%~OK

+VREFCA_A1
+VREFDA_Q1

MAA9
MAA11
MAA8
MAA25
MAA10
MAA24
MAA22
MAA7
MAA21
MAA6
MAA29
MAA23
MAA28
MAA20
MAA4
MAA14

MAA12
MAA27
MAA26

CLKA0
CLKA0#
MAA3

MAA2
MAA0
MAA30
MAA15
MAA13

QSA0
QSA3

DQMA#0
DQMA#3

QSA#0
QSA#3

MAA5

12

MDA12

E3

MDA8

F7

MDA15

F2

MDA11

F8

MDA13

H3

MDA9

H8

MDA14

G2
H7

MDA18

D7

MDA20

C3

MDA16

C8

MDA21

C2

MDA17

A7

MDA22

A2

MDA19

B8

MDA23

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

UV6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3

MDA1

E3

MDA4

F7

MDA3

F2

MDA5

F8

MDA2

H3

MDA7

H8

MDA0

G2

MDA6

H7

MDA30

D7

MDA27

C3

MDA31

C8

MDA25

C2

MDA28

A7

MDA24

A2

MDA29

B8

MDA26

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

CLKA1<41>
CLKA1#<41>

RV117
243_0402_1%~OK

M8

+VREFDA_Q2 +VREFDA_Q2

H1

MAA9

N3

MAA11

P7

MAA8

P3

MAA25

N2

MAA10

P8

MAA24

P2

MAA22

R8

MAA7

R2

MAA21

T8

MAA6

R3

MAA29

L7

MAA23

R7

MAA28

N7

MAA20

T3

MAA4

T7

MAA14

M7

MAA12

M2

MAA27

N8

MAA26

M3

J7

K7

MAA19

K9

MAA18

K1

MAA16

L2

MAA30
MAA15
MAA13

QSA4
QSA7QSA2

DQMA#4DQMA#1
DQMA#7

QSA#4
QSA#7

MAA5

J3
K3
L3

F3
C7

E7
D3

G3

B7

T2

L8

12

J1
L1

J9
L9

2

UV7

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

K4B1G1646E-HC11_FBGA96

X76@

1

UV8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDA46

E3

MDA40

F7

MDA47

F2

MDA43

F8

MDA44

H3

MDA42

H8

MDA45

G2

MDA41MDA10

H7

MDA53

D7

MDA51

C3

MDA54

C8

MDA49

C2

MDA52

A7

MDA50

A2

MDA55

B8

MDA48

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

CLKA1<41>
CLKA1#<41>

RV118
243_0402_1%~OK

+VREFCA_A2

MAA9
MAA11
MAA8
MAA25
MAA10
MAA24
MAA22
MAA7
MAA21
MAA6
MAA29
MAA23
MAA28
MAA20
MAA4
MAA14

MAA12
MAA27
MAA26

MAA19

MAA18
MAA16
MAA30
MAA15
MAA13

QSA5
QSA6

DQMA#5

QSA#5
QSA#6

MAA5

12

MDA33

E3

MDA36

F7

MDA35

F2

MDA37

F8

MDA32

H3

MDA38

H8

MDA34

G2

MDA39

H7

MDA58

D7

MDA60

C3

MDA56

C8

MDA62

C2

MDA57

A7

MDA63

A2

MDA59

B8

MDA61

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU

1

B B

1.33K_0402_1%~D

1.33K_0402_1%~D

A A

VRAM P/N :
Samsung : SA000041T00 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA 96P )
Hynix : SA000041S20 (S IC D3 64MX16 H5TQ1G63DFR-11C FBGA 96P )

1

CV283

2

0.1U_0402_16V7K~D

+1.5VSDGPU +1.5VSDGPU

RV120

RV124

CV284

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

12

+VREFDA_Q1 +VREFCA_A1

CV278

0.01U_0402_25V7K~D

12

1

2

5

1

1

CV286

CV285

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1.33K_0402_1%~D

1.33K_0402_1%~D

1

1

CV298

2

0.1U_0402_16V7K~D

RV119

RV123

1

CV299

CV287

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

12

CV277

0.01U_0402_25V7K~D

12

1

2

4

1

1

CV288

2

0.1U_0402_16V7K~D

CV289

2

CLKA0

CLKA0#

1

2

0.1U_0402_16V7K~D

12

CV290

RV128
160_0402_1%

1U_0402_6.3V6K~D

1

1

CV282

2

1U_0402_6.3V6K~D

1

CV281

CV500

2

2

1U_0402_6.3V6K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0.1U_0402_16V7K~D

2010/12/01 2011/12/01

1

CV294

2

1

CV295

2

0.1U_0402_16V7K~D

+1.5VSDGPU

RV122

1.33K_0402_1%~D

RV126

1.33K_0402_1%~D

Compal Secret Data

1

CV296

2

0.1U_0402_16V7K~D

12

+VREFDA_Q2

12

Deciphered Date

1

CV293

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

CV280

0.01U_0402_25V7K~D

1

2

2

1

2

CV304

1

CV305

2

0.1U_0402_16V7K~D

+1.5VSDGPU

RV121

1.33K_0402_1%~D

RV125

1.33K_0402_1%~D

1

1

CV300

2

0.1U_0402_16V7K~D

1

CV301

CV302

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CLKA1

12

+VREFCA_A2

12

0.01U_0402_25V7K~D

1

CLKA1#

CV279

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

VRAM_DDR3 / Channel A

1

CV303

2

1U_0402_6.3V6K~D

12

RV131
160_0402_1%

LA-6801P

1

1

1

CV292

2

1U_0402_6.3V6K~D

1

CV291

CV501

2

2

1U_0402_6.3V6K~D

46 60Monday, December 06, 2010

0.3

5

+VREFCB_A1 +VREFCB_A2
+VREFDB_Q1

RV133
243_0402_1%~OK

MAB9
MAB11
MAB8
MAB25
MAB10
MAB24
MAB22
MAB7
MAB21
MAB6
MAB29
MAB23
MAB28
MAB20
MAB4
MAB14

MAB12
MAB27
MAB26

MAB3

MAB2
MAB0
MAB30
MAB15
MAB13

MAB5

12

QSB1

QSB#1
QSB#2

MDB[0..63]<41>

MAB[0..31]<41>

DQMB#[7..0]<41>

QSB[7..0]<41>

D D

QSB#[7..0]<41>

CLKB0<41>
CLKB0#<41>

C C

UV9

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

4

+1.5VSDGPU

RV134
243_0402_1%~OK

+VREFCB_A1
+VREFDB_Q1

MAB9
MAB11
MAB8
MAB25
MAB10
MAB24
MAB22
MAB7
MAB21
MAB6
MAB29
MAB23
MAB28
MAB20
MAB4
MAB14

MAB12
MAB27
MAB26

CLKB0
CLKB0#

MAB3

MAB2
MAB0
MAB30
MAB15
MAB13

QSB0
QSB3

DQMB#0
DQMB#3DQMB#2 DQMB#6

QSB#0
QSB#3

MAB5

12

MDB13

E3

MDB8

F7

MDB12

F2

MDB10

F8

MDB14

H3

MDB11

H8

MDB15

G2

MDB9

H7

MDB18

D7

MDB20

C3

MDB16

C8

MDB21

C2

MDB17 MDB57

A7

MDB22

A2

MDB19

B8

MDB23

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

UV10

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

3

MDB2
MDB4
MDB3
MDB5
MDB1
MDB7
MDB0
MDB6

MDB30
MDB27
MDB31
MDB25
MDB28
MDB26
MDB29
MDB24

+1.5VSDGPU

+1.5VSDGPU

2

UV11

M8

+VREFDB_Q2 +VREFDB_Q2

MAB9
MAB11
MAB8
MAB25
MAB10
MAB24
MAB22
MAB7
MAB21
MAB6
MAB29
MAB23
MAB28
MAB20
MAB4
MAB14

MAB12
MAB27
MAB26

CLKB1<41>
CLKB1#<41>

MAB19

MAB18
MAB16
MAB30
MAB15
MAB13

QSB4
QSB7QSB2

DQMB#4DQMB#1
DQMB#7

QSB#4
QSB#7

MAB5

12

RV135

243_0402_1%~OK

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC11_FBGA96

X76@

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MDB40

E3

MDB46

F7

MDB43

F2

MDB47

F8

MDB42

H3

MDB44

H8

MDB41

G2

MDB45

H7

MDB53

D7

MDB49

C3

MDB54

C8

MDB51

C2

MDB52

A7

MDB50

A2

MDB55

B8

MDB48

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

UV12

M8
H1

N3

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

K4B1G1646E-HC11_FBGA96

X76@

RV136
243_0402_1%~OK

+VREFCB_A2

MAB9
MAB11
MAB8
MAB25
MAB10
MAB24
MAB22
MAB7
MAB21
MAB6
MAB29
MAB23
MAB28
MAB20
MAB4
MAB14

MAB12
MAB27
MAB26

CLKB1
CLKB1#
MAB19

MAB18
MAB16
MAB30
MAB15
MAB13

QSB5
QSB6

DQMB#5

QSB#5
QSB#6

MAB5

12

MDB36

E3

MDB33

F7

MDB38

F2

MDB34

F8

MDB39

H3

MDB32

H8

MDB37

G2

MDB35

H7

MDB58

D7

MDB60

C3

MDB56

C8

MDB62

C2
A7

MDB63

A2

MDB59

B8

MDB61

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU +1.5VSDGPU

B B

A A

1

CV327

2

0.1U_0402_16V7K~D

1.33K_0402_1%~D

1.33K_0402_1%~D

5

0.1U_0402_16V7K~D

1

CV328

2

+1.5VSDGPU

12

RV138

12

RV142

1

1

CV329

CV326

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

+VREFDB_Q1

CV308

0.01U_0402_25V7K~D

1

0.1U_0402_16V7K~D

2

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

1

CV334

2

1.33K_0402_1%~D

1.33K_0402_1%~D

1

2

0.1U_0402_16V7K~D

CV335

+1.5VSDGPU

12

RV137

12

RV141

4

1

1

CV330

CV331

2

2

0.1U_0402_16V7K~D

+VREFCB_A1

1

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CV307

0.01U_0402_25V7K~D

2

1

1

CV333

CV332

2

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

CLKB0

12

CLKB0#

1

CV325

2

RV146
160_0402_1%

1

CV324

2

1U_0402_6.3V6K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.5VSDGPU +1.5VSDGPU

1

1

1

1

2

1U_0402_6.3V6K~D

CV502

CV315

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2010/12/01 2011/12/01

CV318

2

0.1U_0402_16V7K~D

RV140

1.33K_0402_1%~D

RV144

1.33K_0402_1%~D

Compal Secret Data

CV319

2

12

12

Deciphered Date

1

CV320

2

1U_0402_6.3V6K~D

1

CV322

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1.33K_0402_1%~D

CV310

0.01U_0402_25V7K~D

1

2

1.33K_0402_1%~D

2

1

1

2

CV323

+1.5VSDGPU+1.5VSDGPU

RV139

RV143

CV314

2

0.1U_0402_16V7K~D

12

+VREFCB_A2+VREFDB_Q2

12

1

2

1

1

CV317

CV316

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CV309

0.01U_0402_25V7K~D

Title

Size Document Number Rev

Custom

Date: Sheet of

0.1U_0402_16V7K~D

CLKB1

CLKB1#

Compal Electronics, Inc.

VRAM_DDR3 / Channel B

1

CV321

2

1U_0402_6.3V6K~D

12

RV149
160_0402_1%

LA-6801P

1

1

CV313

2

1U_0402_6.3V6K~D

1

1

CV503

CV312

2

2

1U_0402_6.3V6K~D

47 60Monday, December 06, 2010

0.3

5

+VREFCC_A1 +VREFCC_A2
+VREFDC_Q1

RV151
243_0402_1%~OK

MAC9
MAC11
MAC8
MAC25
MAC10
MAC24
MAC22
MAC7
MAC21
MAC6
MAC29
MAC23
MAC28
MAC20
MAC4
MAC14

MAC12
MAC27
MAC26

MAC3

MAC2
MAC0
MAC30
MAC15
MAC13

MAC5

12

QSC1

QSC#1
QSC#2

MDC[0..63]<42>

MAC[0..31]<42>

DQMC#[7..0]<42>

QSC[7..0]<42>

D D

QSC#[7..0]<42>

CLKC0<42>
CLKC0#<42>

C C

UV13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

4

+1.5VSDGPU

RV152
243_0402_1%~OK

+VREFCC_A1
+VREFDC_Q1

MAC9
MAC11
MAC8
MAC25
MAC10
MAC24
MAC22
MAC7
MAC21
MAC6
MAC29
MAC23
MAC28
MAC20
MAC4
MAC14

MAC12
MAC27
MAC26

CLKC0
CLKC0#

MAC3

MAC2
MAC0
MAC30
MAC15
MAC13

QSC0
QSC3

DQMC#0
DQMC#3DQMC#2 DQMC#6

QSC#0
QSC#3

MAC5

12

MDC15

E3

MDC11

F7

MDC14

F2

MDC10

F8

MDC13

H3

MDC9

H8

MDC12

G2

MDC8

H7

MDC23

D7

MDC19

C3

MDC22

C8

MDC17

C2

MDC20

A7

MDC18

A2

MDC21

B8

MDC16

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

UV14

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC11_FBGA96

X76@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1
B9
D1
D8
E2
E8
F9
G1
G9

MDC4
MDC6
MDC0
MDC2
MDC7
MDC1
MDC5
MDC3

MDC29
MDC24
MDC30
MDC27
MDC28
MDC26
MDC31
MDC25

+1.5VSDGPU

+1.5VSDGPU

3

M8

+VREFDC_Q2

H1

MAC9

N3

MAC11
MAC8
MAC25
MAC10
MAC24
MAC22
MAC7
MAC21
MAC6
MAC29
MAC23
MAC28
MAC20
MAC4
MAC14

MAC12
MAC27
MAC26

CLKC1<42>
CLKC1#<42>

MAC18
MAC16
MAC30
MAC15
MAC13

MAC19

QSC4
QSC7QSC2

DQMC#4DQMC#1
DQMC#7

QSC#4
QSC#7

MAC5

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

12

J1

L1

RV153

J9

L9

243_0402_1%~OK

2

UV15

96-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

K4B1G1646E-HC11_FBGA96

X76@

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MDC46

E3

MDC43

F7

MDC47

F2

MDC40

F8

MDC45

H3

MDC42

H8

MDC44

G2

MDC41

H7

MDC53

D7

MDC51

C3

MDC54

C8

MDC49

C2

MDC52

A7

MDC50

A2

MDC55

B8

MDC48

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

UV16

M8
H1

N3

P7
P3

N2

P8

P2
R8
R2

T8
R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

K4B1G1646E-HC11_FBGA96

X76@

RV154
243_0402_1%~OK

+VREFCC_A2
+VREFDC_Q2

MAC9
MAC11
MAC8
MAC25
MAC10
MAC24
MAC22
MAC7
MAC21
MAC6
MAC29
MAC23
MAC28
MAC20
MAC4
MAC14

MAC12
MAC27
MAC26

CLKC1
CLKC1#
MAC19

MAC18
MAC16
MAC30
MAC15
MAC13

QSC5
QSC6

DQMC#5

QSC#5
QSC#6

MAC5

12

MDC37

E3

MDC32

F7

MDC36

F2

MDC33

F8

MDC38

H3

MDC35

H8

MDC39

G2

MDC34

H7

MDC61

D7

MDC59

C3

MDC60

C8

MDC62

C2

MDC57

A7

MDC58

A2

MDC63

B8

MDC56

A3

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU +1.5VSDGPU+1.5VSDGPU +1.5VSDGPU

B B

1

1

1

1

CV358

CV356

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+1.5VSDGPU +1.5VSDGPU

12

RV156

1.33K_0402_1%~D

+VREFDC_Q1 +VREFCC_A1

CV338

0.01U_0402_25V7K~D

12

RV160

1.33K_0402_1%~D

A A

5

1

2

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

1

CV359

2

2

1U_0402_6.3V6K~D

1.33K_0402_1%~D

1.33K_0402_1%~D

CV355

RV155

RV159

1

CV364

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

12

12

1

1

CV365

2

0.1U_0402_16V7K~D

1

CV360

CV361

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CLKC0

12

CV337

0.01U_0402_25V7K~D

1

2

4

CV362

2

RV164
160_0402_1%

1

1

CV363

2

0.1U_0402_16V7K~D

CV354

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

3

CV353

1

CV504

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

+1.5VSDGPU +1.5VSDGPU

RV158

1.33K_0402_1%~D

RV162

1.33K_0402_1%~D

2010/12/01 2011/12/01

1

CV347

2

12

+VREFDC_Q2CLKC0#

12

1

1

CV348

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CV340

0.01U_0402_25V7K~D

1

2

Compal Secret Data

Deciphered Date

CV349

1U_0402_6.3V6K~D

1.33K_0402_1%~D

1.33K_0402_1%~D

1

2

RV157

RV161

CV350

0.1U_0402_16V7K~D

12

+VREFCC_A2

12

2

1

1

CV351

2

0.1U_0402_16V7K~D

CV339

0.01U_0402_25V7K~D

1

CV343

CV352

2

2

0.1U_0402_16V7K~D

CLKC1

CLKC1#

1

1

1

1

1

1

CV344

CV345

CV346

2

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

12

RV167
160_0402_1%

CV342

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CV341

CV505

2

2

1U_0402_6.3V6K~D

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

VRAM_DDR3 / Channel C

LA-6801P

48 60Monday, December 06, 2010

1

0.3

5

4

3

2

1

Power block

D D

CPU OTP

Page 59

Turn Off

DC IN

Input
Switch

Page 51

B+

+3VALWP: TDC:4.8A efficiency: 93%
+5VALWP: TDC:6A efficiency: 90%
RT8205E

Always

Page 52

CHARGER
CC:0A~3A

C C

CV:14.8V(8cell)
ISL6251AHAZ-T

Page 51

Battery

DGPU_PWR_EN

B B

+GPU CORE efficiency: 88%
TDC:36.8A
ISL6264CRZ-T

Page 56

+1.8VP: TDC:1.25A
RT8209B efficiency: 88%

+VCCPP: TDC:12.8A
R

T8209B efficiency: 82%

+1.5VSDGPUP: TDC:5.6A
R

T8209B efficiency: 83%

+1.5VP: TDC:7A
R

T8209B efficiency: 84%

SUSP#

Page 54

SUSP#

Page 54

DGPU_PWR_EN

Page 55

SYSON

Page 53

+0.75VSP: TDC:1A

VR_ON

A A

VR_ON

5

CPU CORE efficiency: 86%
TDC: 52A
ISL95831CRZ-T

GFX CORE efficiency: 85%
TDC: 21.5A
ISL95831CRZ-T

Page 57

Page 57

4

+VCCSAP: TDC:4.2A

VTTPWRGOOD

RT8209B efficiency: 80%

Page 55

+1.5VSP: TDC:1.26A
RT8209B efficiency: 89%

Page 53

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

2

RT9026

Page 53

SUSP#

Title

Size Document Number Rev

Custom

Date: Sheet of

+3VALW

Compal Electronics, Inc.

POWER BLOCK DIAGRAM

LA-6801P

49 60Monday, December 06, 2010

1

0.1

5

PL1

BLM18BD102SN1D_0603~D

@

PJDCIN

9

D D

C C

B B

8

7

6

DETECT_PSID

GND_4

GND_3

GND_2

GND_1

FOX_JPD113D-DB570-7F

BATT+

51ON#<29>

2

1

DETECT

DC+_1

DC+_2

DC-_1

DC-_2

3

@

PD4
SM24_SOT23

LL4148_LL34-2

100K_0402_5%

PR23

22K_0402_5%

1 2

PD7

PR22

5

1

2

3

4

PR11

1 2

100K_0402_1%

PR13

15K_0402_1%

1 2

12

Pre_V

TP0610K-T1-E3_SOT23-3

Pre_V

12

12

PC9

0.22U_0603_25V7K

DETECT_PSIDPSID

12

ADPIN

12

12

PC1

100P_0402_50V8J

PR8
0_0402_5%@

1 2

D

1 3

2

C

2

B

E

3 1

PQ6

13

32.7

2

4

PL2

C8B BPH 853025_2P

1 2

PC2

1000P_0402_50V7K

PR10

33_0402_5%

S

1 2

PQ4
FDV301N_NL_SOT23-3~D

G

PQ5
MMST3904-7-F_SOT323~D

VIN

PD6
LL4148_LL34-2

1 2

12

12

PR18

68_1206_5%

12

PC10

0.1U_0603_25V7K

PC3

+5VALW

PD3

DA204U_SOT323~D

PR19

68_1206_5%

VS

3

VIN

PreCHG

VIN

12

100P_0402_50V8J

3

1

2

+5VALW

12

12

PC4

1000P_0402_50V7K

PR12

10K_0402_1%

PR14

1 2

10K_0402_1%

+3VALW

PR9

2.2K_0402_5%

PD5

@

1 2

+5VALW

DA204U_SOT323~D

ACOFF<31,51>

+5VALW

PS_ID <31>

2

3

1

PSID_DISABLE#

Dyn_Turbo_Sel<31>

EMC_THERM#<51>

VR_HOT#<31,57>

1K_1206_5%

1 2

PR2

1K_1206_5%

1 2

1K_1206_5%

1 2

1K_1206_5%

1 2

PR17

@

0_0402_5%

PR24

@

0_0402_5%

PR25

@

0_0402_5%

PR1

PR3

PR6

PD2

2

3

RB715F_SOT323-3

12

12

12

1

10K_0402_1%

13

D

S

2

PD1

12

LL4148_LL34-2

12

PR4

13

2

+3VALW

12

PR16

2

G

PQ12
2N7002W-T/R7_SOT323-3

12

PR5

470K_0402_5%

470K_0402_5%

PQ2
DTC115EUA_SC70-3

12

PC23

1

0

PQ1

TP0610K-T1-E3_SOT23-3

2

12

13

2

PR26

@

0_0402_5%

12

VL

PU1A

8

LM393DR_SO8

1000P_0402_50V7K

3

P

+

2

-

G

4

B+

13

PR7
470K_0402_5%

PQ3
DTC115EUA_SC70-3

12

12

1

PC8

@

0_0402_5%
PR21

1000P_0402_50V7K

12

ADP_I <31,51>

12

PR20
0_0402_5%

PC7

@

1000P_0402_50V7K

AC_SEL <31>

modify 10/07
design change

PBJ1

1
2

SP020009Z0L

CONN@

3

4

PU2
MAX1615EUK+_SOT23-5~D

1
2

OUT

5/3+

#SHDN

GND

2

+RTCBATT

1

IN

5

+RTCBATT

+CHGRTC

12

PC11

4.7U_0603_6.3V6K

A A

MOLEX_53261-0271~D

5

PR27

1 2

200_0805_5%

modify 10/21
for ME request

4

12

PC12

1U_0603_25V6K

revise 9/17
reduce S5 loss

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-DCIN / Vin Detector

Size Document Number Rev

C

LA-6801P

Date: Sheet of

1

50 60Monday, December 06, 2010

0.1

Iada=0~7.693A(150W/19.5V=7.693A)

A

ADP_I = 19.9*Iadapter*Rsense

PQ101

VIN

1 1

12

PR105
200K_0402_1%

V1

2

61

D

2

G

2 2

3 3

PQ108A
DMN66D0LDW-7_SOT363-6

S

PACIN<45>

ACOFF<31,50>

SI4459ADY-T1-GE3_SO8

8
7

5

2

13

1 3

PQ105
DTC115EUA_SC70-3

47K_0402_1%

PACIN

1 2

DTC115EUA_SC70-3

ACOFF

PQ104
DTA144EUA_SC70-3

PR122

PQ113

2

CP = 90%*Iada ; CP = 6.92A

PQ102

SI4459ADY-T1-GE3_SO8

1
2
3 6

4

PR106
200K_0402_1%

12

6251VDD

PR113
150K_0402_1%

34

D

PQ108B
DMN66D0LDW-7_SOT363-6

S

PR126

147K_0402_1%

12

PR128

100K_0402_1%

+3VALW

PR143

@

10K_0402_1%

1 2

2

G

PC133

1 2

@

0.1U_0402_16V7K

FSTCHG<31>

revise 10/25

12

1
2
36

4

5

13

P2

12

12

PC106

0.1U_0603_25V7K

G

IREF<31>

CP_SEL<31>

add 12/06
CP point select

8
7

5

1 2

PC101

5600P_0402_25V7K

PR114 0_0402_5%

1 2

2

1 2

PC115

0.01U_0402_25V7K

ADP_I<31,50>

12

PC120

0.01U_0402_25V7K

1 2

PR142

4.53K_0402_1%

13

D

S

PQ115

2N7002W-T/R7_SOT323-3

13

6251VREF

@

add 10/19
for EMI request

P3

PD103 1SS355_SOD323-2

1 2

PR112

10K_0402_5%

1 2

0.1U_0402_16V7K

PQ109
DTC115EUA_SC70-3

PC114 6800P_0402_25V7K

1 2

PR120 10K_0402_1%

1 2

1 2

PC117

100P_0402_50V8J@

PC118

1 2

.1U_0402_16V7K

PR129

6251VREF

1 2

11.5K_0402_1%

CHGVADJ<31>

1

2

PC110

CP mode

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
Vaclim=2.39*((6.98K//152K)/((11.5K//152K)+(6.98K//152K)))

CC=3.3A

IREF=1*Icharge

IREF=0.25V~3.3V

4 4

BATT Type Charging Voltage

CV mode

(0x15)

Normal 4S LI-ON Cells

14800mV

A

14.80V

CHGVADJ CV mode

0V

1.93V

3.3V

3.99V per cell

4.2V per cell

4.35V per cell

PR101

0.01_2512_1%

EMC_SENSE+

ACSETIN

12

PR115

100_0402_1%

1 2

6251VREF

6251aclim

12

PR131

6.98K_0402_1%

PR132

25.5K_0402_1%

1 2

B

PL102

12

12

PC126

10U_0805_25V6K

4

3

EMC_SENSE-

12

PC128

@

10U_0805_25V6K

B+

PC129

10U_0805_25V6K

VIN

6251VDD

12

PC107

2.2U_0603_6.3V6K

PU101

12

100K_0402_1%

PR123

1

2

6251_EN CSON

3

4

5

6

7

6251VREF

8

9

10

11

12

ISL6251AHAZ-T_QSOP24

PR133

43.2K_0402_1%

1 2

PR134

47K_0402_1%

ACPRN

B

PD102

RB751V-40_SOD323-2

VDD

DCIN

ACSET

ACPRN

EN

CSON

CELLS

CSOP

ICOMP

CSIN

VCOMP

CSIP

PHASE

ICM

UGATE

VREF

CHLIM

BOOT

ACLIM

VDDP

VADJ

LGATE

PGND

GND

12

2

PR110

10_1206_5%

24

23

22

21

20

19

18

17

16

15

14

13

6251VDD

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

@

3.3UH_1231AS-H-3R3M-P3_1.6A_20%

1 2

PJP101

@

2

112

CSIP

PreCHG

PR104

1 2

12

0_0402_5%

PR107

191K_0402_1%

ACSETIN

12

PR111

15K_0402_1%

ACPRN <52>

PR116

20_0402_5%

1 2

PR118

20_0402_5%

12

PR119
20_0402_5%

1 2

PR121

2_0402_5%

BST_CHGA

12

PD105
RB751V-40_SOD323-2

PC127

1 2

4.7U_0603_6.3V6K

PR136

10K_0402_1%

1 2

PACIN

12

PR137

14.3K_0402_1%

CSIN

0.1U_0603_25V7K

1 2

PR102

@

1 2

0_0402_5%

1 2

12

12

PC108

1000P_0402_50V7K

0.1U_0603_25V7K

DCIN

ACPRN

PC113

0.047U_0603_16V7K

1 2

PC116

0.1U_0603_25V7K

1 2

LX_CHG

DH_CHG

2.2_0603_5%

BST_CHG

6251VDDP

DL_CHG

12

PR135
10K_0402_1%

13

PQ114
DTC115EUA_SC70-3

JUMP_43X118

PC111

12

1 2

PR127

1 2

Issued Date

PR130

4.7_0603_5%

2010/08/03 2011/08/03

add 10/20
for EMI request

12

PC102

PC103

4.7U_0805_25V6-K

4.7U_0805_25V6-K

CSOP

PC119

12

6251VDD

ACIN <3 1,34>

Compal Secret Data

C

12

PC104

0.1U_0603_25V7K

C

CHG_B+

12

12

PC105

2200P_0402_50V7K

6

578

4

6

578

4

+5VS

Deciphered Date

PQ103
SI4459ADY-T1-GE3_SO8

1
2
3 6

PR108

10K_0402_1%

PQ106

DTC115EUA_SC70-3

100K_0402_1%

V1

PQ111
AO4466L_SO8

PC131

12

12

1 2

PL101

1 2

PR125

4.7_1206_5%

PC123

680P_0402_50V7K

PC132

1 2

1U_0402_6.3V6K

0.1U_0402_16V7K

10UH_PCMB104T-100MS_6A_20%

123

PQ112
AO4466L_SO8

123

EMC_SENSE-

EMC_SENSE+

4

47K_0402_1%

1 2
13

PR117

12

ACPRN

CHGCH G

3

SENSE-

SENSE+4SMDATA

5

VDD

D

8
7

5

PR103

1 2

2

ADDR_SEL

6

12

PR138

VIN

PD101

@

1 2

1SS355_SOD323-2

BAT_DIS_G

PD104

@

1 2

1SS355_SOD323-2

12

PC109

13

2200P_0402_50V7K

D

PQ110

2

G

S

2N7002W-T/R7_SOT323-3

PR124

1

2

2

N/C

ALERT#

THERM#

20K_0402_1%

0.02_1206_1%

4

3

PU102
EMC1701-2-AIZL-TR_MSOP10

1

SMCLK

10

9

8

12

GND

7

@

slave address : 0101101
p

lease placemnet near R-sense

Compal Electronics, Inc.

Title

PWR-CHARGER

Size Document Number Rev

Custom

LA-6801P

Date: Sheet

@

PR139

+3VS

PC112

10K_0402_1%

ACOFF

PR109

@

200K_0402_1%

1 2

12

0.1U_0603_25V7K

PC124

1 2

PR141

@

0_0402_5%

12

PR140

@

10K_0402_1%

D

VIN

13

D

PACIN

2

G

PQ107

@

S

2N7002W-T/R7_SOT323-3

12

12

PC121

10U_0805_25V6K

10U_0805_25V6K

PCH_SMLCLK <14,31>

PCH_SMLDATA <14,31>

12

PC125

10U_0805_25V6K

modify 10/06
customer request

EMC_ALERT# <31>

EMC_THERM# <50>

BATT+

12

PC122

10U_0805_25V6K

0.1

of

51 60Monday, December 06, 2010

5

4

3

2

1

2VREF_RT8205E

Note:
Use TPS51125 IC can remove RTC refernece LDO

D D

Use TPS51427 IC must keep RTC refernece LDO

12

PC201

1U_0603_10V6K

PR201

13K_0402_1%

1 2

PR221

PR213

BST_3V

UG_3V

LX_3V

LG_3V

100K_0402_1%

71.5K_0402_1%

PC218

PR203

20K_0402_1%

1 2

PR205

1 2

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

1 2

12

0_0402_5%@

PR222

1U_0603_10V6K

0_0402_5%

1 2

RT8205E_B+

2VREF_RT8205E

ENTRIP2

5

4

6

FB2

TONSEL

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

15

13

PR214

3

12

PL201

HCB2012KF-121T50_0805

B+

1 2

12

@

PC202

680P_0402_50V7K

C C

12

12

PC203

PC204

0.1U_0603_25V7K

4.7U_0805_25V6-K

+3VALWP

3.3VALWP
TDC 4.8 A
Peak Current 8.93 A
OCP current 10.67 A

PJP201

2

112

JUMP_43X118@

PJP202

+3VALWP +3VALW

B B

A A

2

112

JUMP_43X118@

MAINPWON<30,59>

1 2

VS

PR218
100K_0402_1%

ACPRN<51>

EC_ON<29,31>

1 2

PR219

200K_0402_1%

13

2

12

PC206

PC205

4.7U_0805_25V6-K
2200P_0402_50V7K

PC214

330U_D_6.3VM_R18M~D

PQ205A
DMN66D0LDW-7_SOT363-6

2

G

PQ208
DTC115EUA_SC70-3

12

PL202

4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D

1 2

1

+

2

VL

PR217

1 2

0_0402_5%

12

13

D

PR220

S

PQ207
2N7002W-T/R7_SOT323-3

PR209

PR216
100K_0402_1%

40.2K_0402_1%

12

4.7_1206_5%

12

PC215

680P_0402_50V7K

61

D

S

12

2

12

PC221

2.2U_0603_10V6K

123

786

123

2

G

6

578

PQ201
AO4466L_SO8

4

5

4

PQ203
SI4634DY-T1-E3_SO8

5

G

13

Typ: 175mA

B+

VS

Pre_V

34

D

PQ205B

S

DMN66D0LDW-7_SOT363-6

PQ206
DTC115EUA_SC70-3

PC211

4.7U_0805_10V6K

499K_0402_1%@

1 2

499K_0402_1%

1 2

499K_0402_1%@

1 2

ENTRIP2ENTRIP1

+3VLP

12

1 2

1 2

2.2_0603_5%

PC212

0.1U_0402_16V7K

MAINPWON<30,59>

PR211

PR212

PR215

PR207

1 2

@

0_0402_5%

reserve 10/06

12

reserve 10/27

RT8205E_B+

PR202

30K_0402_1%

1 2

PR204

20K_0402_1%

1 2

PR206

88.7K_0402_1%

ENTRIP1

1 2

2

1

FB1

REF

ENTRIP1

24

VO1

23

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

VIN16GND

17

12

PC219

4.7U_0805_10V6K

PC220

0.1U_0603_25V7K

BST_5V

22

UG_5V

21

LX_5V

20

LG_5V

19

PU201
RT8205EGQW_WQFN24_4X 4

VL

Typ: 175mA

RT8205E_B+

PC207

4.7U_0805_25V6-K

PR208

2.2_0603_5%

1 2

12

12

PC208

4.7U_0805_25V6-K

SPOK <59>

PC213

0.1U_0402_16V7K

1 2

12

PC210

PC209

2200P_0402_50V7K

SI4634DY-T1-E3_SO8

12

0.1U_0603_25V7K

6

578

4

PQ202
AO4466L_SO8

123

PL203

4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D

1 2

12

786

5

PR210

4

PQ204

+5VALWP +5VALW

4.7_1206_5%

12

PC216

123

680P_0402_50V7K

PJP203

2

112

JUMP_43X118@
PJP204

2

112

JUMP_43X118@

+5VALWP

1

+

PC217

2

330U_D_6.3VM_R18M~D

5VALWP
TDC 6A
Peak Current 11.24 A
OCP current 13.24 A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALWP/5VALWP

Size Document Number Rev

Custom

LA-6801P

2

Date: Sheet of

1

52 60Monday, December 06, 2010

0.1

A

PR301

PR307

1 2

10K_0402_1%

4

PVIN

PVIN

SVIN

EN

TP

11

PG

NC

7

267K_0402_1%

1 2

2

LX

3

LX

6

FB

NC

1

PR328

10.5K_0402_1%

1 1

SYSON<27,31,33>

+5VALW

2 2

PR314
10K_0402_5%@

1.5VDDR_VID0<16>

PR320

3 3

10K_0402_5%@

1.5VDDR_VID1<16>

+5VALW

4 4

+3VALW

12

+3VALW

12

PR316
10K_0402_5%

1 2

PR321
10K_0402_5%

1 2

PR323

10K_0402_5%

@

2

12

PR317

10K_0402_5%

PJP306

JUMP_43X79

SUSP#<10,18,31,33,54>

+3VALW

12

PR313
10K_0402_5%

3

PQ303B

5

4

12

PC326

0.01UF_0402_25V7K

PQ304B

12

112

5

12

PC328

0.01UF_0402_25V7K

12

PC329
10U_0805_10V6K

1 2

PR325
0_0402_5%

A

DMN66D0LDW-7 2N SOT363-6

+3VALW

12

3

4

12

10K_0402_5%

PR315

PR319
10K_0402_5%

DMN66D0LDW-7 2N SOT363-6

EN_1.5VS

PR302

0_0402_5%

1 2

PR306

10_0603_5%

1 2

1U_0603_10V6K

PQ303A

2

12

PC325

12

PR322

12

PC330
10U_0805_10V6K

PR326

1M_0402_1%

0.01UF_0402_25V7K

10K_0402_5%

PC316

12

PR312
75K_0402_1%@

61

DMN66D0LDW-7 2N SOT363-6

PQ304A

2

12

1.5VS_PIN

1 2

PC327

0.01UF_0402_25V7K

12

PC308

.1U_0402_16V7K

12

12

PR318
150K_0402_1%@

61

DMN66D0LDW-7 2N SOT363-6

12

PC334

@

12

PR308
10K_0402_1%

10

9

8

5

PU303
RT8061AZQW_WDFN10_3X3

1U_0402_6.3V6K

B

15

14

1

PU301

TON

VOUT

VDD

FB

PGOOD

NC

EN/DEM

VFB=0.75V

GND7PGND

8

2

3

4

5

6

BST_1.5V

DH_1.5V

13

BOOT
UGATE

LX_1.5V

12

PHASE

1 2

11

CS

PR305

6.49K_0402_1%

10

VDDP

9

LGATE

RT8209BGQW_WQFN14_3P5X3P5

DDR GPIO Output Voltage Selection

bit2 = 1.5DDR_VID0 DDR Voutbit1 = 1.5DDR_VID1

0

0

1

0

1

0

1 1

+1.5VP

+0.75VSP

12

PC321

PL303

LX_1.5VS

1.5VS_FB

12

1UH_PCMC063T-1R0MN_11A_20%

1 2

PR324

4.7_1206_5%

1 2

1.5VS_SNB

PC331
680P_0603_50V7K

1 2

1 2

PR327

15.8K_0402_1%

12

PC335
68P_0402_50V8J

B

PR303

2.2_0603_5%

1 2

PJP304

112

@

JUMP_43X79

12

4.7U_0805_6.3V6K

DL_1.5V

@

0.1U_0603_25V7K

BST_1.5V-1

+5VALW

12

PC313

4.7U_0805_10V6K

1.65V

1.6V

1.55V

1.5V (Default)

2

12

PC317

PC322

4.7U_0805_6.3V6K

12

PC332

22U_0805_6.3VAM

PC307

1 2

4

678

35241

786

5

C

PQ301
SI4172DY-T1-GE3_SO8

PQ302
SI4634DY-T1-E3_SO8

123

1.5V_B+

12

12

PC303

PC301

0.1U_0603_25V7K

2200P_0402_50V7K

PL302

1UH_PCMB062D-1R0MS_9A_20%

1 2

12

PR304

4.7_1206_5%

12

PC314

680P_0402_50V7K

12

PC305

PC304

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PC309

.1U_0402_16V7K

12

PC310

modify 10/20
for EMI request

3.3UH_1231AS-H-3R3M-P3_1.6A_20%

12

PC306

4.7U_0805_25V6-K

@

1

12

+

PC311

2

10U_0805_6.3V6M

220U_D2_2VY_R15M

Low Side MOS RDS(on)=5.5m ohm(Typ),6.7m ohm(Max)

+3VALW

12

PR309

1.2K_0402_1%

12

PR310
1K_0402_1%

12

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

PC318

@

+1.5VSP

12

PC333

22U_0805_6.3VAM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

PU302

RT9026_MSOP10

1

VDDQSNS

2

VLDOIN

3

VTT

5

VTTSNS

+1.5VSP
Imax=1.26A
Ipeak=1.8A
Iocp(minimum)=4A

10

VIN

8

GND

6

VTTREF

9

S5

7

S3

PGND

GND

4

11

2010/08/03 2011/08/03

12

Compal Secret Data

C

PR311

10K_0402_5%

PC323

.1U_0402_16V7K

+1.5VSP +1.5VS

Deciphered Date

12

12

PC319

1U_0603_10V6K

12

PC320

0.1U_0402_16V7K

SUSP# <10,18,31,33,54>

PJP307

2

112

@

JUMP_43X79

D

PL301

@

1 2

PJP301

112

@

JUMP_43X79

2

B+

12

PC302

@

680P_0402_50V7K

+1.5VP

1

+

PC312

2

220U_D2_2VY_R15M

@

1.5VP
TDC 7 A
Peak Current 10 A
OCP current 12 A

+3VALW

PJP305

112

@

JUMP_43X79

Compal Electronics, Inc.

Title

PWR-+1.5VP/+0.75VSP/+1.5VSP

Size Document Number Rev

C

LA-6801P

Date: Sheet of

PJP302

2

112

JUMP_43X118@

PJP303

2

112

JUMP_43X118@

2

+0.75VS+0.75VSP

D

+1.5V+1.5VP

53 60Monday, December 06, 2010

0.1

5

VCCPP
T

C 12.8 A

D
Peak Current 18.3 A
OCP current 22.4 A

D D

C C

Low Side MOS RDS(on)=2.6m ohm(Typ),3.2m ohm(Max)

PR403

0_0402_5%

+5VALW

12

100K_0402_5%

@

PC417

0.01U_0402_16V7K

1 2

PR408

10_0603_5%

1 2

1U_0603_10V6K

G

2

S

PQ403

@

35.7K_0402_1%

13

D

SUSP#<10,18,31,33,53>

+5VS

PR409

10K_0402_5%@

1 2

PR411

10K_0402_5%

@

12

12

PR413

@

PR410

@

1 2

0_0402_5%

VCCP_PWRCTRL<8>

PC415

PR414

1 2

@

BSS138W-7-F_SOT323~D

4

12

PC407

@

0.1U_0402_16V7K

12

4.02K_0402_1%

1 2

12

PR416

10K_0402_1%

PR415

PR402

267K_0402_1%

1 2

VTTPWRGOOD<55>

3

4

15

14

1

PU401

TON

VOUT

VDD

FB

PGOOD

VFB=0.75V

1 2

PR420
10K_0402_1%

@

1 2

NC

UGATE

EN/DEM

GND7PGND

RT8209BGQW_WQFN14_3P5X3P5

8

VCCP_AGND

PR412
0_0402_5%

1 2

PR417

10K_0402_1%

BOOT

PHASE

VDDP

LGATE

+3VS

13

12

11

CS

10

9

2

3

4

5

6

BST_VCCP

DH_VCCP

LX_VCCP

2.2_0603_5%

1 2

PR406

1 2

5.9K_0402_1%

PR404

DL_VCCP

VSSIO_SENSE<9>

BST_VCCP-1

12

PC408

0.1U_0603_25V7K

1 2

+5VALW

PC414

4.7U_0805_10V6K

PR418

0_0402_5%

1 2

VCCP_AGND

0_0402_5%

2

VCCP_B+

12

12

PC403

PC402

0.1U_0603_25V7K

2200P_0402_50V7K

5

PQ401
AON6414AL-1N_DFN

123

0.42UH_FDUE0640-R42M_20.2A_20%~D

12

PR405

4.7_1206_5%

12

PQ402

PC411

3 5

241

680P_0402_50V7K

AON6702L-1N_DFN8

PR419

12

12

PC405

PC404

4.7U_0805_25V6-K

4.7U_0805_25V6-K

VCCIO_SENSE <9>

PL402

12

PC406

10_0402_5%

12

4.7U_0805_25V6-K

@

12

PR407

PL401

@

HCB2012KF-121T50_0805

1 2

PJP401

2

112

JUMP_43X118@

1

+

2

PC409

1 2

330U_D2_2.5VY_R9M

1

revise 10/25
design change

PR401

0.01_1206_1%

1

4

B+

3

12

PC401

@

680P_0402_50V7K

2

CPU_IN_B+

CPU_VIN-<58> CPU_VIN+<58>

+VCCPP

12

12

PC410

PC413

.1U_0402_16V7K

10U_0805_6.3V6M

PJP402

2

112

JUMP_43X118@

PJP403

2

JUMP_43X118@

+VCCP+VCCPP

112

PJP406

2

JUMP_43X118@

+1.05VS

112

PU402
RT8061AZQW_WDFN10_3X3

PJP404

@

+5VALW

B B

A A

5

4

2

JUMP_43X79

SUSP#<10,18,31,33,53>

112

12

PC419
10U_0805_10V6K

1 2

PR422
0_0402_5%

12

EN_1.8VS

1M_0402_1%

1.8VS_PIN

PC420
10U_0805_10V6K

PR424

12

@

1 2

3

4

10

PVIN

9

PVIN

8

SVIN

5

EN

TP

11

PC424

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

PG

NC

7

2

LX

3

LX

6

FB

NC

1

14.3K_0402_1%

LX_1.8VS

1.8VS_FB

1 2

PR423

12

PR425

28.7K_0402_1%

PC425
68P_0402_50V8J

2010/08/03 2011/08/03

PL403

1UH_PCMC063T-1R0MN_11A_20%

1 2

PR421

4.7_1206_5%

1 2

1.8VS_SNB

PC421
680P_0603_50V7K

1 2

12

Compal Secret Data

Deciphered Date

+1.8VSP

12

12

PC422

PC423

22U_0805_6.3VAM

22U_0805_6.3VAM

PJP405

2

112

JUMP_43X118@

1.8VSP
TDC 1.25 A
Peak Current 1.75 A
OCP current 4 A

Compal Electronics, Inc.

Title

PWR+VCCPP/+1.8VSP

Size Document Number Rev

C

LA-6801P

2

Date: Sheet of

1

+1.8VS+1.8VSP

54 60Monday, December 06, 2010

0.1

5

4

3

2

1

D D

PR501

PR509

1 2

2K_0402_1%

PR524

1 2

10K_0402_1%

267K_0402_1%

1 2

1 2

SA_PGOOD<31>

PR518

267K_0402_1%

1 2

1 2

DGPU_PWROK<16,17,38,39,56>

4

PU501

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

PR526

10K_0402_5%

1 2

PR527
0_0402_5%

PU502

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

PR529

10K_0402_5%

1 2

PR530
0_0402_5%

3 5

241

5

4

123

6

578

4

123

786

5

4

123

BST_SAP-1

12

BST_1.35V-1

12

PC507

0.1U_0603_25V7K

1 2

+5VALW

PC512

4.7U_0805_10V6K

PC522

0.1U_0603_25V7K

1 2

+5VALW

PC528

4.7U_0805_10V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

PR503

15

14

1

NC

13

BOOT
UGATE

EN/DEM

VFB=0.75V

GND7PGND

1

EN/DEM

VFB=0.75V

GND7PGND

12

PHASE

11

CS

10

VDDP

9

LGATE

RT8209BGQW_WQFN14_3P5X3P5

8

+3VS

VID[0] VID[1] VCCSA Vout Required on 2011 / 2012 Req uired

0 0 0.9V Yes / Yes

0 1 0.8V Yes / Yes

15

14

NC

13

BOOT
UGATE

12

PHASE

11

CS

10

VDDP

9

LGATE

RT8209BGQW_WQFN14_3P5X3P5

8

+3VS

add 10/19
for EE request

BST_SAP

DH_SAP

LX_SAP

1 2

PR505

10.7K_0402_1%

BST_1.35V

DH_1.35V

LX_1.35V

1 2

PR522

5.76K_0402_1%

2.2_0603_5%

1 2

DL_SAP

revise 9/21
RF request

PR520

2.2_0603_5%

1 2

DL_1.35V

PR502

PR511
10K_0402_5%

PR514

10K_0402_5%

1 2

PR516

@

100K_0402_5%

+5VALW

0_0402_5%

1 2

PR504

10_0603_5%

1 2

1U_0603_10V6K

12

@

PR519

@

100K_0402_1%

1 2

PR528

0_0402_5%

1 2

PR523
10_0603_5%

1 2

1U_0603_10V6K

PC515

PC511

2

G

.1U_0402_16V7K

PC531

12

PC506

.1U_0402_16V7K@

12

12

PR512
15K_0402_1%

13

D

S

SSM3K7002F_SC59-3
PQ503

12

PC523

.1U_0402_16V7K

12

12

PR513
30K_0402_1%

12

PR525
10K_0402_1%

VTTPWRGOOD<54>

+5VALW

C C

+3VS

VCCSA_SEL

1 2

PR515

1 2

0_0402_5%

PR517

@

10K_0402_5%

1 2

B B

1

2

12

3

PQ504

PMBT2222A_SOT23-3

DGPU_PWR_EN<16,33,43,56>

VGA_PWROK<56>

add 10/19
for EE request

A A

5

VCCSAP_B+

12

PC501

PQ501
AON7408L_DFN8-5

PQ502
SI7716ADN-T1-GE3_POWERPAK8-5

PQ505
AO4466L_SO8

PQ506
SI4634DY-T1-E3_SO8

2200P_0402_50V7K

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

12

PR506

4.7_1206_5%

12

PC513

680P_0402_50V7K

1.35V_B+

12

PC517

2200P_0402_50V7K

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

1 2

12

PR521

4.7_1206_5%

12

PC529

680P_0402_50V7K

revise 9/21
RF request

PC502

PL502

PC518

PL504

12

0.1U_0603_25V7K

12

12

0.1U_0603_25V7K

12

12

PC504

PC503

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PC510

PC509

.1U_0402_16V7K

10_0402_5%

12

1 2

PC524

PR510

0_0402_5%

1 2

12

PC520

4.7U_0805_25V6-K

12

PC527

.1U_0402_16V7K

10U_0805_6.3V6M

10U_0805_6.3V6M

PR507

PC519

4.7U_0805_25V6-K

Low Side MOS RDS(on)=5.5m ohm(Typ),6.7m ohm(Max)

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

2

PJP501

2

112

JUMP_43X79@

CPU_IN_B+

+VCCSAP
TDC 4.2A
Peak Current 6 A
OCP current 7.2 A

Low Side MOS RDS(on)=13.5m ohm(Typ),16.5m ohm(Max)

+VCCSAP

1

12

+

PC508

PR508

2

0_0402_5%

330U_D2_2.5VY_R9M

12

PC521

4.7U_0805_25V6-K

@

1 2

VCCSA_SENSE <10>

PL503

@

HCB2012KF-121T50_0805

1 2

PJP503

2

JUMP_43X79@

112

VSSSA_SENSE <10>

GPU_IN_B+

12

PC516

@

680P_0402_50V7K

PJP502

2

112

JUMP_43X118@

+VCCSA+VCCSAP

+1.5VSDGPUP

12

+

+

PC526

PC525

2

2

220U_D2_2VY_R15M

220U_D2_2VY_R15M

@

1.5VSDGPUP (for VRAM)
TDC 5.6 A
Peak Current 8 A
OCP current 9.6 A

Compal Electronics, Inc.

Title

PWR-+VCCSAP/+1.5VSDGPUP

Size Document Number Rev

C

LA-6801P

Date: Sheet of

1

1

PJP504

2

112

JUMP_43X118@

PJP505

2

112

JUMP_43X118@

1

+1.5VSDGPU+1.5VSDGPUP

55 60Monday, December 06, 2010

0.1

5

N12E-GE-B
(N11E-GE for SSI)

VGA_CORE

GPU_VID0GPU_VID1

0.825V

11

0

0

0

D D

add 10/19
for EE request

PR623

1 2

PC606

1000P_0402_50V7K

PR625

C C

97.6K_0402_1%

1 2

PR628

255_0402_1%

1 2

+NVVDD_SENSE<40>

+VGA_CORE

平平平平平平平平平平平平

10_0402_5%

from output Bulk Cap

10_0402_5%

1 2

GND_SENSE<40>

B B

470P_0402_50V7K

PC613

220P_0402_50V8J

1 2

PR626

1K_0402_1%

12

1000P_0402_50V7K

1 2

PR630

12

PR638

PC611

1 2

PC621

0_0402_5%

PR629

12

PR639

0_0402_5%

0.875V

1

0.925V

PR648

5.49K_0402_1%

1 2

1 2

PC608

0.047U_0402_16V7K

PC623

330P_0402_50V7K

1 2

1 2

PC625

1000P_0402_50V7K

PC629

1 2

0.22U_0402_6.3V6K

0_0402_5%

PR603

@

0_0402_5%

PR616

1 2

36.5K_0402_1%

@

PC630

.1U_0402_16V7K

PR617

1K_0402_1%

1 2

VGA_PWROK<55>

DGPU_PWROK<16,17,38,39,55>

VCC_PRM

1 2

PR615

PC607

@

1 2

1000P_0402_50V7K

6.81K_0402_1%

1 2

PC622

@

330P_0402_50V7K

12

4

+3VS_DELAY

PR647

add 10/19
for EE request

12

12

1 2

150K_0402_1%

PR631

VCC_PRM

PC631

0_0402_5%

+3VS

PC634

+3VS

PR602

10K_0402_5%

1 2

+3VS

1 2

PR605 0_0402_5%

PR606

PR612

1 2

1 2
@

10K_0402_5%

10K_0402_5%

40

PGOOD

1

SET

2

RBIAS

3

OFS

4

SOFT

5

OCSET

6

VW

7

COMP

8

FB

9

VDIFF

10

VSEN

41

GND PAD

11

PC626

180P_0402_50V8J

1 2

PR632

787_0402_1%

12

1 2

Close to Phase1 Choke PL18

PR642

1 2

11K_0402_1%

1 2

.1U_0402_16V7K

PR643

2.61K_0402_1%

PR604

12

10K_0402_1%@

1 2

+3VS_DELAY

.1U_0402_16V7K

PR607 0_0402_5%

1 2

37

38

39

PSI_L

VR_ON

PU601

ISL6264CRZ-T_QFN40_6X6

DFB

13

PH601

1 2

1 2

10K_0603_5%_TSM1A103J4302RE

VSUM

+3VS_DELAY

DGPU_PWR_EN<16,33,43,55>

12

+3VS_DELAY

PR608 10K_0402_5%

PR613 10K_0402_5%

1 2

15

1 2

1 2

VIN16VO14DROOP12RTN

18

B+

PR641

PR640

10_0402_5%

1 2

PC632

PC633

1 2

0.01U_0402_50V7K

PR609
10K_0402_5%

1 2

+3VS_DELAY

PR610
10K_0402_5%

1 2

PQ610

13

D

2N7002W-T/R7_SOT323-3

S

PR611

PR614 10K_0402_5%

31

VID032VID133VID234VID335VID436VID5

BOOT1

30

UGATE1

29

PHASE1

28

PGND1

27

LGATE1

26

PVCC

25

LGATE2

24

PGND2

23

PHASE2

22

UGATE2

21

BOOT2

ISEN219GND17VSUM

ISEN120VDD

VGA_ISEN1

VGA_ISEN2

+5VS

10_0402_5%

1 2

12

1U_0402_6.3V6K

3

PR644
0_0402_5%

1 2

+3VS_DELAY

PR645
10K_0402_5%

1 2

PR646

2

G

1 2

2.2_0603_5%

PR627

2.2_0603_5%

0.22U_0603_25V7K

VGA_CORE
TDC 36.8 A
Peak Current 46 A
OCP current 55 A
Cesr=9 mOHM
DCR=1.48 mOHM+-7%

1 2

PC605

0.22U_0603_25V7K

1 2

PR624 0_0402_5%

12

PC612

4.7U_0603_6.3V6K

UG_VGA2

12

1 2

PC624

0_0402_5%

12

UG_VGA1

PHASE_VGA1

LG_VGA1

+5VS

PHASE_VGA2

LG_VGA2

modify 8/11

GPU_VID1 <45>

GPU_VID0 <45>

VGA_B+

5

4

123

PQ601

AON6414AL_DFN8-5

5

4

123

5

4

123

5

4

123

5

4

AON6702L_DFN8-5

PQ603

PQ605

AON6414AL_DFN8-5

4

AON6702L_DFN8-5

PQ607

AON6702L_DFN8-5

PQ604

123

VGA_B+

PC614

5

AON6702L_DFN8-5

PQ608

123

2

12

12

PC602

PC601

4.7U_0805_25V6-K

2200P_0402_50V7K

0.42UH_FDUE0640-R42M_20.2A_20%~D

PR620

10K_0402_1%

1 2

PR618

4.7_1206_5%
PR619

1 2

PC610

VSUM

680P_0603_50V7K

12

PC616

PC615

4.7U_0805_25V6-K

1 2

PR637

1 2

3.65K_0805_1%

VSUM

680P_0603_50V7K

0.22U_0603_16V7K

3.65K_0805_1%

VGA_ISEN1 VCC_PRM

12

PC617

4.7U_0805_25V6-K

PL603

PR633

10K_0402_1%

PC627

0.22U_0603_16V7K

1 2

1 2

12

12

2200P_0402_50V7K

0.42UH_FDUE0640-R42M_20.2A_20%~D

PR636

1 2

4.7_1206_5%

12

PC628

PC603

4.7U_0805_25V6-K

PL602

PC609

1 2

12

4.7U_0805_25V6-K

12

12

12

PC604

4.7U_0805_25V6-K

12

PR621

1 2

+

PR634

1_0402_5%

1 2

VCC_PRMVGA_ISEN2

PL601

HCB2012KF-121T50_0805

1 2

PR622

1_0402_5%

10K_0402_1%

1 2

VGA_ISEN2

1

1

+

+

2

2

PC619

PC618

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

PR635
10K_0402_1%

1 2

VGA_ISEN1

GPU_IN_B+

+VGA_CORE

1

2

PC620

330U_D2_2.5VY_R9M

+VGA_CORE

revise 10/25
design change

PR601

0.01_1206_1%

1

2

GPU_VIN-<58> GPU_VIN+<58>

+VGA_CORE

1

4

3

B+

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

VGA_CORE

Size Document Number Rev

C

LA-6801P

Date: Sheet

1

of

56 60Monday, December 06, 2010

0.1

5

12

PR702

D D

@

12

PR706

499K_0402_1%

IMONG

8.06K_0402_1%

39P_0402_50V8J
PC716

150P_0402_50V8J

12

PC711

12

12

PR718

PC720

VSS_AXG_SENSE<10>

18.2K_0402_1%

revise 8/23

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VSSSENSE<9>

PR737

@

1 2

499_0402_1%

PR773

10K_0402_5%

PQ720B

VR_SVID_CLK<9>

1 2

PR750

@

499K_0402_1%

+3VALW

12

5

PR775
100K_0402_5%@

1 2

12

PR736

12

43P_0603_50V8

150P_0402_50V8J

+5VS

12

PR771
10K_0402_5%

Quad_SEL#

3

4

12

PC730

18.7K_0402_1%

0.047U_0603_25V7M

PC735

PR738

1 2

3.83K_0402_1%

12

PR741

8.06K_0402_1%

39P_0402_50V7K

12

PC752

+5VS

12

2

PR774
100K_0402_5%@

PQ720A
DMN66D0LDW-7 2N SOT363-6

+3VS

VGATE<6,15,31>

@

470P_0402_50V7K

12

PC741

PC748

12

PR754
316K_0402_1%

12

PR772
10K_0402_5%

Quad_SELQuad_SEL#

61

PC736

1000P_0402_50V7K

Alert# PU resister need close CPU,
s

o the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.

C C

IMON

VR_HOT#

+VCCP

B B

CPU_SEL<31>

DMN66D0LDW-7 2N SOT363-6

A A

PC708

12

PR712

12

475K_0402_1%

1 2

PC724

0.047U_0603_25V7M

@

.1U_0402_16V7K

VR_ON<31>

1 2

PR734

1.91K_0402_1%

12

1 2

470KB_0402_5%_ERTJ0EV474J

PR739

27.4K_0402_1%

PR768
2K_0402_1%

12

PR751
499_0402_1%

PR755

3.74K_0603_1%~D

D

1 3

Quad_SEL#

+VCC_CORE

12

1000P_0402_50V7K

PR710

12

422_0402_1%

PR713

2.43K_0402_1%

+VCCP

12

PR720

PR722

130_0402_1%

VGATEG

PR733

1 2

0_0402_5%

PH703

12

12

12

PC768
680P_0402_50V7K

PC749

12

12

470P_0402_50V7K

12

S

PR770

@

5.11K_0402_1%

PQ718

G

2

2N7002W-T/R7_SOT323-3

PR757
10_0402_1%@

VCCSENSE<9>

VSSSENSE<9>

PR759
10_0402_1%@

PC712

330P_0402_50V7K

12

12

+3VS

54.9_0402_1%

12

PR724

SVID_SDA

SVID_ALERT#

SVID_SCLK

12

12

12

Quad & Dual CORE selection

L

PR758//PR769

TBD

953

PR755//PR770

TBD

3.74k

CORE

Dual

Quad

(Default)

CPU_SEL

L

H

Quad_SEL Quad_SEL#

L H

H

5

PC767
470P_0402_50V7K

12

revise 10/25

1

2

1.91K_0402_1%

3

4

5

6

7

8

9

10

11

12

VSUM-

0.01U_0402_16V7K

4

3.83K_0402_1%

PR701

12

@

470P_0402_50V7K

12

12

PR767

4.99K_0402_1%

PC701

12

470KB_0402_5%_ERTJ0EV474J

1 2

PR703

27.4K_0603_1%~D

12

PC713

330P_0402_50V7K

ISPG

ISNG

48

49

46

44

45

VWG

IMONG

47

FBG

GND

COMPG

43

ISPG

ISNG

RTNG

VSENG

PGOODG

SDA

ALERT#

SCLK

VR_ON

PGOOD

IMON

ISL95831CRZ-T_TQFN48_6X6

VR_HOT#

NTC

VW

COMP13FB14ISEN3/ FB215ISEN216ISEN117VSEN18RTN19ISUMN20ISUMP21VDD22VIN23PROG1

PC743

@

10P_0402_25V8J

12

ISEN1

PC745

PC750

PC751

ISEN3

12

0.22U_0402_6.3V6K

12

0.22U_0402_6.3V6K

12

0.22U_0402_6.3V6K

ISEN2

revise 10/25

PC760

12

330P_0402_50V7K

12

PC762

12

PC761

330P_0402_50V7K

PROG1

4.32k

0

4

PH701

12

PC710

330P_0402_50V7K

1 2

PC714

0.01U_0402_16V7K

NTCG

16.5K_0402_1%

PR721

@

1 2

41

42

NTCG

PROG2

PC753

@

PR769

@

1.27K_0402_1%

1

+

+

PC780

2

@

470U_D2_2VM_R4.5M

revise 9/21

12

UGATEG

BOOTG

39

40

UGG

BOOTG

12

PC746

1U_0603_10V6K

12

0.068U_0402_16V7K

12

PR758
953_0402_1%

12

Quad_SEL#

1

+

PC781

2

@

470U_D2_2VM_R4.5M

NTCG

10_0402_1%

LGATEG

PHASEG

37

38

LGG

PHG
BOOT2

UG2

PH2

VSSP2

LG2

VDDP

PWM3

LG1

VSSP1

PH1

UG1

BOOT1

24

PR742

0_0603_5%

1 2

PR745

1_0603_5%

12

0.22U_0603_25V7K

PC747

12

PC754

D

1 3

3

+VCC_GFXCORE_AXG

PR704

12

PR714

12

10_0402_1%

BOOT2

36

UGATE2

35

PHASE2

34

33

LGATE2

32

31

30

LGATE1

29

28

PHASE1

27

UGATE1

26

BOOT1

25

PU701

CPU_B+

12

+5VS

12

PR756

PC755

0.068U_0402_16V7K

@

0.47U_0603_16V7K

S

PQ717

G

2

2N7002W-T/R7_SOT323-3

+VCC_CORE

VCC_AXG_SENSE <10>

VSS_AXG_SENSE <10>

12

PR716

0_0603_5%

12

PR725

0_0603_5%

12

13

D

2

G

PQ719

S

PR740

0_0402_5%

2N7002W-T/R7_SOT323-3

oot=0

Vb

VSUM+

12

PR753

2.61K_0402_1%

12

12

PH704
10K_0402_5%_ERTJ0ER103J

11K_0402_1%

VSUM-

12

PC763

.1U_0402_16V7K

UGATEG

PHASEG

BOOTG

+5VS

12

PC718

1U_0603_10V6K

PU702

5

VCC

BOOT

6

FCCM

UGATE

2

PWM

PHASE

3

LGATE

GND

PGND

ISL6208ACRZ-T_QFN8_3X3

PR729

@

0_0603_5%

1 2

PR730

1 2

0_0603_5%

12

12

PC731

PC732

1U_0603_10V6K

UGATE2

PHASE2

Quad_SEL

BOOT2

@

LGATE2

UGATE1

PHASE1

BOOT1

LGATE1

LGATEG

1

8

7

4

9

1U_0603_10V6K

PR743

2.2_0603_5%

PR760

2.2_0603_5%

PR705

2.2_0603_5%

PR719

2.2_0603_5%

PC722

0.1U_0603_25V7K

+5VS

PC742

0.1U_0603_25V7K

12

PC764

0.1U_0603_25V7K

12

12

PC709

0.1U_0603_25V7K

12

12

12

2

CPU_B+

5

PQ701

4

12

4

12

PQ705

4

5

PQ702

4

AON6414AL-1N_DFN

123

5

PQ703

4

AON6702L-1N_DFN8

213

CPU_B+

5

PQ706

4

AON6414AL-1N_DFN

123

5

PQ707

4

AON6702L-1N_DFN8

213

5

PQ709

4

PQ710

4

AON6414AL-1N_DFN

123

5

PQ711

4

5

PQ713

4

123

5

PQ715

4

213

PQ712

4

AON6702L-1N_DFN8

213

5

PQ714

4

AON6414AL-1N_DFN

123

5

PQ716

4

AON6702L-1N_DFN8

213

1

PC782

2

@

Security Classification

470U_D2_2VM_R4.5M

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/24 2011/08/24

Compal Secret Data

Deciphered Date

2

4

5

5

CPU_B+

AON6414AL-1N_DFN

123

5

PQ704

213

5

123

213

AON6702L-1N_DFN8

HCB4532KF-800T90_1812

12

AON6414AL-1N_DFN

123

5

PQ708

CPU_B+

12

PC704

10U_0805_25V5K

PR709

4.7_1206_5%

AON6702L-1N_DFN8

12

PC725

PC726

10U_0805_25V5K

AON6414AL-1N_DFN

PR727

AON6702L-1N_DFN8

213

PC737

10U_0805_25V5K

AON6414AL-1N_DFN

12

12

PC705

PC706

PC707

10U_0805_25V5K

10U_0805_25V5K

10U_0805_25V5K

0.36UH_ETQP4LR36AFC_28A_20%~D

12

PR707

12

10K_0603_1%

PR711

1 2

7.5K_0402_1%

12

PC717

680P_0402_50V7K

@

12

12

12

PC727

PC728

10U_0805_25V5K

10U_0805_25V5K

10U_0805_25V5K

ISPG

0.36UH_ETQP4LR36AFC_28A_20%~D

12

4.7_1206_5%

12

PC729

12

PC738

10U_0805_25V5K

PR728

ISEN3

1 2

10K_0603_1%

PR732

VSUM+

1 2

3.65K_0603_1%

680P_0402_50V7K

@

12

12

12

PC739

PC740

10U_0805_25V5K

10U_0805_25V5K

0.36UH_ETQP4LR36AFC_28A_20%~D

12

PR744

4.7_1206_5%

12

PC744

AON6702L-1N_DFN8

12

PC757

PC756

10U_0805_25V5K

680P_0402_50V7K

10U_0805_25V5K

ISEN2

12

PC758

PR746

1 2

10K_0603_1%

PR748

VSUM+

1 2

3.65K_0603_1%

VSUM-

12

PC759

10U_0805_25V5K

10U_0805_25V5K

@

12

0.36UH_ETQP4LR36AFC_28A_20%~D

12

PR761

4.7_1206_5%

12

PC765

PR762

ISEN1

1 2

10K_0603_1%

680P_0402_50V7K

PR764

VSUM+

1 2

3.65K_0603_1%

VSUM-

Compal Electronics, Inc.

Title

PWR-CPU_CORE

Size Document Number Rev

Custom

LA-6801P

Date: Sheet of

1

1 2

PL701

PL702

4

3

PH702

10K_0402_5%_ERTJ0ER103J

1 2

1 2

PR715 11K_0402_1%

PC719

1 2

.1U_0402_16V7K

1 2

PC721

0.022U_0402_16V7K

487_0402_1%

PL703

4

3

PR735

VSUM-

1_0402_5%

1

1

+

+

PC733

2

2

100U_25V_M

PL704

4

3

PR752

12

1_0402_5%

DCR:0.82mOHM

PL705

4

3

PR766

12

1_0402_5%

1

PR723

12

PC734

PC703

@

1

2

1

2

100U_25V_M

1

2

12

PC702

@

680P_0402_50V7K

680P_0402_50V7K

+VCC_GFXCORE_AXG

12

PR708
1_0402_5%

PC715

.1U_0402_16V7K

PR717

@

1 2

100_0402_1%

12

revise 10/25

ISNG

PR726

10K_0402_1%

PR731

10K_0402_1%

add 10/26

1

design change

+

PC766

2

100U_25V_M

1

2

PR747

10K_0402_1%

PR749

10K_0402_1%

+VCC_CORE

PR763

10K_0402_1%

PR765

10K_0402_1%

57 60Monday, December 06, 2010

CPU_IN_B+

12

1 2

PC723

@

+VCC_CORE

ISEN1

12

ISEN2

12

+VCC_CORE

ISEN1

12

12

ISEN2

12

ISEN3

12

12

470P_0402_50V7K

ISEN3

0.1

5

4

3

2

1

VENTURA

D D

I2CB_SDA<44>

I2CB_SCL<44>

I2CB_SDA I2CB_DATA

+3VS_DELAY

2

61

PQ801A

@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

@

2.2K_0402_5%

5

PQ801B

+3VS

PR801

@

1 2

3

PR802

@

2.2K_0402_5%

1 2

I2CB_CLKI2CB_SCL

12

PR823
0_0402_5%

12

PR824
0_0402_5%

EC_SMB_DA2 <3 0,31,45>

EC_SMB_CK2 <3 0,31,45>

connect to EC 10/05

CPU_VIN+<54>

C C

CPU_VIN-<54>

GPU_VIN+<56>

GPU_VIN-<56>

12

PR803 0_0402_5%

12

PR806 0_0402_5%

PR804 0_0402_5%

1

PC801

@

2

0.1U_0402_16V7K
PR805 0_0402_5%

PR807 0_0402_5%

1

PC803

@

2

0.1U_0402_16V7K
PR808 0_0402_5%

1 2

1 2

1 2

1 2

PC802

PC804

@

1

@

2

0.1U_0402_16V7K

+3VS

1

2

0.1U_0402_16V7K

+3VS

PU801

1

VIN+

2

VIN-

3

GND

4

VS

INA219AIDCNRG4_SOT23-8

PU802

1

VIN+

2

VIN-

3

GND

4

VS

INA219AIDCNRG4_SOT23-8

SDA

SDA

SCL

SCL

A1
A0

A1
A0

CPU_A1

8

CPU_A0

7

I2CB_DATA

6

I2CB_CLK

5

GPU_A1

8

GPU_A0

7

I2CB_DATA

6

I2CB_CLK

5

B B

A A

5

+3VS +3VS

PR810

@

PR809

@

0_0402_5%

1 2

CPU_A1

PR819
0_0402_5%

1 2

Ventura for CPU side
slave address : 1000010
please placemnet near R-sense

1 2

@

1 2

0_0402_5%

CPU_A0

PR820
0_0402_5%

12

@

I2CB_DATA

12

PR813 0_0 402_5%

PR815
0_0402_5%

I2CB_CLK

12

PR817 0_0 402_5%@

4

PR811
0_0402_5%

1 2

PR821

@

0_0402_5%

1 2

Ventura for GPU side
slave Address 1000110
please placement near R-sense

1 2

@

1 2

0_0402_5%

GPU_A0

PR822
0_0402_5%

12

PR814 0_0402_5%

12

PR816

@

0_0402_5%

12

PR818 0_0402_5%@

PR812

@

I2CB_DATA

I2CB_CLKGPU_A1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

VENTURA

Size Document Number Rev

Custom

LA-6801P

Date: Sheet

1

of

58 60Monday, December 06, 2010

0.1

5

4

revise 8/09
ESD request

3

2

1

1

PD9

D D

PJP30 battery connector

C C

B B

BATT+ BATT++

PL3

SMB3025500YA_2P

BATT+

1 2

12

12

PC15

0.01U_0402_25V7K

PC13

100P_0402_50V8J

SMART

SMART

SMARTSMART
Battery:

Battery:

Battery:Battery:

11.BAT+

11.BAT+

11.BAT+11.BAT+

10.BAT+

10.BAT+

10.BAT+10.BAT+

9.BAT+

9.BAT+

9.BAT+9.BAT+

8.ID

8.ID

8.ID8.ID

7.B/I

7.B/I

7.B/I7.B/I

6.TS

6.TS

6.TS6.TS

5.SMD

5.SMD

5.SMD5.SMD

4.SMC

4.SMC

4.SMC4.SMC

3.GND

3.GND

3.GND3.GND

2.GND

2.GND

2.GND2.GND

1.GND

1.GND

1.GND1.GND

100K_0402_1%

SPOK<52>

BATT++

12

PC14
1000P_0402_50V7K

MOLEX_87437-1173_11P-T

SP020907230

@

+5VALW

PR44

1 2

1 2

11
10

9
8
7
6
5
4
3
2
1

PJP30

PR45
0_0402_5%

12

PC16

100P_0402_50V8J

11
10
9
8
7
6
5
4
3
2
1

B+

13

D

2

G

S

12

PC22

@

0.1U_0402_16V7K

+3VALWP

3S/4S#

1 2

PR34

100_0402_5%

1 2

PR37

100_0402_5%

12

PR43

22K_0402_1%

1 2

PQ11

2N7002W-T/R7_SOT323-3

1 2

PR42

100K_0402_1%

PR30
47K_0402_5%

12

PC20

@

0.22U_1206_25V7K

PJSOT24C_SOT23-3

2

3

PR32

1K_0402_5%

EC_SMB_DA1 <31>

EC_SMB_CK1 <31>

PQ10

TP0610K-T1-E3_SOT23-3

13

2

12

12

@

0.1U_0603_25V7K

1

PD10
PJSOT24C_SOT23-3

2

3

Place clsoe to E C pin

BATT_TEMP

1 2

PR31

1K_0402_5%

1 2

PR33

6.49K_0402_1%

B+_BIAS

PC21

PC17

0.1U_0402_16V7K

1 2

@

+3VALWP

BATT_TEMP <31>

Battery Connect/OTP

PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 50 degree C

VL VL

12

PH1

100K_0402_1%_TSM0B104F4251RZ

OTP-1

12

12

PC18

PR39

0.22U_0603_25V7K

PR38

13.7K_0402_1%

1 2

16.9K_0402_1%

PR36

47K_0402_1%

1 2

VL

8

OTP-2

5

P

1000P_0402_50V7K

+

6

-

PR40

12

100K_0402_1%

PR41
100K_0402_1%

G

4

OTP-4

12

PC19

modify 9/27
reduce S5 loss

OTP-3

7

0

PU1B
LM393DR_SO8

12

VL

1 2

PR35
47K_0402_1%

13

D

PQ9

2

G

S

MAINPWON <30,52>

2N7002W-T/R7_SOT323-3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/08/03 2011/08/03

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-BATTERY CONN

Size Document Number Rev

Custom

LA-6801P

2

Date: Sheet of

1

59 60Monday, December 06, 2010

0.1

5

Request

Request

Item

Item Issue Description

ItemItem

D D

C C

Page# Title

Page#Page#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 58 VENTURA

17 57 +CPU_CORE

18 52 3VALWP/5VALWP

19 51 CHARGER

50 PWR-DCIN / Vin Det ector reduce S5 loss add PU2;PR27;PC1 1;PC12

55 +VCCSAP/+1.5VSDGPU P RF request add PR521;PC529 change PR520 f rom 0 to 2.2

57 +CPU_CORE design change change PR703 fro m 0 to 27.4K

51 CHARGER desi gn change change PC131 from 0. 1u to 1u

54 +VCCPP/+1.8VSP design change modify 1.8VSP so lution

51 CHARGER EMI request add PC126;PC128

55 +VCCSAP/+1.5VSDGPU P EE request add PR528;PR529; PR530 del PR51 9

51 CHARGER desi gn change change PR114 from 47 K to 0

54 +VCCPP/+1.8VSP design change change PR401 fro m 0 to 0.01

56 +VGA_CORE

57 +CPU_CORE

57 +CPU_CORE

57 +CPU_CORE

Title

TitleTitle

Date

DateDate

10/09/17

10/09/21

10/09/21

10/10/06

10/10/07

10/10/07

10/10/19

10/10/19

10/10/19

10/10/25

10/10/25

10/10/25

10/10/25

10/10/25

10/10/25 COMPAL

10/10/26 COMPAL

10/10/27 COMPAL

10/12/06 COMPAL

RequestRequest
Owner

Owner

OwnerOwner

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

COMPAL

COMPAL

COMPAL 0.2

COMPAL 0.2

COMPAL

COMPAL 0.2

COMPAL

COMPAL 0.2

COMPAL

COMPAL 0.2

COMPAL

COMPAL

COMPAL

COMPAL

design change50 PWR-DCIN / Vin Det ector add PQ12;PC23

EE request56 +VGA_CORE add PR647;PR648 del PR603;PR60 4

design change change PR601 fro m 0 to 0.01

change CPU OCP s etting change PR758 fro m 887 to 953

change GFX OCP & LL setting change PR723 fro m 442 to 487 c hange PR713 from 2.61K to 2.43K

quad & dual core CPU switch set ting design

add ventura conn ect to EC

design change add PC766

design change add PR222

add CP point sel ect

3

Page 1

Page 1

Page 1Page 1

add PQ717;PQ718; PQ720;PR771;PR7 72;PR773;PR767;P R768;PC767;PC768

add PU801;PU802; PR803;PR804;PR8 05;PR806;PR807;P R808

;PR811;PR813;PR8 14;PR819;PR823; PR824

add PR142;PQ115

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

0.2

0.2

0.2

0.2

0.2

0.210/10/25 COMPAL

0.2

0.2

0.2

0.2

0.2

0.2

0.3

0.3

0.3

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2009/10/07 2012/09/28

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PWR-PIR

60 60Monday, December 06, 2010

1

0.1