Compal LA-6801P PALB0 Specter (Huron River), Alienware M14x Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-6801P ( DAB00000400 )

46198531L01
46198531L02

PALB0

Dell/Compal Confidential

Schematic Document

2 2

Specter (Huron River)

Sandy Bridge(PGA) + Cougar Point(standard)

DISCRETE VGA N12E-GE-B (optimus)

3 3

4 4

A

B

2010-12-06

Rev: 0.3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-6801P

E

1 60Monday, December 06, 2010

0.3

A

B

C

D

E

Compal Confidential

Project Code : PALB0

FFS

e Name : LA-6801P

Fil

1 1

HDMI
Conn.

DP Conn.

P.39

P.38

DP MUX

P.37

LVDS

2 2

Conn.

P.21

CRT Conn.

P.21

HDMI

DisplayPort

DisplayPort

DP (DIS)

DP

GPU
N12E-GE

P.40~45

PEG x16 (DIS)

LVDS

CRT

(UMA)

100MHz

2.7GT/s

DisplayPort

PCI-E x1

Port 3 Port 2 Port 1 Port 4

Mini Card-2

WLAN (Half)

USB[x]

3 3

port4

WWAN (Full)

USB[x]
port5

LAN(GbE)

AR8151-BL1A

RJ45

Card ReaderMini Card-1

RTS5209

P.22 P.23

9 in 1
Socket

DMC/Daughter Board

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

P.32

P.13

P.29

P.33

P.49~59

USB 3.0/2.0

USB 3.0/2.0
Com

P.23P.22

SPI ROM

Port 6

Host Ctrl.

P.27

bo Conns x2

P.27

ENE 3810

P.13 P.31

Intel

Sandy Bridge

Processor

4C 45W SV

rPGA 989 Socket

P.5~10

DMI x4FDI x8

100MHz
5GB/s

Intel

Cougar Point

PCH

BGA 989 Balls

P13~20

P

I

S

P.31

Touch Pad Int.KBD

LPC Bus

ENE KB930

P.35

P.

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MHz

SATA2.0

Port 0

Port 2

Port 4

USB2.0

Port 5

Port 6

HD Audio

Port 8

BIOS ROM

29 P.31

Port 0

Port 2

Fan Control

P.28

204pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

SATA HDD Conn.

SATA ODD Conn.

USB 2.0

( USB Charger )

Digital Camera

Mini Card-1 (WLAN)

( Half )

Mini Card-2 (WWAN)

( Full )

AlienFX/ELC

BT 2.1 /BT 3.0

Audio Codec
ALC665-GR

TI TPA6017A2

Int. Speaker

P.30

CPU XDP
Conn.

P.11,12

P.28

P.28

P.26

P.21

P.32

P.32

P.34~36

P.32

P.24

P.25

P.25

P.6

DMC/Daughter Board

SIM Card

P.32

TPA6211A

sub-woofer conn.

Audio Jack x3

( HeadPhone x2, MIC)

Digital MIC

P.25

P.25

P.25

P.24

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-6801P

E

2 60Monday, December 06, 2010

0.3

A

Compal Confidential

Project Code : PALB0

ile Name : LA-6801P

F

B

C

D

E

1 1

LA-6801P M/B

Camera

40 pin

Wire

LCD Panel

Blue Tooth

LS-6801P

LS-6803P

INDICATOR/B

2 2

Led-Wireless

Led-CapsLock

Wire

6 pin

BTB conn.

WLAN WWAN/DMC

80 pin

DMC/B

14 pin

Wire

12 pin

Wire

20 pin

HDD

ODD

LF-6801P

FPC

FFC

20 pin

Wire

6 pin

FFC

12 pin

LS-6802P

TP LED/B

Touch Pad

3 3

FFC

4 pin

Led x 6

Lid

LS-6809P

LOGO LIGHT GUIDE/B

Led x 6

LS-6806P

POWER BUTTON/B

on/off SW

Led x 3

4 pin4 pin

WireWire

LS-6807P

LS-6808P

FRONT LIGHT L/B

Led x 2 Led x 2

4 4

A

FRONT LIGHT R/B

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

D

Date: Sheet of

Title

Size Document Number Rev

Compal Electronics, Inc.

Block Diagram

E

3 60Monday, December 06, 2010

0.3

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SOURCE

KB930

KB930

PCH

PCH

AD_BID

0.168 V

0.375 V 0.503 V
0

0.958 V

1.372 V

1.851 V

2.433 V

MINI2

MINI1 BATT SODIMM

V V

.634 V

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

Thermal
Sensor 1

V V

V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal
Sensor 2

max

FFS VGA

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal
Sensor

V

V V

A

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

DMCVXDP

Charger

V

V

PCB Revision

0.1

0.2

0.3

0.4

0.5

Link

PCH

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

DESTINATION

None

JUSB1 (2.0 Ext Left Side)

Bluetooth

CAMERA

J

MINI1 (WLAN)

JMINI2 (WWAN/DMC)

ELC 8051

None

None

None

None

None

12

CLKOUT

1 1

PCI0

PCI1

PCI2

PCI3

PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

None

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7 None

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN

MINI CARD-2 WWAN

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

None

ODD

None

None

None

Symbol Note :

: means Digital Ground

: means Analog Ground

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

13

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

None

None

DESTINATION

10/100/1G LAN

MINI CARD-2 WWAN/DMC

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-6801P

4 60Monday, December 06, 2010

0.3

5

D D

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>

C C

B B

FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

+VCCP

1 2

RC36 24.9_0402_1%

R1942 10K_0402_5%~D

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

12

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

CONN@

DMI

Intel(R) FDI

eDP

4

+VCCP

12

RC2

24.9_0402_1%

PEG_COMP

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

CC200 220nF_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CC199 220nF_0402_16V7K
CC198 220nF_0402_16V7K
CC197 220nF_0402_16V7K
CC196 220nF_0402_16V7K
CC195 220nF_0402_16V7K
CC194 220nF_0402_16V7K
CC193 220nF_0402_16V7K
CC192 220nF_0402_16V7K
CC191 220nF_0402_16V7K
CC190 220nF_0402_16V7K
CC189 220nF_0402_16V7K
CC188 220nF_0402_16V7K
CC187 220nF_0402_16V7K
CC186 220nF_0402_16V7K
CC185 220nF_0402_16V7K

CC216 220nF_0402_16V7K
CC215 220nF_0402_16V7K
CC214 220nF_0402_16V7K
CC213 220nF_0402_16V7K
CC212 220nF_0402_16V7K
CC211 220nF_0402_16V7K
CC210 220nF_0402_16V7K
CC209 220nF_0402_16V7K
CC208 220nF_0402_16V7K
CC207 220nF_0402_16V7K
CC206 220nF_0402_16V7K
CC205 220nF_0402_16V7K
CC204 220nF_0402_16V7K
CC203 220nF_0402_16V7K
CC202 220nF_0402_16V7K
CC201 220nF_0402_16V7K

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

3

PEG_ICOMPI and R COMPO signals s hould be shorted and routed
with - max lengt h = 500 mils - typical impedanc e = 43 mohms
PEG_ICOMPO signa ls should be ro uted with - max length = 500 mil s

- typical impeda nce = 14.5 mohm s

PEG_GTX_C_HRX_N15 <40>
PEG_GTX_C_HRX_N14 <40>
PEG_GTX_C_HRX_N13 <40>
PEG_GTX_C_HRX_N12 <40>
PEG_GTX_C_HRX_N11 <40>
PEG_GTX_C_HRX_N10 <40>
PEG_GTX_C_HRX_N9 <40>
PEG_GTX_C_HRX_N8 <40>
PEG_GTX_C_HRX_N7 <40>
PEG_GTX_C_HRX_N6 <40>
PEG_GTX_C_HRX_N5 <40>
PEG_GTX_C_HRX_N4 <40>
PEG_GTX_C_HRX_N3 <40>
PEG_GTX_C_HRX_N2 <40>
PEG_GTX_C_HRX_N1 <40>
PEG_GTX_C_HRX_N0 <40>

PEG_GTX_C_HRX_P15 <40>
PEG_GTX_C_HRX_P14 <40>
PEG_GTX_C_HRX_P13 <40>
PEG_GTX_C_HRX_P12 <40>
PEG_GTX_C_HRX_P11 <40>
PEG_GTX_C_HRX_P10 <40>
PEG_GTX_C_HRX_P9 <40>
PEG_GTX_C_HRX_P8 <40>
PEG_GTX_C_HRX_P7 <40>
PEG_GTX_C_HRX_P6 <40>
PEG_GTX_C_HRX_P5 <40>
PEG_GTX_C_HRX_P4 <40>
PEG_GTX_C_HRX_P3 <40>
PEG_GTX_C_HRX_P2 <40>
PEG_GTX_C_HRX_P1 <40>
PEG_GTX_C_HRX_P0 <40>

PEG_HTX_C_GRX_N15 <40>
PEG_HTX_C_GRX_N14 <40>
PEG_HTX_C_GRX_N13 <40>
PEG_HTX_C_GRX_N12 <40>
PEG_HTX_C_GRX_N11 <40>
PEG_HTX_C_GRX_N10 <40>
PEG_HTX_C_GRX_N9 <40>
PEG_HTX_C_GRX_N8 <40>
PEG_HTX_C_GRX_N7 <40>
PEG_HTX_C_GRX_N6 <40>
PEG_HTX_C_GRX_N5 <40>
PEG_HTX_C_GRX_N4 <40>
PEG_HTX_C_GRX_N3 <40>
PEG_HTX_C_GRX_N2 <40>
PEG_HTX_C_GRX_N1 <40>
PEG_HTX_C_GRX_N0 <40>

PEG_HTX_C_GRX_P15 <40>
PEG_HTX_C_GRX_P14 <40>
PEG_HTX_C_GRX_P13 <40>
PEG_HTX_C_GRX_P12 <40>
PEG_HTX_C_GRX_P11 <40>
PEG_HTX_C_GRX_P10 <40>
PEG_HTX_C_GRX_P9 <40>
PEG_HTX_C_GRX_P8 <40>
PEG_HTX_C_GRX_P7 <40>
PEG_HTX_C_GRX_P6 <40>
PEG_HTX_C_GRX_P5 <40>
PEG_HTX_C_GRX_P4 <40>
PEG_HTX_C_GRX_P3 <40>
PEG_HTX_C_GRX_P2 <40>
PEG_HTX_C_GRX_P1 <40>
PEG_HTX_C_GRX_P0 <40>

2

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

Sandy Bridge_rPGA_Rev1p0

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-6801P

1

of

5 60Monday, December 06, 2010

0.3

5

XDP_PREQ#_R
XDP_PRDY#_R

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

CFG10_R

RC130_0402_5%~D @

1 2
1 2

1 2
1 2

1 2

12

RC150_0402_5%~D @

12

RC221K_0402_5%~D
RC230_0402_5%~D

RC241K_0402_5%~D
RC260_0402_5%~D

RC30

CFG11_R

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_XD P
CFD_PWRBTN#_X DP

XDP_HOOK2
SYS_PWROK_XDP

XDP_TCK1
XDP_TCK_R

D D

C C

CFG10<8>
CFG11<8>

H_CPUPWRGD

CFG0<8>

VGATE<15,31,57>

PCH_JTAG_TCK<13>

The resistor
for HOOK2 should be
placed such that the
stub is very sma ll
on CFG0 net

PCH_SMBDATA<11,12,14,28,32>
PCH_SMBCLK<11,12,14,28,32>

0_0402_5%~D @

+VCCP +VCCP

+3VALW

12

@

RC27
1K_0402_5%~D

SYS_PWROK_XDP

4

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

CONN@

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

JCPU1B

3

PM_DRAM_PWR GD<15>

PCH_PWROK<15,31>

SYS_PWROK<15>

+3V_PCH

1 2

2

CFG16_R

RC3 0_0402_5%~D@

4

CFG17_R

6
8

CFG0_R

10

CFG1_R

12
14

CFG2_R

16

CFG3_R

18
20

CFG8_R

22

CFG9_R

24
26

CFG4_R

28

CFG5_R

30
32

CFG6_R

34

CFG7_R

36
38

CLK_CPU_ITP

40

CLK_CPU_ITP#

42
44

XDP_RST#_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#_R

54

XDP_TDI

56

XDP_TMS_R

58
60

1 2

RC5 0_0402_5%~D@

1 2

RC7 0_0402_5%~D@

1 2

RC9 0_0402_5%~D@

1 2

RC10 0_0402_5%~D@

1 2

RC12 0_0402_5%~D@

1 2

RC14 0_0402_5%~D@

1 2

RC16 0_0402_5%~D@

1 2

RC17 0_0402_5%~D@

1 2

RC18 0_0402_5%~D@

1 2

RC20 0_0402_5%~D@

1 2

RC21 0_0402_5%~D@

1 2

1 2

RC25 1K_0402_5%~D

RC28 0_0402_5%~D@

1 2

RC31 0_0402_5%~D@

1 2

RC29 0_0402_5%~D@

1 2

+VCCP

0.1U_0402_16V7K~D

1

CC67

2

CFG16 < 8>
CFG17 < 8>

CFG0 <8>
CFG1 <8>

CFG2 <8>
CFG3 <8>

CFG8 <8>
CFG9 <8>

CFG4 <8>
CFG5 <8>

CFG6 <8>
CFG7 <8>

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,31>

PLT_RST#

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

0.1U_0402_16V7K~D

1

CC66

2

Place near JXDP1

0_0402_5%~D

RC4

200_0402_1%

2

RC128

@

RC127

1 2

1 2

0_0402_5%~D

1 2

RC11 0_0402_5%~D

RUN_ON_CPU1.5VS3#<10,33>

PLT_RST#<16,22,23,27,31,32>

+3VS

12

@

RC6

10K_0402_5%~D

D_PWG

1
2

+3VALW

UC1

5

B

VCC

A

4

GND3Y

74AHC1G09GW TSSOP 5P

RUN_ON_CPU1.5VS3#

UC2

1

NC

VCC

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

5

4

1

2

2

G

+3VALW

0.1U_0402_16V7K~D

+1.5V_CPU_VDDQ

CC65

12

RC19
39_0402_1%

1 2

13

D

QC1
SSM3K7002F_SC59-3

S

0.1U_0402_16V7K~D

1

CC68

2

BUFO_CPU_RST#

1

RC8
200_0402_1%

VDDPWRGOOD

RC8
CRB 1.1K
CHECK LIST 0.7 - -> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev --> 200

+VCCP

12

RC32
75_0402_5%

RC33

1 2

43_0402_1%

BUF_CPU_RST#

12

@

RC34
0_0402_5%~D

CLK_CPU_DMI_R

A28

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

BCLK

BCLK#

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H_SNB_IVB#<17>

+VCCP

RC41

RC49

RC53

RC57

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

T1PAD~D @

RC43

62_0402_5%

B B

A A

H_PROCHOT#<31>

1 2

H_THERMTRIP#<17>

H_PM_SYNC< 15>

H_CPUPWRGD<17>

H_PECI<17,31>

VDDPWRGOOD

1 2

56_0402_5%

1 2

0_0402_5%~D

1 2

0_0402_5%~D

1 2

130_0402_1%~D

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

CONN@

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

CLK_CPU_DMI#_R

A27

CLK_CPU_DPLL_R

A16

CLK_CPU_DPLL#_R

A15

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

DDR3 Compensation Signals

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

TCK

XDP_TMS

AR27

TMS

XDP_TRST#

AP30

XDP_TDI_R

AR28

TDI

XDP_TDO_R

AP26

TDO

XDP_DBRESET#_R

AL35

XDP_BPM#0_R

AT28

XDP_BPM#1_R

AR29

XDP_BPM#2_R

AR30

XDP_BPM#3_R

AT30

XDP_BPM#4_R

AP32

XDP_BPM#5_R

AR31

XDP_BPM#6_R

AT31

XDP_BPM#7_R

AR32

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

2010/12/01 2011/12/01

RC37 0_0402_5%~D

1 2

RC38 0_0402_5%~D

1 2

RC39 0_0402_5%~D

1 2

RC40 0_0402_5%~D

1 2

H_DRAMRST# <7>

RC55140_0402_1%

1 2

RC5825.5_0402_1%

1 2

RC60200_0402_1%

1 2

for EMC request, close to CPU 7/26

RC121 0_0402_5%~D

1 2

RC122 0_0402_5%~D

1 2

RC123 0_0402_5%~D

1 2

RC124 0_0402_5%~D

1 2

RC125 0_0402_5%~D

1 2

RC50 0_0402_5%~D

1 2

RC51 0_0402_5%~D

1 2

RC56

1 2

RC59 0_0402_5%~D

1 2

RC61 0_0402_5%~D

1 2

RC62 0_0402_5%~D

1 2

RC63 0_0402_5%~D

1 2

RC64 0_0402_5%~D

1 2

RC65 0_0402_5%~D

1 2

RC66 0_0402_5%~D

1 2

RC67 0_0402_5%~D

1 2

RC68 0_0402_5%~D

1 2

RC69 0_0402_5%~D

1 2

RC70 0_0402_5%~D

1 2

RC71 0_0402_5%~D

1 2

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI
XDP_TDO

close to CPU 7/26

XDP_DBRESET#

0_0402_5%~D

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

CFG12 < 8>
CFG13 < 8>
CFG14 < 8>
CFG15 < 8>

Compal Secret Data

Deciphered Date

2

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

CLK_CPU_DPLL <14>
CLK_CPU_DPLL# <14>

XDP_DBRESET# <15>

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_DBRESET#

H_CPUPWRGD_R

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-6801P

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

+VCCP

RC4551_0402_5%

RC4651_0402_5%

RC4751_0402_5% @

RC4851_0402_5%

RC5251_0402_5%

RC5451_0402_5%

+3VS

RC421K_0402_5%~D

RC4410K_0402_5%~D

6 60Monday, December 06, 2010

0.3

5

4

3

2

1

JCPU1C

M_CLK_DDR0

DDR_A_D[0..63]<11>

D D

C C

B B

A A

DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>

H_DRAMRST#<6>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_DRAMRST#

4.99K_0402_1%~D

5

RC77

AP11
AN11

AL12
AM12
AM11

AL11

AP12

AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

C5
D5
D3
D2
D6
C6
C2
C3

F10

F8

G10

G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2

M8

N10

N8
N7

M10

M9
N9

M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

V6

AE8
AD9
AF9

12

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

@

1 2

RC74 0_0402_5%~D

QC2

BSS138_SOT23

S

G

2

1

2

DDR SYSTEM MEMORY A

D

DDR3_DRAMRST#_R

13

DRAMRST_CNTRL

CC69
.047U_0402_16V7K~D

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

AH2

RSVD_TP[10]

C4

SA_DQS#[0]

G6

SA_DQS#[1]

J3

SA_DQS#[2]

M6

SA_DQS#[3]

AL6

SA_DQS#[4]

AM8

SA_DQS#[5]

AR12

SA_DQS#[6]

AM15

SA_DQS#[7]

D4

SA_DQS[0]

F6

SA_DQS[1]

K3

SA_DQS[2]

N6

SA_DQS[3]

AL5

SA_DQS[4]

AM9

SA_DQS[5]

AR11

SA_DQS[6]

AM14

SA_DQS[7]

AD10

SA_MA[0]

W1

SA_MA[1]

W2

SA_MA[2]

W7

SA_MA[3]

V3

SA_MA[4]

V2

SA_MA[5]

W3

SA_MA[6]

W6

SA_MA[7]

V1

SA_MA[8]

W5

SA_MA[9]

AD8

SA_MA[10]

V4

SA_MA[11]

W4

SA_MA[12]

AF8

SA_MA[13]

V5

SA_MA[14]

V7

SA_MA[15]

+1.5V

12

RC75
1K_0402_5%~D

1 2

RC76 1K_0402_5%~D

DG 1.0 Figure 61 RC76=1K

4

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

1 2

RC72 0_0402_5%~D

@

1 2

RC73 0_0402_5%~D

M_CLK_DDR0 <11>
M_CLK_DDR#0 <11>
DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL_EC <31>

DDR_B_D[0..63]<12>

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

Compal Secret Data

Deciphered Date

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

Sandy Bridge_rPGA_Rev1p0

CONN@

2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

Title

Size Document Number Rev

Date: Sheet of

M_CLK_DDR#2

AD2

DDR_CKE2_DIMMB

R9

M_CLK_DDR3

AE1

M_CLK_DDR#3

AD1

DDR_CKE3_DIMMB

R10

AB2
AA2
T9

AA1
AB1
T10

DDR_CS2_DIMMB#

AD3

DDR_CS3_DIMMB#

AE3
AD6
AE6

M_ODT2

AE4

M_ODT3

AD4
AD5
AE5

DDR_B_DQS#0

D7

DDR_B_DQS#1

F3

DDR_B_DQS#2

K6

DDR_B_DQS#3

N3

DDR_B_DQS#4

AN5

DDR_B_DQS#5

AP9

DDR_B_DQS#6

AK12

DDR_B_DQS#7

AP15

DDR_B_DQS0

C7

DDR_B_DQS1

G3

DDR_B_DQS2

J6

DDR_B_DQS3

M3

DDR_B_DQS4

AN6

DDR_B_DQS5

AP8

DDR_B_DQS6

AK11

DDR_B_DQS7

AP14

DDR_B_MA0

AA8

DDR_B_MA1

T7

DDR_B_MA2

R7

DDR_B_MA3

T6

DDR_B_MA4

T2

DDR_B_MA5

T4

DDR_B_MA6

T3

DDR_B_MA7

R2

DDR_B_MA8

T5

DDR_B_MA9

R3

DDR_B_MA10

AB7

DDR_B_MA11

R1

DDR_B_MA12

T1

DDR_B_MA13

AB10

DDR_B_MA14

R5

DDR_B_MA15

R4

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-6801P

1

M_CLK_DDR2

AE2

M_CLK_DDR2 <12>
M_CLK_DDR#2 <12>
DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12>
DDR_CS3_DIMMB# <12>

M_ODT2 <12>
M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

7 60Monday, December 06, 2010

0.3

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

L7

RSVD28

AG7

CFG0<6>
CFG1<6>
CFG2<6>
CFG3<6>
CFG4<6>
CFG5<6>
CFG6<6>
CFG7<6>
CFG8<6>
CFG9<6>

+VCC_CORE

@

RC80
50_0402_1%

C C

+V_DDR_REFA

+V_DDR_REFB

B B

RC82 0_0402_5%~D@

RC83 0_0402_5%~D@

+VCC_GFXCORE_AXG

1 2

1 2
1 2

RC84

1K_0402_1%~D

INTEL 12/28 reco mmand
to add 1k pull d own

VCCP_PWRCTRL<54>

1 2

@

RC79
50_0402_1%

12

VCC_AXG_VAL_SENSE

VCC_VAL_SENSE

12

RC85
1K_0402_1%~D

CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>
CFG16<6>
CFG17<6>

+V_DDR_REFA_R
+V_DDR_REFB_R

1 2

RC88 0_0402_5%~D

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

T19PAD~D @

T25PAD~D @
T26PAD~D @
T27PAD~D @

T30PAD~D @
T32PAD~D @
T33PAD~D @
T34PAD~D @
T35PAD~D @
T37PAD~D @
T38PAD~D @
T39PAD~D @
T40PAD~D @
T41PAD~D @
T42PAD~D @
T43PAD~D @

T44PAD~D @

H_VCCP_SEL

T49PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

RESERVED

Need PWR add new circuit on 1. 05V(refer CRB)

Sandy Bridge_rPGA_Rev1p0

CONN@

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

KEY

T2 PAD~D@
T3 PAD~D@
T4 PAD~D@
T5 PAD~D@
T6 PAD~D@

T7 PAD~D@
T8 PAD~D@
T9 PAD~D@

T10 PAD~D@
T11 PAD~D@
T12 PAD~D@
T13 PAD~D@

T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@
T18 PAD~D@

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
T23 PAD~D@
T24 PAD~D@

T29 PAD~D@T28PAD~D @
T31 PAD~D@

T36 PAD~D@

CLK_RES_ITP <14>
CLK_RES_ITP# <14>

T46 PAD~D@T45PAD~D @
T47 PAD~D@
T48 PAD~D@

T50 PAD~D@

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

12

RC78
1K_0402_1%~D

1:(Default) Norm al Operation; L ane #

CFG2

definition match es socket pin m ap definition

0:Lane Reversed

*

CFG4

12

RC81

@

1K_0402_1%~D

1 : Disabled; No Physical Displ ay Port

*

CFG4

attached to Embe dded Display Po rt

0 : Enabled; An external Displa y Port device is
connected to the Embedded Displ ay Port

CFG6

CFG5

12

12

RC87

@

1K_0402_1%~D

11: (Default) x1 6 - Device 1 fu nctions 1 and 2 disabled

*

10: x8, x8 - Dev ice 1 function 1 enabled ; func tion 2
disabled
01: Reserved - ( Device 1 functi on 1 disabled ; function

2 enabled)

00: x8,x4,x4 - D evice 1 functio ns 1 and 2 enabl ed

CFG7

@

12

RC89

@

1K_0402_1%~D

RC86
1K_0402_1%~D

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

@

RC90

50_0402_1%

A A

INTEL 12/28 reco mmand
to add RC120, RC 121, RC122, RC1 23
Please place as close as JCPU1

5

@

RC91
50_0402_1%

1 2

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

PEG DEFER TRAINING

1: (Default) PEG Train immediat ely

*

CFG7

following xxRESE TB de assertion

0: PEG Wait for BIOS for traini ng

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-6801P

8 60Monday, December 06, 2010

1

of

0.3

5

4

3

2

1

QC=94A
DC=53A

POWER

PEG AND DDR

CORE SUPPLY

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

8.5A

VCCSENSE_R
VSSSENSE_R

PDDG 0.7@P12

1

2

1

2

1

2

130_0402_1%~D

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

22U_0805_6.3VAM~D

CC72

22U_0805_6.3VAM~D

CC92

22U_0805_6.3VAM~D

CC103

12

RC95

RC98 0_0402_5%~D

1 2

RC99 0_0402_5%~D

1 2

VCCIO_SENSE <54>
VSSIO_SENSE <54>

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

2

1

2

1

2

CC74

CC73

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC93

CC94

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC104

CC105

2

RC95 close to CPU

RC94 43_0402_1%

1 2

RC92 0_0402_5%~D

1 2

RC96 0_0402_5%~D

1 2

+VCCP

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC75

2

22U_0805_6.3VAM~D

1

CC95

2

22U_0805_6.3VAM~D

1

CC106

2

22U_0805_6.3VAM~D

1

1

CC76

CC77

2

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

2

1

2

CC97

CC96

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC108

CC107

2

+VCCP

12

+VCC_CORE

12

12

22U_0805_6.3VAM~D

1

CC88

2

22U_0805_6.3VAM~D

1

CC98

2

22U_0805_6.3VAM~D

1

@

CC109

2

RC93
75_0402_5%

RC97
100_0402_1%~D

RC100
100_0402_1%~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

CC78

2

22U_0805_6.3VAM~D

1

CC99

2

330U_D2_2VM_R6M~D

1

CC110

+

2

Place the PU
resistors close to CPU

VR_SVID_ALRT# <57>
VR_SVID_CLK <57>
VR_SVID_DAT <57>

VCCSENSE <57>
VSSSENSE <57>

22U_0805_6.3VAM~D

1

1

CC79

2

2

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1

1

CC100

2

2

330U_D2_2VM_R6M~D

1

CC111

+

2

22U_0805_6.3VAM~D

1

CC80

CC81

2

22U_0805_6.3VAM~D

1

CC101

CC102

2

JCPU1F

+VCC_CORE

1

CC70
10U_0805_4VAM~D

2

1

CC89
10U_0805_4VAM~D

2

1

CC114
22U_0805_6.3VAM~D

2

1

CC119
22U_0805_6.3VAM~D

2

1

CC124
22U_0805_6.3VAM~D

2

1

CC129
22U_0805_6.3VAM~D

2

1

+

CC133

2

470U_D2_2VM_R4.5M~D

+VCC_CORE

+VCC_CORE

1

CC85
10U_0805_4VAM~D

2

1

CC82
10U_0805_4VAM~D

2

1

CC113
22U_0805_6.3VAM~D

2

1

CC118
22U_0805_6.3VAM~D

2

1

CC123
22U_0805_6.3VAM~D

2

1

CC128
22U_0805_6.3VAM~D

2

1

+

2

470U_D2_2VM_R4.5M~D

1

+

CC136

2

470U_D2_2VM_R4.5M~D

CC132

D D

C C

B B

A A

1

CC86
10U_0805_4VAM~D

2

1

CC90
10U_0805_4VAM~D

2

1

CC115
22U_0805_6.3VAM~D

2

1

CC120
22U_0805_6.3VAM~D

2

1

CC125
22U_0805_6.3VAM~D

2

1

CC130
22U_0805_6.3VAM~D

2

1

+

CC134

2

470U_D2_2VM_R4.5M~D

1

CC87
10U_0805_4VAM~D

2

1

CC91
10U_0805_4VAM~D

2

1

CC116
22U_0805_6.3VAM~D

2

1

CC121
22U_0805_6.3VAM~D

2

1

CC126
22U_0805_6.3VAM~D

2

1

CC131
22U_0805_6.3VAM~D

2

470U_D2_2VM_R4.5M~D

1

CC71
10U_0805_4VAM~D

2

1

CC83
10U_0805_4VAM~D

2

1

CC117
22U_0805_6.3VAM~D

2

1

CC122
22U_0805_6.3VAM~D

2

1

CC127
22U_0805_6.3VAM~D

2

1

+

CC135

2

1

CC84
10U_0805_4VAM~D

2

+VCC_CORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev1p0

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

LA-6801P

9 60Monday, December 06, 2010

1

0.3

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

B+_BIAS+3VALW

12

RC102
100K_0402_5%~D

1

2

22U_0805_6.3V6M~D

1

2

22U_0805_6.3V6M~D

1

2

1U_0402_6.3V6K~D

CC175

RUN_ON_CPU1.5VS3#

61

QC5A
2N7002DW-7-F_SOT363-6~D

2

22U_0805_6.3V6M~D

CC147

CC146

1

2

22U_0805_6.3V6M~D

CC154

CC155

1

2

@

330U_D2_2.5VM_R6M~D

1

CC176

+

2

33A

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

TBD

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev1p0

CONN@

D D

RC104

@

1

2

1

2

CC157

22U_0805_6.3V6M~D

CC142

22U_0805_6.3V6M~D

CC150

1 2

0_0402_5%~D

1 2

0_0402_5%~D

CC217

0.1U_0402_10V7K~D

22U_0805_6.3V6M~D

CC143

1

1

2

2

22U_0805_6.3V6M~D

CC151

1

1

2

2

10U_0805_4VAM~D

1

CC172

2

RC107

@

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

22U_0805_6.3V6M~D

CC144

1

2

22U_0805_6.3V6M~D

CC152

1

2

+1.8VS_VCCPLL

1U_0402_6.3V6K~D

CC174

CC145

CC153

@

1

2

SUSP#<18,31,33,53,54>

CPU1.5V_S3_GATE<31>

+VCC_GFXCORE_AXG

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC140

CC141

1

1

2

2

22U_0805_6.3V6M~D

C C

B B

22U_0805_6.3V6M~D

CC148

1

2

1

+

CC156

2

470U_D2_2VM_R4.5M~D

+1.8VS

RC109 0_0805_5%~D

CC149

1

2

1

+

2

470U_D2_2VM_R4.5M~D

1 2

12

RC101
100K_0402_5%~D

RUN_ON_CPU1.5VS3

3

QC5B

5

2N7002DW-7-F_SOT363-6~D

4

RUN_ON_CPU1.5VS3# <6,33>

POWER

VSSAXG_SENSE

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

QC3

AO4728L_SO8~D

8
7
6
5

4

0.1U_0603_50V_X7R

12

1

CC139

2

RC105

330K_0402_1%

VCC_AXG_SENSE

AK35

VSS_AXG_SENSE

AK34

+V_SM_VREF should
have 10 mil trace width

+V_SM_VREF_CNT

AL1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

H_FC_C22

C22
C24

1
2
3

1

2

CC138

10U_0805_10V4Z~D

1

2

VCCSA_SEL <55>

12

RC103

RC126

100K_0402_5%~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CC160

2

10U_0805_4VAM~D

1

1

CC167

2

2

RC111

10K_0402_5%~D

20K_0402_5%~D

VCC_AXG_SENSE <57>
VSS_AXG_SENSE <57>

1 2

RC106 0_0402_5%~D@

3

12

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC161

CC163

CC162

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D

1

1

CC169

CC168

2

2

RC120 0_0402_5%~D

12

1

QC4

2

NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC164

CC165

2

2

1

@

+

CC171

CC170

330U_D2_2VM_R6M~D

2

1 2

12

RC110

@

0_0402_5%~D

+V_SM_VREF

1

+

CC166
330U_D2_2VM_R6M~D

2

+VCCSA

VCCSA_SENSE <55>

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

+1.5V_CPU_VDDQ

12

1K_0402_5%~D
RC112

12

1K_0402_5%~D
RC116

@

J8

1 2

PAD-OPEN 4x4m

J8 OPEN

VSSSA_SENSE <55>

+1.5V_CPU_VDDQ +1.5V

add CC181 , CC182, 4 caps ar e all pop.

ollow checklist 1.0 5/24

f

+1.5V

CC182 0.1U_0402_10V7K~D

12

CC184 0.1U_0402_10V7K~D

12

CC181 0.1U_0402_10V7K~D

12

CC183 0.1U_0402_10V7K~D

12

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

LA-6801P

1

10 60Monday, December 06, 2010

0.3

5

+1.5V

CD6

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD11

1

2

1U_0402_6.3V6K~D

1

CD20

2

<BOM Structure>

12

RD1
1K_0402_1%~D

+V_DDR_REFA

12

RD3
1K_0402_1%~D

All VREF traces should
have 10 mil trace width

10U_0603_6.3V6M~D

330U_SX_2VY~D

@

1

CD12

1

2

CD14

CD13

1

+

2

2

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_MA[0..15]<7>

D D

Layout Note:
Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD3

1

1

2

2

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C C

B B

CD7

CD8

1

1

2

2

Layout Note:
Place near JDIMM1.203,204

+0.75VS

1U_0402_6.3V6K~D

1

1

CD17

2

2

1U_0402_6.3V6K~D

CD4

CD5

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD9

CD10

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD19

CD18

2

+V_DDR_REFA

4

RD2 0_0402_5%~D

1 2

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

1

1

CD1

2

2

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

+3VS

CD21

1

1

2

2

+DIMM0_VREF

DDR_A_D0
DDR_A_D1

CD2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

RD6 10K_0402_5%~D

1 2

RD7 10K_0402_5%~D

CD22

+0.75VS

+1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A626-U2SN-7F

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

3

+1.5V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2
A0

VDD

CK1

VDD

BA1

VDD

S0#

VDD

NC

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

+VREF_CA

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

1

CD15

2

PCH_SMBDATA <6, 12,14,28,32>
PCH_SMBCLK <6,12,14,28,32>

DDR3_DRAMRST# <7,12>

+1.5V

1

CD16

2

2

12

RD4
1K_0402_1%~D

12

RD5
1K_0402_1%~D

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-6801P

1

11 60Monday, December 06, 2010

0.3

5

+1.5V

12

RD15
1K_0402_1%~D

+V_DDR_REFB

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

D D

C C

B B

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.5V

10U_0603_6.3V6M~D

CD32

1

2

Layout Note:
Place near JDIMMB.203,204

+0.75VS

CD29

CD28

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD34

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD42

CD43

2

2

Layout Note:
Place near JDIMMB

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD31

CD30

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD36

CD35

1

1

2

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD45

CD44

2

2

10U_0603_6.3V6M~D

@

1

CD38

CD37

1

2

2

12

RD16
1K_0402_1%~D

330U_SX_2VY~D

CD39

+

4

+V_DDR_REFB

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

RD14 0_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

1

CD27

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

12

RD19

10K_0402_5%~D

3

+1.5V

0.1U_0402_16V7K~D

10K_0402_5%~D

+DIMM1_VREF

DDR_B_D0
DDR_B_D1

1

CD26

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

12

RD20

+0.75VS

CD47

CD46

1

1

2

2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4926-0100

O

NN@

C

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+1.5V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

2

DDR3_DRAMRST# <7,11>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

1

1

CD40

2

2

PCH_SMBDATA <6, 11,14,28,32>
PCH_SMBCLK <6,11,14, 28,32>

RD17
1K_0402_1%~D

CD41

+1.5V

12

12

RD18
1K_0402_1%~D

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-6801P

1

12 60Monday, December 06, 2010

0.3

5

PCH_RTCX1

32.768KHZ_12.5PF_Q13MC14610002

1

CH3
18P_0402_50V8J~D

2

1 2

RH27 33_0402_5%

1 2

RH28 33_0402_5%

1 2

RH33 33_0402_5%

1 2

RH275 1M_0402_5%~D

HDA_SDO<31>

12

RH39

@

200_0402_5%

12

RH45
100_0402_1%~D

1 2

RH53 51_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD#

@

12

1 2

CH98

12

@

10P_0402_50V8J~D

PCH_RTCX2

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1 2

RH24 0_0402_5%~D

1 2

RH30 33_0402_5%

12

RH40

@

200_0402_5%

12

RH46

100_0402_1%~D

+3V_PCH

12

@

RH267
10K_0402_5%~D

DP_PCH_HPD

RH268
100K_0402_5%~D

@

1 2

@

RH256

PCH_SPI_CLK_R

33_0402_5%

PCH_SPI_CLK

+RTCVCC

1U_0603_10V4Z

1 2

RH25 20K_0402_5%~D

1 2

RH23 20K_0402_5%~D

1U_0603_10V4Z

QH1BSS138_SOT23

1 2

RH36 0_0402_5%~D

@

1M_0402_5%~D

CMOS

CLRP1

CLRP2

ME CMOS

HDA_SPKR<24>

HDA_SDIN0<24>

DP_PCH_HPD<38>

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

SM_INTRUDER#

RH255 0_0402_5%~D

RH11

CH4

CH5

+5VS

G

2

S

@

HDA_SDOUT

HDA_SDOUT

1 2

1

2

1

2

13

D

PCH_SPI_CLK_R

12

SHORT PADS

12

SHORT PADS

CLP1 & CLP2 place near DIMM

HDA_SYNC

close to UH1

+3V_PCH

@

1 2

1 2

RH58 0_0402_5%~D

PCH_SPI_SO PCH_SPI_SO_R

1 2

RH60 33_0402_5%

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

12

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

RH57

3.3K_0402_5%

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

1 2

RH2 10M_0402_5%

18P_0402_50V8J~D

1

1

CH2

OSC4OSC

2

D D

C C

B B

A A

YH1

NC3NC

2

far away hot spot

HDA_BITCLK_AUDIO<24>

HDA_RST_AUDIO#<24>

HDA_SYNC_AUDIO<24>

HDA_SDOUT_AUDIO<24>

+3V_PCH +3V_PCH+3V_PCH

12

RH38

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH44

100_0402_1%~D

PCH_JTAG_TCK

+3V_PCH

1 2

RH54 3.3K_0402_5%

1 2

RH56 3.3K_0402_5%

CH94

22P_0402_50V8J~D

Reserve for EMI please close to U48

Reserve for RF please close t o UH1

5

4

@

HDA_SDOUT

12

CH103 10P_0402_50V8J~D

@

HDA_BIT_CLK

12

CH97 10P_0402_50V8J~D

Reserve for RF please close t o UH1

ES2@

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CougarPoint_Rev_1p0

SA00003P42L

RTCIHDA

JTAG

SPI

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATA3RCOMPO

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI ROM FOR ME ( 4MByte )

SPI ROM FOR ME
( 4MByte )

U48

1

/CS

2

DO

3

/WP

GND4DIO

W25X32VSSIG_SO8~D

SPI BIOS Pinout

(1)CS# (5)DIO
(2)DO (6)CLK
(3)WP# (7)HOLD #
(4)GND (8)VCC

W25X32

4

/HOLD

8

VCC

PCH_SPI_HOLD#

7

PCH_SPI_CLK_R

6

CLK

5

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

RH63 33_0402_5%

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

1 2

UH1

BD82HM67 QNDK B1

SA00004ED0L

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

PCH_SPI_SIPCH_SPI_SI_R

3

QS@

LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>

LPC_FRAME# <31>

SERIRQ <31>

CH91 0.01U_0402_16V7K~D

1 2

CH90 0.01U_0402_16V7K~D

1 2

CH92 0.01U_0402_16V7K~D

1 2

CH93 0.01U_0402_16V7K~D

1 2

PCH_SATALED# <35>

10K_0402_5%~D

12

+1.05VS_VCC_SATA

+1.05VS_SATA3

1 2

RH41 37.4_0402_1%

1 2

RH43 49.9_0402_1%

1 2

RH48 750_0402_1%~D

RH276

+3V_PCH

1

CH6

0.1U_0402_16V7K~D

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

Issued Date

2

SATA_PRX_DTX_N1 <28>
SATA_PRX_DTX_P1 <28>
SATA_PTX_DRX_N1_C <28>
SATA_PTX_DRX_P1_C <28>

SATA_PRX_DTX_N2 <28>
SATA_PRX_DTX_P2 <28>
SATA_PTX_DRX_N2_RP <28>
SATA_PTX_DRX_P2_RP <28>

HDD1

ODD

PCH_INTVRMEN

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

RTC Battery

DH4

+RTCVCC

W=20mils

1

2

+CHGRTC

2010/12/01 2011/12/01

BAS40-04_SOT23-3

CH95
1U_0603_10V4Z

RH260

0_0603_5%~D

@

Compal Secret Data

Deciphered Date

2

RH31 330K_0402_5%

RH34 330K_0402_5%@

+RTCBATT

RH259
1K_0402_5%~D

1 2
1

W=20mils

+CHGRTC

2

3

W=20mils

RH261

0_0603_5%~D

12

12

@

1

+3VS

SERIRQ

+RTCVCC

12

12

RH29 10K_0402_5%~D

PCH_GPIO21

RH32 10K_0402_5%~D

PCH_SATALED#PCH_INTVRMEN

RH35 10K_0402_5%~D

HDA_SPKR

RH37 1K_0402_5%~D@

*

HDA_SDOUT

RH42 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

HDA_SYNC

This signal has a weak intern al pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for H uron River plat from

HDA_SYNC

RH52 1K_0402_5%~D

12

12

12

12

12

LOW=Default
HIGH=No Reboot

12

+3V_PCH

+3VS

+3V_PCH

+3VLP

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-6801P

1

of

13 60Monday, December 06, 2010

0.3

5

PCIE_PRX_GLANTX_N3<22>

@

CH21

1 2

PCIE_PRX_GLANTX_P3<22>
PCIE_PTX_GLANRX_N3<22>
PCIE_PTX_GLANRX_P3<22>

PCIE_PRX_WANTX_N2<32>

PCIE_PRX_WANTX_P2<32>
PCIE_PTX_WANRX_N2<32>
PCIE_PTX_WANRX_P2<32>

PCIE_PRX_WLANTX_N1<32>

PCIE_PRX_WLANTX_P1<32>
PCIE_PTX_WLANRX_N1<32>
PCIE_PTX_WLANRX_P1<32>

PCIE_PRX_CARDTX_N4<23>

PCIE_PRX_CARDTX_P4<23>
PCIE_PTX_CARDRX_N4<23>
PCIE_PTX_CARDRX_P4<23>

PCIE_PRX_USB3TX_N6<27>

PCIE_PRX_USB3TX_P6<27>
PCIE_PTX_USB3RX_N6<27>
PCIE_PTX_USB3RX_P6<27>

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

USB 3.0 --->

@

CLK_PCH_14M

RH86

33_0402_5%

12

22P_0402_50V8J~D

CH9 0.1U_0402_10V7K~D

1 2

CH14 0.1U_0402_10V7K~D

1 2

CH10 0.1U_0402_10V7K~D

1 2

CH15 0.1U_0402_10V7K~D

1 2

CH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~D

1 2

CH12 0.1U_0402_10V7K~D

1 2

CH13 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~D

1 2

Reserve for EMI please close t o UH1

C C

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH1

RH89

33_0402_5%

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

B B

YH2

25MHZ_18PF_1Y725000CE1A~D

1 2

22P_0402_50V8J~D

1

CH23

2

A A

@

@

CH22

1 2

12

22P_0402_50V8J~D

10/100/1G LAN --->

Card Reader --->

USB 3.0 --->

XTAL25_IN

CH24

1

2

XTAL25_OUT

22P_0402_50V8J~D

12

RH1171M_0402_5%~D

+3V_PCH

CLK_PCIE_LAN#<22>
CLK_PCIE_LAN<22>

LANCLK_REQ#<22>

CLK_PCIE_MINI2#<32>
CLK_PCIE_MINI2<32>

MINI2CLK_REQ#<32>

CLK_PCIE_MINI1#<32>
CLK_PCIE_MINI1<32>

MINI1CLK_REQ#<32>

CLK_PCIE_CD#<23>
CLK_PCIE_CD<23>

CDCLK_REQ#<23>

+3V_PCH

+3V_PCH

CLK_PCIE_USB30#<27>
CLK_PCIE_USB30<27>

+3V_PCH

USB30_CLKREQ#<27>

+3V_PCH

CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>

CLK_RES_ITP#<8>
CLK_RES_ITP<8>

CLK_CPU_ITP#
CLK_CPU_ITP

RH91 10K_0402_5%~D

RH93 0_0402_5%~D
RH94 0_0402_5%~D

RH95 10K_0402_5%~D@

+3VS

RH96 0_0402_5%~D
RH97 0_0402_5%~D
RH100 10K_0402_5%~D

+3VS

RH101 0_0402_5%~D
RH102 0_0402_5%~D
RH103 10K_0402_5%~D

+3V_PCH

RH104 0_0402_5%~D
RH106 0_0402_5%~D
RH107 10K_0402_5%~D

+3V_PCH

RH110 10K_0402_5%~D

RH112 10K_0402_5%~D

RH114 0_0402_5%~D
RH115 0_0402_5%~D
RH116 10K_0402_5%~D

RH118 10K_0402_5%~D

RH119 0_0402_5%~D
RH120 0_0402_5%~D

RH121 0_0402_5%~D@
RH122 0_0402_5%~D@

1 2

1 2
1 2

1 2

1 2

1 2

1 2

12

12
12
12

12
12
12

12
12
12

12
12

12
12

12
12

4

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WANTX_N2
PCIE_PRX_WANTX_P2
PCIE_PTX_WANRX_N2_C
PCIE_PTX_WANRX_P2_C

PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1
PCIE_PTX_WLANRX_N1_C
PCIE_PTX_WLANRX_P1_C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C

PCIE_PRX_USB3TX_N6
PCIE_PRX_USB3TX_P6
PCIE_PTX_USB3RX_N6_C
PCIE_PTX_USB3RX_P6_C

T81PAD~D @
T82PAD~D @

PCIECLKREQ0#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD#
PCIE_CD

CDCLK_REQ#

PEG_B_CLKREQ#

PCIE_USB30#
PCIE_USB30

USB30_CLKREQ#

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

CLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_1p0

ES2@

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_LID_SW_IN#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

CLK_CPU_DPLL#

AM12

CLK_CPU_DPLL

AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

KB_DET#

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

CAM_DET#

DMC_PCH_DET#

BT_DET#

KB_DET#

MEMORY

Total device

+3V_PCH

1 2

RH113 90.9_0402_1%

1 2

RH166 10K_0402_5%~D

1 2

RH109 10K_0402_5%~D

1 2

RH108 10K_0402_5%~D

12

R1791 100K_0402_5%~D

2

EC_LID_OUT#

1 2

RH680_0402_5%~D

@

1 2

RH710_0402_5%~D

DRAMRST_CNTRL_PCH <7>

20090512
add double mosfet prevent
ATI M92 electric leakage

RH141
10K_0402_5%~D

1 2

CLK_PEG_VGA# <40>
CLK_PEG_VGA <40>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>

CLK_PCI_LPBACK <16>

KB_DET# <29>

DMC_PCH_DET# <37>

BT_DET# <32>

CAM_DET# <21>

PEG_A_CLKRQ# <40>

SMBCLK

DMN66D0LDW-7_SOT363-6~D

SMBDATA

+1.05VS_VCCDIFFCLKN

SML1CLK

SML1DATA

+3VS

EC_LID_OUT# <31>

LID_SW_IN# <31,34,35>

2

6 1

QH3A
RH105

@

1 2

0_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

6 1

DMN66D0LDW-7_SOT363-6~D

QH4A

DMN66D0LDW-7_SOT363-6~D

3

1 2

0_0402_5%~D

+3VS

2

3

+3VS

2.2K_0402_5%~D

5

QH3B
RH111

@

QH4B

1

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

LID_SW_IN#

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, pleas e place close to CLK gen
else, please p lace close to P CH

+3VS

RH98

1 2

4

5

4

1 2

RH67 2.2K_0402_5%~D

1 2

RH69 2.2K_0402_5%~D

1 2

RH70 2.2K_0402_5%~D

1 2

RH72 2.2K_0402_5%~D

1 2

RH73 2.2K_0402_5%~D

1 2

RH74 2.2K_0402_5%~D

1 2

R1790 10K_0402_5%~D

@

1 2

RH75 1K_0402_5%~D

RH76 10K_0402_5%~D

1 2

RH78 10K_0402_5%~D

1 2

RH77 10K_0402_5%~D

1 2

RH79 10K_0402_5%~D

1 2

RH80 10K_0402_5%~D

1 2

RH81 10K_0402_5%~D

1 2

RH82 10K_0402_5%~D

1 2

RH83 10K_0402_5%~D

1 2

RH84 10K_0402_5%~D

1 2

RH99

2.2K_0402_5%~D

1 2

PCH_SMBCLK <6,11,12,28,32>

PCH_SMBDATA <6,11,12,28,32>

PCH_SMLCLK <31,51>

PCH_SMLDATA <31,51>

+3V_PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-6801P

1

of

14 60Monday, December 06, 2010

0.3

5

Compal Electronics, Inc.

UH1C

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>

D D

XDP_DBRESET#<6>

C C

PM_DRAM_PWRGD<6>

SUSWARN# SUSACK#_R

B B

GPIO72

RI#

WAKE#

AC_PRESENT

SUSWARN#

PCH_RSMRST#

SYS_PWROK

A A

DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

4mil width and place
within 500mil of the PCH

SUSACK#<31>

PCH_PWROK

PCH_APWROK<31>

PCH_RSMRST#<31>

SUSWARN#<31>

PBTN_OUT#<6,31 >

AC_PRESENT<31>

1 2

RH139 0_0402_5%~D

RH143 10K_0402_5 %~D

1 2

RH145 10K_0402_5 %~D

1 2

RH146 10K_0402_5 %~D

1 2

RH150 10K_0402_5 %~D@

1 2

RH154 10K_0402_5 %~D

1 2

RH159 10K_0402_5 %~D

1 2

RH272 10K_0402_5 %~D

1 2

PCH_PWROK<6,31>

VGATE<6,31,57>

RH124 49.9_0 402_1%

RH125 750_0 402_1%~D

PCH_PWROK

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

1 2

RH127 0_0402_5%~D

RH273 0_0402_5 %~D

RH130 0_0402_5 %~D

RH131 0_0402_5 %~D

RH133 0_040 2_5%~D

RH134 0_040 2_5%~D

RH135 0_040 2_5%~D

RH137 0_040 2_5%~D

DMI_IRCOMP

RBIAS_CPY

1 2

XDP_DBRESET#

@

1 2

1 2

1 2

PM_DRAM_PWRGD

PCH_RSMRST#_R

1 2

1 2

1 2

1 2

GPIO72

+3V_PCH

+3VS

1

CH96

0.1U_0402_16V7K~D

2

1

IN1

2

IN2

SUSACK#_R

SYS_PWROK

PM_PWROK_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

RI#

BC24
BE20
BG18
BG20

BE24
BC20

BJ18
BJ20

AW24
AW20

BB18
AV18

AY24
AY20
AY18
AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

CougarPoint_Rev_1p0

ES2@

DSWODVREN

DSWODVREN

DSWODVREN - On Die DSW VR Enable

*

5

UH7

VCC

SYS_PWROK

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

3

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

RH147 330K_0402 _5%

RH151 330K_0402 _5%@

H：Enable
L：Disable

SYS_PWROK <6>

4

FDI_CTX_PRX_N0

BJ14

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

12

+RTCVCC

AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

1 2

RH132 0_0402_5%~D

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5>
FDI_CTX_PRX_P1 < 5>
FDI_CTX_PRX_P2 < 5>
FDI_CTX_PRX_P3 < 5>
FDI_CTX_PRX_P4 < 5>
FDI_CTX_PRX_P5 < 5>
FDI_CTX_PRX_P6 < 5>
FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5 >

FDI_FSYNC1 <5 >

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

@

RH126 0_0402_5%~D

1 2

RH128 0_0402_5%~D

12

If not using integrated
LAN,signal may be left as NC.

PCH_DPWROK <31>

T76 PAD~D

PM_SLP_S5# <31,34>

PM_SLP_S4# <31>

PM_SLP_S3# <31,34>

PM_SLP_SUS# <31>

H_PM_SYNC <6>

PCH_RSMRST#_R

PCIE_WAKE# <22,31,32>

SUSCLK_R <31>

SUSCLK

Reserve for RF please close to UH1

3

VGA_LVDDEN<21,31>

LVDS_DDC_CLK<21>

LVDS_DDC_DATA<21>

LVDS_ACLK-< 21>
LVDS_ACLK+<21>

LVDS_A0-<21>
LVDS_A1-<21>
LVDS_A2-<21>

LVDS_A0+<21>
LVDS_A1+<21>
LVDS_A2+<21>

LVDS_BCLK-< 21>
LVDS_BCLK+<21>

LVDS_B0-<21>
LVDS_B1-<21>
LVDS_B2-<21>

LVDS_B0+<21>
LVDS_B1+<21>
LVDS_B2+<21>

CRT_B<21>
CRT_G<21>
CRT_R<21>

CRT_DDC_CLK<21>
CRT_DDC_DATA<21>

CRT_HSYNC< 21>
CRT_VSYNC<21>

Can be left NC when IAMT is
not support on the platfrom

CH102

12

@

10P_0402_50V8J~D

+3VS

@

1 2

RH148 2.2K_0402_5%~D

@

1 2

RH152 2.2K_0402_5%~D

1 2

RH155 2.2K_0402_5%~D

1 2

RH157 2.2K_0402_5%~D

1 2

RH248 8.2K_0402_5%~D@

+3VS

RV169 2 .2K_0402_5%~D

1 2

RV170 2 .2K_0402_5%~D

1 2

ENBKL<31>

VGA_PWM<21>

1K_0402_0.5%~D

ENBKL

LVDS_DDC_CLK
LVDS_DDC_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

T203PAD~D

LVDS_ACLK­LVDS_ACLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_BCLK­LVDS_BCLK+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

CRT_B
CRT_G
CRT_R

CRT_DDC_CLK
CRT_DDC_DATA

RH136 33_0402_5%

RH138 33_0402_5%

1 2
1 2

RH140

CRT_DDC_CLK

CRT_DDC_DATA

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

HSYNC
VSYNC

CRT_IREF

12

LVDS_DDC_CLK
LVDS_DDC_DATA

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CougarPoint_Rev_1p0

ES2@

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DMC

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46
P42

AP47

DDPC_AUXN

AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

PCH_DPD_CLK

M43

PCH_DPD_DAT

M36

AT45

DDPD_AUXN

AT43

DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

1 2

RH167 10K_0402_5%~D

1 2

RH144 2.37K_0402_1%~D

1 2

RH149 150_0402_1%~D

1 2

RH153 150_0402_1%~D

1 2

RH156 150_0402_1%~D

1 2

RH158 100K_0402_5%~D

1 2

RH123 100K_0402_5%~D

BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PCH_DMC_HPD

PCH_DPD_N0
PCH_DPD_P0
PCH_DPD_N1
PCH_DPD_P1
PCH_DPD_N2
PCH_DPD_P2
PCH_DPD_N3
PCH_DPD_P3

PM_CLKRUN#

LVDS_IBG

CRT_B

CRT_G

CRT_R

VGA_LVDDEN

ENBKL

1

PCH_DPD_CLK <37>
PCH_DPD_DAT < 37>

PCH_DMC_HPD <37>

PCH_DPD_N0 <37>
PCH_DPD_P0 <37>
PCH_DPD_N1 <37>
PCH_DPD_P1 <37>
PCH_DPD_N2 <37>
PCH_DPD_P2 <37>
PCH_DPD_N3 <37>
PCH_DPD_P3 <37>

DMC
( HDMI )

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-6801P

1

15 60Monday, December 06, 2010

0.3

5

D D

C C

B B

A A

+3V_PCH

12

1 2

@

RH269
10K_0402_5%~D

CARD_HPLUG

RH264
100K_0402_5%~D

@

CLK_PCI_LPBACK<14>

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#

T123P AD~D @

12

T165P AD~D @
T166P AD~D @
T204P AD~D @

+3VS

DGPU_SELECT#
DGPU_PWR_EN

DMC_RADIO_OFF#

WL_OFF#

FFS_INT1
ODD_DA#
DP_CBL_DET
CARD_HPLUG

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

DGPU_SELECT#<37>

DGPU_PWR_EN<33,43,55,56>

DMC_RADIO_OFF#<32>

WL_OFF#<32>

FFS_INT1<28>

ODD_DA#<28>

DP_CBL_DET<38>

CARD_HPLUG<23>

CLK_PCI_LPBACK

CLK_PCI_LPC<31>

CLK_PCI_LPC

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#

DMC_RADIO_OFF#
DGPU_SELECT#
DGPU_PWR_EN
FFS_INT1

PCI_PIRQA#

ODD_DA#

DGPU_HOLD_RST#

RH164 22_0402_5%
RH165 22_0402_5%

1 2

RPH3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RPH4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RPH5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RH173 10K_0402_5%~D

1 2

BG26

BJ26

BH25

BJ16
BG16
AH38
AH37
AK43
AK45

C18
N30

H3

AH12

AM4
AM5

Y13
K24

L24
AB46
AB45

B21

M20
AY16
BG46

BE28
BC30
BE32

BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28

AW30

K40
K38
H38

G38

C46
C44
E40

D47
E42
F46

G42
G40

C42
D44

K10

C6

H49
H43
J48
K42
H40

CougarPoint_Rev_1p0

ES2@

10K_0402_5%~D

PLT_RST#<6,22,23,27,31,32>

4

UH1E

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

@

RH169

+3VS

RSVD

1 2

PCI

USB

12

RH171
100K_0402_5%~D

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

@

1 2

RH168 0_0402_5%~D

+3VS

5

UH5

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8

AY5
BA2

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

NV_ALE

USB20_N9
USB20_P9
USB20_N8
USB20_P8
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

USBRBIAS

USB_OC2#
USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
USB_OC0#
USB_OC5#
USB3_SMI#
USB_OC6#

PCH_PLTRST#

3

USB20_N9 <26>
USB20_P9 <26>
USB20_N8 <32>
USB20_P8 <32>
USB20_N3 <21>
USB20_P3 <21>
USB20_N4 <32>
USB20_P4 <32>
USB20_N5 <32>
USB20_P5 <32>
USB20_N6 <34>
USB20_P6 <34>

Within 500 mils

1 2

RH163 22.6_0402_1%

USB/B

Bluetooth

Camera

Mini Card(WLAN)

Mini Card(Mini2)

ELC LED

PLTRST_VGA#<40>

USB_OC2# <26>

1.5VDDR_VID0 <53>

1.5VDDR_VID1 <53>

USB3_SMI# <27>

12

100_0402_5%~D

100K_0402_5%~D

(For USB Port 9)

1 2

RH254 0_0402_5%~D@

RH170

4

Y

12

RH172

+3VS

5

UH6

2

P

B

DGPU_HOLD_RST#

1

A

G

SN74AHC1G08DCKR_SC70-5

3

2

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floa ting)

NV_ALE

RH160 1K_0402_5%~D@

1 2

USB_OC0#
USB_OC2#
USB3_SMI#
USB_OC5#

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
USB_OC6#

1 2

RH265 0_0402_5%~D@

1 2

RH266 0_0402_5%~D

*

RPH1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

RPH2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

DGPU_PWROK

PCH_PLTRST#

1

+1.8VS

+3V_PCH

DGPU_PWROK <17,38,39,55,56>

CH99

CLK_PCI1

12

@

10P_0402_50V8J~D

Reserve for RF please close to UH1

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-6801P

1

16 60Monday, December 06, 2010

0.3

5

+3V_PCH

12

RH270
10K_0402_5%~D

HDMI_PCH_HPD# GPIO6

D D

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage regulator enabl e

*

L：On-Die PLL Voltage Regulator d isable

RH177 1K_0402_5%~D@

PCH_GPIO37

C C

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage
(DC Coupling Mode)

+3VS

RH181 1K_0402_5%~D@

RH182

1 2

1 2

12

PCH_GPIO28

10K_0402_5%~D

PCH_GPIO37

PCH_GPIO37

GPIO27

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

RH186 10K_0402_5%~D@

B B

High: CRT Plugged

A A

CRT_DET#<21>

1 2

CRT_DET

QH5

SSM3K7002F_SC59-3

5

PCH_GPIO27

+3VS

2

G

RH198
10K_0402_5%~D

1 2

13

D

S

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

4

CRT_DET

DGPU_EDIDSEL#<37>

EC_SCI#<31>

EC_SMI#<31>

BT_RADIO_DIS#<32>

HDMI_PCH_HPD#<39>

DGPU_PWROK<16,38,39,55,56>

BT_ON#<32>

ODD_DETECT#<28>

FFS_INT2<28>

HDD_DETECT#<28>

4

DGPU_EDIDSEL#

EC_SCI#

EC_SMI#

BT_RADIO_DIS#

HDMI_PCH_HPD#

GPIO16

DGPU_PWROK

PCH_GPIO22

PCH_GPIO27

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

FFS_INT2

GPIO49

HDD_DETECT#

UH1F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_Rev_1p0

ES2@

GPIO

3

ODD_EN#

C40

GPIO69

B41

C41

A40

P4

A20GATE

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PECI

NC_1

Issued Date

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

3

ODD_EN# <28>

T126 P AD~D@

@

1 2

RH1750_0402_5%~D

KB_RST# <31>

H_CPUPWRGD <6>

1 2

2010/12/01 2011/12/01

RH176390_0402_5%

H_PECI <6,31>

H_THERMTRIP#

12

@

RH178
10K_0402_5%~D

Compal Secret Data

2

+3VS

RH174
10K_0402_5%~D

1 2

H_THERMTRIP# <6>

INIT3_3V

This signal has weak internal
P

U, can't pull lo w

Deciphered Date

2

GATEA20 <31>

CRT_DET#

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

PCH_GPIO22

GPIO35

GPIO49

PCH_GPIO38

PCH_GPIO39

GPIO6

DGPU_EDIDSEL#

ODD_EN#

HDD_DETECT#

EC_SMI#

1

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

+1.8VS

12

RH161

2.2K_0402_5%~D

12

RH1621K_0402_5%~D

H_SNB_IVB# <6>

CLOSE TO THE BRA NCHING POINT

RH161 and RH162
Follow CRB FAB2 setting

+3VS

RH180 10K_0402_5%~D

1 2

+3V_PCH

10K_0402_5%~D

1 2

RH187

10K_0402_5%~D

1 2

RH188

10K_0402_5%~D

1 2

RH190

+3VS

10K_0402_5%~D@

1 2

RH192

200K_0402_5%

1 2

RH193

10K_0402_5%~D

1 2

RH274

8.2K_0402_5%~D

1 2

RH195

10K_0402_5%~D

1 2

RH196

10K_0402_5%~D

1 2

RH197

10K_0402_5%~D

1 2

RH257

10K_0402_5%~D

1 2

RH258

10K_0402_5%~D

1 2

RH262

10K_0402_5%~D

1 2

RH263

10K_0402_5%~D

1 2

RH271

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-6801P

1

17 60Monday, December 06, 2010

0.3

of

5

4

3

2

1

+1.05VS

@

J10

12

PAD-OPEN 4x4m

D D

+1.05VS

+1.05VS

+VCCAPLLEXP_R

@

RH201 0_0603_5%~D

12

1

2

RH200 0_0603_5%~D

1 2

1UH_LB2012T1R0M_20%~D

Place CH40 Near BJ22 pin

+1.05VS

12

RH203

0_0805_5%~D

C C

+3VS

+1.05VS

B B

12

RH206
0_0805_5%~D

+3VS_VCCA3GBG

1

CH44

0.1U_0402_10V7K~D

2

Place CH53 Near BG6 pin

@

RH208 0_0603_5%~D

12

1

1

CH37

2

2

10U_0805_4VAM~D

1

CH46

2

@

1

CH28

CH27

2

10U_0805_4VAM~D

12

LH3

@

+1.05VS_VCC_EXP

1

CH39

CH38

2

1U_0402_6.3V6K~D

+1.05VS

1U_0402_6.3V6K~D

+1.05VS_VCCCORE

1

CH25

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCDPLLEXP

1

2

@

1

1

CH40

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCAPLL_FDI

RH209

+1.05VS_VCCDPLL_FDI

1 2

0_0805_5%~D

+VCCP_VCCDMI

1

CH26

2

1U_0402_6.3V6K~D

+VCCAPLLEXP

CH35

10U_0805_4VAM~D

CH41

1U_0402_6.3V6K~D

+VCCAFDI_VRM

UH1G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CougarPoint_Rev_1p0

ES2@

2925mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1

mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

20mA

VCCDFTERM[1]

190mA

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

1

CH29

2

+VCCTX_LVDS

CH32

0.01U_0402_16V7K~D

1

CH36

0.1U_0402_10V7K~D

2

1

CH45

2

1

2

1

CH30

2

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

Near AP43

1

2

RH202

1 2

0_0805_5%~D

+VCCP_VCCDMI

1 2

0_0805_5%~D

1

CH43
1U_0402_6.3V6K~D

2

+VCCPNAND

0.1U_0402_10V7K~D
RH210

1 2

0_0805_5%~D

CH47
1U_0402_6.3V6K~D

LH1

BLM18PG181SN1_0603~D

1

CH31
10U_0805_4VAM~D

2

RH199 0_0805_5%

1 2

CH34

1

CH33

0.01U_0402_16V7K~D

2

RH205

1 2

RH207 0_0805_5%~D

+3V_PCH

1

22U_0805_6.3V6M~D

2

+3VS

+1.05VS

+3VS

12

LH2

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

RH204

1 2

1

0_0805_5%~D

CH42

2

1U_0402_6.3V6K~D

+1.8VS

+3VS

+1.8VS

12

+1.05VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

+3VALW

1

1U_0402_6.3V6K~D

A A

5

C432

SUSP#<10,31,33,53,54>

4

2

SUSP#

U47

1

VIN

3

EN

RT9013-15GB_SOT23-5

+1.5VS +VCCAFDI_VRM

RH211

+VCCAFDI_VRM

12

0_0603_5%~D

VOUT

GND

5
4

NC

2

RH212

0_0603_5%~D

@

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

LA-6801P

1

18 60Monday, December 06, 2010

0.3

VCCVRM = 1 60mA detal waiting f or newest spec

5

4

3

2

1

+1.05VS

+3V_PCH

+3V_DSW

D D

+1.05VS

PCH_VREG_EN#<31>

C C

+3VS

RH216

@

1 2

0_0805_5%~D

+3VALW +3V_DSW

QH6
AO3419L_SOT23-3

S

G

2

1 2

RH214 0_0603_5%~D

1 2

RH221 0_0603_5%~D@

LH4

@

D

13

10UH_LBR2012T100M_20%~D

1 2

10U_0805_10V4Z~D

@

1

+1.05VS

CH49

2

+1.05VS

1 2

RH225 0_0805_5%~D

+VCCAPLL_CPY +3VS_VCC_CLKF33

1

CH48

0.1U_0402_10V7K~D

2

0.1U_0402_10V7K~D

1 2

RH219 0_0603_5%~D

@

RH213 0_0603_5%~D

CH51

@

1

CH57

2

22U_0805_6.3V6M~D

1

CH60

2

1U_0402_6.3V6K~D

5/18 delete RH229

LH5

+3VS_VCC_CLKF33_R

1 2

RH2300_0805_5 %~D

+1.05VS

B B

A A

+1.05VS

@

RH234 0_0603_5%~D

+1.05VS

+1.05VS

+1.05VS

1 2

RH247

12

RH235 0_0603_5%~D

+1.05VS

+VCCA_DPLL_L

0_0805_5%~D

12

5

10UH_LBR2012T100M_20%~D

1 2

+1.05VM_VCCSUS

1

CH72

1U_0402_6.3V6K~D

2

RH237 0_0603_5%~D

RH239 0_0603_5%~D

1 2

RH242 0_0603_5%~D

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

12

12

LH7

1 2

1 2

LH8

+3VS_VCC_CLKF33

1

CH66

2

10U_0805_10V4Z~D

+1.05VS_VCCDIFFCLKN

1

CH74
1U_0402_6.3V6K~D

2

1

CH77
1U_0402_6.3V6K~D

2

+V_CPU_IO

1

CH79

4.7U_0603_6.3V6K~D

2

1

+

CH86

2

1

CH67

2

1U_0402_6.3V6K~D

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

1

CH78

0.1U_0402_10V7K~D

2

1

CH80

2

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

1

CH87

2

1U_0402_6.3V6K~D

220U_B2_2.5VM_R35M~D

1

CH71

0.1U_0402_10V7K~D

2

1

2

0.1U_0402_10V7K~D

1

1

+

CH88

2

2

220U_B2_2.5VM_R35M~D

CH81

0.1U_0402_10V7K~D

CH89

12

1

2

1

CH58

2

22U_0805_6.3V6M~D

1

CH61

2

1U_0402_6.3V6K~D

+VCCRTCEXT

1

@

CH76
1U_0402_6.3V6K~D

2

+RTCVCC

1U_0402_6.3V6K~D

4

+VCCACLK

+VCCPDSW

+PCH_VCCDSW

+VCCAPLL_CPY_PCH

+VCCDPLL_CPY

+VCCSUS1

1

@

CH54
1U_0402_6.3V6K~D

2

+1.05VM_VCCASW

1

CH62

2

1U_0402_6.3V6K~D

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCSST

+1.05VM_VCCSUS

1

1

CH82

2

CH83

2

0.1U_0402_10V7K~D

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

1

2

0.1U_0402_10V7K~D

CH84

1U_0402_6.3V6K~D

CougarPoint_Rev_1p0

ES2@

POWER

N26

VCCIO[29]

P26

119mA

PCI/GPIO/LPCMISC

SATA USB

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLSATA

10mA

VCCSUSHDA

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

1mA

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

3

mA

1010mA

Clock and Miscellaneous

80mA

80mA

55mA

95mA

1mA

CPURTC

HDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/12/01 2011/12/01

+1.05VS_VCCUSBCORE

1

CH50
1U_0402_6.3V6K~D

2

+3V_VCCPUSB

1

CH52

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS_1

+PCH_V5REF_RUN

+3V_VCCPSUS

1

CH63
1U_0402_6.3V

2

+3VS_VCCPPCI

+VCC3_3_2

+1.05VS_VCC_SATA

+VCCME_22

+VCCME_23

+VCCME_21

+VCCSUSHDA

1

CH850.1U_0402_10V7K ~D

2

+VCCAFDI_VRM

+VCCAFDI_VRM

Compal Secret Data

RH220 0_0603_5%~D

+3V_VCCAUBG

1

CH53

2

0.1U_0402_10V7K~D

RH223 0_0603_5%~D

0.1U_0402_10V7K~D

+3VS_VCCPCORE

RH232

1

2

+1.05VS_VCC_SATA

12

0_0603_5%~D

CH69

0.1U_0402_10V7K~D

+1.05VS_SATA3

+VCCSATAPLL

RH240 0_0603_5%~D

RH241 0_0603_5%~D

RH243 0_0603_5%~D

12

@

RH246

150_0402_1%~D

Deciphered Date

12

RH217 0_0603_5%~D

0.1U_0402_10V7K~D

1

2

1

2

+3VS

1

2

12

RH218 0_0603_5%~D

12

RH224 0_0603_5%~D

12

12

12

12

CH59

RH226
0_0603_5%~D

12

RH228 0_0805_5%~D

CH65

0.1U_0402_10V7K~D

RH231 0_0603_5%~D

1

CH68

0.1U_0402_10V7K~D

2

+1.05VS_SATA3

1

2

RH238

12

0_0805_5%~D

CH75

+1.05VS

1U_0402_6.3V6K~D

12

RH244 0_0603_5%~D

1 2

RH245 180_0402_1%@

2

+1.05VS

+3V_PCH

12

+1.05VS

+3V_PCH

12

RH233

0_0805_5%~D
CH70
1U_0402_6.3V6K~D

+1.05VS

VCC3_3 = 2 66mA detal waiting f or newest spec

CCDMI = 42 mA detal w aiting for newest s pec

V

QH7
AO3419L_SOT23-3

D

S

12

100_0402_5%~D

100_0402_5%~D

G

2

RH222

RH227

@

RH236

0_0805_5%~D

13

1

2

+3V_PCH+5V_PCH

12

+3VS+5VS

12

12

Compal Electronics, Inc.

1

PCH_PWR_EN#<33>

+3V_PCH

+VCCA_USBSUS

+3V_PCH

+3VS

+3VS

12

12

+1.05VS

LH6

@

10UH_LBR2012T100M_20%~D

1 2

1

CH73

@

10U_0805_10V4Z~D

2

+3V_PCH

+3V_PCH

RH215

0_0603_5%~D

1

CH55

2

@

1U_0402_6.3V6K~D

+VCCSATAPLL_R

Place CH80 Near AK1 pin

If it support 3.3V audio signals
POP:RH228
Depop RH233/RH234

If it support 1.5V audio signals
POP:RH233/RH234
Depop R228

Title

PCH (7/8) PWR

Size Document Number Rev

LA-6801P

Date: Sheet

+5V_PCH+5VALW

12

R22

C8

20K_0402_5%~D

0.1U_0402_10V7K~D

21

DH2
RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

1

CH56

0.1U_0603_25V7K

2

21

DH3
RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

1

CH64
1U_0603_10V6K~D

2

+1.05VS

19 60Monday, December 06, 2010

0.3

of