COMPAL LA-6801P Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-6801P ( DAB00000410 )

46198531L01 -->R3
46198531L02 -->R1

PALB0

46198531L03 -->R3
46198531L04 -->R1

Dell/Compal Confidential

Schematic Document

2 2

Specter (Huron River)

Sandy Bridge(PGA) + Cougar Point(standard)

DISCRETE VGA N12E-GE-B (optimus)

3 3

2011-01-25

Rev: 1.0

4 4

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

C

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-6801P

LA-6801P

LA-6801P

1.0

1.0

1.0

of

of

of

1 61Tuesday, January 25, 2011

1 61Tuesday, January 25, 2011

1 61Tuesday, January 25, 2011

E

A

B

C

D

E

Compal Confidential

Project Code : PALB0

FFS

P.28

Fan Control

P.30

CPU XDP
Conn.

P.6

File Name : LA-6801P

1 1

HDMI
Conn.

DP Conn.

P.39

P.38

DP MUX

P.37

LVDS

2 2

Conn.

CRT Conn.

P.21

P.21

HDMI

DisplayPort

DisplayPort

DP (DIS)

DP

GPU
N12E-GE

P.40~45

PEG x16 (DIS)

LVDS

CRT

(UMA)

100MHz

2.7GT/s

DisplayPort

PCI-E x1

Port 3 Port 2 Port 1 Port 4

Mini Card-2

WLAN (Half)

USB[x]

3 3

port4

WWAN (Full)

USB[x]
port5

DMC/Daughter Board

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4 4

Power Circuit DC/DC

P.13

P.29

P.33

P.49~59

LAN(GbE)

AR8151-BL1A

RJ45

P.32

Card ReaderMini Card-1

RTS5209

P.22 P.23

9 in 1
Socket

P.23P.22

USB 3.0/2.0
Host Ctrl.

USB 3.0/2.0
Combo Conns x2

SPI ROM

Port 6

P.27

P.27

ENE 3810

P.13 P.31

Intel

Sandy Bridge

Processor

4C 45W SV

rPGA 989 Socket

P.5~10

DMI x4FDI x8

100MHz
5GB/s

Intel

Cougar Point

PCH

BGA 989 Balls

P13~20

SPI

P.31

Touch Pad Int.KBD

LPC Bus

ENE KB930

P.35

P.29 P.31

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 1066/1333 MHz

Port 0

SATA2.0

Port 2

Port 0

Port 2

Port 4

USB2.0

Port 5

Port 6

HD Audio

Port 8

BIOS ROM

204pin DDRIII SO-DIMM x2

P.28

P.28

P.26

P.21

P.32

P.32

P.32

P.11,12

DMC/Daughter Board

BANK 0, 1, 2, 3

SATA HDD Conn.

SATA ODD Conn.

USB 2.0

( USB Charger )

Digital Camera

Mini Card-1 (WLAN)

( Half )

Mini Card-2 (WWAN)

( Full )

AlienFX/ELC

P.34~36

BT 2.1 /BT 3.0

Audio Codec
ALC665-GR

TI TPA6017A2

Int. Speaker

P.24

P.25

P.25

( HeadPhone x2, MIC)

SIM Card

P.32

TPA6211A

sub-woofer conn.

Audio Jack x3

Digital MIC

P.25

P.25

P.25

P.24

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

C

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-6801P

LA-6801P

LA-6801P

1.0

1.0

1.0

of

of

of

2 61Tuesday, January 25, 2011

2 61Tuesday, January 25, 2011

2 61Tuesday, January 25, 2011

E

A

Compal Confidential

Project Code : PALB0
File Name : LA-6801P

B

C

D

E

1 1

LA-6801P M/B

40 pin

Wire

Camera

LCD Panel

Blue Tooth

LS-6801P

LS-6803P

INDICATOR/B

2 2

Led-Wireless

Led-CapsLock

Wire

6 pin

BTB conn.

WLAN WWAN/DMC

80 pin

DMC/B

14 pin

Wire

12 pin

Wire

20 pin

HDD

ODD

LF-6801P

FPC

FFC

20 pin

Wire

6 pin

FFC

12 pin

LS-6802P

TP LED/B

Touch Pad

3 3

FFC

4 pin

Led x 6

Lid

LS-6809P

LOGO LIGHT GUIDE/B

Led x 6

LS-6806P

POWER BUTTON/B

on/off SW

Led x 3

4 pin4 pin

WireWire

LS-6807P

LS-6808P

FRONT LIGHT L/B

Led x 2 Led x 2

4 4

A

FRONT LIGHT R/B

B

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

C

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

of

of

of

3 61Tuesday, January 25, 2011

3 61Tuesday, January 25, 2011

3 61Tuesday, January 25, 2011

E

1.0

1.0

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%
Ra

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

100K +/- 5%

Rb V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SOURCE

KB930

KB930

PCH

PCH

PCH

MINI1 BATT SODIMM

V V

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

MINI2

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

Thermal
Sensor 1

V V

V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal
Sensor 2

max

FFS VGA

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal
Sensor

V

V V

A

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

DMCVXDP

Charger

V

V

PCB Revision

0.1

0.2

0.3

0.4

1.0

Link

PCH

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

12

DESTINATION

None

JUSB1 (2.0 Ext Left Side)

Bluetooth

CAMERA

JMINI1 (WLAN)

JMINI2 (WWAN/DMC)

ELC 8051

None

None

None

None

None

None

CLKOUT

1 1

PCI0

PCI1

PCI2

PCI3

PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

None

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

None

10/100/1G LAN

MINI CARD-2 WWAN

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

A

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

None

ODD

None

None

None

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Secret Data

Compal Secret Data

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

13

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

None

DESTINATION

10/100/1G LAN

MINI CARD-2 WWAN/DMC

MINI CARD-1 WLAN

CARD READER

None

USB 3.0

None

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-6801P

LA-6801P

LA-6801P

4 61Tuesday, January 25, 2011

4 61Tuesday, January 25, 2011

4 61Tuesday, January 25, 2011

1.0

1.0

1.0

5

JCPU1A

D D

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15 >
FDI_CTX_PRX_N1<15 >
FDI_CTX_PRX_N2<15 >
FDI_CTX_PRX_N3<15 >
FDI_CTX_PRX_N4<15 >
FDI_CTX_PRX_N5<15 >

C C

B B

FDI_CTX_PRX_N6<15 >
FDI_CTX_PRX_N7<15 >

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

+VCCP

RC36 24.9_0402_1%

RC36 24.9_0402_1%

R1942 10K _0402_5%~DR1942 10K _0402_5%~D

1 2

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

12

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

CONN@

CONN@

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

PEG_GTX_C_HRX_N15

K33

PEG_GTX_C_HRX_N14

M35

PEG_GTX_C_HRX_N13

L34

PEG_GTX_C_HRX_N12

J35

PEG_GTX_C_HRX_N11

J32

PEG_GTX_C_HRX_N10

H34

PEG_GTX_C_HRX_N9

H31

PEG_GTX_C_HRX_N8

G33

PEG_GTX_C_HRX_N7

G30

PEG_GTX_C_HRX_N6

F35

PEG_GTX_C_HRX_N5

E34

PEG_GTX_C_HRX_N4

E32

PEG_GTX_C_HRX_N3

D33

PEG_GTX_C_HRX_N2

D31

PEG_GTX_C_HRX_N1

B33

PEG_GTX_C_HRX_N0

C32

PEG_GTX_C_HRX_P15

J33

PEG_GTX_C_HRX_P14

L35

PEG_GTX_C_HRX_P13

K34

PEG_GTX_C_HRX_P12

H35

PEG_GTX_C_HRX_P11

H32

PEG_GTX_C_HRX_P10

G34

PEG_GTX_C_HRX_P9

G31

PEG_GTX_C_HRX_P8

F33

PEG_GTX_C_HRX_P7

F30

PEG_GTX_C_HRX_P6

E35

PEG_GTX_C_HRX_P5

E33

PEG_GTX_C_HRX_P4

F32

PEG_GTX_C_HRX_P3

D34

PEG_GTX_C_HRX_P2

E31

PEG_GTX_C_HRX_P1

C33

PEG_GTX_C_HRX_P0

B32

PEG_HTX_GRX_N15

M29

PEG_HTX_GRX_N14

M32

PEG_HTX_GRX_N13

M31

PEG_HTX_GRX_N12

L32

PEG_HTX_GRX_N11

L29

PEG_HTX_GRX_N10

K31

PEG_HTX_GRX_N9

K28

PEG_HTX_GRX_N8

J30

PEG_HTX_GRX_N7

J28

PEG_HTX_GRX_N6

H29

PEG_HTX_GRX_N5

G27

PEG_HTX_GRX_N4

E29

PEG_HTX_GRX_N3

F27

PEG_HTX_GRX_N2

D28

PEG_HTX_GRX_N1

F26

PEG_HTX_GRX_N0

E25

PEG_HTX_GRX_P15

M28

PEG_HTX_GRX_P14

M33

PEG_HTX_GRX_P13

M30

PEG_HTX_GRX_P12

L31

PEG_HTX_GRX_P11

L28

PEG_HTX_GRX_P10

K30

PEG_HTX_GRX_P9

K27

PEG_HTX_GRX_P8

J29

PEG_HTX_GRX_P7

J27

PEG_HTX_GRX_P6

H28

PEG_HTX_GRX_P5

G28

PEG_HTX_GRX_P4

E28

PEG_HTX_GRX_P3

F28

PEG_HTX_GRX_P2

D27

PEG_HTX_GRX_P1

E26

PEG_HTX_GRX_P0

D25

+VCCP

12

RC2

RC2

24.9_0402_1%

24.9_0402_1%

PEG_COMP

CC200 220nF_0402_16V7 K

CC200 220nF_0402_16V7 K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CC199 220nF_0402_16V7 K

CC199 220nF_0402_16V7 K
CC198 220nF_0402_16V7 K

CC198 220nF_0402_16V7 K
CC197 220nF_0402_16V7 K

CC197 220nF_0402_16V7 K
CC196 220nF_0402_16V7 K

CC196 220nF_0402_16V7 K
CC195 220nF_0402_16V7 K

CC195 220nF_0402_16V7 K
CC194 220nF_0402_16V7 K

CC194 220nF_0402_16V7 K
CC193 220nF_0402_16V7 KCC193 220nF_0402_16V7 K
CC192 220nF_0402_16V7 KCC192 220nF_0402_16V7 K
CC191 220nF_0402_16V7 KCC191 220nF_0402_16V7 K
CC190 220nF_0402_16V7 KCC190 220nF_0402_16V7 K
CC189 220nF_0402_16V7 KCC189 220nF_0402_16V7 K
CC188 220nF_0402_16V7 KCC188 220nF_0402_16V7 K
CC187 220nF_0402_16V7 KCC187 220nF_0402_16V7 K
CC186 220nF_0402_16V7 KCC186 220nF_0402_16V7 K
CC185 220nF_0402_16V7 KCC185 220nF_0402_16V7 K

CC216 220nF_0402_16V7 K

CC216 220nF_0402_16V7 K
CC215 220nF_0402_16V7 K

CC215 220nF_0402_16V7 K
CC214 220nF_0402_16V7 K

CC214 220nF_0402_16V7 K
CC213 220nF_0402_16V7 K

CC213 220nF_0402_16V7 K
CC212 220nF_0402_16V7 K

CC212 220nF_0402_16V7 K
CC211 220nF_0402_16V7 K

CC211 220nF_0402_16V7 K
CC210 220nF_0402_16V7 K

CC210 220nF_0402_16V7 K
CC209 220nF_0402_16V7 KCC209 220nF_0402_16V7 K
CC208 220nF_0402_16V7 KCC208 220nF_0402_16V7 K
CC207 220nF_0402_16V7 KCC207 220nF_0402_16V7 K
CC206 220nF_0402_16V7 K

CC206 220nF_0402_16V7 K
CC205 220nF_0402_16V7 KCC205 220nF_0402_16V7 K
CC204 220nF_0402_16V7 KCC204 220nF_0402_16V7 K
CC203 220nF_0402_16V7 KCC203 220nF_0402_16V7 K
CC202 220nF_0402_16V7 KCC202 220nF_0402_16V7 K
CC201 220nF_0402_16V7 KCC201 220nF_0402_16V7 K

3

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_C_HRX_N15 <40>
PEG_GTX_C_HRX_N14 <40>
PEG_GTX_C_HRX_N13 <40>
PEG_GTX_C_HRX_N12 <40>
PEG_GTX_C_HRX_N11 <40>
PEG_GTX_C_HRX_N10 <40>
PEG_GTX_C_HRX_N9 <40>
PEG_GTX_C_HRX_N8 <40>
PEG_GTX_C_HRX_N7 <40>
PEG_GTX_C_HRX_N6 <40>
PEG_GTX_C_HRX_N5 <40>
PEG_GTX_C_HRX_N4 <40>
PEG_GTX_C_HRX_N3 <40>
PEG_GTX_C_HRX_N2 <40>
PEG_GTX_C_HRX_N1 <40>
PEG_GTX_C_HRX_N0 <40>

PEG_GTX_C_HRX_P15 <40>
PEG_GTX_C_HRX_P14 <40>
PEG_GTX_C_HRX_P13 <40>
PEG_GTX_C_HRX_P12 <40>
PEG_GTX_C_HRX_P11 <40>
PEG_GTX_C_HRX_P10 <40>
PEG_GTX_C_HRX_P9 <40>
PEG_GTX_C_HRX_P8 <40>
PEG_GTX_C_HRX_P7 <40>
PEG_GTX_C_HRX_P6 <40>
PEG_GTX_C_HRX_P5 <40>
PEG_GTX_C_HRX_P4 <40>
PEG_GTX_C_HRX_P3 <40>
PEG_GTX_C_HRX_P2 <40>
PEG_GTX_C_HRX_P1 <40>
PEG_GTX_C_HRX_P0 <40>

PEG_HTX_C_GRX_N15 <40>
PEG_HTX_C_GRX_N14 <40>
PEG_HTX_C_GRX_N13 <40>
PEG_HTX_C_GRX_N12 <40>
PEG_HTX_C_GRX_N11 <40>
PEG_HTX_C_GRX_N10 <40>
PEG_HTX_C_GRX_N9 <40>
PEG_HTX_C_GRX_N8 <40>
PEG_HTX_C_GRX_N7 <40>
PEG_HTX_C_GRX_N6 <40>
PEG_HTX_C_GRX_N5 <40>
PEG_HTX_C_GRX_N4 <40>
PEG_HTX_C_GRX_N3 <40>
PEG_HTX_C_GRX_N2 <40>
PEG_HTX_C_GRX_N1 <40>
PEG_HTX_C_GRX_N0 <40>

PEG_HTX_C_GRX_P15 <40>
PEG_HTX_C_GRX_P14 <40>
PEG_HTX_C_GRX_P13 <40>
PEG_HTX_C_GRX_P12 <40>
PEG_HTX_C_GRX_P11 <40>
PEG_HTX_C_GRX_P10 <40>
PEG_HTX_C_GRX_P9 <40>
PEG_HTX_C_GRX_P8 <40>
PEG_HTX_C_GRX_P7 <40>
PEG_HTX_C_GRX_P6 <40>
PEG_HTX_C_GRX_P5 <40>
PEG_HTX_C_GRX_P4 <40>
PEG_HTX_C_GRX_P3 <40>
PEG_HTX_C_GRX_P2 <40>
PEG_HTX_C_GRX_P1 <40>
PEG_HTX_C_GRX_P0 <40>

2

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

CONN@

CONN@

A A

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

LA-6801P

LA-6801P

LA-6801P

1

of

of

of

5 61Tuesday, January 25, 2011

5 61Tuesday, January 25, 2011

5 61Tuesday, January 25, 2011

1.0

1.0

1.0

5

XDP_PREQ#_R
XDP_PRDY#_R

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

CFG10_R

RC130_0402_5%~D @ RC130_04 02_5%~D @

1 2
1 2

1 2
1 2

1 2

12

RC150_0402_5%~D @ RC150_04 02_5%~D @

12

RC221K_0402_5%~D RC221K_0402_5%~D
RC230_0402_5%~D RC230_040 2_5%~D

RC241K_0402_5%~D RC241K_0402_5%~D
RC260_0402_5%~D RC260_0402_5%~D

RC30

RC30

CFG11_R

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

XDP_HOOK2
SYS_PWROK_XDP

XDP_TCK1
XDP_TCK_R

D D

C C

CFG10<8>
CFG11<8>

H_CPUPWRGD

CFG0<8>

VGATE<15,31,57>

PCH_JTAG_TCK<13>

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

PCH_SMBDATA<11,12,14,28,32>
PCH_SMBCLK<11,12,14,28,32>

0_0402_5%~D @

0_0402_5%~D @

+VCCP +VCCP

+3VALW

12

@

@

RC27

RC27
1K_0402_5%~D

1K_0402_5%~D

SYS_PWROK_XDP

4

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_A B

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

CONN@

CONN@

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_C D

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

JCPU1B

JCPU1B

3

PM_DRAM_PWRGD<15>

PCH_PWROK<15,31>

SYS_PWROK<15>

+3V_PCH

1 2

2

CFG16_R

RC3 0_0402_5%~D@RC3 0_04 02_5%~D@

4

CFG17_R

6
8

CFG0_R

10

CFG1_R

12
14

CFG2_R

16

CFG3_R

18
20

CFG8_R

22

CFG9_R

24
26

CFG4_R

28

CFG5_R

30
32

CFG6_R

34

CFG7_R

36
38

CLK_CPU_ITP

40

CLK_CPU_ITP#

42
44

XDP_RST#_R

46

XDP_DBRES ET#

48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#_R

54

XDP_TDI

56

XDP_TMS_R

58
60

1 2

RC5 0_0402_5%~D@RC5 0_04 02_5%~D@

1 2

RC7 0_0402_5%~D@RC7 0_04 02_5%~D@

1 2

RC9 0_0402_5%~D@RC9 0_04 02_5%~D@

1 2

RC10 0_0402_5%~D@RC10 0_0402_5 %~D@

1 2

RC12 0_0402_5%~D@RC12 0_0402_5 %~D@

1 2

RC14 0_0402_5%~D@RC14 0_0402_5 %~D@

1 2

RC16 0_0402_5%~D@RC16 0_0402_5 %~D@

1 2

RC17 0_0402_5%~D@RC17 0_0402_5 %~D@

1 2

RC18 0_0402_5%~D@RC18 0_0402_5 %~D@

1 2

RC20 0_0402_5%~D@RC20 0_0402_5 %~D@

1 2

RC21 0_0402_5%~D@RC21 0_0402_5 %~D@

1 2

1 2

RC25 1K_0402_5%~DRC25 1K_0402_5%~D

RC28 0_0402_5%~D@RC28 0_0402_5%~D@

1 2

RC31 0_0402_5%~D@RC31 0_0402_5%~D@

1 2

RC29 0_0402_5%~D@RC29 0_0402_5%~D@

1 2

+VCCP

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CC67

CC67

2

CFG16 <8>
CFG17 <8>

CFG0 <8>
CFG1 <8>

CFG2 <8>
CFG3 <8>

CFG8 <8>
CFG9 <8>

CFG4 <8>
CFG5 <8>

CFG6 <8>
CFG7 <8>

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,31>

PLT_RST#

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

CC66

CC66

2

Place near JXDP1

0_0402_5%~D

0_0402_5%~D

RC4

RC4

200_0402_1%

200_0402_1%

2

RC128

RC128

RC127

RC127

@

@

1 2

1 2

0_0402_5%~D

0_0402_5%~D

1 2

RC11 0_0402_5%~DRC11 0_0402_5%~D

RUN_ON_CPU1.5VS3#<10,33>

PLT_RST#<16,22,23,27,31,32>

+3VS

12

@

@

RC6

RC6

10K_0402_5%~D

10K_0402_5%~D

D_PWG

1
2

+3VALW

UC1

UC1

5

B

VCC

A

4

GND3Y

74AHC1G09GW TSSOP 5P

74AHC1G09GW TSSOP 5P

RUN_ON_CPU1.5VS3#

UC2

UC2

1

NC

VCC

2

A
GND3Y

SN74LVC1G07DC KR_SC70-5~D

SN74LVC1G07DC KR_SC70-5~D

5

4

2

G

G

+3VALW

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+1.5V_CPU_VDDQ

CC65

CC65

1

2

RC19

RC19
39_0402_1%

39_0402_1%

1 2

13

D

D

QC1

QC1
SSM3K7002F_S C59-3

SSM3K7002F_S C59-3

S

S

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

1

2

BUFO_CPU_RST#

1

12

RC8

RC8
200_0402_1%

200_0402_1%

VDDPWRGOOD

RC8
CRB 1.1K
CHECK LIST 0.7 --> 4.75K
INTEL recommand 1.1K
PDG 0.71 rev -->200

+VCCP

CC68

CC68

12

RC32

RC32
75_0402_5%

75_0402_5%

RC33

RC33

1 2

43_0402_1%

43_0402_1%

BUF_CPU_RST#

12

@

@

RC34

RC34
0_0402_5%~D

0_0402_5%~D

CLK_CPU_DMI_R

A28

DPLL_REF_CLK

DPLL_REF_CLK #

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

3

BCLK

BCLK#

PRDY#
PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H_SNB_IVB#<17>

+VCCP

RC41

RC41

RC49

RC49

RC53

RC53

RC57

RC57

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

4

T1PAD~D @T1PAD~D @

RC43

RC43

62_0402_5%

62_0402_5%

B B

A A

H_PROCHOT#<31>

5

1 2

H_THERMTRIP#<17>

H_PM_SYNC<15>

H_CPUPWRGD<17>

H_PECI<17,31>

VDDPWRGOOD

1 2

56_0402_5%

56_0402_5%

1 2

0_0402_5%~D

0_0402_5%~D

1 2

0_0402_5%~D

0_0402_5%~D

1 2

130_0402_1%~D

130_0402_1%~D

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

CONN@

CONN@

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

CLK_CPU_DMI#_R

A27

CLK_CPU_DP LL_R

A16

CLK_CPU_DP LL#_R

A15

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

DDR3 Compensation Signals

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

TCK

XDP_TMS

AR27

TMS

XDP_TRST#

AP30

XDP_TDI_R

AR28

TDI

XDP_TDO_R

AP26

TDO

XDP_DBRES ET#_R

AL35

XDP_BPM#0_ R

AT28

XDP_BPM#1_ R

AR29

XDP_BPM#2_ R

AR30

XDP_BPM#3_ R

AT30

XDP_BPM#4_ R

AP32

XDP_BPM#5_ R

AR31

XDP_BPM#6_ R

AT31

XDP_BPM#7_ R

AR32

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

RC37 0_0402_5%~DRC37 0_0402_5%~D

1 2

RC38 0_0402_5%~DRC38 0_0402_5%~D

1 2

RC39 0_0402_5%~DRC39 0_0402_5%~D

1 2

RC40 0_0402_5%~DRC40 0_0402_5%~D

1 2

H_DRAMRST# <7>

RC55140_0402_1% RC55140_0402_1 %

1 2

RC5825.5_0402_1% RC5825.5_0402_1%

1 2

RC60200_0402_1% RC60200_0402_1 %

1 2

for EMC request, close to CPU 7/26

RC121 0_0402_5%~DRC121 0_0402_5%~D

1 2

RC122 0_0402_5%~DRC122 0_0402_5%~D

1 2

RC123 0_0402_5%~DRC123 0_0402_5%~D

1 2

RC124 0_0402_5%~DRC124 0_0402_5%~D

1 2

RC125 0_0402_5%~DRC125 0_0402_5%~D

1 2

RC50 0_0402_5%~DRC50 0_0402_5%~D

1 2

RC51 0_0402_5%~DRC51 0_0402_5%~D

1 2

RC56

RC56

1 2

RC59 0_0402_5%~DRC59 0_0402_5%~D

1 2

RC61 0_0402_5%~DRC61 0_0402_5%~D

1 2

RC62 0_0402_5%~DRC62 0_0402_5%~D

1 2

RC63 0_0402_5%~DRC63 0_0402_5%~D

1 2

RC64 0_0402_5%~DRC64 0_0402_5%~D

1 2

RC65 0_0402_5%~DRC65 0_0402_5%~D

1 2

RC66 0_0402_5%~DRC66 0_0402_5%~D

1 2

RC67 0_0402_5%~DRC67 0_0402_5%~D

1 2

RC68 0_0402_5%~DRC68 0_0402_5%~D

1 2

RC69 0_0402_5%~DRC69 0_0402_5%~D

1 2

RC70 0_0402_5%~DRC70 0_0402_5%~D

1 2

RC71 0_0402_5%~DRC71 0_0402_5%~D

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI
XDP_TDO

close to CPU 7/26

XDP_DBRES ET#

0_0402_5%~D

0_0402_5%~D

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

CFG12 <8>
CFG13 <8>
CFG14 <8>
CFG15 <8>

2

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

CLK_CPU_DP LL <14>
CLK_CPU_DP LL# <14>

XDP_DBRES ET# <15>

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_DBRES ET#

H_CPUPWRGD_R

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

LA-6801P

LA-6801P

LA-6801P

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

+VCCP

RC4551_0402_5% RC4551_0402_5 %

RC4651_0402_5% RC4651_0402_5 %

RC4751_0402_5% @ RC4751_0402_5% @

RC4851_0402_5% RC4851_0402_5%

RC5251_0402_5% RC5251_0402_5 %

RC5451_0402_5% RC5451_0402_5 %

+3VS

RC421K_0402_5%~D RC421K_0402_5%~D

RC4410K_0402_5%~D RC4410K_0402_5%~D

of

of

of

6 61Tuesday, January 25, 2011

6 61Tuesday, January 25, 2011

6 61Tuesday, January 25, 2011

1.0

1.0

1.0

5

JCPU1C

JCPU1C

DDR_A_D[0.. 63]< 11>

D D

C C

B B

A A

DDR_A_BS0<1 1>
DDR_A_BS1<1 1>
DDR_A_BS2<1 1>

DDR_A_CAS#<11 >
DDR_A_RAS#<11 >
DDR_A_WE#<11>

H_DRAMRST#<6>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_DRAMRST#

4.99K_04 02_1%~D

4.99K_04 02_1%~D

5

RC77

RC77

AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12

AJ14
AH14
AL15
AK15
AL14
AK14

AJ15
AH15

AE10
AF10

C5
D5
D3
D2
D6
C6
C2
C3

F10

F8

G10

G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8

N10

N8
N7

M10

M9
N9

M7
AG6
AG5
AK6
AK5
AH5
AH6

AJ5
AJ6
AJ8

AK8

AJ9
AK9
AH8
AH9
AL9
AL8

V6

AE8
AD9
AF9

12

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

Sandy Brid ge_rPGA_Rev1 p0

Sandy Brid ge_rPGA_Rev1 p0

CONN@

CONN@

@

@

1 2

RC74 0_0402_5 %~D

RC74 0_0402_5 %~D

QC2

QC2

BSS138_SOT23

BSS138_SOT23

S

S

G

G

2

1

2

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

D

D

DDR3_DRAMRST#_R

13

DRAMRST_CNTRL

CC69

CC69
.047U_0 402_16V7K~D

.047U_0 402_16V7K~D

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

AH2

RSVD_TP[10]

C4

SA_DQS#[0]

G6

SA_DQS#[1]

J3

SA_DQS#[2]

M6

SA_DQS#[3]

AL6

SA_DQS#[4]

AM8

SA_DQS#[5]

AR12

SA_DQS#[6]

AM15

SA_DQS#[7]

D4

SA_DQS[0]

F6

SA_DQS[1]

K3

SA_DQS[2]

N6

SA_DQS[3]

AL5

SA_DQS[4]

AM9

SA_DQS[5]

AR11

SA_DQS[6]

AM14

SA_DQS[7]

AD10

SA_MA[0]

W1

SA_MA[1]

W2

SA_MA[2]

W7

SA_MA[3]

V3

SA_MA[4]

V2

SA_MA[5]

W3

SA_MA[6]

W6

SA_MA[7]

V1

SA_MA[8]

W5

SA_MA[9]

AD8

SA_MA[10]

V4

SA_MA[11]

W4

SA_MA[12]

AF8

SA_MA[13]

V5

SA_MA[14]

V7

SA_MA[15]

+1.5V

12

RC75

RC75
1K_0402 _5%~D

1K_0402 _5%~D

1 2

RC76 1K_0402_5 %~D

RC76 1K_0402_5 %~D

DG 1.0 Figure 61 RC76=1K

4

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

1 2

RC72 0_0402_5 %~DRC72 0_0402_ 5%~D

@

@

1 2

RC73 0_0402_5 %~D

RC73 0_0402_5 %~D

M_CLK_DDR0 <11 >
M_CLK_DDR#0 <1 1>
DDR_CKE0_DIMMA <11 >

M_CLK_DDR1 <11 >
M_CLK_DDR#1 <1 1>
DDR_CKE1_DIMMA <11 >

DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>

M_ODT0 <11 >
M_ODT1 <11 >

DDR_A_DQS#[ 0..7] <11>

DDR_A_DQS[0 ..7] <11>

DDR_A_MA[0..1 5] <11>

DDR3_DRAMRST# <11,1 2>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL_EC <31>

3

DDR_B_D[0.. 63]< 12>

DDR_B_BS0<1 2>
DDR_B_BS1<1 2>
DDR_B_BS2<1 2>

DDR_B_CAS#<12 >
DDR_B_RAS#<12 >
DDR_B_WE#<12>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

2

JCPU1D

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

Sandy Brid ge_rPGA_Rev1 p0

Sandy Brid ge_rPGA_Rev1 p0

CONN@

CONN@

2

1

M_CLK_DDR2

AE2

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

M_CLK_DDR#2

AD2

DDR_CKE2_DIMMB

R9

M_CLK_DDR3

AE1

M_CLK_DDR#3

AD1

DDR_CKE3_DIMMB

R10

AB2
AA2
T9

AA1
AB1
T10

DDR_CS2_DIMMB#

AD3

DDR_CS3_DIMMB#

AE3
AD6
AE6

M_ODT2

AE4

M_ODT3

AD4
AD5
AE5

DDR_B_DQS#0

D7

DDR_B_DQS#1

F3

DDR_B_DQS#2

K6

DDR_B_DQS#3

N3

DDR_B_DQS#4

AN5

DDR_B_DQS#5

AP9

DDR_B_DQS#6

AK12

DDR_B_DQS#7

AP15

DDR_B_DQS0

C7

DDR_B_DQS1

G3

DDR_B_DQS2

J6

DDR_B_DQS3

M3

DDR_B_DQS4

AN6

DDR_B_DQS5

AP8

DDR_B_DQS6

AK11

DDR_B_DQS7

AP14

DDR_B_MA0

AA8

DDR_B_MA1

T7

DDR_B_MA2

R7

DDR_B_MA3

T6

DDR_B_MA4

T2

DDR_B_MA5

T4

DDR_B_MA6

T3

DDR_B_MA7

R2

DDR_B_MA8

T5

DDR_B_MA9

R3

DDR_B_MA10

AB7

DDR_B_MA11

R1

DDR_B_MA12

T1

DDR_B_MA13

AB10

DDR_B_MA14

R5

DDR_B_MA15

R4

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

LA-6801P

LA-6801P

LA-6801P

1

M_CLK_DDR2 <12 >
M_CLK_DDR#2 <1 2>
DDR_CKE2_DIMMB <12 >

M_CLK_DDR3 <12 >
M_CLK_DDR#3 <1 2>
DDR_CKE3_DIMMB <12 >

DDR_CS2_DIMMB# < 12>
DDR_CS3_DIMMB# < 12>

M_ODT2 <12 >
M_ODT3 <12 >

DDR_B_DQS#[ 0..7] <12 >

DDR_B_DQS[0 ..7] <12>

DDR_B_MA[0..1 5] <12>

7 61Tuesday, J anuary 25, 2011

7 61Tuesday, J anuary 25, 2011

7 61Tuesday, J anuary 25, 2011

of

of

of

1.0

1.0

1.0

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

JCPU1E

L7

RSVD28

AG7

RESERVED

RESERVED

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

KEY

CFG0<6>
CFG1<6>
CFG2<6>
CFG3<6>
CFG4<6>
CFG5<6>
CFG6<6>
CFG7<6>
CFG8<6>
CFG9<6>

+VCC_GFXCORE_AXG

+VCC_CORE

@

@

RC80

RC80
50_040 2_1%

50_040 2_1%

1 2

C C

+V_DDR_REFA

+V_DDR_REFB

B B

RC82 0_0402_5%~D@RC82 0_0402_ 5%~D@

1 2

RC83 0_0402_5%~D@RC83 0_0402_ 5%~D@

1 2

@

@

RC79

RC79
50_040 2_1%

50_040 2_1%

1 2

VCC_AXG_VAL_SENSE

VCC_VAL_SENSE

12

12

RC85

RC85

RC84

RC84

1K_0402 _1%~D

1K_0402 _1%~D

1K_0402 _1%~D

INTEL 1 2/28 rec ommand
to add 1k pull down

VCCP_PWRCTRL<54 >

1K_0402 _1%~D

CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>
CFG16<6>
CFG17<6>

+V_DDR_REFA_R
+V_DDR_REFB_R

1 2

RC88 0_0402_5%~DRC88 0_04 02_5%~D

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

T19PAD~D @T19PAD~D @

T25PAD~D @T25PAD~D @
T26PAD~D @T26PAD~D @
T27PAD~D @T27PAD~D @
T28PAD~D @T28PAD~D @
T30PAD~D @T30PAD~D @
T32PAD~D @T32PAD~D @
T33PAD~D @T33PAD~D @
T34PAD~D @T34PAD~D @
T35PAD~D @T35PAD~D @
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T39PAD~D @T39PAD~D @
T40PAD~D @T40PAD~D @
T41PAD~D @T41PAD~D @
T42PAD~D @T42PAD~D @
T43PAD~D @T43PAD~D @

T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @

H_VCCP_SEL

T49PAD~D @T49PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Need PWR add ne w circuit on 1. 05V(refer CRB)

Sandy Brid ge_rPGA_Rev1 p0

Sandy Brid ge_rPGA_Rev1 p0

CONN@

CONN@

T2 PAD~D@ T2 PAD~D@
T3 PAD~D@ T3 PAD~D@
T4 PAD~D@ T4 PAD~D@
T5 PAD~D@ T5 PAD~D@
T6 PAD~D@ T6 PAD~D@

T7 PAD~D@ T7 PAD~D@
T8 PAD~D@ T8 PAD~D@
T9 PAD~D@ T9 PAD~D@

T10 PAD~D@ T10 PAD~D@
T11 PAD~D@ T11 PAD~D@
T12 PAD~D@ T12 PAD~D@
T13 PAD~D@ T13 PAD~D@

T14 PAD~D@ T14 PAD~D@
T15 PAD~D@ T15 PAD~D@
T16 PAD~D@ T16 PAD~D@
T17 PAD~D@ T17 PAD~D@
T18 PAD~D@ T18 PAD~D@

T20 PAD~D@ T20 PAD~D@
T21 PAD~D@ T21 PAD~D@
T22 PAD~D@ T22 PAD~D@
T23 PAD~D@ T23 PAD~D@
T24 PAD~D@ T24 PAD~D@

T29 PAD~D@ T29 PAD~D@
T31 PAD~D@ T31 PAD~D@

T36 PAD~D@ T36 PAD~D@

CLK_RES_ITP <14>
CLK_RES_ITP# <14 >

T46 PAD~D@ T46 PAD~D@
T47 PAD~D@ T47 PAD~D@
T48 PAD~D@ T48 PAD~D@

T50 PAD~D@ T50 PAD~D@

CFG[6:5 ]

CFG2

12

RC78

RC78
1K_0402 _1%~D

1K_0402 _1%~D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Defa ult) Nor mal Oper ation; L ane #

CFG2

definit ion matc hes sock et pin m ap defin ition

0:Lane Reversed

*

CFG4

12

RC81

@ RC81

@

1K_0402 _1%~D

1K_0402 _1%~D

Display Port Presence Strap

1 : Dis abled; N o Physic al Displ ay Port

*

CFG4

attache d to Emb edded Di splay Po rt

0 : Ena bled; An externa l Displa y Port d evice is
connect ed to th e Embedd ed Displ ay Port

CFG6

CFG5

1K_0402 _1%~D

1K_0402 _1%~D

RC87

@ RC87

@

12

12

RC86

@ RC86

@

1K_0402 _1%~D

1K_0402 _1%~D

PCIE Port Bifurcation Straps

11: (De fault) x 16 - Dev ice 1 fu nctions 1 and 2 disable d

*

10: x8, x8 - De vice 1 f unction 1 enable d ; func tion 2
dis abled

01: Res erved - (Device 1 functi on 1 dis abled ; functio n
2 e nabled)
00: x8, x4,x4 - Device 1 functio ns 1 and 2 enabl ed

CFG7

12

RC89

@ RC89

@

1K_0402 _1%~D

1K_0402 _1%~D

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

@

@

RC90

RC90

50_040 2_1%

A A

50_040 2_1%

INTEL 1 2/28 rec ommand
to add RC120, R C121, RC 122, RC1 23
Please place as close a s JCPU1

5

@

@

RC91

RC91
50_040 2_1%

50_040 2_1%

1 2

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

PEG DEFER TRAINING

1: (Def ault) PE G Train immediat ely

*

CFG7

followi ng xxRES ETB de a ssertion

0: PEG Wait for BIOS fo r traini ng

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

LA-6801P

LA-6801P

LA-6801P

8 61Tuesday, J anuary 25, 2011

8 61Tuesday, J anuary 25, 2011

8 61Tuesday, J anuary 25, 2011

1

of

of

of

1.0

1.0

1.0

5

+VCC_CORE

1

CC70

CC70
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC89

CC89
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC114

CC114
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC119

CC119
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC124

CC124
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC129

CC129
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

+

+

CC133

CC133

2

470U_D2 _2VM_R4.5M~D

470U_D2 _2VM_R4.5M~D

1

CC86

CC86
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC90

CC90
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC115

CC115
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC120

CC120
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC125

CC125
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC130

CC130
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

+

+

2

470U_D2 _2VM_R4.5M~D

470U_D2 _2VM_R4.5M~D

+VCC_CORE

+VCC_CORE

1

CC85

CC85
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC82

CC82
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC113

CC113
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC118

CC118
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC123

CC123
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC128

CC128
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

+

+

2

470U_D2 _2VM_R4.5M~D

470U_D2 _2VM_R4.5M~D

1

+

+

CC136

CC136

2

470U_D2 _2VM_R4.5M~D

470U_D2 _2VM_R4.5M~D

CC132

CC132

D D

C C

B B

A A

CC134

CC134

1

CC87

CC87
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC91

CC91
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC116

CC116
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC121

CC121
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC126

CC126
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC131

CC131
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

+

+

CC135

CC135

2

470U_D2 _2VM_R4.5M~D

470U_D2 _2VM_R4.5M~D

4

1

CC71

CC71
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC83

CC83
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

1

CC117

CC117
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC122

CC122
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC127

CC127
22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

2

1

CC84

CC84
10U_080 5_4VAM~D

10U_080 5_4VAM~D

2

+VCC_CORE

JCPU1F

JCPU1F

QC=94A
DC=53A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Brid ge_rPGA_Rev1 p0

Sandy Brid ge_rPGA_Rev1 p0

CONN@

CONN@

3

POWER

POWER

CORE SUPPLY

CORE SUPPLY

2

8.5A

PDDG 0.7@P12

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

VSSIO_SENSE

C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

VCCSENSE_R
VSSSENSE_R

PEG AND DDR

PEG AND DDR

VCCIO_SENSE

SENSE LINES SVID

SENSE LINES SVID

130_04 02_1%~D

130_04 02_1%~D

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

CC72

CC72

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

CC92

CC92

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

CC103

CC103

2

RC95

RC95

RC98 0_040 2_5%~DRC98 0_04 02_5%~D

1 2

RC99 0_040 2_5%~DRC99 0_04 02_5%~D

1 2

VCCIO_SENSE <54>
VSSIO_SENSE <54>

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC73

CC73

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

CC93

CC93

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

CC104

CC104

2

12

1

CC74

CC74

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC94

CC94

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC105

CC105

2

2

RC95 close to CPU

RC94 43_04 02_1% RC94 43_0402_1 %

1 2

RC92 0_040 2_5%~DRC92 0_04 02_5%~D

1 2

RC96 0_040 2_5%~DRC96 0_04 02_5%~D

1 2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

CC75

CC75

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

CC95

CC95

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

CC106

CC106

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC77

CC77

CC76

CC76

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC97

CC97

CC96

CC96

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC107

CC107

CC108

CC108

2

2

+VCCP

+VCC_CORE

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

2

12

RC93

RC93
75_040 2_5%

75_040 2_5%

12

RC97

RC97
100_04 02_1%~D

100_04 02_1%~D

12

RC100

RC100
100_04 02_1%~D

100_04 02_1%~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC78

CC78

CC88

CC88

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC98

CC98

CC99

CC99

2

2

330U_D2 _2VM_R6M~D

330U_D2 _2VM_R6M~D

330U_D2 _2VM_R6M~D

330U_D2 _2VM_R6M~D

1

1

@

@

CC110

CC110

CC109

CC109

+

+

+

+

2

2

Place the PU
resistors close to CPU

VR_SVID_ALRT# <57>
VR_SVID_CLK <57 >
VR_SVID_DAT <57>

VCCSENSE <57>
VSSSENSE <57>

1

+VCCP

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC81

CC79

CC79

CC100

CC100

CC111

CC111

CC81

CC80

CC80

2

2

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

22U_080 5_6.3VAM~D

1

1

CC101

CC101

CC102

CC102

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

LA-6801P

LA-6801P

LA-6801P

9 61Tuesday, J anuary 25, 2011

9 61Tuesday, J anuary 25, 2011

9 61Tuesday, J anuary 25, 2011

of

of

1

of

1.0

1.0

1.0

5

12

RC10 2

RC10 2
100K_ 0402 _5%~D

100K_ 0402 _5%~D

CC145

CC145

CC153

CC153

1

2

1

2

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC175

CC175

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC146

CC146

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC154

CC154

1

2

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

1

+

+

2

RUN_ ON_CP U1.5VS3#

61

QC5A

QC5A
2N70 02DW-7 -F_SOT36 3-6~D

2N70 02DW-7 -F_SOT36 3-6~D

33A

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC147

CC147

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC155

CC155

@

@

CC176

CC176

JCPU1 G

JCPU1 G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

TBD

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bri dge_r PGA_Rev1p 0

Sandy Bri dge_r PGA_Rev1p 0

CONN @

CONN @

D D

RC10 4

@ RC1 04

@

1

2

1

2

CC15 7

CC15 7

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC142

CC142

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC150

CC150

1 2

0_04 02_5% ~D

0_04 02_5% ~D

1 2

0_04 02_5% ~D

0_04 02_5% ~D

CC21 7

0.1U_ 0402_ 10V7K~D

0.1U_ 0402_ 10V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC143

CC143

1

1

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC151

CC151

1

1

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CC172

CC172

2

RC10 7

RC10 7

@CC21 7

@

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

CC144

CC144

1

2

CC152

CC152

1

2

+1.8VS_VCC PLL

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC174

CC174

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

@

@

1

2

SUSP#<18,3 1,33,53 ,54>

CPU1 .5V_S3_GATE<31>

+VCC_GFXC ORE_AXG

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC140

CC140

CC141

CC141

1

1

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

C C

B B

22U_0805_6.3V6M~D

CC149

CC149

CC148

CC148

1

1

2

2

1

1

+

+

+

+

CC15 6

CC15 6

2

2

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D

+1.8VS

RC10 9 0_ 0805 _5%~DRC10 9 0_ 0805 _5%~D

1 2

4

B+_BIAS+3VALW

12

RC10 1

RC10 1
100K_ 0402 _5%~D

100K_ 0402 _5%~D

3

QC5B

QC5B

5

2N70 02DW-7 -F_SOT36 3-6~D

2N70 02DW-7 -F_SOT36 3-6~D

4

RUN_ ON_CP U1.5VS3# <6,33>

POWER

POWER

SENSE

SENSE

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_C PU_VDDQ

RUN_ ON_CP U1.5VS3

VSSAXG_SENSE

LINES

LINES

VREFMISC

VREFMISC

VAXG_SENSE

SM_VREF

QC3

QC3

AO4728L _SO8~D

AO4728L _SO8~D

8
7
6
5

4

0.1U_0603_50V_X7R

0.1U_0603_50V_X7R

12

1

2

RC105

RC105

330K_0402_1%

330K_0402_1%

VCC_AXG_SEN SE

AK35

VSS_AXG_SENS E

AK34

+V_SM_VREF should
have 10 mil trace width

+V_SM_VREF_ CNT

AL1

1
2

12

3

1

2

CC138

CC138

10U_0805_10V4Z~D

10U_0805_10V4Z~D

CC139

CC139

100K_ 0402 _5%~D

100K_ 0402 _5%~D

5A

AF7

VDDQ1

AF4

VDDQ2

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

H_FC_ C22

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC160

CC160

2

2

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CC167

CC167

2

VCCSA_SEL <55>

RC11 1

RC11 1

10K_0 402_ 5%~D

10K_0 402_ 5%~D

RC103

RC103

20K_0402_5%~D

20K_0402_5%~D

VCC_AXG_SEN SE <57>
VSS_AXG_SENS E <57 >

12

RC12 6

RC12 6

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CC161

CC161

CC162

CC162

2

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

CC168

CC168

CC169

CC169

2

2

12

3

1 2

RC10 6 0_04 02_5% ~D@RC1 06 0_04 02_5 %~D@

1

3

QC4

QC4

2

NTR45 03NT1 G_SOT23 -3~D

NTR45 03NT1 G_SOT23 -3~D

RUN_ ON_CP U1.5VS3

+1.5V_C PU_VDDQ

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

1

1

1

CC164

CC164

CC163

CC163

CC165

CC165

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

@

@

1

+

+

CC17 1

CC17 1

CC170

CC170

330U _D2_ 2VM_R6M~D

330U _D2_ 2VM_R6M~D

2

2

RC12 0 0_ 0402 _5%~DRC12 0 0_ 0402 _5%~D

1 2

12

RC11 0

@ RC 110

@

0_04 02_5% ~D

0_04 02_5% ~D

+V_SM_VREF

1

+

+

CC16 6

CC16 6
330U _D2_ 2VM_R6M~D

330U _D2_ 2VM_R6M~D

2

+VCCSA

VCCSA_SEN SE < 55>

2

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10

AT7
AT4

AT3
AR25
AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16

+1.5V_CP U_VDDQ

12

1K_04 02_5 %~D

1K_04 02_5 %~D
RC11 2

RC11 2

12

1K_04 02_5 %~D

1K_04 02_5 %~D
RC11 6

RC11 6

@

@

J8

J8

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

J8 OPEN

VSSSA_SEN SE <55>

+1.5V_CP U_VDDQ +1.5V

add CC181 , CC182, 4 caps are all pop.
follow checklist 1.0 5/24

+1.5V

CC18 2 0.1U_040 2_10 V7K~DCC182 0.1U _0402 _10V7K ~D

CC18 4 0.1U_040 2_10 V7K~DCC184 0.1U _0402 _10V7K ~D

CC18 1 0.1U_040 2_10 V7K~DCC181 0.1U _0402 _10V7K ~D

CC18 3 0.1U_040 2_10 V7K~DCC183 0.1U _0402 _10V7K ~D

AP13
AP10

AP7

AP4

AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7
AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7
AK4

AJ25

12

12

12

12

JCPU1 H

JCPU1 H

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

Sandy Bri dge_r PGA_Rev1p 0

Sandy Bri dge_r PGA_Rev1p 0

CONN @

CONN @

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

1

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

Size Do cum ent Num ber Rev

Size Do cum ent Num ber Rev

Size Do cum ent Num ber Rev

LA-6801P

LA-6801P

LA-6801P

Date: Sheet

Date: Sheet

2

Date: Sheet

1

10 61Tues day, Janua ry 25, 201 1

10 61Tues day, Janua ry 25, 201 1

10 61Tues day, Janua ry 25, 201 1

1.0

1.0

1.0

of

of

of

5

+1.5V

CD6

CD6

1

2

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

CD11

CD11

1

2

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1

CD20

CD20

2

<BOM Structure>

<BOM Structure>

12

RD1

RD1
1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFA

12

RD3

RD3
1K_0402_1%~D

1K_0402_1%~D

All VREF traces should
have 10 mil trace width

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

@

@

1

CD12

CD12

CD13

CD13

CD14

1

2

CD14

1

+

+

2

2

DDR_A_DQS#[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_MA[0..15]<7>

D D

Layout Note:
Place near JDIMM1

+1.5V

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

CD3

CD3

1

2

+1.5V

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

C C

CD7

CD7

1

2

Layout Note:
Place near JDIMM1.203,204

+0.75VS

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1

CD17

CD17

2

B B

CD5

CD5

CD4

CD4

1

1

2

2

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

CD10

CD8

CD8

1

2

1

2

CD10

CD9

CD9

1

1

2

2

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1

CD19

CD19

CD18

CD18

2

+V_DDR_REFA

4

RD2 0_0402_5%~DRD2 0_0402_5%~D

1 2

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

1

1

CD1

CD1

2

2

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

+3VS

CD21

CD21

1

1

2

2

+DIMM0_VREF

DDR_A_D0
DDR_A_D1

CD2

CD2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

RD6 10K_0402_5%~DRD6 10K_0402_5%~D

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

RD7 10K_0402_5%~DRD7 10K_0402_5%~D

CD22

CD22

1 2

1 2

+0.75VS

+1.5V

JDIMM1

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A626-U2SN-7F

FOX_AS0A626-U2SN-7F

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

3

+1.5V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD
A15
A14
VDD
A11

VDD

VDD

VDD
CK1

VDD
BA1

VDD
S0#

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

DDR3_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6

DDR_A_MA4

92

A4

94

DDR_A_MA2

96

A2

DDR_A_MA0

98

A0

100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS0_DIMMA#

114

M_ODT0

116
118

M_ODT1

120
122

NC

124
126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PCH_SMBDATA

200

PCH_SMBCLK

202
204

+0.75VS

206
208

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

+VREF_CA

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

1

CD15

CD15

2

PCH_SMBDATA <6,12,14,28,32>
PCH_SMBCLK <6,12,14,28,32>

DDR3_DRAMRST# <7,12>

+1.5V

1

CD16

CD16

2

12

RD4

RD4
1K_0402_1%~D

1K_0402_1%~D

12

RD5

RD5
1K_0402_1%~D

1K_0402_1%~D

2

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL
AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

5

4

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

LA-6801P

LA-6801P

LA-6801P

1

1.0

1.0

11 61Tuesday, January 25, 2011

11 61Tuesday, January 25, 2011

11 61Tuesday, January 25, 2011

1.0

of

of

of

5

+1.5V

12

RD15

RD15
1K_0402_1%~D

1K_0402_1%~D

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

D D

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

Layout Note:
Place near JDIMMB

+1.5V

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

CD29

CD29

CD28

CD28

1

1

2

C C

B B

2

+1.5V

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

CD33

CD33

CD34

CD34

CD32

CD32

1

1

1

2

2

2

Layout Note:
Place near JDIMMB.203,204

+0.75VS

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1

1

CD43

CD43

CD42

CD42

2

2

CD31

CD31

CD30

CD30

1

1

2

2

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

10U_0603 _6.3V6M~D

@

@

330U_SX_2VY~D

330U_SX_2VY~D

@

@

CD35

CD35

CD36

CD36

1

1

2

2

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1U_0402_ 6.3V6K~D

1

1

CD44

CD44

2

2

1

CD37

CD37

CD38

CD38

CD39

1

2

CD45

CD45

CD39

1

+

+

2

2

12

RD16

RD16
1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFB

4

+V_DDR_REFB

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

RD14 0_0402_5%~DRD14 0_0402_5%~D

1 2

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

1

CD27

CD27

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

12

RD19

RD19

10K_0402_5%~D

10K_0402_5%~D

3

+1.5V

JDIMM2

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

+DIMM1_VREF

DDR_B_D0
DDR_B_D1

1

CD26

CD26

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

12

10K_0402 _5%~D

10K_0402 _5%~D

RD20

RD20

+0.75VS

CD46

CD46

1

1

2

2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2

77

NC1

79

BA2
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

CD47

CD47

G1

LCN_DAN06-K4926-0100

LCN_DAN06-K4926-0100

CONN@

CONN@

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQS3

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+1.5V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

DDR3_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE3_DIMMB

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

DDR_B_MA4

92

A4

94

DDR_B_MA2

96

A2

DDR_B_MA0

98

A0

100

M_CLK_DDR3

102

M_CLK_DDR#3

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDR_CS2_DIMMB#

114

M_ODT2

116
118

M_ODT3

120
122
124
126
128

DDR_B_D36

130

DDR_B_D37

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198

PCH_SMBDATA

200

PCH_SMBCLK

202
204

+0.75VS

206

G2

2

DDR3_DRAMRST# <7,11>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

2.2U_060 3_6.3V6K~D

2.2U_060 3_6.3V6K~D

0.1U_040 2_16V7K~D

0.1U_040 2_16V7K~D

1

1

CD40

CD40

2

2

PCH_SMBDATA <6,11,14,28,32>
PCH_SMBCLK <6,11,14,28,32>

RD17

RD17
1K_0402_1%~D

1K_0402_1%~D

CD41

CD41

+1.5V

12

12

RD18

RD18
1K_0402_1%~D

1K_0402_1%~D

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL
AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

5

4

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

LA-6801P

LA-6801P

LA-6801P

1

1.0

1.0

12 61Tuesday, January 25, 2011

12 61Tuesday, January 25, 2011

12 61Tuesday, January 25, 2011

1.0

of

of

of

5

PCH_RTCX1

32.768KHZ_ 12.5PF_Q13MC146 10002

32.768KHZ_ 12.5PF_Q13MC146 10002

1

CH3

CH3

OSC4OSC

18P_0402 _50V8J~D

18P_0402 _50V8J~D

2

NC3NC

1 2

RH27 33_0402 _5%

RH27 33_0402 _5%

1 2

RH28 33_0402 _5%

RH28 33_0402 _5%

1 2

RH33 33_0402 _5%

RH33 33_0402 _5%

1 2

RH275 1M_040 2_5%~DRH275 1M_04 02_5%~D

HDA_SDO<31>

12

RH39

@RH39

@

200_040 2_5%

200_040 2_5%

12

RH45

RH45
100_040 2_1%~D

100_040 2_1%~D

RH53 5 1_0402_5 %

RH53 5 1_0402_5 %

PCH_SPI_WP#

PCH_SPI_HOLD#

@

@

12

1 2

CH98

CH98

@

@

10P_0402 _50V8J~D

10P_0402 _50V8J~D

PCH_RTCX2

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1 2

RH24 0 _0402_5%~D

RH24 0 _0402_5%~D

1 2

RH30 33_0 402_5%

RH30 33_0 402_5%

12

RH40

@RH40

@

200_040 2_5%

200_040 2_5%

12

RH46

RH46

100_040 2_1%~D

100_040 2_1%~D

+3V_PCH

12

@

@

RH267

RH267
10K_0402 _5%~D

10K_0402 _5%~D

DP_PCH_HPD

RH268

RH268
100K_040 2_5%~D

100K_040 2_5%~D

@

@

1 2

1 2

@

@

RH256

RH256

PCH_SPI_CLK_R

33_0402 _5%

33_0402 _5%

PCH_SPI_CLK

12

+RTCVCC

1U_0603_1 0V4Z

1U_0603_1 0V4Z

1 2

RH25 20K_040 2_5%~DRH25 20K_04 02_5%~D

1 2

RH23 20K_040 2_5%~DRH23 20K_04 02_5%~D

1U_0603_1 0V4Z

1U_0603_1 0V4Z

QH1 BSS138_SOT23

QH1 BSS138_SOT23

RH36 0_0402_ 5%~D

RH36 0_0402_ 5%~D

@

@

1M_0402_ 5%~D

1M_0402_ 5%~D

CMOS

CLRP1

CLRP1

CLRP2

CLRP2

ME CMOS

HDA_SPKR<24>

HDA_SYNC

HDA_SDIN0<24>

DP_PCH_HPD<38>

PCH_JTAG_TCK<6 >

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

SM_INTRUDER#

RH255 0_0 402_5%~DRH255 0_04 02_5%~D

RH11

RH11

CH4

CH4

CH5

CH5

+5VS

G

G

2

S

S

@

@

1 2

HDA_SDOUT

HDA_SDOUT

1 2

1

12

SHORT PADS

SHORT PADS

2

1

12

SHORT PADS

SHORT PADS

2

CLP1 & CLP2 place near DIMM

13

D

D

PCH_SPI_CLK_R

close to UH1

+3V_PCH

@ RH57

@

1 2

RH58 0_0402 _5%~DRH58 0_0402 _5%~D

PCH_SPI_SO PCH_SPI_SO_R

1 2

RH60 33_040 2_5%RH60 33_040 2_5%

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

12

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

RH57

3.3K_040 2_5%

3.3K_040 2_5%

1 2

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

DP_PCH_HPD

1 2

RH2 10 M_0402_5%RH2 10M_0402_ 5%

18P_0402 _50V8J~D

18P_0402 _50V8J~D

1

1

CH2

CH2

2

YH1

YH1

D D

C C

B B

A A

2

far away hot spot

HDA_BITCLK_AUDIO<24>

HDA_RST_AUDIO#<24>

HDA_SYNC_AUDIO<24>

HDA_SDOUT_AUDIO<24>

+3V_PCH +3V_PCH+3V_PCH

12

RH38

@RH38

@

200_040 2_5%

200_040 2_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH44

RH44

100_040 2_1%~D

100_040 2_1%~D

PCH_JTAG_TCK

+3V_PCH

1 2

RH54 3.3K_ 0402_5%R H54 3.3K_04 02_5%

1 2

RH56 3.3K_ 0402_5%R H56 3.3K_04 02_5%

CH94

CH94

22P_0402 _50V8J~D

22P_0402 _50V8J~D

Reserve for EMI please close to U48

Reserve for RF please close to UH1

5

4

@

@

HDA_SDOUT

12

CH103 10P_04 02_50V8J~D

CH103 10P_04 02_50V8J~D

@

@

HDA_BIT_CLK

12

CH97 10P_0 402_50V8J~D

CH97 10P_0 402_50V8J~D

Reserve for RF please close to UH1

R3@

R3@

UH1A

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CougarPo int_Rev_1p0

CougarPo int_Rev_1p0

SA00004ED3L

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

LPC

LDRQ1# / GPIO23

SATA LPC

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI ROM FOR ME ( 4MByte )

SPI ROM FOR ME
( 4MByte )

U48

U48

1

2

3

W25Q32BVSSIG_SO8

W25Q32BVSSIG_SO8

SPI BIOS Pinout

(1)CS# (5)DIO
(2)DO (6)CLK
(3)WP# (7)HOLD#
(4)GND (8)VCC

W25X32

4

/CS

DO

/WP

GND4DIO

/HOLD

8

VCC

PCH_SPI_HOLD#

7

PCH_SPI_CLK_R

6

CLK

5

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA 6G

SATA1RXP

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

RH63 33_0402_ 5%RH63 33_0402_5 %

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

1 2

UH1

BD82HM67 SLH9C B2

BD82HM67 SLH9C B2

SA00004ED2L

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

PCH_SPI_SIPCH_SPI_SI_R

3

R1@UH1

R1@

LPC_AD0 <31>
LPC_AD1 <31>
LPC_AD2 <31>
LPC_AD3 <31>

LPC_FRAME# <31 >

SERIRQ <31>

CH91 0 .01U_0402_1 6V7K~DCH91 0.01U_0402 _16V7K~D

1 2

CH90 0 .01U_0402_1 6V7K~DCH90 0.01U_0402 _16V7K~D

1 2

CH92 0 .01U_0402_1 6V7K~DCH92 0.01U_0402 _16V7K~D

1 2

CH93 0 .01U_0402_1 6V7K~DCH93 0.01U_0402 _16V7K~D

1 2

PCH_SATALED# <35 >

10K_0402 _5%~D

10K_0402 _5%~D

12

CH6

CH6

0.1U_0402_ 16V7K~D

0.1U_0402_ 16V7K~D

3

+1.05VS_VCC_SAT A

+1.05VS_SATA3

Security Classification

Security Classification

Security Classification

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL

THIS SHE ET OF ENGINE ERING DR AWING IS THE PR OPRIETARY PR OPERTY OF COMPAL EL ECTRON ICS, INC. AND CONTAINS C ONFIDEN TIAL
AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D

AND TRADE S ECRET IN FORMATION. THIS SH EET MAY NOT BE TRANSFE RED FROM TH E CUSTOD Y OF THE COMPETE NT DIVISION OF R& D
DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS

DEPARTMEN T EXCEPT AS AUTHOR IZED BY COMPAL EL ECTRON ICS, INC. N EITHER TH IS SHEET N OR THE INFO RMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

MAY BE USED BY OR D ISCLOSE D TO ANY THIRD PAR TY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELEC TRONICS , INC.

1 2

RH41 37.4_0 402_1%RH41 37.4_0 402_1%

1 2

RH43 49.9_0 402_1%RH43 49.9_0 402_1%

1 2

RH48 750_0 402_1%~D

RH48 750_0 402_1%~D

RH276

RH276

+3V_PCH

1

2

+3VS

Issued Date

Issued Date

Issued Date

2

SATA_PRX_DTX_N1 <28>
SATA_PRX_DTX_P1 <28>
SATA_PTX_DRX_N1_C <28>
SATA_PTX_DRX_P1_C <28>

SATA_PRX_DTX_N2 <28>
SATA_PRX_DTX_P2 <28>
SATA_PTX_DRX_N2_RP <28>
SATA_PTX_DRX_P2_RP <28>

HDD1

ODD

PCH_INTVRMEN

INTVRMEN

HIntegrated VRM enable

*

L



HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

RTC Battery

+RTCBATT

+CHGRTC

W=20mils

W=20mils

0_0603_ 5%~D

+CHGRTC

0_0603_ 5%~D

2011/01/25 2 012/01/25

2011/01/25 2 012/01/25

2011/01/25 2 012/01/25

3

1

1

CH95

CH95
1U_0603_1 0V4Z

1U_0603_1 0V4Z

2

RH260

RH260

12

Compal Secret Data

Compal Secret Data

Compal Secret Data

RH259

RH259
1K_0402_ 5%~D

1K_0402_ 5%~D

1 2

W=20mils

2

DH4

DH4
BAT54CW_SOT 323-3

BAT54CW_SOT 323-3

RH261

RH261

0_0603_ 5%~D

0_0603_ 5%~D

12

Deciphered Date

Deciphered Date

Deciphered Date

2

RH31 3 30K_0402_5 %RH31 3 30K_0402_5 %

RH34 3 30K_0402_5 %@RH34 33 0K_0402_5%@

Integrated VRM disable

+RTCVCC

+3VLP

1

+3VS

SERIRQ

+RTCVCC

12

12

HDA_SYNC

This signal has a weak internal pull-down
On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

HDA_SYNC

Title

Title

Title

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

Size Docu ment Number Rev

Size Docu ment Number Rev

Size Docu ment Number Rev

LA-6801P

LA-6801P

LA-6801P

Date: Sheet

Date: Sheet

Date: Sheet

RH29 1 0K_0402_5%~DRH29 10K_0402_5%~D

PCH_GPIO21

RH32 1 0K_0402_5%~DRH32 10K_0402_5%~D

PCH_SATALED#PCH_INTVRMEN

RH35 1 0K_0402_5%~DRH35 10K_0402_5%~D

HDA_SPKR

RH37 1 K_0402_5%~D@RH37 1K_0402_5%~D@

HDA_SDOUT

RH42 1 K_0402_5%~D@RH42 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

RH52 1 K_0402_5%~D RH52 1K_0402_5%~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

12

1

LOW=Default
HIGH=No Reboot

*

12

+3V_PCH

13 61Tuesday , January 25, 2011

13 61Tuesday , January 25, 2011

13 61Tuesday , January 25, 2011

12

12

12

+3VS

12

+3V_PCH

1.0

1.0

1.0

of

of

of

5

PCIE_PRX_GLANTX_N3<22>

@

@

CH21

CH21

1 2

PCIE_PRX_GLANTX_P3<22>
PCIE_PTX_GLANRX_N3<22>
PCIE_PTX_GLANRX_P3<2 2>

PCIE_PRX_WANTX_N2<32>
PCIE_PRX_WANTX_P2<32>
PCIE_PTX_WANRX_N2<32>
PCIE_PTX_WANRX_P2<32 >

PCIE_PRX_WLANTX_N1<32>
PCIE_PRX_WLANTX_P1<32>
PCIE_PTX_WLANRX_N1<32>
PCIE_PTX_WLANRX_P1<32>

PCIE_PRX_CARDTX_N4<23>
PCIE_PRX_CARDTX_P4<23>
PCIE_PTX_CARDRX_N4<23>
PCIE_PTX_CARDRX_P4<23>

PCIE_PRX_USB3TX_N6<27 >
PCIE_PRX_USB3TX_P6<27>
PCIE_PTX_USB3RX_N6<27>
PCIE_PTX_USB3RX_P6<27>

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

USB 3.0 --->

@

@

RH86

CLK_PCH_14 M

RH86

33_040 2_5%

33_040 2_5%

12

22P_040 2_50V8J~D

22P_040 2_50V8J~D

CH9 0.1U_0402 _10V7K~DCH9 0.1U_0402 _10V7K~D

1 2

CH14 0.1U_0402_ 10V7K~DCH14 0.1U_0402_ 10V7K~D

1 2

CH10 0.1U_0402_ 10V7K~DCH10 0.1U_0402_ 10V7K~D

1 2

CH15 0.1U_0402_ 10V7K~DCH15 0.1U_0402_ 10V7K~D

1 2

CH11 0.1U_0402_ 10V7K~DCH11 0.1U_0402_ 10V7K~D

1 2

CH16 0.1U_0402_ 10V7K~DCH16 0.1U_0402_ 10V7K~D

1 2

CH12 0.1U_0402_ 10V7K~DCH12 0.1U_0402_ 10V7K~D

1 2

CH13 0.1U_0402_ 10V7K~DCH13 0.1U_0402_ 10V7K~D

1 2

CH19 0.1U_0402_ 10V7K~DCH19 0.1U_0402_ 10V7K~D

1 2

CH20 0.1U_0402_ 10V7K~DCH20 0.1U_0402_ 10V7K~D

1 2

Reserve for EMI please close t o UH1

C C

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH1

B B

25MHZ_18PF_1Y7 25000CE1A~D

25MHZ_18PF_1Y7 25000CE1A~D

1

CH23

CH23

2

A A

@

@

@

RH89

RH89

33_040 2_5%

33_040 2_5%

@

CH22

CH22

12

1 2

22P_040 2_50V8J~D

22P_040 2_50V8J~D

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

Card Reader --->

USB 3.0 --->

12

RH1171M_040 2_5%~D RH11 71M_04 02_5%~D

YH2

YH2

1 2

22P_040 2_50V8J~D

22P_040 2_50V8J~D

22P_040 2_50V8J~D

CH24

CH24

22P_040 2_50V8J~D

1

2

XTAL25_IN

XTAL25_OUT

RH91 10K_04 02_5%~DRH9 1 10K_0402_5 %~D

+3V_PCH

CLK_PCIE_LAN#<22>
CLK_PCIE_LAN<22>

LANCLK_REQ#<22 >

CLK_PCIE_MINI2#<32>
CLK_PCIE_MINI2<3 2>

MINI2CLK_REQ#<32>

CLK_PCIE_MINI1#<32>
CLK_PCIE_MINI1<3 2>

MINI1CLK_REQ#<32>

CLK_PCIE_CD#<23>
CLK_PCIE_CD<23 >

CDCLK_REQ#<23>

CLK_PCIE_USB30 #<27>
CLK_PCIE_USB30<27 >

USB30_CLKREQ#<27>

CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>

CLK_RES_ITP#<8>
CLK_RES_ITP<8 >

CLK_CPU_ITP#
CLK_CPU_ITP

RH93 0_040 2_5%~DRH93 0_04 02_5%~D
RH94 0_040 2_5%~DRH94 0_04 02_5%~D

RH95 10K_0402_5%~D@RH9 5 10K_0 402_5%~D@

+3VS

RH96 0_040 2_5%~DRH96 0_04 02_5%~D
RH97 0_040 2_5%~DRH97 0_04 02_5%~D
RH100 10 K_0402_5%~DRH100 10 K_0402_5%~D

+3VS

RH101 0_ 0402_5%~DRH101 0_0402_5%~D
RH102 0_ 0402_5%~DRH102 0_0402_5%~D
RH103 10 K_0402_5%~DRH103 10 K_0402_5%~D

+3V_PCH

RH104 0_ 0402_5%~DRH104 0 _0402_5%~D
RH106 0_0402_5%~DRH106 0_0402_5%~D
RH107 10K_0402_5%~DRH107 10K_0402_5%~D

+3V_PCH

RH110 10 K_0402_5%~DRH110 10 K_0402_5%~D

+3V_PCH

RH112 10 K_0402_5%~DRH112 10 K_0402_5%~D

+3V_PCH

RH114 0_ 0402_5%~DRH114 0_0402_5%~D
RH115 0_ 0402_5%~DRH115 0_0402_5%~D
RH116 10 K_0402_5%~DRH116 10 K_0402_5%~D

+3V_PCH

RH118 10 K_0402_5%~DRH118 10 K_0402_5%~D

+3V_PCH

RH119 0_ 0402_5%~DRH119 0 _0402_5%~D
RH120 0_ 0402_5%~DRH120 0 _0402_5%~D

RH121 0_ 0402_5%~D@RH1 21 0_0402 _5%~D@
RH122 0_0402_5%~D@RH1 22 0_0402 _5%~D@

1 2

1 2
1 2

1 2

1 2

1 2

1 2

12

12
12
12

12
12
12

12
12
12

12
12

12
12

12
12

4

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3 _C
PCIE_PTX_GLANRX_P3 _C

PCIE_PRX_WANTX_N2
PCIE_PRX_WANTX_P2
PCIE_PTX_WANRX_N2_ C
PCIE_PTX_WANRX_P2_C

PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1
PCIE_PTX_WLANRX_N1 _C
PCIE_PTX_WLANRX_P1_ C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
PCIE_PTX_CARDRX_N4_ C
PCIE_PTX_CARDRX_P4_ C

PCIE_PRX_USB3TX_N6
PCIE_PRX_USB3TX_P6
PCIE_PTX_USB3RX_N6_ C
PCIE_PTX_USB3RX_P6_ C

T81PAD~D @T81PAD~D @
T82PAD~D @T82PAD~D @

PCIECLKREQ0#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD#
PCIE_CD

CDCLK_REQ#

PEG_B_CLKREQ#

PCIE_USB30#
PCIE_USB30

USB30_CLKREQ#

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

CLK_BCLK_ITP

UH1B

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPo int_Rev_1p0

CougarPo int_Rev_1p0

R3@

R3@

PCI-E*

PCI-E*

CLOCKS

CLOCKS

3

SMBALERT# / GPIO11

SMBDATA

SML0ALERT# / GPIO60

SMBUSControll er

SMBUSControll er

SML1ALERT# / PCHHOT# / GPIO74

Link

Link

FLEX CLOCKS

FLEX CLOCKS

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

SMBCLK

PCH_LID_SW_ IN#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

CLK_CPU_DPLL #

AM12

CLK_CPU_DPLL

AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96 #

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14 M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

KB_DET#

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

CAM_DET#

DMC_PCH_DET#

BT_DET#

KB_DET#

MEMORY

Total device

+3V_PCH

1 2

RH113 90.9 _0402_1%RH113 9 0.9_0402_ 1%

1 2

RH166 10K_ 0402_5%~DRH 166 10K_0402 _5%~D

1 2

RH109 10K_ 0402_5%~DRH 109 10K_0402 _5%~D

1 2

RH108 10K_ 0402_5%~DRH 108 10K_0402 _5%~D

12

R1791 100K_04 02_5%~DR1791 100K_04 02_5%~D

2

EC_LID_OUT#

1 2

RH680_0402_5 %~D R H680_ 0402_5%~D

@

1 2

RH710_0402_5 %~D@RH710_0402_5 %~D

DRAMRST_CNTRL_PCH <7>

20090512
add double mosfet prevent
ATI M92 electric leakage

RH141

RH141
10K_040 2_5%~D

10K_040 2_5%~D

1 2

CLK_PEG_VGA# <4 0>
CLK_PEG_VGA <40>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

CLK_CPU_DPLL # <6>
CLK_CPU_DPLL <6>

CLK_PCI_LPBACK <16>

KB_DET# <29>

DMC_PCH_DET# <37>

BT_DET# <3 2>

CAM_DET# <21>

PEG_A_CLKRQ# <40>

SMBCLK

SMBDATA

+1.05VS_VCCDI FFCLKN

+3VS

EC_LID_OUT# <3 1>

LID_SW_IN# <31,34,35>

6 1

DMN66D0LDW- 7_SOT363-6~D

DMN66D0LDW- 7_SOT363-6~D

SML1CLK

SML1DATA

QH3A

QH3A

RH105

RH105

@

@

1 2

0_0402 _5%~D

0_0402 _5%~D

DMN66D0LDW- 7_SOT363-6~D

DMN66D0LDW- 7_SOT363-6~D

6 1

DMN66D0LDW- 7_SOT363-6~D

DMN66D0LDW- 7_SOT363-6~D

DMN66D0LDW- 7_SOT363-6~D

DMN66D0LDW- 7_SOT363-6~D

2

QH4A

QH4A

3

+3VS

2

+3VS

5

QH3B

QH3B

RH111

RH111

@

@

1 2

0_0402 _5%~D

0_0402 _5%~D

3

QH4B

QH4B

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

LID_SW_IN#

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96 #
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14 M

If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH

+3VS

RH98

RH98

2.2K_040 2_5%~D

2.2K_040 2_5%~D

1 2

4

5

4

RH76 10K_040 2_5%~DRH76 10K_040 2_5%~D
RH78 10K_040 2_5%~DRH78 10K_040 2_5%~D
RH77 10K_040 2_5%~DRH77 10K_040 2_5%~D
RH79 10K_040 2_5%~DRH79 10K_040 2_5%~D
RH80 10K_040 2_5%~DRH80 10K_040 2_5%~D
RH81 10K_040 2_5%~DRH81 10K_040 2_5%~D
RH82 10K_040 2_5%~DRH82 10K_040 2_5%~D
RH83 10K_040 2_5%~DRH83 10K_040 2_5%~D
RH84 10K_040 2_5%~DRH84 10K_040 2_5%~D

RH99

RH99

2.2K_040 2_5%~D

2.2K_040 2_5%~D

1 2

PCH_SMLCLK <31,51>

PCH_SMLDATA <31,51>

1

1 2

RH67 2.2K_0402 _5%~DRH67 2. 2K_0402_5%~D

1 2

RH69 2.2K_0402 _5%~DRH69 2. 2K_0402_5%~D

1 2

RH70 2.2K_0402 _5%~D

RH70 2.2K_0402 _5%~D

1 2

RH72 2.2K_0402 _5%~D

RH72 2.2K_0402 _5%~D

1 2

RH73 2.2K_0402 _5%~DRH73 2. 2K_0402_5%~D

1 2

RH74 2.2K_0402 _5%~DRH74 2. 2K_0402_5%~D

1 2

R1790 10K_040 2_5%~D

R1790 10K_040 2_5%~D

@

@

1 2

RH75 1K_0402_5 %~D

RH75 1K_0402_5 %~D

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCH_SMBCLK <6,11, 12,28,32>

PCH_SMBDATA <6,11, 12,28,32>

+3V_PCH

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

LA-6801P

LA-6801P

LA-6801P

1

14 61Tuesday, Ja nuary 25, 2011

14 61Tuesday, Ja nuary 25, 2011

14 61Tuesday, Ja nuary 25, 2011

1.0

1.0

1.0

of

of

of

5

Compal Electronics, Inc.

UH1C

UH1C

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>

D D

C C

PM_DRAM_PWRGD<6>

SUSWARN# SUSACK#_R

B B

GPIO72

RI#

WAKE#

AC_PRESENT

SUSWARN#

PCH_RSMRST#

SYS_PWROK

A A

DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

SUSACK#<31>

XDP_DBRESET#<6>

PCH_APWROK<31>

PCH_RSMRST#<31>

SUSWARN#<31>

PBTN_OUT#<6,31>

AC_PRESENT<31>

1 2

RH139 0_0402_5%~DRH139 0_0402_5%~D

RH143 10K_0402_5%~DRH143 10K_0402_5%~D

1 2

RH145 10K_0402_5%~DRH145 10K_0402_5%~D

1 2

RH146 10K_0402_5%~DRH146 10K_0402_5%~D

1 2

RH150 10K_0402_5%~D@RH150 10K_0402_5%~D@

1 2

RH154 10K_0402_5%~DRH154 10K_0402_5%~D

1 2

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

1 2

RH272 10K_0402_5%~DRH272 10K_0402_5%~D

1 2

PCH_PWROK<6,31>

VGATE< 6,31,57>

RH124 49.9_0402_1%RH124 49.9_0402_1%

RH125 750_0402_1%~DRH125 750_0402_1%~D

4mil width and place
within 500mil of the PCH

PCH_PWROK

PCH_PWROK

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

XDP_DBRESET#

@

@

1 2

1 2

1 2

PM_DRAM_PWRGD

1 2

1 2

1 2

1 2

+3V_PCH

1

CH96

CH96

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2

1

IN1

2

IN2

DMI_IRCOMP

RBIAS_CPY

PCH_RSMRST#_R

GPIO72

+3VS

1 2

1 2

RH127 0_0402_5%~DRH127 0_0402_5%~D

RH273 0_0402_5%~D

RH273 0_0402_5%~D

RH130 0_0402_5%~DRH130 0_0402_5%~D

RH131 0_0402_5%~DRH131 0_0402_5%~D

RH133 0_0402_5%~DRH133 0_0402_5%~D

RH134 0_0402_5%~DRH134 0_0402_5%~D

RH135 0_0402_5%~DRH135 0_0402_5%~D

RH137 0_0402_5%~DRH137 0_0402_5%~D

BC24

BE20
BG18
BG20

BE24
BC20

BJ18
BJ20

AW24
AW20

BB18

AV18

AY24

AY20

AY18

AU18

BJ24

BG25

BH21

SUSACK#_R

SYS_PWROK

PM_PWROK_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

RI#

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

5

UH7

UH7

VCC

SYS_PWROK

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

3

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

CougarPoint_Rev_1p0

CougarPoint_Rev_1p0

R3@

R3@

DSWODVREN

DSWODVREN

RH147 330K_0402_5%RH147 330K_0402_5%

RH151 330K_0402_5%@RH151 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable

HEnable

*



Disable

L

DMI

DMI

System Power Management

System Power Management

SYS_PWROK <6>

4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

12

+RTCVCC

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

RH126 0_0402_5%~D

RH126 0_0402_5%~D

PCH_DPWROK

WAKE#

1 2

1 2

RH128 0_0402_5%~DRH128 0_0402_5%~D

PM_CLKRUN#

SUS_STAT#

SUSCLK

RH132 0_0402_5%~DRH132 0_0402_5%~D

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

If not using integrated
LAN,signal may be left as NC.

@

@

12

3

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 < 5>

FDI_LSYNC1 < 5>

PCH_RSMRST#_R

PCH_DPWROK <31>

PCIE_WAKE# <22,31,32>

T76 PAD~DT76 PAD~D

SUSCLK_R <31>

PM_SLP_S5# <31,34>

PM_SLP_S4# <31>

PM_SLP_S3# <31,34>

PM_SLP_SUS# <31>

H_PM_SYNC <6>

Can be left NC when IAMT is
not support on the platfrom

SUSCLK

Reserve for RF please close to UH1

CRT_B<21>
CRT_G<21>
CRT_R< 21>

CRT_DDC_CLK<21>
CRT_DDC_DATA<21>

CRT_HSYNC<21>
CRT_VSYNC<21>

CH102

CH102

12

@

@

10P_0402_50V8J~D

10P_0402_50V8J~D

+3VS

RH148 2.2K_0402_5%~D

RH148 2.2K_0402_5%~D

RH152 2.2K_0402_5%~D

RH152 2.2K_0402_5%~D

RH155 2.2K_0402_5%~DRH155 2.2K_0402_5%~D

RH157 2.2K_0402_5%~DRH157 2.2K_0402_5%~D

RH248 8.2K_0402_5%~D@RH248 8.2K_0402_5%~D@

+3VS

RV169 2.2K_0402_5%~DRV169 2.2K_0402_5%~D
RV170 2.2K_0402_5%~DRV170 2.2K_0402_5%~D

VGA_LVDDEN<21,31>

VGA_PWM<21>

LVDS_DDC_CLK<21>

LVDS_DDC_DATA<21>

LVDS_ACLK-<21>
LVDS_ACLK+<21>

LVDS_A0-<21>
LVDS_A1-<21>
LVDS_A2-<21>

LVDS_A0+<21>
LVDS_A1+<21>
LVDS_A2+<21>

LVDS_BCLK-<21>
LVDS_BCLK+<21>

LVDS_B0-<21>
LVDS_B1-<21>
LVDS_B2-<21>

LVDS_B0+<21>
LVDS_B1+<21>
LVDS_B2+<21>

@

@

1 2

@

@

1 2

1 2

1 2

1 2

1 2
1 2

ENBKL<31>

T203PAD~D T203PAD~D

RH136 33_0402_5%RH136 33_0402_5%

RH138 33_0402_5%RH138 33_0402_5%

1K_0402_0.5%~D

1K_0402_0.5%~D

ENBKL

LVDS_DDC_CLK
LVDS_DDC_DATA

LVDS_ACLK­LVDS_ACLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_BCLK­LVDS_BCLK+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

CRT_B
CRT_G
CRT_R

CRT_DDC_CLK
CRT_DDC_DATA

1 2
1 2

RH140

RH140

CRT_DDC_CLK

CRT_DDC_DATA

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

CTRL_CLK
CTRL_DATA

LVDS_IBG

HSYNC
VSYNC

CRT_IREF

12

LVDS_DDC_CLK
LVDS_DDC_DATA

J47

M45

P45

T40
K47

T45
P39

AF37
AF36

AE48
AE47

AK39
AK40

AN48

AM47

AK47
AJ48

AN47

AM49

AK49
AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

N48
P49
T49

T39
M40

M47
M49

T43
T42

CougarPoint_Rev_1p0

CougarPoint_Rev_1p0

R3@

R3@

2

UH1D

UH1D

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_C LK
L_DDC_D ATA

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CL K#
LVDSA_CL K

LVDSA_DA TA#0
LVDSA_DA TA#1
LVDSA_DA TA#2
LVDSA_DA TA#3

LVDSA_DA TA0
LVDSA_DA TA1
LVDSA_DA TA2
LVDSA_DA TA3

LVDSB_CL K#
LVDSB_CL K

LVDSB_DA TA#0
LVDSB_DA TA#1
LVDSB_DA TA#2
LVDSB_DA TA#3

LVDSB_DA TA0
LVDSB_DA TA1
LVDSB_DA TA2
LVDSB_DA TA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

1

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

LVDS

DDPC_C TRLCLK

DDPC_C TRLDATA

mDP

Digital Display Interface

Digital Display Interface

DDPD_C TRLCLK

DDPD_C TRLDATA

CRT

CRT

DMC

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46
P42

AP47

DDPC_AUXN

AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

RH167 10K_0402_5%~DRH167 10K_0402_5%~D

RH144 2.37K_0402_1%~DRH144 2.37K_0402_1%~D

RH149 150_0402_1%~DRH149 150_0402_1%~D

RH153 150_0402_1%~DRH153 150_0402_1%~D

RH156 150_0402_1%~DRH156 150_0402_1%~D

RH158 100K_0402_5%~DRH158 100K_0402_5%~D

RH123 100K_0402_5%~DRH123 100K_0402_5%~D

1 2

1 2

1 2

1 2

1 2

1 2

1 2

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PCH_DPD_CLK
PCH_DPD_DAT

PCH_DMC_HPD

PCH_DPD_N0
PCH_DPD_P0
PCH_DPD_N1
PCH_DPD_P1
PCH_DPD_N2
PCH_DPD_P2
PCH_DPD_N3
PCH_DPD_P3

PM_CLKRUN#

LVDS_IBG

CRT_B

CRT_G

CRT_R

VGA_LVDDEN

ENBKL

PCH_DPD_CLK <37>
PCH_DPD_DAT <37>

PCH_DMC_HPD <37>

PCH_DPD_N0 <37>
PCH_DPD_P0 <37>
PCH_DPD_N1 <37>
PCH_DPD_P1 <37>
PCH_DPD_N2 <37>
PCH_DPD_P2 <37>
PCH_DPD_N3 <37>
PCH_DPD_P3 <37>

DMC
( HDMI )

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

201 1/01/25 2012/0 1/25

201 1/01/25 2012/0 1/25

201 1/01/25 2012/0 1/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-6801P

LA-6801P

LA-6801P

1

15 61Tuesday, January 25, 2011

15 61Tuesday, January 25, 2011

15 61Tuesday, January 25, 2011

of

of

of

1.0

1.0

1.0

5

D D

+3V_PCH

C C

B B

A A

12

@

@

RH269

RH269
10K_040 2_5%~D

10K_040 2_5%~D

CARD_HPLUG

RH264

RH264
100K_04 02_5%~D

100K_04 02_5%~D

@

@

1 2

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_ RST#

T123PAD~D @T123PAD~D @

12

T165PAD~D @T165PAD~D @
T166PAD~D @T166PAD~D @
T204PAD~D @T204PAD~D @

+3VS

DGPU_SELECT#
DGPU_PWR_EN

DMC_RADIO_OFF#

WL_OFF#

FFS_INT1
ODD_DA#
DP_CBL_DET
CARD_HPLUG

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

DGPU_SELECT#<37>

DGPU_PWR_EN<33 ,43,55,56>

DMC_RADIO_OFF#<3 2>

WL_OFF#<32>

FFS_INT1<28>

ODD_DA#<28>

DP_CBL_DET<38>

CARD_HPLUG<23 >

CLK_PCI_LPBACK<14>

CLK_PCI_LPC<31>

CLK_PCI_LPBACK
CLK_PCI_LPC

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#

DMC_RADIO_OFF#
DGPU_SELECT#
DGPU_PWR_EN
FFS_INT1

PCI_PIRQA#

ODD_DA#

DGPU_HOLD_ RST#

RH164 22 _0402_5%RH164 2 2_0402_5%
RH165 22 _0402_5%

RH165 22 _0402_5%

1 2

RPH3

RPH3

1 8
2 7
3 6
4 5

8.2K_080 4_8P4R_5%

8.2K_080 4_8P4R_5%

RPH4

RPH4

1 8
2 7
3 6
4 5

8.2K_080 4_8P4R_5%

8.2K_080 4_8P4R_5%

RPH5

RPH5

1 8
2 7
3 6
4 5

8.2K_080 4_8P4R_5%

8.2K_080 4_8P4R_5%

RH173 10K_ 0402_5%~DRH 173 10K_0402 _5%~D

1 2

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

CougarPo int_Rev_1p0

CougarPo int_Rev_1p0

R3@

R3@

10K_040 2_5%~D

10K_040 2_5%~D

PLT_RST#<6,22,23 ,27,31,32>

UH1E

UH1E

4

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P

USB

USB

USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

@

@

1 2

RH168 0_0 402_5%~D

RH168 0_0 402_5%~D

+3VS

5

UH5

UH5

P

IN1

4

O

IN2

G

SN74AHC1G0 8DCKR_SC70-5

SN74AHC1G0 8DCKR_SC70-5

3

NV_ALE

AV5
AV10

AT8

AY5
BA2

AT12
BF3

C24
A24

USB20_N9

C25

USB20_P9

B25

USB20_N8

C26

USB20_P8

A26

USB20_N3

K28

USB20_P3

H28

USB20_N4

E28

USB20_P4

D28

USB20_N5

C28

USB20_P5

A28

USB20_N6

C29

USB20_P6

B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USBRBIAS

C33

B33

USB_OC2#

A14

USB_OC1#

K20

1.5VDDR_VID0

B17

1.5VDDR_VID1

C16

USB_OC0#

L16

USB_OC5#

A16

GPIO10

D14

GPIO14

C14

PCH_PLTRST#

1

2

RH183

RH183

@

@

10K_040 2_5%~D

10K_040 2_5%~D

1 2

@

@

RH169

RH169

+3VS

RSVD

RSVD

1 2

PCI

PCI

12

RH171

RH171
100K_04 02_5%~D

100K_04 02_5%~D

3

USB20_N9 < 26>
USB20_P9 <26>
USB20_N8 < 32>
USB20_P8 <32>
USB20_N3 < 21>
USB20_P3 <21>
USB20_N4 < 32>
USB20_P4 <32>
USB20_N5 < 32>
USB20_P5 <32>
USB20_N6 < 34>
USB20_P6 <34>

Within 500 mils

1 2

RH163 22.6_04 02_1%RH163 22.6_0402 _1%

1 2

RH277 0_0 402_5%~D@ RH277 0_0402_5 %~D@

1 2

RH278 0_0 402_5%~DRH 278 0_0402 _5%~D

USB/B

Bluetooth

Camera

Mini Card(WLAN)

Mini Card(Mini2)

ELC LED

USB3_SMI#

USB3_SMI#

PLTRST_VGA#<40>

USB_OC2# <2 6>

1.5VDDR_VID0 <53>

1.5VDDR_VID1 <53>

USB3_SMI# <27 >

RH17 0

12

100_04 02_5%~D

100_04 02_5%~D

100K_04 02_5%~D

100K_04 02_5%~D

(For USB Port 9 )

1 2

RH254 0_0 402_5%~D@ RH254 0_0402_5 %~D@

RH170

4

Y

12

RH172

RH172

+3VS

5

UH6

UH6

2

P

B

DGPU_HOLD_ RST#

1

A

G

SN74AHC1G0 8DCKR_SC70-5

SN74AHC1G0 8DCKR_SC70-5

3

2

Intel Anti-Thef t Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

RH160 1K_0402_5%~D@RH 160 1K_04 02_5%~D@

USB_OC0#
USB_OC2#
GPIO10
USB_OC5#

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
GPIO14

1 2

RH265 0_0 402_5%~D@ RH265 0_0402_5 %~D@

1 2

RH266 0_0 402_5%~DRH 266 0_0402 _5%~D

RH179

RH179

@

@

10K_040 2_5%~D

10K_040 2_5%~D

1 2

1 2

4 5
3 6
2 7
1 8

10K_120 6_8P4R_5%~D

10K_120 6_8P4R_5%~D

4 5
3 6
2 7
1 8

10K_120 6_8P4R_5%~D

10K_120 6_8P4R_5%~D

*

RPH1

RPH1

RPH2

RPH2

DGPU_PWROK

PCH_PLTRST#

1

+1.8VS

+3V_PCH

DGPU_PWROK <17,38,39,55, 56>

Security Classification

Security Classification

CH99

CH99

CLK_PCI1

12

@

@

10P_040 2_50V8J~D

10P_040 2_50V8J~D

Reserve for RF please close to UH1

5

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

LA-6801P

LA-6801P

LA-6801P

1

16 61Tuesday, Ja nuary 25, 2011

16 61Tuesday, Ja nuary 25, 2011

16 61Tuesday, Ja nuary 25, 2011

1.0

1.0

1.0

of

of

of

5

+3V_PCH

12

RH270

RH270
10K_040 2_5%~D

10K_040 2_5%~D

HDMI_PCH_HPD# GPIO6

D D

GPIO28

On-Die PLL Volt age Regu lator
This si gnal has a weak internal pull up

HOn-Die voltage regulator enabl e

*

LOn-Die PLL Volt age Regulator d isable

PCH_GPIO37

C C

FDI TER MINATION VOLTAGE OVERRID E

LOW - Tx, Rx te rminated

*

to same voltage
(DC Coupling Mo de)

+3VS

RH181 1K_ 0402_5%~D@RH181 1K_0402_5 %~D@

RH182

RH182

1 2

1 2

RH177 1K_0 402_5%~D@R H177 1K_0402 _5%~D@

12

10K_040 2_5%~D

10K_040 2_5%~D

PCH_GPIO28

PCH_GPIO37

PCH_GPIO37

GPIO27

PCH_GPI O27 (Hav e intern al Pull- High)
High: V CCVRM VR Enable

*

Low: VC CVRM VR Disable

RH186 10K_0402_5 %~D@ RH186 10K_0402_ 5%~D@

B B

High: CRT Plugged

A A

CRT_DET#<21>

1 2

CRT_DET

QH5

QH5

SSM3K7002F_SC59 -3

SSM3K7002F_SC59 -3

5

PCH_GPIO27

+3VS

2

G

G

RH198

RH198
10K_040 2_5%~D

10K_040 2_5%~D

1 2

13

D

D

S

S

PCH_GPI O28 need s to be connecte d to XDP _FN8
PCH_GPI O35 need s to be connecte d to XDP _FN9
PCH_GPI O15 need s to be connecte d to XDP _FN16

Please refer to Huron R iver Deb ug Board DG 0.5

4

UH1F

CRT_DET

DGPU_EDIDSEL#<37 >

EC_SCI#<31>

EC_SMI#<3 1>

BT_RADIO_DIS#<32 >

HDMI_PCH_HPD#<39>

DGPU_PWROK<16,38,39,55, 56>

BT_ON#<32>

ODD_DETECT#<28>

FFS_INT2<28 >

HDD_DETECT#<28>

4

DGPU_EDIDSEL#

EC_SCI#

EC_SMI#

BT_RADIO_DIS#

HDMI_PCH_HPD#

GPIO16

DGPU_PWROK

PCH_GPIO22

PCH_GPIO27

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

FFS_INT2

GPIO49

HDD_DETECT#

UH1F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPo int_Rev_1p0

CougarPo int_Rev_1p0

R3@

R3@

3

ODD_EN#

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

GPIO

GPIO

CPU/MISC

CPU/MISC

NCTF

NCTF

3

C40

GPIO69

B41

C41

A40

P4

A20GATE

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PECI

RCIN#

NC_1

Issued Date

Issued Date

Issued Date

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

ODD_EN# <2 8>

T126 PAD~D@T126 PAD~D@

@

1 2

KB_RST# <3 1>

H_CPUPWRGD <6>

1 2

2011/01/25 2012/01/25

2011/01/25 2012/01/25

2011/01/25 2012/01/25

RH1750_0402_5%~D@RH1750_0402_5%~D

RH176390_ 0402_5% RH17639 0_0402_5 %

H_PECI <6, 31>

H_THERMTRIP#

12

@

@

RH178

RH178
10K_040 2_5%~D

10K_040 2_5%~D

Compal Secre t Data

Compal Secre t Data

Compal Secre t Data

2

+3VS

RH174

RH174
10K_040 2_5%~D

10K_040 2_5%~D

1 2

GATEA20 <31>

H_THERMTRIP# <6>

INIT3_3V

This signal has weak internal
PU, can't pull low

CRT_DET#

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

PCH_GPIO22

GPIO35

GPIO49

PCH_GPIO38

PCH_GPIO39

GPIO6

Deciphered Date

Deciphered Date

Deciphered Date

2

DGPU_EDIDSEL#

ODD_EN#

HDD_DETECT#

EC_SMI#

1

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

+1.8VS

12

RH161

RH161

2.2K_040 2_5%~D

2.2K_040 2_5%~D

12

RH1621K_0 402_5%~D RH1621K_0 402_5%~D

H_SNB_IVB# <6>

CLOSE TO THE BRANCHING POINT

RH161 an d RH162
Follow C RB FAB2 setting

+3VS

RH180 10K_ 0402_5%~DRH 180 10K_0402 _5%~D

1 2

+3V_PCH

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH187

RH187

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH188

RH188

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH190

RH190

+3VS

@

@

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH192

RH192

200K_04 02_5%

200K_04 02_5%

1 2

RH193

RH193

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH274

RH274

8.2K_040 2_5%~D

8.2K_040 2_5%~D

1 2

RH195

RH195

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH196

RH196

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH197

RH197

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH257

RH257

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH258

RH258

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH262

RH262

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH263

RH263

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH271

RH271

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

LA-6801P

LA-6801P

LA-6801P

1

17 61Tuesday, Ja nuary 25, 2011

17 61Tuesday, Ja nuary 25, 2011

17 61Tuesday, Ja nuary 25, 2011

1.0

1.0

1.0

of

of

of

5

4

3

2

1

+1.05VS

@

@

J10

J10

12

PAD-OPEN 4x4m

PAD-OPEN 4x4m

D D

+1.05VS

+1.05VS

@

@

12

RH201 0_0603_5%~D

RH201 0_0603_5%~D

1

2

RH200 0_0603_5%~DRH200 0_0603_5%~D

+VCCAPLLE XP_R

1 2

1UH_LB2012T1R0M_20%~D

1UH_LB2012T1R0M_20%~D

Place CH40 Near BJ22 pin

+1.05VS

12

RH203

RH203

0_0805_5%~D

C C

+1.05VS

B B

0_0805_5%~D

+3VS

12

RH206

RH206
0_0805_5%~D

0_0805_5%~D

1

CH44

CH44

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

@

@

RH208 0_0603_5%~D

RH208 0_0603_5%~D

1

CH37

CH37

2

10U_0805_4VAM~D

10U_0805_4VAM~D

+3VS_VCCA 3GBG

Place CH53 Near BG6 pin

12

1

CH46

CH46

2

@

@

1

2

1

CH27

CH27

2

10U_0805_4VAM~D

10U_0805_4VAM~D

LH3

@LH3

@

+1.05VS_VCC_E XP

1

CH38

CH38

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCC ORE

1

CH28

CH28

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

1

CH39

CH39

CH40

CH40

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH209

RH209

1 2

0_0805_5%~D

0_0805_5%~D

+VCCP_VC CDMI

1

CH26

CH26

CH25

CH25

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCD PLLEXP

+VCCAPLLE XP

1

CH35

CH35

2

@

@

10U_0805_4VAM~D

10U_0805_4VAM~D

1

CH41

CH41

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCCAFDI_VRM

+1.05VS_VCCA PLL_FDI

+1.05VS_VCCD PLL_FDI

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

UH1G

UH1G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLE XP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CougarPoint_Rev_1p0

CougarPoint_Rev_1p0

R3@

R3@

1300mA

2925mA

POWER

POWER

VCC CORE

VCC CORE

VCCIO

VCCIO

FDI

FDI

CRTLVDS

CRTLVDS

60mA

DMI

DMI

190mA

DFT / SPI HVCMOS

DFT / SPI HVCMOS

20mA

1mA

VCCADA C

VSSADAC

1mA

VCCALVD S

VSSALVD S

VCCTX_LVDS [1]

VCCTX_LVDS [2]

VCCTX_LVDS [3]

VCCTX_LVDS [4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKD MI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

20mA

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVD S

AK36

AK37

AM37

AM38

AP36

AP37

+3VS_VCC3_ 3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VC CDMI

AT20

+1.05VS_VCC_D MI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPS PI

V1

1

CH29

CH29

2

+VCCTX_LVDS

CH32

CH32

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

CH36

CH36

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

CH45

CH45

2

1

CH47

CH47
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

2

RH202

RH202

1 2

0_0805_5%~D

0_0805_5%~D

1

CH43

CH43
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+VCCPNAND

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
RH210

RH210

1 2

0_0805_5%~D

0_0805_5%~D

1

CH31

CH31
10U_0805_4VAM~D

10U_0805_4VAM~D

CH30

CH30

2

RH199 0_0805_5%RH199 0 _0805_5%

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

Near AP43

1

CH33

CH33

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

2

+3VS

+VCCP_VC CDMI

RH205

RH205

1 2

0_0805_5%~D

0_0805_5%~D

1 2

RH207 0_080 5_5%~DRH207 0_0805_5%~D

+3V_PCH

LH1

LH1

12

BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

CH34

CH34

1

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

2

1

CH42

CH42

+1.05VS

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.8VS

+3VS

+3VS

LH2

LH2

12

0.1UH_MLF1608DR10KT_10%_1608

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

+1.05VS

RH204

RH204

1 2

0_0805_5%~D

0_0805_5%~D

+1.8VS

PCH Powe r Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Ic cmax
Curre nt (A )

0.001

5

5

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

+3VALW

1

C432

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

A A

5

C432

SUSP#<10,31,33,53,54>

4

2

SUSP#

U47

U47

1

VIN

3

EN

RT9013-15GB_SOT23-5

RT9013-15GB_SOT23-5

+1.5VS +VCCAFDI_VRM

RH211

@RH211

@

+VCCAFDI_VRM

12

0_0603_5%~D

0_0603_5%~D

VOUT

GND

5
4

NC

2

12

RH212

RH212

0_0603_5%~D

0_0603_5%~D

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

Compal Secret Data

Dec iphered Date

Dec iphered Date

Dec iphered Date

2

VCCVRM = 160mA detal waiting f or newest spec

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR

PCH (6/8) PWR

LA-6801P

LA-6801P

LA-6801P

1

1.0

1.0

1.0

of

of

of

18 61Tuesday, January 25, 2011

18 61Tuesday, January 25, 2011

18 61Tuesday, January 25, 2011

5

4

3

2

1

+1.05VS

+3V_PCH

+3V_DSW

D D

+1.05VS

PCH_VREG_EN#<31>

C C

+3VS

B B

A A

+1.05VS

RH216

@ RH216

@

1 2

0_0805_5%~D

0_0805_5%~D

QH6

+3VALW +3V_DSW

QH6
AO3419L_SOT23-3

AO3419L_SOT23-3

S

S

G

G

5/18 delete RH229

+3VS_VCC_C LKF33_R

1 2

RH2300_0805_5%~D RH2300_0805 _5%~D

+1.05VS

@

@

12

RH234 0_0603_5%~D

RH234 0_0603_5%~D

+1.05VS

RH235 0_0603_5%~DRH235 0_0603_5%~D

+1.05VS

+1.05VS

+1.05VS

+VCCA_DP LL_L

1 2

RH247

RH247

0_0805_5%~D

0_0805_5%~D

1 2

RH214 0_0603_5%~DRH214 0_0603_5%~D

1 2

RH221 0_0603_5%~D@RH221 0_0603_5%~D@

LH4

@LH4

@

10UH_LBR2012T100M_20%~D

+VCCAPLL_C PY +3VS_VC C_CLKF33

2

5

10UH_LBR2012T100M_20%~D

1 2

D

D

13

1 2

+1.05VM_VCCSUS

12

1

CH72

CH72

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

RH237 0_0603_5%~DRH237 0_0603_5%~D

RH239 0_0603_5%~DRH239 0_0603_5%~D

1 2

RH242 0_060 3_5%~DRH242 0_0603_5%~D

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

1 2

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D

@

@

1

CH49

CH49

2

+1.05VS

1 2

RH225 0_080 5_5%~DRH225 0_0805_5%~D

LH5

LH5

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

12

1

2

12

1

CH77

CH77
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

2

LH7

LH7

LH8

LH8

+1.05VS

+3VS_VCC_C LKF33

1

1

CH66

CH66

2

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

+VCCDIFFCLK

+1.05VS_VCCD IFFCLKN

CH74

CH74
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+V_CPU_IO

CH79

CH79

1

+

+

CH86

CH86

2

220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

1

CH48

CH48

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2

RH219 0_0603_5%~DRH219 0_0603_5%~D

CH67

CH67

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05VS_VCCD IFFCLKN

+1.05VS_SSCVC C

1

CH78

CH78

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

2

+1.05VS_VCCA _A_DPL

+1.05VS_VCCA _B_DPL

1

CH87

CH87

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@

@

RH213 0_0603_5%~D

RH213 0_0603_5%~D

CH51

@CH51

@

1

CH57

CH57

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

CH60

CH60

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH71

CH71

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

CH81

CH81

CH80

CH80

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

+

+

CH88

CH88

CH89

CH89

2

2

220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

12

1

2

1

CH58

CH58

2

1

CH61

CH61

2

+VCCRTCEXT

1

@

@

CH76

CH76
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+RTCVCC

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4

+VCCACLK

+VCCPDSW

+PCH_VCCDS W

+VCCAPLL_C PY_PCH

+VCCDPLL_ CPY

+VCCSUS1

1

@

@

CH54

CH54
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+1.05VM_VCCASW

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

CH62

CH62

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCCAFDI_VRM

+1.05VS_VCCA _A_DPL

+1.05VS_VCCA _B_DPL

+VCCSST

+1.05VM_VCCSUS

1

CH82

CH82

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

UH1J

UH1J

AD49

VCCACLK

T16

VCCDSW3_ 3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLD MI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADP LLA

BF47

VCCADP LLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

1

CH83

CH83

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

VCCRTC

1

CougarPoint_Rev_1p0

CougarPoint_Rev_1p0

CH84

CH84

2

R3@

R3@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

POWER

POWER

N26

VCCIO[29]

P26

119mA

PCI/GPIO/LPCMISC

PCI/GPIO/LPCMISC

SATA USB

SATA USB

HDA

HDA

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLS ATA

10mA

3

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

1mA

V5REF

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

201 1/01/25 201 2/01/25

3mA

1010mA

Clock and Miscellaneous

Clock and Miscellaneous

80mA

80mA

55mA

95mA

1mA

CPURTC

CPURTC

Sec urity Classificatio n

Sec urity Classificatio n

Sec urity Classificatio n

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

+1.05VS_VCCUSB CORE

1

CH50

CH50
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+3V_VCCPUSB

1

CH52

CH52

2

+1.05VS_VCCA UPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPS US_1

+PCH_V5REF_RUN

1

CH63

CH63
1U_0402_6.3V

1U_0402_6.3V

2

+3VS_VCCP PCI

+VCC3_3_2

+VCCAFDI_VRM

+VCCAFDI_VRM

+1.05VS_VCC_S ATA

+VCCME_22

+VCCME_23

+VCCME_21

+VCCSUSHDA

1

CH850.1U_0402_1 0V7K~D C H850.1U_0402_10V7K~D

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

RH220 0_0603_5%~DRH220 0_0603_5%~D

RH217 0_0603_5%~DRH217 0_0603_5%~D

+3V_VCCAUBG

1

CH53

CH53

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+3V_VCCPS US

1

CH69

CH69

2

+1.05VS_VCC_S ATA

RH240 0_0603_5%~DRH240 0_060 3_5%~D

RH241 0_0603_5%~DRH241 0_060 3_5%~D

RH243 0_0603_5%~DRH243 0_060 3_5%~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

12

RH223 0_0603_5%~DRH223 0_0603_5%~D

RH224 0_0603_5%~DRH224 0_0603_5%~D

1

CH59

CH59

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+3VS_VCCP CORE

1

CH65

CH65

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+3VS

RH232

RH232

12

0_0603_5%~D

0_0603_5%~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

+1.05VS_SATA3

+VCCSATAPLL

1

CH75

CH75

2

12

12

12

RH244 0_0603_5%~DRH244 0_0603_5%~D

RH245 180_0402_1%@ RH245 180_0402_1%@

12

@

@

RH246

RH246

150_0402_1%~D

150_0402_1%~D

Dec iphered Date

Dec iphered Date

Dec iphered Date

RH218 0_0603_5%~DRH218 0_0603_5%~D

RH226

RH226
0_0603_5%~D

0_0603_5%~D

RH228 0_080 5_5%~DRH228 0_0805_5%~D

1

2

+1.05VS_SATA3

RH238

RH238

0_0805_5%~D

0_0805_5%~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

2

12

+1.05VS

12

+3V_PCH

12

+1.05VS

12

12

+3V_PCH

12

RH231 0_0603_5%~DRH231 0_0603_5%~D

CH68

CH68

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

RH233

RH233

1

0_0805_5%~D

0_0805_5%~D

CH70

CH70
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

12

+1.05VS

+1.05VS

12

VCC3_3 = 266mA detal waiting f or newest spec

VCCDMI = 42mA d etal waiting fo r newest spec

QH7

QH7
AO3419L_SOT23-3

AO3419L_SOT23-3

D

S

D

S

13

12

G

G

2

12

RH222

RH222

100_0402_5%~D

100_0402_5%~D

12

RH227

RH227

100_0402_5%~D

100_0402_5%~D

@

@

RH236

RH236

12

0_0805_5%~D

0_0805_5%~D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

+3V_PCH

+VCCA_USBSUS

+3V_PCH

+3VS

+3VS

12

12

+1.05VS

LH6

@LH6

@

10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

1

CH73

@CH73

@

10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

+3V_PCH

+3V_PCH

PCH_PWR_EN#<33>

RH215

RH215

0_0603_5%~D

0_0603_5%~D

1

CH55

2

@CH55

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCCSATAPLL_ R

Place CH80 Near AK1 pin

If it support 3.3V audio signals
POP:RH2 28
Depop R H233/RH2 34

If it support 1.5V audio signals
POP:RH2 33/RH234
Depop R 228

Title

Title

Title

PCH (7/8) PWR

PCH (7/8) PWR

PCH (7/8) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-6801P

LA-6801P

LA-6801P

Date: Sheet

Date: Sheet

Date: Sheet

+5V_PCH+5VALW

12

1

R22

R22

C8

2

0.1U_0402_10V7K~DC80.1U_0402_10V7K~D

+3V_PCH+5V_PCH

21

DH2

DH2
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

1

CH56

CH56

0.1U_0603_25V7K

0.1U_0603_25V7K

2

+3VS+5VS

21

DH3

DH3
RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

1

CH64

CH64
1U_0603_10V6K~D

1U_0603_10V6K~D

2

+1.05VS

1

20K_0402_5%~D

20K_0402_5%~D

1.0

1.0

1.0

of

of

of

19 61Tuesday, January 25, 2011

19 61Tuesday, January 25, 2011

19 61Tuesday, January 25, 2011