Compal LA-675AP Schematics Rev1.0

A

1 1

B

C

D

E

Compal Confidential

2 2

G470/G570 UMA M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH

3 3

2010-12-03

LA-675AP

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-675AP

E

151Thursday, May 05, 2011

1.0

of

A

Compal confidential

File Name : G470/G570

B

C

D

For 14"(Page 4x) LS6753P PWR/B LS6751P CardReader/B

E

For 15"(Page 4x+1) LS6753P PWR/B LS6751P CardReader/B LS6754P LED/B

Intel

1 1

HDMI Connector

CRT

Page33

Page32

100MHz

2.7GT/s

Connector LVDS

2 2

Connector

LAN

Page31

Page35

PCI-E x1 *6

Athros

AR8151-B(GLAN) AR8152-B(10/100)

RJ-45 Connector

PCI Express

Mini Card Slot *1

3 3

Page36

SPIROM BIOS

PCI-E(WLAN)

USB(WiMAX)

WLAN WiMAX

Page34

Sandy Bridge

Socket-rPGA988B

37.5mm*37.5mm

FDI *8

Intel

Cougar Point

FCBGA 989 25mm*25mm

LPC BUS

Page40

EC

ENE KB930 ENE KB9012

Page5‐11

DMI *4

Page14‐22

DDR3 SO-DIMM *2

BANK 0, 1, 2, 3

Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V)

Audio Codec

AZALIA

USB2.0 *14

SATA *6

Conexant

CX20671

Up to 8GB

Page12‐13

2 channel speaker Int. MIC

Page39

Audio Jacks

Camera Conn. BlueTooth Conn. Mini Card Slot *1 Card Reader

Reltek

RTS5139 SDXC/MMC/MS/xD

USB2.0 *1(Right)

Page42

Page34

LS6755P ODD/B

Touch Pad Int. KBD

USB2.0 *2(Left)

Thermal Sensor

EMC1403

4 4

A

B

Page37

SPI ROM

Page41 Page42

Security Classification

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

eSATA+USB(Left) SATA3 HDD SATA ODD

Compal Secret Data

2010/07/12 2012/07/11

C

Compal Secret Data

Deciphered Date

D

(Port 0/Port 1 support SATA3)

Page38

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA-675AP

Block Diagram

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A

Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

O O O

X

+5VALW

+3VALW

O

O O

X XX X

+1.5V

EC SM Bus2 address

Device

Thermal Sensor EMC1403-2

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

3 3

DDR DIMM0 DDR DIMM2

1001 000Xb 1001 010Xb

B

+5VS +3VS +1.5VS +VCCP +CPU_CORE +VGA_CORE +GFX_CORE +1.8VS

+0.75VS +1.05VS

BOARD ID Table

Board ID

OO

O

XX X

Address

1001_101xb

X

USB Port Table

X

USB 2.0 USB 1.1 Port

EHCI1

EHCI2

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

D

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

E

ON

OFF

ON ON

ON

OFF

LOW

OFF

ON

Board ID / SKU ID Table for AD channel

0

0.1

1 2 3 4 5 6 7

3 External USB Port

0

PCB Revision

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

USB/B (Right Side)

1

USB Port (Left Side)

2

USB Port (Left Side)

3

USB Port (Left Side)

4 5

Camera

6 7 8

Mini Card(WLAN)

9 10 11

Card Reader

12 13

Blue Tooth

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

7 NC

AD_BID

V typ

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

Blue Tooth BT@ eSATA ESATA@ COMMON HDMI HDMI@ Connector ME@ 45 LEVEL 45@ 10/100 LAN 8152@

CMOS@CAMERA DEVICE

GIGA@GIGA LAN

V

max

AD_BID

0 V 0 V

0.538 V

0.875 V

2.341 V

3.300 V

EVT DVT PVT MP

SMBUS Control Table

X X

V

+3VS

X

WLAN WWAN

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA SML0CLK SML0DATA

4 4

SML1CLK SML1DATA

KB930

+3VALW

KB930

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KE930 SODIMM

X V

+3VALW

X X X

V

+3VS

A

X X X

X

X X

V

+3VS

X XX

V

+3VS

X

B

Thermal Sensor

X X X XX

V

+3VS

PCH

X

V

+3VS

X X XXX

Unpop

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

D

@

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-675AP

Date: Sheet

Compal Electronics, Inc.

Notes List

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351Thursday, May 05, 2011

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1

Power-Up/Down Sequence

All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

VDDR3 should ramp-up before or simultaneously with VDDC. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

D D

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and

VDD_CT have ramped up. VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to

ramp-up (or vice versa).)

PCIE_VDDC(1.0V)

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

C C

VDD_CT(1.8V)

PERSTb

REFCLK

Straps Reset

Straps Valid

Global ASIC Reset

B B

T4+16clock

WithoutBACOoption:

PE_GPIO0:Low‐>ResetdGPU;High‐>Normaloperation

PE_GPIO1:Low‐>dGPUPowerOFF;High‐>dGPUPowerON

BACOoption:

PE_GPIO0:High‐>Normaloperation(dGPUisnotresetonBACOmode)

PE_GPIO1:Low‐>dGPUPowerOFF;High‐>dGPUPowerON(alwaysHigh)

dGPUPowerPins

PCIE_PVDD,PCIE_VDDR,TSVDD,VDDR4,VDD_CT, DPE_PVDD,DP[F:E]_VDD18,DP[D:A]_PVDD, DP[D:A]_VDD18,AVDD,VDD1DI,A2VDDQ,VDD2DI, DPLL_PVDD,MPV18,andSPV18

DP[F:E]_VDD10,DP[D:A]_VDD10,DPLL_VDDC,and SPV10

PCIE_VDDC

VDDR3,andA2VDD

BIF_VDDC(currentconsumption=55mA@1.0V,in BACOmode)

VDDR1

VDDC/VDDCI

PowerSequence

+1.0V

+3.3VALW

+1.5V

SI4800

BACO(jmp)

EN

MOS

BACO(jmp)

SI4800

+1.0VGS

+3.3VGS

+1.5VGS

Voltage

1.8V

1.0V

3.3V

Sameas VDDC

1.5V

1.12V

EN

Regulator

+VGA_CORE

+B

1.12V

SI4800

BACO(jmp)

EN

+1.8VGS

PE_GPIO0

PE_EN

dGPU

P24

+1.8V

PE_GPIO1

iGPU

PX3.0

OFF

BACOSwitch P25

BIF_VDDC

BACOMode

ON

ON Sameas PCIE_VDDC

OFF

PX_mode

PWRGOOD

Maxcurrent

1679mA

575mA

2A

190mA

70mA

2.8A

12.9A

Regulators

VDDC/VDDCI

VDDR1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

CLOCK GENERATOR

LA-675AP

1

1.0

of

451Thursday, May 05, 2011

of

451Thursday, May 05, 2011

of

451Thursday, May 05, 2011

5

4

3

2

1

D D

+1.05VS

12

R1

24.9_0402_1%

JCPU1A

EDP_COMP eDP_HPD

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

ME@

DMI

Intel(R) FDI

eDP

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>

C C

+1.05VS

12

R7

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

24.9_0402_1%

R7

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

PEG_COMP

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-675AP

1

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551Thursday, May 05, 2011

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+1.05VS

12

R9

62_0402_5%

H_PROCHOT#<32>

H_PROCHOT#

closs to EC 250~750mils

H_PECI<19,32>

H_THRMTRIP#<19>

H_SNB_IVB#<18>

4

56_0402_5%

R15

1 2

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THRMTRIP#

C26

AN34

AL33

AN33

AL32

AN32

JCPU1B

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

3

A28

BCLK

A27

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

A16 A15

R8

AK1 A5 A4

CLK_CPU_DMI_R CLK_CPU_DMII#_R

R12 1K_0402_5%R12 1K_0402_5% R13 1K_0402_5%R13 1K_0402_5%

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

R10 0_0402_5%R10 0_0402_5% R11

R11

12 12

H_DRAMRST# <7>

R16 140_0402_1%R16 140_0402_1% R17 25.5_0402_1%R17 25.5_0402_1% R18 200_0402_1%R18 200_0402_1%

2

1 2 1 2

0_0402_5%

12 12 12

DG1.0

+1.05VS

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

DDR3 Compensation Signals

1

PRDY#

R22

C C

R26

0_0402_5%

H_CPUPWRGD<19>

0_0402_5%

0.1U_0402_16V4Z

10/12 reserve R880 / R882

B B

PCH_POK<16,32>

SYS_PWROK<16>

PM_DRAM_PWRGD<16>

1 2

R161 100K_0402_5%R161 100K_0402_5%

+3VS

1 2

R26

1 2

R27

R27 10K_0402_5%

10K_0402_5%

1 2

+3VALW

1

C33

2

R8820_0402_5%@R8820_0402_5%

@

R8800_0402_5%@R8800_0402_5%

@

U1

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

SUSP<10,37,51>

PM_SYS_PWRGD_BUF

4

O

SUSP

2

G

H_PM_SYNC<16>

+1.5V_CPU_VDDQ

12

@

R33

R33 39_0402_5%

39_0402_5%

13

D

Q1

Q1 2N7002H_SOT23-3

2N7002H_SOT23-3

S

12

R30

R30 200_0402_5%

200_0402_5%

@

Change footprint 20100814

R22

0_0402_5%

1 2

R29

1 2

130_0402_5%

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

ME@

12

R35

@R35

@

0_0402_5%

+1.05VS

R32

75_0402_5%

R34

43_0402_1%

1 2

SN74LVC1G07DCKR_SC70-5

Buffered reset to CPU

0.1U_0402_16V4Z

12

BUFO_CPU_RST#

JTAG & BPM

C34

U2

4

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+3VS

1

2

5

1

P

NC

Y

2

A

G

3

TCK TMS

TDO

TDI

AP27 AR26

AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

PLT_RST#

XDP_PREQ# XDP_TCK

XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

3V

PLT_RST# <18>

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5%

XDP_TDO

R23 51_0402_5%@R23 51_0402_5%@

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

R28 1K_0402_5%R28 1K_0402_5%

12

+3VS

XDP_PRDY#

AP29

+1.05VS

12 12 12

12 12

PU/PD for JTAG signals

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-675AP

Date: Sheet

2

Date: Sheet

1

651Thursday, May 05, 2011

1.0

of

5

JCPU1C

4

3

JCPU1D

2

1

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

F10 G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8

AE8 AD9 AF9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

J1

J5

J4

J2

K2 M8

N8 N7

M9 N9 M7

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

RSVD_TP[10]

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0]

SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

SA_ODT[0]

SA_ODT[1] RSVD_TP[9]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AM5 AM6 AR3

AN3 AN2 AN1

AN9

AN8 AR6 AR5 AR9

AJ11

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34]

AP3

SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40] SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

Sandy Bridge_rPGA_Rev1p0

Deciphered Date

Sandy Bridge_rPGA_Rev1p0

ME@

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-675AP

1

751Thursday, May 05, 2011

of

1.0

Sandy Bridge_rPGA_Rev1p0

ME@

R36

@R36

@

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q2

G

BSS138_NL_SOT23-3

2

1

C35

0.047U_0402_16V4Z

2

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH<15>

5

R40

0_0402_5%

1 2

DRAMRST_CNTRL

+1.5V

12

R37

1K_0402_5%

R38

R38 1K_0402_5%

1K_0402_5%

1 2

Eiffel used 0.01u Module design used 0.047u

4

DDR3_DRAMRST# <12,13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

JCPU1E

L7

RSVD28

AG7

AK28

CFG[0]

AK29

CFG2 CFG4

CFG5 CFG6 CFG7

C C

B B

R64

1K_0402_1%

T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD

12

R353

1K_0402_1%

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev1p0

ME@

RESERVED

RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

VCC_DIE_SENSE

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

KEY

AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

T13PAD T13PAD

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

*

Display Port Presence Strap

CFG4

*

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

R41

R41 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

12

R42

@ R42

@

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

12

R43

@R43

@

CFG7

12

@R45

@

R44

@R44

@

1K_0402_1%

R45 1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-675AP

1

851Thursday, May 05, 2011

1.0

of

5

+CPU_CORE

D D

+CPU_CORE

C C

+CPU_CORE

B B

(330uF)*4

(6/16 change 10uF_0603_6.3V)*5

10U_0805_6.3V6M

1

2

1

2

1

C36

2

C48

10U_0603_6.3V6M

C48

10U_0603_6.3V6M

1

2

10U_0805_6.3V6M

1

C37

2

C49

10U_0603_6.3V6M

C49

10U_0603_6.3V6M

1

2

10U_0805_6.3V6M

1

C38

C39

2

C50

10U_0603_6.3V6M

C50

10U_0603_6.3V6M

C51

10U_0603_6.3V6M@C51

10U_0603_6.3V6M

1

2

@

(22uF_0805_6.3V)*16

C67

22U_0805_6.3V6M

C67

22U_0805_6.3V6M

C66

22U_0805_6.3V6M@C66

22U_0805_6.3V6M

1

2

@

C74

22U_0805_6.3V6M

C74

22U_0805_6.3V6M

1

2

1

2

330U_X_2VM_R6M

1

+

2

22U_0805_6.3V6M

1

2

C79

22U_0805_6.3V6M

C79

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

330U_X_2VM_R6M

1

C89

C88

+

2

C68

22U_0805_6.3V6M

C68

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

C75

1

2

22U_0805_6.3V6M@C81

22U_0805_6.3V6M

C80

1

@

2

C84

22U_0805_6.3V6M

1

2

330U_X_2VM_R6M

1

C90

+

2

C70

22U_0805_6.3V6M

C70

22U_0805_6.3V6M

1

2

C76

C77

22U_0805_6.3V6M

C77

22U_0805_6.3V6M

1

2

C82

22U_0805_6.3V6M@C82

22U_0805_6.3V6M

C81

1

@

2

C86

22U_0805_6.3V6M

C86

22U_0805_6.3V6M

C85

1

2

C394

330U_X_2VM_R6M

1

+

2

1

+

C91

2

8/23 modify

A A

5

4

POWER

JCPU1F

POWER

3

2

1

Cap quantity follow HR_PDDG_Rev07

QC=94A

C399

DC=53A

1

+

2

10U_0805_6.3V6M

1

C40

2

C52

10U_0603_6.3V6M

C52

10U_0603_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

1

2

@+C394

@

C53

10U_0603_6.3V6M

C53

10U_0603_6.3V6M

1

2

C71

C78

C83

C87

@+C399

@

330U_X_2VM_R6M

4

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev1p0

ME@

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30

PEG AND DDR

VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

SENSE LINES SVID

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

2010/07/12 2012/07/11

CORE SUPPLY

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

18A

+1.05VS

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

C41

22U_0805_6.3V6M

C41

22U_0805_6.3V6M

C42

22U_0805_6.3V6M

C42

22U_0805_6.3V6M

1

2

C58

22U_0805_6.3V6M

C58

22U_0805_6.3V6M

C57

22U_0805_6.3V6M

C57

22U_0805_6.3V6M

1

2

OSCAN

(220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)

R47 43_0402_5%R47 43_0402_5% R48 0_0402_5% R48 0_0402_5% R49 0_0402_5% R49 0_0402_5%

R50 130_0402_5%R50 130_0402_5%

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

B10 A10

1 2

8/12 Modify, need follow diffential routing R74 close CPU,R75 close PWR

R52 0_0402_5%R52 0_0402_5% R53 0_0402_5%R53 0_0402_5%

R74

VSSIO_SENSE

0_0402_5%

@

Compal Secret Data

1 2 1 2

VCCIO_SENSE <51>

Deciphered Date

22uF*7 NO-STUFF

(22uF_0805_6.3V)*13

OSCAN

C44

22U_0805_6.3V6M

C44

22U_0805_6.3V6M

C43

22U_0805_6.3V6M

C43

22U_0805_6.3V6M

1

2

C59

22U_0805_6.3V6M@C59

22U_0805_6.3V6M

1

2

1 2 1 2 1 2

1 2

R75

0_0402_5%

@

1

2

C60

22U_0805_6.3V6M@C60

22U_0805_6.3V6M

1

@

2

12

22U_0805_6.3V6M

22U_0805_6.3V6M@C61

22U_0805_6.3V6M

C54

C61

@

1

+

2

+1.05VS

12

+1.05VS

+CPU_CORE

C45

22U_0805_6.3V6M

C45

22U_0805_6.3V6M

1

2

C62

22U_0805_6.3V6M@C62

22U_0805_6.3V6M

1

@

2

C69

C69 220U_6.3V_M

220U_6.3V_M

R46

R46 75_0402_5%

75_0402_5%

12

R51

R51 100_0402_1%

100_0402_1%

12

R54

R54 100_0402_1%

100_0402_1%

22U_0805_6.3V6M

C46

22U_0805_6.3V6M

C46

22U_0805_6.3V6M

1

2

C63

22U_0805_6.3V6M@C63

22U_0805_6.3V6M

22U_0805_6.3V6M@C64

22U_0805_6.3V6M

1

@

2

1

+

C72

C72 220U_6.3V_M

220U_6.3V_M

2

VR_SVID_CLK

VCCSENSE <53> VSSSENSE <53>

C55

1

2

C64

1

@

2

series-resistors close to VR

VR_SVID_ALRT# <53> VR_SVID_CLK <53> VR_SVID_DAT <53>

22U_0805_6.3V6M

22U_0805_6.3V6M@C65

22U_0805_6.3V6M

+1.05VS

C56

C47

22U_0805_6.3V6M

C47

22U_0805_6.3V6M

1

2

C65

@

330U_D2_2.5VY_R9M

C73

1

+

@

2

VSS_SENCE 100ohm +-1% pull-down to GND near processor

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-675AP

1

951Thursday, May 05, 2011

1.0

of

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

8/27 change to stuff

SUSP<6,37,51>

D D

CPU1.5V_S3_GATE<32>

SUSP#<32,37,49,51>

0_0402_5%

R60

@

C C

B B

A A

@

8/27 change to @

+VGFX_CORE

12

1 2

C98

22U_0805_6.3V6M

C98

22U_0805_6.3V6M

1

2

C108

22U_0805_6.3V6M

C108

22U_0805_6.3V6M

1

2

@

R580_0402_5%@R580_0402_5%

@

R590_0402_5%@R590_0402_5%

C99

22U_0805_6.3V6M

C99

22U_0805_6.3V6M

1

2

C109

22U_0805_6.3V6M

C109

22U_0805_6.3V6M

1

2

+1.8VS

1 2

+3VALW

12

R667

100K_0402_5% @

@

13

2

G

Change footprint 20100814

8/27 change to @

C100

22U_0805_6.3V6M

C100

22U_0805_6.3V6M

C101

22U_0805_6.3V6M

C101

22U_0805_6.3V6M

1

2

C110

22U_0805_6.3V6M@C110

22U_0805_6.3V6M

1

2

@

10/21 Change

330U_D2_2.5VY_R9M

C115

1

+

2

R67

0_0805_5%

1

2

1 2

R6680_0402_5% R6680_0402_5%

+VSB

12

R56

15K_0402_1%

RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3

D

Q7

Q7 2N7002H_SOT23-3

2N7002H_SOT23-3

S

C102

22U_0805_6.3V6M

C102

22U_0805_6.3V6M

1

2

C111

22U_0805_6.3V6M@C111

22U_0805_6.3V6M

1

2

1

+

2

C154

22U_0805_6.3V6M@C154

22U_0805_6.3V6M

1

2

@

C103

22U_0805_6.3V6M

C103

22U_0805_6.3V6M

C112

22U_0805_6.3V6M

C112

22U_0805_6.3V6M

330U_D2_2.5VY_R9M

C116

C345

22U_0805_6.3V6M@C345

22U_0805_6.3V6M

@

Change footprint 20100814

C104

22U_0805_6.3V6M

C104

22U_0805_6.3V6M

1

2

C113

22U_0805_6.3V6M

C113

22U_0805_6.3V6M

1

2

@

10U_0805_6.3V6M

1

2

1

2

C130

C105

22U_0805_6.3V6M

C105

22U_0805_6.3V6M

13

D

Q4

2

G

2N7002H_SOT23-3

S

C107

22U_0805_6.3V6M

C107

22U_0805_6.3V6M

C106

22U_0805_6.3V6M

C106

22U_0805_6.3V6M

1

2

+1.8VS_VCCPLL VCCSA_SENSE

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

1

2

J1

@J1

@

1 2

PAD-OPEN 4x4m

U3

DMN3030LSS-13_SOP8L-8

8 7

5

AT24

AT23

AT21

AT20

AT18

AT17

AR24

AR23

AR21

AR20

AR18

AR17

AP24

AP23

AP21

AP20

AP18

AP17

AN24

AN23

AN21

AN20

AN18

AN17

AM24

AM23

AM21

AM20

AM18

AM17

AK24

AK23

AK21

AK20

AK18

AK17

AH24

AH23

AH21

AH20

AH18

AH17

U3

4

12

JCPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

Sandy Bridge_rPGA_Rev1p0

ME@

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

R57

R57 330K_0402_5%

330K_0402_5%

@

1 2 36

R885

1 2

0_0402_5%

POWER

GRAPHICS

1.8V RAIL

1

12

R55

220_0402_5%

2N7002H_SOT23-3

Change footprint 20100814

R55

13

D

Q3

S

2

G

@ C92

@

2

C92

0.1U_0402_10V6K

RUN_ON_CPU1.5VS3#

11/18 add for sequence

1

C97

0.1U_0603_25V7K

2

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

AK35 AK34

+V_SM_VREF_CNT +V_SM_VREF

AL1

0.1U_0402_16V4Z

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

H_FC_C22

C22 C24

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID1

VCC_AXG_SENSE <53> VSS_AXG_SENSE <53>

1

C114

2

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

C118

10U_0603_6.3V6M

C118

10U_0603_6.3V6M

1

2

+VCCSA

C125

10U_0805_6.3V6M

C125

10U_0805_6.3V6M

C124

10U_0805_6.3V6M

C124

10U_0805_6.3V6M

1

2

R68 0_0402_5%

R69 10K_0402_5%

100K_0402_5%

100K_0402_5% R666

R666

@

1 2

C119

10U_0603_6.3V6M

C119

10U_0603_6.3V6M

1

2

C126

10U_0805_6.3V6M

C126

10U_0805_6.3V6M

1

2

1 2

@

10U_0603_6.3V6M

1

2

1

2

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

C121

10U_0603_6.3V6M

C121

10U_0603_6.3V6M

C120

1

2

+VCCSA

@

R65 0_0402_5%R65 0_0402_5%

C127

10U_0805_6.3V6M@C127

10U_0805_6.3V6M

1

+

C128

@+C128

@

330U_2.5V_M

6.3 X4.2

2

R66 0_0402_5%R66 0_0402_5%

VCCSA_SEL <50>

+1.5V_CPU_VDDQ

R61

0_0402_5%

3

2

1

+

C123

C123 330U_2.5V_M

330U_2.5V_M

2

1 2

+1.5V

0.1U_0402_10V6K

C95

1

2

12

1

Q5

@Q5

@

AP2302GN-HF_SOT23-3

VCCSA_SENSE

@

0.1U_0402_10V6K

C129

C396

C96

C396

1

2

+1.5V_CPU_VDDQ

12

10/5 change to 1K

VCCSA_SENSE <50>

VSSSA_SENSE <50>

R62

R62 1K_0402_1%

1K_0402_1%

R63

R63 1K_0402_1%

1K_0402_1%

6/9 change 330U to 22U X2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-675AP

Date: Sheet

2

Date: Sheet

1

10 51Thursday, May 05, 2011

1.0

of

5

D D

C C

B B

4

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AR25 AR22 AR19 AR16 AR13 AR10

AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AJ25

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42

AN7

VSS43

AN4

VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77

AK7

VSS78

AK4

VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

1

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Sandy Bridge_rPGA_Rev1p0

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Sandy Bridge_rPGA_Rev1p0

ME@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

LA-675AP

1

1.0

of

11 51Thursday, May 05, 2011

5

+VREF_DQ_DIMMA +1.5V

+VREF_DQ_DIMMA

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K C133

C133

1

2

D D

C C

B B

A A

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7> DDR_A_WE#<7>

DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

1

2

5

DDR_A_D0

C134

DDR_A_D1 DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 M_CLK_DDR0

M_CLK_DDR#0 DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# M_ODT0 DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

1 2

10K_0402_5%

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

C155

C156

1

2

+1.5V +1.5V

3A@1.5V

DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R81

10K_0402_5%

12

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R83

VTT1

205

G1

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2 DQ22

DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1

VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

CK1 CK1#

VDD12

BA1 RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

4

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 M_CLK_DDR1

M_CLK_DDR#1 DDR_A_BS1

DDR_A_RAS# DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

4

DDR3_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C135

C135

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <13,15,26> SMB_CLK_S3 <13,15,26>

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

1

2

DDR_A_D[0..63]<7> DDR_A_DQS[0..7]<7> DDR_A_DQS#[0..7]<7> DDR_A_MA[0..15]<7>

R72

1K_0402_1%

R73

1K_0402_1%

4*0402 1uf

+1.5V

12

1*0402 2.2uf

3

12

R70

1K_0402_1%

+VREF_DQ_DIMMA

12

R71

Layout Note: Place near DIMM

10U_0603_6.3V6M

C137

C138

1

@

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C139

1

2

+1.5V

C140

1

2

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

OSCAN

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

10U_0603_6.3V6M

C142

1

2

10U_0603_6.3V6M

C143

1

2

10U_0603_6.3V6M

C141

1

2

7/28 Update connect GND directly

+0.75VS

C151

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C153

1

2

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

1U_0402_6.3V6K

1

2

@

Compal Secret Data

Deciphered Date

2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

Layout Note: Place near DIMM

10U_0603_6.3V6M

C144

1

2

1

0.1U_0402_10V6K

C145

C146

1

2

C146

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

0.1U_0402_10V6K

0.1U_0402_10V6K C148

C148

C147

1

2

1

+

C149

C149 220U_6.3V_M

220U_6.3V_M

2

@

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

LA-675AP

1

1.0

of

12 51Thursday, May 05, 2011

5

+VREF_DQ_DIMMB

1

C157

2

C177

1

2

+VREF_DQ_DIMMB DDR_B_D0

DDR_B_D1 DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 M_CLK_DDR2

M_CLK_DDR#2 DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D50

DDR_B_D51 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

R95

1 2

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K R97 10K_0402_5%R97 10K_0402_5%

C178

5

1 2

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

1

C158

+3VS

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7> DDR_B_WE#<7>

DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V4Z

1

2

D D

C C

B B

A A

+1.5V

3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18

53

DQ19 VSS2055DQ28

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U8SN-7F

ME@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

DQ23

VSS19

DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

+1.5V

2 4

DQ4

6

DQ5

8 10 12 14 16

DQ6

18

DQ7

20 22 24 26 28

DM1

30 32 34 36 38 40 42 44 46

DM2

48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102

CK1

104 106 108

BA1

110 112 114

S0#

116 118 120 122

NC2

124 126 128 130 132 134 136

DM4

138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170

DM6

172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

SDA

202

SCL

204 206

G2

4

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 M_CLK_DDR3

M_CLK_DDR#3 DDR_B_BS1

DDR_B_RAS# DDR_CS2_DIMMB#

M_ODT2 M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D54

DDR_B_D55 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.75V

4

DDR_B_D[0..63]<7> DDR_B_DQS[0..7]<7> DDR_B_DQS#[0..7]<7> DDR_B_MA[0..15]<7>

DDR3_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C159

C159

1

2

+VREF_CB

2.2U_0603_6.3V4Z

1K_0402_1%

C160

1K_0402_1%

+1.5V

12

R86

12

R87

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <12,15,26> SMB_CLK_S3 <12,15,26>

+0.75VS

3

Layout Note: Place near DIMM

10U_0603_6.3V6M

C161

C162

1

@

2

Layout Note: Place near DIMM

10U_0603_6.3V6M

C163

1

2

(10uF_0603_6.3V)*8 (0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C165

C164

1

2

10U_0603_6.3V6M

C166

1

2

10U_0603_6.3V6M

C167

1

2

10U_0603_6.3V6M

C168

1

2

7/28 Update connect GND directly

+0.75VS

C173

1U_0402_6.3V6K

C173

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C176

1

2

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C176

1

2

@

2010/07/12 2012/07/11

1U_0402_6.3V6K

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

Layout Note: Place near DIMM

Compal Secret Data

Deciphered Date

2

0.1U_0402_10V6K

0.1U_0402_10V6K C169

C169

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C170

C170

1

2

1

+1.5V

12

R84

1K_0402_1%

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit. 07/17/2009

0.1U_0402_10V6K

0.1U_0402_10V6K C172

C172

C171

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

R85

+VREF_DQ_DIMMB

12

LA-675AP

1

1.0

of

13 51Thursday, May 05, 2011

of

13 51Thursday, May 05, 2011

of

13 51Thursday, May 05, 2011

5

W=20milsW=20mils

R99

1K_0402_5%

1

C179

C179 1U_0603_10V4Z

1U_0603_10V4Z

2

D D

+RTCVCC

R101 1M_0402_5%R101 1M_0402_5% R102 330K_0402_5%R102 330K_0402_5%

*

1 2

1 2 1 2

INTVRMEN

H：Integrated VRM enable L：Integrated VRM disable

(INTVRMEN should always be pull high.)

+3VS

R105 1K_0402_5%@R105 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

+3VALW

C C

R106 1K_0402_5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3VALW

R108 1K_0402_5% R108 1K_0402_5%

12

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

R112

33_0402_5%

HDA_BITCLK_AUDIO<31>

HDA_SYNC_AUDIO<31>

B B

HDA_RST_AUDIO#<31>

HDA_SDOUT_AUDIO<31>

+3VALW +3VALW+3VALW

12

R121

@

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

R125

@

100_0402_1%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

12

R122

200_0402_5%

12

R126

R126 100_0402_1%

100_0402_1%

R114

R116

R118

+RTCBATT+RTCVCC

12

CLRP1

SHORT PADS

SM_INTRUDER# PCH_INTVRMEN

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

R123

200_0402_5%

12

R128

100_0402_1%

C180

15P_0402_50V8J

R878

1M_0402_5%

+RTCVCC

ME_FLASH<32>

C183

1U_0603_10V4Z

1 2

R103 20K_0402_5%R103 20K_0402_5%

1 2

R100 20K_0402_5%R100 20K_0402_5%

C182

1U_0603_10V4Z

ME_FLASH

R107 1K_0402_1%@R107 1K_0402_1%@

1 2

+3VS

G

2

Q10

Q10 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

D

S

D

S

1 2

R325

@R325

@

0_0402_5%

1 2

HDA_SPKR<31>

HDA_SDIN0<31>

Kill_SW#<56,57>

9/27 reserve R878 for DG1.5

DPDG1.1

6/30 update R121, R122, R123

A A

4

1 2

R98 10M_0402_5%R98 10M_0402_5%

1

OSC4OSC

NC3NC

2

CMOS

CLRP2

SHORT PADS

CLRP2

SHORT PADS

1

12

2

CLRP3

SHORT PADS

CLRP3

SHORT PADS

1

12

2

R109

1 2

0_0402_5%

R110

51_0402_5%

12

HDA_SYNC

Y1

1

2

32.768KHZ_12.5PF_9H03200413

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_GPIO33 Kill_SW#

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

SPI_CLK_PCH_R SPI_SB_CS0#

SPI_SI SPI_SO_R

PCH_RTCX1 PCH_RTCX2

1 2 1 2

R663 0_0402_5%@ R663 0_0402_5%@ R670 0_0402_5%@ R670 0_0402_5%@

6/24 Update R663,R670 must be close Y1

C181

C181 15P_0402_50V8J

15P_0402_50V8J

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGARPOINT_FCBGA989

RTCIHDA

JTAG

SPI

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA

SATA3RCOMPO

SATA0GP / GPIO21 SATA1GP / GPIO19

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

3

PCH_RTCX1_OUT <32> PCH_RTCX2_OUT <32>

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36 E36

K36

SERIRQ

V5

AM3 AM1

SATA_ITX_C_DRX_N0

AP7

SATA_ITX_C_DRX_P0

AP5 AM10

AM8 AP11 AP10

AD7 AD5

SATA_ITX_C_DRX_N2

AH5

SATA_ITX_C_DRX_P2

AH4 AB8

AB10 AF3 AF1

Y7 Y5

SATA_ITX_C_DRX_N4

AD3

SATA_ITX_C_DRX_P4

AD1 Y3

Y1 AB3 AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

R117 10K_0402_5%R117 10K_0402_5%

HDD_LED#

P3

PCH_GPIO21

V14

PCH_GPIO19

P1

LPC_AD0 <26,32> LPC_AD1 <26,32> LPC_AD2 <26,32> LPC_AD3 <26,32>

LPC_FRAME# <26,32>

R104 10K_0402_5%R104 10K_0402_5%

R115 750_0402_1%R115 750_0402_1%

12

SERIRQ <32>

R111

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

12

HDD_LED# <56,57>

R119

12

10K_0402_5%

R187 10K_0402_5%

12

@

+1.05VS_VCC_SATA

8/16 reserved for MOW

2

EC and Mini card debug port

+3VS

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

C1840.01U_0402_16V7K C1840.01U_0402_16V7K

12

C1850.01U_0402_16V7K C1850.01U_0402_16V7K

12

C1860.01U_0402_16V7K C1860.01U_0402_16V7K

12

C1870.01U_0402_16V7K C1870.01U_0402_16V7K

12

ESATA@

+1.05VS_SATA3

+3VS

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

C1880.01U_0402_16V7K

12

C1890.01U_0402_16V7K

12

+3VS

4MB SPI ROM FOR ME

+3VS

& Non-share ROM.

SPI_SB_CS0#

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_DRX_N2_CONN SATA_ITX_DRX_P2_CONN

SATA_ITX_DRX_N4 SATA_ITX_DRX_P4

7/28 change from port 5 to port 4

+3VS

R127

R129

R130

0_0402_5%

1 2 1 2

33_0402_5%

R131

SATA_DTX_C_IRX_N0 <30> SATA_DTX_C_IRX_P0 <30> SATA_ITX_DRX_N0 <30> SATA_ITX_DRX_P0 <30>

SATA_DTX_C_IRX_N2 <56,57>

SATA_DTX_C_IRX_P2 <56,57> SATA_ITX_DRX_N2_CONN <56,57> SATA_ITX_DRX_P2_CONN <56,57>

SATA_DTX_C_IRX_N4 <35> SATA_DTX_C_IRX_P4 <35> SATA_ITX_DRX_N4 <35>

SATA_ITX_DRX_P4 <35>

SPI_WP#

1 2

3.3K_0402_5%

SPI_HOLD#

1 2

3.3K_0402_5%

U5

1

CS#

2

SPI_WP#

SO

3

WP#

4

GND

S IC FL 32M W25Q32BVSSIG SOIC 8P

HOLD#

SCLK

VCC

1

HDD

ODD

ESATA

SPI_CLK_PCH

12

R124

33_0402_5%

@

C190

22P_0402_50V8J

@

R1320_0402_5% R1320_0402_5%

SPI_CLK_PCH_R SPI_SI

@

+3VS

C191

1 2

0.1U_0402_16V4Z

8

SPI_HOLD#SPI_SO_R SPI_SO_L

7

SPI_CLK_PCH

6 5

SI

SPI_SI_R

1 2 1 2

33_0402_5%

R133

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-675AP

Date: Sheet

2

Date: Sheet

14 51Thursday, May 05, 2011

1

1.0

of

5

LAN

WLAN

D D

C C

WLAN

LAN

B B

PCIE_PRX_DTX_N1<27>

PCIE_PRX_DTX_P1<27> PCIE_PTX_C_DRX_N1<27> PCIE_PTX_C_DRX_P1<27>

PCIE_PRX_DTX_N2<26>

PCIE_PRX_DTX_P2<26> PCIE_PTX_C_DRX_N2<26> PCIE_PTX_C_DRX_P2<26>

CLK_PCIE_WLAN1#<26> CLK_PCIE_WLAN1<26>

WLAN_CLKREQ1#<26>

CLK_PCIE_LAN#<27> CLK_PCIE_LAN<27>

CLKREQ_LAN#<27>

+3VALW

C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K

1 2

C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K

1 2

C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K

1 2

C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K

1 2

R147 10K_0402_5%R147 10K_0402_5%

+3VALW

R149 0_0402_5%R149 0_0402_5%

1 2

R150 0_0402_5%R150 0_0402_5%

1 2

R156 0_0402_5%R156 0_0402_5%

1 2

R158 10K_0402_5%R158 10K_0402_5%

+3VS

R301 10K_0402_5%R301 10K_0402_5%

+3VS

R153 0_0402_5%R153 0_0402_5%

1 2

R154 0_0402_5%R154 0_0402_5%

1 2

R151 0_0402_5%R151 0_0402_5%

1 2

R152 10K_0402_5%R152 10K_0402_5%

+3VALW

R165 10K_0402_5%R165 10K_0402_5%

+3VALW

R168 10K_0402_5%R168 10K_0402_5%

+3VALW

R170 10K_0402_5%R170 10K_0402_5%

+3VALW

R172 10K_0402_5%R172 10K_0402_5%

R174 10K_0402_5%R174 10K_0402_5%

+3VALW

12

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

Desktop Only

PCH_GPIO73

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

WLAN_CLKREQ1#_R

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46 PCIE_CLK_8N

PCIE_CLK_8P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

3

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

Link

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

EC_LID_OUT#

E12

PCH_SMBCLK

H14

PCH_SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

PCH_SML0CLK

C8

PCH_SML0DATA

G12

7/28 reserved

PCH_GPIO74

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

M7

T11

P10

PEG_CLKREQ#_R

M10

AB37 AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLK_BUF_CPU_DMI#

BF18

CLK_BUF_CPU_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLK_BUF_DREF_96M#

G24

CLK_BUF_DREF_96M

E24

CLK_BUF_PCIE_SATA#

AK7

CLK_BUF_PCIE_SATA

AK5

CLK_BUF_ICH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

CLK_PCI_DB_R

F47 H47 K49

10K_0402_5%

R134

10K_0402_5%

R140

+3VALW

R143

R143 10K_0402_5%

10K_0402_5%

1 2

R155 10K_0402_5%R155 10K_0402_5% R157 10K_0402_5%R157 10K_0402_5%

R159 10K_0402_5%R159 10K_0402_5% R160 10K_0402_5%R160 10K_0402_5%

R162 10K_0402_5%R162 10K_0402_5% R163 10K_0402_5%R163 10K_0402_5%

R164 10K_0402_5%R164 10K_0402_5% R166 10K_0402_5%R166 10K_0402_5%

R167 10K_0402_5%R167 10K_0402_5%

R171

90.9_0402_1%

1 2

R173

1 2

@

12

+3VALW

EC_LID_OUT# <32>

R139

12

1K_0402_5%

7/5 change to 1K

12

+3VALW

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

1 2 1 2

1 2

CLK_PCI_LPBACK <18>

+1.05VS_VCCDIFFCLKN

22_0402_5%

2

Q60A

Q60A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

XTAL25_IN XTAL25_OUT

27P_0402_50V8J

CLK_BUF_ICH_14M

6 1

2 5

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q60B

Q60B

Q61A

Q61A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

2 5

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q61B

Q61B

1

25MHZ_20PF_7A25000012

C196

2

2.2K_0402_5%

1 2 1 2

2.2K_0402_5%

4

R169 1M_0402_5%R169 1M_0402_5%

2.2K_0402_5%

2.2K_0402_5% R136

R136

1 2

+3VALW

1 2

R135

2.2K_0402_5%

DRAMRST_CNTRL_PCH <7>

+3VALW

2.2K_0402_5%

2.2K_0402_5% R141

R141

+3VALW +3VS

CLK_PCI_DB <26>

1 2 1 2

R142

2.2K_0402_5%

SMB_CLK_S3

+3VS

SMB_DATA_S3

EC_SMB_CK2

EC_SMB_DA2

CLK_CPU_DMI# CLK_CPU_DMI

1 2

Y2

R175

@R175

@

33_0402_5%

1

SMB_CLK_S3 <12,13,26>

DIMM1

R137

DIMM2

R138

MINI CARD

SMB_DATA_S3 <12,13,26>

8/14 change P/N to DMN66D0LDW-7_SOT363-6 (SB00000DH00)

EC_SMB_CK2 <29,32>

VGA EC thermal sensor

EC_SMB_DA2 <29,32>

2.2K_0402_5%

PCH_SML0CLK PCH_SML0DATA

7/28 reserved

@

R349 10K_0402_5%

1 2

R347 10K_0402_5%

1 2

@

6/30 Update to @

12

1

C197

C197 27P_0402_50V8J

27P_0402_50V8J

2

C198

@C198

@

22P_0402_50V8J

1 2

R544

+3VALW

1 2

R545

2.2K_0402_5%

1 2

Reserve for EMI please close to PCH

C199

@C199

12

@

22P_0402_50V8J

1 2

R176

@R176

@

33_0402_5%

A A

CLK_PCI_LPBACK

33_0402_5%

Reserve for EMI please close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-675AP

1

15 51Thursday, May 05, 2011

1.0

of

5

D D

MC74VHC1G08DFT2G SC70 5P

VGATE PCH_POK

SYS_PWROK_EC<32>

C C

AEPWROK can be connect to PWROK if iAMT disable

PCH_POK_R APWROK

+3VALW

R192 200_0402_5%

B B

R194 10K_0402_5%R194 10K_0402_5%

R197 10K_0402_5%R197 10K_0402_5%

3

1

G

A

2

B

R180 100K_0402_1%R180 100K_0402_1%

SYS_PWROK

4

Y

P

U6

5

7/28 Defult use AND Gate

*

+3VS

12

R743

1 2

0_0402_5%

R742

1 2

0_0402_5%

7/22 modify

R191

1 2

0_0402_5% @

@

12 12

R195

12

200K_0402_1%

12

SYS_PWROK <6>

SYS_PWROK

SYS_PWROKPCH_POK_R

@

7/22 modify

PM_DRAM_PWRGD SUSWARN# ACIN_R

PCH_RSMRST#_R

SUSACK# is only used on platform that support the Deep Sx state.

VGATE<53>

PCH_POK<6,32>

PCH_APWROK<32>

PM_DRAM_PWRGD<6>

EC_RSMRST#<32>

SUSWARN#<32>

ACIN<32,47>

7/28 modify

+3VS

4

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+1.05VS_PCH

+3VS

R188 0_0402_5%@R188 0_0402_5%@

1 2

R190 0_0402_5%R190 0_0402_5%

1 2

R302 0_0402_5%R302 0_0402_5%

1 2

PBTN_OUT#<32>

1 2

R199 0_0402_5%@R199 0_0402_5%@

+3VALW

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

R177 49.9_0402_1%R177 49.9_0402_1%

1 2

R178 750_0402_1%R178 750_0402_1%

4mil width and place within 500mil of the PCH

T72 PADT72 PAD

R184 10K_0402_5%R184 10K_0402_5%

1 2

R193 0_0402_5%R193 0_0402_5%

1 2

R196 0_0402_5%R196 0_0402_5%

1 2

R198 0_0402_5%R198 0_0402_5%

D29

21

CH751H-40PT_SOD323-2

DMI_IRCOMP RBIAS_CPY

SUSACK#

SYS_RST#

12

SYS_PWROK

PCH_POK_R

APWROK

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#_R SLP_S3#

PBTN_OUT#_R

ACIN_R

PCH_GPIO72

R200

1 2

8.2K_0402_5%

8.2K_0402_5% R201

R201

RI#

12

10K_0402_5%

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989

3

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

PCH_DPWROK_R

WAKE#

1 2 1 2

PM_CLKRUN#

SUS_STAT#

SUSCLK

SLP_S5#

SLP_S4#

PM_SLP_SUS#

H_PM_SYNC

T66 PAD@T66 PAD@

R185

R185 0_0402_5%

0_0402_5%

R186

1 2

8.2K_0402_5%

10K_0402_5%

R189

2

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5> FDI_FSYNC0 <5> FDI_FSYNC1 <5> FDI_LSYNC0 <5> FDI_LSYNC1 <5>

R1810_0402_5% @R1810_0402_5% @

1 2

R1820_0402_5% R1820_0402_5%

1 2

PCIE_WAKE# <26,27>

+3VALW

+3VS

SUSCLK <32>

SLP_S5# <32>

SLP_S4# <32>

SLP_S3# <32>

T71PAD T71PAD

H_PM_SYNC <6>

PCH_RSMRST#_R

PCH_DPWROK <32>

7/28 Update

T73PAD T73PAD

Can be left NC when IAMT is not support on the platfrom

Can be left NC if no use integrated LAN.

1

+RTCVCC

12

R179

R179 330K_0402_5%

330K_0402_5%

12

R183

R183 330K_0402_5%

330K_0402_5%

@

DSWODVREN - On Die DSW VR Enable

*

H

：

Enable

L

：

Disable

R546 200_0402_5%R546 200_0402_5%

12

PM_DRAM_PWRGD

7/28 Modify follow CRB & ORB

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,

LA-675AP

1

1.0

of

16 51Thursday, May 05, 2011

Compal LA-675AP Schematics Rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual