COMPAL LA-6741P Schematics

A

ZZZ1

LA-6741P

DA60000JE10

1 1

2 2

B

C

D

E

Brazos PCM10 LA6741 Schematics Document

AMD APU Ontario-FT1+ FCH Hudson-M1

2010-11-30

3 3

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/05/06

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics,Ltd.

Cover Sheet

PCM10 LA6741 M/B SCHEMATIC

1 36Tuesday, November 30, 2010

E

0.1

of

A

Compal Confidential

B

C

D

E

Model Name :

File Name :

1 1

Brazos

LA6741

Single Channel

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

page 7,8

DDR3-800/1066(1.5V)

LVDS Conn.

page 11

AMD FUSION APU Ontario FT1

BGA-413

page4~6

DDR3-800/1066(1.35V)

PCI-Express

HDMI

page 9

MINI Card

WLAN

page 19

UMI*8

2 2

CRT

page 10

AMD HUDSON-M1

S-ATA

HDA Codec

ALC259-GR

page 20

3 3

SPK

port 0

S-ATA HDD Conn.

page 17

Internal clock GEN

CONN

RTC CKT.

page 21

page 13

Power/B

Power On/Off CKT.

page 24

page 23

605-BALL

LPC BUS

EC

ENE KB926D3

page 22

page12~16

3.3V 48MHz

3.3V 24.576MHz/48Mhz

USB

HD Audio

LAN(10/100)

RTL8105E-VC-GR

page 18

RJ45

page 18

USB conn x3CMOS CameraBluetooth

page 24page 11page 18

Card Reader

RTS5138

page 17

3 in 1 socket

page 17

DC/DC Interface CKT.

page 25

4 4

Power Circuit DC/DC

page 26,28,29 30,31,32,33

CHARGER

page 27

A

Debug port

LED

page 24

page 19

page 21

B

Touch Pad

page 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB I/O Conn.

C

Int.KBD

BIOS

2010/05/06

page 23

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics,Ltd.

MB Block Diagram

PCM10 LA6741 M/B SCHEMATIC

2 36Friday, November 26, 2010

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B

C

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DDR3 Voltage Rails

1 1

+5VS

+3VS

+1.5VS

+CPU_CORE

+NB_CORE

+1.8VS

+0.75VS

+1.1VS

+1.0VS

State

power plane

+B

+3VL

+5VL

+RTCVCC

+5VALW

+1.5V

+3VALW

+1.1VALW

FCH SM Bus0 address

Device Device

SDDIM I

SDDIM II

HEX HEX

A0

A2

1010 0000

1010 0010

EC SM Bus1 address

Device Device

Smart Battery

HEX HEX

16H 1001 100X b

Address

0001 011X b

FCH SM Bus1 address

AddressAddress

WLAN

EC SM Bus2 address

Address

APU internal themal sensor

2 2

3 3

4 4

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

@ Reserve

CONN@

8105E@

8111E@

REAL@

VIA@

ROM@

FROM@

O

X

O

X

X X X

ME CONNECTOR

100M LAN function

GLAN function

ALC259-GR

V1802T

not support flash ROM

Support flash ROM

O

X X

X

OO

X

TDP1_AUXP

TDP1_AUXN

LTDP0_AUXP

LTDP1_AUXN

DAC_SCL

DAC_SDA

SIC

SID

SVC

SVD

SMB_FCH_CK0

SMB_FCH_DA0

SMB_FCH_CK1

SMB_FCH_DA1

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SOURCE

APU

FCH

EC

POWER PLAN

+3VS

+1.8VS

+3VS

+3VALW

+5VALW

+3VS

HDMI LVDS CRT FCH

V

V +5VS

V +3VALW

CPU CORE

V

SDDIM I/II

V

BATTWLAN

APU

V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/05/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

MB Notes List

PCM10 LA6741 M/B SCHEMATIC

3 36Friday, November 26, 2010

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POWER MAP

POWER SEQUENCE

+3VL

1 1

B+

UP618CQAG

SUSP#

SY8033BDBC

SUSP#

SI4800BDY

EN_WOL#

AP2301GN

+5VL

+3VALW

+5VALW

+1.8VS

+5VS

+3V_LAN

+3VALW,+5VALW

EC->FCH

FCH->EC

EC->PWR

SUSP#

SI4800BDY

2 2

POK

ENVDD

SI4800BDY

RT8209BGQW

+3VS

+LCDVDD

+1.1VALW

1.1VSON#

IRF8113PBF

+1.1VS

SUSP#

STS11N3LLH5

+1.0VS

VR_ON

ISL6265AH RTZ

3 3

SYSON

RT8209BGQW

SUSP#

SI4800BDY

+CPU_CORE

+CPU_CORE_NB

+1.5V

+1.5VS

FCH->EC

EC->PWR

+3VS,+5VS,+0.75VS

EC->PWR

PWR->EC

EC_FCH_PWROK

EC->FCH

FCH->APU

FCH->DEVICE

FCH->APU

NOTE1: RSMRST# rise time(10% to 90%)<50ms

SUSP

VDTT11V8

+0.75VS

NOTE2: EC_FCH_PWROK rise time(10% to 90%)<50ms

VIN

B+

+3VL

+1.1VALW

ON/OFFBTN#

EC_RSMRST#

PBTN_OUT#

FCH_SLP_S5#

SYSON

+1.5V

FCH_SLP_S3#

SUSP#

+1.8VS

+1.1VS_ON

+1.1VS

VR_ON

+CPU_CORE +CPU_CORE_NB

VGATE

KB_RST#

APU_PWRGD

A_RST#

LDT_RST#

fail time<1ms

NOTE1

T1

T2

T3

T4

T1>10ms, +3VALW to RSMRST#

T2>100ms, RSMRST# to PBTN_OUT#

T3>100ns, PBTN_OUT# to SLP_S5#

T4>10ms, SLP_S5# to SYSON

The same with SLP_S5#

T5

T6

T5>10ms, SYSON to SUSP#

T6>100ms, SUSP# to VR_ON

NOTE2

T7

T8

T9

T7>50ms, VGATE to EC_FCH_PWROK

98ms>T7>150ms, EC_FCH_PWROK to APU_PWRGD

101ms>T7>113ms, EC_FCH_PWROK to A_RST#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/05/06

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics,Ltd.

Powe map and sequence

PCM10 LA6741 M/B SCHEMATIC

4 36Friday, November 26, 2010

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5

+1.8VS

R74 1K_0402_5%R74 1K_0402_5%

R1 1K_0402_5%R1 1K_0402_5%

R2 1K_0402_5%R2 1K_0402_5%

R3 1K_0402_5%R3 1K_0402_5%

R4 300_0402_5%R4 300_0402_5%

R6 300_0402_5%R6 300_0402_5%

R7 510_0402_1%R7 510_0402_1%

D D

R333 1K_0402_5%R333 1K_0402_5%

+3VS

C C

12

1 2

R64 1K_0402_5%R64 1K_0402_5%

1 2

R14 1K_0402_5%R14 1K_0402_5%

1 2

R16 1K_0402_5%@R16 1K_0402_5%@

1 2

R17 1K_0402_5%@R17 1K_0402_5%@

1 2

R18 4.7K_0402_5%R18 4.7K_0402_5%

1 2

R19 4.7K_0402_5%R19 4.7K_0402_5%

1 2

R21 4.7K_0402_5%R21 4.7K_0402_5%

1 2

R22 4.7K_0402_5%R22 4.7K_0402_5%

1 2

R26 1K_0402_5%R26 1K_0402_5%

R27 1K_0402_5%R27 1K_0402_5%

R28 510_0402_1%R28 510_0402_1%

R29 1K_0402_5%@R29 1K_0402_5%@

R30 1K_0402_5%R30 1K_0402_5%

R31 1K_0402_5%@R31 1K_0402_5%@

1 2

12

TEST_35

APU_LDT_STP#

APU_SVC

APU_SVD

LDT_RST#

APU_PWRGD

TEST_25_L

TEST_36

APU_ALERT#_R

APU_PROCHOT

APU_SIC

APU_SID

HDMI_DAT

HDMI_SCL

LVDS_DAT

LVDS_SCL

TEST_18

TEST_19

TEST_25_H

TEST_35

TEST_15

APU_LDT_STP#

LVDS_CLK+<12> LVDS_CLK-<12>

LDT_RST#<14>

APU_PWRGD<14> APU_PROCHOT_FCH#<14> APU_PROCHOT_EC#<23>

APU_ALERT#<13>

VDDCR_NB_SENSE_H<34>

VDDCR_APU_SENSE_H<34>

VDDCR_NB_SENSE_L<34> VDDCR_APU_SENSE_L<34>

4

HDMI_TX2+<10>

HDMI_TX2-<10>

HDMI_TX1+<10>

HDMI_TX1-<10>

HDMI_TX0+<10>

HDMI_TX0-<10>

HDMI_CLK+<10> HDMI_CLK-<10>

LVDS_TX2+<12> LVDS_TX2-<12>

LVDS_TX1+<12> LVDS_TX1-<12>

LVDS_TX0+<12> LVDS_TX0-<12>

CLK_APU<14>

CLK_APU#<14>

CLK_APU_DP<14>

CLK_APU_DP#<14>

APU_SVC<34>

APU_SVD<34>

R23 0_0402_5%R23 0_0402_5% R24 0_0402_5%R24 0_0402_5% R35 0_0402_5%@R35 0_0402_5%@

1 2

R45 0_0402_5%R45 0_0402_5%

1 2

R63 0_0402_5%R63 0_0402_5%

APU_TDI APU_TDO APU_TCLK APU_TMS APU_TRST# DBRDY DBREQ#

1 2 1 2

1 2

R271 0_0402_5%R271 0_0402_5%

1 2

R272 0_0402_5%R272 0_0402_5%

1 2

T28 PADT28 PAD

R273 0_0402_5%R273 0_0402_5%

1 2

R274 0_0402_5%R274 0_0402_5%

1 2

APU_SIC APU_SID

LDT_RST#_R APU_PWRGD_R

APU_PROCHOT

APU_THERMTRIP#_R

APU_ALERT#_R

U1B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

ONTARIO-2M161000-1.6G_BGA413

3

H3

DP_ZVSS

G2

DP_BLON

H2

DP_DIGON

H1

DP_VARY_BL

DP MISC

DISPLAYPORT 1

DISPLAYPORT 0

VGA DAC

CLK

SER

JTAG CTRL

VGA DAC

TEST

TDP1_AUXP TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC

DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST4 TEST5

TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H TEST25_L TEST28_H TEST28_L

TEST31

TEST33_H TEST33_L TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

B2 C2

C1

A3 B3

D3

C12 D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

R8 150_0402_1%R8 150_0402_1%

1 2

ENBKL <12> ENVDD <12> INV_PWM <12>

HDMI_SCL <10>

HDMI_DAT <10>

HDMI_HPD <10>

LVDS_SCL <12>

R10 100K_0402_5%R10 100K_0402_5%

R12 150_0402_1%R12 150_0402_1%

1 2

R13 150_0402_1%R13 150_0402_1%

1 2

R15 150_0402_1%R15 150_0402_1%

1 2

TEST_4 TEST_5

TEST_14 TEST_15 TEST_16

TEST_17 TEST_18 TEST_19 TEST_25_H TEST_25_L TEST_28_H TEST_28_L TEST_31 TEST_33_H TEST_33_L TEST_34_H TEST_34_L TEST_35 TEST_36 TEST_37

LVDS_DAT <12>

12

CRT_HSYNC <11> CRT_VSYNC <11>

CRT_DDC_CLK <11>

CRT_DDC_DATA <11>

R20 499_0402_1%R20 499_0402_1%

1 2

PADT1PAD PADT2PAD

PADT4PAD

PADT5PAD PADT6PAD

PADT7PAD PADT9PAD PADT8PAD

PAD

PAD PAD

PAD

APU_LDT_STP# <14>

T1 T2

T4

T5 T6

T7 T9 T8

T10

T10 T11

T11

T13

CRT_R <11>

CRT_G <11>

CRT_B <11>

2

TEST_33_H

C1 0.1U_0402_16V4ZC1 0.1U_0402_16V4Z

TEST_33_L

C2 0.1U_0402_16V4ZC2 0.1U_0402_16V4Z

EN_FAN1<23>

FAN_SPEED1<23>

1 2

+VCC_FAN1

C4

10U_0805_6.3V6M

+5VS

1

2

+3VS

12

R32

R32 10K_0402_5%

10K_0402_5%

1

C7

C7 1000P_0402_50V7K

1000P_0402_50V7K

2

10U_0805_10V4Z

R5 51_0402_1%R5 51_0402_1%

1 2

R9 51_0402_1%R9 51_0402_1%

1 2

1A

U2

1

VEN

2

VIN

3

VO

4

VSET

G996RD1U_TDFN8_3X3

40mil

+VCC_FAN1

C3

1 2

Thermal Pad

1

9 8

GND

7

GND

6

GND

5

GND

@ C6

@

1 2

1000P_0402_50V7K

1 2 3

4 5

ACES_85205-03001

JFAN

C6

CONN@

1 2 3

GND GND

U1

1.2G@U1

U1

1.5G@U1

U1

1.6G@U1

+3VS

2N7002DW-T/R7_SOT363-6

APU_SIC

B B

2N7002DW-T/R7_SOT363-6

APU_SID

A A

5

4

Q1B

R366

1 2

0_0402_5%

+3VS

Q1A

R367

1 2

0_0402_5%

R25

R25 1K_0402_5%

1K_0402_5%

APU_THERMTRIP#_R

@Q1B

@

2

@Q1A

@

3

1 2

61

1 2

@

R302 0_0402_5%

R364 0_0402_5%R364 0_0402_5%

@

R363 0_0402_5%

R365 0_0402_5%R365 0_0402_5%

+3VS

12

R70

R70 10K_0402_5%

10K_0402_5%

B

2

E

3 1

C

Q212

Q212 MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

R368 0_0402_5%

@

SCL3_LV <15>

EC_SMB_CK2 <23>

SDA3_LV <15>

EC_SMB_DA2 <23>

4

FCH

EC

FCH

EC

APU_THERMTRIP# <15>

3

1.6G@

1.6G

R33

1K_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.5G@

1.5G

+1.8VS+1.8VS

0_0402_5%

R38

1 2

R39 10K_0402_5%R39 10K_0402_5%

R40 10K_0402_5%R40 10K_0402_5%

R41 10K_0402_5%R41 10K_0402_5%

2009/05/06

1.2G@

1.2G

APU_TRST#_RAPU_TRST#

12

Compal Secret Data

Deciphered Date

U1

1.0G@U1

1.0G@

1.0G

HDT CONNECTOR AMD APU DEBUG PORT

JP1

CONN@JP1

CONN@

1

3

5

7

9

11

13

15

17

19

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

SAMTE_ASP-136446-07-B

APU_PWRGD

J108_PLLTST0

APU_TCLK

APU_TMS

APU_TDI

APU_TDO

LDT_RST#

DBRDY

DBREQ#

J108_PLLTST1

R34 1K_0402_5%R34 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

R37 1K_0402_5%R37 1K_0402_5%

R42 300_0402_5%R42 300_0402_5%

R43 0_0402_5%R43 0_0402_5%

R44 0_0402_5%R44 0_0402_5%

12

+1.8VS

1 2

Title

Size Document Number Rev

Custom

PCM10 LA6741 M/B SCHEMATIC

Date: Sheet of

TEST_19

TEST_18

Compal Electronics, Inc.

DISPLAY,CLK,JTAG

5 36Friday, December 03, 2010

1

5 36Friday, December 03, 2010

0.1

5

DDR_D[0..63]<8,9> DDR_DM[0..7]<8,9> DDR_DQS#[0..7]<8,9> DDR_DQS[0..7]<8,9> DDR_MA[0..15]<8,9>

U1E

DDR_MA0 DDR_MA1 DDR_MA2

D D

DDR_BS0<8,9> DDR_BS1<8,9> DDR_BS2<8,9>

C C

DDR_A_CLK0<8>

DDR_A_CLK0#<8>

DDR_A_CLK1<8>

DDR_A_CLK1#<8>

DDR_B_CLK0<9>

DDR_B_CLK0#<9>

DDR_B_CLK1<9>

DDR_B_CLK1#<9>

DDR_RST#<8,9> DDR_EVENT#<8,9>

DDR_CKE0<8,9> DDR_CKE1<8,9>

DDR_A_ODT0<8> DDR_A_ODT1<8>

B B

DDR_B_ODT0<9> DDR_B_ODT1<9>

DDR_A_CS0#<8> DDR_A_CS1#<8> DDR_B_CS0#<9> DDR_B_CS1#<9>

DDR_RAS#<8,9> DDR_CAS#<8,9> DDR_WE#<8,9>

DDR_MA3 DDR_MA4 DDR_MA5 DDR_MA6 DDR_MA7 DDR_MA8 DDR_MA9 DDR_MA10 DDR_MA11 DDR_MA12 DDR_MA13 DDR_MA14 DDR_MA15

DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 DDR_DM4 DDR_DM5 DDR_DM6 DDR_DM7

DDR_DQS0 DDR_DQS#0 DDR_DQS1 DDR_DQS#1 DDR_DQS2 DDR_DQS#2 DDR_DQS3 DDR_DQS#3 DDR_DQS4 DDR_DQS#4 DDR_DQS5 DDR_DQS#5 DDR_DQS6 DDR_DQS#6 DDR_DQS7 DDR_DQS#7

U1E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

ONTARIO-2M161000-1.6G_BGA413

DDR SYSTEM MEMORY

M_ZVDDIO_MEM_S

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

4

DDR_D0

B14

DDR_D1

A15

DDR_D2

A17

DDR_D3

D18

DDR_D4

A14

DDR_D5

C14

DDR_D6

C16

DDR_D7

D16

DDR_D8

C18

DDR_D9

A19

DDR_D10

B21

DDR_D11

D20

DDR_D12

A18

DDR_D13

B18

DDR_D14

A21

DDR_D15

C20

DDR_D16

C23

DDR_D17

D23

DDR_D18

F23

DDR_D19

F22

DDR_D20

C22

DDR_D21

D22

DDR_D22

F20

DDR_D23

F21

DDR_D24

H21

DDR_D25

H23

DDR_D26

K22

DDR_D27

K21

DDR_D28

G23

DDR_D29

H20

DDR_D30

K20

DDR_D31

K23

DDR_D32

N23

DDR_D33

P21

DDR_D34

T20

DDR_D35

T23

DDR_D36

M20

DDR_D37

P20

DDR_D38

R23

DDR_D39

T22

DDR_D40

V20

DDR_D41

V21

DDR_D42

Y23

DDR_D43

Y22

DDR_D44

T21

DDR_D45

U23

DDR_D46

W23

DDR_D47

Y21

DDR_D48

Y20

DDR_D49

AB22

DDR_D50

AC19

DDR_D51

AA18

DDR_D52

AA23

DDR_D53

AA20

DDR_D54

AB19

DDR_D55

Y18

DDR_D56

AC17

DDR_D57

Y16

DDR_D58

AB14

DDR_D59

AC14

DDR_D60

AC18

DDR_D61

AB18

DDR_D62

AB15

DDR_D63

AC15

M23

R49 39.2_0402_1%R49 39.2_0402_1%

M22

1 2

+1.5V

3

U1A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

PCIE_PTX_C_IRX_P2<19> PCIE_PTX_C_IRX_N2<19>

+1.0VS

PCIE_PTX_C_IRX_P3<20> PCIE_PTX_C_IRX_N3<20>

R46 2K_0402_1%R46 2K_0402_1%

1 2

UMI_C_RXP0 UMI_C_RXN0

UMI_C_RXP1 UMI_C_RXN1

UMI_C_RXP2 UMI_C_RXN2

UMI_C_RXP3 UMI_C_RXN3

+1.5V

WLAN WLAN

+M_VREF

AA1 AA2

Y14

AA12

Y12

AA10

Y10

AB10 AC10

AC7 AB7

+M_VREF

1

C428

2

0.1U_0402_16V4Z

P_GPP_RXP2 P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

P_ZVDD_10

P_UMI_RXP0 P_UMI_RXN0

P_UMI_RXP1 P_UMI_RXN1

P_UMI_RXP2 P_UMI_RXN2

P_UMI_RXP3 P_UMI_RXN3

ONTARIO-2M161000-1.6G_BGA413

1000P_0402_50V7K

1

C172

2

+1.5V

12

PCIE I/F

UMI I/F

R48

1K_0402_1%

R50

1K_0402_1%

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_ZVSS

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

2

UMI_C_TXP[0..3]<14> UMI_C_TXN[0..3]<14>

UMI_C_RXP[0..3]<14> UMI_C_RXN[0..3]<14>

AB6 AC6

AB3 AC3

PCIE_ITX_PRX_P2

Y1

PCIE_ITX_PRX_N2

Y2

PCIE_ITX_PRX_P3

V3

PCIE_ITX_PRX_N3

V4

R47 1.27K_0402_1%R47 1.27K_0402_1%

1 2

AA14

UMI_TXP0

C9 0.1U_0402_16V7KC9 0.1U_0402_16V7K

AB12 AC12

AC11 AB11

AA8 Y8

AB8 AC8

UMI_TXN0

UMI_TXP1 UMI_TXN1

UMI_TXP2 UMI_TXN2

UMI_TXP3 UMI_TXN3

1 2

C10 0.1U_0402_16V7KC10 0.1U_0402_16V7K

1 2

C11 0.1U_0402_16V7KC11 0.1U_0402_16V7K

1 2

C12 0.1U_0402_16V7KC12 0.1U_0402_16V7K

1 2

C13 0.1U_0402_16V7KC13 0.1U_0402_16V7K

1 2

C14 0.1U_0402_16V7KC14 0.1U_0402_16V7K

1 2

C15 0.1U_0402_16V7KC15 0.1U_0402_16V7K

1 2

C16 0.1U_0402_16V7KC16 0.1U_0402_16V7K

1 2

C338 0.1U_0402_16V7KC338 0.1U_0402_16V7K

1 2

C339 0.1U_0402_16V7KC339 0.1U_0402_16V7K

1 2

C340 0.1U_0402_16V7KC340 0.1U_0402_16V7K

1 2

C341 0.1U_0402_16V7KC341 0.1U_0402_16V7K

1 2

UMI_C_TXP0 UMI_C_TXN0

UMI_C_TXP1 UMI_C_TXN1

UMI_C_TXP2 UMI_C_TXN2

UMI_C_TXP3 UMI_C_TXN3

1

PCIE_ITX_C_PRX_P2 <19> PCIE_ITX_C_PRX_N2 <19>

PCIE_ITX_C_PRX_P3 <20> PCIE_ITX_C_PRX_N3 <20>

LANLAN

DDR_EVENT#

DDR_RST#

A A

5

R51 1K_0402_1%R51 1K_0402_1%

R69 1K_0402_1%

@

12

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII,UMI

PCM10 LA6741 M/B SCHEMATIC

6 36Friday, December 03, 2010

1

of

0.1

5

4

3

2

+CPU_CORE

1

+CPU_CORE

1

C39

2

1U_0402_6.3V4Z

1

2

1

C65

2

C76

Deciphered Date

+CPU_CORE

1

2

180P_0402_50V8J

1U_0402_6.3V4Z

C40

ESR:9ohm(MAX)

1

+

C56

2

330U_D2_2.5VY_R9M

1U_0402_6.3V4Z

C66

+1.5V

10U_0805_6.3V6M

1

2

C929

@

+CPU_CORE

10U_0805_6.3V6M

C29

1

2

1U_0402_6.3V4Z

1

@

+

C57

2

330U_D2_2.5VY_R9M

1

C67

2

1U_0402_6.3V4Z

1

C77

2

10U_0805_6.3V6M

1

C930

@

2

1

2

1

C41

2

1

2

1U_0402_6.3V4Z

2

180P_0402_50V8J

1

C30

2

10U_0805_6.3V6M

1U_0402_6.3V4Z

1

C42

2

1U_0402_6.3V4Z

1

C68

2

+1.5V

1

C933

@

2

180P_0402_50V8J

1

C78

2

1

+

C25

C24

2

330U_D2_2.5VY_R9M

+

C26

2

330U_D2_2.5VY_R9M

1

ESR:9ohm(MAX)

10U_0805_6.3V6M

1

C31

10U_0805_6.3V6M

C58

1U_0402_6.3V4Z

C79

C32

2

10U_0805_6.3V6M

1

C43

2

0.1U_0402_16V4Z

+CPU_CORE_NB

1

2

0.1U_0402_16V4Z

1

C69

2

1

C934

@

2

1

C80

2

1U_0402_6.3V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

10U_0805_6.3V6M

1

2

0.1U_0402_16V4Z

C44

+CPU_CORE_NB

180P_0402_50V8J

C59

10U_0805_6.3V6M

1

C70

2

180P_0402_50V8J

1

2

PWR,BYPASS

PCM10 LA6741 M/B SCHEMATIC

1

C33

2

1

C45

2

0.1U_0402_16V4Z

1

C931

@

2

10U_0805_6.3V6M

1

C60

2

1

C71

2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1

C81

2

Compal Electronics, Inc.

C34

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

C46

2

1

C932

@

2

1

C61

2

10U_0805_6.3V6M

0.1U_0402_16V4Z

C72

1

C82

2

0.1U_0402_16V4Z

1

2

1

2

180P_0402_50V8J

1

2

1

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

C35

C47

0.1U_0402_16V4Z

10U_0805_6.3V6M

C62

C73

0.1U_0402_16V4Z

1

C83

2

0.1U_0402_16V4Z

7 36Friday, November 26, 2010

1

2

1

2

1

2

1

2

1

C84

2

0.1

of

+CPU_CORE

D D

+CPU_CORE_NB

10000mA

C C

+1.5V

2000mA

B B

A A

U1C

11000mA

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

G16

VDDIO_MEM_S_1

G19

VDDIO_MEM_S_2

E17

VDDIO_MEM_S_3

J16

VDDIO_MEM_S_4

L16

VDDIO_MEM_S_5

L19

VDDIO_MEM_S_6

N16

VDDIO_MEM_S_7

R16

VDDIO_MEM_S_8

R19

VDDIO_MEM_S_9

W18

VDDIO_MEM_S_10

U16

VDDIO_MEM_S_11

ONTARIO-2M161000-1.6G_BGA413

U1D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

ONTARIO-2M161000-1.6G_BGA413

5

GND

CPU CORE

GPU AND NB CORE

DDR3

DAC

POWER

VSSBG_DAC

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7

DIS PLL

VDDPL_10

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DP Phy/IO

VDD_33

0.1U_0402_16V4Z

2000mA

U8 W8 U6 U9 W6 T7 V7

150mA

W9

180P_0402_50V8J

200mA

U11

C936

U13 W13 V12 T12

180P_0402_50V8J

500mA

A4

C167

N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

TSense/PLL/DP/PCIE/IO

VDD_18_DAC

PCIE/IO/DDR3 Phy

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

180P_0402_50V8J

1

@

2

C939

C938

@

180P_0402_50V8J

1

C38

@

2

5500mA

0.1U_0402_16V4Z

1

C937

@

2

+3VS

1

C54 1U_0402_6.3V4ZC54 1U_0402_6.3V4Z

2

1U_0402_6.3V4Z

1

C426

2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1

C28

2

1U_0402_6.3V4Z

1

C37

2

0.1U_0402_16V4Z

1

C52

C53

2

0.1U_0402_16V4Z

1

2

4

1

C20

2

1

C27

2

+1.0VS_VDDPL

1

C36

2

1U_0402_6.3V4Z

1

C50

2

1U_0402_6.3V4Z

1

C19

C21

2

1U_0402_6.3V4Z

+1.8VS_DAC

220 DCR:0.04

L2

1 2

1

FBMA-L11-201209-221LMA30T_0805

10U_0805_6.3V6M

2

220 DCR:0.04

L3

1 2

1

FBMA-L11-201209-221LMA30T_0805

10U_0805_6.3V6M

2

10U_0805_6.3V6M

1

C51

2

1U_0402_6.3V4Z

220U_D2_4VM_R15

330U_D2_2.5VY_R9M

1

C17

2

10U_0805_6.3V6M

次次次次

_3A

次次次次

_3A

1

C48

2

+1.0VS

1

+

C63

2

+1.5V

+1.8VS_VDD

1

2

次次次次

+1.0VS_VDD

C49

C74

120

次次次次

_5A

+1.8VS

次次次次

DCR:0.02

L1

1 2

FBMA-L11-201209-121LMA50

1

C18

1U_0402_6.3V4Z

2

+1.8VS

@+C23

@

C23

+1.8VS

1

+

2

1

+

C22

C22 330U_2.5V_M

330U_2.5V_M

2

330U_D2_2.5VY_R9M

ESR:17ohm(MAX)

+1.0VS

120

次次次次

_5A

DCR:0.02

L4

1 2

FBMA-L11-201209-121LMA50

1

10U_0805_6.3V6M

2

+1.0VS

次次次次

+CPU_CORE_NB

C55

10U_0805_6.3V6M

ESR:9ohm(MAX)

1

C64

@

10U_0805_6.3V6M

2

1U_0402_6.3V4Z

+CPU_CORE_NB

ESR:9ohm(MAX)

1

+

2

1

C75

@C75

@

10U_0805_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/06

Compal Secret Data

5

+1.5V

12

R53

1K_0402_1%

12

D D

+V_DDR3_DIMM_REF

R54

1K_0402_1%

DDR_DQS#[0..7]<6,9>

DDR_D[0..63]<6,9>

DDR_DM[0..7]<6,9>

DDR_DQS[0..7]<6,9>

DDR_MA[0..15]<6,9>

Put it between DDR3 +1.5VS shape and GND shape

0.1U_0402_16V4Z

1

C330

@

2

0.1U_0402_16V4Z

Layout Note: Place near JDDR1

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0603_6.3V6M

1

C95

2

10U_0603_6.3V6M

10U_0805_6.3V6M

1

2

10U_0603_6.3V6M

1

C96

2

0.1U_0402_16V4Z

1

C110

2

10U_0603_6.3V6M

1

C94

2

1U_0402_6.3V6K

1

C108

2

1

2

C109

10U_0805_6.3V6M

C105

+1.5V

10U_0603_6.3V6M

1

C92

2

+0.75VS

1U_0402_6.3V6K

1

C106

2

C93

10U_0603_6.3V6M

1

C107

2

1U_0402_6.3V6K

C C

C91

10U_0603_6.3V6M

Layout Note: Place near JDDR1.203 & JDDR1.204

B B

1U_0402_6.3V6K

A A

1

C113

@

2

1

2

0.1U_0402_16V4Z

1

C97

2

C293

@C293

@

0.01U_0402_16V7K

1

C98

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

C99

2

4

C328

@C328

@

0.01U_0402_16V7K

1

C100

2

+V_DDR3_DIMM_REF

+1.5V

1

C329

0.01U_0402_16V7K

2

10U_0603_6.3V6M

1

C101

2

10U_0603_6.3V6M

R52 0_0402_5%R52 0_0402_5%

1 2

1000P_0402_50V7K

@C329

@

change two 100U to one 220U 06/21

1

+

C87

C102

C87

@

220U_D2_4VM_R15

2

3

1

C86

C85

2

+3VS

C103

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

1

2

DDR_CKE0<6,9>

DDR_BS2<6,9>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_BS0<6,9>

DDR_WE#<6,9> DDR_CAS#<6,9>

DDR_A_CS1#<6>

1

2

+1.5V +1.5V

+VREF_DQA

DDR_D0 DDR_D1

DDR_DM0

DDR_D2 DDR_D3

DDR_D8 DDR_D9

DDR_DQS#1 DDR_DQS1

DDR_D10 DDR_D11

DDR_D16 DDR_D17

DDR_DQS#2 DDR_DQS2

DDR_D18 DDR_D19

DDR_D24 DDR_D25

DDR_DM3

DDR_D26 DDR_D27

DDR_MA12 DDR_MA9

DDR_MA8 DDR_MA5

DDR_MA3 DDR_MA1

DDR_MA10

DDR_MA13

DDR_D32 DDR_D33

DDR_DQS#4 DDR_DQS4

DDR_D34 DDR_D35

DDR_D40 DDR_D41

DDR_DM5

DDR_D42 DDR_D43

DDR_D48 DDR_D49

DDR_DQS#6 DDR_DQS6

DDR_D50 DDR_D51

DDR_D56 DDR_D57

DDR_DM7

DDR_D58 DDR_D59

R56 10K_0402_5%R56 10K_0402_5%

1 2

1

C104

0.1U_0402_16V4Z

2

12

R57

R57 10K_0402_5%

10K_0402_5%

JDDR1

CONN@JDDR1

CONN@

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

5.2mm

205

GND1

207

BOSS1

LCN_DAN06-K4526-0102

2

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

1

2

DDR_D4

4

DDR_D5

6 8

DDR_DQS#0

10

DDR_DQS0

12 14

DDR_D6

16

DDR_D7

18 20

DDR_D12

22

DDR_D13

24 26

DDR_DM1

28 30 32

DDR_D14

34

DDR_D15

36 38

DDR_D20

40

DDR_D21

42 44

DDR_DM2

46 48

DDR_D22

50

DDR_D23

52 54

DDR_D28

56

DDR_D29

58 60

DDR_DQS#3

62

DDR_DQS3

64 66

DDR_D30

68

DDR_D31

70 72

74 76

DDR_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_MA14

DDR_MA11 DDR_MA7

DDR_MA6 DDR_MA4

DDR_MA2 DDR_MA0

+DDR_VREF_CA_DIMMA

DDR_D36 DDR_D37

DDR_DM4

DDR_D38 DDR_D39

DDR_D44 DDR_D45

DDR_DQS#5 DDR_DQS5

DDR_D46 DDR_D47

DDR_D52 DDR_D53

DDR_DM6

DDR_D54 DDR_D55

DDR_D60 DDR_D61

DDR_DQS#7 DDR_DQS7

DDR_D62 DDR_D63

DDR_RST# <6,9>

DDR_CKE1 <6,9>

R55 0_0402_5%R55 0_0402_5%

+0.75VS

Need close to JDDR1

@

C264

1 2

33P_0402_50V8J

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_BS1 <6,9> DDR_RAS# <6,9>

DDR_A_CS0# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

1 2

1000P_0402_50V7K

DDR_EVENT# <6,9> SMB_FCH_DA0 <9,15> SMB_FCH_CK0 <9,15>

1

C89

2

DDR3 SO-DIMM A

DDR_CKE1

+V_DDR3_DIMM_REF

1

C90

0.1U_0402_16V4Z

2

Standard Type

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/06 2010/02/04

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM A

PCM10 LA6741 M/B SCHEMATIC

8 36Friday, December 03, 2010

1

0.1

of

5

DDR_DQS#[0..7]<6,8>

DDR_D[0..63]<6,8>

D D

Layout Note: Place near JP3

C C

C117

10U_0603_6.3V6M

B B

1U_0402_6.3V6K

A A

+1.5V

10U_0603_6.3V6M

1

C118

2

10U_0603_6.3V6M

Layout Note: Place near JP3.203 & JP3.204

+0.75VS

1U_0402_6.3V6K

1

C130

C129

2

1

C120

C119

2

1

C131

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C132

2

C121

1

2

10U_0603_6.3V6M

1

C122

2

C133

C133 10U_0805_6.3V6M

10U_0805_6.3V6M

DDR_DM[0..7]<6,8>

DDR_DQS[0..7]<6,8>

DDR_MA[0..15]<6,8>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

C123

1

C124

2

0.1U_0402_16V4Z

1

C125

2

1

C126

2

0.1U_0402_16V4Z

4

10U_0603_6.3V6M

1

C127

2

Compal common design

ADM CRB

+V_DDR3_DIMM_REF

change two 100U to one 220U 06/21

1

C128

2

10U_0603_6.3V6M

2

SA0 SA1

0 1

1 0

+

C114

220U_D2_4VM_R15

2

3

R58 0_0402_5%R58 0_0402_5%

1 2

1

C111

C112

1000P_0402_50V7K

Need close to JDDR2

@

1 2

2.2U_0603_6.3V6K

C112

2

C288

DDR_CKE0

33P_0402_50V8J

@

R139 10K_0402_5%

1 2

+3VS

1

C134

2

0.1U_0402_16V4Z

1

2

DDR_CKE0<6,8>

DDR_BS2<6,8>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_BS0<6,8>

DDR_WE#<6,8> DDR_CAS#<6,8>

DDR_B_CS1#<6>

1

2

VREF_DQB

C135

0.1U_0402_16V4Z

DDR_D0 DDR_D1

DDR_DM0

DDR_D2 DDR_D3

DDR_D8 DDR_D9

DDR_DQS#1 DDR_DQS1

DDR_D10 DDR_D11

DDR_D16 DDR_D17

DDR_DQS#2 DDR_DQS2

DDR_D19

DDR_D24 DDR_D25

DDR_DM3

DDR_D26 DDR_D27

DDR_MA12 DDR_MA9

DDR_MA8 DDR_MA5

DDR_MA3 DDR_MA1

DDR_MA10

DDR_MA13

DDR_D32 DDR_D33

DDR_DQS#4 DDR_DQS4

DDR_D34 DDR_D35

DDR_D40 DDR_D41

DDR_DM5

DDR_D42 DDR_D43

DDR_D48 DDR_D49

DDR_DQS#6 DDR_DQS6

DDR_D50 DDR_D51

DDR_D56 DDR_D57

DDR_DM7

DDR_D58 DDR_D59

R60 10K_0402_5%R60 10K_0402_5%

1 2

R61 10K_0402_5%@R61 10K_0402_5%@

1 2

R203 10K_0402_5%R203 10K_0402_5%

2

+1.5V +1.5V

JDDR2

CONN@JDDR2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

5.2mm

205

G1

LCN_DAN06-K4526-0101

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA SCL

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

DDR_D4 DDR_D5

DDR_DQS#0 DDR_DQS0

DDR_D6 DDR_D7

DDR_D12 DDR_D13

DDR_DM1

DDR_D14 DDR_D15

DDR_D20 DDR_D21

DDR_DM2

DDR_D22 DDR_D23DDR_D18

DDR_D28 DDR_D29

DDR_DQS#3 DDR_DQS3

DDR_D30 DDR_D31

DDR_MA15 DDR_MA14

DDR_MA11 DDR_MA7

DDR_MA6 DDR_MA4

DDR_MA2 DDR_MA0

DDR_VREF_CA_DIMMB

DDR_D36 DDR_D37

DDR_DM4

DDR_D38 DDR_D39

DDR_D44 DDR_D45

DDR_DQS#5 DDR_DQS5

DDR_D46 DDR_D47

DDR_D52 DDR_D53

DDR_DM6

DDR_D54 DDR_D55

DDR_D60 DDR_D61

DDR_DQS#7 DDR_DQS7

DDR_D62 DDR_D63

+0.75VS

1

DDR_RST# <6,8>

DDR_CKE1 <6,8>

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_BS1 <6,8> DDR_RAS# <6,8>

DDR_B_CS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

R59 0_0402_5%R59 0_0402_5%

1 2

1000P_0402_50V7K

DDR_EVENT# <6,8>

SMB_FCH_DA0 <8,15> SMB_FCH_CK0 <8,15>

C115

1

2

DDR3 SO-DIMM B

+V_DDR3_DIMM_REF

1

C116

0.1U_0402_16V4Z

2

REV Type

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM B

PCM10 LA6741 M/B SCHEMATIC

9 36Friday, December 03, 2010

1

0.1

of

5

D D

HDMI_CLK-<5> HDMI_CLK+<5>

HDMI_TX2+<5> HDMI_TX2-<5>

HDMI_TX1+<5> HDMI_TX1-<5>

HDMI_TX0+<5> HDMI_TX0-<5>

C C

B B

A A

HDMI_CLKHDMI_CLK+

HDMI_TX2+ HDMI_TX2- HDMI_C_TX2-

HDMI_TX1+ HDMI_TX1- HDMI_C_TX1-

HDMI_TX0+ HDMI_TX0-

HDMI_C_CLK+

HDMI_C_CLK-

HDMI_C_TX0+

HDMI_C_TX0-

HDMI_C_TX1+

HDMI_C_TX1-

HDMI_C_TX2+

HDMI_C_TX2-

HDMI_C_CLK+ HDMI_C_CLKHDMI_C_TX0+ HDMI_C_TX0HDMI_C_TX1+ HDMI_C_TX1HDMI_C_TX2+ HDMI_C_TX2-

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

NEAR CONNECT

R80 499_0402_1%R80 499_0402_1%

R81 499_0402_1%R81 499_0402_1%

R82 499_0402_1%R82 499_0402_1%

R83 499_0402_1%R83 499_0402_1%

R85 499_0402_1%R85 499_0402_1%

R87 499_0402_1%R87 499_0402_1%

R89 499_0402_1%R89 499_0402_1%

R92 499_0402_1%R92 499_0402_1%

C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K

C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K

C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K C141 0.1U_0402_16V7KC141 0.1U_0402_16V7K

C142 0.1U_0402_16V7KC142 0.1U_0402_16V7K C143 0.1U_0402_16V7KC143 0.1U_0402_16V7K

L5

4

1

WCM-2012-670T

L6

4

1

WCM-2012-670T

L7

4

1

WCM-2012-670T

L8

4

1

WCM-2012-670T

R65 0_0402_5%@ R65 0_0402_5%@

1 2

R66 0_0402_5%@ R66 0_0402_5%@

1 2

R67 0_0402_5%@ R67 0_0402_5%@

1 2

R68 0_0402_5%@ R68 0_0402_5%@

1 2

R71 0_0402_5%@ R71 0_0402_5%@

1 2

R72 0_0402_5%@ R72 0_0402_5%@

1 2

R73 0_0402_5%@ R73 0_0402_5%@

1 2

R75 0_0402_5%@ R75 0_0402_5%@

1 2

1 2 1 2

3

2

3

2

3

2

3

2

3

2

3

2

3

2

3

2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

4

HDMI_C_CLKHDMI_C_CLK+

HDMI_C_TX2+

HDMI_C_TX1+

HDMI_C_TX0+ HDMI_C_TX0-

HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN

@

13

D

S

2N7002W-T/R7_SOT323-3

@

2

G

Q10

0_0402_5%

R90

R88

0_0402_5%

3

R62 0_0402_5%R62 0_0402_5%

+3VS

HDMI_DAT<5>

HDMI_SCL<5>

C165

0.1U_0402_16V4Z

12

+3VS

12

+5VS

1

@C165

@

2

1 2

5

4

2N7002DW-T/R7_SOT363-6

+5VS

12

R98

0_0402_5%

1

5

P

4

OE#

A2Y

G

U7

@U7

@

74AHCT1G125GW_SOT353-5

3

Q2B

+3VS

2

3

12

R84

2.2K_0402_5%

+5VS

2N7002DW-T/R7_SOT363-6

HDMIDAT_R

61

Q2A

R91

@R91

@

0_0402_5%

R93

@R93

@

0_0402_5%

@R84

@

12

100K_0402_5%

R119

D5

D5 PMEG2010ET SOT23

PMEG2010ET SOT23

3

2

R1559 470_0402_1%@R1559 470_0402_1%@

R1560 470_0402_1%@R1560 470_0402_1%@

R1561 470_0402_1%@R1561 470_0402_1%@

R1562 470_0402_1%@R1562 470_0402_1%@

12

HDMICLK_R

12

HDMI_DET

12

100K_0402_5%

R1192

@

HDMI_HPD <5>

1

+5VS_HDMI

2.2K_0402_5%

HDMIDAT_R HDMICLK_R

1 2

2

+VCC_HDMI

R78

1

C166

0.1U_0402_16V4Z

2

1.1A_6VDC_FUSE

12

R79

2.2K_0402_5%

@C166

@

+5VS

D11 BAT54S-7-F_SOT23-3@D11 BAT54S-7-F_SOT23-3@

F1

2

3

1

HDMI_DET

21

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

+5VS_HDMI

HDMI_DET

1

C144

0.1U_0402_16V4Z

2

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR019M23DZL

CONN@JHDMI

CONN@

GND GND GND GND

1

20 21 22 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/06

Compal Secret Data

Deciphered Date

2

2010/02/04

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics,Ltd.

HDMI Conn

PCM10 LA6741 M/B SCHEMATIC

10 36Friday, December 03, 2010

1

of

0.1

A

B

C

D

E

CRT Connector

D8

D7

+3VS

C146

5P_0402_50V8C

CRT_VSYNC_1

D7

@

DAN217_SC59

1

2

1 1

L11

CRT_R<5>

CRT_G<5>

CRT_B<5>

2 2

C153 0.1U_0402_16V4ZC153 0.1U_0402_16V4Z

CRT_HSYNC<5>

CRT_VSYNC<5>

150_0402_1%

R94

1 2

C158 0.1U_0402_16V4ZC158 0.1U_0402_16V4Z

12

1 2

150_0402_1%

R95

12

150_0402_1%

R96

+CRT_VCC

1

5

U4

P

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

+CRT_VCC

5P_0402_50V8C

C149

4

1

2

CRT_HSYNC_0

5

P

A2Y

G

3

5P_0402_50V8C

1

C150

2

R97 10K_0402_5%R97 10K_0402_5%

R99 27_0402_5%R99 27_0402_5%

1

U5

CRT_VSYNC_0

4

OE#

74AHCT1G125GW_SOT353-5

1 2

FBMA-L10-160808-600LMT_2P

L14

1 2

FBMA-L10-160808-600LMT_2P

L12

1 2

FBMA-L10-160808-600LMT_2P

5P_0402_50V8C

1

C151

2

12

CRT_HSYNC_1

1 2

R100 27_0402_5%R100 27_0402_5%

D8

@

DAN217_SC59

1

2

3

5P_0402_50V8C

C147

1

2

1

2

3

5P_0402_50V8C

C148

10P_0402_50V8J

D9

@

DAN217_SC59

1

2

3

CRT_R_2

CRT_G_2

CRT_B_2

1

2

1

C155

2

+5VS

1

2

PMEG2010ET SOT23

C156

10P_0402_50V8J

+CRT_VCC

1

2

1

100P_0402_50V8J

68P_0402_50V8K

+R_CRT_VCC

W=40mils

1

C154

2

F2

W=40mils

21

1.1A_6VDC_FUSE

DAT_R

R254 33_0402_5%R254 33_0402_5%

CLK_R

R294 33_0402_5%R294 33_0402_5%

1

C157

68P_0402_50V8K

2

JCRT

CONN@

JCRT

CONN@

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070546FR015S297ZR

1 2

16

G

17

G

1

C145

0.1U_0402_16V4Z

2

NEED CHECK SYMBOL 06/02

DAT

CLK

D10

3

2

C152

3 3

+CRT_VCC

+3VS

R102

2

6 1

Q3A

3

Q3B

R102

1 2

0_0402_5%

5

4

12

R106

R105

4.7K_0402_5%

CRT_DDC_DATA <5>

CRT_DDC_CLK <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/05/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

PCM10 LA6741 M/B SCHEMATIC

11 36Friday, December 03, 2010

E

0.1

of

12

R104

R103

4.7K_0402_5%

DAT

CLK

4 4

A

R104

4.7K_0402_5%

2N7002DW-T/R7_SOT363-6

1 2

R86 0_0402_5%

@

2N7002DW-T/R7_SOT363-6

1 2

R101 0_0402_5%

@

B