Compal LA-6732P Schematics

5

D D

4

3

2

1

Compal Confidential

C C

PBL11

LA-6732P

B B

SchematicREV 0.4

Intel Sandy Bridge/Cougar Point

Discrete

2010-11-01 Rev 0.4

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

Monday, November 01, 2010

Monday, November 01, 2010

Monday, November 01, 2010

1

1 59

1 59

1 59

0.1

0.1

0.1

5

4

3

2

1

Compal Confidential
Model Name : PBL11
File Name : LA-6732P

PEG(DIS)

PCI-E 2.0x16 5GT/s PER LANE100MHz

133MHz

Mobile

Sandy Bridge

CK505

Clock Generator
ICS9LRS

Page 26

Fan Control

page 5

CPU Dual Core

D D

VGA (DDR3)

Socket-rPGA989

37.5mm*37.5mm

page 5,6,7,8,9,10,11

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 12,13

NVIDIA N12M GE, 128bit with 512MB/1GB

NVIDIA N12P GV, 128bit with 512MB/1GB

page 14,15,16,17,18,19,20,21,22,23,24,25

DIS

page 27

OPT

CRT

HDMI Conn.

page 29

C C

port 3

USB 3.0 conn x1

PCIe port 2

page 48

PCIeMini Card
WLAN & BT 2.0

DIS

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

port 2 port 1

USB port 13

PCIe port 1

page 41

page 28

LCD Conn.

RTL8105E 10/100M
RTL8111E 1G

PCIe port 3

page 40

OPT

100MHz

RJ45

page 40

B B

USB&Audio/B

page 41

Touch Pad

page 47

DMI X4

Intel
Cougar Point-M

989pin FCBGA

page 30,31,32,33

,34,35,36,37,38

LPC BUS

33MHz

ENE KB930

page 44

FDI

Int.KBD

page 44

USB

USB/B Right

USB port 0,1

SATA port 0

5V 1.5GHz(150MB/s)

SATA port 2

5V 1.5GHz(150MB/s)

page 41

SATA HDD0

SATA ODD

SPI ROM

HD Audio

Int. Camera RTS5138 3IN1

USB port 10

page 28

page 39

page 39

page 46

3.3V 24.576MHz/48Mhz

USB port 11

HDA Codec

ALC259

page 43

MIC

Int.

page 43

MIC CONN

page 41

page 42

HP CONN

page 41

SPK CONN

page 43

Power/B

page 47

BIOS ROM

Touch Pad/B

page 47

page 44

CPU XDP

RTC CKT.

page 29

A A

DC/DC Interface CKT.

page 49

Security Classification

Security Classification

Power Circuit DC/DC

page 50,51,52,53,54,55,56,57,58,59

5

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

page 5

PCH XDP

page 29

2 59Monday, November 01, 2010

2 59Monday, November 01, 2010

2 59Monday, November 01, 2010

0.1

0.1

0.1

B+

5

Ipeak=5A, Imax=3.5A, Iocp min=7.9

4

DESIGN CURRENT 5A

3

+5VALW

2

1

SUSP

N-CHANNEL

SI4800

DESIGN CURRENT 4A

+5VS

SUSP#

D D

SY8033BDBC

DESIGN CURRENT 2A

+1.8VS

RT8205

Ipeak=5A, Imax=3.5A, Iocp min=7.7

WOL_EN#

P-CHANNEL

AO-3413

SUSP

N-CHANNEL

SI4800

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

C C

P-CHANNEL

AO-3413

VR_ON

ISL95831CRZ

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

VGA_ENVDD

DESIGN CURRENT 1.5A

BT_PWR#

DESIGN CURRENT 180mA

PCIE_OK

DESIGN CURRENT 100mA

DESIGN CURRENT 52A

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+BT_VCC

+3VS_DELAY

+CPU_CORE

DESIGN CURRENT 30A

+GFX_CORE

DGPU_PWR_EN / SUSP#

APW7138

DESIGN CURRENT 26A

+VGA_CORE

SUSP#

B B

G5603RU1U

SYSON

Ipeak=18A, Imax=12.6A, Iocp min=19.8

Ipeak=15A, Imax=10.5A, Iocp min=16.5

DESIGN CURRENT 18A

DESIGN CURRENT 15A

+1.05VS_VCCP

+1.5V

+1.5V_CPU

G5603RU1U

CPU1.5V_S3_GATE / SUSP

APL5336

DESIGN CURRENT 2A

SUSP

SI4856

DESIGN CURRENT 12A

SUSP#

Issued Date

Issued Date

Issued Date

DESIGN CURRENT 6A

A A

G5603RU1U

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

+0.75VS

+1.5VS

+VCCSA

Compal Secret Data

Compal Secret Data

Security Classification

Security Classification

Security Classification

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

3 59Monday, November 01, 2010

3 59Monday, November 01, 2010

3 59Monday, November 01, 2010

Power Map

Power Map

Power Map

of

of

of

0.1

0.1

0.1

3 59Monday, November 01, 2010

3 59Monday, November 01, 2010

3 59Monday, November 01, 2010

1

0.1

0.1

0.1

of

of

of

5

4

3

2

1

Voltage Rails

S1

Power Plane Description

VIN

Adapter power supply (19V)

S3 S5

N/A N/A N/A

BATT+ Battery power supply (12.6V) N/A N/A N/A

B+

D D

+CPU_CORE

+VGA_CORE

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

ON

ON

OFF

OFF

N/AN/AN/A

OFF

OFF

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator

+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

+1.05VS_VCCP

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH

+1.5V

+1.5VS

+1.5VP to +1.5V power rail for DDRIII ON ON OFF

+1.5V to +1.5VS switched power rail

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFF OFF

+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF

+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

+3VALW +3VALW always on power rail

+3VALW_EC +3VALW always to KBC ON ON ON*

+3V_LAN

+3VALW_PCH

C C

+3VS

+5VALW

+5VALW_PCH

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

OFF

ON

ON ON*

ON

ON ON

ON ON

OFF

ON

ON

ON ON*

ON ON

OFF

Bom configu(CRT@/HDMI@/N11M@/N12M@/12GE@/12GV@/8105E@/8111E@/DA8@/DAZ@/11GS@/8PCS@/45@/DIS@/OPT@)

ON*

ON*

OFF

ON*

+5VS +5VALW to +5VS switched power rail OFFON OFF

+VSB +VSBP to +VSB always on power rail for sequence control ON ON*

+RTCVCC RTC power

ON

ON

ONON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Device

SIGNAL

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

EC SM Bus2 address

+3VS EC KB930+3VL EC KB930

0001 011x b

+3VS GPU Thermal Sensor

HIGHHIGHHIGH

HIGH

HIGH

Device

PCH+3VALW

ON

ON

ON ON

ON

ON

ON

LOW

ON

ON

ON

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

AddressAddress

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

B B

S4 (Suspend to Disk)

S5 (Soft OFF)

EC SM Bus1 address

Power Power

+3VL Smart Battery

BOM configu table

SKU Description Bom config

1

2

3

OPT D 10-100 N12MGE 1G

4

OPT D GIGA N12PGE 2G

5

OPT Q GIGA N12PGE 2G

6

7

OPT D GIGA N12PGV 512

8

OPT D GIGA N12PGV 1G

DA8@/DIS@/HDMI@/8111E@/12GE@/8PCS@/SAM1G8@/CRT@

DA8@/OPT@/HDMI@/8105E@/N12M@/SAM512@

DA8@/OPT@/HDMI@/8105E@/N12M@/SAM1G@

DA8@/DIS@/HDMI@/8111E@/12GE@/8PCS@/SAM2G@/CRT@

DA8@/OPT@/HDMI@/8111E@/12GE@/8PCS@/SAM2G@

DA8@/OPT@/HDMI@/8111E@/12GV@/SAM512@

DA8@/DIS@/HDMI@/8111E@/12GV@/SAM1G4@/CRT@

X76 AND VGA configu table

SKU Description config

1

46196930L01

ZZZ

SAM1G8@ZZZ

2

3

4

5

6

7

8

N12M

N12M

12GV

12GV

46196930L07

46196930L03

46196930L04

46196930L08

46196930L09

46196930L05

46196930L06

Hynix 1G

SAM 1G

Hynix 1G

SAM 1G

12GV1 Hynix 1G

12GV1

X7626530L02

X7626530L01

X7626530L02

X7626530L01

12GV is 12GV1, pay ateention next phase

12GE

12GE

12GE

12GE

SAM1G8@ UV1

SAM 1G

SAM 1G

ZZZ

SAM512@ZZZ

SAM512@

SAM 512

SAM 512

ZZZ

SAM1G4@ZZZ

SAM1G4@

SAM 1G

SAM 1G

ZZZ

SAM2G@ZZZ

SAM2G@

SAM 2G

SAM 2G

ZZZ

SAM2G@ZZZ

SAM2G@

SAM 2G

SAM 2G

ZZZ

SAM512@ZZZ

SAM512@

SAM 512

SAM 512

ZZZ

SAM1G4@ZZZ

SAM1G4@

SAM 1G

SAM 1G

SAM 1G

Hynix 1G

SAM 1G

Hynix 2G

SAM 2G

ZZZ

HY1G8@ZZZ

HY1G8@

Hynix 1G

Hynix 1G

ZZZ

HY512@ZZZ

HY512@

Hynix 512

Hynix 512

ZZZ

HY1G4@ZZZ

HY1G4@

Hynix 1G

Hynix 1G

ZZZ

HY2G@ZZZ

HY2G@

Hynix 2G

Hynix 2G

ZZZ

HY2G@ZZZ

HY2G@

Hynix 2G

Hynix 2G

ZZZ

HY512@ZZZ

HY512@

Hynix 512

Hynix 512

ZZZ

HY1G4@ZZZ

HY1G4@

Hynix 1G

Hynix 1G

X7626530L06

X7626251L01

X7626530L05

X7626530L07

X7626530L04

X7626530L03

12GE@UV1

12GE@

OPT D GIGA N12PGE 1G

N12P-GE

N12P-GE

UV1

N12M@UV1

N12M@

OPT D 10-100N12MGE 512

N12M-GE2

N12M-GE2

UV1

N12M@UV1

N12M@

OPT D 10-100N12MGE 1G

N12M-GE2

N12M-GE2

UV1

12GE@UV1

12GE@

OPT D GIGA N12PGE 2G

N12P-GE

N12P-GE

UV1

12GE@UV1

12GE@

OPT Q GIGA N12PGE 2G

N12P-GE

N12P-GE

UV1

12GV@UV1

12GV@

OPT D GIGAN12PGV 512

N12P-GV

N12P-GV

UV1

12GV@UV1

12GV@

OPT D GIGA N12PGV 1G

N12P-GV

N12P-GV

46196930L07OPT D GIGA N12PGE 1G

46196930L03OPT D 10-100 N12MGE 512

46196930L04

46196930L08

46196930L09

46196930L05

46196930L06

PCH SM Bus address

Power

Device

PCH

A A

+3VALW

+3VS

+3VS

+3VS

+3VS

Clock Generator

DDR DIMMA

DDR DIMMB

Slot#1--WLAN

5

Address

1101 001x b

1001 000x b

1001 010x b

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

4 59Monday, November 01, 2010

4 59Monday, November 01, 2010

4 59Monday, November 01, 2010

0.1

0.1

0.1

5

D D

H_PROCHOT#45

H_THERMTRIP#35

4

JCPU1B

JCPU1B

AN34

AL33

AN33

AL32

AN32

C26

SNB_IVB#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

H_SNB_IVB#34

TP_SKTOCC#

T1PAD T1PAD

R58

R58

R14

R14

H_CATERR#

H_PECI

H_PROCHOT#_R

56_0402_5%

56_0402_5%

H_THERMTRIP#_R

0_0402_5%

0_0402_5%

T5 PADT5 PAD

H_PECI35,45

1 2

1 2

3

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

CLK_CPU_DMI_R

A28

CLK_CPU_DMI#_R

A27

A16
A15

H_DRAMRST#

R8

SM_RCOMP_0

AK1

SM_RCOMP_1

A5

SM_RCOMP_2

A4

R126 1K_0402_5%R126 1K_0402_5%

12
12

R115 1K_0402_5%R115 1K_0402_5%

+1.05VS_VCCP

H_DRAMRST# 7

RC42 140_0402_1%RC42 140_0402_1%
RC43 25.5_0402_1%RC43 25.5_0402_1%
RC45 200_0402_1%RC45 200_0402_1%

from DDR

2

R138 0_0402_5%R138 0_0402_5%

1 2
1 2

R139 0_0402_5%R139 0_0402_5%

R109 0_0402_5%@R109 0_0402_5%@

1 2
1 2

R128 0_0402_5%@R128 0_0402_5%@

12
12
12

CLK_CPU_DMI 31
CLK_CPU_DMI# 31

CLK_CPU_BCLK 26
CLK_CPU_BCLK# 26

eDP

DDR3 Compensation Signals
Layout Note:Please these
resistors near Processor

1

Terminate DPLL_REF_SSCLK to
GND and PLL_REF_SSCLK# to VCCP
on Processor if motherboard
only supports external
graphics.

PRDY#
PREQ#

TCK

+1.05VS_VCCP

C C

Follow DG 0.71

DRAMPWROK32

B B

Processor Pullups

R47 62_0402_5%R47 62_0402_5%

R50 10K_0402_5%R50 10K_0402_5%

PWROK32

12

12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

CHANG TO OPEN DRAIN MOS--0612

1

2

C85

C85

R104

R104

0_0402_5%

0_0402_5%

H_PROCHOT#_R

H_PWRGOOD_R

C379

C379

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

EMI DEMAND

+3VALW

1

2

1

B

2

A

SUSP49,55

U5

U5

5

74AHC1G08DCKR_SC70-5

74AHC1G08DCKR_SC70-5

P

PM_SYS_PWRGD_BUF

4

O

G

3

SUSP

2

G

G

H_PWRGOOD35

+1.5V_CPU_VDDQ

12

@

@

R110

R110
39_0402_5%

39_0402_5%

13

D

D

@

@

Q5

Q5
2N7002_SOT23

2N7002_SOT23

S

S

H_PM_SYNC32

12

R81

R81
200_0402_5%

200_0402_5%

1 2

R79 130_0402_5%R79 130_0402_5%

Buffered reset to CPU

+3VS

1

C84

C84

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

5

U3

U3

1

P

A A

PLT_RST#34,40,41,45,48

PLT_RST#

NC

2

A

5

BUFO_CPU_RST# BUF_CPU_RST#

4

Y

G

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

3

+1.05VS_VCCP

12

R64

R64
75_0402_5%

75_0402_5%

R72

R72

43_0402_1%

43_0402_1%

1 2

12

@

@

R73

R73
0_0402_5%

0_0402_5%

PBTN_OUT#32,45

CFG010

CLK_CPU_ITP31

CLK_CPU_ITP#31

4

H_PM_SYNC_R

1 2

R15 0_0402_5%R15 0_0402_5%

H_PWRGOOD_R

1 2

R16 0_0402_5%R16 0_0402_5%

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

XDP Connector

+1.05VS_VCCP

0.1U_0402_10V6K

0.1U_0402_10V6K

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

XDP_PREQ#
XDP_PRDY#

H_PWRGOOD XDP_CPU_HOOK0

C8

C8

@

@

R34 1K_0402_5%@ R34 1K_0402_5%@

1 2

R141 0_0402_5%@R141 0_0402_5%@

1 2

R36 1K_0402_5%@ R36 1K_0402_5%@

1 2

R142 0_0402_5%@R142 0_0402_5%@

1 2

1 2

R40 1K_0402_5%@R40 1K_0402_5%@

1

2

XDP_CPU_HOOK1PBTN_OUT#
XDP_CPU_HOOK2CFG0
XDP_CPU_HOOK3PWROK

XDP_CPU_HOOK6PLT_RST#
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

JTAG & BPM

JTAG & BPM

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

ACES_87152-26051

ACES_87152-26051

TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

JXDP

@ JXDP

@

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

27

25

G1

28

26

G2

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

AP27

AR26
AR27
AP30

AR28

TDI

AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

Compal Secret Data

Compal Secret Data

Compal Secret Data

XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

EN_DFAN145

Deciphered Date

Deciphered Date

Deciphered Date

XDP_PRDY#_R

AP29

R1466 0_0402_5%@R1466 0_0402_5%@
R1467 0_0402_5%@R1467 0_0402_5%@

R1468 0_0402_5%@R1468 0_0402_5%@
R1469 0_0402_5%@R1469 0_0402_5%@
R1470 0_0402_5%@R1470 0_0402_5%@

R1471 0_0402_5%@R1471 0_0402_5%@
R1472 0_0402_5%@R1472 0_0402_5%@

R1465 0_0402_5%@R1465 0_0402_5%@

R1458 0_0402_5%@R1458 0_0402_5%@
R1457 0_0402_5%@R1457 0_0402_5%@
R1460 0_0402_5%@R1460 0_0402_5%@
R1459 0_0402_5%@R1459 0_0402_5%@
R1461 0_0402_5%@R1461 0_0402_5%@
R1462 0_0402_5%@R1462 0_0402_5%@
R1463 0_0402_5%@R1463 0_0402_5%@
R1464 0_0402_5%@R1464 0_0402_5%@

+FAN1

10mil

1 2
1 2

1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

Close CPU side

+5VS

1A

1

C1

C1
10U_0805_10V4Z

10U_0805_10V4Z

2

2

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

FAN Control Circuit

C863

C863

10U_0805_10V4Z

10U_0805_10V4Z

U58

U58

1

EN

2

VIN

3

VOUT

4

VSET

G996P11U SOP 8P

G996P11U SOP 8P

GND
GND
GND
GND

8
7
6
5

Title

Title

Title

Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN

Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN

Sandy Bridge(1/6)-CLK/MISC/JTAG/XDP/FAN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Routed as a single daisy chain

1 2

R35 1K_0402_5%R35 1K_0402_5%

T3PADT3PAD
T4PADT4PAD
T6PADT6PAD
T7PADT7PAD

R1474 0_0402_5%@R1474 0_0402_5%@

1 2

R1473 0_0402_5%@R1473 0_0402_5%@

1 2

R1476 0_0402_5%@R1476 0_0402_5%@

1 2

R1477 0_0402_5%@R1477 0_0402_5%@

1 2

+3VS

XDP_DBRESET# 32

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

2

+FAN1

1

2

@C864

@

1000P_0402_50V7K

1000P_0402_50V7K

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

R114 51_0402_5%R114 51_0402_5%

R59 51_0402_5%R59 51_0402_5%

R75 51_0402_5%R75 51_0402_5%

R112 51_0402_5%R112 51_0402_5%

R74 51_0402_5%R74 51_0402_5%

C864

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

JFAN

JFAN

1
2
3

4
5

R3 10K_0402_5%R3 10K_0402_5%

1

C865

@C865

@

0.01U_0402_25V7K

0.01U_0402_25V7K

2

1

CFG12 10
CFG13 10
CFG14 10
CFG15 10

+1.05VS_VCCP

12

12

12

12

12

1
2
3

GND
GND

ACES_85205-03001

ACES_85205-03001

CONN@

CONN@

12

FAN_SPEED1 45

5 59Monday, November 01, 2010

5 59Monday, November 01, 2010

5 59Monday, November 01, 2010

of

of

of

+3VS

0.1

0.1

0.1

5

4

3

2

1

+1.05VS_VCCP

12

RC2

RC2

24.9_0402_1%

D D

DMI_PTX_CRX_N032
DMI_PTX_CRX_N132
DMI_PTX_CRX_N232
DMI_PTX_CRX_N332

DMI_PTX_CRX_P032
DMI_PTX_CRX_P132
DMI_PTX_CRX_P232
DMI_PTX_CRX_P332

DMI_CTX_PRX_N032
DMI_CTX_PRX_N132
DMI_CTX_PRX_N232
DMI_CTX_PRX_N332

DMI_CTX_PRX_P032
DMI_CTX_PRX_P132
DMI_CTX_PRX_P232
DMI_CTX_PRX_P332

FDI_CTX_PRX_N032

C C

+1.05VS_VCCP

12

RC4

RC4

24.9_0402_1%

24.9_0402_1%

B B

+1.05VS_VCCP

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

R193 1K_0402_5%DIS@R193 1K_0402_5%DIS@

1 2

R194 1K_0402_5%DIS@R194 1K_0402_5%DIS@

1 2

R196 1K_0402_5%DIS@R196 1K_0402_5%DIS@

1 2

R270 1K_0402_5%DIS@R270 1K_0402_5%DIS@

1 2

R271 1K_0402_5%DIS@R271 1K_0402_5%DIS@

A A

1 2

FDI_CTX_PRX_N132
FDI_CTX_PRX_N232
FDI_CTX_PRX_N332
FDI_CTX_PRX_N432
FDI_CTX_PRX_N532
FDI_CTX_PRX_N632
FDI_CTX_PRX_N732

FDI_CTX_PRX_P032
FDI_CTX_PRX_P132
FDI_CTX_PRX_P232
FDI_CTX_PRX_P332
FDI_CTX_PRX_P432
FDI_CTX_PRX_P532
FDI_CTX_PRX_P632
FDI_CTX_PRX_P732

FDI_FSYNC032
FDI_FSYNC132

FDI_INT32

FDI_LSYNC032
FDI_LSYNC132

1 2

R88 1K_0402_5%@R88 1K_0402_5%@

EDP_COMP

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

JCPU1A

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

PEG_COMP

PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

24.9_0402_1%

C136 0.22U_0402_10V6KC136 0.22U_0402_10V6K

1 2

C222 0.22U_0402_10V6KC222 0.22U_0402_10V6K

1 2

C60 0.22U_0402_10V6KC60 0.22U_0402_10V6K

1 2

C67 0.22U_0402_10V6KC67 0.22U_0402_10V6K

1 2

C75 0.22U_0402_10V6KC75 0.22U_0402_10V6K

1 2

C118 0.22U_0402_10V6KC118 0.22U_0402_10V6K

1 2

C220 0.22U_0402_10V6KC220 0.22U_0402_10V6K

1 2

C59 0.22U_0402_10V6KC59 0.22U_0402_10V6K

1 2

C62 0.22U_0402_10V6KC62 0.22U_0402_10V6K

1 2

C70 0.22U_0402_10V6KC70 0.22U_0402_10V6K

1 2

C115 0.22U_0402_10V6KC115 0.22U_0402_10V6K

1 2

C197 0.22U_0402_10V6KC197 0.22U_0402_10V6K

1 2

C223 0.22U_0402_10V6KC223 0.22U_0402_10V6K

1 2

C61 0.22U_0402_10V6KC61 0.22U_0402_10V6K

1 2

C68 0.22U_0402_10V6KC68 0.22U_0402_10V6K

1 2

C88 0.22U_0402_10V6KC88 0.22U_0402_10V6K

1 2

C209 0.22U_0402_10V6KC209 0.22U_0402_10V6K

1 2

C224 0.22U_0402_10V6KC224 0.22U_0402_10V6K

1 2

C66 0.22U_0402_10V6KC66 0.22U_0402_10V6K

1 2

C69 0.22U_0402_10V6KC69 0.22U_0402_10V6K

1 2

C89 0.22U_0402_10V6KC89 0.22U_0402_10V6K

1 2

C135 0.22U_0402_10V6KC135 0.22U_0402_10V6K

1 2

C221 0.22U_0402_10V6KC221 0.22U_0402_10V6K

1 2

C71 0.22U_0402_10V6KC71 0.22U_0402_10V6K

1 2

C72 0.22U_0402_10V6KC72 0.22U_0402_10V6K

1 2

C74 0.22U_0402_10V6KC74 0.22U_0402_10V6K

1 2

C117 0.22U_0402_10V6KC117 0.22U_0402_10V6K

1 2

C214 0.22U_0402_10V6KC214 0.22U_0402_10V6K

1 2

C78 0.22U_0402_10V6KC78 0.22U_0402_10V6K

1 2

C79 0.22U_0402_10V6KC79 0.22U_0402_10V6K

1 2

C87 0.22U_0402_10V6KC87 0.22U_0402_10V6K

1 2

C111 0.22U_0402_10V6KC111 0.22U_0402_10V6K

1 2

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 mohms

PCIE_GTX_C_CRX_N[0..15] 14

PCIE_GTX_C_CRX_P[0..15] 14

PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[0..15] 14

PCIE_CTX_C_GRX_P[0..15] 14

IF LEFT NC, 15MW PWR CONSUM IN CPU SIDE

Security Classification

Security Classification

Security Classification

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge(2/6)-DMI/FDI/PEG/eDP

Sandy Bridge(2/6)-DMI/FDI/PEG/eDP

Sandy Bridge(2/6)-DMI/FDI/PEG/eDP

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

of

of

of

6 59Monday, November 01, 2010

6 59Monday, November 01, 2010

6 59Monday, November 01, 2010

0.1

0.1

0.1

5

JCPU1C

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10

AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

K2
M8

N8

N7

M9

N9
M7

V6

J1
J5
J4
J2

JCPU1C

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR_A_D[0..63]12

DDR_A_D0
DDR_A_D1
DDR_A_D2

D D

C C

B B

DDR_A_BS012
DDR_A_BS112
DDR_A_BS212

DDR_A_CAS#12
DDR_A_RAS#12

DDR_A_WE#12

DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

SA_CLK[2]

AA4

SA_CLK#[2]

W9

SA_CKE[2]

AB3

SA_CLK[3]

AA3

SA_CLK#[3]

W10

SA_CKE[3]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

SA_CS#[2]

AH1

SA_CS#[3]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

SA_ODT[2]

AH2

SA_ODT[3]

DDR_A_DQS#0

C4

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDRA_CLK0 12 DDRB_CLK0 13
DDRA_CLK0# 12
DDRA_CKE0 12 DDRB_CKE0 13

DDRA_CLK1 12
DDRA_CLK1# 12 DDRB_CLK1# 13
DDRA_CKE1 12

DDRA_SCS0# 12
DDRA_SCS1# 12 DDRB_SCS1# 13

DDRA_ODT0 12 DDRB_ODT0 13
DDRA_ODT1 12 DDRB_ODT1 13

DDR_A_DQS#[0..7] 12

DDR_A_DQS[0..7] 12

DDR_A_MA[0..15] 12

3

JCPU1D

AM5
AM6

AJ11

AH11

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA10

JCPU1D

C9

A7

D10

C8

A9

A8
D9
D8
G4

F4

F1
G1
G5

F5

F2
G2

J7
J8

K10

K9

J9

J10

K8

K7
M5
N4
N2
N1
M4
N5
M2
M1

AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9

AT8
AT9

AR8

AA9
AA7

R6

AB8
AB9

DDR_B_D[0..63]13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS013
DDR_B_BS113
DDR_B_BS213

DDR_B_CAS#13
DDR_B_RAS#13

DDR_B_WE#13

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

2

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

T9

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

DDR_B_DQS#0

D7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

1

DDRB_CLK0# 13

DDRB_CLK1 13

DDRB_CKE1 13

DDRB_SCS0# 13

DDR_B_DQS#[0..7] 13

DDR_B_DQS[0..7] 13

DDR_B_MA[0..15] 13

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61 CONN@

Sandy Bridge_rPGA_Rev0p61 CONN@

R124

@R124

@

0_0402_5%

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q6

Q6
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

C86

C86

0.047U_0402_16V4Z

0.047U_0402_16V4Z

2

H_DRAMRST#5

R119

A A

5

1 2

R118 0_0402_5%R118 0_0402_5%

1 2

R111 0_0402_5%@ R111 0_0402_5%@

DRAMRST_CNTRL_PCH31

DRAMRST_CNTRL_EC45

4.99K_0402_1%

4.99K_0402_1%

DRAMRST_CNTRL

R119

+1.5V

R123

R123

1K_0402_5%

1K_0402_5%

4

12

R129

R129
1K_0402_5%

1K_0402_5%

1 2

SM_DRAMRST# 12,13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge(3/6)-DDR III

Sandy Bridge(3/6)-DDR III

Sandy Bridge(3/6)-DDR III

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

7 59Monday, November 01, 2010

7 59Monday, November 01, 2010

7 59Monday, November 01, 2010

1

of

of

of

0.1

0.1

0.1

5

Material Note (+VCCP)

330uF/ 9m ohm, number are 4
SGA20331E10 for 330uF
16 * 22uF 0805
10 * 10uF 0805

+CPU_CORE

JCPU1F

JCPU1F

Group1

POWER

POWER

(Place these capacitors under CPU socket Edge, top layer)

94A 18A

D D

C C

B B

A A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

PEG AND DDR

PEG AND DDR

CORE SUPPLY

CORE SUPPLY

VCCIO_SENSE

VSSIO_SENSE

SENSE LINES SVID

SENSE LINES SVID

5

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

VCCSENSE_R
VSSSENSE_R

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C321

C321

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C241

C241

2

Cap quantity follow 43890_HR_CHKLST_Rev07

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCSENSE

VSSSENSE

1 2

10_0402_5%

10_0402_5%

4

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C275

C275

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C235

C235

2

+1.05VS_VCCP +1.05VS_VCCP

12

RC137

RC137
130_0402_5%

130_0402_5%

@

@

Close to CPU

1 2

R53 100_0402_1%R53 100_0402_1%

1 2

R54 100_0402_1%R54 100_0402_1%

0_0402_5%

0_0402_5%

R51

R51

1 2
1 2

R52 0_0402_5%R52 0_0402_5%

R158

R158

4

22U_0805_6.3V6M

1

1

C322

C322

C320

C320

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

@

@

@

@

C231

C231

C323

C323

2

2

RC61

RC61

43_0402_1%

43_0402_1%

1 2

RC59 0_0402_5%RC59 0_0402_5%

1 2

RC65 0_0402_5%RC65 0_0402_5%

1 2

+CPU_CORE

VCCSENSE
VSSSENSE

3

Can connect to GND if motherboard only



supports external graphics and if GFX VR is
not stuffed.

can be left floating (Gfx VR keeps VAXG



rail from floating) if the VR is stuffed

+1.05VS_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C232

C232

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

@

@

C324

C324

2

2

12

RC60

RC60
75_0402_5%

75_0402_5%

VCCSENSE 58
VSSSENSE 58

VCCIO_SENSE 56

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C243

C243

C242

C242

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

@

@

C326

C326

C238

C238

2

VR_SVID_ALRT# 58
VR_SVID_CLK 58
VR_SVID_DAT 58

Resistors
close to VR

1

C228

C228

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C234

C234

2

330U_D2_2V_Y

330U_D2_2V_Y

1

C227

C227

+

+

2

CPU1.5V_S3_GATE45

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

22U_0805_6.3V6M

1

1

C239

C239

C325

C325

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C237

C237

2

330U_D2_2V_Y

330U_D2_2V_Y

1

1

C230

C230

+

+

+

C240

@+C240

@

330U_D2_2V_Y

330U_D2_2V_Y

2

2

+1.5V +1.5V_CPU_VDDQ

SUSP#45,46,48,49,53,56,57,59

3

2

+CPU_CORE

+CPU_CORE

+CPU_CORE

C199

C199

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C201

C201

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0_0402_5%

0_0402_5%

1 2

@R132

@

0_0402_5%

0_0402_5%

1 2

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

R133

R133

R132

+3VALW

12

R134

R134
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3#

61

Q208A

Q208A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+VSB

12

R135

R135
100K_0402_5%

100K_0402_5%

3

Q208B

Q208B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5

4

2

SV type CPU

10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

2

1

2

1

2

1

2

1

C357

C357

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C334

C334

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C344

22U_0805_6.3V6M

C344

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C342

22U_0805_6.3V6M

C342

22U_0805_6.3V6M

1

2

C328

22U_0805_6.3V6M

C328

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

+

+

2

+1.5V +1.5V_CPU_VDDQ

RUN_ON_CPU1.5VS3

RUN_ON_CPU1.5VS3 9

1

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C331

C331

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C353

C353

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C259

C259

1

2

C345

C345

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C339

C339

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C358

C358

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

C335

C335

+

+

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C343

C343

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C260

C260

2

C354

C354

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C347

C347

1

2

C333

C333

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C355

C355

2

330U_D2_2V_Y+C350

330U_D2_2V_Y

1

C337

C337

+

2

10U_0805_6.3V6M

1

C336

C336

C327

C327

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C332

C332

2

C338

C338

1

2

C330

C330

1

2

C351

C351

1

2

1

@

@

C329

C329

2

330U_D2_2V_Y+C356

330U_D2_2V_Y

C350

1

+

2

10U_0805_6.3V6M

1

C348

C348

C352

C352

2

C349

22U_0805_6.3V6M

C349

22U_0805_6.3V6M

C346

22U_0805_6.3V6M

C346

22U_0805_6.3V6M

C341

22U_0805_6.3V6M

C341

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

C340

C340

C356

+1.5V_CPU_VDDQ Source

Q7

Q7

AO4728L_SO8

AO4728L_SO8

8
7
6
5

12

R136

R136

330K_0402_5%

330K_0402_5%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1
2
3

4

1

C196

C196

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Sandy Bridge(4/6)-PWR1

Sandy Bridge(4/6)-PWR1

Sandy Bridge(4/6)-PWR1

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

R131

R131
470_0603_5%

470_0603_5%

1 2

13

D

D

RUN_ON_CPU1.5VS3#

2

G

G

Q8

Q8

S

S

2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

RUN_ON_CPU1.5VS3#55

1

8 59Monday, November 01, 2010

8 59Monday, November 01, 2010

8 59Monday, November 01, 2010

of

of

of

0.1

0.1

0.1

5

+VGFX_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C252

OPT@

C252

OPT@

C251

OPT@

C251

OPT@

1

1

2

2

D D

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C261

OPT@

C261

OPT@

C253

OPT@

C253

1

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

1

C257

OPT@+C257

OPT@

+

2

C236

+

2

OPT@

1

2

OPT@+C236

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C233

OPT@

C233

OPT@

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C248

OPT@

C248

OPT@

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

C193

C193

1

2

22U_0805_6.3V6M

C212

OPT@

C212

OPT@

C210

1

2

1

2

1

2

C210

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C219

OPT@

C219

OPT@

C229

C229

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

@

@

C166

C166

C189

C189

1

2

Vaxg

C C

B B

Can connect to GND if motherboard only

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,

VAXG can be left floating in a common

motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

+1.8VS

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0805_10V4K

10U_0805_10V4K

C92

C92

C93

C93

1

2

4

POWER

JCPU1G

JCPU1G

26A

AT24

VAXG1

22U_0805_6.3V6M

22U_0805_6.3V6M

C211

OPT@

C211

OPT@

OPT@

OPT@

1

C211

C211
0_0805_5%

0_0805_5%

DIS@

DIS@

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C195

OPT@

C195

OPT@

OPT@

OPT@

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

C194

C194

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C94

C94

C91

C91

1

1

2

2

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

1U_0603_10V4Z

1U_0603_10V4Z

C90

C90

1

2

1

2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

POWER

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

3

Group2

SM_VREF

10A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

6A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

FC_C22

AK35
AK34

Follow DG 0.71 page 6

+V_SM_VREF_CNT +V_SM_VREF

AL1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

CC178

CC178

H_FC_C22

1

2

1

2

1

2

1

2

+VCCSA

10U_0805_6.3V6M

10U_0805_6.3V6M

CC168

CC168

1 2

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

VCCSA_VID1

+V_SM_VREF should
have 20 mil trace width

VCC_AXG_SENSE 58
VSS_AXG_SENSE 58

RC76

RC76

0_0402_5%

0_0402_5%

12

3

2

@

@

QC5

QC5

1

AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C54

C54

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

C63

C63

+

+

C56

C56

C55

C55

1

1

1

2

2

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C65

C65

C64

C64

1

1

2

2

(9A,360mils ,Via NO.= 18)

OCP (min)=10.8A

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

1

CC169

CC169

2

RC83

RC83
10K_0402_5%

10K_0402_5%

@

@

1

1

CC171

CC171

CC170

CC170

2

2

12

RC81

@RC81

@

0_0402_5%

0_0402_5%

+1.5V_CPU_VDDQ

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C57

C57

1

2

J3

J3

2

JUMP_43X118

JUMP_43X118

@

@

J2

J2

2

@

@

JUMP_43X118

JUMP_43X118

RC132

RC132
0_0402_5%

0_0402_5%

1 2

1

+

+

CC172

CC172
330U_X_2VM_R6M

330U_X_2VM_R6M

2

2

RC118

RC118
1K_0402_5%

1K_0402_5%

1 2

RC119

RC119
1K_0402_5%

1K_0402_5%

1 2

RUN_ON_CPU1.5VS3 8

C58

C58

+1.5V_CPU_VDDQ

112

112

+VCCSA

VCCSA_SENSE

VCCSA_SENSE 57

VCCSA_SEL 57

1

+1.5V

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge(4/6)-PWR2

Sandy Bridge(4/6)-PWR2

Sandy Bridge(4/6)-PWR2

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

9 59Monday, November 01, 2010

9 59Monday, November 01, 2010

9 59Monday, November 01, 2010

1

0.1

0.1

0.1

of

of

of

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

JCPU1E

JCPU1E

L7

RSVD28

AG7

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

RSVD53

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

KEY

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

T249PAD T249PAD

CLK_RES_ITP 31
CLK_RES_ITP# 31

T245 PADT245 PAD
T246 PADT246 PAD
T247 PADT247 PAD
T248 PADT248 PAD

12

CPU_RSVD6
CPU_RSVD7

12

RC139

RC139

1K_0402_1%

1K_0402_1%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

CFG05

T251 PADT251 PAD
T252 PADT252 PAD
T253 PADT253 PAD
T254 PADT254 PAD
T255 PADT255 PAD
T256 PADT256 PAD
T257 PADT257 PAD
T258 PADT258 PAD
T259 PADT259 PAD
T260 PADT260 PAD
T261 PADT261 PAD

CFG125
CFG135
CFG145
CFG155

T262 PADT262 PAD
T263 PADT263 PAD

C C

RC138

RC138

1K_0402_1%

1K_0402_1%

B B

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

RESERVED

RESERVED

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

*

Display Port Presence Strap

CFG4

*

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

RC51

RC51

@

@

1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

1K_0402_1%

12

@

@

RC52

RC52
1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6

CFG5

@RC54

@

CFG7

RC54

12

12

12

@RC56

@

RC53

@RC53

@

1K_0402_1%

1K_0402_1%

RC56
1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

*

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0: PEG Wait for BIOS for training

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge(5/6) Reserve

Sandy Bridge(5/6) Reserve

Sandy Bridge(5/6) Reserve

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

0.1

0.1

10 59Monday, November 01, 2010

10 59Monday, November 01, 2010

10 59Monday, November 01, 2010

0.1

of

of

of

5

JCPU1H

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

D D

C C

B B

AR25
AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

AM7
AM4
AM3
AM2
AM1

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AN7

VSS43

AN4

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

AK7

VSS78

AK4

VSS79
VSS80

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

4

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

3

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

2

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

1

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

A A

5

4

Sandy Bridge_rPGA_Rev0p61

CONN@

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Sandy Bridge(6/6)-GND

Sandy Bridge(6/6)-GND

Sandy Bridge(6/6)-GND

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

11 59Monday, November 01, 2010

11 59Monday, November 01, 2010

11 59Monday, November 01, 2010

1

of

of

of

0.1

0.1

0.1

5

+1.5V

+VREF_DQ

1K_0402_1%

D D

C C

B B

A A

1K_0402_1%

R55

R55

1K_0402_1%

1K_0402_1%

R57

R57

12

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K
C134

C134

C133

C133

1

1

12

2

2

DDRA_CKE07

DDR_A_BS27

DDRA_CLK07
DDRA_CLK0#7

DDR_A_BS07

DDR_A_WE#7
DDR_A_CAS#7

DDRA_SCS1#7

+3VS

1

2

5

DDR_A_D0
DDR_A_D1

DDR_A_DM0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDRA_CLK0
DDRA_CLK0#

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS# DDRA_ODT0

DDR_A_MA13
DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

C160

C160

C161

C161

1

2

+1.5V +1.5V

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDDRL

JDDRL

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R68

10K_0402_5%

R68

10K_0402_5%

R67

10K_0402_5%

R67

10K_0402_5%

12

12

VTT1

205

G1

CONN@

CONN@

4

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

LCN_DAN06-K4526-0101

LCN_DAN06-K4526-0101

G2

4

3

DDR_A_D[0..63]7

DDR_A_DQS[0..7]7

0.1U_0402_10V6K

0.1U_0402_10V6K
C138

C138

Issued Date

Issued Date

Issued Date

DDR_A_DQS#[0..7]7

DDR_A_MA[0..15]7

+1.5V

12

R56

R56
1K_0402_1%

1K_0402_1%

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
C139

C139

12

1

2

R60

R60
1K_0402_1%

1K_0402_1%

3

+VREF_CA

Compal Secret Data

Compal Secret Data

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

SM_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDRA_CKE1

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

DDRA_CLK1

102

DDRA_CLK1#

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDRA_SCS0#

114
116
118

DDRA_ODT1

120
122
124
126
128

DDR_A_D36

130

DDR_A_D37

132
134

DDR_A_DM4

136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

206

+0.75VS

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

SM_DRAMRST# 7,13

DDRA_CKE1 7

DDRA_CLK1 7
DDRA_CLK1# 7

DDR_A_BS1 7
DDR_A_RAS# 7

DDRA_SCS0# 7
DDRA_ODT0 7

DDRA_ODT1 7

1

2

PM_SMBDATA 13,26,31,41
PM_SMBCLK 13,26,31,41

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Layout Note:
Place near JDDRL

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

+1.5V

2

C140

C140

1

+

+

2

C144

C144

C145

C143

C143

1

2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

+1.5V

+0.75VS

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

C145

1

1

2

2

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

0.1U_0402_10V6K

0.1U_0402_10V6K
C149

C149

1

1

2

2

Layout Note:
Place near JDDRL.203,204

C361

1U_0402_6.3V6K

C361

1U_0402_6.3V6K

1

1

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII-SODIMM0

DDRIII-SODIMM0

DDRIII-SODIMM0

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C146

C146

0.1U_0402_10V6K

0.1U_0402_10V6K
C150

C150

1

2

C360

1U_0402_6.3V6K

C360

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C153

47P_0402_50V8J

C153

C147

C147

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C152

C152

C151

C151

1

2

C359

1U_0402_6.3V6K

C359

1U_0402_6.3V6K

C362

1U_0402_6.3V6K

C362

1U_0402_6.3V6K

1

1

2

2

12 59Monday, November 01, 2010

12 59Monday, November 01, 2010

12 59Monday, November 01, 2010

1

47P_0402_50V8J

C148

C148

1

12

2

C369

22U_0805_6.3V6M

C369

22U_0805_6.3V6M

1

2

0.1

0.1

0.1

of

of

of

5

+VREF_DQ

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

C162

C162

2

D D

+3VS

DDRB_CKE07

DDR_B_BS27

DDRB_CLK07
DDRB_CLK0#7

DDR_B_BS07

DDR_B_WE#7
DDR_B_CAS#7

DDRB_SCS1#7

C C

B B

A A

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
C185

C185

1

2

DDR_B_D0
DDR_B_D1

C163

C163

DDR_B_DM0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDRB_CLK0
DDRB_CLK0#

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS# DDRB_ODT0

DDR_B_MA13
DDRB_SCS1#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

R76

R76

1 2

10K_0402_5%

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K
C186

C186

1

R77 10K_0402_5%R77 10K_0402_5%

2

5

+1.5V +1.5V

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDDRH

JDDRH

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

1 2

SA1

203

VTT1

205

G1

LCN_DAN06-K4926-0101

LCN_DAN06-K4926-0101

CONN@

CONN@

VSS3

DQS#0

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

4

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26

DDR_B_DM1

28

SM_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44

DDR_B_DM2

46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDRB_CKE1

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86
88

DDR_B_MA6

90

DDR_B_MA4

92
94

DDR_B_MA2

96

DDR_B_MA0

98
100

DDRB_CLK1

102

DDRB_CLK1#

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDRB_SCS0#

114
116
118

DDRB_ODT1

120
122
124

+VREF_CA

126
128

DDR_B_D36

130

DDR_B_D37

132
134

DDR_B_DM4

136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198

PM_SMBDATA

200

PM_SMBCLK

202
204

206

4

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

SM_DRAMRST# 7,12

DDRB_CKE1 7

DDRB_CLK1 7
DDRB_CLK1# 7

DDR_B_BS1 7
DDR_B_RAS# 7

DDRB_SCS0# 7
DDRB_ODT0 7

DDRB_ODT1 7

0.1U_0402_10V6K

0.1U_0402_10V6K

C167

C167

1

2

PM_SMBDATA 12,26,31,41
PM_SMBCLK 12,26,31,41

+0.75VS

+VREF_CA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_DQS#[0..7]7

DDR_B_D[0..63]7

DDR_B_DQS[0..7]7

DDR_B_MA[0..15]7

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

C168

C168

1

2

Compal Secret Data

Compal Secret Data

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Layout Note:
Place near JDDRH

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.5V

2

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

C141

C141

C171

C171

1

+

+

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

10U_0603_6.3V6M

C172

C172

1

1

2

2

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

+1.5V

Layout Note:
Place near JDDRH.203 and 204

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C174

C174

C173

C173

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C177

C177

C178

1

2

+0.75VS

DDRIII-SODIMM1

DDRIII-SODIMM1

DDRIII-SODIMM1

C178

1

1

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C181

C181

1

2

1U_0603_10V4Z

C182

C182

1

1

2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C175

C175

0.1U_0402_10V6K

0.1U_0402_10V6K

C183

C183

10U_0603_6.3V6M

C176

C176

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K
C180

C180

C179

C179

1

2

1U_0603_10V4Z

1U_0603_10V4Z

C370

22U_0805_6.3V6M

C370

22U_0805_6.3V6M

C184

C184

1

1

2

2

0.1

0.1

0.1

of

13 59Monday, November 01, 2010

of

13 59Monday, November 01, 2010

of

13 59Monday, November 01, 2010

5

Under GPU(below 150mils)

BLM18PG330SN1D_0603

BLM18PG330SN1D_0603

+1.05VS_DGPU

D D

C C

1 2

LV1

LV1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV86

CV86

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV85

CV85

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3

PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15

CV11

CV11

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CV12

CV12

2

Differential signal

B B

CLK_REQ_VGA#31

A A

DGPU_PWR_EN34,49,59

Add Level Shifter
for different
power plane

3VALW_PCH PU AT PCH SIDE,

1 2

RV28 10M_0402_5%RV28 10M_0402_5%

YV1

XTALIN XTAL_OUT

1

CV45

CV45
18P_0402_50V8J

18P_0402_50V8J

2

YV1

1 2

27MHZ_16PF_X5H027000FG1H

27MHZ_16PF_X5H027000FG1H

5

1 2
2

QV2

QV2

1 3

D

D

2N7002_SOT23-3

2N7002_SOT23-3

DIS@

DIS@

1 2

RV114 0_0402_5%

RV114 0_0402_5%

RV127

RV127
10K_0402_5%

10K_0402_5%

OPT@

OPT@

G

G

OPT@

OPT@

S

S

1

CV46

CV46
18P_0402_50V8J

18P_0402_50V8J

2

+3VS_DGPU

󲆌󲃴󱋟󱦞󲕩

RV118

RV118
10K_0402_5%

10K_0402_5%

OPT@

OPT@

1 2

CLK_REQ_GPU#

RV126

RV126
10K_0402_5%

10K_0402_5%

@

@

1 2

PLTRST_VGA#34

4

150mA

+PLLVDD

2

CV99

CV99

1

C16 0.22U_0402_10V6KC16 0.22U_0402_10V6K

1 2

C17 0.22U_0402_10V6KC17 0.22U_0402_10V6K

1 2

C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K

1 2

C19 0.22U_0402_10V6KC19 0.22U_0402_10V6K

1 2

C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K

1 2

C21 0.22U_0402_10V6KC21 0.22U_0402_10V6K

1 2

C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K

1 2

C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K

1 2

C24 0.22U_0402_10V6KC24 0.22U_0402_10V6K

1 2

C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K

1 2

C26 0.22U_0402_10V6KC26 0.22U_0402_10V6K

1 2

C27 0.22U_0402_10V6KC27 0.22U_0402_10V6K

1 2

C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K

1 2

C29 0.22U_0402_10V6KC29 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K

1 2

C31 0.22U_0402_10V6KC31 0.22U_0402_10V6K

1 2

C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K

1 2

C33 0.22U_0402_10V6KC33 0.22U_0402_10V6K

1 2

C34 0.22U_0402_10V6KC34 0.22U_0402_10V6K

1 2

C35 0.22U_0402_10V6KC35 0.22U_0402_10V6K

1 2

C36 0.22U_0402_10V6KC36 0.22U_0402_10V6K

1 2

C37 0.22U_0402_10V6KC37 0.22U_0402_10V6K

1 2

C38 0.22U_0402_10V6KC38 0.22U_0402_10V6K

1 2

C39 0.22U_0402_10V6KC39 0.22U_0402_10V6K

1 2

C40 0.22U_0402_10V6KC40 0.22U_0402_10V6K

1 2

C45 0.22U_0402_10V6KC45 0.22U_0402_10V6K

1 2

C46 0.22U_0402_10V6KC46 0.22U_0402_10V6K

1 2

C48 0.22U_0402_10V6KC48 0.22U_0402_10V6K

1 2

C116 0.22U_0402_10V6KC116 0.22U_0402_10V6K

1 2

C213 0.22U_0402_10V6KC213 0.22U_0402_10V6K

1 2

C226 0.22U_0402_10V6KC226 0.22U_0402_10V6K

1 2

C47 0.22U_0402_10V6KC47 0.22U_0402_10V6K

1 2

CLK_PCIE_VGA31

CLK_PCIE_VGA#31

@

@

1 2

RV16 200_0402_1%

RV16 200_0402_1%

1 2

RV18 0_0402_5%RV18 0_0402_5%

1 2

RV19 2.49K_0402_1%RV19 2.49K_0402_1%

+PLLVDD

@

@

RV103 0_0402_5%

RV103 0_0402_5%

27M_CLK31

27M_SSC31

CRT

4

1 2

RV26 10K_0402_5%RV26 10K_0402_5%

RV25 10K_0402_5%RV25 10K_0402_5%

1 2

RV105 0_0402_5%@RV105 0_0402_5%@

SMB_CLK_GPU15
SMB_DATA_GPU15

VGA_EDID_CLK28
VGA_EDID_DATA28

VGA_CRT_CLK27
VGA_CRT_DATA27

3

UV1A

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15

PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P4PCIE_GTX_C_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15

CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

PLTRST_VGA_R#

60mA

45mA

45mA

XTALIN

XTAL_OUT

XTALOUT

12

XTALSSIN

12

SMB_CLK_GPU
SMB_DATA_GPU

I2CC_SCL
I2CC_SDA

I2CB_SCL
I2CB_SDA

VGA_CRT_CLK
VGA_CRT_DATA

HDCP_SCL
HDCP_SDA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UV1A

AP17

PEX_RX0

AN17

PEX_RX0_N

AN19

PEX_RX1

AP19

PEX_RX1_N

AR19

PEX_RX2

AR20

PEX_RX2_N

AP20

PEX_RX3

AN20

PEX_RX3_N

AN22

PEX_RX4

AP22

PEX_RX4_N

AR22

PEX_RX5

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

AR13

PEX_CLKREQ_N

AJ17

PEX_TSTCLK_OUT

AJ18

PEX_TSTCLK_OUT_N

AM16

PEX_RST_N

AG21

PEX_TERMP

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

E2

I2CS_SCL

E1

I2CS_SDA

E3

I2CC_SCL

E4

I2CC_SDA

G3

I2CB_SCL

G2

I2CB_SDA

G1

I2CA_SCL

G4

I2CA_SDA

F6

I2CH_SCL

G6

I2CH_SDA

@

@

N12P-GV1-A1_BGA_973P

N12P-GV1-A1_BGA_973P

Part 1 of 7

Part 1 of 7

GPIO

GPIO

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC

MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

DVO

DVO

MIOB_D0_NC

MIOB_D1_NC

MIOB_D2_NC

PCI EXPRESS

PCI EXPRESS

MIOB_D3_NC

MIOB_D4_NC

MIOB_D5_NC

MIOB_D6_NC

MIOB_D7_NC

MIOB_D8_NC

MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

MIOA_HSYNC_NC
MIOA_VSYNC_NC

MIOB_HSYNC_NC
MIOB_VSYNC_NC

MIOA_DE_NC

MIOA_CTL3_NC

MIOA_VREF_NC

MIOB_DE_NC

MIOB_CTL3_NC

MIOB_VREF_NC

MIOA_CLKIN_NC

MIOA_CLKOUT_NC

MIOB_CLKIN_NC

MIOB_CLKOUT_NC

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

MIOACAL_PD_VDDQ_NC

MIOACAL_PU_GND_NC

MIOBCAL_PD_VDDQ_NC

MIOBCAL_PU_GND_NC

CLK

CLK

DACA_GREEN

DACA_HSYNC

DACA_VSYNC

DACB_GREEN

DACs

DACs

DACB_HSYNC

I2C

I2C

DACB_VSYNC

Compal Secret Data

Compal Secret Data

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

DACA_RED

DACA_BLUE

DACA_VDD
DACA_VREF
DACA_RSET

DACB_RED

DACB_BLUE

DACB_VDD
DACB_VREF
DACB_RSET

Deciphered Date

Deciphered Date

Deciphered Date

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
M7

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

N3
L3

W1
W2

N2
P5
N5

Y5
W3
AF1

N4
R4

AE1
V4

T4
W4

U5
T5

AA7
AA6

AM15
AM14
AL14

AM13
AL13

AJ12
AK12
AK13

AK4
AL4
AJ4

AM1
AM2

AG7
AK6
AH7

+DACB_VDD

VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1

GPIO8
THERM#_VGA

GPIO12

dGPU_HDMI_HPD

1 2

RV15 10K_0402_5%RV15 10K_0402_5%

1 2

RV17 10K_0402_5%RV17 10K_0402_5%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

VGA_CRT_HSYNC
VGA_CRT_VSYNC

+DACA_VDD
+DACA_VREF
DACA_RSET

RV27

RV27

124_0402_1%

124_0402_1%

RV31 10K_0402_5%RV31 10K_0402_5%

2

VGA_BL_PWM 28
VGA_ENVDD 28
VGA_ENBKL 45
GPU_VID0 59
GPU_VID1 59

THERM#_VGA 15

TV6TV6

+DACA_VDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

+3VS_DGPU

OPT@

OPT@

OPT@

OPT@

4

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

U13

U13

2

P

B

Y

1

A

G

3

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

1 2

RV32 0_0402_5%

RV32 0_0402_5%

DIS@

DIS@

Under GPU(below 150mils)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV47

CV47

2

12

2

1

CV73

CV73

CRT@

CRT@

2

VGA_CRT_R 27
VGA_CRT_G 27
VGA_CRT_B 27

VGA_CRT_HSYNC 27
VGA_CRT_VSYNC 27

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

CV72

CV72

CRT@

CRT@

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Date: Sheet

Date: Sheet

Date: Sheet

1

PCIE_GTX_C_CRX_P[0..15]6

PCIE_GTX_C_CRX_N[0..15]6

PCIE_CTX_C_GRX_P[0..15]6

PCIE_CTX_C_GRX_N[0..15]6

CV117

CV117

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV48

CV48

CRT@

CRT@

2

VGA_ENVDD

VGA_ENBKL

VGA_BL_PWM

GPIO8

I2CC_SCL

I2CC_SDA

SMB_CLK_GPU

SMB_DATA_GPU

THERM#_VGA

HDCP_SCL

HDCP_SDA

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

GPIO12

120mA

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

CV80

CV80

CRT@

CRT@

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CV81

CV81

CRT@

CRT@

PCIE_GTX_C_CRX_P[0..15]

PCIE_GTX_C_CRX_N[0..15]

PCIE_CTX_C_GRX_P[0..15]

PCIE_CTX_C_GRX_N[0..15]

VGA_PWROK 35,49,59

VGA_HDMI_HPD 29

1 2

RV1 10K_0402_5%RV1 10K_0402_5%

RV2 10K_0402_5%RV2 10K_0402_5%

RV3 10K_0402_5%RV3 10K_0402_5%

1 2

RV4 10K_0402_5%RV4 10K_0402_5%

1 2

RV6 2.2K_0402_5%RV6 2.2K_0402_5%

1 2

RV7 2.2K_0402_5%RV7 2.2K_0402_5%

1 2

RV8 2.2K_0402_5%RV8 2.2K_0402_5%

1 2

RV9 2.2K_0402_5%RV9 2.2K_0402_5%

1 2

RV10 10K_0402_5%RV10 10K_0402_5%

1 2

RV11 2.2K_0402_5%RV11 2.2K_0402_5%

1 2

RV12 2.2K_0402_5%RV12 2.2K_0402_5%

1 2

RV13 2.2K_0402_5%RV13 2.2K_0402_5%

1 2

RV14 2.2K_0402_5%RV14 2.2K_0402_5%

1 2

RV121 2.2K_0402_5%RV121 2.2K_0402_5%

1 2

RV122 2.2K_0402_5%RV122 2.2K_0402_5%

1 2

RV5 10K_0402_5%RV5 10K_0402_5%

CV80

CV80
10K_0402_5%

10K_0402_5%

OPT@

OPT@

FOR OPTIMUS

MMZ1608D301BT_0603

MMZ1608D301BT_0603

1 2

LV3

LV3

CRT@

CRT@

1

CV51

CV51

CRT@

CRT@

2

12

12

1

2

+3VS_DGPU

+3VS_DGPU

CV49

CV49

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CRT@

CRT@

Close to GPU

CRT@

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

VGA(1/12)-PCIE/DAC/GPIO

VGA(1/12)-PCIE/DAC/GPIO

VGA(1/12)-PCIE/DAC/GPIO

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

CRT@

1 2

RV20 150_0402_1%

RV20 150_0402_1%

CRT@

CRT@

1 2

CRT@

CRT@

RV21 150_0402_1%

RV21 150_0402_1%

1 2

RV23 150_0402_1%

RV23 150_0402_1%

of

14 59Monday, November 01, 2010

of

14 59Monday, November 01, 2010

of

14 59Monday, November 01, 2010

1

0.1

0.1

0.1

5

VGA_TXCLK+28

VGA_TXCLK-28
VGA_TXOUT0+28

VGA_TXOUT0-28

VGA_TXOUT1+28

VGA_TXOUT1-28

VGA_TXOUT2+28

VGA_TXOUT2-28

D D

C C

VGA_HDMI_TX2+29
VGA_HDMI_TX2-29

VGA_HDMI_TX1+29

VGA_HDMI_TX1-29

VGA_HDMI_TX0+29
VGA_HDMI_TX0-29
VGA_HDMI_TXC+29
VGA_HDMI_TXC-29

4.7K_0402_5%

B B

VGA_HDMI_CLK29

VGA_HDMI_DATA29

A A

5

4.7K_0402_5%

HDMI@

HDMI@

STRAP025
STRAP125
STRAP225

RV115

RV115

4

VGA_TXCLK+
VGA_TXCLK­VGA_TXOUT0+
VGA_TXOUT0­VGA_TXOUT1+
VGA_TXOUT1­VGA_TXOUT2+
VGA_TXOUT2-

+3VS_DGPU

12

+3VS_DGPU

4

VGA_HDMI_TX2+
VGA_HDMI_TX2-

VGA_HDMI_TX1+

VGA_HDMI_TX1-

VGA_HDMI_TX0+
VGA_HDMI_TX0­VGA_HDMI_TXC+
VGA_HDMI_TXC-

12

RV116

RV116

4.7K_0402_5%

4.7K_0402_5%

HDMI@

HDMI@

RV113

RV113
10K_0402_5%

10K_0402_5%

1 2

STRAP0
STRAP1
STRAP2

UV1D

UV1D

AM11

IFPA_TXC

AM12

IFPA_TXC_N

AM8

IFPA_TXD0

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW_SCL

AN3

IFPC_AUX_I2CW_SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

N12P-GV1-A1_BGA_973P

N12P-GV1-A1_BGA_973P

@

@

3

Part 4 of 7

Part 4 of 7

NC

NC

VDD_SENSE_0

LVDS/TMDS

LVDS/TMDS

VDD_SENSE_1
VDD_SENSE_2

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

TEST

TEST

JTAG_TRST_N

SERIAL

SERIAL

GENERAL

GENERAL

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NC/SPDIF_NC

MULTI_STRAP_REF0_GND

MULTI_STRAP_REF1_GND

Issued Date

Issued Date

Issued Date

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

TESTMODE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

THERMDP
THERMDN

3

A2
A7
B7
C5

STRAP4

C7
D5
D6

STRAP3

D7
E5

PGOOD

E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

VDD_SENSE

D35
P7
AD20

AD19
E35
R7

TESTMODE

AP35
AP14
AN14
AN16
AR14
AP16

C3

ROM_SI

D3

ROM_SO

C4

ROM_SCLK

D4

A5

N9

RV48 40.2K_0402_1%RV48 40.2K_0402_1%

M9

RV50 40.2K_0402_1%RV50 40.2K_0402_1%

B5
B4

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

STRAP4 25

STRAP3 25

MULTI_STRAP_REF2_GND

@

@

RV49

RV49

@

@

1 2

40.2K_0402_1%

40.2K_0402_1%

VGA_SMB_CK2

VGA_SMB_DA2

VDD_SENSE 59

1 2

@

@

1 2

TV7TV7
TV3TV3
TV4TV4

1 2

RV41 10K_0402_5%RV41 10K_0402_5%

1 2

1 2

THERM_D+
THERM_D-

TV5TV5

ROM_SI 25
ROM_SO 25
ROM_SCLK 25

Compal Secret Data

Compal Secret Data

Compal Secret Data

RV101

RV101

THERM_D+

10K_0402_1%

10K_0402_1%

1 2

THERM_D-

2.2K_0402_5%

2.2K_0402_5%

RV54

RV54
10K_0402_5%

10K_0402_5%
RV47

RV47
10K_0402_5%

10K_0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

2200P_0402_50V7K

2200P_0402_50V7K

RV117

RV117

OPT@

OPT@

2

External VGA Thermal Sensor

+3VS_DGPU

12

CV53 0.1U_0402_16V4ZCV53 0.1U_0402_16V4Z

CV54

CV54

1 2

+3VS_DGPU

12

12

RV119

RV119

2.2K_0402_5%

2.2K_0402_5%

OPT@

OPT@

+3VS_DGPU

+3VS_DGPU

2

UV2

UV2

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

ADM1032ARMZ-2REEL_MSOP8

QV211A

QV211A

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

OPT@

OPT@

OPT@

OPT@

4

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

QV211B

QV211B

1 2

RV35 0_0402_5%

RV35 0_0402_5%

1 2

RV36 0_0402_5%

RV36 0_0402_5%

8

SCLK

7

SDATA

6

ALERT#

5

61

2

5

3

DIS@

DIS@

DIS@

DIS@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

Internal Thermal Sensor

12

12

RV33

RV33

0_0402_5%

0_0402_5%

@

@

VGA_SMB_CK2

VGA_SMB_DA2

THERM#_VGA

1 2

RV120

RV120
10K_0402_5%

10K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

VGA(2/12)-LVDS/HDMI/DP/THM

VGA(2/12)-LVDS/HDMI/DP/THM

VGA(2/12)-LVDS/HDMI/DP/THM

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

THERM#_VGA 14

+3VS_DGPU

EC_SMB_CK2 31,45

EC_SMB_DA2 31,45

1

SMB_CLK_GPU 14

SMB_DATA_GPU 14

RV34

RV34
0_0402_5%

0_0402_5%

@

@

Address: 0x9A H

15 59Monday, November 01, 2010

15 59Monday, November 01, 2010

15 59Monday, November 01, 2010

0.1

0.1

0.1

of

of

of

5

4

3

2

1

N11E-GE1-LP Performance Mode

UV1G

UV1G

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

Mode

Mode

D D

C C

B B

NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0

P8

450

405

135

790 0.90 V

324 0.85 V

135 0.80 V

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24

L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24

L25
M12
M14
M16
M18
M20
M22
M24

P11
P13
P15
P17
P19

N12P-GV1-A1_BGA_973P

N12P-GV1-A1_BGA_973P

@

@

N11P-GE1 Performance Mode

NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0

P8

P12 135 135 0.80 V P12

Part 7 of 7

Part 7 of 7

POWER

POWER

575

405

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98

VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

790 0.95 V

324 0.85 V

+VGA_CORE+VGA_CORE

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

32A for N11E-GE1-LP
28A for N11P-GE1
16A for N11M-GE1 & N11M-OP1
14A for N11M-GE2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.047U_0402_25V6K

0.047U_0402_25V6K

0.01U_0402_25V7K

0.01U_0402_25V7K

N11M-GE1 & N11M-OP1 Performance Mode

NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0

P8

625

405

135

790 1.03 V

405 0.85 V

135 0.85 VP12

Near to PL901

+VGA_CORE

CV57

CV57

470U_D2_2VM_R4M

470U_D2_2VM_R4M

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

CV60

CV60

1

10U_0603_6.3V6M

10U_0603_6.3V6M

0.047U_0402_25V6K

0.047U_0402_25V6K

1

CV67

CV67

2

0.047U_0402_25V6K

0.047U_0402_25V6K

0.01U_0402_25V7K

0.01U_0402_25V7K

1

CV75

CV75

2

0.01U_0402_25V7K

0.01U_0402_25V7K

1

CV61

CV61

@

@

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

CV68

CV68

2

1

CV76

CV76

2

0.01U_0402_25V7K

0.01U_0402_25V7K

22U_0805_6.3V6M

1

CV212

CV212

2

0.022U_0402_25V7K

0.022U_0402_25V7K

1

CV69

CV69

2

0.022U_0402_25V7K

0.022U_0402_25V7K

0.01U_0402_25V7K

0.01U_0402_25V7K

1

CV77

CV77

2

+VGA_CORE

CV59

CV59

+VGA_CORE

CV66

CV66

+VGA_CORE

CV74

CV74

Mode

2

1

1

2

1

2

1

+

+

2

1

CV63

CV63

2

1

CV70

CV70

2

0.022U_0402_25V7K

0.022U_0402_25V7K

1

CV78

CV78

2

0.01U_0402_25V7K

0.01U_0402_25V7K

1

+

+

CV58

CV58

470U_D2_2VM_R4M

470U_D2_2VM_R4M

2

1

CV6

CV6
47U_0805_4V6

47U_0805_4V6

2

1

CV71

CV71

2

0.01U_0402_25V7K

0.01U_0402_25V7K

1

CV79

CV79

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

CV52

CV52

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1

CV115

CV115

2

0.01U_0402_25V7K

0.01U_0402_25V7K

N11M-GE2 Performance Mode

Mode

NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0

P8

P12

606

405

135

Under GPU(below 150mils)

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CV55

CV55

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

CV116

CV116

1

CV62

CV62

2

12

CV5

CV5

12

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1

2

1

2

667 1.00 V

405 0.85 V

135 0.85 V

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

12

CV2

CV1

CV1

CV2

A A

Security Classification

Security Classification

Security Classification

2010/05/11 2011/05/11

2010/05/11 2011/05/11

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/11 2011/05/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA(3/12)-VGA CORE

VGA(3/12)-VGA CORE

VGA(3/12)-VGA CORE

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

16 59Monday, November 01, 2010

16 59Monday, November 01, 2010

16 59Monday, November 01, 2010

1

0.1

0.1

0.1

of

of

of

5

4.7U_0603_6.3V6K

1

2

CV120

CV120

DIS@

DIS@

4.7U_0603_6.3V6K

1

2

1

CV104

CV104

2

1

CV83

CV83

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV125

CV125

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

RV51 1K_0402_1%

RV51 1K_0402_1%

1 2

RV52 1K_0402_1%

RV52 1K_0402_1%

FOR OPTIMUS

+VRAM_1.5VS

CV82

CV82

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

D D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VRAM_1.5VS

C C

B B

+1.05VS_DGPU

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

DIS@

DIS@

1

2

LV5

LV5

CV124

CV124

1

CV136

CV136

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU(below 150mils)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

CV123

CV123

CV126

CV126

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Under GPU(below 150mils)

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

CV119

CV119

CV118

CV118

DIS@

DIS@

DIS@

2

DIS@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0618 FOR OPTIMUS, CV120 POP RESISITOR

+1.8VS

LV8

A A

LV8

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

DIS@

DIS@

12

5

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

1

CV133

CV133

DIS@

DIS@

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV134

CV134

DIS@

DIS@

2

1

CV135

CV135

DIS@

DIS@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

CV213

CV213

DIS@

DIS@

FOR OPTIMUS

4

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CV197

CV197

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV102

CV102

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

1 2

RV96 1K_0402_1%

RV96 1K_0402_1%

@

@

RV107 10K_0402_5%RV107 10K_0402_5%

RV109 10K_0402_5%RV109 10K_0402_5%

RV99 10K_0402_5%RV99 10K_0402_5%

@

@

RV97 10K_0402_5%RV97 10K_0402_5%

1 2

RV53 1K_0402_1%RV53 1K_0402_1%

220mA

+IFPAB_PLLVDD

CV120

CV120
10K_0402_5%

10K_0402_5%

OPT@

OPT@

440mA

+IFPAB_IOVDD

CV213

CV213
10K_0402_5%

10K_0402_5%

OPT@

OPT@

4

1

CV214

CV214

2

1

CV103

CV103

2

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

12

+IFPC_IOVDD

12

+IFPD_PLLVDD

12

+IFPD_IOVDD

12

+IFPEF_PLLVDD

+IFPE_IOVDD

3.5A

J23
J24

J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27

AJ28

B18

E21

G17
G18
G22

G8

G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34

W27

Y27

AK9

AJ11

AG9

AG10

AJ9

AK7

AJ8

AC6
AB6

AK8

AJ6
AL1

AE7
AD7

+3VS_DGPU

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

+1.05VS_DGPU

BLM18PG181SN1D_0603

BLM18PG181SN1D_0603

3

UV1E

UV1E

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

IFPAB_PLLVDD
IFPAB_RSET

IFPA_IOVDD
IFPB_IOVDD

IFPC_PLLVDD
IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD
IFPD_RSET

IFPD_IOVDD

IFPEF_PLLVDD
IFPEF_RSET

IFPE_IOVDD
IFPF_IOVDD

@

@

LV7

LV7

HDMI@

HDMI@

Part 5 of 7

Part 5 of 7

N12P-GV1-A1_BGA_973P

N12P-GV1-A1_BGA_973P

12

1

CV128

CV128

HDMI@

HDMI@

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

POWER

POWER

PEX_PLLVDD

PEX_SVDD_3V3

PEX_SVDD_3V3_NC

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

CV129

CV129

HDMI@

HDMI@

2

2500mA

0.1U_0402_16V4Z

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

AK16
AK17
AK21
AK24
AK27

AG14

AG19
F7

J10
J11
J12
J13
J9

P9
R9
T9
U9

AA9
AB9
W9
Y9

Under GPU(below 150mils)

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

120mA

+PEX_PLLVDD

240mA (120mA each)

120mA(12~16mils)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV130

CV130

HDMI@

HDMI@

2

CV131

CV131

HDMI@

HDMI@

Close to Pin

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV111

CV111

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV220

CV220

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RV124

RV124
10K_0402_5%

10K_0402_5%

1 2

RV125

RV125
10K_0402_5%

10K_0402_5%

1 2

1

CV87

CV87

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CV93

CV93

2

Under GPU(below 150mils)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

CV217

CV217

CV216

CV216

2

2

Under GPU(below 150mils)

+IFPEF_PLLVDD

1

CV215

CV215

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HDMI@

HDMI@

2

Under GPU(below 150mils)

LV10

LV10

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

12

HDMI@

HDMI@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

CV142

CV142

HDMI@

HDMI@

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

CV144

CV144

HDMI@

HDMI@

1

CV145

CV145

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HDMI@

HDMI@

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

CV143

CV143

HDMI@

HDMI@

2

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

+IFPE_IOVDD

CV145

CV145
10K_0402_5%

10K_0402_5%

@

@

FOR OPTIMUS

CV88

CV88

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CV94

CV94

1U_0402_6.3V4Z

1U_0402_6.3V4Z

CV105

CV105

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

CV112

CV112

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

220mA

CV215

CV215
10K_0402_5%

10K_0402_5%

@

@

FOR OPTIMUS

570mA

2

1

2

1

2

1

2

2

CV89

CV89

CV95

CV95

CV106

CV106

1

2

CV113

CV113

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

CV90

CV90

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

CV96

CV96

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

CV107

CV107

2

+3VS_DGPU

1

CV114

CV114

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

CV91

CV91

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CV97

CV97

2

LV4

LV4

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

CV108

CV108

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

CV110

CV110

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

CV3

CV92

CV92

CV98

CV98

+3VS_DGPU

CV3

22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

CV4

CV4

22U_0805_6.3V6M

22U_0805_6.3V6M

2

12

1

CV109

CV109

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

1

CV219

CV219

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

VGA(4/12)-POWER

VGA(4/12)-POWER

VGA(4/12)-POWER

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

+1.05VS_DGPU

+1.05VS_DGPU

+1.05VS_DGPU

17 59Monday, November 01, 2010

17 59Monday, November 01, 2010

17 59Monday, November 01, 2010

of

of

of

0.1

0.1

0.1

5

D D

C C

B B

A A

5

4

UV1F

UV1F

B3

GND_0

B6

GND_1

B9

GND_2

B12

GND_3

B15

GND_4

B21

GND_5

B24

GND_6

B27

GND_7

B30

GND_8

B33

GND_9

C2

GND_10

C34

GND_11

E6

GND_12

E9

GND_13

E12

GND_14

E15

GND_15

E18

GND_16

E24

GND_17

E27

GND_18

E30

GND_19

F2

GND_20

F31

GND_21

F34

GND_22

F5

GND_23

J2

GND_24

J5

GND_25

J31

GND_26

J34

GND_27

K9

GND_28

L9

GND_29

M2

GND_30

M5

GND_31

M11

GND_32

M13

GND_33

M15

GND_34

M17

GND_35

M19

GND_36

M21

GND_37

M23

GND_38

M25

GND_39

M31

GND_40

M34

GND_41

N11

GND_42

N12

GND_43

N13

GND_44

N14

GND_45

N15

GND_46

N16

GND_47

N17

GND_48

N18

GND_49

N19

GND_50

N20

GND_51

N21

GND_52

N22

GND_53

N23

GND_54

N24

GND_55

N25

GND_56

P12

GND_57

P14

GND_58

P16

GND_59

P18

GND_60

P20

GND_61

P22

GND_62

P24

GND_63

R2

GND_64

R5

GND_65

R31

GND_66

R34

GND_67

T11

GND_68

T13

GND_69

T15

GND_70

T17

GND_71

T19

GND_72

T21

GND_73

T23

GND_74

T25

GND_75

U11

GND_76

U12

GND_77

U13

GND_78

U14

GND_79

U15

GND_80

U16

GND_81

U17

GND_82

U18

GND_83

U19

GND_84

U20

GND_85

U21

GND_86

U22

GND_87

U23

GND_88

U24

GND_89

U25

GND_90

V2

GND_91

V5

GND_92

V9

GND_93

V12

GND_94

V14

GND_95

V16

GND_96

N12P-GV1-A1_BGA_973P

N12P-GV1-A1_BGA_973P

@

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

Part 6 of 7

Part 6 of 7

3

V18

GND_97

V20

GND_98

V22

GND_99

V24

GND_100

V31

GND_101

Y11

GND_102

Y13

GND_103

Y15

GND_104

Y17

GND_105

Y19

GND_106

Y21

GND_107

Y23

GND_108

Y25

GND_109

AA2

GND_110

AA5

GND_111

AA11

GND_112

AA12

GND_113

AA13

GND_114

AA14

GND_115

AA15

GND_116

AA16

GND_117

AA17

GND_118

AA18

GND_119

AA19

GND_120

AA20

GND_121

AA21

GND_122

AA22

GND_123

AA23

GND_124

AA24

GND_125

AA25

GND_126

AA34

GND_127

AB12

GND_128

AB14

GND_129

AB16

GND_130

AB18

GND_131

AB20

GND_132

AB22

GND_133

AB24

GND_134

AC9

GND_135

AD2

GND_136

AD5

GND_137

AD11

GND_138

AD13

GND_139

AD15

GND_140

AD17

GND_141

AD21

GND_142

AD23

GND_143

AD25

GND_144

AD31

GND_145

AD34

GND_146

AE11

GND_147

GND

GND

AE12

GND_148

AE13

GND_149

AE14

GND_150

AE15

GND_151

AE16

GND_152

AE17

GND_153

AE18

GND_154

AE19

GND_155

AE20

GND_156

AE21

GND_157

AE22

GND_158

AE23

GND_159

AE24

GND_160

AE25

GND_161

AG2

GND_162

AG5

GND_163

AG31

GND_164

AG34

GND_165

AK2

GND_166

AK5

GND_167

AK14

GND_168

AK31

GND_169

AK34

GND_170

AL6

GND_171

AL9

GND_172

AL12

GND_173

AL15

GND_174

AL18

GND_175

AL21

GND_176

AL24

GND_177

AL27

GND_178

AL30

GND_179

AN2

GND_180

AN34

GND_181

AP3

GND_182

AP6

GND_183

AP9

GND_184

AP12

GND_185

AP15

GND_186

AP18

GND_187

AP21

GND_188

AP24

GND_189

AP27

GND_190

AP30

GND_191

AP33

GND_192

Compal Secret Data

Compal Secret Data

2010/05/11 2011/05/11

2010/05/11 2011/05/11

2010/05/11 2011/05/11

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA(5/12)-GND

VGA(5/12)-GND

VGA(5/12)-GND

PBL11 LA6732P M/B

PBL11 LA6732P M/B

PBL11 LA6732P M/B

1

0.1

0.1

of

18 59Monday, November 01, 2010

of

18 59Monday, November 01, 2010

of

18 59Monday, November 01, 2010

1

0.1