COMPAL LA-6731P Schematics

5

D D

4

3

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1

Compal Confidential

C C

PBL10 Project

LA-6731P

B B

SchematicREV1.0

Intel Sandy Bridge/Cougar Point(UMA)

2010-12-06 Rev 1.0

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

145Wednesday, March 09, 2011

145Wednesday, March 09, 2011

145Wednesday, March 09, 2011

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Compal Confidential
Model Name : PBL10
File Name : LA-6731P

Mobile

Sandy Bridge

CK505

Clock Generator
ICS9LRS

Page 14

Fan Control

page 5

CPU Dual Core

D D

Socket-rPGA989

37.5mm*37.5mm

page 5,6,7,8,9,10,11

DMI X4

LCD Conn.

CRT

C C

HDMI Conn.

page 15

page 16

page 17

HDMI
Level Shifter

PCIeMini Card
WLAN & BT 2.0

USB port 5
PCIe port 2

page 29

page 17

USB

PCIe 1x

1.5V 2.5GHz(250MB/s)

Intel Cougar Point

FCBGA989

25mm*25mm

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333

FDI X4

USB/B Right

USB port 0,1

page 29

Int. Camera

USB

SATA port 1

5V 1.5GHz(150MB/s)

SATA port 4

5V 1.5GHz(150MB/s)

USB port 11

page 15

SATA HDD0

SATA ODD

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

USB/B Left

USB port 2

page 29

RTS5138 3IN1

USB port 3

page 27

page 27

page 32

page 12,13

SPI ROM

B B

USB&Audio/B

Power/B

Touch Pad/B

page 29

page 34

page 34

RJ45

page 30

RTL8111E Giga
RTL8105E 10/100

PCIe port 3

page 30

PCIe 1x

1.5V 2.5GHz(250MB/s)

page 18,19,20,21
22,23,24,25,26

HD Audio

3.3V 24.576MHz/48Mhz

page 28

HDA Codec

ALC259

page 31

ENE KB930

RTC CKT.

page 36

A A

DC/DC Interface CKT.

page 35

Security Classification

Security Classification

Power Circuit DC/DC

page 36,37,38,39,
40,41,42,43,44

5

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Int.KBD

page 32

page 33

SPI ROM

page 32

Compal Secret Data

Compal Secret Data

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Int.

MIC CONN

page 15

2

MIC CONN

page 29

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

HP CONN

page 29

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

SPK CONN

page 31

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+3VL

B+

+5VL

B+

UP6182CQAG

SUSP

SI4800BDY

RB161M

USB_EN#

RB491D

RT9715BGS

C C

USB_EN#

RT9715BGS

SUSP#

SY8033BDBC

+5VALW

+5VS

+HDMI_5V_OUT

+CRT_VCC

+USB_VCCA

+USB_VCCB

+1.8VS

POK

TP0610K

ISL95831CRZ

SYSON

G5603RU1U

SUSP#

G5603RU1U

SUSP

UP7711U8

SUSP#

G5603RU1U

SUSP

SI4856ADY

+VSB

+CPU_CORE
+VGFX_CORE

+1.5V

+1.5VS

+1.05VS_VCCP

+0.75VS

+VCCSA

+3VALW

PCH_PWR_EN#

SI4800BDY

+3VALW_PCH

SUSP

B B

SI4800BDY

VGA_ENVDD

AO3413

+3VS

+LCD_VDD

+3V_LAN

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

345Wednesday, March 09, 2011

345Wednesday, March 09, 2011

345Wednesday, March 09, 2011

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Voltage Rails

S1

Power Plane Description
VIN

Adapter power supply (19V)

S3 S5

N/A N/A N/A

BATT+ Battery power supply (12.6V) N/A N/A N/A

D D

B+
+CPU_CORE
+VGA_CORE

AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for GPU

ON
ON

OFF
OFF

N/AN/AN/A
OFF

OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
+1.05VS_VCCP

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
+1.5V
+1.5VS

+1.5VP to +1.5V power rail for DDRIII ON ON OFF

+1.5V to +1.5VS switched power rail

ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF

ON OFF OFF

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

PCH SM Bus address

Device

Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)

DDR DIMM0
DDR DIMM2

Address

1101 0010b

1001 000Xb
1001 010Xb

+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VALW +3VALW always on power rail

ON
ON

OFF

OFF

ON ON*

BOM configu table

+3VALW_EC +3VALW always to KBC ON ON ON*

C C

+3VALW_PCH
+3VS
+5VALW
+5VALW_PCH
+5VS +5VALW to +5VS switched power rail OFFON OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

+3V_LAN

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON ON
ON ON

OFF

ON
ON

ON ON*

ON ON

ON
ON

ON*
ON*
OFF

ON*

ONON

SKU DescriptionBom config

46196830L01

1

46196830L02

2

DA6@/HDMI@/8105E@/PCH@

DA6@/HDMI@/8111E@/PCH@

3
4
5
6

SIGNAL

STATE

Full ON

S1(Power On Suspend)

B B

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

HIGH

ON

ON

ON

OFF

OFF

ON ON

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

ON

ON

ON

ON

ON

7
8

Bom configu(HDMI@/8105E@/8111E@/DA6@/DAZ@/45@)

PCH And PCBA table

U4

U4
BD82HM65 SLH9D B2 FCBGA 989P PCH

BD82HM65 SLH9D B2 FCBGA 989P PCH

PCH

PCH@

PCH@

EC SM Bus2 address

Device

PBL10 UMA DUAL 10-100

PBL10 UMA DUAL GIGA LAN

ZZZ

DA4@ZZZ

DA6@ZZZ

ZZZ

DAZ@ZZZ

DAZ@

DA6@ ZZZ

DA4@ZZZ

DA2@ZZZ

DA2@

PCB

PCB LS-6732P REV10

PCB LA-6731P REV10

PCB LA-6731P REV10

PCB LA-6731P REV10

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCB LA-6731P REV10

2

PCB LS-6732P REV10

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PCB LS-6731P REV10

PCB LS-6731P REV10

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

445Wednesday, March 09, 2011

445Wednesday, March 09, 2011

445Wednesday, March 09, 2011

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H_PROCHOT#
H_THRMTRIP#
H_PM_SYNC

PM_SYS_PWRGD_BUF

BUF_CPU_RST#

C C

+1.05VS_VCCP

Processor Pullups

R47 62_0402_5%R47 62_0402_5%

12

R50 10K_0402_5%R50 10K_0402_5%

1 2

C312 330P_0402_50V7K

C312 330P_0402_50V7K

CLOSE TO PCH, EMI DEMAND

@

@

@

@

1 2

C234 0.1U_0402_16V4Z

C234 0.1U_0402_16V4Z

@

@

1 2

C235 0.1U_0402_16V4Z

C235 0.1U_0402_16V4Z

@

@

1 2

C236 0.1U_0402_16V4Z

C236 0.1U_0402_16V4Z

@

@

1 2

C238 0.1U_0402_16V4Z

C238 0.1U_0402_16V4Z

@

@

1 2

C243 0.1U_0402_16V4Z

C243 0.1U_0402_16V4Z

12

EMI Demand

H_PROCHOT#

H_CPUPWRGD_R

4

JCPUB

JCPUB

H_SNB_IVB#22

R48

R48

R52

R52

R54

R54

R58

R58

R64

R64

SKTOCC#

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THEMTRIP#_R

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

T68 PADT68 PAD

T5 PADT5 PAD

0_0402_5%

0_0402_5%

H_PECI23,33

H_PROCHOT#33

H_THRMTRIP#23

H_PM_SYNC20

H_CPUPWRGD23

1 2

56_0402_5%

56_0402_5%

1 2

0_0402_5%

0_0402_5%

1 2

0_0402_5%

0_0402_5%

1 2

0_0402_5%

0_0402_5%

1 2

R65

R65

130_0402_5%

130_0402_5%

1 2

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

3

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

CLK_CPU_DMI_R

A28

CLK_CPU_DMII#_R

A27

R234 1K_0402_5%R234 1K_0402_5%

A16

R240 1K_0402_5%R240 1K_0402_5%

A15

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

AP29
AP27

XDP_TCK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI_R

AR28

TDI

XDP_TDO_R

AP26

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

1 2
1 2

2

R41 0_0402_5%@R41 0_0402_5%@

1 2

R42 0_0402_5%@R42 0_0402_5%@

1 2

R43 0_0402_5%R43 0_0402_5%

1 2

R44 0_0402_5%R44 0_0402_5%

1 2

+1.05VS_VCCP

H_DRAMRST# 7

CLK_BUF_CPU_BCLK 14
CLK_BUF_CPU_BCLK# 14

CLK_CPU_DMI 19
CLK_CPU_DMI# 19

DDR3 Compensation Signals

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PU/PD for JTAG signals

XDP_TMS

R55 51_0402_5%R55 51_0402_5%

XDP_TDI_R

R56 51_0402_5%R56 51_0402_5%

XDP_TDO_R

R57 51_0402_5%R57 51_0402_5%

XDP_TCK

R59 51_0402_5%R59 51_0402_5%

XDP_TRST#

R62 51_0402_5%R62 51_0402_5%

R266 1K_0402_5%R266 1K_0402_5%

1 2

XDP_DBRESET#

1

R49 140_0402_1%R49 140_0402_1%
R51 25.5_0402_1%R51 25.5_0402_1%
R53 200_0402_1%R53 200_0402_1%

12
12
12

+1.05VS_VCCP

12
12
12
12
12

+3VS

XDP_DBRESET# 18,20

Buffered reset to CPU

+3VS

C83

C83

R82

R82

0_0402_5%

0_0402_5%

1 2

5

+1.05VS_VCCP

12

R60

R60
75_0402_5%

75_0402_5%

R66

R66

43_0402_1%

43_0402_1%

1 2

+3VALW

1

2

1

B

2

A

SUSP35,42

12

@

@
R68

R68
0_0402_5%

0_0402_5%

U3

U3
74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

5

P

4

O

G

3

SUSP

2

G

G

+1.5V_CPU_VDDQ

12

@

@
R83

R83
39_0402_5%

39_0402_5%

13

D

D

@

@
Q4

Q4
2N7002_SOT23

2N7002_SOT23

S

S

12

R81

R81
200_0402_5%

200_0402_5%

PM_SYS_PWRGD_BUF

4

FAN Control Circuit

+5VS

1A

2

C863

C863

10U_0805_10V4Z

10U_0805_10V4Z

U58

U58

1

EN

2

1

C17

C17
10U_0805_10V4Z

10U_0805_10V4Z

2

VIN

3

VOUT

4

VSET

G996P11U SOP 8P

G996P11U SOP 8P

+FAN1

EN_DFAN133

10mil

8

GND

7

GND

6

GND

5

GND

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

+FAN1

2

C864

@C864

@
1000P_0402_50V7K

1000P_0402_50V7K

1

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

JFAN

JFAN

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

ACES_85205-03001

CONN@

CONN@

R219 10K_0402_5%R219 10K_0402_5%

1

C865

@C865

@

0.01U_0402_25V7K

0.01U_0402_25V7K

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

+3VS

FAN_SPEED1 33

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

401968

401968

401968

545Wednesday, March 09, 2011

545Wednesday, March 09, 2011

1

545Wednesday, March 09, 2011

D

D

D

of

of

of

1

C82

B B

1

PLT_RST#

2

PLT_RST# 22,29,30,33

C82

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

5

U2

U2

P

NC

4

Y

A

G

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

3

BUFO_CPU_RST# BUF_CPU_RST#

Follow DG 0.71

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A A

SYS_PWROK20

PM_DRAM_PWRGD20

5

4

3

2

1

D D

+1.05VS_VCCP

12

R17

R17

24.9_0402_1%

JCPUA

JCPUA

EDP_COMP

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0

CONN@

CONN@

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

DMI_CRX_PTX_N020
DMI_CRX_PTX_N120
DMI_CRX_PTX_N220
DMI_CRX_PTX_N320

DMI_CRX_PTX_P020
DMI_CRX_PTX_P120
DMI_CRX_PTX_P220
DMI_CRX_PTX_P320

DMI_CTX_PRX_N020
DMI_CTX_PRX_N120
DMI_CTX_PRX_N220
DMI_CTX_PRX_N320

DMI_CTX_PRX_P020

R185 1K_0402_5%@R185 1K_0402_5%@

1 2

DMI_CTX_PRX_P120
DMI_CTX_PRX_P220
DMI_CTX_PRX_P320

FDI_CTX_PRX_N020
FDI_CTX_PRX_N120
FDI_CTX_PRX_N220
FDI_CTX_PRX_N320
FDI_CTX_PRX_N420
FDI_CTX_PRX_N520
FDI_CTX_PRX_N620
FDI_CTX_PRX_N720

FDI_CTX_PRX_P020
FDI_CTX_PRX_P120
FDI_CTX_PRX_P220
FDI_CTX_PRX_P320
FDI_CTX_PRX_P420
FDI_CTX_PRX_P520
FDI_CTX_PRX_P620
FDI_CTX_PRX_P720

FDI_FSYNC020
FDI_FSYNC120

FDI_INT20
FDI_LSYNC020

FDI_LSYNC120

C C

+1.05VS_VCCP

eDP_COMPIO and ICOMPO signals

B B

should be shorted near balls
and routed with typical
impedance <25 mohms

+1.05VS_VCCP

12

R18

R18

24.9_0402_1%

24.9_0402_1%

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

PEG_COMP

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

24.9_0402_1%

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 mohms

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

D

D

D

of

of

of

645Wednesday, March 09, 2011

645Wednesday, March 09, 2011

645Wednesday, March 09, 2011

5

JCPUC

JCPUC

4

3

JCPUD

JCPUD

2

1

DDR_A_D[0..63]12

D D

C C

B B

DDR_A_BS012
DDR_A_BS112
DDR_A_BS212

DDR_A_CAS#12
DDR_A_RAS#12
DDR_A_WE#12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10
AF10

F10
G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

C5
D5
D3
D2
D6
C6
C2
C3

F8
G9

F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2

M8
N8

N7
M9

N9
M7

V6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

RSVD_TP[10]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 12
M_CLK_DDR#0 12
DDR_CKE0_DIMMA 12

M_CLK_DDR1 12
M_CLK_DDR#1 12
DDR_CKE1_DIMMA 12

DDR_CS0_DIMMA# 12
DDR_CS1_DIMMA# 12

M_ODT0 12
M_ODT1 12

DDR_A_DQS#[0..7] 12

DDR_A_DQS[0..7] 12

DDR_A_MA[0..15] 12 DDR_B_MA[0..15] 13

DDR_B_D[0..63]13

DDR_B_BS013
DDR_B_BS113
DDR_B_BS213

DDR_B_CAS#13
DDR_B_RAS#13
DDR_B_WE#13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AM5
AM6
AR3

AN3
AN2
AN1

AN9

AN8
AR6
AR5
AR9

AJ11

AH11

AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA10

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]

AP3

SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]
SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

RSVD_TP[17]
RSVD_TP[18]

RSVD_TP[19]
RSVD_TP[20]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 13
M_CLK_DDR#2 13
DDR_CKE2_DIMMB 13

M_CLK_DDR3 13
M_CLK_DDR#3 13
DDR_CKE3_DIMMB 13

DDR_CS2_DIMMB# 13
DDR_CS3_DIMMB# 13

M_ODT2 13
M_ODT3 13

DDR_B_DQS#[0..7] 13

DDR_B_DQS[0..7] 13

Sandy Bridge_rPGA_Rev1p0

Deciphered Date

Deciphered Date

Deciphered Date

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

of

of

of

745Wednesday, March 09, 2011

745Wednesday, March 09, 2011

745Wednesday, March 09, 2011

D

D

D

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

+1.5V

R84

@R84

@
0_0402_5%

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

Q5

Q5
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

C84

C84

0.047U_0402_16V4Z

0.047U_0402_16V4Z

2

H_DRAMRST#5

R87

A A

R88

R88

0_0402_5%

0_0402_5%

DRAMRST_CNTRL_PCH19

DRAMRST_CNTRL_EC33

1 2

R89 0_0402_5%@R89 0_0402_5%@

5

4.99K_0402_1%

4.99K_0402_1%

1 2

R87

DRAMRST_CNTRL

R85

R85

1K_0402_5%

1K_0402_5%

12

4

R86

R86
1K_0402_5%

1K_0402_5%

1 2

DDR3_DRAMRST# 12,13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

5

D D

4

3

2

1

JCPUE

JCPUE

L7

RSVD28

AG7

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

KEY

AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

T10PAD T10PAD

CLK_RES_ITP 19
CLK_RES_ITP# 19

T6 PADT6 PAD
T7 PADT7 PAD
T8 PADT8 PAD
T9 PADT9 PAD

12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

CPU_RSVD6
CPU_RSVD7

12

R93

R93
1K_0402_1%

1K_0402_1%

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

RESERVED

RESERVED

T63 PADT63 PAD
T60 PADT60 PAD
T62 PADT62 PAD
T59 PADT59 PAD
T61 PADT61 PAD
T74 PADT74 PAD
T76 PADT76 PAD

T75 PADT75 PAD
T78 PADT78 PAD
T80 PADT80 PAD
T77 PADT77 PAD
T85 PADT85 PAD
T83 PADT83 PAD
T84 PADT84 PAD
T82 PADT82 PAD
T79 PADT79 PAD
T81 PADT81 PAD

C C

R92

R92

1K_0402_1%

1K_0402_1%

B B

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

CFG7

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is

*

connected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1: (Default) PEG Train immediately following xxRESETB
de assertion

0: PEG Wait for BIOS for training

R187 1K_0402_5%@R187 1K_0402_5%@

1 2

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

D

D

D

of

of

of

845Wednesday, March 09, 2011

845Wednesday, March 09, 2011

845Wednesday, March 09, 2011

5

+CPU_CORE

Bottom Socket Cacity

10U_0805_6.3V6M

10U_0805_6.3V6M

C99

C99

10U_0805_6.3V6M

10U_0805_6.3V6M

C93

C93

C115

22U_0805_6.3V6M

C115

22U_0805_6.3V6M

C123

22U_0805_6.3V6M

C123

22U_0805_6.3V6M

C128

22U_0805_6.3V6M

C128

22U_0805_6.3V6M

1

2

1

2

1

2

1

2

1

+

+

2

12

C85

C85

12

C94

C94

C116

22U_0805_6.3V6M

C116

22U_0805_6.3V6M

C124

22U_0805_6.3V6M

C124

22U_0805_6.3V6M

C129

22U_0805_6.3V6M

C129

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C133

C133

330U_D2_2VM_R4.5M

330U_D2_2VM_R4.5M

C137

C137

12

D D

+CPU_CORE

C C

+CPU_CORE

B B

10U_0805_6.3V6M

10U_0805_6.3V6M

12

10U_0805_6.3V6M

10U_0805_6.3V6M

Top Socket Edge 22U * 11
Top Socket Cavity 22U * 8

1

2

1

2

1

2

12

C86

C86

10U_0805_6.3V6M

10U_0805_6.3V6M

12

C95

C95

10U_0805_6.3V6M

10U_0805_6.3V6M

C118

22U_0805_6.3V6M

C118

22U_0805_6.3V6M

1

2

C125

22U_0805_6.3V6M

C125

22U_0805_6.3V6M

1

2

C130

22U_0805_6.3V6M

C130

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C134

C134

2

C138

330U_D2_2V_Y+C138

330U_D2_2V_Y

1

+

2

10U_0805_6.3V6M

10U_0805_6.3V6M

12

C87

C87

10U_0805_6.3V6M

10U_0805_6.3V6M

12

C96

C96

C119

22U_0805_6.3V6M

C119

22U_0805_6.3V6M

1

2

C126

22U_0805_6.3V6M

C126

22U_0805_6.3V6M

1

2

C131

22U_0805_6.3V6M

C131

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C135

C135

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

C139

C139

+

+

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

2

Bottom Socket Edge

change C137 from 440U to 330U for PWR demand--1201

A A

12

C100

C100

10U_0805_6.3V6M

10U_0805_6.3V6M

12

C97

C97

@ C98

@

C120

22U_0805_6.3V6M

C120

22U_0805_6.3V6M

1

2

C127

22U_0805_6.3V6M

C127

22U_0805_6.3V6M

1

2

C132

22U_0805_6.3V6M

C132

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C136

C136

2

C140

330U_D2_2V_Y+C140

330U_D2_2V_Y

4

12

C98

10U_0805_6.3V6M

10U_0805_6.3V6M

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

3

POWER

JCPUF

JCPUF

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

POWER

PEG AND DDR

PEG AND DDR

CORE SUPPLY

CORE SUPPLY

VCCIO_SENSE

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

VSSIO_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

8.5A94A

VCCSENSE_R
VSSSENSE_R

Top Socket Cacity 22U *9
Bottom Socket Cacity 22U *10

+1.05VS_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C101

C101

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C106

C106

2

2

12

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R103 0_0402_5%R103 0_0402_5%

1 2

R104 0_0402_5%R104 0_0402_5%

1 2

VCCIO_SENSE 41

1 2

R117 10_0402_5%R117 10_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

R97

R97
130_0402_5%

130_0402_5%

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C102

C102

2

1

C107

C107

2

43_0402_1%

43_0402_1%

1 2

R100 0_0402_5%R100 0_0402_5%

1 2

R101 0_0402_5%R101 0_0402_5%

1 2

C89

C89

C88

C88

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

@

@

C109

C109

C108

C108

2

+1.05VS_VCCP+1.05VS_VCCP

12

R99

R99

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C103

C103

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C110

C110

2

R98

R98
75_0402_5%

75_0402_5%

12

R102

R102
100_0402_1%

100_0402_1%

12

R105

R105
100_0402_1%

100_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C90

C90

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C111

C111

2

Place the PU
resistors close to CPU

VCCSENSE 44
VSSSENSE 44

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

2

1

2

C91

C91

C104

C104

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

@

@

C112

C112

C113

C113

2

330U_D2_2V_Y

330U_D2_2V_Y

1

C117

C117

+

+

2

VR_SVID_ALRT# 44
VR_SVID_CLK 44
VR_SVID_DAT 44

1

+1.05VS_VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C92

C92

C105

C105

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

C114

C114

2

330U_D2_2V_Y

330U_D2_2V_Y

1

1

C121

C121

+

+

+

2

C122

@+C122

@
330U_D2_2V_Y

330U_D2_2V_Y

2

Place the PU
resistors close to VR

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

of

of

of

945Wednesday, March 09, 2011

945Wednesday, March 09, 2011

945Wednesday, March 09, 2011

D

D

D

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

+VSB

+3VALW

12

R108

R108
100K_0402_5%

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C145

C145

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C154

C154

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C159

C159

1

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

100K_0402_5%

RUN_ON_CPU1.5VS3#

61

Q7A

Q7A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

22U_0805_6.3V6M

22U_0805_6.3V6M

C146

C146

C147

C147

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C155

C155

C151

C151

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C161

C161

C160

C160

C237

C237

1

1

@

@

2

2

1

@

@

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C148

C148

22U_0805_6.3V6M

22U_0805_6.3V6M

C152

C152

22U_0805_6.3V6M

22U_0805_6.3V6M

C162

C162

@

@

D D

CPU1.5V_S3_GATE33

SUSP#28,33,35,39,41,43

+VGFX_CORE

Top Socket Cacity 22U *2
Top Socket Edge 22U *6
Bottom Socket Cacity 22U *2

C C

B B

Bottom Socket Edge 22U *6

+VGFX_CORE

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

C157

C157

+

+

2

Bottom Socket Edge

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C232

C232

+

+

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

C158

C158

@

@

R110

R110

0_0402_5%

0_0402_5%

1 2

R111

@R111

@

0_0402_5%

0_0402_5%

1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

C153

C153

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C149

C149

1

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C144

C144

C150

C150

C233

C233

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

@

@

EMI DEMAND

+1.8VS

R118

R118

0_0805_5%

0_0805_5%

1 2

A A

10U_0603_6.3V6M

10U_0603_6.3V6M

C175

330U_D2_2V_Y

C175

330U_D2_2V_Y

1

1

+

+

@

@

2

2

C176

C176

C177

1U_0402_6.3V6K

C177

1U_0402_6.3V6K

1

2

12

3

5

4

26A

+1.8VS_VCCPLL

C178

1U_0402_6.3V6K

C178

1U_0402_6.3V6K

1

2

R106

R106
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

Q7B

Q7B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

330K_0402_5%

330K_0402_5%

JCPUG

JCPUG

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24
AL23
AL21
AL20
AL18

AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17
AH24
AH23
AH21
AH20
AH18
AH17

B6
A6
A2

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

Bottom Socket Edge

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCCPLL1
VCCPLL2
VCCPLL3

R109

R109

Q6

Q6

AO4728L_SO8

AO4728L_SO8

8
7
6
5

12

1
2
3

4

D

1

C142

C142

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

POWER

POWER

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

D

S

S

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

R107

R107
470_0603_5%

470_0603_5%

1 2
13

RUN_ON_CPU1.5VS3#

2

G

G

Q8

Q8
2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

FC_C22

VCCSA_VID1

AK35
AK34

AL1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

10A

6A

VCC_AXG_SENSE 44
VSS_AXG_SENSE 44

+V_SM_VREF should
have 20 mil trace width

+V_SM_VREF_CNT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Bottom Socket Cacity 10U *2
Bottom Socket Edge 10U *1

H_FC_C22

1 2

+1.5V_CPU_VDDQ +1.5V

C141 0.1U_0402_10V7KC141 0.1U_0402_10V7K

C143 0.1U_0402_10V7KC143 0.1U_0402_10V7K

RUN_ON_CPU1.5VS3# 42

12

12

Follow DG 0.71 page 6

R113

R113

0_0402_5%

0_0402_5%

1

C156

C156

2

RUN_ON_CPU1.5VS3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C163

C163

1

C164

C164

2

2

1

2

Bottom Socket Edge

+VCCSA

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

C170

C170

C171

C171

2

2

2

12

R119

R119
10K_0402_5%

10K_0402_5%

R120

@R120

@

0_0402_5%

0_0402_5%

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

2

10U_0603_6.3V6M

1

C166

C166

C167

C167

2

+VCCSA

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

C173

C173

1

+

+

2

VCCSA_SENSE 43

VCCSA_SEL 43

10U_0603_6.3V6M

10U_0603_6.3V6M

C165

C165

10U_0603_6.3V6M

10U_0603_6.3V6M

C172

C172

12

+V_SM_VREF

3

Q9

@Q9

@

AP2302GN-HF_SOT23-3

AP2302GN-HF_SOT23-3

+1.5V_CPU_VDDQ

PJ4

PJ4

2

112

JUMP_43X118@

JUMP_43X118@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

+

+

C169

C169

C168

C168

330U_D2_2V_Y

330U_D2_2V_Y

2

2

R116 0_0402_5%R116 0_0402_5%

C174

C174
330U_D2_2V_Y

330U_D2_2V_Y

2

1 2

PJ5

PJ5

112

JUMP_43X118@

JUMP_43X118@

+1.5V_CPU_VDDQ

12

R114

R114
1K_0402_1%

1K_0402_1%

12

R115

R115
1K_0402_1%

1K_0402_1%

+1.5V

VCCSA_SENSE

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

D

D

D

of

of

of

10 45Wednesday, March 09, 2011

10 45Wednesday, March 09, 2011

10 45Wednesday, March 09, 2011

5

JCPUH

D D

C C

B B

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10

AR25
AR22
AR19
AR16
AR13
AR10

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

JCPUH

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AN7

VSS43

AN4

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

AK7

VSS78

AK4

VSS79
VSS80

VSS

VSS

4

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH26

VSS97

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

AE27

VSS119

AE26

VSS120

AE9

VSS121

AD7

VSS122

AC9

VSS123

AC8

VSS124

AC6

VSS125

AC5

VSS126

AC3

VSS127

AC2

VSS128

AB35

VSS129

AB34

VSS130

AB33

VSS131

AB32

VSS132

AB31

VSS133

AB30

VSS134

AB29

VSS135

AB28

VSS136

AB27

VSS137

AB26

VSS138

Y9

VSS139

Y8

VSS140

Y6

VSS141

Y5

VSS142

Y3

VSS143

Y2

VSS144

W35

VSS145

W34

VSS146

W33

VSS147

W32

VSS148

W31

VSS149

W30

VSS150

W29

VSS151

W28

VSS152

W27

VSS153

W26

VSS154

U9

VSS155

U8

VSS156

U6

VSS157

U5

VSS158

U3

VSS159

U2

VSS160

3

JCPUI

JCPUI

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

2

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

1

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Sandy Bridge_rPGA_Rev1p0

Sandy Bridge_rPGA_Rev1p0
CONN@

CONN@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

D

D

D

of

of

of

11 45Wednesday, March 09, 2011

11 45Wednesday, March 09, 2011

11 45Wednesday, March 09, 2011

5

4

3

2

1

+1.5V

12

R122

R122
1K_0402_1%

1K_0402_1%

+V_DDR_REF

5

12

R123

R123
1K_0402_1%

1K_0402_1%

+3VS

2

G

G

1 3

D

S

D

S

Q1

Q1

2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

+3VS

2

G

G

1 3

D

S

D

S

Q2

Q2

2N7002E-T1-GE3_SOT23-3

2N7002E-T1-GE3_SOT23-3

R1

R1

4.7K_0402_5%

4.7K_0402_5%

1 2

D_CK_SDATA

R4

R4

4.7K_0402_5%

4.7K_0402_5%

1 2

D_CK_SCLK

+3VS

+3VS

D D

C C

B B

PCH_SMBDATA19

A A

PCH_SMBCLK19

+V_DDR_REF

All VREF traces should
have 10 mil trace width

+0.75VS +0.75VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
C180

C180

C179

C179

1

1

2

2

DDR_CKE0_DIMMA7 DDR_CKE1_DIMMA 7

DDR_A_BS27

M_CLK_DDR07
M_CLK_DDR#07

DDR_A_BS07
DDR_A_WE#7

DDR_A_CAS#7

DDR_CS1_DIMMA#7

+3VS

C200

2.2U_0603_6.3V6K

C200

2.2U_0603_6.3V6K

C199

0.1U_0402_16V4Z

C199

0.1U_0402_16V4Z
1

1

2

2

4

+V_DDR_REF
DDR_A_D0

DDR_A_D1
DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

R134

10K_0402_5%

R134

10K_0402_5%

12

1 2

+1.5V

10K_0402_5%

10K_0402_5%

R135

R135

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

3

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

DDR3_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76

DDR_A_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

BA1

S0#

G2

DDR_A_MA14DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS0_DIMMA#

114

M_ODT0

116
118

M_ODT1

120
122
124
126
128

DDR_A_D36

130

DDR_A_D37

132
134

DDR_A_DM4

136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

D_CK_SDATA

200

D_CK_SCLK

202
204

206

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

DDR3_DRAMRST# 7,13

M_CLK_DDR1 7
M_CLK_DDR#1 7

DDR_A_BS1 7
DDR_A_RAS# 7

DDR_CS0_DIMMA# 7
M_ODT0 7

M_ODT1 7

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

2

D_CK_SDATA 13,14,29
D_CK_SCLK 13,14,29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+VREF_CA

C193

C193

+1.5V

12

R124

R124
1K_0402_1%

1K_0402_1%

C194

0.1U_0402_16V4Z

C194

0.1U_0402_16V4Z

12

R125

R125

1

1K_0402_1%

1K_0402_1%

2

2

JDIMM1

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

LCN_DAN06-K4526-0101

LCN_DAN06-K4526-0101

CONN@

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_DQS#[0..7] 7

DDR_A_DQS[0..7] 7

DDR_A_D[0..63] 7

DDR_A_MA[0..15] 7

Layout Note:

+1.5V

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

+0.75VS

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Place near JDIMM1

C181

C181

C182

1U_0402_6.3V6K

C182

1U_0402_6.3V6K

1

2

C186

10U_0603_6.3V6M

C186

10U_0603_6.3V6M

10U_0603_6.3V6M

C185

C185

C195

C195

10U_0603_6.3V6M

1

1

2

2

Layout Note:
Place near JDIMM1.203,204

C196

1U_0402_6.3V6K

C196

1U_0402_6.3V6K

1

2

1

2

1

2

C187

C187

1U_0402_6.3V6K

C183

1U_0402_6.3V6K

C183

1U_0402_6.3V6K

1

2

C189

10U_0603_6.3V6M

C189

10U_0603_6.3V6M

C188

10U_0603_6.3V6M

C188

10U_0603_6.3V6M

1

1

2

2

C198

1U_0402_6.3V6K

C198

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

1

2

C184

1U_0402_6.3V6K

C184

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

C191

10U_0603_6.3V6M

C191

10U_0603_6.3V6M

C190

10U_0603_6.3V6M

C190

10U_0603_6.3V6M

1

1

2

2

12 45Wednesday, March 09, 2011

12 45Wednesday, March 09, 2011

12 45Wednesday, March 09, 2011

1

+

+

2

of

of

of

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

C192

C192

D

D

D

5

All VREF traces should
have 10 mil trace width

D D

C C

B B

A A

+V_DDR_REF

10K_0402_5%

10K_0402_5%

+0.75VS

R149

R149

4

+1.5V

+V_DDR_REF

C202

0.1U_0402_16V4Z

C202

0.1U_0402_16V4Z

C201

2.2U_0603_6.3V6K

C201

+3VS

2.2U_0603_6.3V6K

1

2

DDR_CKE2_DIMMB7

DDR_B_BS27

M_CLK_DDR27
M_CLK_DDR#27

DDR_B_BS07
DDR_B_WE#7

DDR_B_CAS#7

DDR_CS3_DIMMB#7

C222

2.2U_0603_6.3V6K

C222

2.2U_0603_6.3V6K

C221

0.1U_0402_16V4Z

C221

0.1U_0402_16V4Z

12

1

1

2

2

1

2

+3VS

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

R150

R150

10K_0402_5%

10K_0402_5%

12

3

JDIMM2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4926-0101

LCN_DAN06-K4926-0101

CONN@

CONN@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

VSS12

DQ14
DQ15

VSS14

DQ20
DQ21

VSS16

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

VSS24

DQ30
DQ31

VSS26

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

2

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26

DDR_B_DM1

28

DDR3_DRAMRST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44

DDR_B_DM2

46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE3_DIMMB

74
76

DDR_B_MA15

78

A15
A14

A11

A7
A6

A4
A2

A0

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

D_CK_SDATA
D_CK_SCLK

+0.75VS

DDR3_DRAMRST# 7,12

DDR_CKE3_DIMMB 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

DDR_B_BS1 7
DDR_B_RAS# 7

DDR_CS2_DIMMB# 7
M_ODT2 7

M_ODT3 7

+VREF_CA

C219

2.2U_0603_6.3V6K

C219

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

D_CK_SDATA 12,14,29
D_CK_SCLK 12,14,29

C220

C220

+1.5V

+1.5V

+0.75VS

C203

1U_0402_6.3V6K

C203

1U_0402_6.3V6K

1

2

C207

10U_0603_6.3V6M

C207

10U_0603_6.3V6M

1

2

C215

1U_0402_6.3V6K

C215

1U_0402_6.3V6K

1

2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

1

2

1

2

1

2

C204

1U_0402_6.3V6K

C204

1U_0402_6.3V6K

Layout Note:
Place near JDIMMB

10U_0603_6.3V6M

10U_0603_6.3V6M

C208

10U_0603_6.3V6M

C208

10U_0603_6.3V6M

1

2

Layout Note:
Place near JDIMMB.203,204

C216

1U_0402_6.3V6K

C216

1U_0402_6.3V6K

1

2

C209

C209

1

2

C205

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

C217

1U_0402_6.3V6K

C217

1U_0402_6.3V6K

1

DDR_B_DQS#[0..7] 7

DDR_B_DQS[0..7] 7

DDR_B_D[0..63] 7

DDR_B_MA[0..15] 7

C206

1U_0402_6.3V6K

C206

1U_0402_6.3V6K

1

2

C210

C210

C211

10U_0603_6.3V6M

C211

10U_0603_6.3V6M

1

2

C218

1U_0402_6.3V6K

C218

1U_0402_6.3V6K

1

2

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

C214

10U_0603_6.3V6M

10U_0603_6.3V6M

<BOM Structure>

<BOM Structure>

C213

C213

1

2

C214

1

+

+

2

C212

10U_0603_6.3V6M

C212

10U_0603_6.3V6M

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

1

D

D

D

of

of

of

13 45Wednesday, March 09, 2011

13 45Wednesday, March 09, 2011

13 45Wednesday, March 09, 2011

A

B

C

D

E

F

G

H

1 1

2 2

Silego Have Internal Pull-Up

+CLK_3VS

IDT 9LVS3199AKLFT NC

R9 10K_0402_5%@R9 10K_0402_5%@

1 2

3 3

C14

@C14

@

1 2

27P_0402_50V8J

27P_0402_50V8J

C15

@C15

@

27P_0402_50V8J

27P_0402_50V8J

1 2

H_STP_CPU#

CLK_XTAL_IN

12

Y1

@Y1

@

14.31818MHZ 20PF 7A14300003

14.31818MHZ 20PF 7A14300003
CLK_XTAL_OUT

Change to 5x3.2

CLK_BUF_ICH_14M19

SM010014520 3000ma 220ohm@100mhz DCR 0.04

@L1

@

FBMA-L11-201209-221LMA30T_0805

+3VS

C1

@ C1

@

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.5VS

D_CK_SDATA12,13,29

VGATE20,33,44

D_CK_SCLK12,13,29

FBMA-L11-201209-221LMA30T_0805

1

2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L4

@L4

@
FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

C9

@C9

@

10U_0603_6.3V6M

10U_0603_6.3V6M

2

R12

@R12

@

0_0402_5%

0_0402_5%

CLK_BUF_ICH_14M

L1

L3

@L3

@

+CLK_1.5VS

+CLK_3VS

+CLK_1.05VS

+CLK_1.5VS

+CLK_3VS

@R13

@

R14 0_0402_5%@R14 0_0402_5%@

R15

@R15

@
33_0402_5%

33_0402_5%

12

12

12

R13

0_0402_5%

0_0402_5%

12

12

40mil

1

2

1

2

D_CK_SDATA_R

12

D_CK_SCLK_R

12

H_STP_CPU#

CK505_PWRGD

CLK_XTAL_IN
CLK_XTAL_OUT

REF_0/CPU_SEL

40mil

+CLK_3VS

C2

10U_0603_6.3V6M@C2

10U_0603_6.3V6M

C3

0.1U_0402_16V4Z@C3

0.1U_0402_16V4Z

C4

0.1U_0402_16V4Z@C4

0.1U_0402_16V4Z

1

@

C10

10U_0603_6.3V6M@C10

10U_0603_6.3V6M

@

Standard
IDT: 9LRS3199AKLFT, SA000030P00
SILEGO: SLG8SP587V(WF), SA00002XY10

1

@

2

1

2

@U1

@

1
5

15
18

17
24
29

31
32

16

25

28
27

30

@

2

+CLK_1.5VS

C11

0.1U_0402_16V4Z@C11

0.1U_0402_16V4Z

C13

0.1U_0402_16V4Z@C13

0.1U_0402_16V4Z

1

@

@

2

U1

VDD_DOT
VDD_27

VDDSRC_IO
VDDCPU_IO

VDDSRC_3.3
VDDCPU_3.3
VDDREF_3.3

SDA
SCL

CPU_STOP#

CKPWRGD/PD#

XTAL_IN
XTAL_OUT

REF_0/CPU_SEL

SLG8SP585VTR_QFN32_5X5

SLG8SP585VTR_QFN32_5X5

1

2

0.1U_0402_16V4Z@C12

0.1U_0402_16V4Z

@

C12

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_1/SATA

SRC_1/SATA#

SRC_2

SRC_2#

DOT_96

DOT_96#

27MHz

27MHz_SS

VSS_DOT

VSS_27

VSS_SATA

VSS_SRC
VSS_CPU

VSS_REF

L2

@L2

+1.05VS_PCH

@

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

C5

@C5

@

10U_0603_6.3V6M

10U_0603_6.3V6M

2

40mil

12

C6

10U_0603_6.3V6M@C6

10U_0603_6.3V6M

1

1

@

2

2

Use internal Clock first, reseve external clock.

23
22

20
19

10
11

13
14

3
4

6
7

2
8
9
12
21
26
33

EP

R2 33_0402_5%@R2 33_0402_5%@
R3 33_0402_5%@R3 33_0402_5%@

R5 33_0402_5%@R5 33_0402_5%@
R6 33_0402_5%@R6 33_0402_5%@

R7 33_0402_5%@R7 33_0402_5%@
R8 33_0402_5%@R8 33_0402_5%@

R10 33_0402_5%@R10 33_0402_5%@
R11 33_0402_5%@R11 33_0402_5%@

12
12

12
12

12
12

12
12

CLK_BUF_CPU_BCLKCLK_BCLK
CLK_BUF_CPU_BCLK#CLK_BCLK#

CLK_BUF_PCIE_SATACLK_SATA
CLK_BUF_PCIE_SATA#CLK_SATA#

CLK_BUF_CPU_DMICLK_DMI
CLK_BUF_CPU_DMI#CLK_DMI#

CLK_BUF_DREF_96MCLK_96M
CLK_BUF_DREF_96M#CLK_96M#

+CLK_1.05VS

C7

0.1U_0402_16V4Z@C7

0.1U_0402_16V4Z

@

C8

0.1U_0402_16V4Z@C8

0.1U_0402_16V4Z

1

@

2

CLK_BUF_CPU_BCLK 5
CLK_BUF_CPU_BCLK# 5

CLK_BUF_PCIE_SATA 19
CLK_BUF_PCIE_SATA# 19

CLK_BUF_CPU_DMI 19
CLK_BUF_CPU_DMI# 19

CLK_BUF_DREF_96M 19

CLK_BUF_DREF_96M# 19

IDT Have Internal Pull-Down
FOR Realtek

R16 10K_0402_5%

R16 10K_0402_5%

1 2

@

4 4

@

REF_0/CPU_SEL

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

A

1

100MHz 100MHz

133MHz

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2010/05/17 2011/05/17

2010/05/17 2011/05/17

2010/05/17 2011/05/17

E

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

SCHEMATICS,MB A6731

401968

401968

401968

G

D

D

D

of

of

of

14 45Wednesday, March 09, 2011

14 45Wednesday, March 09, 2011

14 45Wednesday, March 09, 2011

H