Compal LA-6632P PEW52 Schematic

1 1

Compal Confidential

2 2

PEW52 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRIII + ICH9M + ATI Park

3 3

2010-08-09

REV:0.2

4 4

0.2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/22 2011/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Page

PEW52 M/B LA-6632P Schematic

1 52Monday, August 09, 2010

0.2

Compal Confidential

Clo

Model Name : PEW52 File Name : LA6632P

DA80000K400

P/N :

1 1

N :

HDMI Conn

page 25

VRAM 512MB DDR3 64M16 x 4

page 22

TMDS

ATI Park

page 17,18,19,20,21

Fan Control

page 4

PCI-Express 16x

Intel Penryn Processor

uPGA-478 Package

(Socket P)

H_A#(3..35) H_D#(0..63)

667/800/1066MHz

page 4,5,6

FSB

Intel Cantiga

LVDS

uFCBGA-1329

page 7,8,9,10,11,12,13

DMI

C-Link

LCD Conn.

page 23

VGA

LVDS

Mux

VGA

2 2

CRT Conn.

page 24

MINI Card x1

WLAN

page 33

LAN Broadcom 57780

page 32

SATA HDD Conn.

RJ45

page 32

page 30

port 0

PCI-Express

S-ATA

SATA ODD Conn.

page 30

Intel ICH9-M

BGA-676

page 26,27,28,29

port 1

Thermal Sensor

EMC 1402

page 4

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066

USB conn x1

USB port 0

3.3V 48MHz

3.3V 24.576MHz/48Mhz

USB

Bluetooth Conn

page 34

ck Generator

RTM890N-397-VC Low Power

page 16

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 14,15

CMOS Camera

HD Audio

HDA Codec

ALC272

page 38

Phone Jack x2

page 39

Card Reader Realtek RTS5138

page 31page 28 page 32

Audio AMP

page 39

LPC BUS

3 3

RTC CKT.

page 27

LS-6631P

POWER/B Conn.

page 36

ENE KB926 D2

page 35

LS-6581P

Power On/Off CKT.

page 37

USB/B Conn.

page 34

Touch Pad

page 36

Int.KBD

page 36

LS-6583P

DC/DC Interface CKT.

page 40

ODD/B Conn.

page 30

BIOS

page 36

Power Circuit DC/DC

4 4

page 41 42 43 44 45

46 47 48 49

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/22 2011/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

PEW52 M/B LA-6632P Schematic

2 52Thursday, August 05, 2010

0.2

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+

+CPU_CORE

+0.75VS 0.75V power rail for DDR

+1.05VS

+1.5V 1.5V power rail for DDR ON ON OFF

+1.8VS 1.8VS power rail for LVDS ON OFF

+3VALW

+3V

+3V_LAN

+3VS

+5VALW

+5VS

+VSB

+RTCVCC RTC power

+VGA_CORE V

+1.0VSDGPU

+1.5VSDGPU

+1.8VSDGPU

+3VSDGPU

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail

1.5V switched power rail

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail ON*ONON

GA power ON OFF OFF

VGA power

External PCI Devices

Device IDSEL#

REQ#/GNT#

S1 S3 S5

N/A N/A N/A

ON OFF

ON OFF OFF

ON ON

ON OFF

ON ON ON

ON OFF OFF

Interrupts

N/AN/AN/A

OFF

OFFOFFON+1.5VS

OFF

ON*ON

OFF

ON*

OFF

ON*ON

OFF

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

1.0

HIGHHIGHHIGH

HIGH

V typ

AD_BID

OFF

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

BTO Option

PLEASE REFER PAGE 52

PCIE table

ON ON

OFF

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

LOW

OFF

max

EC SM Bus1 address

3 3

Device

Smart Battery

EEPROM(24C16/02)

GMT G781-1

Address Address

1010 000X b

1001 101X b

ICH9M SM Bus address

Device

Clock Generator (ICS9LPRS387, SLG8SP556V)

DDR DIMM0

DDR DIMM2

Address

1101 001Xb

1001 000Xb

1001 010Xb

EC SM Bus2 address

Device

CPU EMC1402-1

VGA ADM1032-2

0100 1100 b0001 011X b

0100 1101 b

USB table

EHCI1

EHCI2

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11

MB USB Conn. USB/B Conn.

CMOS Camera Card Reader

USB/B Conn.

Blue Tooth

Wireless Card

PCIE port1

PCIE port2

PCIE port3

PCIE port4

PCIE port5

PCIE port6

SATA table

SATA port0

SATA port1

SATA port2

SATA port3

Wireless Card

PCIE LAN

HDD

ODD

SATA port4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/25 2011/04/22

Compal Secret Data

Deciphered Date

SATA port5

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

PEW52 M/B LA-6632P Schematic

0.2

3 52Thursday, July 29, 2010

0.2

H_A#[3..35 ]7

H_REQ#[0 ..4]7

H_RS#[0..2 ]7

D D

C C

B B

BSEL2 BSEL1 BSEL0 BCLK

0 0 0 266

0 1 0 200

A A

H_A#[3..35 ]

H_REQ#[0 ..4]

H_RS#[0..2 ]

JCPU1A

AA4 AB2 AA3

D22

J4 L5 L4

J1 N3 P5 P2

L2 P4 P1 R1

K3 H2 K2

Y2 U5 R3

U4 Y5 U1 R4 T5 T3

W2 W5

Y4 U2 V4

A6 A5 C4

D5 C6 B4 A3

N5 T2 V3 B2 D2

D3 F6

1660 1

JCPU1A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

Penryn

CONN@

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDI TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA THERMDC

H CLK

BCLK[0] BCLK[1]

H_PROCH OT#

H1 E2 G5

H5 F21 E1

H_IERR#

D20 B3

H_RESET #

H_RS#0

H_RS#1

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2

XDP_BPM #5

AC1

XDP_TCK

AC5

XDP_TDI

AA6 AB3

XDP_TMS

AB5

XDP_TRS T#

AB6

XDP_DBR ESET#

C20

H_PROCH OT#

D21

H_THERM DA

A24

H_THERM DC

B25

A22 A21

Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil

+1.05VS

R12

R12 56_0402 _5%

56_0402 _5%

3 1

Q1 MMBT390 4_SOT23-3

MMBT390 4_SOT23-3

H_ADS# 7 H_BNR# 7 H_BPRI# 7

H_DEFER # 7 H_DRDY# 7 H_DBSY# 7

H_BR0# 7

H_INIT# 27

H_LOCK# 7

H_RESET # 7

H_TRDY# 7

H_HIT# 7 H_HITM# 7

Add for

TDO

XDP_DBR ESET# 28

H_THERM TRIP# 8,27

CLK_CPU _BCLK 16 CLK_CPU _BCLK# 16

OCP# 28

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

測測測測測測測測

EN_DFAN 135

20080430 A

dd soft-start fo r +5VS drop iss ue

1 2

R38

R38 330_040 2_5%

330_040 2_5%

0804

H_THERM DA

C11

2200P_0 402_50V7K

H_THERM DC

Compal Secret Data

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15

H_ADSTB #07

H_ADSTB #17

H_A20M#27

H_FERR#27

H_IGNNE#27

H_STPCL K#27

H_INTR27

H_NMI27

H_SMI#27

H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

+5VS

+VCC_FA N1 VSET

XDP_TDI

XDP_TMS

XDP_BPM #5

H_PROCH OT#

H_IERR#

XDP_TRS T#

XDP_TCK

+3VS

C46 10U_ 0805_10V6KC4 6 10U _0805_10V6K

1 2

VIN

VOUT

VSET

APL5607 KI-TRG_SO8

C33

0.01U_04 02_16V7K

APL5607 KI-TRG_SO8

FAN_SPE ED135

R76 54.9_040 2_1% R76 54.9_040 2_1%

1 2

R77 54.9_040 2_1% R77 54.9_040 2_1%

1 2

R90 54.9_040 2_1%@R90 54.9_0402 _1%@

1 2

R25 56_0402 _5% R25 56_0402 _5%

R30 56_0402 _5% R30 56_0402 _5%

R82 54.9_040 2_1% R82 54.9_040 2_1%

R86 54.9_040 2_1% R86 54.9_040 2_1%

1 2

C12

0.1U_040 2_16V4Z

1 2

VDD

THERM#

EMC1402 -1-ACZL-TR_MSOP 8

SMBus Address:0100_1100b

FAN1 Conn

GND

+3VS

R404

R404 10K_040 2_5%

10K_040 2_5%

C559

C559 1000P_0 402_50V7K

1000P_0 402_50V7K

SMCLK

SMDATA

ALERT#

GND

+5VS

D17

D17 1SS355_ SOD323-2@

1SS355_ SOD323-2@

D16

@D16

BAS16_S OT23-3

1 2

C561

10U_080 5_10V6K

1 2

C560

1000P_0 402_50V7K

1 2

40mil

+VCC_FA N1

+1.05VS

JFAN1

CONN@

ACES_85 204-03001

4 5

left NC if no ITP

39Ohm

Title

Size Document Number Rev

Date: Sheet of

EC_SMB_ CK2 18,35

EC_SMB_ DA2 18,35

1 2

R18

R18 10K_040 2_5%

10K_040 2_5%

PEW52 M/B LA-6632P Schematic

+3VS

Compal Electronics, Inc.

Penryn (1/3) & FAN

4 52Friday, August 06, 201 0

0.2

H_D#[0..63 ]

JCPU1B

G22

G25

G24

H22

H23

H26 H25

N22

R23

M24

M23

R24

N25

M26 N24

AD26

C23 D25 C24

AF26

AF1

C21

E22 F24 E26

F23

E25 E23 K24

J24 J23

F26 K22

J26

K25 P26

L23

L22

P25 P23 P22 T24

L25 T25

L26

A26

B22 B23

JCPU1B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

CONN@

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

H_D#0

PAD

PAD PAD

PAD

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTL_REF 0

@ @

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

D D

H_DSTBN #07 H_DSTBN #2 7 H_DSTBP #07 H_DSTBP#2 7

H_DINV#07

C C

Trace Close CPU < 0.5'

Width=4 mil , Spacing: 15mil (55Ohm)

B B

R436

R436 1K_0402 _1%

1K_0402 _1%

R434

R434 2K_0402 _1%

2K_0402 _1%

+1.05VS

1 2

H_DSTBN #17 H_DSTBN #3 7 H_DSTBP #17 H_DSTBP#3 7

H_DINV#17

R364 1K_0402 _5%@R364 1K_0402 _5%@ R365 1K_0402 _5%@R365 1K_0402 _5%@

C621

0.1U_040 2_16V4Z

@C621

1 2

12 12

T27

T27 T25

T25

CPU_BSE L016 CPU_BSE L116 CPU_BSE L216

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

H_PW RGOOD H_CPUSL P#

R399 27.4_040 2_1%R399 27.4_040 2_1% R415 54.9_040 2_1%R415 54.9_040 2_1% R74 27.4_040 2_1%R74 27.4_040 2_1% R80 54.9_040 2_1%R80 54.9_040 2_1%

H_DINV#2 7

H_DINV#3 7

1 2 1 2 1 2 1 2

H_DPRST P# 8,27,4 9 H_DPSLP # 27 H_DPW R# 7 H_PW RGOOD 27 H_CPUSL P# 7 PSI# 49

TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)

H_D#[0..63 ] 7

+CPU_CO RE

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

A7 A9

B7 B9

E7 E9

F7 F9

JCPU1C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

NN@

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

+CPU_CO RE

VCCSENS E

VSSSENS E

C15

CPU_VID0 4 9 CPU_VID1 4 9 CPU_VID2 4 9 CPU_VID3 4 9 CPU_VID4 4 9 CPU_VID5 4 9 CPU_VID6 4 9

R443 1 00_0402_1%

R451 1 00_0402_1%

0.01U_04 02_16V7K

1 2

C15

+1.05VS

20mils

C13

10U_080 5_10V6K

VCCSENS E 49

VSSSENS E 49

+1.5VS

+CPU_CO RE

R443 & R451

A A

Security Class ification

2010/04/ 22 201 1/04/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

PEW52 M/B LA-6632P Schematic

Date: Sheet of

改改改改

,0702

Compal Electronics, Inc.

Penryn (2/3)

5 52Wednesd ay, August 04, 2 010

0.2

+CPU_CO RE +CPU_CO RE

JCPU1D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

NN@

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

C10

330U_D2 E_2.5VM_R9

+CPU_CO RE

10U_080 5_6.3V6M

+CPU_CO RE

10U_080 5_6.3V6M

+CPU_CO RE

10U_080 5_6.3V6M

+CPU_CO RE

10U_080 5_6.3V6M

+1.05VS

C49

330U_D2 E_2.5VM_R9

2 x 330uF(6mOhm/2) 2 x 330uF(6mOhm/2)

330U_D2 E_2.5VM_R9

South Side Secondary North Side Secondary

C514

10U_080 5_6.3V6M

C510

C558

10U_080 5_6.3V6M

C197

330U_D2 E_2.5VM_R9

C42

10U_080 5_6.3V6M

C27

10U_080 5_6.3V6M

C639

330U_D2 E_2.5VM_R9

(Place these capacitors on South side,Secondary Layer)

C89

10U_080 5_6.3V6M

C90

C91

10U_080 5_6.3V6M

C92

10U_080 5_6.3V6M

C93

10U_080 5_6.3V6M

(Place these capacitors on North side,Secondary Layer)

C23

C22

C539

C23

10U_080 5_6.3V6M

(

Place these capacitors on South side,Primary Layer)

C557

10U_080 5_6.3V6M

C24

10U_080 5_6.3V6M

C576

10U_080 5_6.3V6M

C25

10U_080 5_6.3V6M

C575

10U_080 5_6.3V6M

C574

10U_080 5_6.3V6M

C513

10U_080 5_6.3V6M

(Place these capacitors on North side,Primary Layer)

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

C74

0.1U_040 2_16V4Z

C,uF ESR, mohm ESL,nH

4X330uF 6m ohm/4 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32

32X10uF 3m ohm/32 0.6nH/32

C52

0.1U_040 2_16V4Z

C94

C48

0.1U_040 2_16V4Z

C83

0.1U_040 2_16V4Z

C58

10U_080 5_6.3V6M

C540

10U_080 5_6.3V6M

C578

10U_080 5_6.3V6M

C577

10U_080 5_6.3V6M

C34

C67

10U_080 5_6.3V6M

C521

10U_080 5_6.3V6M

C88

10U_080 5_6.3V6M

C512

10U_080 5_6.3V6M

C522

C26

C69

C511

A A

Security Class ification

2010/04/ 22 201 1/04/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Penryn (3/3)

PEW52 M/B LA-6632P Schematic

6 52Thursday, July 29, 2010

0.2

U28A

H_D#[0..63 ]5

D D

+1.05VS

R67

221_040 2_1%

H_SW ING

width=10mil

H_RCOMP

+1.05VS

1 2

C84

0.1U_040 2_16V4Z

width=10mil

R64

1K_0402 _1%

R65

2K_0402 _1%

C64

0.1U_040 2_16V4Z

H_RESET #4

H_CPUSL P#5

C C

B B

R66

100_040 2_1%

1 2

R414

24.9_040 2_1%

width:spacing=10mil:20mil (<0.5")

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SW ING H_RCOMP

H_RESET # H_CPUSL P#

H_AVREF

U28A

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

H_D#_10

M11

H_D#_11

H_D#_12

H_D#_13

N12

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

P13

H_D#_27

H_D#_28

H_D#_29

N10

H_D#_30

H_D#_31

H_D#_32

AD14

H_D#_33

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

H_D#_38

H_D#_39

AA8

H_D#_40

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

H_SWING

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

AC82GM4 5_SLB94_B3_F CBGA1329

H_ADSTB#_0 H_ADSTB#_1

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_HIT#

H_HITM#

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_ADS# H_ADSTB #0 H_ADSTB #1 H_BNR# H_BPRI# H_BR0# H_DEFER # H_DBSY# CLK_MCH _BCLK CLK_MCH _BCLK# H_DPW R# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN #0 H_DSTBN #1 H_DSTBN #2 H_DSTBN #3

H_DSTBP #0 H_DSTBP #1 H_DSTBP #2 H_DSTBP #3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

H_A#[3..35 ] 4

H_ADS# 4 H_ADSTB #0 4 H_ADSTB #1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER # 4 H_DBSY# 4 CLK_MCH _BCLK 16 CLK_MCH _BCLK# 16 H_DPW R# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4

H_DINV#0 5 H_DINV#1 5 H_DINV#2 5 H_DINV#3 5

H_DSTBN #0 5 H_DSTBN #1 5 H_DSTBN #2 5 H_DSTBN #3 5

H_DSTBP #0 5 H_DSTBP #1 5 H_DSTBP #2 5 H_DSTBP #3 5

H_REQ#[0 ..4] 4

H_RS#[0..2 ] 4

within 100mil to Ball A9,B9

A A

Security Class ification

2010/04/ 22 201 1/04/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(1/7)-GTL

PEW52 M/B LA-6632P Schematic

7 52Wednesd ay, August 04, 2 010

0.2

D D

All RSVD balls on GMCH should be left No Connect.

C C

MCH_CLKSEL016 MCH_CLKSEL116 MCH_CLKSEL216

PM_EXTTS#0

VGATE16,28,49

+1.05VS

R385

54.9_0402_1%

1 2

R389

R389 330_0402_5%

330_0402_5%

1 2

R54 10K_0402_5%

R92 10K_0402_5%

R50 10K_0402_5%

H_DPRSTP#5,27,49 PM_EXTTS#014 PM_EXTTS#115

H_THERMTRIP#4,27 PM_DPRSLPVR28,49

1 2

VGATE

ICH_PWROK

PM_SYNC#28

PLT_RST#26,32,35

PM_EXTTS#1

MCH_CLKREQ#

+3VS

3 1

1 2

R130 0_0402_5%

1 2

R131 0_0402_5%

R132 100_0402_5% R132 100_0402_5%

1 2

+3VS

R368

R368 1K_0402_5%

1K_0402_5%

3 1

Q32

Q32 MMBT3904_SOT23-3

MMBT3904_SOT23-3

R372

R372 1K_0402_5%

1K_0402_5%

Q33

Q33 MMBT3904_SOT23-3

MMBT3904_SOT23-3

GMCH_PWROK

PM_SYNC# H_DPRSTP#

THERMTRIP#_R DPRSLPVR_R

+3VS

ICH_PWROK28

B B

A A

MCH_TSATN#

MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2

MCH_CFG_5 MCH_CFG_6 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10

MCH_CFG_12 MCH_CFG_13

MCH_CFG_16

MCH_CFG_19 MCH_CFG_20

PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK MCH_RSTIN#

MCH_TSATN_EC# 35

U28B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

AL34

RSVD10

AK34

RSVD11

AN35

RSVD12

AM35

RSVD13

T24

RSVD14

B31

RSVD15

RSVD16

RSVD17

AY21

RSVD20

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

NC_25

A47

NC_26

AC82GM45_SLB94_B3_FCBGA1329

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

RSVD CFG PM NC

DDR CLK/ CONTROL/ COMPENSATIONHDA

CLKDMIGRAPHICS VIDMEMISC

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_O

AY13

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

Issued Date

SMRCOMP SMRCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_PWROK SM_REXT SM_DRAMRST#

CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC#

CLK_MCH_3GPLL CLK_MCH_3GPLL#

DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3

DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3

DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3

DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3

ICH_PWROK

CL_VREF

Add for

MCH_CLKREQ#

MCH_TSATN#

DG 8.3.2 iHDMI T

he GMCH provides two ports capable of supporting HDMI. However, Intel HD Audio can be supported on any one of the iHDMI ports at any given point. A separate audio path shall be required for the other port

DDRA_CLK0 14 DDRA_CLK1 14 DDRB_CLK0 15 DDRB_CLK1 15

DDRA_CLK0# 14 DDRA_CLK1# 14 DDRB_CLK0# 15 DDRB_CLK1# 15

DDRA_CKE0 14 DDRA_CKE1 14 DDRB_CKE0 15 DDRB_CKE1 15

DDRA_SCS0# 14 DDRA_SCS1# 14 DDRB_SCS0# 15 DDRB_SCS1# 15

DDRA_ODT0 14 DDRA_ODT1 14 DDRB_ODT0 15 DDRB_ODT1 15

R465 80.6_0402_1% R465 80.6_0402_1%

1 2

R464 80.6_0402_1% R464 80.6_0402_1%

1 2

SM_VREF

SM_PWROK 37

R463 499_0402_1% R463 499_0402_1%

1 2

SM_DRAMRST# 14,15

CLK_DREF_96M 16 CLK_DREF_96M# 16 CLK_DREF_SSC 16 CLK_DREF_SSC# 16

CLK_MCH_3GPLL 16 CLK_MCH_3GPLL# 16

DMI_ITX_MRX_N0 28 DMI_ITX_MRX_N1 28 DMI_ITX_MRX_N2 28 DMI_ITX_MRX_N3 28

DMI_ITX_MRX_P0 28 DMI_ITX_MRX_P1 28 DMI_ITX_MRX_P2 28 DMI_ITX_MRX_P3 28

DMI_MTX_IRX_N0 28 DMI_MTX_IRX_N1 28 DMI_MTX_IRX_N2 28 DMI_MTX_IRX_N3 28

DMI_MTX_IRX_P0 28 DMI_MTX_IRX_P1 28 DMI_MTX_IRX_P2 28 DMI_MTX_IRX_P3 28

CL_CLK0 28 CL_DATA0 28

CL_RST#0 28

測測測測測測測測

0804

DDPC_CTRLDATA

SDVO_SCLK 25 SDVO_SDATA 25

MCH_CLKREQ# 16 MCH_ICH_SYNC# 28

Compal Secret Data

2010/04/22 2011/04/22

Compal Secret Data

SM_DRAMRST# would be needed for DDR3 only

For Cantiga

+1.5V +1.5V

20mil

C231

0.1U_0402_16V4Z

Strap Pin Table

C176

0.1U_0402_16V4Z

Deciphered Date

DDR3

80 Ohm

R140

R140 10K_0402_1%

10K_0402_1%

1 2

R138

R138 10K_0402_1%

10K_0402_1%

1 2

+1.5V

R472

1K_0402_1%

R466

3.01K_0402_1%

R471

1K_0402_1%

CFG[2:0]

CFG5

CFG6

CFG7

CFG9

CFG10

CFG[13:12]

CFG16

SM_RCOMP_VOH

C688

2.2U_0603_6.3V6K

C687

2.2U_0603_6.3V6K

C671

0.01U_0402_16V7K

SM_RCOMP_VOL

C670

0.01U_0402_16V7K

CLK_DREF_96M

CLK_DREF_96M#

CLK_DREF_SSC

CLK_DREF_SSC#

Add pull-l ow 0 ohm , 0625

011 = FSB667

0 = DMI x 2 1 = DMI x 4

0 = iTPM Host Interface is enabled 1 = iTPM Host Interface is Disabled

0 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality

1 = Intel Management Engine Crypto TLS cipher suite with confidentiality (default)

0 = Lane Reversal Enable 1 = Normal Operation

0 = PCIe Loopback Enable 1 = Disable*(Default)

00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation

0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled

(Default)

0 = Normal Operation

+1.05VS

1 2

R115

1K_0402_1%

R126

511_0402_1%

CFG19

CFG20

(PCIE/SDVO select)

SDVO_CTRLDATA

L_DDC_DATA

DDPC_CTRLDATA

1 = DMI Lane Reversal Enable

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

0 = No SDVO Card Present 1 = SDVO Card Present

0 = LFP Disable 1 = LFP Card Present; PCIE disable

0 = Digital DisplayPort Disable 1 = Digital DisplayPort Device Present

MCH_CFG_5

MCH_CFG_6

MCH_CFG_7

MCH_CFG_9

MCH_CFG_10

MCH_CFG_12

MCH_CFG_13

MCH_CFG_16

MCH_CFG_19

MCH_CFG_20

Title

Size Document Number Rev

Custom

Date: Sheet of

R63 2.21K_0402_1%

R58 4.02K_0402_1%

R44 2.21K_0402_1%

R71 2.21K_0402_1%

R56 2.21K_0402_1%

R91 2.21K_0402_1%

R93 2.21K_0402_1%

R84 2.21K_0402_1%

R68 4.02K_0402_1%

R43 4.02K_0402_1%

Compal Electronics, Inc.

Cantiga GMCH(2/7)-DMI/DDR

PEW52 M/B LA-6632P Schematic

DIS@

1 2

R576 0_0402_5%

DIS@

1 2

R577 0_0402_5%

DIS@

1 2

R578 0_0402_5%

DIS@

1 2

R579 0_0402_5%

010 = FSB800

(Default)

000 = FSB1067

(Default)

8 52Friday, August 06, 2010

(Default)

+3VS

0.2

DDR_B_D Q[0..63]

DDR_B_D M[0..7]

DDR_B_M A[0..14]

DDR_B_D QS#[0..7]

DDR_A_B S0 1 4 DDR_A_B S1 1 4 DDR_A_B S2 1 4

DDR_A_R AS# 14 DDR_A_C AS# 14 DDR_A_W E# 14

DDR_A_D QS0 14 DDR_A_D QS1 14 DDR_A_D QS2 14 DDR_A_D QS3 14 DDR_A_D QS4 14 DDR_A_D QS5 14 DDR_A_D QS6 14 DDR_A_D QS7 14

DDR_B_D 0 DDR_B_D 1 DDR_B_D 2 DDR_B_D 3 DDR_B_D 4 DDR_B_D 5 DDR_B_D 6 DDR_B_D 7 DDR_B_D 8 DDR_B_D 9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39 DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8 BH12 BF11

BF8 BG7 BC5 BC6

AY3

AY1

BF6

BF5

BA1 BD3

AV2 AU3 AR3 AN2

AY2

AV1

AP3 AR1

AL1

AL2

AJ1 AH1 AM2 AM3 AH3

AJ3

U28E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

DDR_B_D M0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2

DDR SYSTEM MEMORY B

SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

AC82GM4 5_SLB94_B3_F CBGA1329

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6

AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

DDR_B_D M1 DDR_B_D M2 DDR_B_D M3 DDR_B_D M4 DDR_B_D M5 DDR_B_D M6 DDR_B_D M7

DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7

DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7

DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_M A14

DDR_B_B S0 1 5 DDR_B_B S1 1 5 DDR_B_B S2 1 5

DDR_B_R AS# 15 DDR_B_C AS# 15 DDR_B_W E# 15

DDR_B_D QS0 15 DDR_B_D QS1 15 DDR_B_D QS2 15 DDR_B_D QS3 15 DDR_B_D QS4 15 DDR_B_D QS5 15 DDR_B_D QS6 15 DDR_B_D QS7 15

U28D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

DDR_A_D [0..63]

DDR_A_D M[0..7]

DDR_A_M A[0..14]

DDR_A_D QS#[0..7]

DDR_B_D [0..63]15

DDR_B_D M[0..7]15

DDR_B_M A[0..14]15

DDR_B_D QS#[0..7]15

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

DDR_A_D M0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3

DDR SYSTEM MEMORY A

SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

AC82GM4 5_SLB94_B3_F CBGA1329

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7

AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

DDR_A_D M1 DDR_A_D M2 DDR_A_D M3 DDR_A_D M4 DDR_A_D M5 DDR_A_D M6 DDR_A_D M7

DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7

DDR_A_D QS#0 DDR_A_D QS#1 DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7

DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_M A10 DDR_A_M A11 DDR_A_M A12 DDR_A_M A13 DDR_A_M A14

DDR_A_D [0..63]14

D D

C C

B B

DDR_A_D M[0..7]14

DDR_A_M A[0..14]14

DDR_A_D QS#[0..7]14

DDR_A_D 0 DDR_A_D 1 DDR_A_D 2 DDR_A_D 3 DDR_A_D 4 DDR_A_D 5 DDR_A_D 6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63

AJ38

AJ41 AN38 AM38

AJ36

AJ40 AM44 AM42 AN43 AN44 AU40

AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37

AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AN12 AM13

AJ11 AJ12

AJ9 AJ8

A A

Security Class ification

2010/04/ 22 201 1/04/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Cantiga GMCH(3/7)-DDR

PEW52 M/B LA-6632P Schematic

9 52Wednesd ay, August 04, 2 010

0.2

DPST_PW M23

D D

GMCH_LC D_CLK23

GMCH_LC D_DATA23

GMCH_EN VDD23

1 2

R395 2.3 7K_0402_1%

R395 R75 , Add UMA@ 0625

GMCH_TX CLK-23 GMCH_TX CLK+23

GMCH_TX OUT0-23 GMCH_TX OUT1-23 GMCH_TX OUT2-23

GMCH_TX OUT0+23 GMCH_TX OUT1+23 GMCH_TX OUT2+23

C C

R85

R73

TV-Out Disable Guidelines TV_DCONSEL [1:0] Connect to GND

R72

UMA@

150_040 2_1%

2 1

R81

UMA@

150_040 2_1%

2 1

R89

UMA@

150_040 2_1%

R61 2.2K_040 2_5%UMA@R61 2.2K_0402 _5%UMA@

R45 2.2K_040 2_5%UMA@R45 2.2K_0402 _5%UMA@

R60 10K_040 2_5%UMA@R60 10K _0402_5%UMA @

R46 10K_040 2_5%UMA@R46 10K _0402_5%UMA @

R55 2.2K_040 2_5%UMA@R55 2.2K_0402 _5%UMA@

R59 2.2K_040 2_5%UMA@R59 2.2K_0402 _5%UMA@

LBKLT_E N

R32

100K_04 02_5%

UMA@

2 1

1 2

B B

+3VS

A A

R85

UMA@

2 1

75_0402_1%

R57

UMA@

2 1

75_0402_1%

GMCH_CR T_B24

GMCH_CR T_G24

GMCH_CR T_R24

Add UMA@, 0625

VGA_BKL _EN18

UMA@

2 1

75_0402_1%

R73

DIS@

1 2

0_0402_5%

R85

R57

DIS@

1 2

0_0402_5%

Change to 0Ohm when use PM chip

R72 0_0 402_5%DIS@R72 0_040 2_5%DIS@

R81 0_0 402_5%DIS@R81 0_040 2_5%DIS@

R89 0_0 402_5%DIS@R89 0_040 2_5%DIS@

GMCH_CR T_HSYNC24

GMCH_CR T_VSYNC24

GMCH_LC D_CLK

GMCH_LC D_DATA

LCTLB_D ATA

LCTLA_C LK

GMCH_CR T_CLK

GMCH_CR T_DATA

VGA_BKL _EN ENBKL

GMCH_CR T_CLK24 GMCH_CR T_DATA24

UMA ONLY@

R53 0_0402_5 %

1 2

GND S23D

STG3157 CTR_SOT323-6

SG@

R35 0_0402_ 5%

1 2

DIS ONLY@

SPDT

IGPU_BKLT_EN

DGPU_BKL_EN

UMA@

DIS@

1 2

VCC

5 4

LBKLT_E N LCTLA_C LK LCTLB_D ATA GMCH_LC D_CLK GMCH_LC D_DATA

LVDS_IBG

UMA@

R75

R75 0_0402_ 5%

0_0402_ 5%

GMCH_TX CLKGMCH_TX CLK+

GMCH_TX OUT0GMCH_TX OUT1GMCH_TX OUT2-

GMCH_TX OUT0+ GMCH_TX OUT1+ GMCH_TX OUT2+

GMCH_TV _COMPS GMCH_TV _LUMA GMCH_TV _CRMA

GMCH_CR T_CLK GMCH_CR T_DATA

DGPU_SELECT#

L H

ONO FF

OFF

TV_DCON SEL_0 TV_DCON SEL_1

CRT_IREF

R70

1.02K_04 02_1%

DIS@

1 2

U28C

L32 G32 M32 M33 K33

M29

C44 B43 E37 E38

C41 C40 B37 A37

H47 E46 G40 A40

H48 D45

B40

A41 H38 G37

B42 G38

K37

H25 K25

H24

C31 E32

E28

G28

G29

H32

E29

J33

F40

J37

F37

F25

J28

J32

J29

L29

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL

LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TV_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF

CRT_VSYNC

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

LVDS TV VGA

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PCI-EXPRESS GRAPHICS

PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

AC82GM4 5_SLB94_B3_F CBGA1329

PEG_COM P

T37 T36

PCIE_GTX_ C_MRX_N0

H44

PCIE_GTX_ C_MRX_N1

J46

PCIE_GTX_ C_MRX_N2

L44

PCIE_GTX_ C_MRX_N3

L40

PCIE_GTX_ C_MRX_N4

N41

PCIE_GTX_ C_MRX_N5

P48

PCIE_GTX_ C_MRX_N6

N44

PCIE_GTX_ C_MRX_N7

T43

PCIE_GTX_ C_MRX_N8

U43

PCIE_GTX_ C_MRX_N9

Y43

PCIE_GTX_ C_MRX_N10

Y48

PCIE_GTX_ C_MRX_N11

Y36

PCIE_GTX_ C_MRX_N12

AA43

PCIE_GTX_ C_MRX_N13

AD37

PCIE_GTX_ C_MRX_N14

AC47

PCIE_GTX_ C_MRX_N15

AD39

PCIE_GTX_ C_MRX_P0

H43

PCIE_GTX_ C_MRX_P1

J44

PCIE_GTX_ C_MRX_P2

L43

PCIE_GTX_ C_MRX_P3

L41

PCIE_GTX_ C_MRX_P4

N40

PCIE_GTX_ C_MRX_P5

P47

PCIE_GTX_ C_MRX_P6

N43

PCIE_GTX_ C_MRX_P7

T42

PCIE_GTX_ C_MRX_P8

U42

PCIE_GTX_ C_MRX_P9

Y42

PCIE_GTX_ C_MRX_P10

W47

PCIE_GTX_ C_MRX_P11

Y37

PCIE_GTX_ C_MRX_P12

AA42

PCIE_GTX_ C_MRX_P13

AD36

PCIE_GTX_ C_MRX_P14

AC48

PCIE_GTX_ C_MRX_P15

AD40

PCIE_MTX_ GRX_N0

J41

PCIE_MTX_ GRX_N1

M46

PCIE_MTX_ GRX_N2

M47

PCIE_MTX_ GRX_N3

M40

PCIE_MTX_ GRX_N4

M42

PCIE_MTX_ GRX_N5

R48

PCIE_MTX_ GRX_N6

N38

PCIE_MTX_ GRX_N7

T40

PCIE_MTX_ GRX_N8

U37

PCIE_MTX_ GRX_N9

U40

PCIE_MTX_ GRX_N10

Y40

PCIE_MTX_ GRX_N11

AA46

PCIE_MTX_ GRX_N12

AA37

PCIE_MTX_ GRX_N13

AA40

PCIE_MTX_ GRX_N14

AD43

PCIE_MTX_ GRX_N15

AC46

PCIE_MTX_ GRX_P0

J42

PCIE_MTX_ GRX_P1

L46

PCIE_MTX_ GRX_P2

M48

PCIE_MTX_ GRX_P3

M39

PCIE_MTX_ GRX_P4

M43

PCIE_MTX_ GRX_P5

R47

PCIE_MTX_ GRX_P6

N37

PCIE_MTX_ GRX_P7

T39

PCIE_MTX_ GRX_P8

U36

PCIE_MTX_ GRX_P9

U39

PCIE_MTX_ GRX_P10

Y39

PCIE_MTX_ GRX_P11

Y46

PCIE_MTX_ GRX_P12

AA36

PCIE_MTX_ GRX_P13

AA39

PCIE_MTX_ GRX_P14

AD42

PCIE_MTX_ GRX_P15

AD46

10mils

1 2

R97 49.9_040 2_1%

C603 0.1U_040 2_16V7KDIS@C603 0.1U_0402_16V7 KDIS@

1 2

C605 0.1U_040 2_16V7KDIS@C605 0.1U_0402_16V7 KDIS@

1 2

C611 0.1U_040 2_16V7KDIS@C611 0.1U_0402_16V7 KDIS@

1 2

C616 0.1U_040 2_16V7KDIS@C616 0.1U_0402_16V7 KDIS@

1 2

C626 0.1U_040 2_16V7KDIS@C626 0.1U_0402_16V7 KDIS@

1 2

C633 0.1U_040 2_16V7KDIS@C633 0.1U_0402_16V7 KDIS@

1 2

C642 0.1U_040 2_16V7KDIS@C642 0.1U_0402_16V7 KDIS@

1 2

C644 0.1U_040 2_16V7KDIS@C644 0.1U_0402_16V7 KDIS@

1 2

C646 0.1U_040 2_16V7KDIS@C646 0.1U_0402_16V7 KDIS@

1 2

C657 0.1U_040 2_16V7KDIS@C657 0.1U_0402_16V7 KDIS@

1 2

C660 0.1U_040 2_16V7KDIS@C660 0.1U_0402_16V7 KDIS@

1 2

C662 0.1U_040 2_16V7KDIS@C662 0.1U_0402_16V7 KDIS@

1 2

C669 0.1U_040 2_16V7KDIS@C669 0.1U_0402_16V7 KDIS@

1 2

C679 0.1U_040 2_16V7KDIS@C679 0.1U_0402_16V7 KDIS@

1 2

C676 0.1U_040 2_16V7KDIS@C676 0.1U_0402_16V7 KDIS@

1 2

C678 0.1U_040 2_16V7KDIS@C678 0.1U_0402_16V7 KDIS@

1 2

Modify to DIS@,0630

DGPU_SE LECT# 2 3,24,26

ENBKL 35

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS

C40

0.1U_040 2_16V7K

SG@

Compal Secret Data

2010/04/ 22 201 1/04/22

Compal Secret Data

Deciphered Date

C593 0.1U_040 2_16V7KDIS@C593 0.1U_040 2_16V7KDIS@ C604 0.1U_040 2_16V7KDIS@C604 0.1U_040 2_16V7KDIS@ C607 0.1U_040 2_16V7KDIS@C607 0.1U_040 2_16V7KDIS@ C614 0.1U_040 2_16V7KDIS@C614 0.1U_040 2_16V7KDIS@ C627 0.1U_040 2_16V7KDIS@C627 0.1U_040 2_16V7KDIS@ C634 0.1U_040 2_16V7KDIS@C634 0.1U_040 2_16V7KDIS@ C643 0.1U_040 2_16V7KDIS@C643 0.1U_040 2_16V7KDIS@ C645 0.1U_040 2_16V7KDIS@C645 0.1U_040 2_16V7KDIS@ C647 0.1U_040 2_16V7KDIS@C647 0.1U_040 2_16V7KDIS@ C648 0.1U_040 2_16V7KDIS@C648 0.1U_040 2_16V7KDIS@ C658 0.1U_040 2_16V7KDIS@C658 0.1U_040 2_16V7KDIS@ C661 0.1U_040 2_16V7KDIS@C661 0.1U_040 2_16V7KDIS@ C663 0.1U_040 2_16V7KDIS@C663 0.1U_040 2_16V7KDIS@ C674 0.1U_040 2_16V7KDIS@C674 0.1U_040 2_16V7KDIS@ C675 0.1U_040 2_16V7KDIS@C675 0.1U_040 2_16V7KDIS@ C677 0.1U_040 2_16V7KDIS@C677 0.1U_040 2_16V7KDIS@

+1.05VS

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PCIE_GTX_ C_MRX_P[0..15]17

PCIE_GTX_ C_MRX_N[0..15]17

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_ C_GRX_N0 PCIE_MTX_ C_GRX_N1 PCIE_MTX_ C_GRX_N2 PCIE_MTX_ C_GRX_N3 PCIE_MTX_ C_GRX_N4 PCIE_MTX_ C_GRX_N5 PCIE_MTX_ C_GRX_N6 PCIE_MTX_ C_GRX_N7 PCIE_MTX_ C_GRX_N8 PCIE_MTX_ C_GRX_N9 PCIE_MTX_ C_GRX_N10 PCIE_MTX_ C_GRX_N11 PCIE_MTX_ C_GRX_N12 PCIE_MTX_ C_GRX_N13 PCIE_MTX_ C_GRX_N14 PCIE_MTX_ C_GRX_N15

PCIE_MTX_ C_GRX_P0 PCIE_MTX_ C_GRX_P1 PCIE_MTX_ C_GRX_P2 PCIE_MTX_ C_GRX_P3 PCIE_MTX_ C_GRX_P4 PCIE_MTX_ C_GRX_P5 PCIE_MTX_ C_GRX_P6 PCIE_MTX_ C_GRX_P7 PCIE_MTX_ C_GRX_P8 PCIE_MTX_ C_GRX_P9 PCIE_MTX_ C_GRX_P10 PCIE_MTX_ C_GRX_P11 PCIE_MTX_ C_GRX_P12 PCIE_MTX_ C_GRX_P13 PCIE_MTX_ C_GRX_P14 PCIE_MTX_ C_GRX_P15

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(4/7)-VGA/LVDS/TV

PEW52 M/B LA-6632P Schematic

PCIE_GTX_ C_MRX_P[0..15]

PCIE_GTX_ C_MRX_N[0..15]

PCIE_MTX_ C_GRX_P[0..15] 17

PCIE_MTX_ C_GRX_N[0..15] 17

10 52Wed nesday, August 04, 2010

0.2

Change nam e to VCC G FX , 0625

U28F

+1.5V

D D

Reference PILLAR_ROCK CRB Rev1.0

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 board.

C C

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16

VCC_SM_AW16

VCC_SM_AT13

+VGFX_CORE

CHANGE To +VGFX_CORE ,0625

B B

VCC_AXG_SENSE

PAD

A A

VSS_AXG_SENSE

U28F

2600mA

AP33

VCC_SM_1

AN33

VCC_SM_2

BH32

VCC_SM_3

BG32

VCC_SM_4

BF32

VCC_SM_5

BD32

VCC_SM_6

BC32

VCC_SM_7

BB32

VCC_SM_8

BA32

VCC_SM_9

AY32

VCC_SM_10

AW32

VCC_SM_11

AV32

VCC_SM_12

AU32

VCC_SM_13

AT32

VCC_SM_14

AR32

VCC_SM_15

AP32

VCC_SM_16

AN32

VCC_SM_17

BH31

VCC_SM_18

BG31

VCC_SM_19

BF31

VCC_SM_20

BG30

VCC_SM_21

BH29

VCC_SM_22

BG29

VCC_SM_23

BF29

VCC_SM_24

BD29

VCC_SM_25

BC29

VCC_SM_26

BB29

VCC_SM_27

BA29

VCC_SM_28

AY29

VCC_SM_29

AW29

VCC_SM_30

AV29

VCC_SM_31

AU29

VCC_SM_32

AT29

VCC_SM_33

AR29

VCC_SM_34

AP29

VCC_SM_35

BA36

VCC_SM_36/NC

BB24

VCC_SM_37/NC

BD16

VCC_SM_38/NC

BB21

VCC_SM_39/NC

AW16

VCC_SM_40/NC

AW13

VCC_SM_41/NC

AT13

VCC_SM_42/NC

Y26

VCC_AXG_1

AE25

VCC_AXG_2

AB25

VCC_AXG_3

AA25

VCC_AXG_4

AE24

VCC_AXG_5

AC24

VCC_AXG_6

AA24

VCC_AXG_7

Y24

VCC_AXG_8

AE23

VCC_AXG_9

AC23

VCC_AXG_10

AB23

VCC_AXG_11

AA23

VCC_AXG_12

AJ21

VCC_AXG_13

AG21

VCC_AXG_14

AE21

VCC_AXG_15

AC21

VCC_AXG_16

AA21

VCC_AXG_17

Y21

VCC_AXG_18

AH20

VCC_AXG_19

AF20

VCC_AXG_20

AE20

VCC_AXG_21

AC20

VCC_AXG_22

AB20

VCC_AXG_23

AA20

VCC_AXG_24

T17

VCC_AXG_25

T16

VCC_AXG_26

AM15

VCC_AXG_27

AL15

VCC_AXG_28

AE15

VCC_AXG_29

AJ15

VCC_AXG_30

AH15

VCC_AXG_31

AG15

VCC_AXG_32

AF15

VCC_AXG_33

AB15

VCC_AXG_34

AA15

VCC_AXG_35

Y15

VCC_AXG_36

V15

VCC_AXG_37

U15

VCC_AXG_38

AN14

VCC_AXG_39

AM14

VCC_AXG_40

U14

VCC_AXG_41

T14

VCC_AXG_42

AJ14

VCC_AXG_SENSE

AH14

VSS_AXG_SENSE

AC82GM45_SLB94_B3_FCBGA1329

VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC SM

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43

VCC GFX NCTF

VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52

POWER

VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC GFX

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

+VGFX_CORE

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

Add Jump to split +VGFX_CORE from +1.05VS

+1.05VS

Add 0 ohm to discharge VCC GFX 0625

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

C199

C239

0.1U_0402_16V7K

Place close to the GMCH

Change to stuff,0629

J12

J12 JUMP_43X79

JUMP_43X79

112

J11 JUMP_43X79

0625

2 1

C127

DIS@

0_0402_5%

C689

330U_2.5V_M_R15

Reference PILLAR_ROCK CRB Rev1.0

VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13

C214

0.1U_0402_16V7K

C219

0.22U_0402_6.3V6K

C234

0.22U_0402_6.3V6K

VCC: 1930.4mA (GMCH), 1210.34mA (MCH)

+1.05VS

C17

220U_D2_4VM_R15

+VGFX_CORE

VCC_AXG: 6326.84mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

C134

UMA@

0.47U_0603_16V4Z

C475

UMA@

330U_D2E_2.5VM_R9

(270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)

10U_0805_10V6K

C139

C173

0.22U_0402_6.3V6K

Cavity Capacitors

C127

C175

UMA@

1U_0402_6.3V6K

C175

UMA@

10U_0805_10V6K

C131

0.1U_0402_16V4Z

C148

10U_0805_10V6K

UMA@

Cavity Capacitors

C163

C130

UMA@

0.1U_0402_16V4Z

UMA@

C164

+1.05VS

AG34 AC34 AB34 AA34

Y34 V34

U34 AM33 AK33

AJ33 AG33 AF33

AE33 AC33 AA33

W33

AH28 AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24

AJ23 AH23 AF23

Y33

V33 U33

T32

Place close to the GMCH

VCC_SM: 2600mA

+1.5V

(330UF*1, 22UF*2, 0.1UF*1)

C221

10U_0805_10V6K

C258

C244

0.1U_0402_16V4Z

Place on the edge

C228

0.1U_0402_16V7K

C198

0.47U_0603_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C254

0.1U_0402_16V7K

C237

1U_0402_6.3V6K

C245

0.1U_0402_16V7K

C220

1U_0402_6.3V6K

2010/04/22 2011/04/22

C232

0.1U_0402_16V7K

Compal Secret Data

Deciphered Date

U28G

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35

AC82GM45_SLB94_B3_FCBGA1329

VCC CORE

POWER

Title

Size Document Number Rev

Custom

PEW52 M/B LA-6632P Schematic

Date: Sheet

Date: Sheet of

+1.05VS

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28

VCC NCTF

VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

Compal Electronics, Inc.

Cantiga GMCH(5/7)-VCC

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

11 52Wednesday, August 04, 2010

0.2

L67

+1.05VS

VCCA_HPLL: 24mA

Please check Power source if want support IAMT

D D

(4.7UF*1, 0.1UF*1)

VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1)

1 2

MBK1608121YZF_0603

120Ohm@100MHz

L16

1 2

MBK1608121YZF_0603

VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)

UMA@

1 2

+3VS

L41

L41 MBK1608221YZF_0603

MBK1608221YZF_0603

C508

220U_D2_4VM_R15

C C

VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1)

+3VS

B B

A A

VCCA_TV_DAC: 40mA (0.1UF*1,

0.01UF*1 for each DAC)

L42

+3VS

180Ohm@100MHz

1 2

MBK1608221YZF_0603

+1.5VS

C532

0.1U_0402_16V4Z

UMA@

Close to Ball A26, B27

UMA@

1 2

L40

L40 MBK1608221YZF_0603

MBK1608221YZF_0603

UMA@

C530

UMA@

0.1U_0402_16V4Z

VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1)

1 2

MBK1608221YZF_0603

1 2

R29

100_0603_1%

180Ohm@100MHz

+1.05VS_HPLL

C635

4.7U_0805_10V4Z

+1.05VS_MPLL

R101

0.5_0603_1%

C125

C125 22U_0805_6.3V6M

22U_0805_6.3V6M

+3VS_CRTDAC

2 1

C544

UMA@

DIS@

0.01U_0402_16V7K

Please check Power source if want support IAMT

UMA@

C543

C531

UMA@

0.1U_0402_16V4Z

0.01U_0402_16V7K

Close to Ball A25

+3VS_TVDAC

C542

0.01U_0402_16V7K

UMA@

VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1)

C110

0.1U_0402_16V4Z

0.022U_0402_16V7K

C31

0.1U_0402_16V4Z

0.01U_0402_16V7K

C542

DIS@

C112

C109

C631

0.1U_0402_16V4Z

Please check Power source if want support IAMT

C162

0.1U_0402_16V4Z

0_0402_5%

+3VS_DACBG

R575

DIS@

0_0402_5%

2 1

0_0402_5%

+1.5VS_TVDAC

+1.5VS_QDAC

Also power for internal Thermal Sensor

+1.05VS

R441

R441 0_0402_5%@

0_0402_5%@

1 2

+3VS

R440

R440 0_0402_5%

0_0402_5%

1 2

+1.5VS

Please check Power source if want support IAMT

+1.05VS

C507

220U_D2_4VM_R15

FOR EMI 20080226

L39

1 2

MBK1608121YZF_0603

UMA@

VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1)

L51

1 2

MBK1608121YZF_0603

UMA@

FOR EMI 20080226

+VCCA_PEG_BG

+1.05VS

C613

10U_0805_6.3V6M

1 2

R117

0_0805_5%

Please check Power source if want support IAMT

+1.05VS

+1.05VS_DPLLA

C518

UMA@

220U_D2_4VM_R15

+1.05VS_DPLLB

C565

C565 10U_0805_10V6K

10U_0805_10V6K

UMA@

+1.8V_TX_LVDS

C629

0.1U_0402_16V4Z

No CIS Symbol

L66

1 2

MBK1608221YZF_0603

1 2

R437

R437 1_0402_1%

1_0402_1%

+1.05VS_A_SM

+1.05VS_A_SM_CK

1 2

R118

R118 0_0603_5%

0_0603_5%

2.2U_0603_6.3V6K

NO_STUFF

+1.05VS_HPLL

+1.8VS

C547

DIS@

C202

VCCD_PEG_PLL: 50mA (0.1UF*1)

Add 0 ohm for DIS@,0625

2 1

C546

DIS@

UMA@

0.1U_0402_16V4Z

C579

UMA@

0.1U_0402_16V4Z

2 1

C547

0_0402_5%

VCCA_PEG_BG: 0.414mA (0.1UF*1)

+1.05VS_PEGPLL

VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1)

C188

22U_0805_6.3V6M

C204

22U_0805_6.3V6M

R392

0_0402_5%

+3VS_CRTDAC

+3VS_DACBG

2 1

C579

DIS@

0_0402_5%

+3VS_TVDAC

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL

+1.05VS_MPLL

VCCA_LVDS: 13.2mA (1000PF*1)

UMA@

1000P_0402_50V7K

VCCA_PEG_PLL: 50mA

C624

(0.1UF*1)

0.1U_0402_16V4Z

C211

1U_0402_6.3V6K

C203

0.1U_0402_16V4Z

+1.5VS_TVDAC

+1.5VS_QDAC

C206

4.7U_0805_10V4Z

VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1, 0.1UF*1)

VCCD_HDA: 50mA (0.1UF*1)

Close to A32

VCCD_HPLL: 157.2mA (0.1UF*1)

+1.05VS_PEGPLL

UMA@

1 2

R62

R62 0_0603_5%

0_0603_5%

+1.8V_LVDS

C78

UMA@

10U_0805_6.3V6M

1U_0402_6.3V6K

VCCD_LVDS: 60.311111mA (1UF*1)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U28H

73mA

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

2.69mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

4.8mA

F47

VCCA_DPLLA

L48

VCCA_DPLLB

24mA

AD1

VCCA_HPLL

139.2mA

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

0.414mA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

480mA

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

24mA

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

87.79mA

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

50mA

A32

VCC_HDA

8.696mA

M25

VCCD_TVDAC

48.363mA

L28

VCCD_QDAC

157.2mA

AF1

VCCD_HPLL

0mA

AA47

VCCD_PEG_PLL

60.31mA

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

AC82GM45_SLB94_B3_FCBGA1329

C107

UMA@

DIS@

2010/04/22 2011/04/22

VTT: 852mA

+1.05VS

852mA

U13

VTT_1

T13

VTT_2

U12

VTT_3

T12

VTT_4

U11

VTT_5

T11

VTT_6

U10

VTT_7

T10

VTT_8

CRTPLLA LVDSA PEG

VTT

POWER

A SM

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

118.8mA

VCC_TX_LVDS

A CK

HDA

DMI PEG

VTTLF

LVDS D TV/CRT

2 1

0_0402_5%

Compal Secret Data

Deciphered Date

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

105.3mA

VCC_HV_1 VCC_HV_2 VCC_HV_3

1782mA

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

456mA

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

VCC_DMI: 456mA (0.1UF*1)

A8 L1 AB2

C503

220U_D2_4VM_R15

VCC_HV: 105.3mA

VTTLF_CAP1 VTTLF_CAP2 VTTLF_CAP3

C144

0.47U_0603_16V4Z

(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)

4.7U_0805_10V4Z

+1.05VS_AXF

C527

10U_0805_6.3V6M

+1.5V_SM_CK

+1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1)

C548

DIS@

+3VS

C79

0.1U_0402_16V4Z

+1.05VS_PEG: 1782mA (220UF*1, 22UF*1, 4.7UF*1)

+1.05VS_DMI

C602

0.47U_0603_16V4Z

C528

0.47U_0603_16V4Z

D21

+1.05VS +3VS

RB751V-40_SOD323-2

VCC_AXF: 321.35mA (10UF*1, 1UF*1)

C545

1U_0402_6.3V6K

2 1

10U_0805_10V6K

C21

C32

4.7U_0805_10V4Z

2.2U_0603_6.3V6K

1 2

R387

0_0603_5%

VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1)

C666

0.1U_0402_16V4Z

+1.8V_TX_LVDS

C520

C548

UMA@

0_0402_5%

1000P_0402_50V7K

+1.05VS_PEG

C37

C57

220U_D2_4VM_R15

1 2

R454

0_0805_5%

C637

0.1U_0402_16V4Z

R446

R446 10_0603_5%

10_0603_5%

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PEW52 M/B LA-6632P Schematic

C41

C51

0.47U_0603_16V4Z

1 2

R144

R144 1_0402_1%

1_0402_1%

10U_0805_10V6K

Crestline GMCH (6/7)-VCC

0.47U_0603_16V4Z

Please check Power source if want support IAMT

+1.05VS

1uH 30%

1 2

L68

MBK1608121YZF_0603

0.1uH 20%

UMA@

1 2

R373

R373 0_0603_5%

0_0603_5%

UMA@

1 2

0_1206_5%

+1.05VS

1 2

C283

C283 10U_0805_6.3V6M

10U_0805_6.3V6M

R28

+1.5V

+1.8VS

Please check Power source if want support IAMT

+1.05VS

Change R28 to 1206 footprint 0804

12 52Wednesday, August 04, 2010

0.2

U28I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

VSS_10

Y47

VSS_11

T47

BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

BC43 AV43 AU43

AM43

BG42 AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

BG40 BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36 BD36 AK15 AU36

N47 L47 G47

V46 R46 P46 H46 F46

Y44 U44 T44 M44 F44

C43

N42 L42

Y41 U41 T41 M41 G41 B41

H40 E40

N39 L39 B39

Y38 U38 T38

F38 C38

H37 C37

VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39

J43

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84

J38

VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS

AC82GM45_SLB94_B3_FCBGA1329

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6

U28J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

VSS_230

M17

VSS_231

H17

VSS_232

C17

BA16

AU16 AN16

BG15 AC15

BG14 AA14

BG13 BC13 BA13

AN13

AJ13

AE13

BF12

AV12

AT12

AM12

AA12

BD11 BB11

AY11 AN11 AH11

BG10 AV10

AT10

AJ10 AE10 AA10

N16

G16

W15

C14

N13

G13

N11 G11 C11

M10 BF9 BC9 AN9 AM9 AD9

BH8 BB8 AV8 AT8

VSS_233

VSS_235

VSS_237 VSS_238 VSS_239

K16

VSS_240 VSS_241

E16

VSS_242 VSS_243 VSS_244 VSS_245

A15

VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258

L13

VSS_259 VSS_260

E13

VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266

J12

VSS_267

A12

VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

Y11

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290

VSS_291

VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

VSS NCTF

AC82GM45_SLB94_B3_FCBGA1329

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5

VSS SCB

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1 A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/22 2011/04/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga GMCH(1/7)-GTL

PEW52 M/B LA-6632P Schematic

13 52Thursday, July 29, 2010

0.2

+DIMM_VREF

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2

D D

C C

B B

A A

DDRA_CKE08

DDR_A_BS29

DDRA_CLK08 DDRA_CLK0#8

DDR_A_BS09

DDR_A_WE#9

DDR_A_CAS#9 DDRA_ODT0 8

DDRA_SCS1#8

+3VS

DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDRA_CLK0 DDRA_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# DDRA_ODT0

DDR_A_MA13 DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R181

1 2

10K_0402_5%

C332

C331

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

+1.5V +1.5V

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

R180

10K_0402_5%

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0

EVENT# VDDSPD SA1 VTT1

+0.75VS

FOX_AS0A626-U8SN-7F

CONN@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

SDA SCL

VTT2

A15 A14

A11

A6 A4

A2 A0

S0#

DIMM0 REV H:5.2mm (BOT)

DDR_A_D4

DDR_A_D5

6 8

DDR_A_DQS#0

DDR_A_DQS0

12 14

DDR_A_D6

DDR_A_D7

18 20

DDR_A_D12

DDR_A_D13

24 26

DDR_A_DM1

SM_DRAMRST#

30 32

DDR_A_D14

DDR_A_D15

36 38

DDR_A_D20

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

DDR_A_D23

52 54

DDR_A_D28

DDR_A_D29

58 60

DDR_A_DQS#3

DDR_A_DQS3

64 66

DDR_A_D30

DDR_A_D31

70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDRA_CKE1

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDRA_CLK1 DDRA_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDRA_SCS0#

DDRA_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0 D_CK_SDATA D_CK_SCLK

+0.75VS

SM_DRAMRST# 8,15

DDRA_CKE1 8

DDRA_CLK1 8 DDRA_CLK1# 8

DDR_A_BS1 9 DDR_A_RAS# 9

DDRA_SCS0# 8

DDRA_ODT1 8

PM_EXTTS#0 8

D_CK_SDATA 15,16 D_CK_SCLK 15,16

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

C350

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF

C347

Layout Note: Place near JDIMM2

+1.5V

10U_0603_6.3V6M

C337

C351

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

C3541U_0603_10V6K C3541U_0603_10V6K

Compal Secret Data

2010/04/22 2011/04/22

Compal Secret Data

Deciphered Date

DDR_A_DQS#[0..7]9

DDR_A_D[0..63]9

DDR_A_DM[0..7]9

DDR_A_DQS[0..7]9

DDR_A_MA[0..14]9

+DIMM_VREF15

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0603_6.3V6M

C339

C352

C336

C3551U_0603_10V6K C3551U_0603_10V6K

C336

C3301U_0603_10V6K C3301U_0603_10V6K

C3291U_0603_10V6K C3291U_0603_10V6K

10U_0603_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

C333

C353

C346

Title

Size Document Number Rev

PEW52 M/B LA-6632P Schematic

Date: Sheet of

+DIMM_VREF

C341

0.1U_0402_16V4Z

C349

Compal Electronics, Inc.

+1.5V

R173

1K_0402_1%

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C348

DDRIII-SODIMM0

R173

+DIMM_VREF

C335

R176

1K_0402_1%

C334

C696

C696 330U_2.5V_M_R15

330U_2.5V_M_R15

0.2

14 52Wednesday, August 04, 2010

0.2

+1.5V +1.5V

+DIMM_VREF

JDIMM2

+DIMM_VREF14

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1 1

2 2

3 3

4 4

+3VS

C368

DDR_B_BS29

DDRB_CLK08 DDRB_CLK0#8

DDR_B_BS09

DDR_B_WE#9

DDR_B_CAS#9

DDRB_SCS1#8

C371

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2

C369

DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDRB_CLK0 DDRB_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS# DDRB_ODT0

DDR_B_MA13 DDRB_SCS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R197

1 2

10K_0402_5%

1 2

R211

10K_0402_5%

C370

0.1U_0402_16V4Z

2.2U_0603_6.3V6K

JDIMM2

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

FOX_AS0A626-U4SN-7F

CONN@

DIMM1 REV H:9.2mm (BOT)

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

+0.75VS

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

DDR_B_D4

DDR_B_D5

6 8

DDR_B_DQS#0

DDR_B_DQS0

12 14

DDR_B_D6

DDR_B_D7

18 20

DDR_B_D12

DDR_B_D13

24 26

DDR_B_DM1

SM_DRAMRST#

30 32

DDR_B_D14

DDR_B_D15

36 38

DDR_B_D20

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

DDR_B_D23DDR_B_D18

52 54

DDR_B_D28

DDR_B_D29

58 60

DDR_B_DQS#3

DDR_B_DQS3

64 66

DDR_B_D30

DDR_B_D31

70 72

DDRB_CKE1

74 76 78

A15 A14

A11

A6 A4

A2 A0

S0#

DDR_B_MA14

80 82

DDR_B_MA11

DDR_B_MA7

86 88

DDR_B_MA6

DDR_B_MA4

92 94

DDR_B_MA2

DDR_B_MA0

98 100

DDRB_CLK1

102

DDRB_CLK1#

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDRB_SCS0#

114 116 118

DDRB_ODT1

120 122 124 126 128

DDR_B_D36

130

DDR_B_D37

132 134

DDR_B_DM4

136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168

DDR_B_DM6

170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196

PM_EXTTS#1

198

D_CK_SDATA

200

D_CK_SCLK

202 204

206

+0.75VS

SM_DRAMRST# 8,14

DDRB_CKE1 8DDRB_CKE08

DDRB_CLK1 8 DDRB_CLK1# 8

DDR_B_BS1 9 DDR_B_RAS# 9

DDRB_SCS0# 8 DDRB_ODT0 8

DDRB_ODT1 8

2.2U_0603_6.3V6K

PM_EXTTS#1 8

D_CK_SDATA 14,16 D_CK_SCLK 14,16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+DIMM_VREF

0.1U_0402_16V4Z

C388

C389

2010/04/22 2011/04/22

Layout Note: Place near JDIMM1

+1.5V

10U_0603_6.3V6M

C397

C361

Layout Note: Place near JDIMM1.203 & JDIMM1.204

+0.75VS

1U_0603_10V6K

C363

Compal Secret Data

10U_0805_6.3V6M

C365

1U_0603_10V6K

C377

Deciphered Date

10U_0603_6.3V6M

C378

DDR_B_DQS#[0..7]9

DDR_B_D[0..63]9

DDR_B_DM[0..7]9

DDR_B_DQS[0..7]9

DDR_B_MA[0..14]9

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0603_6.3V6M

C364

C398

1U_0603_10V6K

C374

C362

10U_0603_6.3V6M

0.1U_0402_16V4Z

C367

C396

10U_0805_6.3V6M

C367

0.1U_0402_16V4Z

C366

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_16V4Z

C394

C393

Compal Electronics, Inc.

PEW52 M/B LA-6632P Schematic

C411

@+C411

330U_D2E_2.5VM_R9

DDRIII-SODIMM1

15 52Wednesday, August 04, 2010

0.2

FSLC FSLB FSLA CPU

CLKSEL2 CLKSE L1 CLKSEL0

MHz

0 0 0 266 100 33.3

1 1

0 1

CLK_REQ#

200 100 33.3

Table : ICS9LPRS387

Control

CR#_10(WLAN) PCIEX10 PCIEX0

CR#_6(MCH)

CR#_4(NEW CARD)

CR#_9(MINI CARDII)

PCIEX6

PCIEX4

PCIEX9

SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable]

+3VS

CLK_PCI2=1, Trusted Mode Enable(No overclocking al lowed)

1 2

R264 10K_0 402_5%

CLK_PCI2

mount to Enable ITP_CLK

1 2

R279 10K_0 402_5%

1 2

R277 10K_0 402_5%

2 2

R277 10K_0 402_5%

CLK_PCI5=0, Pin63,64 is SRC_CLK CLK_PCI5=1, Pin63,64 is ITP_CLK

1 2

R274 10K_0 402_5%

CLK_PCI4=0, Pin28, 29 is SRC_CLK Pin24, 25 is DOT96_CLK

1 2

R218 10K_0 402_5%

C438 10 P_0402_50V8J@C4 38 10P_0402_5 0V8J@

1 2

C442 10 P_0402_50V8J@C4 42 10P_0402_5 0V8J@

1 2

CLK_PCI5

CLK_PCI4

CK_PW RGD

For EMI 10/9

+1.05VS

R285

56_0402 _5%@

R286

+1.05VS

1 2

R235

1K_0402 _5%@

R233

R233 1K_0402 _5%

1K_0402 _5%

1 2

R229

R229 0_0402_ 5%

0_0402_ 5%

R249

1K_0402 _5%@

R243

R243 1K_0402 _5%

1K_0402 _5%

1 2

R286 1K_0402 _5%

1K_0402 _5%

1 2

Add R578 , 0625

R282

3 3

CLKSEL0

R282

2.2K_040 2_5%

1 2

R281

R281 1K_0402 _5%@

1K_0402 _5%@

Add R580 , 0625

CLKSEL1

1 2

R238

R238 0_0402_ 5%

0_0402_ 5%

4 4

R250

R250 10K_040 2_5%

10K_040 2_5%

CLKSEL2

1 2

R244

R244 0_0402_ 5%

0_0402_ 5%

Add R581 , 0625

SRC MHz

CLK_PCI_L PC

CLK_PCI_ICH

MCH_CLK SEL0 8

MCH_CLK SEL1 8

CPU_BSE L1 5

MCH_CLK SEL2 8

CPU_BSE L2 5

PCI MHz

33.3100166

Free-Run

PCIEX1

+3VS

CPU_BSE L0 5

+1.05VS

L34

+3VS

FBMA-L11 -201209-221LMA 30T_0805

L32

+1.5VS

FBMA-L11 -201209-221LMA 30T_0805

R226

R226 10K_040 2_5%

10K_040 2_5%

1 2

CK505_P WRGD

Q18

Q18 2N7002E -T1-GE3_SOT23-3

2N7002E -T1-GE3_SOT23-3

L37

FBMA-L11 -201209-221LMA 30T_0805

C449

C449 10U_080 5_10V6K

10U_080 5_10V6K

CLK_ENA BLE# 49

CLK_PCI_L PC35

CLK_PCI_ICH26

CLK_ICH_4 8M28 CLK_SD_ 48M3 1

CLK_ICH_1 4M28

+CLK_VD D1

ICH_SMBDA TA28,33

ICH_SMBCL K28,33

+CLK_VD DSRC

C443

10U_080 5_10V6K

C399

0.1U_040 2_16V4Z

10U_080 5_10V4Z

+CLK_VD DSRC

C422

1 2

27P_040 2_50V8J

C414

27P_040 2_50V8J

1 2

C403

C446

0.1U_040 2_16V4Z

C405

0.1U_040 2_16V4Z

+CLK_VD D1

CLK_PCI_L PC CLK_PCI3

CLK_PCI_ICH CLK_PCI5

CK_PW RGD28

VGATE8,28,4 9

CLK_ICH_4 8M CLK_SD_ 48M

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_040 2_16V4Z

+3VS

1 3

+3VS

1 3

C447

C407

0.1U_040 2_16V4Z

R223

1 2

0_0402_ 5%

0_0402_ 5% R224

R224

1 2

0_0402_ 5% @

H_STP_C PU#28

H_STP_P CI#2 8

R270 33 _0402_5% R270 33 _0402_5%

R276 33 _0402_5% R276 33 _0402_5%

14.31818 MHz_20P_FSX8L 14.318181M20FD B

R283 22 _0402_5% R283 22 _0402_5% R284 22 _0402_5% R284 22 _0402_5%

R248 33 _0402_5% R248 33 _0402_5%

R232

4.7K_040 2_5%

1 2

D_CK_SD ATA

Q19

Q19 2N7002E -T1-GE3_SOT23-3

2N7002E -T1-GE3_SOT23-3

R242

4.7K_040 2_5%

1 2

Q20

Q20 2N7002E -T1-GE3_SOT23-3

2N7002E -T1-GE3_SOT23-3

D_CK_SC LK

C448

C417

0.1U_040 2_16V4Z

+CLK_VD DSRC

+CLK_VD DSRC_R

0.1U_040 2_16V4Z

R2250_0402_ 5% R22 50_0402_ 5%

R2310_0402_ 5% @ R 2310_0402_5% @

12 12

+3VS

2010/04/ 22 201 1/04/22

C439

+CLK_VD D

+CLK_VD D1

C404

H_STP_C PU#

H_STP_P CI#

CLK_PCI2

CLK_PCI4

CK505_P WRGD

CLK_XTA LIN

CLK_XTA LOUT

CLKSEL0

CLKSEL1

CLKSEL2CLK_ICH_1 4M

+3VS

U15

VDDREF

VDD48

VDDCPU

VDDPCI

VDDPLL3

VDDSRC

VDDSRC_IO

VDDPLL3_IO

VDDCPU_IO

VDD96_IO

CPU_STOP#

PCI_STOP#

PCI1

PCI2/TME

PCI3

PCI4/27_SELECT

PCI_F5/ITP_EN

CK_PWRGD/PD#

USB_48MHz/FSLA

FSLB/TEST_MODE

FSLC/TEST_SEL/REF0

REF1

GNDCPU

GNDREF

GNDPCI

GND48

GND

GNDSRC

GND_THERMAL_PAD

ICS9LPRS3 87BKLFT_MLF7 2_10x10

Compal Secret Data

Deciphered Date

L36

FBMA-L11 -201209-221LMA 30T_0805

C391

C391 10U_080 5_10V6K

10U_080 5_10V6K

ICS9LPRS387, PN:SA000020H10 SLG8SP556V, PN:SA000020K00 RTM875N, PN:SA000020N00

------------------------LOW Power RTM890N, PN:SA00003H730 ICS9LVRS387, PN:SA00003H610

+CLK_VD D

0.1U_040 2_16V4Z

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT3_LPR

SRCC3_LPR

SRCT4_LPR

SRCC4_LPR

SRCT6_LPR

SRCC6_LPR

SRCT7_LPR

SRCC7_LPR

SRCT9_LPR

SRCC9_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

C435

0.1U_040 2_16V4Z

SDATA

SCLK

CR#3

CR#4

CR#6

CR7#

CR#9

CR10#

CR#11

CR#A

Title

Size Document Number Rev

Date: Sheet of

C437

10U_080 5_10V6K

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

Clock Generator

C425

C444

0.1U_040 2_16V4Z

D_CK_SD ATA

D_CK_SC LK

CLK_CPU _BCLK

CLK_CPU _BCLK#

CLK_MCH _BCLK

CLK_MCH _BCLK#

CLK_DRE F_96M

CLK_DRE F_96M#

CLK_DRE F_SSC

CLK_DRE F_SSC#

CLK_PCIE_ SATA

CLK_PCIE_ SATA#

CLK_PCIE_ ICH

CLK_PCIE_ ICH#

CLK_MCH _3GPLL

CLK_MCH _3GPLL#

CLK_PCIE_ VGA

CLK_PCIE_ VGA#

CLK_PCIE_ MINI1

CLK_PCIE_ MINI1#

CLK_PCIE_ LAN

CLK_PCIE_ LAN#

(Pull High to +3VS at GMCH side)

R583 0_0402_ 5%R583 0_0402_5%

Custom

1 2

R265 10K_0402_5%

1 2

R256 10K_0402_5%

(Pull High to +3VS at ICH side)

Compal Electronics, Inc.

Clock Generator (CK505)

PEW52 M/B LA-6632P Schematic

VGA: disable this pair by BIOS

GA: disable this pair by BIOS

R5800_0402_5% R58 00_0402_ 5%

R574 10 K_0402_5%R574 10 K_0402_5%

1 2

D_CK_SC LK 1 4,15

CLK_CPU _BCLK 4

CLK_CPU _BCLK# 4

CLK_MCH _BCLK 7

CLK_MCH _BCLK# 7

CLK_DRE F_96M 8

CLK_DRE F_96M# 8

CLK_DRE F_SSC 8

CLK_DRE F_SSC# 8

CLK_PCIE_ SATA 2 7

CLK_PCIE_ SATA# 27

CLK_PCIE_ ICH 28

CLK_PCIE_ ICH# 28

CLK_MCH _3GPLL 8

CLK_MCH _3GPLL# 8

CLK_PCIE_ VGA 17

CLK_PCIE_ VGA# 17

CLK_PCIE_ MINI1 33

CLK_PCIE_ MINI1# 33

CLK_PCIE_ LAN 32

CLK_PCIE_ LAN# 32

MCH_CLK REQ# 8

Add R580,07/28

+3VS

MINI1_CLKREQ # 33

+3VS

LAN_CLK REQ# 32

SATA_CL KREQ# 28

D_CK_SD ATA 14,1 5

+3VS

PEG_CLK REQ# 18

16 52Wed nesday, August 04, 2010

0.2

+ 37 hidden pages

Compal LA-6632P PEW52 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual