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LA-6611P PAL70
Schematic
65 pgs3.15 Mb0

Compal LA-6611P PAL70 Schematic

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ϯD>>EϭϯΗhD
COMPAL CONFIDENTIAL
BGA Sandy Bridge +
PAL70
1 1
PCB NO :
BOM P/N :
O MAP Version 1010
GPI
MODEL NAM
E :
LA-6611P (DAA
43XXXXXXLXX
00001W10)
FCBGA PCH Cougar Point-M
2010-01-21
REV
: 1.0(A00)
Items R1 P/N R3 P/N

CPU 2.5G SA00004EL2L SA00004EL3L CPU 2.6G SA00004EM2L SA00004EM3L CPU 2.7G SA00004F02L SA00004F03L CPU 2.1G SA00004KP1L SA00004KP2L PCH SA00004IW2L SA00004IW3L LAN SA00003SI4L SA00003SI5L
   

USH SA00003AO1L SA00003AO2L
@ : Nopop Component
DdLJƉĞ
Ϯϱ'WhdWDEdD/^td
2 2
Ϯϱ'WhdWDEdD/^t^W/
Ϯϱ'WhdWD/^dDE
Ϯϱ'WhdWD/^dDEt^W/
Ϯϱ'WhdWD/^dD/^
Ϯϱ'WhdWD/^dD^/t^W/
Ϯϲ'WhdWDEdD/^td
Ϯϲ'WhdWDEdD/^t^W/
Ϯϲ'WhdWD/^dDE
3 3
Ϯϲ'WhdWD/^dDEt^W/
Ϯϲ'WhdWD/^dD/^
Ϯϲ'WhdWD/^dD^/t^W/
Ϯϳ'WhdWDEdD/^td
Ϯϳ'WhdWDEdD/^t^W/
Ϯϳ'WhdWD/^dDE
Ϯϳ'WhdWD/^dDEt^W/
Ϯϳ'WhdWD/^dD/^
4 4
Ϯϳ'WhdWD/^dD^/t^W/
KDWE
ϰϯϭϵϯϰϯϭ>Ϭϲ
ϰϯϭϵϯϰϯϭ>Ϭϯ
ϰϯϭϵϯϰϯϭ>ϭϱ
ϰϯϭϵϯϰϯϭ>Ϭϳ
ϰϯϭϵϯϰϯϭ>Ϭϰ
ϰϯϭϵϯϰϯϭ>ϭϲ
ϰϯϭϵϯϰϯϭ>Ϭϴ
ϰϯϭϵϯϰϯϭ>Ϭϱ
ϰϯϭϵϯϰϯϭ>ϭϳ
ϭΛ ϮΛ
*
*
*
*
*
*
ϯΛ ϰΛ
*
*
*
*
*
*
*
*
*
*
*
*
**
**
*
*
**
**
*
*
**
**
*
*
dWD dD
tŝƚŚ^W/
ϱΛ
*
*
*
*
*
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tŝƚŚd
ϲΛ
*
*
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MB PC
MB PC
B
B
Part Number Description
Part Number Description
DAA00001W00
DAA00001W00
PCB PAL70 LA6611
PCB PAL70 LA6611
DELL CONFIDENTIAL/PROPRIETA
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
Comp
Comp
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Comp
Cover
Cover
Cover
LA-6611P
LA-6611P
LA-6611P
nesday, January 26, 2011
nesday, January 26, 2011
nesday, January 26, 2011
Sheet
Sheet
Sheet
164Wed
164Wed
164Wed
E
RY
of
of
of
Block Diagram
A
Compal confidential
B
Model: PAL70
C
D
E
Memory BUS (DDR3)
1066/1333MH
1 1
Sandy B
idge
r
z
DDRIII-DIMM X2
BA
NK 0, 1, 2, 3, 4 ,5 ,6 ,7
page 12~13
LVDS CONN
page 24
CRT CONN
/K
VGA
2 2
3 3
DOCKING
RT
PO
page 41
DAI
USB
SATA
LAN
DOCK
ni Card
EXPRESS
Card
page 38 page 37page 37page 37
USB
CPU ITP Por
PCH ITP Por
1/2 Mi
page 7
page 14
Flas
USB
t
t
PCIE
h
Thermal
GUARDIAN III EMC4022
4 4
WiFi ON/OFF
DC/DC Inte
Powe SW & LED
page 45
r On/Off
page 46
page 22
/K
rface
A
For MB/Dock Video Switch PI3V712-AZLE
page 25
HDMI CONN
page 26
C
SDX
page 36 page 36
PCIE
ni Card
1/2 Mi
Smart
RFID
FAN
page 22
WLA
USB
Card
page 34
page 34
N
Card reader
OZ600FJ0LN
PCI Exp
PCIEPCIE
ini Card
Full M
TD
Fingerprint CONN
WWAN
USB
A8034HN
page 34
page 23
/UWB
SMSC SIO
E5028
EC
page 42
ress BUS
Optio
FP_USB
BC BUS
B
LVDS
VGA
DPB
DP
C
DPD
PCIE x1
n
CB
SSX35B
page 35
TPM1
M5882
page 34~35
USB
.2
USH
BC
SMSC KBC
ME
C5055
page 43
page 44 page 44
KB CONNTP CONN
4MB (Socket
BGA CPU
1023 pins
COUGAR POIN
LPC BUSChina TPM1.2
FDI
x 8
Lane
INTEL
BGA
SP
I
G1)
page 6~11
DMI
x 4
Lane
USB
T-M
page 14~21
HD Audio I/F
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
page 14
ector
E
page 14
ector
PCIE
E
TA Repeater
SA
MAX4951BECTP+
Module
E-
page 29
page 29
W25X64Z
64M 4K s
W25X16Z
16M 4K s
C
SATA
PCI Exp
BT
Camera
SATA Repeater MAX4951BECTP+
ress BUS
HDD
page 28
D
page 44
page 24
page 14
HDA Codec 92H
D
Troug
h LVDS Cable
E-SATA
USB
page 40
B
US
page 39
l Lewisville
Inte
DOCK LAN
T.Speaker
IN
page 30
82579LM
LAN PI3L720
90B2
page 30
HeadPhone &
Tr
MIC Jack
/K
DAI
To Dock
ing side
Dig. MIC
Trough LVDS Cable
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
UMA Block
UMA Block
UMA Block
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
Diagram
Diagram
Diagram
E
page 32
SWITCH
page 32
ansformer
page 33
RJ4
5
page 33
/PROPRIETARY
264We
264We
264We
of
of
of
5
4
3
2
1
State
ATES
Signal
SLP
SLP
SLP
#
S4#
S3
HIGH
HIGH
W HIGH HIGH HIGH ON ON ON OFF
LO
LOW
LOW HIGH HIGHLOW
LOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
S4
S5#
STATE#
HIGH HIGH
HIG
H
SLP M#
HIG
HIGH
H
ALWAYS PLANE
ON
M PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
USB PORT#
0
1
2
3
4
5
6
7
DESTINA
T
ION
JUSB1 (Ext Right Side)
none
Right Side (ESA
TA)
none
WLAN/WIMAX
WWAN/UWB
Flash
USH->BIO
POWER ST
S0 (
Full ON) / M0
D D
S3 (Suspend to RAM) / M1
S4 (Suspend to DISK) / M1 ON ON OFF
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
(Suspend to RAM) / M-OFF
S3
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
DOCKING8
PM T
ABLE
C C
pow plane
State
S0
S3
S5 S4/AC
S4/AC don't exist
S5
B B
SATA
TA 0
SA
SATA
1
SATA 2
SATA 3
4
A A
SATA
SATA 5
+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
r
e
+3.3V_RTC_LDO
ON
ON
DESTINAT
HDD
ODD/ E3 Module Bay
NA
NA
ESATA
k
Doc
5
V_SUS
+3.3
+1.5V_MEM
ON ON
ON
OFF
OFFOFF
ION
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
OFF
OFF
4
+3.3
+1.
V_M
05V_M
ON
ON
ON
V_M
+3.3
+1.05V_M
(M-OFF)
ON
OFF
OFF
OFFOFF
Stack up
Thickness
Layer
SolderMask
Add Plating
Top/L1(signal)
Prepreg
Core
L3(IN1)
Prepreg
L4(IN2)
Core
L5(GND2)
Prepreg
L6(IN3)
Core
L7(IN4)
Prepreg
L8(VCC)
Core
L9(IN5)
Prepreg
L10(IN6) 0.5oz 0.65
Core 3mil 3.09
L11(GND3) 0.5oz
Prepreg
Bottom/L12(signal)
Add Plating
SolderMask
Overall Thickness
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
(Material SPEC.) Unit : mil
min 0.4
1.30
0.5oz(0.68)
1080LRC
0.5oz
3mil
0.5oz
1080LRC+1080
1oz
3mil
1oz
1080HRC
0.5oz
6mil
0.5oz
1080HRC
1oz
3mil
1oz
1080LRC+1080
1080LRC 2.65
0.5oz(0.68)
1.30
min 0.4
1.36mm+/-10%
3
Thickness (Actuality) Unit : mil
0.50
1.05
0.65
2.65
0.65
3.09
0.65
5.1
1.35
3.09
1.35
2.90
0.65
6
0.65
2.90
1.35
3.09
1.35
5.1
0.65
0.65
1.05
0.50
53.36
USH
2
9
DOCKING
10 Express car
11
12
13
Bluetooth
Cam
none
0
1
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 N
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
d
era
BIO
NA
DESTINAT
MI
NI CARD-1 WWAN
MI
NI CARD-2 WLAN
Express car
ION
d
E3 Module Bay (USB3)
1/
2vMINI CARD-3 PCIE
MMI
10/100/1G LOM
one
/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
and Config.
and Config.
and Config.
Index
Index
Index
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
1
364We
364We
364We
of
of
of
5
+V_DDR_REF
ADAPTER
D D
+0.75V_DDR_VT
4
TPS51206
(PU5
)
T
3
N
HDDC_E
2
ODD_MOD
SI
3456BDVSI3456BDV
(Q
30)@(Q27)
SN1003055
(PU7
)
S
M3K7002F
S
@(QH4)
1
+1
.05V_RU
N_VTT
SI
4164DY
(Q63)
AO
V_CPU_VDDQ
+1.5
+PWR_SRC
BAT
TERY
V_RUN
+1.5
CHARG
ER
C C
V_RUN
+1.8
4728L
(QC3)
NTGS4144
(Q
59)
1.5V_R
UN_ENABLE
ALWON
TPS51311
(PU4
+3.
3V_SUS
3456BDV
SI
(Q
MA
X17511
)
(PU9
B B
VP_VR_ON IM
+VCC_CORE
+V
CC_GFXCORE
IS
L95870A
U13)
(P
VTT_ON
CPU_
+0.
8V_VCC_SA
FDC654P
(Q21)
NVPWR
EN_I
+BL_
PWR_SRC
_WOWL
AUX_EN
SI
3456BDV
(Q38)
WWAN_PWREN
MCARD_
SI
3456BDV
(Q40)
5V_MEM
+1.
)
54)
MC
ARD_PCIE_BKT_PWREN
+1.
RUN_O
05V_M
SUS_ON
S13456
(
Q42)
N
+5V_HDD
MAX17020
)
(PU2
3V_ALW
+3.
AUX_ON
SI
3456
(Q34) (Q55)
+5V_
MOD
SN1003055
(PU3
SN1003055
(PU6
PCH
_ALW_ON
RUN_ON
NTM
)
)
S4920
PJP6
SI
3456BDV
(Q
49)
3
A_ON
SI
3456BDV
58)
(Q
+5V_
+15V
ALW
_ALW
+3.
3V_ALW_PCH
SI
ALW_ENABLE
+5V_
RUN_O
EN_LCDPWR
3456BDV
18)
(Q
ALW_PCH
N
05V_RUN
+1.
4164DY
SI
(Q50)
+5V_RUN
3V_WLAN
+3.
A A
5
4
+3.3
+3.
Pop option
V_RUN
3V_PCIE_WWAN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3V_PCIE_FLASH
+3.
3
+3.
3V_LAN
+3.3
V_RUN
2
+3.3V_M
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+LCDVDD
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Power
Power
Power
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
Rail
Rail
Rail
1
464We
464We
464We
of
of
of
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBC LK
MEM_
SMBDATA
PCH
D D
N_SMBCLK
2.2K
B4
A3
B5
A4
LA
LAN_SMBDATA
2.2K
DOCK_
SMB_CLK
DOCK_SMB_DAT
_SMBCLK
LCD
LCD_SMDATA
+3.3V_ALW_PCH
C8
G12
M16E14
SM
L1_SMBDATA
SM
L1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
2N7002
2N7002
SMBUS Address [C8]
DDR_X
DDR_XDP_WAN_SMBDAT
2.2K
2.2K
+3.3V_ALW
127
129
DOCKING
2.2K
2.2K
+LCD_VDD
Keep pull up only for PWM LCD
3
DP_WAN_SMBCLK
SMBUS Address
APR_EC: 0x48 SPR_EC: 0x70 MSLICE_EC: 0x72 USB: 0x59 AUDIO: 0x34 SLICE_BATTERY: 0x17 SLICE_CHARGER: 0x13
202
200
202
200
2
MMA
DI
DI
MMB
30
32
WWAN
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
1
2.2K
G Se
+3.3V_RUN
nsor
SMBUS Address [TBD]
2.2K
14
13
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
7
6
M9
L9
7
8
10
9
31
32
8
9
ERY
BATT CONN
USH
x
press card
E
ger
Char
Module Bay
E3
A/D,
D/A
converter
SMBUS Address [0x16]
SMBUS Address [0xa4]
SMBUS Address [TBD]
SMBUS Address [0x12]
SMBUS Address [0xd2]
SMBUS Address [0x30]
3
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Co
US TOPOLOGY
US TOPOLOGY
US TOPOLOGY
SMB
SMB
SMB
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
564We
564We
564We
1
of
of
of
KBC
A56
1C1CB59
PBA
T_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
1E
B53
B B
C 5055
ME
1E
A49
2B
B52
2B
SMBCLK
USH_
USH_S
MBDAT
CARD_S
MBCLK
CARD_SMBDAT
2.2K
2.2K
2.2K
B50
1G
A47
1G
R_SMBCLK
CHARGE
CHARGER_SMBDAT
2.2K
2.2K
B7
_SMBDAT
A7
BAY
BAY_SMBCLK
2D
A A
2D
2.2K
2.2K
B49
B48
DAI_SMBCLK
DAI_SMBDAT
2A
2A
5
2.2K
5
;ϭͿW'ͺZKDWK;'ϰͿƵƐĞϰŵŝůĐŽŶŶĞĐƚƚŽW'ͺ/KDW/ƚŚĞŶƵƐĞϰŵŝůĐŽŶŶĞĐƚƚŽZϮ ;ϮͿW'ͺ/KDWKƵƐĞϭϮŵŝůĐŽŶŶĞĐƚƚŽZϮ
U1A
U1A
_CRX_PTX_N0
DMI
_CRX_PTX_N016 _CRX_PTX_N116
DMI DMI
_CRX_PTX_N216 _CRX_PTX_N316
D D
C C
B B
DMI
DMI
_CRX_PTX_P016 _CRX_PTX_P116
DMI
I
_CRX_PTX_P216
DM
_CRX_PTX_P316
DMI
_CTX_PRX_N016
DMI DMI
_CTX_PRX_N116
DMI
_CTX_PRX_N216 _CTX_PRX_N316
DMI
_CTX_PRX_P016
DMI DMI
_CTX_PRX_P116 _CTX_PRX_P216
DMI DMI
_CTX_PRX_P316
FDI_
CTX_PRX_N016 CTX_PRX_N116
FDI_ FDI_
CTX_PRX_N216 CTX_PRX_N316
FDI_ FDI_
CTX_PRX_N416
FDI_
CTX_PRX_N516
FDI_
CTX_PRX_N616
FDI_
CTX_PRX_N716
CTX_PRX_P016
FDI_ FDI_
CTX_PRX_P116 CTX_PRX_P216
FDI_ FDI_
CTX_PRX_P316
FDI_
CTX_PRX_P416 CTX_PRX_P516
FDI_ FDI_
CTX_PRX_P616 CTX_PRX_P716
FDI_
_FSYNC016
FDI FDI
_FSYNC116
I_INT16
FD
_LSYNC016
FDI FDI
_LSYNC116
;ϭͿWͺKDW/KƵƐĞϰŵŝůƚƌĂĐĞƚŽZϭ ;ϮͿWͺ/KDWKƵƐĞϭϮŵŝůƚŽZϭ
DMI
_CRX_PTX_N1
DMI DMI
_CRX_PTX_N2
DMI
_CRX_PTX_N3
DMI
_CRX_PTX_P0 _CRX_PTX_P1
DMI DMI
_CRX_PTX_P2
I
_CRX_PTX_P3
DM
DMI
_CTX_PRX_N0 _CTX_PRX_N1
DMI DMI
_CTX_PRX_N2 _CTX_PRX_N3
DMI
DMI
_CTX_PRX_P0 _CTX_PRX_P1
DMI DMI
_CTX_PRX_P2 _CTX_PRX_P3
DMI
CTX_PRX_N0
FDI_ FDI_
CTX_PRX_N1 CTX_PRX_N2
FDI_ FDI_
CTX_PRX_N3 CTX_PRX_N4
FDI_ FDI_
CTX_PRX_N5
FDI_
CTX_PRX_N6 CTX_PRX_N7
FDI_
FDI_
CTX_PRX_P0 CTX_PRX_P1
FDI_ FDI_
CTX_PRX_P2 CTX_PRX_P3
FDI_ FDI_
CTX_PRX_P4
FDI_
CTX_PRX_P5 CTX_PRX_P6
FDI_ FDI_
CTX_PRX_P7
FDI
_FSYNC0 _FSYNC1
FDI
FD
I_INT
FDI
_LSYNC0 _LSYNC1
FDI
EDP_CO
MP
W11
AC9
W10
AC8
AA11 AC12
AA10
AG8
AD2
AG11
AG4
AC3 AC4
AE11
AC1
AE10
M2
DMI
_RX#[0]
P6
_RX#[1]
DMI
P1
DMI
_RX#[2]
P10
I
_RX#[3]
DM
N3
DMI
_RX[0]
P7
_RX[1]
DMI
P3
DMI
_RX[2]
P11
_RX[3]
DMI
K1
DMI
_TX#[0]
M8
DMI
_TX#[1]
N4
DMI
_TX#[2]
R2
_TX#[3]
DMI
K3
DM
I_TX[0]
M7
DM
I_TX[1]
P4
I_TX[2]
DM
T3
I_TX[3]
DM
U7
I0_TX#[0]
FD FD
I0_TX#[1]
W1
I0_TX#[2]
FD
AA6
I0_TX#[3]
FD
W6
I1_TX#[0]
FD
V4
FD
I1_TX#[1]
Y2
I1_TX#[2]
FD
I1_TX#[3]
FD
U6
FDI
0_TX[0] 0_TX[1]
FDI
W3
FDI
0_TX[2]
AA7
0_TX[3]
FDI
W7
FDI
1_TX[0]
T4
1_TX[1]
FDI
AA3
1_TX[2]
FDI FDI
1_TX[3]
FDI
0_FSYNC 1_FSYNC
FDI
U11
FD
I_INT
0_LSYNC
FDI
1_LSYNC
FDI
AF3
eDP
_COMP IO
e
P_ICOMPO
D
_HPD
eDP
eD
P_AUX#
AF4
P_AUX
eD
eDP
_TX#[0 ]
eDP
_TX#[1 ] _TX#[2 ]
eDP
AE7
eDP
_TX#[3 ]
eDP
_TX[0]
AA4
_TX[1]
eDP eDP
_TX[2]
AE6
eDP
_TX[3]
SANDY
SANDY
4
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
PEG PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
ICOMPI
ICOMPO
RCOMPO
_
RX#[0] RX#[1] RX#[2] RX#[3] RX#[4] RX#[5] RX#[6] RX#[7] RX#[8]
RX#[9] RX#[10] RX#[11] RX#[12] RX#[13] RX#[14] RX#[15]
RX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8]
RX[9] RX[10] RX[11] RX[12] RX[13] RX[14] RX[15]
TX#[0] TX#[1] TX#[2] TX#[3] TX#[4] TX#[5] TX#[6] TX#[7] TX#[8] TX#[9]
TX#[10] TX#[11] TX#[12] TX#[13] TX#[14] TX#[15]
TX[0]
_
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9] TX[10] TX[11] TX[12] TX[13] TX[14] TX[15]
G3 G1 G4
H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7
K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6
G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4
F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4
PEG_
PEG_
PEG_
DMI Intel(R) FDI DP
DMI Intel(R) FDI DP
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_ PEG_ PEG_
PEG_
COMP
3
2
U1I
U1I
BG
17
VSS[181]
21
BG
VSS[182]
BG
24
VSS[183]
BG
28
184]
VSS[
37
BG
VSS[185]
BG
41
VSS[186]
45
BG
VSS[187]
BG
49
VSS[188]
53
BG
VSS[189]
9
BG
VSS[190]
C2
9
VSS[191]
C3
5
VSS[192]
C4
0
VSS[193]
0
D1
VSS[194]
4
D1
VSS[195]
D1
8
VSS[196]
D2
2
VSS[197]
6
D2
VSS[198]
9
D2
VSS[199]
D3
5
VSS[200]
D4
VSS[201]
D4
0
VSS[202]
3
D4
VSS[203]
6
D4
VSS[204]
D5
0
VSS[205]
4
D5
VSS[206]
8
D5
VSS[207]
D6
VSS[208]
E2
5
VSS[209]
9
E2
VSS[210]
E3
VSS[211]
5
E3
VSS[212]
0
E4
VSS[213]
F13
VSS[214]
F15
VSS[215]
F19
VSS[216]
F29
VSS[217]
F35
VSS[218]
F40
VSS[219]
F55
VSS[220]
G4
8
VSS[221]
1
G5
VSS[222]
G6
VSS[223]
1
G6
VSS[224]
H1
0
VSS[225]
H1
4
VSS[226]
H1
7
VSS[227]
1
H2
VSS[228]
H4
VSS[229]
H5
3
VSS[230]
8
H5
VSS[231]
J1
VSS[232]
J49
VSS[233]
J55
VSS[234]
1
K1
VSS[
235]
1
K2
VSS[236]
1
K5
VSS[237]
K8
VSS[238]
L16
VSS[239]
L20
VSS[240]
L22
VSS[241]
L26
VSS[242]
L30
VSS[243]
L34
VSS[244]
L38
VSS[245]
L43
VSS[246]
L48
VSS[247]
L61
VSS[248]
1
M1
VSS[249]
M1
5
VSS[250]
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
VSS
VSS
VSS[2 VSS[2 VSS[2 VSS[ VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[3 VSS[3
VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_
VSS_NCTF_
NCTF
NCTF
VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_
1
M4
51]
M58
52]
M6
53]
N1
2
54]
N17
55]
N21
56]
N25
57]
N28
58]
N33
59]
N36
60]
N40
61]
N43
62]
N47
63]
N48
64]
N51
65]
N52
66]
N56
67]
N61
68]
P14
69]
P16
70]
P18
71]
P21
72]
P58
73]
P59
74]
P9
75]
R17
76]
R20
77]
R4
78]
R46
79]
T1
80]
T47
81]
T50
82]
T51
83]
T52
84]
T53
85]
T55
86]
T56
87]
U13
88]
U8
89]
V20
90]
V61
91]
W13
92]
W15
93]
W18
94]
W21
95]
W46
96]
W8
97]
Y4
98]
Y47
99]
Y58
00]
Y59
01]
A5
1
A57
2
BC61
3
BD3
4
BD59
5
BE4
6
BE58
7
BG5
8
BG57
9
C3
10
C58
11
D59
12
E1
13
E61
14
WŽŵƉĞŶƐĂƚŝŽŶ
.05V_RUN_VTT
+1
12
RC1
RC1
~D
~D
24.9_0402_1%
24.9_0402_1%
MP
EDP_CO
A A
ĞWͺKDW/KĂŶĚ/KDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƐŚŽƌƚĞĚŶĞĂƌďĂůůƐĂŶĚ ƌŽƵƚĞĚǁŝƚŚƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞфϮϱŵŽŚŵƐ
5
4
W'ŽŵƉĞŶƐĂƚŝŽŶ
+1
.05V_RUN_VTT
12
RC2
RC2
24.9_0402_1%
24.9_0402_1%
~D
~D
PEG_
COMP
W'ͺ/KDW/ĂŶĚZKDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƐŚŽƌƚĞĚĂŶĚƌŽƵƚĞĚ ǁŝƚŚͲŵĂdžůĞŶŐƚŚсϱϬϬŵŝůƐͲƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞсϰϯŵŽŚŵƐ W'ͺ/KDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƌŽƵƚĞĚǁŝƚŚͲŵĂdžůĞŶŐƚŚсϱϬϬŵŝůƐ ͲƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞсϭϰϱŵŽŚŵƐ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (1/6)
ndy Bridge (1/6)
ndy Bridge (1/6)
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
664W edn
664W edn
664W edn
of
of
1
of
5
+1
OK_AND
F49
C57
C49
A48
C45
D45
C48
B46
BE45
D44
12
2
G
G
U1B
U1B
PROC
PROC
CATE
PECI
PROCHO
THERMT
SYNC
PM_
UNCOREPW
SM_
DRAMPWROK
RESET#
75_0402_1%
75_0402_1%
RC4
RC4
~
~ D
D
1 2
RC10
RC10
43_0402_5%
43_0402_5%
.5V_CPU_VDDQ
RC64
RC64
39_0402_5%
39_0402_5%
1 2 13
D
D
QC1
QC1
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
S
S
_SELECT#
_DETECT#
RR#
T#
RIP#
RGOOD
PCH_PL
~D
~D
&ŽůůŽǁ'ZĞǀϬϳϭ^DͺZDWtZK<ƚŽƉŽůŽŐLJ
D D
+3
.3V_ALW_PCH
.05V_RUN_VTT
+1
1 2
RC
1 2
RC
1 2
RC
RC
C C
H_PRO
HERMTRIP#22
H_T
B B
H_CPUPW
RUNPWR
1 2
18 200_0402_5%~D
18 200_0402_5%~D
RC
RC
_
DRAM_PWRGD16
PM
126 56_0402_5%~D@RC126 56_0402_5%~D@
128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@
44 62_0402_5%~D
44 62_0402_5%~D
CHOT#43,53,55
RGD18
H_T
H_CAT
H_PRO
H_PM
ƵĨĨĞƌĞĚƌĞƐĞƚƚŽWh
A A
PCH_PL
TRST#14,17
5
+3
.3V_ALW_PCH
5
OK42,43
HERMTRIP#
CPU_DET
ƉůĂĐĞZϭϮϵŶĞĂƌWh
RC
RC
1
B
2
A
3
N_CPU1.5VS3#11,45
RUN_O
ERR#
CHOT#
EDS 1.0 SNB_IVB# -> PROC_SELECT#
ECT#42
H_CAT
H_PECI18
H_PRO
1 2
RC
RC
57 56_0402_5%~D
57 56_0402_5%~D
ůŽƐĞƚŽhϭ
RC
RC
129 0_0402_5%~D
129 0_0402_5%~D
_SYNC16
1 2
25 0_0402_5%~D
25 0_0402_5%~D
+3
1
2
H_
1 2
H_PM
VC
CPWRGOOD _0_R
DRAM_PWRGD_CPU
PM_
TRST#_R
PCH_PL
.3V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC14
CC14
0
0
2
5
P
NC
PCH_PL
4
Y
A
G
UC1
UC1
3
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
CC
CC
156
156
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
P
RUNPWR
4
O
G
UC2
UC2
C1G09GW_TSSOP5~D
C1G09GW_TSSOP5~D
74AH
74AH
ERR#
CHOT#_R
HERMTRIP#_R
T
_SYNC
+1
TRST#_BUF
.05V_RUN_VTT
4
200_0402_5%
200_0402_5%
12
RC12
RC12
~D
~D
1 2
RC
RC
28 130_0402_5%~D
28 130_0402_5%~D
~D
~D
SANDY
SANDY
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
TRST#_R
0_0402_5%
0_0402_5%
12
@
@
RC11
RC11
~D
~D
4
DRAM_PWRGD_CPU
PM_
DP
LL_REF_CLK
LL_REF_CLK#
DP
BC
DRAMRST#
SM_
SM_ SM_ SM_
BCLK
BCLK
LK_ITP
BC
LK_ITP#
RCOMP[0] RCOMP[1] RCOMP[2]
PRDY# PREQ#
TCK TMS
TRST#
TDO
DBR#
BP
M#[0] M#[1]
BP BP
M#[2] M#[3]
BP BP
M#[4] M#[5]
BP BP
M#[6]
BP
M#[7]
#
TDI
MISC THERMAL
MISC THERMAL
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
ǀŽŝĚƐƚƵďŝŶƚŚĞWtZ'ƉĂƚŚǁŚŝůĞƉůĂĐŝŶŐƌĞƐŝƐƚŽƌƐZϮϱΘZϭϯϬ
CPU_DM
J3 H2
AG3 AG1
N59 N58
AT30
BF44 BE43 BG43
N5 N5
L56 L55 J58
M6 L59
K58
G58 E55 E59 G55 G59 H60 J59 J61
VC
I I#
CPU_DM
CPU_DPL
L
CPU_DPL
L#
XDP_ITP
CLK_ CLK_
XDP_ITP#
DRAMRST#_CPU
DDR3_
SM_
RCOMP0 RCOMP1
SM_ SM_
RCOMP2
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XDP_PRDY
3
XDP_PREQ
5
XDP_TCL XDP_TM XDP_TRST#
XDP_TDI
0
XDP_TDO
XDP_DBRESET#
CPWRGOOD _0_R
3
+3
.3V_ALW_PCH
12
RC
124
@RC124
@
1K_0402_5%~D
1K_0402_5%~D
PWROK_XDP
SYS_
+1
.05V_RUN_VTT
1
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CC65
CC65
2
WůĂĐĞŶĞĂƌ:yWϭ
H_CPUPW
RGD
_PWRBTN#_R14,16
SIO
09
CFG
PWROK16,42
SYS_
XDP#17
PLTRST_
dŚĞƌĞƐŝƐƚŽƌĨŽƌ,KK<ϮƐŚŽƵůĚďĞƉůĂĐĞĚ ƐƵĐŚƚŚĂƚƚŚĞƐƚƵďŝƐǀĞƌLJƐŵĂůůŽŶ&'ϬŶĞƚ
1 2
13 0_0402_5%~D
13 0_0402_5%~D
RC
RC
1 2
RC
RC
15 0_0402_5%~D
15 0_0402_5%~D
1 2
16 0_0402_5%~D
16 0_0402_5%~D
RC
RC
1 2
RC
RC
17 0_0402_5%~D
17 0_0402_5%~D
DĂdžϱϬϬŵŝůƐ
#
#
K
S
_R
_R
_R
RC
RC
T128 P
T128 P T131 P
T131 P T129 P
T129 P T130 P
T130 P T125 P
T125 P T126 PAD~D@ T126 PAD~D@ T107 P
T107 P T127 PAD~D@ T127 PAD~D@
12
130
130
RC
RC 10K_0402_5%~D
10K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
26 0_0402_5%~D
26 0_0402_5%~D
AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
3
CPU_DMI 15
CLK_ CLK_
CPU_DMI# 15
CLK_
CPU_DPLL 15 CPU_DPLL# 15
CLK_
4.
4. 99K_0402_1%~D
99K_0402_1%~D
DDR_HVREF
DDR_HVREF
XDP_DBRESET#
RC50
RC50
12
_RST_PCH15
_RST_GATE43
XDP_DBRESET#
RCOMP2
SM_ SM_RCOMP1 SM_
RCOMP0
1 2
RC
48 0_0402_5%~D@RC48 0_0402_5%~D@
S
S
G
G
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
CC
CC
1
177
177
2
RC
RC
RC
D
D
13
QC2
QC2
SS138W-7-F_SOT323-3~D
SS138W-7-F_SOT323-3~D
B
B
46 0_0402_5%~D
46 0_0402_5%~D
47 0_0402_5%~D@RC47 0_0402_5%~D@
1 2
1 2
14,16
XDP_TDO
140_0402_1%
140_0402_1%
12
~D
~D
RC
RC
5 1K_0402_5%~D
5 1K_0402_5%~D 6 0_0402_5%~D
6 0_0402_5%~D
RC
RC RC
RC
7 1K_0402_5%~D
7 1K_0402_5%~D 9 0_0402_5%~D@RC9 0_0402_5%~D@
RC
8 1K_0402_5%~D
8 1K_0402_5%~D
RC
RC
DDR_HVREF
_R
1 2
23 0_0402_5%~D
23 0_0402_5%~D
RC
RC
_R
1 2
RC
RC
24 0_0402_5%~D
24 0_0402_5%~D
25.
25. 5_0402_1%~D
5_0402_1%~D
12
RC43
RC43
RC42
RC42
2
1 2 1 2 1 2 1 2
1 2
DDR3_
DRAMRST# 12
_RST
200_0402_1%
200_0402_1%
12
RC45
RC45
~D
~D
1
+1
.05V_RUN_VTT
#
CLK_ CLK_
CLK_
CLK_
XDP XDP#
XDP_ITP
XDP_ITP#
XDP_PREQ XDP_PRDY
#
H_CPUPW
RGD_XDP
PWRBTN#_XDP
CFD_ XDP_HO
OK2
PWROK_XDP
SYS_
XDP
CLK_ CLK_
XDP#
XDP_RST#
_R
XDP_DBRESET#
XDP_TDO XDP_TRST# XDP_TDI
S
XDP_TM
XDP_TCL
K
RH
109 0_0402_5%~D@RH109 0_0402_5%~D@
108 0_0402_5%~D@RH108 0_0402_5%~D@
RH
1 2
1 2
RH10
RH10
12
RH10
RH10
12
1
OBSFN_
2
OBSFN_
3
D
GN
4
OBSDATA_
5
OBSDATA_
6
GND
7
OBSDATA_
8
OBSDATA_
9
GND
10
HOOK
0
11
HOOK
1
12
HOOK
2
13
3
HOOK
14
4
HOOK
15
HOOK
5
16
VCCOBS_
17
6
HOOK
18
7
HOOK
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
MOLEX_52435-2671
70_0402_5%~D
70_0402_5%~D 60_0402_5%~D
60_0402_5%~D
WhWĨŽƌ:d'ƐŝŐŶĂůƐ
XDP_TDIXDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_TM
XDP_TDI
XDP_PREQ
XDP_TDO
XDP_TCL
XDP_TRST#
RC
RC
S
RC27 51_0402_1%~DRC27 51_0402_1%~D
_R
RC29 51_0402_1%~DRC29 51_0402_1%~D
#
RC
RC
RC
K
RC40
RC40
RC41
RC41
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (2/6)
ndy Bridge (2/6)
ndy Bridge (2/6)
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
12
19 1K_0402_5%~D
19 1K_0402_5%~D
32 51_0402_1%~D@RC32 51_0402_1%~D@
35 51_0402_1%~D
35 51_0402_1%~D
12
12
12
12
12
51_0402_1%
51_0402_1%
12
51_0402_1%
51_0402_1%
+1
/PROPRIETARY
-6611P
-6611P
-6611P
1
P1
@
P1
@
JXD
JXD
A0 A1
A[0] A[1]
A[2] A[3]
AB
27 28
GND
CLK_ CLK_
.3V_RUN
+3
.05V_RUN_VTT
~D
~D
~D
~D
764W edn
764W edn
764W edn
of
of
of
CPU_ITP 15 CPU_ITP# 15
5
U1C
D D
C C
B B
DDR_A_
D[0..63]12
BS012
DDR_A_ DDR_A_
BS112
DDR_A_
BS212
DDR_A_
CAS#12 RAS#12
DDR_A_ DDR_A_WE#12
DDR_A_ DDR_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_
A_
A_
BS0 BS1 BS2
CAS# RAS# WE#
U1C
D0
AG6
SA_DQ
AJ10
AT13
AY13
AY17
AT48 AY48
AY53
AT54
BF36
AT41
AJ6
AL6
AJ8 AL8 AL7
AP6 AU6 AV9 AR6 AP8
BC7 BB7
BA7 BA9 BB9
9
[0] [1]
SA_DQ
[2]
SA_DQ SA_DQ
[3]
SA_DQ
[4]
SA_DQ
[5] [6]
SA_DQ
[7]
SA_DQ SA_DQ
[8]
SA_DQ
[9] [10]
SA_DQ
[11]
SA_DQ SA_DQ
[12] [13]
SA_DQ SA_DQ
[14] [15]
SA_DQ
[16]
SA_DQ SA_DQ
[17] [18]
SA_DQ
[19]
SA_DQ
[20]
SA_DQ SA_DQ
[21] [22]
SA_DQ
[23]
SA_DQ
[24]
SA_DQ
[25]
SA_DQ SA_DQ
[26] [27]
SA_DQ SA_DQ
[28] [29]
SA_DQ SA_DQ
[30] [31]
SA_DQ
[32]
SA_DQ SA_DQ
[33] [34]
SA_DQ SA_DQ
[35] [36]
SA_DQ SA_DQ
[37]
SA_DQ
[38]
SA_DQ
[39] [40]
SA_DQ
[41]
SA_DQ SA_DQ
[42] [43]
SA_DQ SA_DQ
[44] [45]
SA_DQ SA_DQ
[46]
SA_
[47]
DQ
[48]
SA_DQ
[49]
SA_DQ
[50]
SA_DQ SA_DQ
[51] [52]
SA_DQ SA_DQ
[53] [54]
SA_DQ SA_DQ
[55]
SA_DQ
[56] [57]
SA_DQ SA_DQ
[58] [59]
SA_DQ SA_DQ
[60] [61]
SA_DQ SA_DQ
[62]
SA_DQ
[63]
0]
SA_BS[ SA_BS[
1] 2]
SA_BS[
SA_CAS# SA_RAS# SA_W
E#
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
SANDY
SANDY
D1 D2
AP11
D3 D4 D5 D6 D7 D8
AR11
D9 D10 D11 D12 D13 D14 D15
AU13
D16 D17 D18
BA13
D19
BB11
D20 D21 D22 D23 D24
AV14
D25
AR14
D26 D27
AR19
D28
BA14
D29
AU14
D30
BB14
D31
BB17
D32
BA45
D33
AR43
D34
AW48
D35
BC48
D36
BC45
D37
AR45
D38 D39 D40
BA49
D41
AV49
D42
BB51
D43 D44
BB49
D45
AU49
D46
BA53
D47
BB55
D48
BA55
D49
AV56
D50
AP50
D51
AP53
D52
AV54
D53 D54
AP56
D55
AP52
D56
AN57
D57
AN53
D58
AG56
D59
AG53
D60
AN55
D61
AN52
D62
AG55
D63
AK56
BD37
BA28
BE3
BD39
4
_
CLK_DDR0
M
AU36
K[0]
SA_CL
K#[0]
SA_CL
SA_CKE[
0]
SA_CL
K[1]
K#[1]
SA_CL
1]
SA_CKE[
SA_CS#
[0] [1]
SA_CS#
DT[0]
SA_O
DT[1]
SA_O
S#[0]
SA_DQ
S#[1]
SA_DQ SA_DQ
S#[2] S#[3]
SA_DQ SA_DQ
S#[4] S#[5]
SA_DQ SA_DQ
S#[6]
SA_DQ
S#[7]
S[0]
SA_DQ SA_DQ
S[1]
SA_
S[2]
DQ
S[3]
SA_DQ
S[4]
SA_DQ
S[5]
SA_DQ SA_DQ
S[6] S[7]
SA_DQ
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
A[0]
SA_M SA_M
A[1]
SA_M
A[2]
SA_M
A[3]
SA_M
A[4] A[5]
SA_M SA_M
A[6] A[7]
SA_M SA_M
A[8] A[9]
SA_M
SA_M
A[10] A[11]
SA_M SA_M
A[12]
SA_M
A[13] SA_MA[14] SA_M
A[15]
AV36 AY26
AT40 AU40 BB26
BB40 BC41
AY40 BA41
AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55
AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54
BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26
CLK_DDR#0
M_ DDR_CKE0
CLK_DDR1
M_ M_
CLK_DDR#1
DDR_CKE1
DDR_CS0 DDR_CS1
DT0
M_O
DT1
M_O
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_
A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
_DIMMA
_DIMMA
_DIMMA# _DIMMA#
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15
CLK_DDR0 12
M_ M_
CLK_DDR#0 12
CKE0
DDR_
M_
CLK_DDR1 12 CLK_DDR#1 12
M_ DDR_CKE1
DDR_CS0 DDR_CS1
DT0 12
M_O M_O
DT1 12
DDR_A_
DDR_A_
DDR_A_
_DIMMA 12
_DIMMA 12
_DIMMA# 12 _DIMMA# 12
DQS#[0..7] 12
DQS[0..7] 12
MA[0..15] 12
3
DDR_B_
D[0..63]13
DDR_B_
BS013 BS113
DDR_B_ DDR_B_
BS213
CAS#13
DDR_B_ DDR_B_
RAS#13 WE#13
DDR_B_
DDR_B_ DDR_B_ DDR_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_
D0
AL4
D1
AL1
B_
D2
AN3
D3
AR4
D4
AK4
D5
AK3
D6
AN4
D7
AR1
D8
AU4
D9
AT2
D10
AV4
D11
BA4
D12
AU3
D13
AR3
D14
AY2
D15
BA3
D16
BE9
D17
BD9
D18
BD13
D19
BF12
D20
BF8
D21
BD10
D22
BD14
D23
BE13
D24
BF16
D25
BE17
D26
BE18
D27
BE21
D28
BE14
D29
BG14
D30
BG18
D31
BF19
D32
BD50
D33
BF48
D34
BD53
D35
BF52
D36
BD49
D37
BE49
D38
BD54
D39
BE53
D40
BF56
D41
BE57
D42
BC59
D43
AY60
D44
BE54
D45
BG54
D46
BA58
D47
AW59
D48
AW58
D49
AU58
D50
B_
AN61
D51
AN59
D52
AU59
D53
AU61
D54
AN58
D55
AR58
D56
AK58
D57
AL58
D58
AG58
D59
AG59
D60
AM60
D61
AL59
D62
AF61
D63
AH60
BS0
BG39
BS1
BD42
BS2
AT22
CAS#
AV4
3
RAS#
BF4
0
WE#
BD45
2
D
D
U1
U1
[0]
SB_DQ SB_DQ
[1] [2]
SB_DQ
[3]
SB_DQ SB_DQ
[4]
SB_DQ
[5]
SB_DQ
[6] [7]
SB_DQ
[8]
SB_DQ SB_DQ
[9]
SB_DQ
[10] [11]
SB_DQ
[12]
SB_DQ SB_DQ
[13] [14]
SB_DQ SB_DQ
[15] [16]
SB_DQ
[17]
SB_DQ SB_DQ
[18] [19]
SB_DQ
[20]
SB_DQ
[21]
SB_DQ SB_DQ
[22] [23]
SB_DQ
[24]
SB_DQ
[25]
SB_DQ
[26]
SB_DQ SB_DQ
[27] [28]
SB_DQ SB_DQ
[29] [30]
SB_DQ SB_DQ
[31] [32]
SB_DQ
[33]
SB_DQ SB_DQ
[34] [35]
SB_DQ SB_DQ
[36] [37]
SB_DQ SB_DQ
[38]
SB_DQ
[39]
SB_DQ
[40] [41]
SB_DQ
[42]
SB_DQ SB_DQ
[43] [44]
SB_DQ SB_DQ
[45] [46]
SB_DQ SB_DQ
[47]
SB_
[48]
DQ
[49]
SB_DQ
[50]
SB_DQ
[51]
SB_DQ SB_DQ
[52] [53]
SB_DQ SB_DQ
[54] [55]
SB_DQ SB_DQ
[56]
SB_DQ
[57] [58]
SB_DQ SB_DQ
[59] [60]
SB_DQ SB_DQ
[61] [62]
SB_DQ SB_DQ
[63]
SB_BS[
0] 1]
SB_BS[ SB_BS[
2]
SB_CAS# SB_RAS# SB_WE#
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
M_
CLK_DDR2
BA34
SB_CL
K[0]
K#[0]
SB_CL
SB_CKE[
SB_CL
K[1]
SB_CL
K#[1]
SB_CKE[
_CS#[0]
SB SB
_CS#[1]
DT[0]
SB_O
DT[1]
SB_O
SB_DQ
S#[0] S#[1]
SB_DQ
S#[2]
SB_DQ SB_DQ
S#[3] S#[4]
SB_DQ SB_DQ
S#[5] S#[6]
SB_DQ SB_DQ
S#[7]
S[0]
SB_DQ SB_DQ
S[1]
SB_
S[2]
DQ
S[3]
SB_DQ
S[4]
SB_DQ
S[5]
SB_DQ SB_DQ
S[6] S[7]
SB_DQ
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_M
A[0] A[1]
SB_M SB_M
A[2]
SB_M
A[3]
SB_M
A[4]
SB_M
A[5] A[6]
SB_M SB_M
A[7] A[8]
SB_M SB_M
A[9]
A[10]
SB_M SB_M
A[11] A[12]
SB_M SB_M
A[13]
SB_M
A[14]
SB_MA[15]
_
CLK_DDR#2
M
AY34 AR22
0]
BA36 BB36 BF27
1]
BE41 BE47
AT43 BG47
AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59
AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61
BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22
DDR_CKE2
M_
CLK_DDR3 CLK_DDR#3
M_ DDR_CKE3
DDR_CS2 DDR_CS3
DT2
M_O
DT3
M_O
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_
B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
_DIMMB
_DIMMB
_DIMMB# _DIMMB#
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15
1
_
CLK_DDR2 13
M
CLK_DDR#2 13
M_ DDR_CKE2
CLK_DDR3 13
M_ M_
CLK_DDR#3 13
DDR_CKE3
DDR_CS2 DDR_CS3
M_O
DT2 13 DT3 13
M_O
DDR_B_
DDR_B_
DDR_B_
_DIMMB 13
_DIMMB 13
_DIMMB# 13 _DIMMB# 13
DQS#[0..7] 13
DQS[0..7] 13
MA[0..15] 13
A A
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (3/6)
ndy Bridge (3/6)
ndy Bridge (3/6)
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
864W edn
864W edn
864W edn
of
of
1
of
5
4
3
2
1
&'^ƚƌĂƉƐĨŽƌWƌŽĐĞƐƐŽƌ
CFG
2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
U1E
U1E
CFG
07
CFG
T11
T11
PAD~D@
PAD~D@
T13
T13
PAD~D@
PAD~D@
T17
T17
PAD~D@
PAD~D@ PAD~D@
PAD~D@
T18
T18 T15
T15
PAD~D@
+V
CC_CORE
H_CPU_
H_CPU_
H_CPU_
H_CPU_
+D
12
+D
12
RSVD3
RSVD1
RSVD2
RSVD4
IMM0_1_VREF_CPU
IMM0_1_CA_CPU
EDS 1.0 RSVD_12 -> VCC_DIE_SENSE
1 2
120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
C C
B B
CC_GFXCORE
+V
RC
RC
RC
RC
RC
RC
1 2
122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
1 2
121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
1 2
123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
96 1K_0402_5%~D@RC96 1K_0402_5%~D@
97 1K_0402_5%~D@RC97 1K_0402_5%~D@
T19
T19 T9 PAD~
T9 PAD~ T10
T10 T12
T12 T14
T14 T21
T21 T20
T20
MM0_1_VREF_CPU
+DI
+DI
MM0_1_CA_CPU
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
T22PAD~D @T22PAD~D @
T25PAD~D @T25PAD~D @ T26PAD~D @T26PAD~D @ T27PAD~D @T27PAD~D @ T28PAD~D @T28PAD~D @ T29PAD~D @T29PAD~D @ T30PAD~D @T30PAD~D @ T31PAD~D @T31PAD~D @ T32PAD~D @T32PAD~D @ T33PAD~D @T33PAD~D @ T34PAD~D @T34PAD~D @ T35PAD~D @T35PAD~D @ T36PAD~D @T36PAD~D @ T37PAD~D @T37PAD~D @ T38PAD~D @T38PAD~D @ T39PAD~D @T39PAD~D @ T40PAD~D @T40PAD~D @ T41PAD~D @T41PAD~D @ T42PAD~D @T42PAD~D @ T43PAD~D @T43PAD~D @ T44PAD~D @T44PAD~D @
D@
D@
H_CPU_ H_CPU_
H_CPU_ H_CPU_
0
CFG
1 2
CFG
3
CFG CFG
4 5
CFG CFG
6 7
CFG CFG
8
CFG
9 10
CFG
11
CFG
12
CFG CFG
13 14
CFG CFG
15 16
CFG CFG
17
RSVD3 RSVD4
RSVD1 RSVD2
CC_DIESENSE
TP_V
+D
IMM0_1_VREF_CPU IMM0_1_CA_CPU
+D
PU_RSVD8
TP_C TP_
PU_RSVD9
C
PU_RSVD10
TP_C TP_C
PU_RSVD11 PU_RSVD12
TP_C
PU_RSVD13
TP_C
PU_RSVD14
TP_C TP_C
PU_RSVD15
TP_C
PU_RSVD16 PU_RSVD17
TP_C
PU_RSVD18
TP_C
PU_RSVD19
TP_C TP_C
PU_RSVD20 PU_RSVD21
TP_C
PU_RSVD22
TP_C TP_C
PU_RSVD23
TP_C
PU_RSVD24
TP_C
PU_RSVD25 PU_RSVD26
TP_C
PU_RSVD27
TP_C
BA19 AV19
AT2 BB2 BB1
AY BA2
AY AU1 AU2 BD2 BD2 BD2 BD2 BG BE2 BG BE2
BF2 BE2
B50
[0]
CFG
C51
CFG
[1]
B54
[2]
CFG
D53
[3]
CFG
A51
CFG
[4]
C53
[5]
CFG
C55
[6]
CFG
H49
[7]
CFG
A55
CFG
[8]
H51
[9]
CFG
K49
[10]
CFG
K53
[11]
CFG
F53
[12]
CFG
G53
CFG
[13]
L51
[14]
CFG
F51
CFG
[15]
D52
[16]
CFG
L53
CFG
[17]
H43
VCC_VAL
1 1 9
21
2
22
9 1 1 2 5 6
22
2
26
6 3 4
VSS_VAL
VAXG_ VSSAXG_
VCC_DI
RSVD6 RSVD7
RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
_SENSE
_SENSE
VAL_SENSE
VAL_SENSE
E_SENSE
RESERVED
RESERVED
K43
H45 K45
F48
H48 K48
DC_T DC_ DC_T DC_T
_TEST_A58
DC DC
_TEST_A59
_TEST_C59
DC DC
_TEST_A61
_TEST_C61
DC DC
_TEST_D61
DC_T
EST_BD61 DC_TEST_ DC_TEST_
EST_BG61
DC_T DC_T
EST_BG59
EST_BG58
DC_T
DC_T DC_T DC_TEST_ DC_T DC_TEST_ DC_T
RSVD28 RSVD29
RSVD30 RSVD31 RSVD32 RSVD33
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38
RSVD39 RSVD40
RSVD41 RSVD42 RSVD43 RSVD44
RSVD45
EST_A4 EST_C4
T
EST_D3 EST_D1
BE61 BE59
EST_BG4 EST_BG3
EST_BG1
EST_BD1
TP_C
PU_RSVD28
BE7
TP_C
PU_RSVD29
BG
7
TP_C
PU_RSVD30
N4
2
PU_RSVD31
TP_C
L42
TP_C
PU_RSVD32
L45
PU_RSVD33
TP_C
L47
PU_RSVD34
TP_C
3
M1
PU_RSVD35
TP_C
4
M1
PU_RSVD36
TP_C
4
U1
TP_C
PU_RSVD37
W1
4
PU_RSVD38
TP_C
3
P1
TP_C
PU_RSVD39
AT4
9
TP_C
PU_RSVD40
4
K2
PU_RSVD41
TP_C
AH2
TP_C
PU_RSVD42
AG
13
PU_RSVD43
TP_C
14
AM
TP_C
PU_RSVD44
AM
15
TP_C
PU_RSVD45
0
N5
TP
_DC_TEST_A4
A4 C4
_TEST_C4_D3
DC
D3
T
_DC_TEST_D1
P
D1
C_TEST_A58
TP_D
A58 A59
_TEST_A59_C59
DC
C59 A61
_TEST_A61_C61
DC
C61
TP_D
C_TEST_D61
D61
TP
_DC_TEST_BD61
BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3
BE3
BG1 BE1
BE1
BD1
BE59_BE61
DC_TEST_
DC
_TEST_BG59_BG61
_DC_TEST_BG58
TP
_DC_TEST_BG4
TP
DC_TEST_
BE3_BG3
BE1_BG1
DC_TEST_
_DC_TEST_BD1
TP
T45
T45 T46
T46
T47
T47 T48
T48 T49
T49 T50
T50
T51
T51 T52
T52 T53
T53 T55
T55 T109 P
T109 P
T110 P
T110 P T111 P
T111 P
T112 P
T112 P T113 P
T113 P T114 P
T114 P T115 P
T115 P
T116 P
T116 P
T117 P
T117 P
T118 P
T118 P T119 P
T119 P
T120 P
T120 P T121 P
T121 P
T122 P
T122 P T123 P
T123 P
T124 P
T124 P
PAD~D@
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
definition matches socket pin map definition 0:Lane Reversed
CFG
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
CFG
CFG
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
@
@
1K
1K
12
RC51
RC51
_0402_1%~D
_0402_1%~D
4
1K
1K
12
@
@
_0402_1%~D
_0402_1%~D
RC52
RC52
6
5
1K_0402_1%~D
1K_0402_1%~D
1K
1K
12
12
@RC54
@
@
@
_0402_1%~D
_0402_1%~D
RC54
RC53
RC53
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
SANDY
SANDY
CFG
7
@
@
1K
1K
12
RC56
RC56
_0402_1%~D
_0402_1%~D
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Sa
Sa
Sa
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
ndy Bridge (4/6)
ndy Bridge (4/6)
ndy Bridge (4/6)
964We
964We
964We
1
of
of
of
5
CC_CORE
+V
D D
C C
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC67
CC67
CC75
CC75
1
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC94
CC94
CC
CC
1
104
104
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
122
122
124
124
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
148
148
151
151
2
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC
CC
CC76
CC76
1
1
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
1
123
123
2
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC95
CC95
CC96
CC96
1
1
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
127
127
125
125
2
@
@
CC
CC
1
152
152
2
@
@
2.
2.
2.
2.
2.
2.
2.
2.
2.
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC87
CC87
CC77
CC77
1
2
2.
2.
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC97
CC97
CC
CC
1
100
100
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
1
143
143
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
154
154
157
157
2
2U_0402_6.3V6M~D
CC71
CC71
CC72
CC72
1
1
2
2
2.
2.
2.
2.
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC98
CC98
CC99
CC99
1
1
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
C
C
1
C
C 201
201
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
1
155
155
160
160
2
2
@
@
2.
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC8
CC8
CC73
CC73
1
1
1
8
8
2
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
C
C
CC
CC
1
1
C
C 121
121
198
198
2
2
@
@
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
C
C
1
1
C
C
158
158
159
159
2
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
111
111
110
B B
110
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
115
115
116
116
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
C
C C
C 112
112
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
C
C C
C 117
117
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC 113
113
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC 118
118
2
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
114
114
181
181
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
119
119
186
186
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
C
C C
C
183
183
182
182
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
C
C
CC
CC
C
C 187
187
189
189
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
1
CC
CC
CC
CC
185
185
184
184
2
1
CC
CC 188
188
2
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC 190
190
2
2
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1
+
+
9
9
CC12
CC12 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
A A
1
+
+
CC13
CC13 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
0
0
1
+
+
131
131
CC
CC 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
1
+
+
CC13
CC13 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
2
2
4
U1F
CC_CORE
+V
U1F
53A
A26
]
VCC[1
A29
VCC[2
]
A31
3
]
VCC[
A34
]
VCC[4
A35
VCC[5
]
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC74
CC74
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC
CC
CC
194
194
192
192
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC19
CC19
1
CC
CC
7
7
193
193
2
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
1
1
106
106
191
191
2
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC19
CC19
1
5
5
2
A38
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC 196
196
]
VCC[6
A39
VCC[7
]
A42
]
VCC[8
C26
]
VCC[9
C27
VCC[1
0]
C32
VCC[1
1]
C34
VCC[1
2]
C37
3]
VCC[1
C39
4]
VCC[1
C42
VCC[1
5]
D27
VCC[1
6]
D32
7]
VCC[1
D34
8]
VCC[1
D37
VCC[1
9]
D39
0]
VCC[2
D42
VCC[2
1]
E26
2]
VCC[2
E28
3]
VCC[2
E32
VCC[2
4]
E34
5]
VCC[2
E37
6]
VCC[2
E38
7]
VCC[2
F25
VCC[2
8]
F26
9]
VCC[2
F28
0]
VCC[3
F32
1]
VCC[3
F34
2]
VCC[3
F37
VCC[3
3]
F38
4]
VCC[3
F42
VCC[3
5]
G42
6]
VCC[3
H25
VCC[3
7]
H26
8]
VCC[3
H28
9]
VCC[3
H29
VCC[4
0]
H32
1]
VCC[4
H34
VCC[4
2]
H35
3]
VCC[4
H37
VCC[4
4]
H38
VCC[4
5]
H40
VCC[4
6]
J25
7]
VCC[4
J26
8]
VCC[4
J28
VCC[4
9]
J29
0]
VCC[5
J32
VCC[5
1]
J34
2]
VCC[5
J35
VCC[5
3]
J37
VCC[
4]
5
J38
5]
VCC[5
J40
6]
VCC[5
J42
7]
VCC[5
K26
VCC[5
8]
K27
9]
VCC[5
K29
VCC[6
0]
K32
1]
VCC[6
K34
VCC[6
2]
K35
VCC[6
3]
K37
4]
VCC[6
K39
VCC[6
6]
K42
7]
VCC[6
L25
VCC[6
8]
L28
9]
VCC[6
L33
VCC[7
0]
L36
VCC[7
1]
L40
VCC[7
2]
N26
VCC[7
3]
N30
4]
VCC[7
N34
VCC[7
5]
N38
6]
VCC[7
CORE SUPPLY
CORE SUPPLY
3
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO
PEG AND DDRSENSE LINES SVID QUIET RAILS
PEG AND DDRSENSE LINES SVID QUIET RAILS
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
POWER
POWER
VCCIO
VCCPQE VCCPQE
VIDALERT#
VCC_SENSE VSS_SENSE
VCCIO_SENSE
VSS_SENSE_
VCCIO VCCIO VCCIO VCCIO VCCIO
O
VCCI VCCIO VCCIO
VCCIO VCCIO
_SEL
VIDSCL VIDSOUT
VCCIO
2
8.5A
AF46
[1]
AG48
[3]
AG50
[4]
AG51
[5]
AJ17
[6]
AJ21
[7]
AJ25
[8]
AJ43
[9]
AJ47
[10]
AK50
[11]
AK51
[12]
AL14
[13]
AL15
[14]
AL16
[15]
AL20
[16]
AL22
[17]
AL26
[18]
AL45
[19]
AL48
[20]
AM16
[21]
AM17
[22]
AM21
[23]
AM43
[24]
AM47
[25]
AN20
[26]
AN42
[27]
AN45
[28]
AN48
[29]
AA14
[30]
AA15
[31]
AB17
[32]
AB20
[33]
AC13
[34]
AD16
[35]
AD18
[36]
AD21
[37]
AE14
[38]
AE15
[39]
AF16
[40]
AF18
[41]
AF20
[42]
AG15
[43]
AG16
[44]
AG17
[45]
AG20
[46]
AG21
[47]
AJ14
[48]
AJ15
[49]
+1
.05V_RUN_VTT_F
W16
50
W17
51
BC22
1
2
1
2
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC69
CC69
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC 243
243
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 244
244
0_0402_5%
0_0402_5%
1
2
1
2
1
2
RC65
RC65
CC79
CC79
CC238
CC238
CC245
CC245
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U
1U
1U
1U
1U
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
RC62
RC62
0_0402_5%
0_0402_5%
12
~D
~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC80
CC80
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC 233
233
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 246
246
12
~D
~D
.05V_RUN_VTT
+1
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC81
CC81
CC82
CC82
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
234
234
236
236
2
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC228
CC228
1
1
247
247
2
2
H_CPU_
.05V_RUN_VTT
+1
1U
1U
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
CC83
CC83
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
237
237
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
229
229
2
EŽƚĞWůĂĐĞƚŚĞWhƌĞƐŝƐƚŽƌƐĐůŽƐĞƚŽWh ZϭϱϱϱĐůŽƐĞƚŽWhϯϬϬͲϭϱϬϬŵŝůƐ
SVIDALRT#
+3
.3V_ALW_PCH
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC84
CC84
CC85
CC85
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC227
CC227
1
1
109
109
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
230
230
231
231
2
2
1 2
61 43_0402_5%~D
61 43_0402_5%~D
RC
RC
12
RC69
RC69 10K
10K
_0402_5%~D
_0402_5%~D
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC86
CC86
CC70
CC70
1
1
2
CC
CC
1
226
226
2
CC
CC
1
232
232
2
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC93
CC93
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
239
239
2
EŽƚĞWůĂĐĞƚŚĞWh ƌĞƐŝƐƚŽƌƐĐůŽƐĞƚŽWh ZϭϱϱϴĐůŽƐĞƚŽWhϯϬϬͲϭϱϬϬŵŝůƐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC23
CC23
5
5
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC78
CC78
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC
CC
+
+
107
107
2
Voltage Rail
VCC
AM25
[1]
AN22
[2]
A44 B43
K
C44
VCCSENSE_R
F43
VSSSENSE_R
3
G4
VTT_SENSE_
AN16
VSSIO
AN17
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC
CC 573
573
2
H_CPU_
SVIDALRT#
K
VIDSCL VIDSOUT
RC
RC RC
RC
R
RC
RC
132 0_0402_5%~D
132 0_0402_5%~D
_SENSE_R
1 2
RC133 0_0402_5%~DRC133 0_0402_5%~D
1 2
.05V_RUN_VTT
+1
12
VIDSCLK 53
WůĂĐĞZϲϲĂŶĚZϳϬŶĞĂƌWh
67 0_0402_5%~D
67 0_0402_5%~D
1 2
68 0_0402_5%~D
68 0_0402_5%~D
1 2
RC63
RC63 130_0402_1%
130_0402_1%
VTT_SENSE VTT_GN
D 52
~D
~D
+V
52
VIDSO
CC_CORE
12
12
UT 53
RC66
RC66 100_0402_1%~D
100_0402_1%~D
VCCSENSE 53
VSSSENSE 5
RC70
RC70 100_0402_1%~D
100_0402_1%~D
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM 1.5
Description
*
3
5A to Mem controller(+1.5V_CPU_VDDQ) 5-6A to 2 DIMMs/channel 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
1
.05V_RUN_VTT
+1
1U
1U
1U
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC90
CC90
1
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
RC60
RC60 75_0402_1%
75_0402_1%
CC91
CC91
1
2
Voltage
1U _0402_6.3V6K~D
_0402_6.3V6K~D
~D
~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC92
CC92
1
2
VI
DALERT_N 53
S0 Iccmax Current (A)
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC89
CC89
1
2
1
CC
CC
+
+
108
108
2
+1
.05V_RUN_VTT
12
CPU Power Rail Table
0.65-1.3
1.05
0.0-1.1
1.8
1.5
0.65-0.9
53
8.5
33
1.2
10
6
12-16
*
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
ndy Bridge (5/6)
ndy Bridge (5/6)
ndy Bridge (5/6)
10 64Wedn
10 64Wedn
10 64Wedn
1
of
of
of
5
D D
CC_GFXCORE
+V
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC13
CC13
CC13
CC13
1
1
1
8
8
7
7
2
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
285
285
284
284
2
C C
B B
A A
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
286
286
2
CC_SA
+V
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
1
4
4
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
C
1
1
288
288
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
1
2
2
2
1 2
RC
RC
137 0_0402_5%~D
137 0_0402_5%~D
C C
C 289
289
1
2
1
287
287
2
ϰϮϬZĞŵŽǀĞϮϲϱϭϳϯĚƵĞƚŽWŽǁĞƌĐŝƌĐƵŝƚĂůƌĞĂĚLJŚĂƐ WϮϬϭWϮϬϮ
CC26
CC26
1
3
3
2
RUN_O
5V_S3_GATE43
CPU1.
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC14
CC14
CC14
CC14
1
1
4
4
5
5
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
290
290
291
291
2
2
.8V_RUN
+1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
CC26
CC26
1
1
1
1
0
0
2
2
5
CC14
CC14
1
6
6
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC18
CC18
0
0
77 0_0402_5%~D@RC77 0_0402_5%~D@
RC
1 2
RC
RC
79 0_0402_5%~D
79 0_0402_5%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC14
CC14
1
C
C C
C 280
280
7
7
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
C
C
1
C
C
292
292
293
293
2
VCC_AXG
VSS_AXG_SENSE53
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC
CC 174
174
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC16
CC16
1
1
8
8
2
2
+G
ND_VCC_SA 56
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC1
CC1
6
6 9
9
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC
CC 281
281
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
1
296
296
2
2
_SENSE53
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CC
CC 175
175
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC17
CC17
1
1
0
0
2
2
1 2
N38,42,45,50
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC28
CC28
1
CC
CC
3
3
282
282
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
297
297
294
294
2
1.2A
330U_V_2.5MV~D
330U_V_2.5MV~D
CC
CC
+
+
176
176
6A
10U
10U
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CC17
CC17
1
CC
CC
+
+
172
172
2
4
+3
.3V_ALW2
12
RC74
RC74
_0402_5%~D
_0402_5%~D
100K
100K
RUN_O
61
QC4
QC4
A
A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
U1G
U1G
33A
AA46
VAXG[
AB47
VAXG[
AB50
VAXG[
AB51
VAXG[
AB52
VAXG[
AB53
VAXG[
AB55
VAXG[
AB56
VAXG[
AB58
VAXG[
AB59
VAXG[
AC61
VAXG[
AD47
VAXG[
AD48
VAXG[
AD50
VAXG[
AD51
VAXG[
AD52
VAXG[
AD53
VAXG[
AD55
VAXG[
AD56
VAXG[
AD58
VAXG[
AD59
VAXG[
AE46
VAXG[
N45
VAXG[
P47
VAXG[
P48
VAXG[
P50
VAXG[
P51
VAXG[
P52
VAXG[
P53
VAXG[
P55
VAXG[
P56
VAXG[
P61
VAXG[
T48
VAXG[
T58
VAXG[
T59
VAXG[
T61
VAXG[
U46
VAXG[
V47
VAXG[
V48
VAXG[
V50
VAXG
[
V51
VAXG[
V52
VAXG[
V53
VAXG[
V55
VAXG[
V56
VAXG[
V58
VAXG[
V59
VAXG[
W50
VAXG[
W51
VAXG[
W52
VAXG[
W53
VAXG[
W55
VAXG[
W56
VAXG[
W61
VAXG[
Y48
VAXG[
Y61
VAXG[
F45
VAXG_
G45
VSSAXG_
BB3
VCCPLL
BC1
VCCPLL
BC4
VCCPLL
L17
VCCSA[1
L21
VCCSA[2
N16
VCCSA[3
N20
VCCSA[4
N22
VCCSA[5
P17
VCCSA[6
P20
VCCSA[7]
R16
VCCSA[8
R18
VCCSA[9]
R21
VCCSA[1
U15
VCCSA[1
V16
VCCSA[1
V17
VCCSA[1
V18
VCCSA[1
V21
VCCSA[1
W20
VCCSA[16]
SANDY
SANDY
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
4
N_CPU1.5VS3#
1] 2] 3] 4] 5] 6] 7] 8] 9] 10] 11] 12] 13] 14] 15] 16] 17] 18] 19] 20] 21] 22] 23] 24] 25] 26] 27] 28] 29] 30] 31] 32] 33] 34] 35] 36] 37] 38] 39] 40] 41] 42] 43] 44] 45] 46] 47] 48] 49] 50] 51] 52] 53] 54] 55] 56]
SENSE
SENSE
[1] [2] [3]
] ] ] ] ] ]
]
0] 1] 2] 3] 4] 5]
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
LW
+15V_A
100K
100K
12
RC72
RC72
_0402_5%~D
_0402_5%~D
RUN_O
3
4
4
B
B
QC
QC DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
RUN_O
N_CPU1.5VS3# 7,45
VREF
SM_
VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[
VDDQ[
10] 11]
VDDQ[ VDDQ[
12] 13]
VDDQ[ VDDQ[
14] 15]
VDDQ[
16]
VDDQ[ VDDQ[
17] 18]
VDDQ[ VDDQ[
19] 20]
VDDQ[ VDDQ[
21]
VDDQ[
22]
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
POWER
POWER
VDDQ[ VDDQ[ VDDQ[ VDDQ[
VCCDQ[ VCCDQ[
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_
SENSE LINES
SENSE LINES
VCCSA_SENSE
VCCSA_VI VCCSA_VI
VDDQ
D[0] D[1]
23] 24] 25] 26]
A
A
8 7 6 5
3
QC3
QC3
O4728L_SO8~D
O4728L_SO8~D
4
1
CC
CC 4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
V_MEM
+1.5
N_CPU1.5VS3
нϭϱsͺWhͺsY^ŽƵƌĐĞ
_SM_VREF_CNT
+V
AY43
5A
AJ28
1]
AJ33
2]
AJ36
3]
AJ40
4]
AL30
5]
AL34
6]
AL38
7]
AL42
8]
AM33
9]
AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33
AM28
1]
AN26
2]
BC43 BA43
U10
D48
H_VCCSA_
D49
нsͺ^DͺsZ&ƐŚŽƵůĚŚĂǀĞϭϬŵŝů ƚƌĂĐĞǁŝĚƚŚ
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
250
250
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
161
161
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC
CC
+
+
167
167
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
2
VID1_R
1 2
RC138 0_0402_5%~DRC138 0_0402_5%~D
3
1 2 3
136
136
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
251
251
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
162
162
2
.5V_CPU_VDDQ
+1
CCSA_SENSE 56
+V
H_VCCSA_
1
2
1
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC252
CC252
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 163
163
1
2
+1
.5V_CPU_VDDQ
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
CC135
CC135
+1
.5V_CPU_VDDQ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
253
253
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC
CC 164
164
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC574
CC574
VID0
20K
20K
12
_0402_5%~D
_0402_5%~D
1
2
1
2
H_VCCSA_ H_VCCSA_
2
1 2
134 0_0402_5%~D@RC134 0_0402_5%~D@
RC
QC5
_DDR_REF
+V
@
@
RC73
RC73
RUN_O
N_CPU1.5VS3
CC
202 0.1U_0402_10V7K~D@CC202 0.1U_0402_10V7K~D@
173 0.1U_0402_10V7K~D@CC173 0.1U_0402_10V7K~D@
CC
149 0.1U_0402_10V7K~D
149 0.1U_0402_10V7K~D
CC
CC
150 0.1U_0402_10V7K~D
150 0.1U_0402_10V7K~D
CC
CC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
255
255
254
254
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC166
CC166
CC
CC
1
165
165
2
VID0 56 VID1 56
1U_0402_6.3V6K~D
CC
CC
CC257
CC257
1
1
256
256
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
179
179
178
178
2
2
QC5
R4503NT1G_SOT23-3~D
R4503NT1G_SOT23-3~D
NT
NT
1
12
12
12
12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
258
258
259
259
2
2
_SM_VREF_CNT
+V
3
100K
100K
12
RC78
RC78
_0402_5%~D
_0402_5%~D
2
+1.5
V_MEM
U1H
U1H
A13
]
VSS[1
A17
VSS[2
]
A21
]
VSS[3
A25
VSS[4
]
A28
5
]
VSS[
A33
]
VSS[6
A37
VSS[7
]
A40
]
VSS[8
A45
VSS[9
]
A49
0]
VSS[1
A53
1]
VSS[1
A9
VSS[1
2]
AA1
VSS[1
3]
AA13
VSS[1
4]
AA50
5]
VSS[1
AA51
6]
VSS[1
AA52
VSS[1
7]
AA53
VSS[1
8]
AA55
9]
VSS[1
AA56
0]
VSS[2
AA8
VSS[2
1]
AB16
2]
VSS[2
AB18
VSS[2
3]
AB21
4]
VSS[2
AB48
5]
VSS[2
AB61
VSS[2
6]
AC10
7]
VSS[2
AC14
8]
VSS[2
AC46
9]
VSS[2
AC6
VSS[3
0]
AD17
1]
VSS[3
AD20
2]
VSS[3
AD4
3]
VSS[3
AD61
4]
VSS[3
AE13
VSS[3
5]
AE8
6]
VSS[3
AF1
VSS[3
7]
AF17
8]
VSS[3
AF21
VSS[3
9]
AF47
0]
VSS[4
AF48
1]
VSS[4
AF50
VSS[4
2]
AF51
3]
VSS[4
AF52
VSS[4
4]
AF53
5]
VSS[4
AF55
VSS[4
6]
AF56
VSS[4
7]
AF58
VSS[4
8]
AF59
9]
VSS[4
AG10
0]
VSS[5
AG14
VSS[5
1]
AG18
2]
VSS[5
AG47
VSS[5
3]
AG52
4]
VSS[5
AG61
VSS[5
5]
AG7
VSS[
6]
5
AH4
7]
VSS[5
AH58
8]
VSS[5
AJ13
9]
VSS[5
AJ16
VSS[6
0]
AJ20
1]
VSS[6
AJ22
VSS[6
2]
AJ26
3]
VSS[6
AJ30
VSS[6
4]
AJ34
VSS[6
5]
AJ38
6]
VSS[6
AJ42
VSS[6
7]
AJ45
8]
VSS[6
AJ48
VSS[6
9]
AJ7
0]
VSS[7
AK1
VSS[7
1]
AK52
VSS[7
2]
AL10
VSS[7
3]
AL13
VSS[7
4]
AL17
5]
VSS[7
AL21
VSS[7
6]
AL25
7]
VSS[7
AL28
VSS[7
8]
AL33
9]
VSS[7
AL36
VSS[8
0]
AL40
1]
VSS[8
AL43
VSS[8
2]
AL47
VSS[8
3]
AL61
VSS[84]
AM13
VSS[8
5]
AM20
VSS[86]
AM22
VSS[8
7]
AM26
8]
VSS[8
AM30
VSS[8
9]
AM34
0]
VSS[9
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
S
S
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1
VSS
VSS
ndy Bridge (6/6)
ndy Bridge (6/6)
ndy Bridge (6/6)
Sa
Sa
Sa
LA
LA
LA
-6611P
-6611P
-6611P
1
AM38
1]
VSS[9
AM4
VSS[9
2]
AM42
3]
VSS[9
AM45
VSS[9
4]
AM48
9
5]
VSS[
AM58
6]
VSS[9
AN1
VSS[9
7]
AN21
8]
VSS[9
AN25
VSS[9
9]
AN28
00]
VSS[1
AN33
01]
VSS[1
AN36
VSS[1
02]
AN40
VSS[1
03]
AN43
VSS[1
04]
AN47
05]
VSS[1
AN50
06]
VSS[1
AN54
VSS[1
07]
AP10
VSS[1
08]
AP51
09]
VSS[1
AP55
10]
VSS[1
AP7
VSS[1
11]
AR13
12]
VSS[1
AR17
VSS[1
13]
AR21
14]
VSS[1
AR41
15]
VSS[1
AR48
VSS[1
16]
AR61
17]
VSS[1
AR7
18]
VSS[1
AT14
19]
VSS[1
AT19
VSS[1
20]
AT36
21]
VSS[1
AT4
22]
VSS[1
AT45
23]
VSS[1
AT52
24]
VSS[1
AT58
VSS[1
25]
AU1
26]
VSS[1
AU11
VSS[1
27]
AU28
28]
VSS[1
AU32
VSS[1
29]
AU51
30]
VSS[1
AU7
31]
VSS[1
AV17
VSS[1
32]
AV21
33]
VSS[1
AV22
VSS[1
34]
AV34
35]
VSS[1
AV40
VSS[1
36]
AV48
VSS[1
37]
AV55
VSS[1
38]
AW13
39]
VSS[1
AW43
40]
VSS[1
AW61
VSS[1
41]
AW7
42]
VSS[1
AY14
VSS[1
43]
AY19
44]
VSS[1
AY30
VSS[1
45]
AY36
VSS[
46]
1
AY4
47]
VSS[1
AY41
48]
VSS[1
AY45
49]
VSS[1
AY49
VSS[1
50]
AY55
51]
VSS[1
AY58
VSS[1
52]
AY9
53]
VSS[1
BA1
VSS[1
54]
BA11
VSS[1
55]
BA17
56]
VSS[1
BA21
VSS[1
57]
BA26
58]
VSS[1
BA32
VSS[1
59]
BA48
60]
VSS[1
BA51
VSS[1
61]
BB53
VSS[1
62]
BC13
VSS[1
63]
BC5
VSS[1
64]
BC57
65]
VSS[1
BD12
VSS[1
66]
BD16
67]
VSS[1
BD19
VSS[1
68]
BD23
69]
VSS[1
BD27
VSS[1
70]
BD32
71]
VSS[1
BD36
VSS[1
72]
BD40
VSS[1
73]
BD44
VSS[174]
BD48
VSS[1
75]
BD52
VSS[176]
BD56
VSS[1
77]
BD8
78]
VSS[1
BE5
VSS[1
79]
BG13
80]
VSS[1
/PROPRIETARY
11 64Wedn
11 64Wedn
11 64Wedn
of
of
of
5
RD
RD
1 0_0402_5%~D
1 0_0402_5%~D
_DDR_REF
+V
+D
DQS#[0..7]8
DDR_A_
DDR_A_
D[0..63]8
DDR_A_
DQS[0..7]8
DDR_A_
MA[0..15]8
D D
IMM0_1_VREF_CPU
WŽƉƵůĂƚĞZϭĨŽƌ/ŶƚĞůZϯ sZ&YŵƵůƚŝƉůĞŵĞƚŚŽĚƐDϭ
ůůsZ&ƚƌĂĐĞƐƐŚŽƵůĚ ŚĂǀĞϭϬŵŝůƚƌĂĐĞǁŝĚƚŚ
7 0_0402_5%~D@RD7 0_0402_5%~D@
RD
1 2 1 2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DD
+1.5
V_MEM
1U_0402_6.
1U_0402_6.
1U_0402_6.
1U_0402_6.
1
1
CD3
CD3
CD4
CD4
3V6K~D
3V6K~D
3V6K~D
3V6K~D
2
2
+1.5
C C
V_MEM
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD7
CD7
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD8
CD8
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD9
CD9
1
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
1U_0402_6.
1U_0402_6.
CD5
CD5
3V6K~D
3V6K~D
1
2
1U_0402_6.
1U_0402_6.
1
CD6
CD6
3V6K~D
3V6K~D
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD10
CD10
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD11
CD11
1
2
330U
330U
_0603_6.3V6M~D
_0603_6.3V6M~D
@
@
_SX_2VY~D
_SX_2VY~D
CD13
CD13
CD1
CD1
1
1
2
2
2
2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DDϮϬϯϮϬϰ
.75V_DDR_VTT
+0
B B
A A
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
CD17
CD17
CD18
CD18
2
2
5
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
CD20
CD20
CD19
CD19
2
2 10K_0402_5%~D
2 10K_0402_5%~D
RD
RD
1 2
1 2
RD
RD
3 10K_0402_5%~D
3 10K_0402_5%~D
4
2.
2. 2U
2U _0603_6.3V6K~D
_0603_6.3V6K~D
1
2
CD1
CD1
MM0_1_VREF_DQ
+DI
0.1U
0.1U
_0402_16V4Z~D
_0402_16V4Z~D
1
CD2
CD2
2
EŽƚĞ ŚĞĐŬǀŽůƚĂŐĞƚŽůĞƌĂŶĐĞŽĨ sZ&ͺYĂƚƚŚĞ/DDƐŽĐŬĞƚ
_DIMMA8
DDR_A_
M_
CLK_DDR08 CLK_DDR#08
M_
DDR_A_
DDR_A_
DDR_A_
DDR_CKE0
BS28
BS08
WE#8
CAS#8
_DIMMA#8
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD22
CD22
1
2
DDR_CKE0
1
CD14
CD14
+
+
2
DDR_CS1
+3.3V_RUN
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD21
CD21
1
2
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
A_
DDR_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
_DIMMA
DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
M_
CLK_DDR0
M_
CLK_DDR#0
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_CS1
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_D56 DDR_A_
DDR_A_ DDR_A_
+1.5
D0 D1
D2 D3
D8 D9
DQS#1 DQS1
D10 D11
D16 D17
DQS#2 DQS2
D18 D19
D24 D25
D26 D27
BS2
MA12 MA9
MA8 MA5
MA3 MA1
MA10 BS0
WE# CAS#
MA13
_DIMMA#
D32 D33
DQS#4 DQS4
D34 D35
D40 D41
D42 D43
D48 D49
DQS#6 DQS6
D50 D51
D57
D58 D59
V_MEM
/DD,сϰϬŵŵ
4
3
JD
JD
IMMA1
IMMA1
1
VREF_D
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
9
DQ
25
VSS
27
DQS1
#
29
DQS1
31
VSS
33
0
DQ1
35
1
DQ1
37
VSS
39
DQ1
6
41
DQ1
7
43
VSS
45
#
DQS2
47
DQS2
49
VSS
51
8
DQ1
53
9
DQ1
55
VSS
57
4
DQ2
59
DQ2
5
61
VSS
63
DM3
65
VSS
67
6
DQ2
69
7
DQ2
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/
BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
AP
A10/
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1
#
123
VDD
125
TEST
127
VSS
129
DQ3
2
131
3
DQ3
133
VSS
135
#
DQS4
137
DQS4
139
VSS
141
4
DQ3
143
DQ3
5
145
VSS
147
DQ4
0
149
1
DQ4
151
VSS
153
DM5
155
VSS
157
DQ4
2
159
3
DQ4
161
VSS
163
8
DQ4
165
DQ4
9
167
VSS
169
DQS6
#
171
DQS6
173
VSS
175
DQ5
0
177
DQ51
179
VSS
181
DQ56
183
DQ5
7
185
VSS
187
DM7
189
VSS
191
DQ5
8
193
9
DQ5
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013022-2~D
TYCO_2-2013022-2~D
Q
CONN@
CONN@
VREF_C
VSS DQ4 DQ5 VSS
DQS0
DQS0
VSS DQ6 DQ7
VSS DQ1 DQ
VSS
DM1
RESET#
VSS DQ1 DQ1
VSS DQ2 DQ2
VSS
DM2
VSS DQ2 DQ2
VSS DQ2 DQ2
VSS
DQS3
DQS3
VSS DQ3 DQ3
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1 RAS#
VDD
ODT
VDD ODT
VDD
VSS DQ3 DQ3
VSS
DM4
VSS DQ3 DQ3
VSS DQ4 DQ4
VSS
DQS5
DQS5
VSS DQ4 DQ4
VSS DQ5 DQ5
VSS
DM6
VSS DQ5 DQ5
VSS DQ6 DQ61
VSS
DQS7
DQS7
VSS DQ6 DQ6
VSS
EVENT#
SDA
SCL
VTT
GND1
V_MEM
+1.5
2 4 6 8 10
#
12 14 16 18 20 22
2
24
1
3
26 28 30 32 34
4
36
5
38 40
0
42
1
44 46 48 50
2
52
3
54 56
8
58
9
60 62
#
64 66 68
0
70
1
72
74 76 78
A15
80
A14
82 84
A11
86
A7
88 90
A6
92
A4
94 96
A2
98
A0
100 102 104 106 108 110 112 114
S0#
116
0
118 120
1
122
NC
124 126
A
128 130
6
132
7
134 136 138 140
8
142
9
144 146
4
148
5
150 152
#
154 156 158
6
160
7
162 164
2
166
3
168 170 172 174
4
176
5
178 180
0
182 184 186
#
188 190 192
2
194
3
196 198 200 202 204
206
ϮͲϯƚŽϭ/DDƐĐŚĂŶŶĞů
D4
DDR_A_ DDR_A_
D5
DDR_A_
DQS#0 DQS0
DDR_A_
DDR_A_
D6 D7
DDR_A_
DDR_A_
D12
DDR_A_
D13
DRAMRST#_R
DDR3_
A_
D14
DDR_
D15
DDR_A_
D20
DDR_A_ DDR_A_
D21
D22
DDR_A_ DDR_A_
D23
DDR_A_
D28
DDR_A_
D29
DQS#3
DDR_A_
DQS3
DDR_A_
D30
DDR_A_ DDR_A_
D31
_DIMMA
DDR_CKE1
MA15
DDR_A_ DDR_A_
MA14
DDR_A_
MA11 MA7
DDR_A_
DDR_A_
MA6 MA4
DDR_A_
MA2
DDR_A_ DDR_A_
MA0
M_
CLK_DDR1
M_
CLK_DDR#1
DDR_A_
BS1 RAS#
DDR_A_
_DIMMA#
DDR_CS0 M_O
DT0
M_O
DT1
DDR_A_
D36 D37
DDR_A_
DDR_A_
D38 D39
DDR_A_
D44
DDR_A_ DDR_A_
D45
DQS#5
DDR_A_ DDR_A_
DQS5
DDR_A_
D46 D47
DDR_A_
DDR_A_
D52
DDR_A_
D53
DDR_A_
D54 D55
DDR_A_
D60
DDR_A_ DDR_A_D61
DDR_A_DQS#7 DDR_A_
DQS7
DDR_A_
D62 D63
DDR_A_
DDR_XDP_WAN_SMBDAT
WAN_SMBCLK
DDR_XDP_
+0.75V_DDR_VTT+0.75V_DDR_VTT
DDR3_
DDR_CKE1
M_
CLK_DDR1 8
CLK_DDR#1 8
M_
DDR_A_
DDR_A_
DDR_CS0
M_O
M_O
DRAMRST#_R13
2
DRAMRST#_R
DDR3_
_DIMMA 8
BS1 8
RAS# 8
_DIMMA# 8
DT0 8
DT1 8
MM0_1_VREF_CA
+DI
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD15
CD15
1
2
WAN_SMBDAT 13,15,28,37
DDR_XDP_
DDR_XDP_WAN_SMBCLK 13,15,28,37
1
2
>ŝŶŬŽŶĞ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
1 2
RD
RD
28 1K_0402_1%~D
28 1K_0402_1%~D
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD16
CD16
1
+1.5
V_MEM
12
RD27
RD27
_0402_1%~D
_0402_1%~D
1K
1K
DDR3_
DRAMRST# 7
RD290_0402_5%
~D
~D
~D @
~D @
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RD290_0402_5%
12
+V
RD310_0402_5%
RD310_0402_5%
12
+DI
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
DDRIII-S
DDRIII-S
DDRIII-S
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
_DDR_REF
MM0_1_CA_CPU
/PROPRIETARY
ODIMM SLOT1
ODIMM SLOT1
ODIMM SLOT1
12 64We
12 64We
12 64We
1
of
of
of
5
DDR_B_
DQS#[0..7]8
DDR_B_
D[0..63]8
DDR_B_
DQS[0..7]8
DDR_B_
D D
MA[0..15]8
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DD
V_MEM
+1.5
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
C C
V_MEM
+1.5
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
1
2
B B
1
CD25
CD25
CD26
CD26
2
2
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CD30
CD30
CD29
CD29
CD31
CD31
1
2
1
1
2
2
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD28
CD28
CD27
CD27
2
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CD34
CD32
CD32
CD34
CD33
CD33
1
1
2
2
330U
330U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_SX_2VY~D
_SX_2VY~D
@
@
1
CD36
CD36
CD35
CD35
1
+
+
2
2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DDϮϬϯϮϬϰ
.75V_DDR_VTT
+0
1U
1U
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
A A
CD40
CD40
CD39
CD39
2
5
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
CD41
CD41
CD42
CD42
2
2
4
ůůsZ&ƚƌĂĐĞƐƐŚŽƵůĚ ŚĂǀĞϭϬŵŝůƚƌĂĐĞǁŝĚƚŚ
WŽƉƵůĂƚĞZϭĨŽƌ/ŶƚĞůZϯ sZ&YŵƵůƚŝƉůĞŵĞƚŚŽĚƐDϭ
EŽƚĞ ŚĞĐŬǀŽůƚĂŐĞƚŽůĞƌĂŶĐĞŽĨ sZ&ͺYĂƚƚŚĞ/DDƐŽĐŬĞƚ
.3V_RUN
+3
RD5 10K_0402_5%~DRD5 10K_0402_5%~D
4
+DI
+3.3V_RUN
12
MM0_1_VREF_DQ
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
1
CD23
CD23
2
DDR_CKE2
M_ M_
DDR_CS3
_DIMMB#8
12
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
2
_DIMMB8
DDR_B_
CLK_DDR28 CLK_DDR#28
DDR_B_
DDR_B_
DDR_B_
10K_0402_5%
10K_0402_5%
RD6
RD6
~D
~D
3
ϮͲϯƚŽϭ/DDƐĐŚĂŶŶĞů
V_MEM
CD24
CD24
BS28
BS08
WE#8
CAS#8
1
2
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_CKE2
DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
M_ M_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_
DDR_
CS3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_D51
DDR_B_D56 DDR_B_
DDR_B_ DDR_B_
+0.75V_DDR_VTT
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD43
CD43
+1.5
D0 D1
D2 D3
D8 D9
DQS#1
B_
DQS1
D10 D11
D16 D17
DQS#2 DQS2
D18 D19
D24 D25
D26 D27
_DIMMB
BS2
MA12 MA9
MA8 MA5
MA3 MA1
CLK_DDR2 CLK_DDR#2
MA10 BS0
WE# CAS#
MA13
_DIMMB#
D32 D33
DQS#4 DQS4
D34 D35
D40 D41
D42 D43
D48 D49
DQS#6 DQS6
D50
D57
D58 D59
1
2
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD44
CD44
JD
JD
IMMB1
IMMB1
1
VREF_D
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1
#
29
DQS1
31
VSS
33
DQ1
0
35
DQ1
1
37
VSS
39
6
DQ1
41
7
DQ1
43
VSS
45
DQS2
#
47
DQS2
49
VSS
51
DQ1
8
53
9
DQ1
55
VSS
57
4
DQ2
59
5
DQ2
61
VSS
63
DM3
65
VSS
67
6
DQ2
69
DQ2
7
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12
/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10
/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ3
2
131
3
DQ3
133
VSS
135
DQS4
#
137
DQS4
139
VSS
141
4
DQ3
143
DQ3
5
145
VSS
147
DQ4
0
149
DQ4
1
151
VSS
153
DM5
155
VSS
157
DQ4
2
159
3
DQ4
161
VSS
163
8
DQ4
165
DQ4
9
167
VSS
169
DQS6
#
171
DQS6
173
VSS
175
DQ5
0
177
DQ51
179
VSS
181
6
DQ5
183
DQ5
7
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ5
9
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013297-2~D
TYCO_2-2013297-2~D
CONN@
CONN@
Q
DQS0
RESET#
DQS3
VREF_C
DQS5
DQS7
EVENT#
DQS0
DQ1 DQ1
DQ1 DQ1
DQ2 DQ2
DQ2 DQ2
DQ2 DQ2
DQS3
DQ3 DQ3
CKE1
RAS#
ODT
ODT
DQ3 DQ3
DQ3 DQ3
DQ4 DQ4
DQS5
DQ4 DQ4
DQ5 DQ5
DQ54 DQ5
DQ6 DQ6
DQS7
DQ62 DQ6
GND1
/DD,сϴŵŵ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DQ4 DQ5 VSS
VSS DQ6 DQ7 VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA SCL VTT
VSS
A15 A14
A11
S0#
V_MEM
+1.5
2
DDR_B_
4
DDR_B_
6 8
DDR_B_
10
#
2 3
4 5
0 1
2 3
8 9
#
0 1
A7
A6 A4
A2 A0
0
1
NC
A
6 7
8 9
4 5
#
6 7
2 3
5
0 1
#
3
12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_CKE3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
M_ M_
DDR_B_ DDR_B_
DDR_CS2 M_O
M_O
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_D61
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_XDP_WAN_SMBDAT DDR_XDP_
+0.75V_DDR_VTT
>ŝŶŬŽŶĞ
D4 D5
DQS#0 DQS0
D6 D7
D12 D13
_
DRAMRST#_R
D14 D15
D20 D21
D22 D23
D28 D29
DQS#3 DQS3
D30 D31
MA15 MA14
MA11 MA7
MA6 MA4
MA2 MA0
CLK_DDR3 CLK_DDR#3
BS1 RAS#
_DIMMB#
DT2
DT3
D36 D37
D38 D39
D44 D45
DQS#5 DQS5
D46 D47
D52 D53
D54 D55
D60
DQS#7 DQS7
D62 D63
2
_DIMMB
WAN_SMBCLK
2
DRAMRST#_R 12
DDR3_
DDR_CKE3
_DIMMB 8
CLK_DDR3 8
M_
CLK_DDR#3 8
M_
DDR_B_
BS1 8
RAS# 8
DDR_B_
DDR_CS2
_DIMMB# 8
M_O
DT2 8
DT3 8
M_O
MM0_1_VREF_CA
+DI
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
1
CD37
CD37
2
DDR_XDP_
DDR_XDP_WAN_SMBCLK 12,15,28,37
1
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
CD38
CD38
2
WAN_SMBDAT 12,15,28,37
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
DDRIII-S
DDRIII-S
DDRIII-S
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
ODIMM SLOT2
ODIMM SLOT2
ODIMM SLOT2
13 64We
13 64We
13 64We
1
of
of
of
5
S_CLR1
CMO
Shunt
Open
ME_
CLR1
TPM setting
Shunt
Clear
Keep
Open
D D
TC
_CELL
+R
12
RH38
RH38 330K
330K
_0402_1%~D
_0402_1%~D
PCH_I
12
@
@
RH39
RH39
_0402_1%~D
_0402_1%~D
330K
330K
setting
CMOS
Clear
CMOS
Keep CM
OS
ME RTC Registers
ME RTC Registers
NTVRMEN
W,ͺͺ^zEŝƐƐĂŵƉůĞĚ ĂƚƚŚĞƌŝƐŝŶŐĞĚŐĞŽĨZ^DZ^dηƉŝŶ ^ŽƐŝŐŶĂůƐŚŽƵůĚďĞWhƚŽƚŚĞ>tz^ƌĂŝů
.3V_ALW_PCH
+3
12
RH66
RH66
_0402_5%~D
_0402_5%~D
1K
1K
PCH_AZ
_SYNC
12
2
@
2
@
RH28
RH28 100K_0402_5%~D
100K_0402_5%~D
KŶŝĞW>>sZŝƐƐƵƉƉůŝĞĚďLJ ϭϱsǁŚĞŶƐĂŵƉůĞĚŚŝŐŚϭϴs ǁŚĞŶƐĂŵƉůĞĚůŽǁ
/EdsZDEͲ/ŶƚĞŐƌĂƚĞĚ^h^ϭϭs sZDŶĂďůĞ
Ύ
,ŝŐŚͲŶĂďůĞ/ŶƚĞƌŶĂůsZƐ >ŽǁͲŶĂďůĞdžƚĞƌŶĂůsZƐ
1
1
C C
SPI_
DO32
I_CLK32
SP
PCH_
_CS0#
SPI
+3.3
V_M
@
@
ME
ME
CONN@
CONN@
JP1
JP1
112 334 556 778 9910 111112
G113G2 G315G4 G517G6
CO_5-1775013-4~D
CO_5-1775013-4~D
TY
TY
1 SHORT PADS~D
1 SHORT PADS~D
1 2
CH
CH
5 1U_0402_6.3V6K~D
5 1U_0402_6.3V6K~D
2 4 6 8
PCH_SPI
10 12
14 16 18
>ŝŶŬŽŶĞ
B B
5@
5@
R933 0_0402_5%
R933 0_0402_5%
1 2
R894 33_0402_5%
R894 33_0402_5%
1 2
R898 0_0402_5%
R898 0_0402_5%
1 2
SPI_
PCH_SPI
PCH_SPI
WP#_SEL42
_CS0#
_DIN
2
2
I_DIN32
SP
_CS1_R#
R890
R890
5@
5@
3.
3.
3K_0402_5%~D
3K_0402_5%~D
~D
~D
+RTC
PCH_SPI
~D5@
~D5@
~D@
~D@
SPI_
SPI_
_CELL
1 2
_CS0_R#
DIN64
WP#0
1 2
22 20K_0402_5%~D
22 20K_0402_5%~D
RH
RH
1 2
23 20K_0402_5%~D
23 20K_0402_5%~D
RH
RH
1 2
11 1M_0402_5%~D
11 1M_0402_5%~D
RH
RH
1
1
@
@
CMO
CMO
CH4
CH4
DK^ƉůĂĐĞŶĞĂƌ/DD
_CODEC_SDOUT30
PCH_AZ
CODEC_SYNC30
PCH_AZ_
CODEC_RST#30
PCH_AZ_
PCH_AZ_
CODEC_BITCLK30
27P_0402_50V8J~D
27P_0402_50V8J~D
X76ROM@
X76ROM@
U52
U52
1
/CS
2
DO
3
/WP
GND4DIO
25Q64BVSSIG_SO8~D
25Q64BVSSIG_SO8~D
W
W
S1 SHORT PADS~D
S1 SHORT PADS~D
1 2
1U_0402_6.
1U_0402_6.
101
@CH101
@
CH
8
VCC
7
D
/HOL
6
CLK
5
ϮϬϬD/>^Kϴ
ϲϰDď&ůĂƐŚZKD
R888
R888
5@
5@
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
U53
X76ROM@U53
PCH_SPI
_CS1#
R935
R935
PCH_SPI
SPI_
_DIN
WP#_SEL
A A
1 2
R895 33_0402_5%
R895 33_0402_5%
1 2
1 2
R936 0_0402_5%
R936 0_0402_5%
R896 0_0402_5%
R896 0_0402_5%
1 2
PCH_SPI
0_0402_5%
0_0402_5%
~D
~D
~D6@
~D6@
_CS1_R#
~D5@
~D5@
~D@
~D@
SPI_
R936 colay R895 for TAA
1
/CS
DIN32
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q16BVSSIG_SO8~D
W25Q16BVSSIG_SO8~D
ϮϬϬD/>^Kϴ
X76ROM@
VCC
/HOLD(IO3)
CLK
IO0)
DI(
8
7
6
5
ϭϲDď&ůĂƐŚZKD
5
2
2
3V6K~D
3V6K~D
1 2
29 33_0402_5%~D
29 33_0402_5%~D
RH
RH
1 2
RH
RH
26 33_0402_5%~D
26 33_0402_5%~D
1 2
27 33_0402_5%~D
27 33_0402_5%~D
RH
RH
1 2
25 33_0402_5%~D
25 33_0402_5%~D
RH
RH
1
2
SPI_
I_CLK64
SP
SPI_
SPI_
HOLD#1
SPI_CLK32
SPI_DO32
4
SPKR
H
H
35 10K_0402_5%~D@
35 10K_0402_5%~D@
R
R
No Reboot Strap
Low = Default
SPKR
High = No Reboot
CH2
CH2
15P_0402_50V
15P_0402_50V
CH3
CH3
15P_0402_50V
15P_0402_50V
PCH_AZ
PCH_AZ
PCH_AZ_
PCH_AZ
V_M
+3.3
5@
5@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R891
R891
3.
3.
1 2
HOLD#0
DO64
+3.3
V_M
1 2
~D
~D
1 2
1 2
R944 0_0402_5%
R944 0_0402_5%
~D 5@
~D 5@
1 2
1 2
R943 0_0402_5%~D6@R943 0_0402_5%~D6@
4
+3
.3V_RUN
12
12
8J~D
8J~D
8J~D
8J~D
12
_SDOUT
_SYNC_Q
RST#
_BITCLK
C74
C74
6
6
1 2
5@
5@
3K_0402_5%~D
3K_0402_5%~D
~D
~D
1 2
1 2
C745
C745
1 2
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
R892
R892
5@
5@
3K_0402_5%~D
3K_0402_5%~D
3.
3.
R944 colay R897 for TAA
5@
5@
+3
.3V_RUN
YH1
YH1
768KHZ_12.5PF_Q13MC1461000~D
768KHZ_12.5PF_Q13MC1461000~D
32.
32.
1
G
G
G
G
RH
RH
PCH_AZ
FWP42
ME_
+3
.3V_ALW_PCH
USB30
5@
5@
R89756_0402_5%
R89756_0402_5%
R90033_0402_5%
R90033_0402_5%
PCH_SPI
R89956_0402_5%
R89956_0402_5%
PCH_SPI
R90133_0402_5%~D 5@ R 90133_0402_5%~D 5@
PCH_SPI_CLK
~D6@
~D6@
PCH_SPI
_CLK
_DO
1
2
_DO
RH
RH
2
34
1 2
286 0_0402_5%~D
286 0_0402_5%~D
_CODEC_SDIN030
RH
RH
1 2
RH
_SMI#29
SP
I_CLK64
CH
CH 27P_0402_50V8J~D
27P_0402_50V8J~D
@
@
R943 colay R900 for TAA
TRST#_EC17,35,37,38,42,43
PCH_PL
RH
RH
37 10K_0402_5%~D
37 10K_0402_5%~D
50 1K_0402_5%~D
50 1K_0402_5%~D
287 1K_0402_5%~D@RH287 1K_0402_5%~D@
108
108
12
41 1M_0402_5%~D
41 1M_0402_5%~D
_SYNC_Q
PCH_AZ
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
PCH_AZ
_SYNC_Q
12
12
RH2
RH2 10M_0402_5%
10M_0402_5%
PCH_RT
SRTCRST
IN
TRUDER#
PCH_I
PCH_AZ
PCH_AZ
SPKR
SPKR30
PCH_AZ_
PCH_AZ
1 2
T132 P
T132 P
B30_SMI#
US
PCH_J
PCH_J
PCH_J
PCH_J
PCH_SPI
PCH_SPI
PCH_SPI
PCH_SPI
PCH_SPI
+3
SP
I_CLK32
1
107
107
CH
CH 27P_0402_50V8J~D
27P_0402_50V8J~D
2
@
@
PCH_RT
PCH_RT
.3V_ALW_PCH
3
G
G
2
13
D
S
D
S
QH7
QH7
CX1
~D
~D
CX2
CRST#
#
NTVRMEN
_BITCLK
_SYNC
RST#
_CODEC_SDIN0
PCH_AZ
AD~D@
AD~D@
TAG_TCK
TAG_TMS
TAG_TDI
TAG_TDO
_CLK
_CS0#
_CS1#
_DO
_DIN
12
RH
RH
0_0603_5%~D
0_0603_5%~D
+3
3
_RUN
+1.05V
0.1U
0.1U
@
@
_0402_16V4Z~D
_0402_16V4Z~D
CH6
CH6
1
2
_SYNC
PCH_AZ
SIO
_PWRBTN#_R
_SDOUT
@
@
288
288
.3V_ALW_PCH_JTAG
36 10K_0402_5%~D@RH36 10K_0402_5%~D@
RH
RST#16,43
PCH_RSM
UH4A
UH4A
0
A2
RTCX1
0
C2
RTCX2
D20
RTCRST
#
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
H7
H1
Y14
U3
#
SRTCRST
IN
TRUDER#
VRMEN
INT
CLK
HDA_B
YNC
HDA_S
SPKR
HDA_R
ST#
DIN0
HDA_S
HDA_S
DIN1
DIN2
HDA_S
HDA_S
DIN3
DO
HDA_S
OCK_EN# / GPIO33
HDA_D
OCK_RST# / GPIO13
HDA_D
J3
G_TCK
JTA
JTA
G_TMS
K5
JTA
G_TDI
JTA
G_TDO
T3
I_CLK
SP
CS0#
SPI_
T1
CS1#
SPI_
V4
SPI_
MOSI
SPI_MISO
2CPMS-QMVY-A1_FCBGA989~D
2CPMS-QMVY-A1_FCBGA989~D
BD8
BD8
/ŶƚĞůƌĞǀŝĞǁĨĞĞĚďĂĐŬ
RH59 51_0402_1%~DRH59 51_0402_1%~D
44 200_0402_1%~D
44 200_0402_1%~D
RH
RH
45 200_0402_1%~D
45 200_0402_1%~D
RH
RH
43 200_0402_1%~D
43 200_0402_1%~D
RH
RH
+3.3V_RUN
8.2K_0402_5%~D
8.2K_0402_5%~D
@RH295
@
12
RH295
SPI_MOSI
,ŝŐŚŶĂďůĞ/ŶƚĞůŶƚŝͲdŚĞĨƚdĞĐŚŶŽůŽŐLJ >ĞĨƚĨůŽĂƚŝŶŐŝƐĂďůĞ/ŶƚĞůŶƚŝͲdŚĞĨƚdĞĐŚŶŽůŽŐLJ
PCH_RSM
12
12
12
12
PCH_SPI
+3
.3V_ALW_PCH
12
RST#
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
_DO
.3V_ALW_PCH
+3
0.1U
0.1U
@
@
_0402_16V4Z~D
_0402_16V4Z~D
CH1
CH1
1
2
RH
24 1K_0402_5%~D@RH24 1K_0402_5%~D@
FW FW FW FW
LPC
LPC
H4 / LFRAME#
FW
LD
RQ1# / GPIO23
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP SATA1TXN
SATA1TXP
SATA2RXN SATA2RXP SATA2TXN
SATA2TXP
SATA3RXN SATA3RXP SATA3TXN
SATA3TXP
SATA4RXN SATA4 SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN SATA5RXP SATA5TXN
SATA5TXP
SATAICO
SATAICO
SATA3RCO
SATA3CO
SATA3RBI
SATALED#
SATA0G
P / GPIO21
SATA1GP / GPIO19
12
RH48
RH48
@
@
2
,ϭĐůƐŽĞƚŽ:yWϮ,ϲĐůƐŽĞƚŽ:yWϮ
12
H0 / LAD0 H1 / LAD1 H2 / LAD2 H3 / LAD3
LDRQ
SERIR
RXP
MPO
MPI
MPO
MPI
PCH_J
12
RH49
RH49
@
@
100_0402_1%~D
100_0402_1%~D
2
1.05V
+3
XDP_DBRESET#7,
16
RSMR
C38 A38 B37 C37
D36
E36
0#
K36
V5
Q
AM AM AP7 AP5
AM AM AP1 AP1
AD7 AD5 AH5 AH4
AB8 AB1 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11
Y10
AB12
AB13
AH1
AS
P3
V14
P1
TAG_TCK
PCH_J
TAG_TMS
TAG_TDI
PCH_J
PCH_J
TAG_TDO
~D
~D
12
RH47
RH47
@
@
100_0402_1%
100_0402_1%
RSMR
_0.8V_PWROK43,53
_PWRBTN#_R7,16
SIO
.3V_ALW_PCH
ST#_XDP
LP
C_LAD0
LP
C_LAD1 C_LAD2
LP
C_LAD3
LP
C_LFRAME#
LP
C_LDRQ0#
LP LP
C_LDRQ1#
IRQ_
3 1
10 8
1 0
0
+SATA_
+SATA3
RBIAS_
SATA_ACT#
HDD_DET
BBS_BI
~D
~D
100_0402_1%
100_0402_1%
ST#_XDP
SERIRQ
SATA3
T0_R
PCH_PL
1
+1.05V
_RUN
RH
284 0_0402_5%~D@RH284 0_0402_5%~D@
1 2
283 1K_0402_5%~D@RH283 1K_0402_5%~D@
RH
1 2 1 2
RH
21 0_0402_5%~D@RH21 0_0402_5%~D@
RSMR
ST#_XDP
DBRESET#
XDP_
PCH_J
TAG_TDO
PCH_J
TAG_TDI TAG_TMS
PCH_J
TAG_TCK
PCH_J
LPC
LP
C_LDRQ0# 42
L
C_LDRQ1# 42
P
IR
Q_SERIRQ 34,35,42,43
PSATA_PRX_ PSATA_PRX_
PSATA_PTX_
PSATA_PTX_
SATA_O
SATA_O SATA_O SATA_O
ESATA_PRX_
ESATA_PRX_ ESATA_PTX_ ESATA_PTX_
SATA_PRX_
SATA_PRX_ SATA_PTX_ SATA_PTX_
COMP
1 2
40 37.4_0402_1%~D
40 37.4_0402_1%~D
RH
RH
_COMP
1 2
42 49.9_0402_1%~D
42 49.9_0402_1%~D
RH
RH
1 2
RH
RH
46 750_0402_1%~D
46 750_0402_1%~D
#_R
1 3
1 BSS138W-7-F_SOT323-3~D
1 BSS138W-7-F_SOT323-3~D
QH
QH
TRST#7,17
+3.3V_RUN
_0.8V_PWROK_R
1.05V RBTN#_XDP
PCH_PW
_LAD0 34,35,42,43
LPC LPC
_LAD1 34,35,42,43 _LAD2 34,35,42,43
LPC LPC
_LAD3 34,35,42,43
_LFRAME# 34,35,42,43
DTX_N0_C 28
DTX_P0_C 28 DRX_N0_C 28 DRX_P0_C 28
DD_PRX_DTX_N1_C 29 DD_PRX_DTX_P1_C 29 DD_PTX_DRX_N1_C 29 DD_PTX_DRX_P1_C 29
DTX_N4_C 40
DTX_P4_C 40 DRX_N4_C 40 DRX_P4_C 40
DKTX_N5_C 41
DKTX_P5_C 41
DKRX_N5_C 41
DKRX_P5_C 41
SATA_ACT#
46
1 2
RH290 0_0402_5%~DRH290 0_0402_5%~D
D
S
D
S
G
G
2
+1.05V
+1.05V
SERIRQ
IRQ_
2K_0402_5%~D
2K_0402_5%~D
,
KDŽĚƵůĞĂLJ
Ͳ^d
K<
_RUN
_RUN
+3
.3V_RUN
^ͺ/dϬͲ/K^KKd^dZW/dϬ
7K_0402_5%~D
7K_0402_5%~D
4.
4.
T0_R
BBS_BI
12
^dϬ'WWƐŝŵƵůĂƚĞƐƚŚĞĚƌŝǀĞƐƚĂƚƵƐ
RH31
RH31
&ŽƌƉƌŽƉĞƌĨƵŶĐƚŝŽŶŽĨƚŚĞŚŽƚƉůƵŐ ƚŚŝƐZϭϱϵϳŵƵƐƚďĞΗEŽ^ŚƵŶƚΗ ǁŚĞŶƌĞƐƉĞĐƚŝǀĞĚƌŝǀĞŝƐƌĞŵŽǀĞĚ ĂŶĚΗ^ŚƵŶƚΗĂĨƚĞƌƚŚĞƌĞƐƉĞĐƚŝǀĞ ĚƌŝǀĞŝƐƉůƵŐŐĞĚŝŶ
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1/8)
1/8)
1/8)
-6611P
-6611P
-6611P
1
P2
@
P2
@
JXD
JXD
1
OBSFN_
A0
2
A1
OBSFN_
3
GND
4
OBSDATA_
A[0]
5
A[1]
OBSDATA_
6
GND
7
A[2]
OBSDATA_
8
OBSDATA_
A[3]
9
GND
10
HOOK
0
11
1
HOOK
12
HOOK
2
13
OOK
3
H
14
4
HOOK
15
HOOK
5
16
AB
VCCOBS_
17
HOOK
6
18
7
HOOK
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
MOLEX_52435-2671
12
RH30
RH30 10K
10K
PCH_SATA_
GND
+3
12
RH288.
RH288.
_0402_5%~D
_0402_5%~D
HDD_DET
27 28
.3V_RUN
# 28
MOD_EN# 43
/PROPRIETARY
14 64Wedn
14 64Wedn
14 64Wedn
of
of
of
5
D D
&ŽůůŽǁ'ϬϵĞǀŝĐĞĚŽǁŶΘdžƉƌĞƐƐDŝŶŝĐĂƌĚ ƚŽƉŽůŽŐLJ
IE_PRX_WANTX_N137
PC PC
MiniWWAN (Mini Card 1)--->
MiniWLAN (Mini Card 2)--->
EXPRESS Card--->
E3 Module Bay--->
1/2vMINI CARD-3 PCIE (Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
MiniWWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI Card--->
B B
MiniWPAN (Mini Card 3)--->
Express card--->
MiniWLAN (Mini Card 2)--->
eModule Bay--->
A A
IE_PRX_WANTX_P137
PC
IE_PTX_WANRX_N137 IE_PTX_WANRX_P137
PC
_PRX_WLANTX_N237
PCIE PCIE
_PRX_WLANTX_P237
PC
IE_PTX_WLANRX_N237 IE_PTX_WLANRX_P237
PC
PCIE
_PRX_EXPTX_N338
PCI
PRX_EXPTX_P338
E_
_PTX_EXPRX_N338
PCIE
PTX_EXPRX_P338
PCIE_
PC
IE_PRX_EMBTX_N429 IE_PRX_EMBTX_P429
PC
IE_PTX_EMBRX_N429
PC PC
IE_PTX_EMBRX_P429
PCI
_PRX_WPANTX_N537
E
_PRX_WPANTX_P537
PCIE
_PTX_WPANRX_N537
PCIE PCIE
_PTX_WPANRX_P537
IE_PRX_MMITX_N636
PC PC
IE_PRX_MMITX_P636
PC
IE_PTX_MMIRX_N636
PC
IE_PTX_MMIRX_P636
IE_PRX_GLANTX_N732
PC PC
IE_PRX_GLANTX_P732
PC
IE_PTX_GLANRX_N732 IE_PTX_GLANRX_P732
PC
K_PCIE_MIN I1#37
CL
K_PCIE_MIN I137
CL
.3V_ALW_PCH
+3
MI
NI1CLK_REQ#37
PCIE_LAN#32
CLK_ CLK_
PCIE_LAN32
NCLK_REQ#32
LA
CLK_
PCIE_MMI#36 PCIE_MMI36
CLK_
+3
ICLK_REQ#36
MM
K_PCIE_MIN I3#37
CL
K_PCIE_MIN I337
CL
.3V_ALW_PCH
+3
NI3CLK_REQ#37
MI
PCIE_EXP#38
CLK_
CLK_
+3
.3V_ALW_PCH
EXPCLK
CL
K_PCIE_MIN I2#37
K_PCIE_MIN I237
CL
.3V_ALW_PCH
+3
NI2CLK_REQ#37
MI
.3V_ALW_PCH
+3
CLK_PCIE_EMB#29 CLK_
PCIE_EMB29
+3
.3V_ALW_PCH
EMBCL
CLK_
CPU_ITP#7
CPU_ITP7
CLK_
W/ZYƉŽǁĞƌƌĂŝů
.3V_RUN
PCIE_EXP38
_REQ#38
K_REQ#29
307 0_0402_5%~D
307 0_0402_5%~D
RH
RH
308 0_0402_5%~D
308 0_0402_5%~D
RH
RH
81 10K_0402_5%~D
81 10K_0402_5%~D
RH
RH
RH
RH
82 0_0402_5%~D
82 0_0402_5%~D
RH
RH
83 0_0402_5%~D
83 0_0402_5%~D
RH
RH
85 0_0402_5%~D
85 0_0402_5%~D 86 0_0402_5%~D
86 0_0402_5%~D
RH
RH
87 10K_0402_5%~D
87 10K_0402_5%~D
RH
RH
88 0_0402_5%~D
88 0_0402_5%~D
RH
RH
90 0_0402_5%~D
90 0_0402_5%~D
RH
RH RH
RH
152 10K_0402_5%~D
152 10K_0402_5%~D
RH
RH
92 0_0402_5%~D
92 0_0402_5%~D 93 0_0402_5%~D
93 0_0402_5%~D
RH
RH
94 10K_0402_5%~D
94 10K_0402_5%~D
RH
RH
95 0_0402_5%~D
95 0_0402_5%~D
RH
RH RH96 0_0402_5%~DRH96 0_0402_5%~D RH
RH
97 10K_0402_5%~D
97 10K_0402_5%~D
98 10K_0402_5%~D
98 10K_0402_5%~D
RH
RH
RH310 0_0402_5%~DRH310 0_0402_5%~D
312 0_0402_5%~D
312 0_0402_5%~D
RH
RH RH104 10K_0402_5%~DRH104 10K_0402_5%~D
RH
RH
280 0_0402_5%~D
280 0_0402_5%~D 281 0_0402_5%~D
281 0_0402_5%~D
RH
RH
ƐƵƐƉĞŶĚϬϯϰϱϲϳ ĐŽƌĞϭϮ
5
1 2
1 2
4
UH4B
C
IE_PRX_WANTX_N1
P
IE_PRX_WANTX_P1
PC PC
IE_PTX_WANRX_N1 IE_PTX_WANRX_P1
PC
IE_PRX_WLANTX_N2
PC
IE_PRX_WLANTX_P2
PC PC
IE_PTX_WLANRX_N2 IE_PTX_WLANRX_P2
PC
_PRX_EXPTX_N3
PCIE PCIE_
PRX_EXPTX_P3
PCIE
_PTX_EXPRX_N3
PCIE_
PTX_EXPRX_P3
IE_PRX_EMBTX_N4
PC PC
IE_PRX_EMBTX_P4 IE_PTX_EMBRX_N4
PC PC
IE_PTX_EMBRX_P4
PC
IE_PRX_WPANTX_N5
PC
IE_PRX_WPANTX_P5 IE_PTX_WPANRX_N5
PC
IE_PTX_WPANRX_P5
PC
PC
IE_PRX_MMITX_N6 IE_PRX_MMITX_P6
PC PC
IE_PTX_MMIRX_N6 IE_PTX_MMIRX_P6
PC
PC
IE_PRX_GLANTX_N7 IE_PRX_GLANTX_P7
PC PC
IE_PTX_GLANRX_N7 IE_PTX_GLANRX_P7
PC
PC
12 12 12
12 12
12 12
12 12 12
12 12 12
12 12 12
12 12 12
12 12
4
IE_MINI1# IE_MINI1
PC
NI1CLK_REQ#
MI
_LAN#
PCIE PCI
_LAN
E
LA
NCLK_REQ#
IE_MMI#
PC PC
IE_MMI
ICLK_REQ#
MM
PC
IE_MINI3# IE_MINI3
PC
MI
NI3CLK_REQ#
_EXP#
PCIE
_EXP
PCIE
EXPCLK
_REQ#
IE_MINI2#
PC PC
IE_MINI2
MI
NI2CLK_REQ#
G_B_CLKRQ#
PE
PCIE
_EMB# _EMB
PCIE
K_REQ#
EMBCL
BCLK_ITP#
CLK_ CLK_BCLK_ITP
UH4B
4
BG3
PERN1
4
BJ3
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY3
2
PETP2
6
BG3
PERN3
BJ3
6
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
4
AY3
PETN4
BB34
PETP4
BG3
7
PERN5
BH37
PERP5
6
AY3
PETN5
BB36
PETP5
BJ3
8
PERN6
8
BG3
PERP6
AU36
PETN6
AV36
PETP6
0
BG4
PERN7
0
BJ4
PERP7
AY4
0
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW3
8
PETN8
AY3
8
PETP8
Y40
CLKO
UT_PCIE0N
Y39
UT_PCIE0P
CLKO
J2
IECLKRQ0# / GP IO73
PC
AB49
UT_PCIE1N
CLKO
AB47
UT_PCIE1P
CLKO
M1
PC
IECLKRQ1# / GP IO18
AA48
UT_PCIE2N
CLKO
AA47
CLKO
UT_PCIE2P
V10
IECLKRQ2# / GP IO20
PC
Y37
CLKO
UT_PCIE3N
Y36
UT_PCIE3P
CLKO
A8
PC
IECLKRQ3# / GP IO25
Y43
UT_PCIE4N
CLKO
Y45
CLKO
UT_PCIE4P
L12
PC
IECLKRQ4# / GP IO26
V45
UT_PCIE5N
CLKO
V46
CLKO
UT_PCIE5P
L14
PCIECLKR Q5# / GPIO44
AB42
CLKO
UT_PEG_B_N
AB40
UT_PEG_B_P
CLKO
E6
G_B_CLKRQ# / GPIO56
PE
V40
CLKOUT_PCIE6N
V42
CLKO
UT_PCIE6P
T13
PC
IECLKRQ6# / GP IO45
V38
CLKO
UT_PCIE7N
V37
UT_PCIE7P
CLKO
K12
IECLKRQ7# / GP IO46
PC
AK14
CLKO
UT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
3
B_ALERT#
PCH_SM
SMBCL
SMBDATA
SM
L0CLK
SML
0DATA
CL_C
DATA1
CL_
RST1#
CL_
UT_DMI_N UT_DMI_P
UT_DP_N
UT_DP_P
N_DMI_N
N_DMI_P
N_GND1_N N_GND1_P
N_DOT_96P
N_SATA_N N_SATA_P
FCLK14IN
XTAL2
5_IN
AL25_OUT
LK_RCOMP
E12
H14
K
C9
A12
C8
G12
C13
E14
M16
M7
LK1
T11
P10
M10
AB37 AB38
AV22 AU22
AM12 AM13
BF18 BE18
BJ30 BG30
G24 E24
AK7 AK5
K45
H45
V47 V49
Y47
K43
F47
H47
K49
MEM_
MEM
DDR_HVREF
LA
N_SMBCLK
LA
N_SMBDATA
GPIO7
1_SMBCLK
SML
SML
1_SMBDATA
PCH_CL
PCH_CL
PCH_CL
G_A_CLKRQ#
PE
CLK_ CL
K_
CLK_ CLK_
CLK_ CLK_
CLK_
CLK_ CLK_
CLK_ CLK_
CLK_
CLK_
AL25_IN
XT XTAL25_OUT
LK_RCOMP
XC
PCI_
TCM
SIO
_14M
PCI_
TPM
JETWAY_14M
SMBCLK
_SMBDATA
_RST_PCH
4
_CLK1
_DATA1
_RST1#
CPU_DMI# CPU_DMI
CPU_DPLL# CPU_DPLL
BUF_DMI# BUF_DMI
BUF_BCLK
BUF_DOT96# BUF_DOT96
BUF_CKSSCD# BUF_CKSSCD
PCH_14M
PCI_LOOPBACK
ERT# / GPIO11
SMBAL
L0ALERT# / GPIO60
SM
SMBUSController
SMBUSController
1ALERT# / PCHHOT# / GPIO74
SML
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
L1CLK / GPIO58
SM
1DATA / GPIO75
SML
Link
Link
G_A_CLKRQ# / GPIO47
PE
CLKO
CLKO
CLKO
CLKO
CLKO CLKO
CLKI
CLKI
CLKI
CL
KIN_DOT_96N
CLKI
CLKI
CLKI
CLKIN_PCILOOPBACK
XC
CLKO
UTFLEX0 / GPIO64
CLKO
UTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
UT_PEG_A_N UT_PEG_A_P
CLKI
RE
XT
2
SMBCLK
MEM_
MEM
_SMBDATA
DDR_HVREF
N_SMBCLK 32
LA
LA
N_SMBDATA 32
S
L1_SMBCLK 43
M
L1_SMBDATA 43
SM
Intel review feed back
PC
H_CL_CLK1 37
H_CL_DATA1 37
PC
_RST1# 37
PCH_CL
CPU_DMI# 7
CLK_ CLK_
CPU_DMI 7
CLK_
CPU_DPLL# 7
CLK_
CPU_DPLL 7
PCI_LOOPBACK 17
CLK_
1 2
RH
RH
100 90.9_0402_1%~D
100 90.9_0402_1%~D
311 22_0402_5%~D4@RH311 22_0402_5%~D4@
RH
313 22_0402_5%~D
313 22_0402_5%~D
RH
RH
RH
RH
314 22_0402_5%~D
314 22_0402_5%~D
RH
315 22_0402_5%~D@RH315 22_0402_5%~D@
12
12
12
12
2
_RST_PCH 7
.3V_RUN
+3
A
A
QH5
QH5
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
3
4
B
B
QH5
QH5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1 2
296 0_0402_5%~D@RH296 0_0402_5%~D@
RH
1 2
297 0_0402_5%~D@RH297 0_0402_5%~D@
RH
SM
L1_SMBCLK
SM
L1_SMBDATA
_RST_PCH
DDR_HVREF
4
GPIO7
SMBCLK
MEM_
MEM
_SMBDATA
B_ALERT#
PCH_SM
PE
G_A_CLKRQ#
ϴϮϱϳϳƌĞĨĞƌĞŶĐĞĚĞƐŝŐŶWhƚŽ нϯϯsͺ
LA
N_SMBCLK
LA
N_SMBDATA
BUF_DMI#
CLK_
BUF_DMI
CLK_
CLK_
BUF_BCLK
CLK_
BUF_DOT96# BUF_DOT96
CLK_
CLK_
BUF_CKSSCD#
CLK_
BUF_CKSSCD
CLK
_PCH_14M
74 10K_0402_5%~D
74 10K_0402_5%~D
RH
RH RH
RH
75 10K_0402_5%~D
75 10K_0402_5%~D
91 10K_0402_5%~D
91 10K_0402_5%~D
RH
RH
76 10K_0402_5%~D
76 10K_0402_5%~D
RH
RH
77 10K_0402_5%~D
77 10K_0402_5%~D
RH
RH
78 10K_0402_5%~D
78 10K_0402_5%~D
RH
RH
79 10K_0402_5%~D
79 10K_0402_5%~D
RH
RH
183 10K_0402_5%~D
183 10K_0402_5%~D
RH
RH
>K<dZD/Ed/KEĨŽƌ&/DĂŶĚŶĞĞĚĐůŽƐĞƚŽW,
RH
RH
309 0_0402_5%~D
309 0_0402_5%~D
12
RH99
RH99 1M_0402_5%~D
_RUN
+1.05V
CLK_PCI_TPM_CHA 35
SIO_14M 42
CLK_
PCI_TPM 34
CLK_
AY_CLK14M 35
JETW
1M_0402_5%~D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1
DDR_XDP_
WAN_SMBCLK 12,13,28,37
DDR_XDP_
WAN_SMBDAT 12,13,28,37
1 2
298 2.2K_0402_5%~D
298 2.2K_0402_5%~D
RH
RH
1 2
299 2.2K_0402_5%~D
299 2.2K_0402_5%~D
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
1 2 1 2
1 2
1 2 1 2
1 2 1 2
1 2
12
300 1K_0402_5%~D
300 1K_0402_5%~D
12
301 10K_0402_5%~D
301 10K_0402_5%~D
12
302 2.2K_0402_5%~D
302 2.2K_0402_5%~D
12
303 2.2K_0402_5%~D
303 2.2K_0402_5%~D
12
304 10K_0402_5%~D
304 10K_0402_5%~D
12
80 10K_0402_5%~D
80 10K_0402_5%~D
12
305 2.2K_0402_5%~D
305 2.2K_0402_5%~D
12
306 2.2K_0402_5%~D
306 2.2K_0402_5%~D
12
YH2
YH2
25MHZ_12PF_7A25000111~D
25MHZ_12PF_7A25000111~D
2
CH18
CH18
1
_0402_50V8J~D
_0402_50V8J~D
10P
10P
/PROPRIETARY
2/8)
2/8)
2/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
12
+3
.3V_ALW_PCH
+3.3V
_LAN
2
1
15 64Wedn
15 64Wedn
15 64Wedn
CH19
CH19
_0402_50V8J~D
_0402_50V8J~D
10P
10P
of
of
of
5
+3
.3V_ALW_PCH
D D
+3
.3V_RUN
C C
+1
.05V_RUN
RH
RH
RH
RH
SUSACK#42
14
B B
A A
XDP_DBRESET#7,
PM_
PCH_RSM
ME_SUS_PWR_ACK43
SIO
SIO
+3
DRAM_PWRGD7
PWROK7,42
SYS_
RESET_O
PM_
APWROK43
RST#14,43
_PWRBTN#_R7,14
_PWRBTN#43
RESENT43
AC_P
.3V_ALW_PCH
UT#43
1 2
318 10K_0402_5%~D@RH318 10K_0402_5%~D@
RH
1 2
RH
RH
144 10K_0402_5%~D
144 10K_0402_5%~D
1 2
RH
RH
142 10K_0402_5%~D
142 10K_0402_5%~D
1 2
RH
319 10K_0402_5%~D@RH319 10K_0402_5%~D@
1 2
140 10K_0402_5%~D
140 10K_0402_5%~D
RH
RH
1 2
137 8.2K_0402_5%~D
137 8.2K_0402_5%~D
RH
RH
DMI
_CTX_PRX_N06 _CTX_PRX_N16
DMI DMI
_CTX_PRX_N26 _CTX_PRX_N36
DMI
DMI
_CTX_PRX_P06 _CTX_PRX_P16
DMI DMI
_CTX_PRX_P26 _CTX_PRX_P36
DMI
_CRX_PTX_N06
DMI
_CRX_PTX_N16
DMI
_CRX_PTX_N26
DMI DMI
_CRX_PTX_N36
_CRX_PTX_P06
DMI
_CRX_PTX_P16
DMI
_CRX_PTX_P26
DMI DMI
_CRX_PTX_P36
1 2
111 49.9_0402_1%~D
111 49.9_0402_1%~D
1 2
112 750_0402_1%~D
112 750_0402_1%~D
1 2
RH
114 0_0402_5%~D@RH114 0_0402_5%~D@
1 2
116 0_0402_5%~D
116 0_0402_5%~D
RH
RH
1 2
RH
RH
117 0_0402_5%~D
117 0_0402_5%~D
1 2
118 0_0402_5%~D
118 0_0402_5%~D
RH
RH
1 2
320 0_0402_5%~D
320 0_0402_5%~D
RH
RH
1 2
120 0_0402_5%~D
120 0_0402_5%~D
RH
RH
1 2
RH
RH
121 0_0402_5%~D
121 0_0402_5%~D
1 2
RH
RH
139 8.2K_0402_5%~D
139 8.2K_0402_5%~D
5
SUS_STAT#
E
_SUS_PWR_ACK
M
PCH_PCI
SIO
PCH_RI
CLKRUN#
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI
_COMP_R
CPY
RBIAS_
PM_
ME
1 2
122 0_0402_5%~D
122 0_0402_5%~D
RH
RH
/LPCPD#
E_WAKE#
_SLP_LAN#
#
_CTX_PRX_N0 _CTX_PRX_N1 _CTX_PRX_N2 _CTX_PRX_N3
_CTX_PRX_P0 _CTX_PRX_P1 _CTX_PRX_P2 _CTX_PRX_P3
_CRX_PTX_N0 _CRX_PTX_N1 _CRX_PTX_N2 _CRX_PTX_N3
_CRX_PTX_P0 _CRX_PTX_P1 _CRX_PTX_P2 _CRX_PTX_P3
SUSACK#_
XDP_DBRESET#
SYS_
PWROK_R
PCH_PW
PM_
APWROK_R
DRAM_PWRGD_R
PCH_RSM
RST#_R
_SUS_PWR_ACK_R
_PWRBTN#_R
_PWRBTN#_R
SIO
SIO
AC_P
RESENT
OW#
PCH_BATL
#
PCH_RI
PCH_DPW
RESET_O
_SUS_PWR_ACK_R
ME
PCH_RSM
ME
_SUS_PWR_ACK
UH4C
UH4C
BC24
0RXN
DMI
BE20
1RXN
DMI
BG18
2RXN
DMI
BG20
DMI
3RXN
BE24
DMI
0RXP
BC20
1RXP
DMI
BJ18
DMI
2RXP
BJ20
3RXP
DMI
AW24
DMI
0TXN
AW20
1TXN
DMI
BB18
DMI
2TXN
AV18
3TXN
DMI
AY24
DMI
0TXP
AY20
DMI
1TXP
AY18
2TXP
DMI
AU18
3TXP
DMI
BJ24
DMI
_ZCOMP
BG25
DMI
_IRCOMP
BH21
2RBIAS
DMI
R
C12
SUSACK#
K3
SYS_
RESET#
P12
SYS_
PWROK
ROK
L22
PWRO
L10
APWRO
B13
DRAMP
C21
RSMRST#
K16
SUSWARN#
0
E2
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BA
TLOW# / GPIO72
0
A1
RI#
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
ROK
UT#
RST#
K
WROK
4
1 2
RH
RH
113 0_0402_5%~D
113 0_0402_5%~D
1 2
321 0_0402_5%~D@RH321 0_0402_5%~D@
RH
1 2
RH
RH
323 0_0402_5%~D
323 0_0402_5%~D
1 2
322 10K_0402_5%~D
322 10K_0402_5%~D
RH
RH
1 2
RH
145 10K_0402_5%~D@RH145 10K_0402_5%~D@
K
/SUSPWRDNACK/GPIO30
4
RST#_R
PCH_RSM
SYS_
PWROK
R
SUSACK#_
FDI_
BJ14
I_RXN0
FD
I_RXN1
FD
I_RXN2
FD FD
I_RXN3 I_RXN4
FD FD
I_RXN5 I_RXN6
FD FD
I_RXN7
RXP0
FDI_ FDI_
RXP1 RXP2
FDI_ FDI_
RXP3 RXP4
FDI_ FDI_
RXP5
FDI_
FDI
FDI
FDI
FDI
FDI
FDI
DSWV
CLKRUN#
SUSCLK
S5# / GPIO63
SLP_
_LAN# / GPIO29
SLP
RXP6
FDI_
RXP7
FDI
_INT
_FSYNC0
_FSYNC1
_LSYNC0
_LSYNC1
RMEN
DPWR
WAKE#
/ GPIO32
/ GPIO61
/ GPIO62
SLP_S4#
SLP_
SLP_
SLP_SUS#
PMSY
NCH
OK
S3#
A#
DMI
DMI
SUS_STAT#
System Power Management
System Power Management
AY14 BE14 BH13 BC12 BJ12 BG10 BG9
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DSWO
FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_
FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_
FD
I_INT
FDI
FDI
FDI
FDI
DVREN
PCH_DPW
PCH_PCI
CLKRUN#
SUS_STAT#
SUSCLK
_SLP_S5#
SIO
SIO
_SLP_S4#
_SLP_S3#
SIO
_SLP_A#
SIO
SIO
_SLP_SUS#
_SYNC
H_PM
_SLP_LAN#
SIO
3
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: RH127 STUFFED, RH129 UNSTUFFED
Disabled
LOW: RH129 STUFFED, RH127 UNSTUFFED
CTX_PRX_N0 CTX_PRX_N1 CTX_PRX_N2 CTX_PRX_N3 CTX_PRX_N4 CTX_PRX_N5 CTX_PRX_N6 CTX_PRX_N7
CTX_PRX_P0 CTX_PRX_P1 CTX_PRX_P2 CTX_PRX_P3 CTX_PRX_P4 CTX_PRX_P5 CTX_PRX_P6 CTX_PRX_P7
_FSYNC0
_FSYNC1
_LSYNC0
_LSYNC1
RH
RH
127 330K_0402_1%~D
127 330K_0402_1%~D
129 330K_0402_1%~D@RH129 330K_0402_1%~D@
RH
ROK
E_WAKE#
/LPCPD#
1 2
1 2
PCH_DPW
PCH_PCI
CLKRUN#
T56
T56
T57
T57
T58
T58
_SLP_S5# 43
SIO
T59 PAD~DT59 PAD~D
SIO_SLP_S4# 42
T60
T60
SIO
_SLP_S3# 42
T61
T61
_SLP_A# 42,51
SIO
T62 PAD~DT62 PAD~D
SIO_SLP_SUS# 42
T63
T63
H_PM_SYNC 7
O_SLP_LAN# 32,42
SI
FDI_
CTX_PRX_N0 6 CTX_PRX_N1 6
FDI_ FDI_
CTX_PRX_N2 6 CTX_PRX_N3 6
FDI_ FDI_
CTX_PRX_N4 6
FDI_
CTX_PRX_N5 6 CTX_PRX_N6 6
FDI_ FDI_
CTX_PRX_N7 6
FDI_
CTX_PRX_P0 6 CTX_PRX_P1 6
FDI_
CTX_PRX_P2 6
FDI_
CTX_PRX_P3 6
FDI_ FDI_
CTX_PRX_P4 6
FDI_
CTX_PRX_P5 6 CTX_PRX_P6 6
FDI_
CTX_PRX_P7 6
FDI_
I_INT 6
FD
FDI
_FSYNC0 6
FDI
_FSYNC1 6
_LSYNC0 6
FDI
FDI
_LSYNC1 6
ROK 42
E_WAKE# 42
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
3
35,42,43
+3
.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
RH31
RH31
RH316
RH316
7
7
CLK_DDC2
G_
.3V_RUN
PANEL_ ENVDD_PCH
BIA_
LDDC_ LDDC_
2.37K_0402_1%~D
2.37K_0402_1%~D
LCD_ LCD_
LCD_ LCD_ LCD_
LCD_ LCD_ LCD_
2
5
4
PWM_PCH
LVD
_IBG
ACLK-_PCH ACLK+_PCH
A0-_PCH A1-_PCH A2-_PCH
A0+_PCH A1+_PCH A2+_PCH
+3
G_
DAT_DDC2
PANEL_
BKEN_PCH24
ENVDD_PCH24,
42
BIA_
PWM_PCH24
CLK_PCH24
LDDC_ LDDC_
DATA_PCH24
RH
RH
125
125
1 2
Minimum speacing of 20mils for LVD_IBG
ACLK-_PCH24
LCD_
ACLK+_PCH24
LCD_
LCD_
A0-_PCH24
LCD_
A1-_PCH24 A2-_PCH24
LCD_
LCD_
A0+_PCH24 A1+_PCH24
_CELL
LCD_ LCD_
A2+_PCH24
+RTC
13" support one channel LVDS
PCH_CRT
_BLU25
PCH_CRT PCH_CRT PCH_CRT
_HSYNC25
PCH_CRT PCH_CRT
_VSYNC25
1 2
RH
RH
131 150_0402_1%~D
131 150_0402_1%~D
1 2
RH
RH
132 150_0402_1%~D
132 150_0402_1%~D
1 2
RH133 150_0402_1%~DRH133 150_0402_1%~D
1 2
RH134 100K_0402_5%~DRH134 100K_0402_5%~D
PCH_CRT
_GRN25
PCH_CRT
_RED25
CLK_DDC2
G_ G_DAT_DDC2
RH
RH
123 20_0402_1%~D
123 20_0402_1%~D
1 2 1 2
124 20_0402_1%~D
124 20_0402_1%~D
RH
RH
RH
RH
1K_0402_0.5%~D
1K_0402_0.5%~D
_BLU
PCH_CRT
PCH_CRT
_GRN
PCH_CRT
_RED
ENVDD_PCH
HSYN VSYNC
126
126
12
2
NO CO
NNECT FOR DISCRETE
CONNE
CT FOR UMA
PCH_CRT
61
A
A
QH6
QH6
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
B
B
QH6
QH6 DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PCH_CRT
3
In
BKEN_PCH
CLK_PCH DATA_PCH
_BLU _GRN _RED
C
CRT_
IREF
2
M45
AF37 AF36
AE48 AE47
AK39 AK40
AN48 AM47 AK47
AJ48
AN47 AM49 AK49
AJ47
AF40 AF39
AH45 AH47 AF49 AF45
AH43 AH49 AF47 AF43
N48
M40
M47 M49
J47
5
P4
T40 K47
T45 P39
P49 T49
T39
T43 T42
_DDC_CLK
_DDC_DAT
PCH_CRT
PCH_CRT
_DDC_CLK 25
_DDC_DAT 25
tel request DDPB can not support eDP
UH4D
UH4D
BKLTEN
L_
VDD_EN
L_
L_BKLTCTL
DDC_CLK
L_ L_
DDC_DATA
RL_CLK
L_CT L_CT
RL_DATA
LVD
_IBG
D_VBG
LV
LV
D_VREFH
LV
D_VREFL
LV
DSA_CLK# DSA_CLK
LV
SA_DATA#0
LVD LVD
SA_DATA#1
LV
SA_DATA#2
D
SA_DATA#3
LVD
DSA_DATA0
LV LV
DSA_DATA1 DSA_DATA2
LV LV
DSA_DATA3
LV
DSB_CLK# DSB_CLK
LV
SB_DATA#0
LVD LVD
SB_DATA#1 SB_DATA#2
LVD LVD
SB_DATA#3
LV
DSB_DATA0
LV
DSB_DATA1 DSB_DATA2
LV LV
DSB_DATA3
CR
T_BLUE CRT_ CRT_
CRT_ CRT_DDC_DATA
CRT_ CRT_
DAC_IREF CRT_
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
GREEN RED
DDC_CLK
HSYNC VSYNC
IRTN
LVDS
LVDS
CRT
CRT
TVCLKINN
SDVO_
TVCLKINP
SDVO_
STALLN
SDVO_ SD
VO_STALLP
SDVO_
INTN
INTP
SDVO_
SDVO_
CTRLCLK
CTRLDATA
SDVO_
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0 DD
PB_0P DDPB_1 DD
PB_1P DDPB_
PB_2P
DD DDPB_3
PB_3P
DD
DDPC_CT
RLCLK
RLDATA
DDPC_CT
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0 DDPC_0 DDPC_1 DDPC_1 DDPC_2 DDPC_2 DDPC_3 DDPC_3
Digital Display Interface
Digital Display Interface
DDPD_CT
RLCLK
RLDATA
DDPD_CT
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0 DDPD_0 DDPD_1 DDPD_1 DDPD_2 DDPD_2P DDPD_3 DDPD_3P
DELL CONFIDENTIAL
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
Date: Sheet
Date: Sheet
Date: Sheet
1
_CTRLCLK
PCH_SDVO
PCH_SDVO
N
N
N
2
N
N P N P N P N P
N P N P N
N
AP43 AP45
AM42 AM40
AP39 AP40
P38 M39
AT4 AT4 AT4
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
P46 P42
AP4 AP4 AT3
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
M43 M36
AT45 AT4 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
_CTRLDATA
9 7 0
7 9 8
3
RH
RH
351 2.2K_0402_5%~D
351 2.2K_0402_5%~D
RH
RH
352 2.2K_0402_5%~D
352 2.2K_0402_5%~D
PC
PCH_SDVO
HDMI
TM TMDSB_ TM TMDSB_ TM TMDSB_ TM TM
PCH_DDPC_
PCH_DDPC_
DPC_PCH_ DPC_PCH_ DPC_PCH_
DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_
PCH_DDPD_
DPD_PCH_DOCK_AUX# 27 DPD_PCH_ DPD_PCH_DOCK_HPD 41
DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_LANE_P2 41 DPD_PCH_ DPD_PCH_LANE_P3 41
/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
3/8)
3/8)
3/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
12
12
H_SDVO_CTRLCLK 26
_CTRLDATA 26
B_PCH_HPD 26
DSB_PCH_N2 26
PCH_P2 26
DSB_PCH_N1 26
PCH_P1 26
DSB_PCH_N0 26
PCH_P0 26 DSB_PCH_CLK# 26 DSB_PCH_CLK 26
CTRLCLK 27
CTRLDATA 27
DOCK_AUX# 27 DOCK_AUX 27 DOCK_HPD 41
LANE_N0 41 LANE_P0 41 LANE_N1 41 LANE_P1 41 LANE_N2 41 LANE_P2 41 LANE_N3 41 LANE_P3 41
CTRLCLK 27
PCH_DDPD_
CTRLDATA 27
DOCK_AUX 27
LANE_N0 41 LANE_P0 41 LANE_N1 41 LANE_P1 41 LANE_N2 41
LANE_N3 41
16 64Wedn
16 64Wedn
16 64Wedn
of
of
of
+3
.3V_RUN
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
5
+3
.3V_RUN
PCI_
PCI_
_
PCI
PCI_
PCI_
LVD
S_CBL_DET#
CAM_
MIC_CBL_DET#
BT_D
PCH_G
PCI_
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1#
ET#
PIO3
GNT3#
1 2
H
H
324 8.2K_0402_5%~D
324 8.2K_0402_5%~D
R
D D
C C
R
1 2
325 8.2K_0402_5%~D
325 8.2K_0402_5%~D
RH
RH
1 2
RH
RH
326 8.2K_0402_5%~D
326 8.2K_0402_5%~D
1 2
RH
RH
329 8.2K_0402_5%~D
329 8.2K_0402_5%~D
1 2
RH
RH
327 10K_0402_5%~D
327 10K_0402_5%~D
1 2
330 10K_0402_5%~D
330 10K_0402_5%~D
RH
RH
1 2
RH
RH
331 10K_0402_5%~D
331 10K_0402_5%~D
1 2
RH
RH
328 10K_0402_5%~D
328 10K_0402_5%~D
1 2
332 10K_0402_5%~D@RH332 10K_0402_5%~D@
RH
12
3
@
3
@
RH33
RH33 1K_0402_5%~D
1K_0402_5%~D
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
Low = A16 swap
High = Default
PLTRST_
USH#34 MMI#36
PLTRST_ PLTRST_
XDP#7 LAN#32
PLTRST_ PLTRST_
EMB#29
ALL_INT28
HDD_F
335 0_0402_5%~D
335 0_0402_5%~D
RH
RH
1 2
336 0_0402_5%~D
336 0_0402_5%~D
RH
RH
1 2
RH337 0_0402_5%~DRH337 0_0402_5%~D
1 2
338 0_0402_5%~D
338 0_0402_5%~D
RH
RH
1 2
RH339 0_0402_5%~DRH339 0_0402_5%~D
1 2
CLK_PCI_504842
PCI_MEC43
CLK_
CLK_PCI_DOCK41
PCI_LOOPBACK15
CLK_
PCIE BT_D
CAM_
1 2
334 0_0402_5%~D
334 0_0402_5%~D
RH
RH
160 22_0402_5%~D
160 22_0402_5%~D
RH
RH RH
RH
102 22_0402_5%~D
102 22_0402_5%~D 103 22_0402_5%~D
103 22_0402_5%~D
RH
RH
1 2
105 22_0402_5%~D
105 22_0402_5%~D
RH
RH
4
UH4E
UH4E
BG2
6
TP1
6
BJ2
TP2
BH25
TP3
BJ1
6
TP4
BG1
6
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
RSVD
A# B# C# D#
Q1# / GPIO50 Q2# / GPIO52 Q3# / GPIO54
T1# / GPIO51 T2# / GPIO53 T3# / GPIO55
QE# / GPIO2 QF# / GPIO3 QG# / GPIO4 QH# / GPIO5
UT_PCI0
UT_PCI2 UT_PCI3 UT_PCI4
RSVD
PCI
PCI
B21
TP21
M20
TP22
6
AY1
TP23
BG4
6
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ3
2
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG3
2
TP32
AV26
TP33
BB26
TP34
AU28
TP35
0
AY3
TP36
AU26
TP37
6
AY2
TP38
AV28
TP39
0
AW3
TP40
PCI_
PIRQA# PIRQB#
PCI_
PIRQC#
PCI_
PIRQD#
PCI_
PCI_
REQ1# _MCARD2_DET#
_MCARD2_DET#37
ET#44
S_CBL_DET#24
LVD
MIC_CBL_DET#24
12 12
12
PCIE
ET#
BT_D
BBS_BI
T1
GNT3#
PCI_
LVD
S_CBL_DET#
PIO3
PCH_G
MIC_CBL_DET#
CAM_ FFS_PCH
T104PAD~D @T104PAD~D @
PCH_PL
I_5048
PC PCI_MEC
DOCK
PCI_
PCI_
LOOPBACKOUT
TRST#
_INT
K40
PIRQ
K38
PIRQ
H38
PIRQ
G38
PIRQ
C46
RE
C44
RE
E40
RE
D47
GN
E42
GN
F46
GN
G42
PIR
G40
PIR
C42
PIR
D44
PIR
K1
0
PME#
C6
PLTRST#
H49
CLKO
H43
CLKOUT_PCI1
J48
CLKO
K42
CLKO
H40
CLKO
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
USB
USB
3
RSVD1 RSVD2 RSVD3 RSVD4
RSVD5 RSVD6
RSVD7 RSVD8
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22
RSVD23 RSVD24
RSVD25
RSVD26 RSVD27
RSVD28 RSVD29
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5 USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
USBP10 USBP10 USBP11 USBP11 USBP12 USBP12 USBP13 USBP13
USBRBIAS#
USBRBIAS
OC
0# / GPIO59
OC
1# / GPIO40 OC2# / GPIO41 OC
3# / GPIO42 OC4# / GPIO43
OC5
# / GPIO9
6# / GPIO10
OC OC
7# / GPIO14
2
AY7 AV7 AU3 BG4
AT10 BC8
AU2 AT4 AT3 AT1
3
AY AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6
AV5
0
AV1
AT8
AY
5
BA2
2
AT1 BF3
C2
4
A2
4
USBP1-
C2
5
USBP1+
5
B2
USBP2-
6
C2
USBP2+
A2
6 8
K2 H2
8
USBP4-
8
E2
USBP4+
D2
8
USBP5-
8
C2
N
N P N P N P N P
USBP5+
8
A2
USBP6 USBP6+ USBP7­USBP7+ USBP8­USBP8+ USBP9­USBP9+ USBP10 USBP10 USBP11 USBP11 USBP12 USBP12
USBRBIAS
USB_O USB_O USB_O USB_O USB_OC4# USB_O USB_OC6# SIO
_EXT_SMI#
C0# C1# C2# C3#
C5#
-
­+
­+
­+
W
1 2
22.6_0402_1%~D
22.6_0402_1%~D
thin 500 mils
i
RH
RH
9
C2
9
B2 N2
8
8
M2 L30
0
K3 G3
0
E3
0 C30 A30 L32 K32 G32 E32 C32 A32
C3
3
3
B3
A14 K20 B17 C16 L16 A16 D14 C14
USBP1­USBP1+ USBP2­USBP2+
USBP4­USBP4+ USBP5­USBP5+ USBP6­USBP6+ USBP7­USBP7+ USBP8­USBP8+ USBP9­USBP9+ USBP10 USBP10 USBP11 USBP11 USBP12 USBP12
151
151
B_OC0# 40
US US
B_OC1# 40
_EXT_SMI# 43
SIO
39
----->Ri
ght Side
----->Right Side (ESATA)
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash H
----->US
CK
----->DO
----->DOCK
----->Express Card
----->Blue Tooth mera
----->Ca
- 38 + 38
- 44 + 44
- 24 + 24
39
40
40
37
37
37
37
37
37
34
34
41
41
41
41
C0#
USB_O
C1#
USB_O USB_O
C3#
USB_O
C4#
USB_O
C5# C6#
USB_O
C2#
USB_O
SIO_EXT_SMI#
RPH1
RPH1
4 5 3 6 2 7 1 8
10K
10K
4R_5%~D
4R_5%~D
_1206_8P
_1206_8P
RPH2
RPH2
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
1 2
164 10K_0402_5%~D
164 10K_0402_5%~D
RH
RH
.3V_ALW_PCH
+3
1
.3V_RUN
+3
A A
PCH_PL
PCH_PLTRST#
TRST#7,14
5
1
B
2
A
102
102
CH
CH
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
5
UH3
UH3
P
PCH_PL
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
TRST#_EC
PCH_PLTRST#_EC 14,35,37,38,42,43
4
BBS_BI
T1
12
342
@RH342
@
RH
1K_0402_5%~D
1K_0402_5%~D
BBS_BIT1 Boot BIOS Location
*
3
SATA_SLPD (BBS_BIT0)
00
01
10
11
LPC
Reserved (NAND)
PCI
SPI
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
4/8)
4/8)
4/8)
-6611P
-6611P
-6611P
1
17 64Wedn
17 64Wedn
17 64Wedn
of
of
of
Boot BIOS Strap
5
.3V_ALW_PCH
+3
1 2
RH
RH
355 4.7K_0402_5%~D
355 4.7K_0402_5%~D
1 2
353 1K_0402_5%~D@RH353 1K_0402_5%~D@
RH
D D
ENABLED - HIGH (RH238 UNSTUFFED) DEFAULT DISABLED - LOW (RH238 STUFFED)
+3
.3V_ALW_PCH
PLL ON DIE VR ENABLE
1 2
177 10K_0402_5%~D
177 10K_0402_5%~D
RH
RH
SLP_
SIO
_EXT_WAKE#
ME_CSW_DEV#
SIO
_EXT_SCI#
_EXT_SCI#43
SIO
PM_
RH
RH
SI
IO_L
LED
B_DET#31
SIO
_EXT_WAKE#42
LANPHY_ENABLE32
Integrated Clock Chip Enable
ICC_EN#
C C
HIGH: DISABLED [DEFAULT] LOW: ENABLED
+3
.3V_ALW_PCH
1 2
354 1K_0402_5%~D
354 1K_0402_5%~D
RH
RH
PCH_G
PIO15
PCIE
_MCARD1_DET#37
EXPRCRD_DET
SLP_
ME_CSW_DEV#42
USB_M
M
E
CARD1_DET#37
GPIO15
Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
PCH_G
5
PCH_G
PCH_G
PCH_G
PCH_G
TEM
P_ALERT#
ME
DIA_DET#
GPIO17
IO_LOOP#
B_DET#
LED
KB_DET#
PIO37
PIO36
PIO36
PIO37
PIO16
Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad.
1 2
174 10K_0402_5%~D@RH174 10K_0402_5%~D@
RH
B B
1 2
175 10K_0402_5%~D@RH175 10K_0402_5%~D@
RH
+3.3V_RUN
RH
RH
RH265 10K_0402_5%~DRH265 10K_0402_5%~D
A A
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
RH
RH
RH
RH
RH
RH
+3
.3V_ALW_PCH
12
171 10K_0402_5%~D@RH171 10K_0402_5%~D@
12
173 1K_0402_1%~D@RH173 1K_0402_1%~D@
12
12
1 2
1 2
269 8.2K_0402_5%~D
269 8.2K_0402_5%~D
1 2
163 10K_0402_5%~D
163 10K_0402_5%~D
1 2
273 10K_0402_5%~D
273 10K_0402_5%~D
12
170 10K_0402_5%~D
170 10K_0402_5%~D
RH
RH
TEMP
FFS_IN
_ALERT#42
KB_DET#44
4
1 2
263 10K_0402_5%~D
263 10K_0402_5%~D
O
_EXT_SCI#
1 2
RH
RH
259 0_0402_5%~D
259 0_0402_5%~D
PCH_G
IO_L
#38
OOP#
B_DET#
LED
_EXT_WAKE#
SIO
_LANPHY_ENABLE
PM
PCH_G
PCH_G
GPIO1
ME
DIA_DET#
IE_MCARD1_DET#
PC
EXPRCRD_DET
ME_CSW_DEV#
SLP_
PCH_G
USB_M
PCH_G
PCH_G
TPM_
TPM_
FFS_IN
P_ALERT#
TEM
KB_DET#
TPM_ID0
4
OOP#31
DIA_DET#31
T228
+3
.3V_RUN
UH4F
SI
PIO1
PIO15
PIO16
7
PIO34
CARD1_DET#
PIO36
PIO37
ID0
ID1
T2
VSS_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
O
_EXT_SCI#_R
#
1
NCTF_
2
3
4
5
6
7
8
9
10
11
12
13
14
UH4F
T7
# / GPIO0
BMBUSY
A42
TA
CH1 / GPIO1
H36
TA
CH2 / GPIO6
E38
CH3 / GPIO7
TA
C1
0
GPIO8
C4
N_PHY_PWR_CTRL / GPIO12
LA
G2
5
GPIO1
U2
P / GPIO16
SATA4G
D40
CH0 / GPIO17
TA
T5
SC
LOCK / GPIO22
E8
IO24 / MEM_LED
GP
E16
7
GPIO2
P8
8
GPIO2
K1
P_PCI# / GPIO34
ST
K4
5
GPIO3
V8
SATA2G
P / GPIO36
M5
SATA3G
P / GPIO37
N2
SL
OAD / GPIO38
M3
SDATAOUT0
V13
SDATAOUT1
V3
P / GPIO49
SATA5G
D6
7
GPIO5
A4
VSS_NCTF_
A44
VSS_NCTF_
A45
VSS_NCTF_
A46
VSS_NCTF_
A5
VSS_NCTF_
A6
VSS_NCTF_
B3
VSS_NCTF_
B47
VSS_NCTF_
BD1
VSS_NCTF_
BD49
VSS_NCTF_
BE1
VSS_NCTF_
BE49
VSS_NCTF_
BF1
VSS_NCTF_
BF49
VSS_NCTF_14
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
EĞĞĚƚŽŵŽĚŝĨLJĨŽůůŽǁdWDKDĐŽŶĨŝŐ
+3.3V_RUN
1 2
1 2
1@
1@
RH267
RH267 10K_0402_5%~D
10K_0402_5%~D
2@
2@
0
0
RH27
RH27 10K_0402_5%~D
10K_0402_5%~D
+3.3V_RUN
TPM_ID1
/ GPIO39
/ GPIO48
1
2
3
4
5
6
7
8
9
10
11
12
13
12
12
GPIO
GPIO
3@
3@
RH268
RH268 20K_0402_5%~D
20K_0402_5%~D
4@
4@
271
271
RH
RH
2.2K_0402_5%~D
2.2K_0402_5%~D
3
CH4 / GPIO68
TA
TA
CH5 / GPIO69
TA
CH6 / GPIO70
CH7 / GPIO71
TA
ATE
A20G
PECI
RCIN#
PWRGD
PROC
THRM
TRIP#
IT3_3V#
IN
TVS
DF_
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
15
VSS_NCTF_
16
VSS_NCTF_
17
VSS_NCTF_
VSS_
18
NCTF_
19
VSS_NCTF_
VSS_NCTF_
20
VSS_NCTF_
21
VSS_NCTF_
22
23
VSS_NCTF_
NCTF
NCTF
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_32
Chi
24
25
26
27
28
29
30
31
na TPM
No TPM, No China TPM
USH2.0
3
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK1
AH1
AK1
P3
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
2
NTACTL
ESS_DET#
CO
PCH_G
PIO69
PCIE
_MCARD3_DET#
CARD2_DET#
USB_M
SIO
_A20GATE
H_PECI
SIO
_RCIN#
H_CPUPW
PCH_T
HRMTRIP#_R
IT3_3V#
IN
TVS
DF_
1
0
0
NC_1
7
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_
NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
_A20GATE 43
SIO
_R
1 2
RH
159 0_0402_5%~D@RH159 0_0402_5%~D@
SIO
RGD
H_CPUPW
@
15
16
17
18
19
20
21
22
23
24
Layout note: Trace wide 10mil & length 30mil
25
All NCTF pins should have thick
26
traces at 45°from the pad.
27
28
29
30
31
32
ESS_DET# 34
CONTACTL
IE_MCARD3_DET# 37
PC
USB_M
CARD2_DET# 37
_RCIN# 43
RGD 7
T106PAD~D@T106PAD~D
T108PAD~D @T108PAD~D @
1 2
RH
RH
261 0_0402_5%~D
261 0_0402_5%~D
262 56_0402_5%~D
262 56_0402_5%~D
RH
RH
1
CH97
CH97
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
+1
.05V_RUN_VTT
12
PECI_
H_PECI
EC 43
+V
7
CCDFTERM
2.2K_0402_5%~D
2.2K_0402_5%~D
RH149
RH149
CONTACTL
_A20GATE
SIO
_RCIN#
SIO
PCH_G
PCH_G
EXPRCRD_DET
GPIO27 (EXPRCRD_DET#)
ĞĨĂƵůƚсŽŶŽƚĐŽŶŶĞĐƚ;ĨůŽĂƚŝŶŐͿ ,ŝŐŚ;ϭͿсŶĂďůĞƐƚŚĞŝŶƚĞƌŶĂůsĐĐsZDƚŽŚĂǀĞĂĐůĞĂŶ ƐƵƉƉůLJĨŽƌĂŶĂůŽŐƌĂŝůƐEŽŶĞĞĚƚŽƵƐĞ ŽŶͲďŽĂƌĚĨŝůƚĞƌĐŝƌĐƵŝƚ >Žǁ;ϬͿсŝƐĂďůĞƐƚŚĞsĐĐsZDEĞĞĚƚŽƵƐĞŽŶͲďŽĂƌĚ ĨŝůƚĞƌĐŝƌĐƵŝƚƐĨŽƌĂŶĂůŽŐƌĂŝůƐ
PCH_G
12
150 0_0402_5%~D
150 0_0402_5%~D
RH
RH
ESS_DET#
PIO1
PIO34
PIO69
1 2
1
1 2
256 10K_0402_1%~D
256 10K_0402_1%~D
RH
RH
RH
RH
158 10K_0402_5%~D
158 10K_0402_5%~D
RH
RH
203 10K_0402_5%~D
203 10K_0402_5%~D
RH
RH
254 10K_0402_5%~D
254 10K_0402_5%~D
1 2
165 10K_0402_5%~D
165 10K_0402_5%~D
RH
RH
#
1 2
241 10K_0402_5%~D
241 10K_0402_5%~D
RH
RH
1 2
RH
RH
260 1.5K_0402_1%~D
260 1.5K_0402_1%~D
DF_TVSDF_TVS_R
.3V_RUN
+3
12
12
12
DMI & FDI Termination Voltage
0
0
0
1
ID1TPM_ID0
TPM_
11
NV_CLE
DELL CONFIDENTIAL
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
Set to Vss when LOW
Set to Vcc when HIGH
/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
5/8)
5/8)
5/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
18 64Wedn
18 64Wedn
18 64Wedn
of
of
of
5
+1.05V
_RUN
10U
10U
_0805_4VAM~D
_0805_4VAM~D
1
D D
_RUN
+1.05V
50 mA
+3
.3V_RUN
+1.05V
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH51
CH51
2
C C
B B
@
@
_RUN
1
2
+1.05V
RH24
RH24
10U
10U
_0805_4VAM~D
_0805_4VAM~D
2
1 2
7
7
1
CH44
CH44
2
_RUN
RH
195 0.022_0805_1%@RH195 0.022_0805_1%@
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+1
4.555A
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH32
CH32
CH30
CH30
1
2
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
1U
1U
1
_0402_6.3V6K~D
_0402_6.3V6K~D
CH45
CH45
CH46
CH46
2
_+1.5V_1.8V_RUN
+1.05V
1 2
+1.05V
_RUN
.05V_RUN_VTT
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CH33
CH33
CH31
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+1.05V
CH47
CH47
1
2
_RUN
1
2
1
2
@
@
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+VC
CH31
+V
CH40
CH40
_0805_4VAM~D
_0805_4VAM~D
10U
10U
CH48
CH48
CAPLL_FDI
1
2
1
2
CCAPLLEXP
4
UH4G
UH4G
AA23 AC23 AD21 AD23
AF21
AF23 AG21 AG23 AG24 AG26 AG27 AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
1]
VCCCORE[ VCCCORE[
2] 3]
VCCCORE[ VCCCORE[
4]
RE[
5]
VCCCO
6]
VCCCORE[ VCCCORE[
7] 8]
VCCCORE[ VCCCORE[
9] 10]
VCCCORE[
11]
VCCCORE[ VCCCORE[
12]
VCCCORE[
13]
VCCCORE[
14] 15]
VCCCORE[
16]
VCCCORE[ VCCCORE[
17]
VCCIO
[28]
EXP
VCCAPLL
[15]
VCCIO
[16]
VCCIO
[17]
VCCIO
[18]
VCCIO
[19]
VCCIO
[20]
VCCIO
[21]
VCCIO
VCCIO
[22]
VCCIO
[23]
VCCIO
[24]
[25]
VCCIO
VCCIO
[26]
C3_3[3]
VC
2]
VCCVRM[
VccA
FDIPLL
VCCIO
[27]
[2]
VCCDMI
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
POWER
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
VCCTX_
VCCTX_
VCCTX_
VCCTX_
DMI
DMI
VCCDFT
VCCDFT
VCCDFT
VCCDFT
DFT / SPI HVCMOS
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALV
VSSALVDS
LVDS[1]
LVDS[2]
LVDS[3]
LVDS[4]
VC
C3_3[6]
VC
C3_3[7]
VCCVRM[
VCCDMI
VCCCLKDM
ERM[1]
ERM[2]
ERM[3]
ERM[4]
VCCSPI
3
.3V_RUN
+3
LH1
+V
CCADAC
0.
0.
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
01U_0402_16V7K~D
U48
U47
AK36
DS
7
AK3
AM37
AM38
AP36
AP37
V33
V34
AT16
3]
AT20
[1]
AB36
I
AG16
AG17
AJ16
AJ17
V1
01U_0402_16V7K~D
1
1
CH34
CH34
2
2
+1
.8V_RUN_LVDS
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH
CH
1
103
103
2
1
CH43
CH43
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
+1.05V
CH
CH
49 1U_0402_6.3V6K~D
49 1U_0402_6.3V6K~D
1 2
+1
.05V_RUN_CLKDMI
10U_0603_4VAM~D
CH50
CH50
1
2
1
CH52
CH52
0.
0.
2
1
2
10U_0603_4VAM~D
@
@
1
CH
CH 106
106
2
1U_0402_10V7K~D
1U_0402_10V7K~D
+3.3
CH54
CH54
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH35
CH35
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
2
+3
_+1.5V_1.8V_RUN
100N
100N
CCDFTERM
+V
V_M
LH1
12
LM18PG181SN1_0603~D
LM18PG181SN1_0603~D
B
B
10U
10U
_0805_4VAM~D
_0805_4VAM~D
1
CH36
CH36
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH
CH
CH
CH
1
104
104
105
105
2
.3V_RUN
1 2
H_HK1608R10J-T_5%_0603~D
H_HK1608R10J-T_5%_0603~D
1 2
RH
276 0_0805_5%~D@RH276 0_0805_5%~D@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
.3V_RUN
+3
100N
100N
H_HK1608R10J-T_5%_0603~D
H_HK1608R10J-T_5%_0603~D
LH9
LH9
2
2
PJP5
PJP5
LH8
LH8
12
+1
.05V_RUN_VTT
_RUN
+1.05V
+3
.3V_RUN
.8V_RUN
+1
+1
2
.8V_RUN
1
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax Current (A)
0.001
5
5
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
1.05VccIO 2.925
VccASW
VccSPI
VccDSW3_3 0.003
1.05
3.3
3.3
1.01
0.020
1.8 0.19+VCCDFTERM
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
VccVRM 1.8 / 1.5
0.119
0.01
0.16
1.05VccClkDMI 0.02
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.06
+1.05V
_+1.5V_1.8V_RUN
+1.05V_RUN
1
+
+
@
@
CH41
CH41
_D2_2VM_R6M~D
_D2_2VM_R6M~D
330U
330U
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
+
+
2
@
@
CH42
CH42
_D2_2VM_R6M~D
_D2_2VM_R6M~D
330U
330U
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
LA
/PROPRIETARY
6/8)
6/8)
6/8)
-6611P
-6611P
-6611P
1
19 64Wedn
19 64Wedn
19 64Wedn
of
of
of
_RUN
/ŶƚĞůƌĞǀŝĞǁĨĞĞĚďĂĐŬ
12
197 0_0603_5%~D
197 0_0603_5%~D
RH
RH
12
198 0_0603_5%~D@RH198 0_0603_5%~D@
RH
RH199 0_0603_5%~D@RH199 0_0603_5%~D@
12
4
.5V_RUN
+1
+1
.8V_RUN
+1.05V
A A
5
5
_RUN
+1.05V
.3V_ALW_PCH
+3
+3
.3V_ALW2
D D
.05V_RUN
+1
.3V_RUN
+3
LH4
LH4
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
C C
+1
.05V_RUN_VCCA_A_DPL
LH6
LH6
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
.05V_RUN
+1
B B
+1.05V_M
A A
1 2
1 2
LH7
LH7
10U
10U
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
1 2
RH
248 0.022_0805_1%@RH248 0.022_0805_1%@
1 2
RH
RH
201 0_0402_5%~D
201 0_0402_5%~D
1 2
H
H
253 0_0402_5%~D@
253 0_0402_5%~D@
R
R
@
@
LH3
LH3
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
+3
.3V_RUN_VCC_CLKF33
1
CH73
CH73
2
1 2
279 0_0805_5%~D@RH279 0_0805_5%~D@
RH
220U
220U
1
_B2_2.5VM_R35M~D
_B2_2.5VM_R35M~D
CH94
CH94
+
+
2
_M_VCCSUS
+1.05V
+1
5
@
@
10U
10U
CH5
CH5
_0805_6.3V6M~D
_0805_6.3V6M~D
8
8
1
CH74
CH74
2
_0402_6.3V6K~D
_0402_6.3V6K~D
_0805_6.3V6M~D
_0805_6.3V6M~D
1U
1U
10U
10U
+1
.05V_RUN_VCCA_B_DPL
.05V_RUN_VCCA_A_DPL
+1
.05V_RUN_VCCA_B_DPL
+1
220U
220U
1U
1U
1
_0402_6.3V6K~D
_0402_6.3V6K~D
_B2_2.5VM_R35M~D
_B2_2.5VM_R35M~D
CH92
CH92
1
+
+
2
2
+1.05V
.05V_RUN_VTT
4.
4.
1
7U_0603_6.3V6K~D
7U_0603_6.3V6K~D
CH85
CH85
2
1
.05V_RUN
+1
2
+1.05V
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH95
CH95
CH93
CH93
1
2
_RUN
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH96
CH96
1
2
0.
0.
0.
0.
1
1
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
CH86
CH86
2
2
CH87
CH87
_M
1
2
1 2
RH
200 0.022_0805_1%@RH200 0.022_0805_1%@
1
CH5
CH5
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH67
CH67
1
2
1
2
CH79
CH79 1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
5
5
CH57
CH57
@
@
22U
22U
_0805_6.3VAM~D
_0805_6.3VAM~D
CH64
CH64
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH68
CH68
1
2
CH78
CH78
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
CH81
CH81
1 2
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
CH84
CH84
1
2
4
1
2
1
@
@
CH61
CH61
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
2
22U
22U
_0805_6.3VAM~D
_0805_6.3VAM~D
CH65
CH65
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH69
CH69
1
2
+1.05V
+1
.05V_RUN_VCCA_A_DPL
+1
.05V_RUN_VCCA_B_DPL
+VCCSST
+1
.05V_M_VCCSUS
1
@
@
CH83
CH83
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
_CELL
+RTC
1
2
4
CCACLK
+V
CCDSW3_3
+V
+P
CH_VCCDSW
+3
.3V_RUN_VCC_CLKF33
CCAPLL_CPY_PCH
+V
CCSUS1
+V
+V
CCRTCEXT
_+1.5V_1.8V_RUN
0.
0.
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH89
CH89
CH88
CH88
2
3
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
1
CH56
CH56
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH59
CH59
2
1
CH70
CH70
_0603_10V6K~D
_0603_10V6K~D
1U
1U
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH76
CH76
2
+1.05V
POWER
C3_3[5]
[14]
[7]
POWER
_3
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
3
VC
VC
VC
CSUS3_3[10]
VC
VC
VC
VC
VC
VC
VC
VCCAPLL
VCCASW[
VCCASW[
VCCASW[21]
VCCSUSHDA
DMI2
]
1]
2]
3]
4]
5]
6]
7]
8]
9]
10]
11]
12]
13]
14]
Clock and Miscellaneous
Clock and Miscellaneous
15]
16]
17]
[
18]
19]
20]
4]
A
B
FCLKN[1] FCLKN[2] FCLKN[3]
] ]
C_IO
CPURTC
CPURTC
VCCIO
O
VCCI
VCCIO
VCCIO
VCCIO
CSUS3_3[7]
CSUS3_3[8]
CSUS3_3[9]
CSUS3_3[6]
VCCIO
V5REF_
DCPSUS[4
CSUS3_3[1]
V5REF
CSUS3_3[2]
CSUS3_3[3]
CSUS3_3[4]
CSUS3_3[5]
C3_3[1]
VC
C3_3[8]
VC
C3_3[4]
VC
VC
C3_3[2]
VCCIO
VCCIO
VCCIO
VCCIO
SATA
VCCVRM[
VCCIO
VCCIO
VCCIO
SUS
N26
[29]
P26
[30]
P28
[31]
T27
[32]
T29
[33]
T23
T24
V23
V24
P24
T26
[34]
+P
CH_V5REF_SUS
M26
+V
CCA_USBSUS
AN23
]
AN24
CH_V5REF_RUN
+P
4
P3
N20
N22
P20
P22
AA16
W16
T34
.3V_RUN
+3
AJ2
AF13
[5]
AH13
[12]
AH14
[13]
AF14
[6]
AK1
AF11
1]
AC16
[2]
AC17
[3]
AD17
[4]
T21
22]
V21
23]
T19
P32
+1.05V
+1.05V
_M
.3V_ALW_PCH
+3
_+1.5V_1.8V_RUN
1
CH91
CH91
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
UH4J
UH4J
9
AD4
VCCACLK
T16
VCCDSW3
V1
2
DCPSUSBYP
T38
VC
BH23
VCCAPLL
AL29
VCCIO
AL24
DCPSUS[3
AA19
VCCASW[
AA21
VCCASW[
AA24
VCCASW[
AA26
VCCASW[
AA27
VCCASW[
AA29
VCCASW[
AA31
VCCASW[
AC26
VCCASW[
AC27
VCCASW[
AC29
VCCASW[
AC31
VCCASW[
AD29
VCCASW[
AD31
VCCASW[
W21
VCCASW[
W23
VCCASW[
W24
VCCASW[
W26
VCCASW
W29
VCCASW[
W31
VCCASW[
W33
VCCASW[
N1
6
DCPRTC
Y49
VCCVRM[
BD47
VCCADPLL
BF47
VCCADPLL
AF17
VCCIO
AF33
VCCDIF
AF34
VCCDIF
AG34
VCCDIF
AG3
3
VCCSSC
V16
DCPSST
T17
DCPSUS[1
V19
DCPSUS[2
BJ8
V_PRO
2
A2
VCCRTC
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
1
CH90
CH90
2
_RUN
.3V_ALW_PCH
+3
+
.3V_ALW_PCH
3
+3
.3V_RUN
+1.05V
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH60
CH60
2
1
CH66
CH66
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
1
CH72
CH72
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
1
CH75
CH75
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
2
_RUN
1
CH77
CH77 1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
2
+V
CCSATAPLL
1
CH80
CH80 10U
10U
_0805_6.3V6M~D
_0805_6.3V6M~D
2
1
CH82
CH82
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
2
2
.3V_ALW_PCH
+3
@
@
+1.05V
.3V_ALW_PCH
+3
.3V_RUN
+3
+1.05V
1
2
2
RH20
RH20
0_0402_5%~D
0_0402_5%~D
1 2
D
D
1 3
QH4
QH4
@
@
+3
RB
RB
751S40T1_SOD523-2~D
751S40T1_SOD523-2~D
CH_V5REF_SUS
+P
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
CCA_USBSUS
+V
RB
RB
751S40T1_SOD523-2~D
751S40T1_SOD523-2~D
+P
CH_V5REF_RUN
1U
1U
_0603_10V6K~D
_0603_10V6K~D
G
G
2
.3V_ALW_PCH+5V_ALW_PCH
+1.05V
_RUN
_RUN
V_ALW
+5
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
_ENABLE45
ALW
@
@
LH5
LH5
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
+5
S
S
1
CH98
CH98
2
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
21
DH2
DH2
1
CH63
CH63
2
1
@
@
2
+3
.3V_RUN+5V_RUN
21
DH3
DH3
1
CH71
CH71
2
_RUN
7/8)
7/8)
7/8)
PCH (
PCH (
PCH (
-6611P
-6611P
-6611P
1
V_ALW_PCH
12
12
CRB 0.7 10ohm 0603 trace width 20mil.
CH62
CH62
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
12
/PROPRIETARY
278
278 RH
RH
@
@
20K_0402_5%~D
20K_0402_5%~D
RH
RH
208
208
10_0402_5%~D
10_0402_5%~D
RH
RH
213
213
10_0402_5%~D
10_0402_5%~D
20 64Wedn
20 64Wedn
20 64Wedn
of
of
of
5
UH4H
UH4H
H5
]
VSS[0
AA17
1
]
VSS[
AA2
]
D D
C C
B B
A A
VSS[2
AA3
VSS[3
]
AA33
]
VSS[4
AA34
VSS[5
]
AB11
]
VSS[6
AB14
]
VSS[7
AB39
VSS[8
]
AB4
VSS[9
]
AB43
VSS[1
0]
AB5
1]
VSS[1
AB7
2]
VSS[1
AC19
VSS[1
3]
AC2
VSS[1
4]
AC21
5]
VSS[1
AC24
6]
VSS[1
AC33
VSS[1
7]
AC34
8]
VSS[1
AC48
VSS[1
9]
AD10
0]
VSS[2
AD11
1]
VSS[2
AD12
VSS[2
2]
AD13
3]
VSS[2
AD19
4]
VSS[2
AD24
5]
VSS[2
AD26
VSS[2
6]
AD27
7]
VSS[2
AD33
8]
VSS[2
AD34
9]
VSS[2
AD36
0]
VSS[3
AD37
VSS[3
1]
AD38
2]
VSS[3
AD39
VSS[3
3]
AD4
4]
VSS[3
AD40
VSS[3
5]
AD42
6]
VSS[3
AD43
7]
VSS[3
AD45
VSS[3
8]
AD46
9]
VSS[3
AD8
VSS[4
0]
AE2
1]
VSS[4
AE3
VSS[4
2]
AF10
VSS[4
3]
AF12
VSS[4
4]
AD14
5]
VSS[4
AD16
6]
VSS[4
AF16
VSS[4
7]
AF19
8]
VSS[4
AF24
VSS[4
9]
AF26
0]
VSS[5
AF27
VSS[5
1]
AF29
VSS[
2]
5
AF31
3]
VSS[5
AF38
4]
VSS[5
AF4
5]
VSS[5
AF42
VSS[5
6]
AF46
7]
VSS[5
AF5
VSS[5
8]
AF7
9]
VSS[5
AF8
VSS[6
0]
AG19
VSS[6
1]
AG2
2]
VSS[6
AG31
VSS[6
3]
AG48
4]
VSS[6
AH11
VSS[6
5]
AH3
6]
VSS[6
AH36
VSS[6
7]
AH39
VSS[6
8]
AH40
VSS[6
9]
AH42
VSS[7
0]
AH46
1]
VSS[7
AH7
VSS[7
2]
AJ19
3]
VSS[7
AJ21
VSS[7
4]
AJ24
5]
VSS[7
AJ33
VSS[7
6]
AJ34
7]
VSS[7
AK12
VSS[7
8]
AK3
VSS[7
9]
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
4
AK38
8
0]
VSS[
AK4
1]
VSS[8
AK42
VSS[8
2]
AK46
3]
VSS[8
AK8
VSS[8
4]
AL16
5]
VSS[8
AL17
6]
VSS[8
AL19
VSS[8
7]
AL2
VSS[8
8]
AL21
VSS[8
9]
AL23
0]
VSS[9
AL26
1]
VSS[9
AL27
VSS[9
2]
AL31
VSS[9
3]
AL33
4]
VSS[9
AL34
5]
VSS[9
AL48
VSS[9
6]
AM11
7]
VSS[9
AM14
VSS[9
8]
AM36
9]
VSS[9
AM39
00]
VSS[1
AM43
VSS[1
01]
AM45
02]
VSS[1
AM46
03]
VSS[1
AM7
04]
VSS[1
AN2
VSS[1
05]
AN29
06]
VSS[1
AN3
07]
VSS[1
AN31
08]
VSS[1
AP12
09]
VSS[1
AP19
VSS[1
10]
AP28
11]
VSS[1
AP30
VSS[1
12]
AP32
13]
VSS[1
AP38
VSS[1
14]
AP4
15]
VSS[1
AP42
16]
VSS[1
AP46
VSS[1
17]
AP8
18]
VSS[1
AR2
VSS[1
19]
AR48
20]
VSS[1
AT11
VSS[1
21]
AT13
VSS[1
22]
AT18
VSS[1
23]
AT22
24]
VSS[1
AT26
25]
VSS[1
AT28
VSS[1
26]
AT30
27]
VSS[1
AT32
VSS[1
28]
AT34
29]
VSS[1
AT39
VSS[1
30]
AT42
VSS[
31]
1
AT46
32]
VSS[1
AT7
33]
VSS[1
AU24
34]
VSS[1
AU30
VSS[1
35]
AV16
36]
VSS[1
AV20
VSS[1
37]
AV24
38]
VSS[1
AV30
VSS[1
39]
AV38
VSS[1
40]
AV4
41]
VSS[1
AV43
VSS[1
42]
AV8
43]
VSS[1
AW14
VSS[1
44]
AW18
45]
VSS[1
AW2
VSS[1
46]
AW22
VSS[1
47]
AW26
VSS[1
48]
AW28
VSS[1
49]
AW32
50]
VSS[1
AW34
VSS[1
51]
AW36
52]
VSS[1
AW40
VSS[1
53]
AW48
54]
VSS[1
AV11
VSS[1
55]
AY12
56]
VSS[1
AY22
VSS[1
57]
AY28
VSS[1
58]
3
UH4I
UH4I
AY4
59]
VSS[1
AY42
60]
VSS[1
AY46
61]
VSS[1
AY8
VSS[1
62]
B11
63]
VSS[1
B15
VSS[1
64]
B19
65]
VSS[1
B23
VSS[1
66]
B27
1
67]
VSS[
B31
68]
VSS[1
B35
VSS[1
69]
B39
70]
VSS[1
B7
VSS[1
71]
F45
72]
VSS[1
BB12
73]
VSS[1
BB16
VSS[1
74]
BB20
VSS[1
75]
BB22
VSS[1
76]
BB24
77]
VSS[1
BB28
78]
VSS[1
BB30
VSS[1
79]
BB38
VSS[1
80]
BB4
81]
VSS[1
BB46
82]
VSS[1
BC14
VSS[1
83]
BC18
84]
VSS[1
BC2
VSS[1
85]
BC22
86]
VSS[1
BC26
87]
VSS[1
BC32
VSS[1
88]
BC34
89]
VSS[1
BC36
90]
VSS[1
BC40
91]
VSS[1
BC42
VSS[1
92]
BC48
93]
VSS[1
BD46
94]
VSS[1
BD5
95]
VSS[1
BE22
96]
VSS[1
BE26
VSS[1
97]
BE40
98]
VSS[1
BF10
VSS[1
99]
BF12
00]
VSS[2
BF16
VSS[2
01]
BF20
02]
VSS[2
BF22
03]
VSS[2
BF24
VSS[2
04]
BF26
05]
VSS[2
BF28
VSS[2
06]
BD3
07]
VSS[2
BF30
VSS[2
08]
BF38
VSS[2
09]
BF40
VSS[2
10]
BF8
11]
VSS[2
BG17
12]
VSS[2
BG21
VSS[2
13]
BG33
14]
VSS[2
BG44
VSS[2
15]
BG8
16]
VSS[2
BH11
VSS[2
17]
BH15
VSS[
18]
2
BH17
19]
VSS[2
BH19
20]
VSS[2
H10
21]
VSS[2
BH27
VSS[2
22]
BH31
23]
VSS[2
BH33
VSS[2
24]
BH35
25]
VSS[2
BH39
VSS[2
26]
BH43
VSS[2
27]
BH7
28]
VSS[2
D3
VSS[2
29]
D12
30]
VSS[2
D16
VSS[2
31]
D18
32]
VSS[2
D22
VSS[2
33]
D24
VSS[2
34]
D26
VSS[2
35]
D30
VSS[2
36]
D32
37]
VSS[2
D34
VSS[2
38]
D38
39]
VSS[2
D42
VSS[2
40]
D8
41]
VSS[2
E18
VSS[2
42]
E26
43]
VSS[2
G18
VSS[2
44]
G20
VSS[2
45]
G26
VSS[246]
G28
VSS[2
47]
G36
VSS[248]
G48
VSS[2
49]
H12
50]
VSS[2
H18
VSS[2
51]
H22
52]
VSS[2
H24
VSS[2
53]
H26
54]
VSS[2
H30
VSS[255]
H32
VSS[2
56]
H34
VSS[257]
F3
VSS[2
58]
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
2
H46
59]
VSS[2
K18
60]
VSS[2
K26
61]
VSS[2
K39
VSS[2
62]
K46
63]
VSS[2
K7
VSS[2
64]
L18
65]
VSS[2
L2
VSS[2
66]
L20
2
67]
VSS[
L26
68]
VSS[2
L28
VSS[2
69]
L36
70]
VSS[2
L48
VSS[2
71]
M12
72]
VSS[2
P16
73]
VSS[2
M18
VSS[2
74]
M22
VSS[2
75]
M24
VSS[2
76]
M30
77]
VSS[2
M32
78]
VSS[2
M34
VSS[2
79]
M38
VSS[2
80]
M4
81]
VSS[2
M42
82]
VSS[2
M46
VSS[2
83]
M8
84]
VSS[2
N18
VSS[2
85]
P30
86]
VSS[2
N47
87]
VSS[2
P11
VSS[2
88]
P18
89]
VSS[2
T33
90]
VSS[2
P40
91]
VSS[2
P43
VSS[2
92]
P47
93]
VSS[2
P7
94]
VSS[2
R2
95]
VSS[2
R48
96]
VSS[2
T12
VSS[2
97]
T31
98]
VSS[2
T37
VSS[2
99]
T4
00]
VSS[3
W34
VSS[3
01]
T46
02]
VSS[3
T47
03]
VSS[3
T8
VSS[3
04]
V11
05]
VSS[3
V17
VSS[3
06]
V26
07]
VSS[3
V27
VSS[3
08]
V29
VSS[3
09]
V31
VSS[3
10]
V36
11]
VSS[3
V39
12]
VSS[3
V43
VSS[3
13]
V7
14]
VSS[3
W17
VSS[3
15]
W19
16]
VSS[3
W2
VSS[3
17]
W27
VSS[
18]
3
W48
19]
VSS[3
Y12
20]
VSS[3
Y38
21]
VSS[3
Y4
VSS[3
22]
Y42
23]
VSS[3
Y46
VSS[3
24]
Y8
25]
VSS[3
BG29
VSS[3
28]
N24
VSS[3
29]
AJ3
30]
VSS[3
AD47
VSS[3
31]
B43
33]
VSS[3
BE10
VSS[3
34]
BG41
35]
VSS[3
G14
VSS[3
37]
H16
VSS[3
38]
T36
VSS[3
40]
BG22
VSS[3
42]
BG24
43]
VSS[3
C22
VSS[3
44]
AP13
45]
VSS[3
M14
VSS[3
46]
AP3
47]
VSS[3
AP1
VSS[3
48]
BE16
49]
VSS[3
BC16
VSS[3
50]
BG28
VSS[3
51]
BJ28
VSS[352]
1
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
8/8)
8/8)
8/8)
-6611P
-6611P
-6611P
1
21 64Wedn
21 64Wedn
21 64Wedn
of
of
of
5
D D
C
C
WůĂĐĞƵŶĚĞƌWh
_0402_50V8J~D
_0402_50V8J~D
100P
100P
ŝŽĚĞĐŝƌĐƵŝƚĂƚWϱEϱŝƐƵƐĞĚĨŽƌƐŬŝŶƚĞŵƉƐĞŶƐŽƌĂŶĚƉůĂĐĞ ϮϳϮĐůŽƐĞƚŽYϭϰ;ƉůĂĐĞĚYϭϯĐůŽƐĞƚŽ:D/E/ϭĨŽƌttEĐĂƌĚͿ ŝŽĚĞĐŝƌĐƵŝƚĂƚWϯEϯŝƐŶƵƐĞĚĨŽƌƐĞŶƐŽƌ^KͲ/DDƚĞŵƉWůĂĐĞ YϭϰŶĞĂƌ/DDϭĂŶĚƉůĂĐĞϮϲϵĐůŽƐĞƚŽYϭϯ
C
C
1
9
@
9
@
C26
100P_0402_50V8J~D
.05V_RUN_VTT
1 2
P
P
C28
C28
100P_0402_50V8J~D
MST3904_SOT323-3~D
MST3904_SOT323-3~D
2
2
C C
B B
A A
+1
HERMTRIP#7
H_T
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C26
8
8
R39
R39
2.2K_0402_5%~D
2.2K_0402_5%~D
V_M
+3.3
12
R40
R40
8.2K_0402_5%~D
8.2K_0402_5%~D
THER
1
C280
C280
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
2
1
2
+3.3
2
B
B
Q15
Q15
5
5
MATRIP3#
12
2
V_M
12
R395
R395
8.
8.
C
C
E
E
3 1
VSET_4
6
6
R40
R40
1.4K_0402_1%~D
1.4K_0402_1%~D
ZĞƐƚсϭϰ<dƉсϵϰĚĞŐƌĞĞ
5
1
@
@
C286
C286
2
2
B
B
E
E
Q13
Q13
3 1
M
M
MBT3904WT1G_SC70-3~D
MBT3904WT1G_SC70-3~D
2K_0402_5%~D
2K_0402_5%~D
THER
MATRIP2#
1
8
8
C27
C27
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
022
2
B
B
E
E
Q12
Q12
3 1
MBT3904WT1G_SC70-3~D
MBT3904WT1G_SC70-3~D
M
M
100P
100P
1
_0402_50V8J~D
_0402_50V8J~D
@
@
C272
C272
2
7SH08FU_SSOP5~D
7SH08FU_SSOP5~D
TC
TC
POW
ůŽƐĞƚŽ
ER_SW#
4
Q14
Q14
E
E
31
M
M
MBT3904WT1G_SC70-3~D
MBT3904WT1G_SC70-3~D
B
B
2
C
C
+RTC_CELL
U10
U10
4
O
4
2
1
+5
C270
C270 2200P
2200P
V_RUN
1
2
5
P
B
A
G
3
M_DIODE1_P_4022
RE
_0402_50V7K~D
_0402_50V7K~D
RE
M_DIODE1_N_4022
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
C27
C27
1
6
6
2
C281
C281
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
1
2
1
C27
C27 2200P_0402_50V7K~D
2200P_0402_50V7K~D
2
.3V_RUN
+3
10U
10U
C305
C305
_0805_6.3V6M~D
_0805_6.3V6M~D
1
2
RE
1
1
RE
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C275
C275
2
M_DIODE3_P_4022
M_DIODE3_N_4022
C277
C277
24765_IINP55
BQ
DOCK_PWR_SW# 43
POWER_SW_IN# 43
3
AN1_VOUT
+F
_DET#
FAN1 +F
AN1_VOUT
N1_TACH_FB
FA
1
9
9
D2
C21
C21
2
2 1
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
RB751S40T1_SOD523-2~DD2RB751S40T1_SOD523-2~D
U9
U9
2
V_M
+3.3
V_M
+3.3
PCH_PWRGD#43
R389
R389
_0402_5%~D
_0402_5%~D
10K
10K
1 2
_CELL
+RTC
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
M_DIODE1_N_4022
RE
M_DIODE1_P_4022
RE
M_DIODE3_P_4022
RE
M_DIODE3_N_4022
RE
R387
R387
4.
4.
7K_0402_5%~D
7K_0402_5%~D
VSET_4022
N1_TACH_FB
FA
1_DET#
FAN
1 2
R403
R403
1 2
R391
R391
VDD_
RGD
PW
VCP2
12
4022_PW
10K_0402_5%~D
10K_0402_5%~D
3V_PWROK#
1K_0402_5%~D
1K_0402_5%~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
1
2
VDDH
3
VDDH
6
VDDL
13
RGD
VDD_PW
23
THERM
DN1/
24
DP1/
VREF_T
26
DN2/
DP4
27
DP2/
DN4
30
DP3/
DN5
29
DP5
DN3/
31
VCP
25
VIN
28
VSET
10
CH/GPIO1
TA
11
GPIO2
N
15
GP
IO3/PWM/THERMTRIP_SIO
12
WROK#
3V_P
16
RTC_
PWR3V
C4022-1-EZK-TR_QFN32_5X5~D
C4022-1-EZK-TR_QFN32_5X5~D
EM
EM
C274
C274
N1
CONN@
N1
CONN@
JFA
JFA
1
1
2
2
3
3
4
4
5
GND
6
GND
TYCO_2-1775293-4~D
TYCO_2-1775293-4~D
>ŝŶŬŽŶĞ
THERMT
THERMT
SYS_
SHDN#
POW
ER_SW#
ACAVAIL
T#/BC_IRQ#
ATF_IN
FAN_ FAN_
SMCL
K/BC_CLK
A/BC_DATA
SMDAT
ODE/XEN
ADDR_M
2
RIP2#
RIP3#
_CLR
OUT OUT
VDD
TEST1 TEST2
VSS
2
1
V_M
+3.3
_INT#_EMC4022
BC
1_DET#
FAN
FA
N1_TACH_FB
MATRIP2#
THER
17
MATRIP3#
THER
18
19
POW
ER_SW#
20
N
ACAV_I
21
_INT#_EMC4022
BC
9
5 4
8 7
1
DDR_XEN
+A
32
14 22 33
AN1_VOUT
+F
12
R390 47K
R390 47K
R404
R404 10K
10K
_0402_5%~D
_0402_5%~D
1 2
AV_IN 43,55,57
AC
_INT#_EMC4022 43
BC
BC
_CLK_EMC4022 43
BC
_DAT_EMC4022 43
+VC
C_4022
12
R39
R39
34.7K_0402_5%~D
34.7K_0402_5%~D
R385 10K
R385 10K
R402 10K
R402 10K
R431 10K
R431 10K
+VC
_0402_1%~D@
_0402_1%~D@
C_4022
12
12
12
THERM_
+RTC
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
C273
C273
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
STP# 48
_CELL
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
2
+3.3
C279
C279
V_M
22_0402_5%
22_0402_5%
12
~D
~D
1
2
R388
R388
SMSC request
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
FAN & Therm
FAN & Therm
FAN & Therm
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
al Sensor
al Sensor
al Sensor
22 64We
22 64We
22 64We
of
of
1
of
5
D D
4
3
2
1
JBI
O1
CONN@
O1
CONN@
1
C C
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
TYCO_2041070-6~D
TYCO_2041070-6~D
FP_U FP_U
SB_D­SB_D+
>ŝŶŬŽŶĞ
B B
FP_R
V_FP
+3.3
ESET# 34
1 2
R1135 0_0603_5%
R1135 0_0603_5%
1 2
R1136 0_0603_5%
R1136 0_0603_5%
V_FP
+3.3
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
C285
C285
1
ϮϴϱWůĂĐĞĐůŽƐĞƚŽ:/Kϭϭ
2
+3
.3V_RUN
~D
~D
+3
.3V_ALW
~D@
~D@
FP_U
SB_D-
U12
U12
1
GND
VCC
2
IO1
IO2
P
P
RTR5V0U2X_SOT143-4~D
RTR5V0U2X_SOT143-4~D
4
3
FP_U
SB_D+
.3V_RUN
+3
FP_U
FP_U
SBD+34
SBD-34
JBI
&ŝŶŐĞƌƉƌŝŶƚKEE
@
@
L8
L8
21SN121SQ2L_4P~D
21SN121SQ2L_4P~D
DLW
DLW
1
1
4
4
1 2
R409
R409
1 2
R410
R410
2
2
3
3
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
FP_U
FP_U
SB_D+
SB_D-
A A
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
FP Conn.
FP Conn.
FP Conn.
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
23 64We
23 64We
23 64We
of
of
1
of
5
VDS1
CONN@
VDS1
CONN@
JL
JL
45 44 43 42 41
D D
AMPHE_LVDSS05400121
AMPHE_LVDSS05400121
C C
>ŝŶŬŽŶĞ
CDVDD
+L
40
G5
39
G4
38
G3
37
G2
36
G1
35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
1
C29
C29
8
8
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DMI
C0
DMI
C_CLK
US
BP12_D-
US
BP12_D+
MIC_CBL_DET#
CAM_
294 0.
294 0.
C
C
1 2
ACLK+_PCH
LCD_ LCD_
ACLK-_PCH
A2+_PCH
LCD_ LCD_
A2-_PCH
LCD_
A1+_PCH A1-_PCH
LCD_
LCD_
A0+_PCH
LCD_
A0-_PCH
DATA_PCH
LDDC_
CLK_PCH
LDDC_
BREATH_W
TT_YELLOW_LED
BA
HITE_LED
BATT_W
+BL_P
WR_SRC
DISP_
BIA_
D
S_CBL_DET# 17
LV
HITE_LED
.3V_RUN
+3
1U_0603_50V4Z~D
1U_0603_50V4Z~D
ON
PWM_LVDS_L
1
C30
C30
4
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
CAM_
MIC_CBL_DET# 17
L83
L83
1 2
BLM
BLM
18BB221SN1D_2P~D
18BB221SN1D_2P~D
BIA_
PWM_LVDS
+3
Close to JVDS1.34,35 Close to JLVDS1.33
4
ACLK+_PCH 16
LCD_
ACLK-_PCH 16
LCD_
LCD_
A2+_PCH 16 A2-_PCH 16
LCD_
A1+_PCH 16
LCD_ LCD_
A1-_PCH 16
A0+_PCH 16
LCD_ LCD_
A0-_PCH 16
DATA_PCH 16
LDDC_ LDDC_
CLK_PCH 16
TST 42
LCD_
.3V_RUN
+3 +L
CDVDD
BREATH_W
HITE_LED 46
TT_YELLOW_LED 46
BA BATT_W
HITE_LED 46
.3V_RUN
R424 2.
R424 2.
1 2
R426 2.
R426 2.
1 2
WůĂĐĞŶĞĂƌƚŽ:>s^ϭ
2K_0402_5%~D
2K_0402_5%~D
2K_0402_5%~D
2K_0402_5%~D
LDDC_
LDDC_
DMI
DM
CLK_PCH
DATA_PCH
C0 30
IC_CLK 30
PWM_LVDS
BIA_
12
DISP_
ON
12
R1137
R1137 10K
10K
_0402_5%~D
_0402_5%~D
R1138
R1138 100K
100K
_0402_5%~D
_0402_5%~D
+C
AMERA_VDD
3
D63
D63
D68
D68
B751V-40GTE-17_SOD323-2~D
B751V-40GTE-17_SOD323-2~D
R
R
B751V-40GTE-17_SOD323-2~D
B751V-40GTE-17_SOD323-2~D
R
R D64
D64
D69
D69 R
R
B751V-40GTE-17_SOD323-2~D
B751V-40GTE-17_SOD323-2~D
R
R
B751V-40GTE-17_SOD323-2~D
B751V-40GTE-17_SOD323-2~D
21
21
21
21
LCD_
2
wer
LCD Po
+15V_A
130_0402_5%~D
130_0402_5%~D
12
R41
R41
3
3
61
2
2
40mil
1000P
1000P
_0402_50V7K~D
_0402_50V7K~D
1
C297
C297
2
+15V_A
+PW
EN_I
12
13
R_SRC
12
R423
R423
NVPWR43
LW
100K
100K
R414
R414
_0402_5%~D
_0402_5%~D
5
Q20
Q20 P
P
R422
R422 100K
100K
1 2
DTC124EU_SC70-3~D
DTC124EU_SC70-3~D
_0402_5%~D
_0402_5%~D
PWR_
+L
CDVDD
D
D MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
Q19A
Q19A
D6
D6
BKEN_PCH 16
BKEN_EC 42
2
3
BA
BA
T54CW_SOT323-3~D
T54CW_SOT323-3~D
CDPWR
EN_L
1
VCC_TEST_EN42
42
ENVDD_PCH16,
BIA_
PWM_PCH 16
PWM_EC 43
BIA_
PANEL_
PANEL_
+L
LW
CDVDD
12
R412
R412 100K
100K
_0402_5%~D
_0402_5%~D
D
D MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
3
Q19B
Q19B
4
Q21
Q21
54P-G_SSOT-6~D
54P-G_SSOT-6~D
FDC6
FDC6
S
S
4 5
G
G
3
SRC_ON
47K_0402_5%~D
47K_0402_5%~D
NVPWR
EN_I
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
4 5
D
D
Q22
Q22 S
S
D
D
1 3
1
Q18
Q18
D
D
S
S
6
2 1
G
G
3
0.
0. 1U_0402_25V4Z~D
1U_0402_25V4Z~D
1
C293
C293
2
40mil
6
2 1
1
C29
C29
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
2
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
G
G
2
FD
C654P: P CHANNAL
+3
.3V_ALW
1
C292
C292
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
2
WR_SRC
+BL_P
6
6
Panel backlight power control by EC
For Webcam
B B
+C
AMERA_VDD
S
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
10U
10U
1
1
_0805_10V4Z~D
_0805_10V4Z~D
C299
C299
C300
C300
2
2
We
bcam PWR CTRL
CCD_OFF42
A A
CCD_O
FF
2
5
V45EN_SOT23-3~D
V45EN_SOT23-3~D
PM
PM
+15V_A
G
G
S
Q23
Q23
G
G
2
LW
100K
100K
12
_0402_5%~D
_0402_5%~D
R429
R429
13
D
D
S
S
1
Q24
Q24
2
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D S
S
.3V_RUN
+3
D
D
13
3
3
C30
C30
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C301
C301
2
USBP12
USBP12
4
USBP12
+17
USBP12
-17
+
1
-
4
@
@
L10
L10
21SN121SQ2L_4P~D
21SN121SQ2L_4P~D
DLW
DLW
1
4
1 2
R427
R427
1 2
R428 0_0402_5%~DR428 0_0402_5%~D
2
2
3
3
0_0402_5%~D
0_0402_5%~D
US
BP12_D+
BP12_D-
US
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL
C
C
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
C
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
LVDS
LVDS
LVDS
& CAM Conn
& CAM Conn
& CAM Conn
LA
LA
LA
-6611P
-6611P
-6611P
24 64Wedn
24 64Wedn
24 64Wedn
1
of
of
of
2
B B
1
VGA S
A A
W for MB/DOCK
PCH_CRT
_VSYNC16 _HSYNC16
PCH_CRT
PCH_CRT
_RED16 _GRN16
PCH_CRT PCH_CRT
_BLU16
PCH_CRT
_DDC_DAT16 _DDC_CLK16
PCH_CRT
SWITCH42
CRT_
SEL1
/SEL2
0
1
Chanel
A=B2
Sourc
MBA=B1
APR/SPR
PCH_CRT PCH_CRT PCH_CRT PCH_CRT PCH_CRT
CRT_
PCH_CRT PCH_CRT
CRT_
e
SWITCH
SWITCH
_VSYNC _HSYNC _RED _GRN _BLU
_DDC_DAT _DDC_CLK
U14
U14
1
A0
2 5 6 7
8
9
10
30
3 11 28 31 33
VDD
A1
VDD
A2
VDD
A3
VDD
A4
VDD
0B1
SEL1
1B1 2B1 3B1
A5
4B1
A6
5B1 6B1
SEL2
0B2 1B2
GND
2B2 3B2
GND
4B
GN
D
GND
5B2 6B2
GPAD
I3V712-AZLEX_TQFN32_6X3~D
I3V712-AZLEX_TQFN32_6X3~D
P
P
+3
.3V_RUN
4 16 23 29 32
27 25 22 20 18 12 14
26 24 21 19 17
2
13 15
VSYNC_ HSYNC_ RED_CRT GR
EEN_CRT BLUE_ DAT_
DDC2_CRT
CLK_
DDC2_CRT
VSYNC_ HSYNC_ RED_DO GRE
EN_DOCK
BLUE_
DDC2_DOCK
DAT_ CL
DDC2_DOCK
K_
1
2
BUF
CRT
DOCK
DOCK
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
BUF
DOCK CK
C316
C316
BUF 31
VSYNC_ HSYNC_
BUF 31
RED_CRT
31
EEN_CRT 31
GR BLUE_
CRT 31
DDC2_CRT 31
DAT_ CLK_
DDC2_CRT 31
DOCK 41
VSYNC_ HSYNC_
DOCK 41
RED_DO
CK 41
EN_DOCK 41
GRE
DOCK 41
BLUE_
DDC2_DOCK 41
DAT_ CLK_
DDC2_DOCK 41
.3V_RUN
+3
0.
0.
0.
0.
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C317
C317
2
0.
01U_0402_16V7K~D
01U_0402_16V7K~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
1
C318
C318
C319
C319
2
2
0.
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D 01U_0402_16V7K~D
01U_0402_16V7K~D
1
1
C321
C321
C320
C320
2
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
1
Date: Sheet
o
CR
CR
CR
T switch
T switch
T switch
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
25 64Wedn
25 64Wedn
25 64Wedn
of
of
of
2
1 2
R451
R451
0_0402_5%~D@
0_0402_5%~D@
L19
TM
C352 0.
TM
DSB_PCH_CLK16
DSB_PCH_CLK#16
TM
.3V_RUN
+3
_CEC
HDMI
DSB_PCH_C_P2
TM TM
DSB_PCH_C_N2
TM
B B
DSB_PCH_C_P1
TM
DSB_PCH_C_N1 DSB_PCH_C_P0
TM
DSB_PCH_C_N0
TM TM
DSB_PCH_C_CLK DSB_PCH_C_CLK#
TM
R1165 10K
R1165 10K
R449 680_0402_5%
R449 680_0402_5% R448 680_0402_5%
R448 680_0402_5% R450 680_0402_5%
R450 680_0402_5% R452 680_0402_5%
R452 680_0402_5% R453 680_0402_5%
R453 680_0402_5% R454 680_0402_5%
R454 680_0402_5% R455 680_0402_5%
R455 680_0402_5% R456 680_0402_5%
R456 680_0402_5%
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
+3
.3V_RUN
12
_0402_5%~D
_0402_5%~D
~D
~D ~D
~D ~D
~D ~D
~D ~D
~D ~D
~D ~D
~D ~D
~D
2
G
G
13
D
D
Q26
Q26
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
S
S
TMDSB_
DSB_PCH_N016
TM
TMDSB_
TM
DSB_PCH_N116
TMDSB_
DSB_PCH_N216
TM
PCH_P016
PCH_P116
PCH_P216
C352 0.
C353 0.
C353 0.
C350 0.
C350 0.
C351 0.
C351 0.
C348 0.
C348 0.
C349 0.
C349 0.
C346 0.
C346 0.
C347 0.
C347 0.
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
DSB_PCH_C_CLK
DSB_PCH_C_CLK#
TM
DSB_PCH_C_P0
TM
TM
DSB_PCH_C_N0
TM
DSB_PCH_C_P1
DSB_PCH_C_N1
TM
DSB_PCH_C_P2
TM
TM
DSB_PCH_C_N2
L19
1
1
4
4
DLW
DLW
21SN900HQ2L_0805_4P~D
21SN900HQ2L_0805_4P~D
1 2
R459
R459
1 2
R462
R462 L20
L20
1
1
4
4
21SN900HQ2L_0805_4P~D
21SN900HQ2L_0805_4P~D
DLW
DLW
1 2
R466
R466
1 2
R468
R468 L21
L21
1
1
4
4
DLW
DLW
21SN900HQ2L_0805_4P~D
21SN900HQ2L_0805_4P~D
1 2
R469
R469
1 2
R470
R470 L22
L22
1
1
4
4
DLW
DLW
21SN900HQ2L_0805_4P~D
21SN900HQ2L_0805_4P~D
1 2
R471
R471
2
3
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
2
3
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
2
3
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
2
3
0_0402_5%~D@
0_0402_5%~D@
TM
2
3
2
3
2
3
2
3
DSB_CON_CLK
DSB_CON_CLK#
TM
DSB_CON_P0
TM
TM
DSB_CON_N0
TM
DSB_CON_P1
DSB_CON_N1
TM
DSB_CON_P2
TM
TM
DSB_CON_N2
+5
BA
BA T1000-7-F_SOT23-3~D
T1000-7-F_SOT23-3~D
2A_8V
2A_8V
DC_SMD1812P200TF
DC_SMD1812P200TF
1
V_RUN
D4
D4
F2
F2
21
3
NC
NC
21
V_RUN_HDMI
+5
1 2
+V
DISPLAY_VCC
@
@
R5
R5
0_1206_5%~D
0_1206_5%~D
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
C337
C337
2
10U
10U
_0805_10V4Z~D
_0805_10V4Z~D
1
C338
C338
2
B_PCH_HPD_R
HDMI
PCH_SDVO
_CTRLDATA_R
PC
H_SDVO_CTRLCLK_R
HDMI
_CEC
DSB_CON_CLK#
TM TM
DSB_CON_CLK
TM
DSB_CON_N0 DSB_CON_P0
TM
TM
DSB_CON_N1 DSB_CON_P1
TM
DSB_CON_N2
TM TM
DSB_CON_P2
JHDM
JHDM
I1
CONN@
I1
CONN@
19
ET
HP_D
18
+5V
17
erved
Res
16
SDA
15
SCL
14
CEC
13
DDC/CEC_
12
CK-
11
CK+
10
hield
CK_s
9
D0-
8
D0+
7
D0_shi
eld
6
D1
-
5
D1+
4
eld
D1_shi
GND1
3
D2-
GND2
2
D2+
GND3
1
eld
D2_shi
GND4
FOX_QJC3N93-2140-7H
FOX_QJC3N93-2140-7H
GND
20 21 22 23
>ŝŶŬŽŶĞ
+3
.3V_RUN
Q12
Q12
0A
0A
5
4
0B
0B
Q12
Q12
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PC
H_SDVO_CTRLCLK_R
61
_CTRLDATA_R
PCH_SDVO
3
HDMIB_PCH_HPD16
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
A A
_CTRLCLK16
PCH_SDVO
PCH_SDVO_CTRLDATA16
PCH_SDVO
_CTRLCLK
_CTRLDATA
PCH_SDVO
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
.3V_RUN
+3
PC
HDMI
B_PCH_HPD_R
H_SDVO_CTRLCLK_R
PCH_SDVO_CTRLDATA_R
1M
1M _0402_5%~D
_0402_5%~D
12
R1168
R1168
G
G
2
13
D
S
D
S
Q12
Q12
1
1
12
R11
R11 20K_0402_5%~D
20K_0402_5%~D
28
28
1 2
R1584 2.
R1584 2.
1 2
R1583 2.
R1583 2.
2K_0402_5%~D
2K_0402_5%~D
2K_0402_5%~D
2K_0402_5%~D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
HDMI port
HDMI port
HDMI port
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
-6611P
-6611P
-6611P
V_RUN_HDMI
+5
/PROPRIETARY
26 64Wedn
26 64Wedn
26 64Wedn
of
of
of
5
4
3
2
1
+3
DET#
.3V_RUN
+3
C356
C356
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
PCH_DDPC_
PCH_DDPC_
.3V_RUN
1 2
R487
R487
1 2
R488
R488
1 2
R489
R489
1 2
R490
R490
12
CTRLCLK 16
CTRLDATA 16
1 2
R491
R491
1 2
R492
R492
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
1M_0402_5%~D
1M_0402_5%~D
1M_0402_5%~D
1M_0402_5%~D
PCH_DDPC_
PCH_DDPC_
PCH_DDPD_
PCH_DDPD_
DPD_CA_
DPC_CA_
CTRLCLK
CTRLDATA
CTRLCLK
CTRLDATA
DET
DET
DOCK_AUX16
DPD_PCH_
DPD_PCH_
Int
DPD_DO
DOCK_AUX#16
DPD_DO
DPD_CA_
el WW18 Strapping option
Intel WW18 Strapping option
C367
C367
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
CK_AUX41
C368
C368
CK_AUX#41
DET41
DPD_AUX_
12
DO
CK_AUX
DPD_
DPD_AUX#
12
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CK_AUX#
DPD_DO
DET
DPD_CA_
C
_C
U23
U23
1
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
I3C3125LEX_TSSOP14~D
I3C3125LEX_TSSOP14~D
P
P
+5
9
9
C36
C36
12
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V_RUN
5
P
A2Y
G
3
1
U24
U24
NC
N
N
14
VCC
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
DPD_CA_
4
C7SZ04P5X-G_SC70-5~D
C7SZ04P5X-G_SC70-5~D
AUX/DDC SW for DPC to E-DOCK AUX/DDC SW for DPD to E-DOCK
C357
DPC_DO
DPC_DO
DPC_CA_
C357
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
CK_AUX41
C360
C360
CK_AUX#41
DET41
DPC_AUX_
12
DO
CK_AUX
DPC_
DPC_AUX#
12
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CK_AUX#
DPC_DO
DET
DPC_CA_
C
_C
0.
0.
D D
C C
DPC_PCH_
DPC_PCH_
DOCK_AUX16
DOCK_AUX#16
1 2
3
4 5
6
7
C365
C365
12
1U_0402_16V4Z~D
1U_0402_16V4Z~D
U20
U20
VCC
BE0
BE3
A0
B0
BE1 A1
B1
GND
I3C3125LEX_TSSOP14~D
I3C3125LEX_TSSOP14~D
P
P
+5
V_RUN
5
P
A2Y
G
3
A3
B3
BE2
A2
B2
1
U21
U21
NC
4
SZ04P5X-G_SC70-5~D
SZ04P5X-G_SC70-5~D
NC7
NC7
14 13
12
11 10
9
8
DPC_CA_
DET#
+3
.3V_RUN
12
C36
C36
6
6
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CTRLCLK 16
PCH_DDPD_
CTRLDATA 16
PCH_DDPD_
B B
A A
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
W
W
W
DP S
DP S
DP S
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
LA
LA
LA
/PROPRIETARY
-6611P
-6611P
-6611P
1
27 64Wedn
27 64Wedn
27 64Wedn
of
of
of
5
D D
.3V_RUN
+3
10U
10U
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
_0805_6.3V6M~D
_0805_6.3V6M~D
1
1
C387
C387
2
HDD_F FFS_IN
ALL_INT T2
2
C C
HDD_F
ALL_INT17
WAN_SMBDAT12,13,15,37
DDR_XDP_
WAN_SMBCLK12,13,15,37
DDR_XDP_
4
C388
C388
&ƌĞĞ&Ăůů^ĞŶƐŽƌ
U26
U26
DE351DLTR
DE351DLTR
1
O
VDD_I
6
VDD
8
INT
1
9
2
INT
12
SDO
13
SDA / SDI
14
SPC
SCL /
7
CS
E351DLTR8_LGA14_3X5~D
E351DLTR8_LGA14_3X5~D
D
D
/ SDO
GND GND GND GND
RSVD RSVD
2 4 5 10
3 11
.3V_RUN
+3
3
PSATA_PTX_
PSATA_PTX_
PSATA_
PSATA_PRX_
PRX_
2
CONN@
CONN@
JSATA1
DRX_P0_C
DRX_P0_C14
DRX_N0_C14
DTX_N0_C14
DTX_P0_C14
PSATA_PTX_
PSATA_PTX_
PSATA_PRX_
PSATA_PRX_
.3V_RUN
+3
DRX_N0_C
DTX_N0_C
DTX_P0_C
PJP6
PJP6
4
4
1 2
12
C383 0.
C383 0.
12
C384 0.
C384 0.
12
C386 0.
C386 0.
12
C385 0.
C385 0.
PAD-OPEN1x1m
PAD-OPEN1x1m
HDD_DET
DRX_P0
PSATA_PTX_
01U_0402_16V7K~D
01U_0402_16V7K~D
DRX_N0
PSATA_PTX_
01U_0402_16V7K~D
01U_0402_16V7K~D
DTX_N0
PSATA_PRX_
01U_0402_16V7K~D
01U_0402_16V7K~D
PSATA_PRX_
DTX_P0
01U_0402_16V7K~D
01U_0402_16V7K~D
.3V_RUN_HDD
+3
HDD_DET
#14
V_HDD
+5
FFS_IN
#
T2_Q
JSATA1
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
17
GND
18
Res
19
GND
20
12V
21
12V
22
12V
TY
TY
erved
GND1 GND2
CO_1775770-3~D
CO_1775770-3~D
23 24
1
>ŝŶŬŽŶĞ
+3
.3V_RUN_HDD
0.
0. 1U_0402_16V4Z~D
.3V_RUN
+3
DDR_XDP_
1 2
10K_0402_5%~D
10K_0402_5%~D
R501
R501
1 2
R502
R502
10K_0402_5%~D
10K_0402_5%~D
1 2
R503
R503
100K_0402_5%~D
B B
100K_0402_5%~D
DDR_XDP_
ALL_INT
HDD_F
WAN_SMBDAT
WAN_SMBCLK
1U_0402_16V4Z~D
C402
C402
1
1
2
C399
C399
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
2
Pleace near HDD CONN
_HDD Source
+5V
V_ALW
_0402_5%~D
_0402_5%~D
5V
Q2
Q2 8
8 B
B
@
@
+5
6
2
1
D
D
G
G
3
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
1
C39
C39
3
3
2
@
@
@
@
Q27
Q27
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
S
S
+5
V_HDD
4 5
10U
10U
_0805_10V4Z~D
_0805_10V4Z~D
C394
C394
1
12
R504
R504 100K
2
100K
4
PJP3
PJP3
112
JU
JU
MP_43X79
MP_43X79
_0402_5%~D
_0402_5%~D
V_RUN
+5
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
FFS_INT218
3
+15V_ALW
+3
.3V_ALW2
12
R50
R50 100K_0402_5%~D
100K_0402_5%~D
@
@
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
61
Q2
Q2 8
A A
HDDC_EN43
100K_0402_5%~D
100K_0402_5%~D
5
12
5
5
R50
R50
8 A
A
2
@
@
12
@
@
R499
R499 100K
0
0
100K
HDD_EN_
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
5
4
+5
V_HDD
1000P
1000P
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
_0402_50V7K~D
_0402_50V7K~D
C396
1
2
C396
1
C395
C395
2
Pleace near HDD CONN
.3V_RUN
+3
G
G
2
FFS_INT2 FFS_INT2_Q
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
Q29
Q29
13
D
D
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
R
R
+5V_HDD
12
R506
@R506
@
100K_0402_5%~D
100K_0402_5%~D
D16
D16
21
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
HDD CONNE
HDD CONNE
HDD CONNE
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
CTOR
CTOR
CTOR
-6611P
-6611P
-6611P
1
28 64Wedn
28 64Wedn
28 64Wedn
of
of
of
5
4
3
2
1
&ŽƌK
JSATA2
JSATA2
CONN@
MOD
+5V_
1000P
1000P
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
1
_0402_50V7K~D
_0402_50V7K~D
C398
C398
C397
D D
Pleace near JSATA2
+3
C C
2
+3
.3V_ALW
.3V_ALW_PCH
C397
2
1 2
R510 10K
R510 10K
1 2
R513 10K
R513 10K
1 2
100K_0402_5%~D
100K_0402_5%~D
R514
R514
ZODD_
_0402_5%~D
_0402_5%~D
MOD
_0402_5%~D
_0402_5%~D
USB30
_MD
_SMI#
WAKE#
CLK_ CLK_
IE_PRX_EMBTX_P415
PC
IE_PRX_EMBTX_N415
PC
PC
IE_PTX_EMBRX_P415
PC
IE_PTX_EMBRX_N415
EM
PLTRST_
BAY_
BAY_
D_SATA_PCIE#_DET42
MO
MOD
PCIE
SMBDAT43,47
SMBCLK43,47
BCL
PCIE_EMB15 PCIE_EMB#15
_MD
SATA_O SATA_O
SATA_O SATA_O
K_REQ#15 _WAKE#37,38,42
EMB#17
DD_PTX_DRX_P1_RP DD_PTX_DRX_N1_RP
DD_PRX_DTX_N1_RP DD_PRX_DTX_P1_RP
EMBCL
K_REQ#
PCIE
_WAKE#
PLTRST_
SMBDAT
BAY_
SMBCLK
BAY_ MO
D_SATA_PCIE#_DET
C389 0.
C389 0.
12
C390 0.
C390 0.
12
12
C391 0.
C391 0.
12
C392 0.
C392 0.
DET#43
DEVICE_
C40
C40
12
C40
C40
12
EMB#
+3
.3V_ALW
Q76
Q76
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
D
S
D
S
13
G
G
2
MO
DC_EN#
Q12
Q12
3B
3B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
5
USB30
01U_0402_16V7K~D
01U_0402_16V7K~D 01U_0402_16V7K~D
01U_0402_16V7K~D
01U_0402_16V7K~D
01U_0402_16V7K~D 01U_0402_16V7K~D
01U_0402_16V7K~D
MOD
+5V_
IE_PTX_EMBRX_P4_C
PC
90.1U_0402_10V7K~D
90.1U_0402_10V7K~D
IE_PTX_EMBRX_N4_C
PC
80.1U_0402_10V7K~D
80.1U_0402_10V7K~D
+5V_
MOD
1 2
R1177
R1177
ZODD_
WAKE#
USB30
_EN
10K_0402_5%~D
10K_0402_5%~D
SATA_PTX_ SATA_PTX_
SATA_PRX_ SATA_PRX_
MOD
_SMI#
_MD
DRX_P1 DRX_N1
DTX_N1 DTX_P1
ZODD_
B30_SMI# 14
US
WAKE# 42
1
GND
2
A+
3
A-
4
D
GN
5
B-
6
B+
7
GND
8
DP
9
+5V
10
+5V
11
MD
12
GND
13
GND
14
GND
15
REFC
LK+
16
LK-
REFC
17
GND
18
PETX+
19
PETX-
20
GND
21
GND
22
PERX+
23
PERX-
24
GND
25
+5V
26
CLKREQ
27
WAKE#
28
PERST#
29
DATA
SMB_
30
CLK
SMB_
31
HPD
TY
TY
CO_2-2129116-1
CO_2-2129116-1
>ŝŝŶŬŽŶĞ
.3V_RUN
+3
CONN@
#
GND1 GND2
M
D_SATA_PCIE#_DET
O
+5VM
OD Source
_A
LW
+15V
.3V_ALW2
+3
12
R50
R50 100K_0402_5%~D
100K_0402_5%~D
MO
DC_EN#
D
D
61
MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
Q31A
MO
100K
100K
32 33
+3
.3V_ALW
12
R515
R515 100K
100K
_0402_5%~D
_0402_5%~D
USB30
_EN
61
Q123A
Q123A
MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
D
D
2
R512
R512
_0402_5%~D
_0402_5%~D
12
DC_EN
MO
DC_EN42
Q31A
2
12
9
9
2
MOD
D
D
3
MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
5
4
R507
R507 100K
100K
Q31B
Q31B
_0402_5%~D
_0402_5%~D
_EN
3
0.
0. 1U_0603_50V4Z~D
1U_0603_50V4Z~D
1
2
+
C400
C400
5
V_ALW
G
G
6
2
1
D
D
Q30
Q30 S
S
S
S
+5V_
4 5
10U
10U
_0805_10V4Z~D
_0805_10V4Z~D
1
C401
C401
2
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
MOD
100K
100K
12
R511
R511
_0402_5%~D
_0402_5%~D
0.
0.
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
01U_0402_16V7K~D
B B
01U_0402_16V7K~D
C407 0.
DD_PTX_DRX_P1_C14
SATA_O
DD_PTX_DRX_N1_C14
SATA_O
SATA_ODD_PRX_DTX_N1_C14
DD_PRX_DTX_P1_C14
SATA_O
A A
5
C407 0.
C406 0.
C406 0.
C405 0.
C405 0.
C404 0.
C404 0.
01U_0402_16V7K~D
12
01U_0402_16V7K~D
01U_0402_16V7K~D
12
01U_0402_16V7K~D
01U_0402_16V7K~D
12
01U_0402_16V7K~D
01U_0402_16V7K~D
12
12
12
+3
10K
10K
_0402_5%~D
_0402_5%~D
0_0402_5%~D
0_0402_5%~D
.3V_RUN
@
@
12
R1173
R1173
12
R11
R11
74
74
^dZĞƉĞĂƚĞƌĨŽƌK
U25
U25
7
EN
18
SATA_O
DD_PTX_DRX_P1
SATA_O
DD_PTX_DRX_N1
SATA_ODD_PRX_DTX_N1
SATA_ODD_PRX_DTX_P1
HDD_EQ HDD_EQ
10K
10K
@
@
_0402_5%~D
_0402_5%~D
R1175
R1175
0_0402_5%~D
0_0402_5%~D
R11
R11
76
76
4
1 2
CAD
1
AINP
2
AINM
4
BOUTM
5
BOUTP
3
GND
13
GND
17
GND
19
GND
21
EP
AX4951BECTP+TGH7_TQFN20_4X4~D
AX4951BECTP+TGH7_TQFN20_4X4~D
M
M
X76M@
X76M@
VCC VCC VCC VCC
AOUTP AOUTM
BINP BINM
6 10 16 20
9
PA
8
PB
15 14
11 12
01U_0402_16V7K~D
1
1
C382
C382
C381
C381
2
2
HDD_DEW
2
HDD_DEW
1
HDD_PE1 HDD_PE2
SATA_ODD_PTX_DRX_P1_RP SATA_O
DD_PTX_DRX_N1_RP
SATA_O
DD_PRX_DTX_P1_RP DD_PRX_DTX_N1_RP
SATA_O
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
X76M
X76M
0_0402_5%
0_0402_5%
12
~D
~D
10K
10K
12
_0402_5%~D
_0402_5%~D
@
@
R1169
R1169
X76@
X76@
R1170
R1170
X76M
X76M
0_0402_5%
0_0402_5%
12
~D
~D
10K
10K
12
_0402_5%~D
_0402_5%~D
R1171
R1171
X76@
X76@
R1172
R1172
@
@
1 2
12
.3V_RUN
+3
0_0402_5%
0_0402_5%
@
@
R493
R493
~D
~D
@
@
0_0402_5%
0_0402_5%
R496
R496
~D
~D
SA00003LH1L SA00003ZX0L
0_0402_5%~D
0_0402_5%~D
@R494
@
R494
1 2
R1169 R1171
R1170 R1172
@R495
@
0_0402_5%~D
0_0402_5%~D
12
R495
2
MAXIM TI
pop depop
popdepop
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
ODD CO
ODD CO
ODD CO
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
NNECTOR
NNECTOR
NNECTOR
-6611P
-6611P
-6611P
1
29 64Wedn
29 64Wedn
29 64Wedn
of
of
of
2
sͺ/KƐŚŽƵůĚŵĂƚĐŚ ǁŝƚŚ,ƵƐůĞǀĞů
/ŶƚĞƌŶĂů^ƉĞĂŬĞƌƐ,ĞĂĚĞƌ
ϮϬŵŝůƐƚƌĂĐĞ
T_SPK_L+
IN IN
T_SPK_L-
IN
T_SPK_R+ T_SPK_R-
IN
C974
C974
C973
C973
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
1
1
2
2
B B
se to U72 pin5
Clo
_CODEC_SDOUT
PCH_AZ
12
R10
R10
77
@
77
@
47_0402_5%~D
47_0402_5%~D
1
8
@
8
@
C97
C97
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
Pl
ace closely to Pin 13.
C975
C975
680P_0402_50V7K~D
680P_0402_50V7K~D
1
1
2
2
AUD_SENSE_
L78 BLM
L78 BLM
1 2
L79 BLM
L79 BLM
1 2
L80 B
L80 B
1 2
L81 BLM
L81 BLM
1 2
C976
C976
680P_0402_50V7K~D
680P_0402_50V7K~D
se to U72 pin6
Clo
PCH_AZ_
12
R1076
R1076
@
@
10_0402_5%
10_0402_5%
1
@
@
C977
C977
10P
10P
2
A
12
R1086
R1086
_0402_1%~D
_0402_1%~D
20K
20K
3
AUD_HP_
5
7B
7B
Q10
Q10
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
18BD121SN1D_2P~D
18BD121SN1D_2P~D 18BD121SN1D_2P~D
18BD121SN1D_2P~D
LM
LM
18BD121SN1D_2P~D
18BD121SN1D_2P~D 18BD121SN1D_2P~D
18BD121SN1D_2P~D
CODEC_BITCLK
~D
~D
_0402_50V8J~D
_0402_50V8J~D
1
2
NB_SENSE
R1083
R1083
2.
2.
49K_0402_1%~D
49K_0402_1%~D
1000P
1000P
_0402_50V7K~D
_0402_50V7K~D
C980
C980
+3
.3V_RUN
12
Add for solve pop noise and detect issue
A A
ace closely to Pin 14
Pl
DOCK_
HP_DET42
AUD_SENSE_
+3
.3V_RUN
100K
100K
12
R1081
R1081
_0402_5%~D
_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
R10
R10
39.2K_0402_1%~D
39.2K_0402_1%~D
2
Q106A
Q106A
B
12
12
79
79
R1080
R1080
_0402_1%~D
_0402_1%~D
20K
20K
3
61
5
Q106B
Q106B
4
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
2
R1078
R1078
49K_0402_1%~D
49K_0402_1%~D
2.
2.
C97
C97
.3V_RUN
+3
9
9
2
12
DDA_AVDD
+V
12
R1087
R1087 100K
100K
AUD_HP_
+VDDA_AVDD
12
R1082
R1082 100K
100K
DOCK_
T_SPKL_L+
IN IN
T_SPKL_L-
IN
T_SPKR_R+ T_SPKR_R-
IN
_0402_5%~D
_0402_5%~D
NB_SENSE 31,42
_0402_5%~D
_0402_5%~D
MIC_DET 42
>ŝŶŬŽŶĞ
^ƉĞĂŬĞƌŽŶŶĞĐƚŽƌ
JSPK1
JSPK1
1 2 3 4
5 6
PCH_AZ_
CODEC_BITCLK14
PCH_AZ
_CODEC_SDOUT14
PCH_AZ_
CODEC_SYNC14
_CODEC_SDIN014
PCH_AZ
CODEC_RST#14
PCH_AZ_
AUD_NB_
MUTE#42
+3
D><΀ϮϬ΁
ϬϬϬ
ϬϬϭ
ϬϭϬ
Ϭϭϭ
Conn@
Conn@
1 2 3 4
GND GND
CO_2-1775765-4
CO_2-1775765-4
TY
TY
I2S
_12MHZ
I2
S_BCLK
_DO
I2S
S_LRCLK
I2
_DI#
I2S
.3V_RUN
WŽƌƚ &ƵŶĐƚŝŽŶ
ZĞƐŝƐƚŽƌ ^E^ͺ
ϯϵϮ<
ϮϬ<
ϭϬ<
ϱϭϭ<
Ϯϰϵ<
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
1
C951
C951
2
2
WůĂĐĞZϭϬϵϲĐůŽƐĞƚŽĐŽĚĞĐ
1 2
33_0402_5%~DR
33_0402_5%~DR
1096
1096
WůĂĐĞZϭϬϵϳĐůŽƐĞƚŽĐŽĚĞĐ
1 2
1097
1097
1 2
10K_0402_5%
10K_0402_5%
džƚĞƌŶĂůD/
,ĞĂƌWŚŽŶĞKƵƚ
ŽĐŬƵĚŝŽ
/ŶƚĞƌŶĂů^W<
&ƌĞƋƵĞŶĐLJ ;D,njͿ Ϯϰ ϭϮ ϮϮϱϳϵϮ ϭϭϮϴϵϲ
WKZd;,WϬͿ
WKZd;,WϭͿ
E
^W/&KhdϬ
.3V_RUN
+3
0.
0.
1U_0603_10V
1U_0603_10V
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C953
C953
C952
C952
2
6K~D
6K~D
PCH_AZ_
PCH_AZ
PCH_AZ_
PCH_AZ
PCH_AZ_
33_0402_5%~DR
33_0402_5%~DR
~DR1099
~DR1099
W>>ĐůŽĐŬ ĚŝǀŝƐŽƌ E E ϱ ϭϬ
^W/&Khdϭ;D/ϭͿ
WƵůůͲƵƉƚŽs
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
EŽƚĞƐ <ĞĞƉWsƐƵƉƉůLJĂŶĚƐƉĞĂŬĞƌƚƌĂĐĞƐƌŽƵƚĞĚŽŶƚŚĞ'EƉůĂŶĞ <ĞĞƉĂǁĂLJĨƌŽŵ'EĂŶĚŽƚŚĞƌĂŶĂůŽŐƐŝŐŶĂůƐ
10U_0805_10V
10U_0805_10V
1
C954
C954
2
6K~D
6K~D
CODEC_BITCLK
_CODEC_SDOUT
CODEC_SYNC
_SDIN0_R
CODEC_RST#
_DO_R
I2S
dŝĞŶĂůŽŐ'ƌŽƵŶĚƚŽŝŐŝƚĂůŐƌŽƵŶĚƵŶĚĞƌ ĐŽĚĞĐďLJĂƐŝŶŐůĞƉŽŝŶƚ
ƐƵŐŐĞƐƚĞĚ ƐĂŵƉůĞƌĂƚĞ ϵϲ<,nj ϰϴ<,nj ϴϴϮ<,nj ϰϰϭ<,nj
^E^ͺ
WKZd
WKZd&
D/Ϭ
WůĂĐĞϵϱϭΕϵϲϭĐůŽƐĞƚŽŽĚĞĐ
U72
U72
1
RE
DVDD_CO
3
DVDD_I
O
9
DVDD
6
K
BITCL
5
SDATA_O
UT
10
SYNC
8
N
SDATA_I
11
RESET#
15
_MCLK
I2S
16
I2
S_SCLK
17
S_DOUT
I2
18
S_LRCLK
I2
24
_DIN
I2S
19
nnect
No Co
20
No Co
nnect
47
EAPD
7
DVSS
42
PVSS
49
GND
D90B2X5NLGXZAX8_QFN48_7X7~D
D90B2X5NLGXZAX8_QFN48_7X7~D
92H
92H
2
2
PJP6
PJP6
12
PAD-OPEN1x1m
PAD-OPEN1x1m
EŽƚĞƐ
,ƵĚŝŽŝƚůŬ ,ƵĚŝŽŝƚů<Ϯ
EN_I2S_NB_CODEC#42
SENSE_A SENSE_B
PORTA_ Vre
PORTB_
PORT
PORT
PORT
PORT
MO
PC_BEEP
IC_CLK/GPIO 1
DM
IC_0/GPIO 2
DM
DM
IC1/GPIO0/SPDIF OUT1
DIFOUT0//GPIO3/A ux_Out
SP
VREFFIL
ƉůĂĐĞĂƚ'EĂŶĚ'EƉůĂŶĞ
27
AVDD1
38
AVDD2
45
PVDD
39
PVDD
13 14
28
L
PORTA_
29
R
23
fOut_A
31
L
PORTB_
32
R
40
D_+L
41
D_-L
44
D_+R
43
D_-R
25
NO_OUT
12
2 4 46 48
36
CAP+
35
CAP-
21
T
22
CAP2
34
V-
37
Vre
g
26
AVSS1
30
AVSS
33
AVSS
12
C267
C267
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
12
3
3
C28
C28
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
12
C284
C284
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
.3V_RUN
+3
I2S_BCLK
I2S_LRCLK
_DO
I2S
_12MHZ
I2S
R1110
R1110 1K_0402_5%~D
1K_0402_5%~D
2
1
1
10U_0805_10V
10U_0805_10V
1
C955
C955
2
6K~D
6K~D
AUD_SENSE_ AUD_SENSE_
_IN_L
MIC
C1155 1U
C1155 1U
_IN_R
MIC
AUD_HP_
OUT_L OUT_R
AUD_HP_
IN
T_SPK_L+
IN
T_SPK_L-
T_SPK_R+
IN IN
T_SPK_R-
BEEP
AUD_PC_
IC_CLK_R
DM
1 2
L8
L8
2 BLM18BB221SN1D_2P~D
2 BLM18BB221SN1D_2P~D
1
C962
C962
4.7U
4.7U
_0603_10V6K~D
_0603_10V6K~D
WůĂĐĞϵϲϮĐůŽƐĞƚŽŽĚĞĐ
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C1103
C1103
U73
U73
16
VCC
2
1A
4
2A
6
3A
10
4A
12
5A
14
6A
1
OE1
#
15
12
#
OE2
CD74HC366M96_SO16~D
CD74HC366M96_SO16~D
1
DDA_AVDD
+V
1U_0603_10V
1U_0603_10V
1
2
6K~D
6K~D
+V
DDA_PVDD
A B
+V
1 2
R1143
R1143
C1113
C1113
C1114
C1114
C956
C956
1 2
REFOUT
1
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C957
C957
_0402_6.3V6K~D
_0402_6.3V6K~D
2.2K_0402_5%~D
2.2K_0402_5%~D
12
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
12
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DM DMI
1U_0603_10V
1U_0603_10V
1
C1172
C1172
2
6K~D
6K~D
SPKR_R
BEEP_R
IC_CLK 24
C0 24
BLM
1 2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C1173
C1173
2
R1119 100K
R1119 100K
R1120 100K
R1120 100K
R1141
R1141
R1142
R1142
10U_0805_10V
10U_0805_10V
1
2
6K~D
6K~D
12
12
12
10K_0402_5%~D@
10K_0402_5%~D@
12
10K_0402_5%~D@
10K_0402_5%~D@
+5
C958
C958
MI
L77
L77
21PG600SN1D_0805~D
21PG600SN1D_0805~D
BLM
WůĂĐĞϵϲϯΕϵϲϲĐůŽƐĞƚŽŽĚĞĐ
4.7U_0603_10V6K~D
4.7U_0603_10V6K~D
4.7U
4.7U
1
1
_0603_10V6K~D
_0603_10V6K~D
2
1Y#
2Y#
3Y#
4Y#
5Y#
6Y#
GND
C963
C963
+3
3
5
7
9
11
13
8
2
.3V_RUN
3
C964
C964
D
D
2
A204U_SOT323-3~D
A204U_SOT323-3~D
@
@
D54
D54
1
_DI#
I2S
1U_0603_10V
1U_0603_10V
1
2
6K~D
6K~D
3
1
+3
C965
C965
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
.3V_RUN
@D55
@
D55
3
10U_0805_10V
10U_0805_10V
1
2
6K~D
6K~D
3
2
1
C966
C966
2
1
@
@
D58
D58
A204U_SOT323-3~D
A204U_SOT323-3~D
D
D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Azalia
Azalia
Azalia
(HD) Codec
(HD) Codec
(HD) Codec
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
+V
D
D
D
D
2
3
A204U_SOT323-3~D
A204U_SOT323-3~D
A204U_SOT323-3~D
A204U_SOT323-3~D
@
@
D56
D56
1
/PROPRIETARY
V_RUN
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C959
C959
2
C_IN_R 31
AUD_HP_ AUD_
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
REFOUT
1U_0603_10V
1U_0603_10V
1
C1180
C1180
2
6K~D
6K~D
@
@
D57
D57
DAI_BCLK# 41
DAI_
DAI_
DAI_
DAI_DI 41
30 64Wedn
30 64Wedn
30 64Wedn
+5
V_RUN
10U_0805_10V6K~D
10U_0805_10V6K~D
1
C960
C960
2
OUT_L 31 OUT_R 31
HP_
SPKR 1
BEEP 4
LRCK# 41
DO# 41
12MHZ# 41
of
of
of
95
95
R10
R10
1 2
0_0805_5%~D
0_0805_5%~D
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C961
C961
2
4
3
5
D D
ER_SW#_MB
W
ER_SW#_MB43,44
PO
POW
SW1
SW1
2
4
SKRBAAE0
SKRBAAE0
4
10_4P~D
10_4P~D
3
1
3
/KďŽĂƌĚKEE
2
1
>^ͲϲϲϭϭW
@
@
D23
D23
3
4VS2UT_SOT23-3~D
4VS2UT_SOT23-3~D
PESD2
PESD2
1
2
SW2
SW2
@
LAT_O
LAT_O
N_SW_BTN#43
C C
N_SW_BTN#
POWER & INSTAN
T ON SWITCH
2
4
SKRBAAE0
SKRBAAE0
@
1
3
10_4P~D
10_4P~D
DAT_ CLK_
VSYNC_ HSYNC_
RED_
EEN_CRT25
GR
BLUE_
DDC2_CRT25 DDC2_CRT25
VSYNC_ HSYNC_
RED_CRT GR
EEN_CRT
BLUE_
DDC2_CRT
DAT_
DDC2_CRT
CLK_
DETECT_GND
CRT
BUF
BUF
BUF25 BUF25
CRT25
CRT25
ĞĨƵůƚŽŶ t/Z>^^ͺKEK&&η >KtKE ,/',K&&
M
DIA_DET#
ME
DIA_DET#18
RELESS_ON#/OFF42
WI
VO
L_MUTE43
VO
L_DOWN43 L_UP43
VO
B B
E
RELESS_ON#/OFF
WI
_MUTE
VOL
_DOWN
VOL VOL
_UP
DĞĚŝĂŽĂƌĚ
>^ͲϲϲϭϯW
DIA1
CONN@
DIA1
CONN@
JME
JME
1
1
2
2
3
3
4
4
5
5
6
11
6
G1
7
12
7
G2
8
8
9
9
10
10
TYCO_1-2041070-0~D
TYCO_1-2041070-0~D
>ŝŶ<ŽŶĞ
>ŝŶŬŽŶĞ
1
CONN@
1
CONN@
JIO
JIO
2
112
4
334
6
556
8
778
10
9910
12
11
12
14
13
14
16
15
16
18
17
18
20
19
20
22
21
22
24
G1
G2
26
G3
G4
28
G5
G6
TYCO_8921155-1
TYCO_8921155-1
OOP# 18
IO_L
V_RUN
+5 +3
11 13 15 17 19 21
23 25 27
.3V_RUN
AUD_
HP_
AUD_HP_
MI
C_IN_R 30
AUD_HP_
OUT_R 30 OUT_L 30
NB_SENSE 30,42
V_RUN
+5
1
2
WůĂĐĞĐůŽƐĞ ƚŽ:/Kϭϯϱ
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C1000
C1000
.3V_RUN
+3
1
2
WůĂĐĞĐůŽƐĞ ƚŽ:/Kϭϳ
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C1002
C1002
>ŽĂƌĚǁŝƚŚ>ŝĚ
>^ͲϲϲϭϮW
1
CONN@
1
CONN@
JLED
LED SATA_LED46 BATT_WH
ITE46
LLOW46
BATT_YE
WL
AN_LED46
LI
.3V_ALW
+3
A A
D_CL#42,46
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
5
C45
C45
7
7
ED
SATA_L BATT_WHITE BATT_YE
AN_LED
WL LI
D_CL#
1
2
LLOW
LEDB_DET#
B_DET#18
JLED
1
1
2
2
3
3
4
4
5
5
6
9
6
G1
7
10
7
G2
8
8
TYCO_2041084-8
TYCO_2041084-8
>ŝŶŬŽŶĞ
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
IO/S
IO/S
IO/S
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
niffer/LID
niffer/LID
niffer/LID
-6611P
-6611P
-6611P
1
31 64Wedn
31 64Wedn
31 64Wedn
of
of
of
5
+3.3V
_LAN
TAG_TMS
1 2
R545
R545
1 2
R546
R546
D D
PM_
LANPHY_ENABLE18
C C
TP_LAN_J
10K_0402_5%~D@
10K_0402_5%~D@
10K_0402_5%~D@
10K_0402_5%~D@
TAG_TCK
TP_LAN_J
LA
PLTRST_
CLK_
K_
CL
_PRX_GLANTX_P715
PCIE
C
IE_PRX_GLANTX_N715
+3.3V
9
9
R54
R54
10K_0402_5%~D
10K_0402_5%~D
1 2
0_0402_5%~D
0_0402_5%~D
R555
R555
R55
R55
@
@
10K_0402_5%~D
10K_0402_5%~D
XTALO
25MH
25MH
2
C470
C470
1
Need to verify A3 silicon drive power before removing C465 KDS crystal vender verify driving level in A3
P
7
7
_LAN
_R
_0402_50V8J~D
_0402_50V8J~D
33P
33P
IE_PTX_GLANRX_P715
PC
12
PC
IE_PTX_GLANRX_N715
12
R1144
R1144
0_0402_5%
0_0402_5%
~D
~D
1 2
Y3
Y3
Z_18PF_7A25000110~D
Z_18PF_7A25000110~D
1 2
LA
LA
N_SMBDATA15
2
C471
C471
1
PCIE_LAN15 PCIE_LAN#15
N_SMBCLK15
_0402_50V8J~D
_0402_50V8J~D
33P
33P
NCLK_REQ#15
1 2
R1187
R1187
LAN#17
12
C458
C458
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
12
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C459
C459
1 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C460
C460
1 2
C461
C461
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
R551
R551
1 2 1 2
R552
R552
SMBus Device Address 0xC8
LA
N_DISABLE#_R42
T14
T14
2 PAD~D
2 PAD~D
T14
T14
3 PAD~D
3 PAD~D
1K
1K
12
R561
R561
_0402_5%~D
_0402_5%~D
+3
.3V_RUN
12
LA
0_0402_5%~D
0_0402_5%~D
PCIE_LAN
CLK_ CLK_
PCIE_LAN#
C
IE_PRX_GLANTX_P7_C
P
PCIE
_PRX_GLANTX_N7_C
PC
IE_PTX_GLANRX_P7_C
IE_PTX_GLANRX_N7_C
PC
0_0402_5%~D
0_0402_5%~D
LAN
_SMBCLK_R
N_SMBDATA_R
LA
0_0402_5%~D
0_0402_5%~D
LA
N_DISABLE#_R
M_ACTLED_YEL#
LO LOM
_SPD100LED_ORG#
M_SPD10LED_GRN#
LO
TP_LA TP_LA TP_LA TP_LA
XTALO XTALI
_TEST_EN
LAN
RES_BI
3.
3.
12
01K_0402_1%~D
01K_0402_1%~D
R562
R562
4
R54
R54
7
7
10K_0402_5%~D
10K_0402_5%~D
U31
NCLK_REQ#_R
N_JTAG_TDI N_JTAG_TDO N_JTAG_TMS N_JTAG_TCK
AS
R562 Resistor Value:
3.01 kohm for Hanksville-M LOM
2.37 kohm for Hanksville-D LOM
48 36
44 45
38 39
41 42
28 31
3
26 27 25
32 34 33 35
9
10
30
12
U31
K_
REQ_N
CL PE_RST_
PE_CL PE_CL
PETp PETn
PERp PERn
SMB_ SMB_
LA
N_DISABLE_N
0
LED
1
LED
2
LED
G_TDI
JTA
G_TDO
JTA JTA
G_TMS G_TCK
JTA
XTAL_ XTAL_
TEST_E
S
RBIA
KP KN
CLK DATA
OUT IN
N
MDI
MDI
PCIE
PCIE
VD_VCC3P3_1
RS RS
VD_VCC3P3_2
SMBUS
SMBUS
VDD3P3
JTAG LED
JTAG LED
N
82579_Q
82579_Q
I
_PLUS0
MD
_MINUS0
MDI
_PLUS1
MDI
MDI
_MINUS1
_PLUS2
MDI
MDI
_MINUS2
MDI
_PLUS3
_MINUS3
MDI
RSVD_N
VDD3P3
VD
D3P3_15 D3P3_19
VD
D3P3_29
VD
D1P0_47
VD
D1P0_46
VD
D1P0_37
VD
VD
D1P0_43
VD
D1P0_11
VD
D1P0_40 D1P0_22
VD
D1P0_16
VD
VDD1P0
RL_1P0
CT
VSS_EPAD
FN48_6X6~D
FN48_6X6~D
_OUT
3
_SPD100LED_ORG#
LOM
LOM
+3.3
C46
C46
4
4
1U_0603_10V6K~D
1U_0603_10V6K~D
_SPD10LED_GRN#
V_LAN
LAN
_TX0+
13
_TX0-
LAN
14
_TX1+
LAN
17
LAN
_TX1-
18
_TX2+
LAN
20
LAN
_TX2-
21
LAN
_TX3+
23
_TX3-
LAN
24
6
C
VD_VCC3P3_1
+RS
1
+RS
VD_VCC3P3_2
2 5
_IN
+3.3V
4
15 19 29
47 46 37
43
11
40 22 16 8
_8
GCTL_PNP10
RE
7
49
_LAN_OUT
+1.0V
R553 4.
R553 4. R554 4.
R554 4.
_LAN
12
7K_0402_1%~D
7K_0402_1%~D
12
7K_0402_1%~D
7K_0402_1%~D
1
2
Note: +1.0V_LAN will work at 0.95V to 1.15V
2
_LAN
REGC
+3.3V
1
2
TL_PNP10
B
A
8
8
C47
C47
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
5
P
4
O
G
TC7
TC7
SH08FU_SSOP5~D
SH08FU_SSOP5~D
3
U15
U15
L29
L29
1 2
4.7U
4.7U
H_CBC2012T4R7M_20%~D
H_CBC2012T4R7M_20%~D
Idc max=330mA
WL
AN_LAN_DISB# 42
Place R548, C462, C463 and L29 close to U31
_LAN
+1.0V
0.
0.
0.
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
1
1
2
C467
C467
C466
C466
2
0.
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
C468
C468
2
22U
22U
1U_0402_10V7K~D
1U_0402_10V7K~D
_0805_6.3V6M~D
_0805_6.3V6M~D
C1177
C1177
1
1
C469
C469
2
2
1
_LAN
+1.0V
0.
0.
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1U_0402_10V7K~D
1U_0402_10V7K~D
C463
C463
C1181
C1181
1
1
2
2
+3.3V
_LAN
22U
22U
_0805_6.3V6M~D
_0805_6.3V6M~D
C1178
C1178
1
2
WůĂĐĞϭϭϳϴĐůŽƐĞƚŽƉŝŶϱ
+1.0V_LAN POWER OPTIONS
Shared with PCH
1.05V SVR
STUFF: R548 NO STUFF: L29
Internal SRV
*
STUFF: L29 NO STUFF: R548
_LAN
+3.3V
B B
LAN
_TX0+
1 2
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
L30 12N
L30 12N
LAN
_TX0-
1 2
L31 12NH_0603CS-120EJTS_5%~DL31 12NH_0603CS-120EJTS_5%~D
_TX1+
LAN
1 2
L33 12N
L33 12N
H_0603CS-120EJTS_5%~D
_TX1-
LAN
_TX2-
LAN
LAN
_TX3+
LAN_TX3-
DOCKED
DOCKED42
A A
ut Notice : Place bead as
Layo close PI3L500 as possible
FR
NIC DOCKED
OM
H_0603CS-120EJTS_5%~D
1 2
L32 12N
L32 12N
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
1 2
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
L34 12N
L34 12N
1 2
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
L35 12N
L35 12N
1 2
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
L36 12N
L36 12N
1 2
H_0603CS-120EJTS_5%~D
H_0603CS-120EJTS_5%~D
L37 12N
L37 12N
5
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
C47
C47
2
2
1
M_ACTLED_YEL#
LO LOM
_SPD100LED_ORG# _SPD10LED_GRN#
LOM
1: T
O DOCK
0: TO RJ45
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
C47
C47
C47
C47
3
3
4
4
1
1
39
U32
U32
LAN
_TX0+R
LAN
_TX0-R
_TX1+R
LAN
_TX1-R
LAN
LAN_TX2+RLAN_TX2+
_TX2-R
LAN
LAN
_TX3+R
LAN_TX3-R
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
A0
LED
16
LEDA1
42
LED
A2
5
PD
43
PAD_G
ND
I3L720ZHEX_TQFN42_9X3P5~D
I3L720ZHEX_TQFN42_9X3P5~D
P
P
VDD1VDD4VDD8VDD14VDD21VDD30VDD
4
LED LED LED
LEDC0 LE
DC1 DC2
LE
B0+
B0-
B1+
B1-
B2+
B2-
B3+
B3-
B0 B1 B2
C0+
C0-
C1+
C1-
C2+
C2-
C3+
C3-
ANALO G
LAN SWITCH
38 37
34 33
29 28
25 24
17 18 41
36 35
32 31
27 26
23 22
19 20 40
LAN_TX0+
SW_ SW_
LAN_TX0-
LAN_TX1+
SW_ SW_
LAN_TX1-
SW_
LAN_TX2+ LAN_TX2-
SW_
LAN_TX3+
SW_ SW_LAN_TX3-
LAN_ACTLED_YEL# LED
_100_ORG#
D_10_GRN#
LE
LOM_TRD0+
DOCK_ DOCK_
LOM_TRD0-
DOCK_LOM_TRD1+
LOM_TRD1-
DOCK_
DOCK_
LOM_TRD2+ LOM_TRD2-
DOCK_
LOM_TRD3+
DOCK_ DOCK_
LOM_TRD3-
DOCK_LOM_ACTLED_YEL#
CK_LOM_SPD100LED_ORG#
DO DOCK_LOM_SPD10LED_GRN#
SW
_LAN_TX0+ 33 _LAN_TX0- 33
SW
SW
_LAN_TX1+ 33 _LAN_TX1- 33
SW
SW
_LAN_TX2+ 33 _LAN_TX2- 33
SW
SW_LAN_TX3+ 33
_LAN_TX3- 33
SW
LA
N_ACTLED_YEL# 33
_100_ORG# 33
LED LED
_10_GRN# 33
DOCK_
LOM_TRD0+ 41 LOM_TRD0- 41
DOCK_
LOM_TRD1+ 41
DOCK_ DOCK_LOM_TRD1- 41
DOCK_
LOM_TRD2+ 41 LOM_TRD2- 41
DOCK_
DOCK_
LOM_TRD3+ 41 LOM_TRD3- 41
DOCK_
LOM_ACTLED_YEL# 41
DOCK_ DOCK_LOM_SPD100LED_ORG# 41 DO
CK_LOM_SPD10LED_GRN# 41
3
TO DOCK
5
5
R56
R56 100K_0402_5%~D
100K_0402_5%~D
D
D MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
Q35A
Q35A
+15V_A
5
.3V_ALW2
+3
12
61
AUX_O
SIO
_SLP_LAN#16,42
R566 0_0402_5%~DR566 0_0402_5%~D
1 2
R567
R567
1 2
N43
2
0_0402_5%~D@
0_0402_5%~D@
2
+3
.3V_ALW
LW
12
R564
R564
_0402_5%~D
_0402_5%~D
100K
100K
ENAB_3
D
D
3
MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
Q35B
Q35B
4
DELL CONFIDENTIAL
C
C
C
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Intel 82579 (Hanksville) / LAN SW
Intel 82579 (Hanksville) / LAN SW
Intel 82579 (Hanksville) / LAN SW
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
Q34
Q34
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
D
D
6
S
S
45
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
C475
G
G
C475
3
VLAN
2 1
2200P
2200P
_0402_50V7K~D
_0402_50V7K~D
1
C477
C477
2
/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
LA
LA
LA
-6611P
-6611P
-6611P
32 64Wedn
32 64Wedn
32 64Wedn
1
_LAN
+3.3V
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
1
C476
C476
2
2
of
of
of
5
T155
D D
SW_LAN_TX0+32
SW_LAN_TX0-32
+TRM_CT1
+TRM_CT2
SW_LAN_TX1+32
1
1
SW_LAN_TX1-32
C37
C37
C36
C36
2
2
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
C C
1
C38
C38
2
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
+TRM_CT3
+TRM_CT4
1
C39
C39
2
0.47U_0603_10V7K~D
0.47U_0603_10V7K~D
SW_LAN_TX2+32
SW_LAN_TX2-32
SW_LAN_TX3+32
SW_LAN_TX3-32
T155
1
TD1+
2
TD1-
3
1
TDCT
4
2
TDCT
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
3
TDCT
10
4
TDCT
11
TD4+
12
TD4-
350UH_H5120DNL~D
350UH_H5120DNL~D
1:1
1:1
T1/A
T1/A
1:1
1:1
T1/A
T1/A
1:1
1:1
T1/A
T1/A
1:1
1:1
T1/A
T1/A
4
T1/B
T1/B
T1/B
T1/B
T1/B
T1/B
T1/B
T1/B
TX1+
TXCT
TXCT
TX2+
TX3+
TXCT
TXCT
TX4+
TX1-
TX2-
TX3-
TX4-
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
NB_LAN_TX0+
NB_LAN_TX0-
Z2805
Z2807
NB_LAN_TX1+
NB_LAN_TX1-
NB_LAN_TX2+
NB_LAN_TX2-
Z2806
Z2808
NB_LAN_TX3+
NB_LAN_TX3-
3
R1089 150_0402_5%~DR1089 150_0402_5%~D
LAN_ACTLED_YEL#32
LED_10_GRN#32
LED_100_ORG#32
12
12
12
12
1 2
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX1-
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX1+
NB_LAN_TX0-
NB_LAN_TX0+
R1091 150_0402_5%~DR1091 150_0402_5%~D
1 2
R1090 150_0402_5%~DR1090 150_0402_5%~D
1 2
2
+3.3V_LAN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
470P_0402_50V7K~D
C1106
C1106
470P_0402_50V7K~D
C1167
C1167
1
2
JLOM1
JLOM1
9
Yel
10
Ye
l
8
PR4-
7
PR4
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
een LED-
Gr
13
Or
ange LED-
12
een-Orange LED+
Gr
CONN@
CONN@
low LED+
low LED-
+
TYCO_2010008-
TYCO_2010008-
1U_0603_10V4Z~D
1U_0603_10V4Z~D
C1105
C1105
1
1
2
2
LAN_ACTLED_YEL#_R
1
14
GND
15
GND
3
3
>ŝŶŬŽŶĞ
R1114 75_0402_1%~DR1114 75_0402_1%~D
R1112 75_0402_1%~DR1112 75_0402_1%~D
R1111 75_0402_1%~DR1111 75_0402_1%~D
B B
GND CHASSIS
A A
5
4
C1104 1000P_1808_3KV7K~DC1104 1000P_1808_3KV7K~D
GND_CHASSIS
1 2
THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONT AINS
DEPARTM
SED BY OR DISCLOSED TO ANY THIRD PARTY WITHO UT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE U
R1113 75_0402_1%~DR1113 75_0402_1%~D
3
DELL CONFIDE
Tit
Tit
tle
le
le
Ti
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
NTIAL/PROPRIETARY
Co
Co
Co
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
RJ45
RJ45
RJ45
LA
LA
LA
6611P
6611P
6611P
-
-
-
1
0.3
0.3
33 64We
33 64We
33 64We
of
of
of
0.3
5
SB_
GPIO27
U
1 2
R575 0_0402_5%
R575 0_0402_5%
USBP7
+
1 2
R576 1.
R576 1.
+3.3
V_ALW
1 2
R579
R579
1 2
R583
R583
1 2
R584 4.
R584 4.
1 2
R581 4.
R581 4.
D D
C C
B B
A A
12
@
@
I_TPM_TERM PC
2
1
1
2
+3
SCC_CM
1
2
R603
R603 10_0402_5%~
10_0402_5%~
4.7P
4.7P
_0402_50V8C~D
_0402_50V8C~D
@
@
C486
C486
XI
27.12M
27.12M C492
C492 12P_0402_50V
12P_0402_50V
.3V_ALW
DVCC_N_R
@
@
10U_0805_10V4Z
10U_0805_10V4Z
@
@
C509
C509
~D
~D
1 2
1.5K
1.5K
1 2
R589 2.
R589 2.
1 2
R585 2.
R585 2.
1 2
R592 2.
R592 2.
1 2
R586 4.
R586 4.
1 2
R596 4.
R596 4.
PCI_TPM
CLK_
D
D
R610 1K
R610 1K
R615 4.
R615 4.
1 2
R612 10M
R612 10M
Y4
Y4
1
IN
2
GND
HZ_12PF_1N227120CC0B~D
HZ_12PF_1N227120CC0B~D
1 2
R632 4.
R632 4.
1 2
R635 4.
R635 4.
@
@
R637
R637
0_0402_5%~
0_0402_5%~
T154PAD
T154PAD
~D
~D
+SC_
0.22U_0402_10V
0.22U_0402_10V
2
C510
C510
1
6K~D
6K~D
SC_RST
SC SC_ SC_ SC_ SC_
R646
R646
_0402_5%~D
_0402_5%~D
S
S
I2301CDS-T1-GE3_SOT23- 3~D
I2301CDS-T1-GE3_SOT23- 3~D
~D@
~D@
5K_0402_5%~D
5K_0402_5%~D
TRST1#_USH
PL
_0402_5%~D@
_0402_5%~D@
10K
10K
US
CEN
H_LP
4.
4.
7K_0402_5%~D1@
7K_0402_5%~D1@
LPD#
7K_0402_5%~D@
7K_0402_5%~D@
SERIRQ_R
IRQ_
7K_0402_5%~D
7K_0402_5%~D
MBCLK
USH_S
2K_0402_5%~D
2K_0402_5%~D
H_SMBDAT
US
2K_0402_5%~D
2K_0402_5%~D
M5882_ALERT#
BC
2K_0402_5%~D
2K_0402_5%~D
_PWR_STATE#
USH
7K_0402_5%~D
7K_0402_5%~D
H_OC1
USB
7K_0402_5%~D
7K_0402_5%~D
JT
AG_RST#_USH
1 2
_0402_5%~D
_0402_5%~D
2@
2@
USH_LP
1 2
7K_0402_5%~D
7K_0402_5%~D
1 2
R627 0_0402_5%
R627 0_0402_5%
_0402_5%~D@
_0402_5%~D@
3
OUT
4
VCC
_CLK
8J~D
8J~D
GND
D
D
IO C4 C8 DET
1
C493
C493 15P_0402_50V
15P_0402_50V
2
RADJ
PO
7K_0402_5%~D
7K_0402_5%~D
1
CLKDIV
7K_0402_5%~D
7K_0402_5%~D
RADJ
PO
1
CLKDIV
2
CLKDIV
M5882_SCRST
BC
DVCC_N
SCC_CM
12
M5882_GPIO25
BC BC
M5882_GPIO26
AUX1UC
UC
AUX2
M5882_IO
BC BCM5882_SCDET
M5882_SCCLK
BC
SC_VCC should be 3X wide as regular SC trace width to carry ~60mA max. current per ISO spec C510 and C509 should be p laced very close to SC cage pin
JSC1
CONN@JSC1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
TYCO_1-2041084-0~D
TYCO_1-2041084-0~D
5
Q36
Q36
1 3
D
D
G
G
2
CEN
REF
REF
8J~D
8J~D
1 2
R631 4.
R631 4.
1 2
R633 4.7K
R633 4.7K
U34
U34
18
POR
adj
6
CLK
DIV1
7
CLK
DIV2
3
RST
IN
5
CMDV
CCN
2
EN_
5V/3VN
4
_1.8VN
EN
21
AUX1
UC
22
AUX2
UC
20
I/OU
C
19
OFFN
23
XTAL1
25
GPAD
A8034HN_HVQFN24_4X4~D
A8034HN_HVQFN24_4X4~D
TD
TD
>ŝŶŬŽŶĞ
+3
.3V_ALW_PCH
S
S
R580
R580
4.7K
4.7K
_0402_5%~D
_0402_5%~D
1 2
7
7
Q3
Q3 S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
13
D
D
GPIO27
USB_
2
G
G
S
S
CL
K_PCI_TPM15
LPC_LA
D014,35,42,43
LPC_LA
D114,35,42,43
LPC_LA
D214,35,42,43 D314,35,42,43
LPC_LA LPC_LF
RAME#14,35,42,43
IRQ_
SERIRQ14,35,42,43
PLT
RST_USH#17
SP_T
PM_LPC_EN35,42
USH_S
MBCLK43
USH_S
MBDAT43
BC
M5882_ALERT#42
_PWR_STATE#42
USH
_XOUT
~D
~D
_XIN
All XTAL components and traces should be placed/layout on top layer. The gnd/pwr layer below will provide shielding from
27.12Mhz interference which might affect cellular certification.
PO
RADJ
7K
7K
_0402_5%~D@
_0402_5%~D@
CLKDIV
_0402_5%~D
_0402_5%~D
1
VDD(
intf)
17
VDD
16
VDDP
15
VCC
14
RST
13
CLK
9
I/O
10
AUX1
11
AUX2
8
PRESN
24
XTAL2
12
GND
USBP7 USBP7
K_PCI_TPM
CL
D0
LPC_LA
D1
LPC_LA
D2
LPC_LA
D3
LPC_LA
RAME#
LPC_LF
1 2
R600 0_0402_5%
R600 0_0402_5%
R602 0_0402_5%
R602 0_0402_5%
R604 0_0402_5%
R604 0_0402_5%
DET
SC_
COEX_STATUS2
BT_
R613 0_0402_5%
R613 0_0402_5%
0.1U_0402_16V
0.1U_0402_16V
1
2
2
4Z~D
4Z~D
+SC_
VCC
R638 0_0402_5%~
R638 0_0402_5%~
1 2
R639 22_0402_5%~
R639 22_0402_5%~
1 2
R640 100_0402_5%~
R640 100_0402_5%~
1 2
R641 0_0402_5%~DR641 0_0402_5%~D
1 2
R642 0_0402_5%~
R642 0_0402_5%~
1 2
R643 0_0402_5%~
R643 0_0402_5%~
1 2
+SC_
WůĂĐĞϱϬϴĐůŽƐĞƚŽ hϯϰƉŝŶϭϱ
0_0402_5%~
0_0402_5%~
1 2
-17
1 2
+17
R588
R588 0_0402_5%~
0_0402_5%~
R593 0_0402_5%~
R593 0_0402_5%~
1 2
R594 0_0402_5%~
R594 0_0402_5%~
1 2
R595 0_0402_5%~
R595 0_0402_5%~
1 2
R597 0_0402_5%~
R597 0_0402_5%~
1 2
R598 0_0402_5%~
R598 0_0402_5%~
1 2
1 2
1 2
R606 150_0402_5%~
R606 150_0402_5%~
1 2 1 2
R1581 0_0402_5%~
R1581 0_0402_5%~
1 2
1 2
R619 1K
R619 1K
1 2
R622 1K
R622 1K
1 2
R624 1K
R624 1K
+3
.3V_ALW
0.1U_0402_16V
0.1U_0402_16V
1
1
C497
C497
C498
C498
2
2
4Z~D
4Z~D
D
D
D
D D
D
VCC
.47U_0402_6.
.47U_0402_6.
2
C508
C508
3V6-K~D
3V6-K~D
1
+3
SPI_ SPI_ SPI_
SPI_
R587
R587
~D@
~D@
~D
~D
~D
~D
SMB_G
WR_STATE#_R
USH_P
~D
~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
10U_0805_10V6M
10U_0805_10V6M
C499
C499
~D
~D
D
D
D
D
10P_0402_50V
10P_0402_50V
2
1
8J~D
8J~D
.3V_ALW
R645 4.
R645 4.
TXD CLK RST
CS
BC
M5882_GPIO15
USH_S USH_S BC
C506
C506
1 2
4
D
D
-_R
USBP7 USBP7
USB_
D
D
IRQ_
PL USH_LP
M5882_ALERT#
PIO1
SB POR
+5
2
1
2
1
U36
U36
1 2 3 4
M45PE16-VMW6T G_SO8W8~D
M45PE16-VMW6T G_SO8W8~D
P5
+_R
P6
GPIO27
N7
P2
D
D
N3
D
D
M4
D
D
K5
D
D
N4
D
D
K4
SERIRQ_R
L4
TRST1#_USH
M3
CEN
M5
LPD#
N6
MBCLK
M9
MBDAT
L9 K9
D
D
M7
N8
D@
D@
L7
K1
P1
E12
OOT
_EXTR
V_ALW
10U_0805_10V6M
10U_0805_10V6M
0.1U_0402_16V
0.1U_0402_16V
1
C501
C501
C500
C500
2
4Z~D
4Z~D
~D
~D
RST
SC_ SC
_CLK
SC_
IO
SC_C4
C8
SC_
DET
SC_
10P_0402_50V
10P_0402_50V
C507
C507
8J~D
8J~D
RST
SPI_
7K_0402_5%~D
7K_0402_5%~D
D
Q
C
VSS
RESET
VCC
#
S#
W#
1 2
R647 4.7K_0402_5%~DR647 4.7K_0402_5%~D
4
U33A
U33A
USB
D_DN
USB
D_UP
USB
D_ATTACH_GPIO_2 7
LCLK LAD
0_GPIO_20
LAD
1_GPIO_21
LAD
2_GPIO_22
LAD
3_GPIO_23
LFR
AME_N_GPIO_18
LSE
RIRQ_GPIO_19
LRE
SET_N_GPIO_17
LPC
EN
LP
CPD_N_GPIO_24
SMBC
LK
SMBD
AT
SMBAL
ERT_N
SMB_
GPIO_0 GPIO_1
SMB_
W
AKEU
_EN
IDDQ
_PWRDN
CORE
DO_PWRDN
AL
8 7 6 5
BCM5882
BCM5882
P_N
.3V_ALW
+3
4.
4. 7K
7K _0402_5%~D
_0402_5%~D
R629
R629
1 2
+3
.3V_ALW
+3
.3V_ALW
.3V_ALW
+3
0.
0. 1U_0402_16V
1U_0402_16V
1
C513
C513
4Z~D
4Z~D
2
RXD
SPI_
M5882_GPIO15
BC
USB
H_DN_0
USBH
_UP_0
USB
H_OC_0
USB
H_DN_1
USBH
_UP_1
USB
H_OC_1
SSP_C
LK0_GPIO_6
SSP_F
SS0_GPIO_7
SSP_R
XD0_GPIO_8
SSP_T
XD0_GPIO_9
SSP_C
LK1_GPIO_10
SSP_F
SS1_GPIO_11
SS
P_RXD1_GPIO_12
SPI
SPI
LPC
LPC
SSP_
XD1_GPIO_13
T
SC SC_
_SEL5V_GPIO_25
SC
_SEL18V_GPIO_26
SC
SC
SC_
SC_
_PWR_N14
SC
_PWR_P14
SC
SM BUS
SM BUS
Smard Card
Smard Card
BC
BC
5.1M
5.1M
_0402_5%~D
_0402_5%~D
R630
R630
1 2
3.3M
3.3M
_0402_5%~D
_0402_5%~D
R634
R634
1 2
ADER_RXP
RFRE
3
2
A204U_SOT323-3~D@
A204U_SOT323-3~D@
D25 D
D25 D
3
2
A204U_SOT323-3~D@
A204U_SOT323-3~D@
D27 D
D27 D
ADER_RXN
RFRE
Component
R494,R498
SC_
M5882KFBG_FBGA 196~D
M5882KFBG_FBGA 196~D
1
1
RFID MODE
VOLTAGE
NOPOP
R555,R633
3K
R634
C641,C647
NOPOP
NOPOP
D28,D29 POP
D31-D34
.3V_ALW
+3
L41 B
L41 B
3.3U_0603_10V
3.3U_0603_10V
1
2
6K~D
6K~D
POP NOPOP
LM18BB100SN1D_2P~D
LM18BB100SN1D_2P~D
C515
C515
FP_
P7
FP_
P8
USBH
P9
P11 P12
USBH
P10
I_CLK
SP
G3
SPI_
G2
SPI_
H1
SPI_
H2
BCMG
C3
BCMG
B2
BCMG
A2
BCMG
A1
R607 0_0402_5%~
R607 0_0402_5%~
M11
_CLK
R608 0_0402_5%~
R608 0_0402_5%~
M12
FCB
R609 0_0402_5%~
R609 0_0402_5%~
F2
R611 0_0402_5%~
R611 0_0402_5%~
F1
R614 0_0402_5%~
R614 0_0402_5%~
M2
DET
_
R616 0_0402_5%~
R616 0_0402_5%~
L11
IO
R620 0_0402_5%~
R620 0_0402_5%~
M10
RST
N14 P14
SC_
L10
VCC
.2V_ALW_AVDD
+1
1U_0402_6.3V
1U_0402_6.3V
2
6K~D
6K~D
1
C502
C502
1 2
4Z~D
4Z~D
0.1U_0402_16V
0.1U_0402_16V
C505
C505
1 2
0.1U_0402_16V
0.1U_0402_16V
4Z~D
4Z~D
CURRENT
3K
NOPOP3K
NOPOP
150P
D_AVDD3P3
+RFI
12
1U_0603_10V6K
1U_0603_10V6K
2
C516
C516
1
~D
~D
3
+3
.3V_ALW
1 2
R577 4.
R577 4.
1 2
R578 4.
R578 4.
1 2
R582
R582
USBD­USBD+
_OC0#
R590 4.
R590 4.
_OC1
CS RXD TXD
PIO_10 PIO_11 PIO_12 PIO_13
12 12 12 12 12 12 12
+SC_
PWR
TEST
R623 0_0402_5%
R623 0_0402_5%
1U_0402_6.3V
1U_0402_6.3V
1
2
C494
C494
C495
C495
6K~D
6K~D
2
1
READER_RXP_C
RF
+3.3
V_ALW
READER_RXN_C
RF
V_ALW
+3.3
0.1U_0402_16V
0.1U_0402_16V
1
C517
C517
2
4Z~D
4Z~D
3
4.
4.
FP_
USBD- 23
FP_
USBD+ 23
12
7K_0402_5%~D
7K_0402_5%~D
T146
T146
PAD~D
PAD~D
T147
T147
PAD~D
PAD~D
T148
T148
PAD~D
PAD~D
T150
T150
PAD~D
PAD~D
SCC_CM
12
.5V_ALW_AVDD
+2
10U_0603_6.3V
10U_0603_6.3V
C490
C490
2
6M~D
6M~D
1
RF
DA204U_SOT323-3~D
DA204U_SOT323-3~D
RFREADER_TXN1
DA204U_S
DA204U_S
.5V_ALW_AVDD
+2
RST
_N
7K_0402_5%~D
7K_0402_5%~D
OVST
B
7K_0402_5%~D
7K_0402_5%~D
RESET#
FP_
7K_0402_5%~D
7K_0402_5%~D
@
@ @
@ @
@ @
@
M5882_SCCLK
D
D
BC AUX1
D
D
BC
M5882_GPIO25
D
D
BC
M5882_GPIO26
D
D
M5882_SCDET
D
D
BC
M5882_IO
D
D
BC BC
M5882_SCRST
D
D
DVCC_N
~D
~D
1U_0402_6.3V
1U_0402_6.3V
2
C488
C488
6K~D
6K~D
1
READER_TXP1
3
2
D26
@D26
@
3
2
@
@
D28
D28
OT323-3~D
OT323-3~D
L42 B
L42 B
1U_0603_10V6K
1U_0603_10V6K
2
C518
C518
1
~D
~D
+3
.3V_ALW
UC
4.7U_0603_6.
4.7U_0603_6.
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C489
C489
C496
C496
3V6K~D
3V6K~D
2
150NH_LLQ1608-
150NH_LLQ1608-
150NH_0805CS-
150NH_0805CS-
1
150NH_0805CS-
150NH_0805CS-
1
150NH_LLQ1608-
150NH_LLQ1608-
LM18BB100SN1D_2P~D
LM18BB100SN1D_2P~D
D_AVDD2P5
+RFI
12
1U_0603_10V6K
1U_0603_10V6K
2
C519
C519
1
~D
~D
10U_0603_6.3V
10U_0603_6.3V
1
6M~D
6M~D
2
JT
J
JT
JTAG
JTAG
JTC
HF
HF
C491
C491
@
@
L45
L45
FR15G_2%~D
FR15G_2%~D
1 2
L39
L39
331EKTS_2%
331EKTS_2%
1 2
L40
L40
331EKTS_2%
331EKTS_2%
1 2
1 2
@
@
FR15G_2%~D
FR15G_2%~D
1
2
AG_CLK_USH
R591
R591
@
@
0_0402_5%~
0_0402_5%~
1 2
AG_TDI_USH
T
AG_TDO_USH
@
@
R599
R599 0_0402_5%~
0_0402_5%~
1 2
_TMS_USH
_RST#_USH
@
@
R605
R605 0_0402_5%~
0_0402_5%~
1 2
E_USH
_RX_TEST0
HF
@
@
R621
R621 0_0402_5%~
0_0402_5%~
1 2
_RX_TEST1
_RX_TEST2
HF
R618
R618
@
@
0_0402_5%~
0_0402_5%~
1 2
_RX_TEST3
15K_0402_1%
15K_0402_1%
15K_0402_1%~D
15K_0402_1%~D
L46
L46
0.1U_0402_16V
0.1U_0402_16V
C520
C520
4Z~D
4Z~D
2
D
D
D
D
D
D
1 2
D
D
D
D
R625 0_0402_5%~
R625 0_0402_5%~
1 2
R628 0_0402_5%~
R628 0_0402_5%~
1 2
12
R636
R636
~D
~D
390P_0603_50V
390P_0603_50V
C503
C503
1
2
8G~D
8G~D
12
R644
R644
390P_0603_50V
390P_0603_50V
C511
C511
1
2
8G~D
8G~D
.2V_ALW_AVDD
+1
1U_0603_10V6K
1U_0603_10V6K
1
2
~D
~D
JT JT JT JT JTAG JTC
@
@
R601
R601
D
D
0_0402_5%~
0_0402_5%~
@
@
T145PAD
T145PAD
~D
~D
1K_0402_5%
1K_0402_5%
@
@
R626
R626
~D
~D
1 2
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C487 0.01U_0402_16V
C487 0.01U_0402_16V
390P_0603_50V
390P_0603_50V
C504
C504
1
2
8G~D
8G~D
390P_0603_50V
390P_0603_50V
C512
C512
1
2
8G~D
8G~D
LM18BB100SN1D_2P~D
LM18BB100SN1D_2P~D
L43 B
L43 B
+RFI
12
1U_0603_10V6K
1U_0603_10V6K
1
C521
C521
2
~D
~D
2
AG_CLK_USH AG_TDI_USH AG_TDO_USH AG_TMS_USH
_RST#_USH
E_USH
SCAN
USH_T
D
D D
D
1 2
.2V_ALW_AVDD
+1
.5V_ALW_AVDD
+2
D_AVDD1P2
C514
C514
_XIN
REF RE
_XOUT
F
_N
RST
TB
OVS
ACCMODE
OOT
SB
ESTMODE
_EXTR
POR
RF RF
1
2
TAG_VRXP TAG_VRXN
0.1U_0402_16V
0.1U_0402_16V
C522
C522
4Z~D
4Z~D
G14
F14
G1
L1 M1 N1 N2
L3
L2
E1
E3
E2
D1
J14
U33D
U33D
RE
FCLK_XTALIN
RE
FCLK_XTALOUT
RST
JTA
G_TCK
JTA
G_TDI
JTA
G_TDO
JTA
G_TMS
JTA
G_TRSTN
JTC
E
OVST
SCAN
SE
CURE_BOOT
TEST
POR
A6 B6
C5
A5
7K~D
7K~D
B4
C6 E6
D6 B5
A4
1
BCM5882
_N
B
ACCMODE
MODE
_EXTR
U33C
U33C
RFIDTAG_VRX_P
HF_
RFIDTAG_VRX_N
HF_
RFIDTAG_VTX
HF_
RFIDTAG_VREF
HF_
HF_
RFIDTAG_DVDD1P2
RFIDTAG_AVDD2P 5_C6
HF_
RFIDTAG_AVDD2P 5_E6
HF_
HF_
RFIDTAG_AVSS _D6
HF
_RFIDTAG_AVSS_B5
HF_
RFIDTAG_DVSS
BCM5882
UART
UART UART UART
UART
UART
JTAG CLK
JTAG CLK
BC
BC
M5882KFBG_FBGA 196~D
M5882KFBG_FBGA 196~D
BCM5882
BCM5882
BC
BC
_TX_GPIO_1
_RX_GPIO_0 _CTS_GPIO_2 _RTS_GPIO_3
GPI GPI GPI
CLK
RST
PO
R_MONITOR
ESTOUT
PLL_T
HF_
RX_ADC_AVDD1P2
HF_ HF
_TX_AVDD3P3_B7
HF
HF HF
M5882KFBG_FBGA 196~D
M5882KFBG_FBGA 196~D
D4 C4 B3 A3
L14
NC
J1
GPI
O_4
D2
O_14
C2
O_15
B1
O_16
D3
OUT
C1
OUT_N
J13
K1
SWV
C13
TX_P
HF_
TX_N
HF_
RX_P
HF_
RX_N
HF_
_RX_TEST0
HF
_RX_TEST1
HF HF
_RX_TEST2
HF
_RX_TEST3
_TX_AVDD1P2
HF
_RX_AVDD1P2
HF
_RX_AVDD2P5
HF HF
_TX_AVDD2P5
TX_AVDD3P3_D8
HF
_TX_AVSS_C7
HF
_TX_AVSS_C8
HF
_TX_AVSS_E7
HF
_RX_AVSS_A9
_RX_AVSS_B11
_RX_ADC_AVSS1 _RX_ADC_AVSS2
1
UART UA
CO SCC_CM BC
CLKO
SPI_
PO
SWV
PLL
Changed to 0.5 pitch same as JBIO1
READER_TXN1_PI
RF
READER_TXP1_PI
NTACTLESS_DET#18
CO
RF
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Co
Co
Co
mpal Electronics, Inc.
mpal Electronics, Inc.
Tit
Tit
Title
le
le
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
mpal Electronics, Inc.
H BCM5882 (1/2)
H BCM5882 (1/2)
H BCM5882 (1/2)
US
US
US
LA-
LA-
LA-
6611P
6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
6611P
1
_TX/GPIO1 _RX/GPIO0
RT
BT_
NTACTLESS_DET#
DVCC_N_R
M5882_GPIO15
BT
UT
T144
T144
RST
R_MONITOR
_TESTOUT
RF
READER_TXP1
A8
RFRE
B8
RF
READER_RXP
A10
RF
READER_RXN
B10
HF
_RX_TEST0
B9
HF
_RX_TEST1
C9
HF
_RX_TEST2
C10
HF
_RX_TEST3
E9
+RFI
D_AVDD1P2
D7 F8 D10
I
D_AVDD2P5
+RF
F9 A7
D_AVDD3P3
+RFI
D8 B7
C7 C8 E7
A9 B11
E8 D9
T
T
YCO_2041070-6~D
YCO_2041070-6~D
>ŝŶŬŽŶĞ
34 64Wednes
34 64Wednes
34 64Wednes
R666
R666
@
@
0_0402_5%~
0_0402_5%~
D
D
FP_
RESET# 23
COEX_STATUS2 44
_PRI_STATUS 44
@
@
PAD~D
PAD~D
T149
T149
PAD~D
PAD~D
T151
T151
PAD~D
PAD~D
T153
T153
PAD~D
PAD~D
ADER_TXN1
JCS1
JCS1
CONN@
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
of
of
of
12
@
@
@
@
@
@
0.3
0.3
0.3
5
D D
.3V_ALW
+3
C C
LOW:Power Down Mode High:Working Mode
B B
R650 0_0402_5%
R650 0_0402_5%
_LPC_EN34,42
SP_TPM
LP
C_LAD014,34,42,43
LP
C_LAD114,34,42,43 C_LAD214,34,42,43
LP LP
C_LAD314,34,42,43
CLK_PCI_TPM_CHA15
_LFRAME#14,34,42,43
LPC
1 2
PCH_PLTRST#_EC14,17,37,38,42,43
IRQ_
SERIRQ14,34,42,43
42,43
CLKRUN#16,
4.7K_0402_5%~D@
4.7K_0402_5%~D@
.3V_RUN
+3
12
R657
@R657
@
10K_0402_5%~D
10K_0402_5%~D
12
R659
4@ R659
4@
1K_0402_5%~D
1K_0402_5%~D
5
+3
.3V_RUN
R656
R656
A A
1 2
R649 0_0402_5%
R649 0_0402_5%
1 2
R648 0_0402_5%
R648 0_0402_5%
1 2
R651 0_0402_5%
R651 0_0402_5%
1 2
R652 0_0402_5%~D4@ R652 0_0402_5%~D4@
1 2
R653 0_0402_5%
R653 0_0402_5%
1 2
R654 0_0402_5%
R654 0_0402_5%
1 2
R655 0_0402_5%
R655 0_0402_5%
1 2
12
R658
@R658
@
10K_0402_5%~D
10K_0402_5%~D
12
R660
4@R660
4@
1K_0402_5%~D
1K_0402_5%~D
China TCM: NationZ & Jetw
~D4@
~D4@ ~D4@
~D4@ ~D4@
~D4@ ~D4@
~D4@
LPC_LFRAME#_R
~D4@
~D4@
I_RST#_R
PC
~D4@
~D4@
IRQ_SERIRQ CLKRUN#
~D4@
~D4@
TCM_BA0
BA1
TCM_
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
1
C_T
PM_LPC_EN LPC LPC LPC LPC
_R
TCM_ TCM_
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
C527
C527
1
2
C536
C536
1
_LAD0_R _LAD1_R _LAD2_R _LAD3_R
BA1 BA0
TCM V
NationZ
Jetway
4
2
1
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
C537
C537
ender
4
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
C528
C528
2
1
28 26 23 20 17
21 22 16 27 15
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
7 3 9
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
1
C538
C538
4@
4@
LP LAD LAD LAD LAD
LCLK LFRAME# LR SERIR CLKRUN# PP BA_1 BA_0
SSX4
SSX4
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
C529
C529
C530
C530
1
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
2
C539
C539
1
1
U37
U37
CPD#
0 1 2 3
ESET#
Q
4-B_TSSOP28~D
4-B_TSSOP28~D
POP
R660, C554, C550
R659,
C555, RH315
3
+1
.2V_ALW_PLL
1U
1U
10U_0603_6.3V6M~D
1U
1U
1
_0402_6.3V6K~D
_0402_6.3V6K~D
C524
+VD
2
DC_5882
2
1
C524
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
C543
C543
1U
1U
1U
1U
1U
1U
10U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
2
2
C531
C531
C532
C532
1
1
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
2
2
C541
C541
C
C 540
540
1
1
10U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0603_6.3V6M~D
_0603_6.3V6M~D
C534
C534
1
2
C533
C533
2
1
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
C542
C542
10U_0603_6.3V6M~D
1
1
_0402_6.3V6K~D
_0402_6.3V6K~D
C525
C525
C526
C526
_PWR
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
2
2
C545
C545
C544
C544
1
1
+SC
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
2
1
2
2
C546
C546
C547
C547
1
1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C1161
C1161
2
1U
1U
10U
10U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0603_6.3V6M~D
_0603_6.3V6M~D
1
C548
C548
C549
C549
2
ay co-lay
.3V_RUN
+3
10
VDD_0 VDD_1 VDD_2
GN GN GN
GND_
NC_12 NC
D_11 D_18 D_25
NC_5
NC_1 NC_2 NC_6 NC_8
NC_P
19 24
11 18 25 4
4
WAY_PIN5
JET
5 12
AY_CLK14M
JETW
13
_13
1 2 6 8 14
1
C554
C554
4@
4@
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
4@
4@
2
2
C551
C551
1
1
JETWAY_CLK14M 15
JETWAY_PIN5
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
4@
4@
C552
C552
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
4@
4@
2
C553
C553
1
2
@C555
@
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
4@C550
4@
1
C550
2
C555
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
TCM circuit
PART
USH_LPCEN
SIO 5028 ->SP_TPM_LPC_EN
PCH GPIO39 ->TPM_ID1
PCH GPIO38 ->TPM_ID0
+1
+2
+3
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
C535
C535
1
2
.2V_ALW_PLL
+1 .2V_ALW_AVDD
.5V_ALW_AVDD
.3V_ALW
4.
4. 7U_0603_6.3V6K~D
7U_0603_6.3V6K~D
1
C523
C523
2
+1
.2V_ALW_PLL
+VD
.3V_ALW
+3
/PIN
DC_5882
U33B
U33B
H14
DD_1P2I_REF
AV
A11
DD_1P2O_A11
AV
A12
DD_1P2O_A12
AV
H13
DD_2P5I
AV
E10
AV
DD_2P5O_E10
E11
DD_2P5O_E11
AV
A13
V
DD25_LDO12_A13
A
B12
DD25_LDO12_B12
AV
A14
AVDD25
_PLL_A14
D11
AVDD33
_LDO25
P13
P_PWR
OT
D14
VDD_1P2I
PLL_A
E14
VDD_1P2O
PLL_A
C14
PLL_D
VDD_1P2I
D13
VDDC_D1
3
F3
3
VDDC_F
J4
4
VDDC_J
J5
VDDC_J
5
J6
6
VDDC_J
J7
7
VDDC_J
J8
8
VDDC_J
J10
VDDC_J
10
J11
11
VDDC_J
K7
VDDC_K7
K8
VDDC_K8
E4
VD
DO_33_E4
J2
DO_33_J2
VD
K3
VD
DO_33_K3
L8
DO_33_L8
VD
N10
VD
DO_33_N10
G4
DO_33CORE_G4
VD
H3
VD
DO_33CORE_H3
H4
DO_33CORE_H4
VD
J3
VD
DO_33CORE_J3
M13
VD
DO_33SC_M13
N13
VD
DO_33SC_N13
L6
LPC_L6
VDDO_
M6
LPC_M6
VDDO_
K10
VDDO_
SC_K10
K12
SC_K12
VDDO_
L12
VDDO_
SC_L12
L13
VDDO
SC_L13
_
D5
VAR_D5
VDDO_
E5
VAR_E5
VDDO_
N5
VESD
5882 and China TCM Z8H172T Option
USH BCM
Ref Des TCM Enable
All 4@ POP
PU R583
PD R615
PU R772
PU RH268
PD RH271
PU RH267
PD RH270
@
POP @
@@
@
POP @
POP
@
1
BCM5882
BCM5882
C11
DO12
AVSS_L
AVSS_L AVSS_L
CM5882KFBG_FBGA196~D
CM5882KFBG_FBGA196~D
B
B
DO25_B13
DO25_C12
AVSS_PL
AVSS_R
_AVSS
PLL
PLL_D
POR_
VSSC_F VSSC_F VSSC_F
VSSC_F VSSC_F VSSC_F VSSC_F
VSSC_G
VSSC_G
VSSC_G
VSSC_G
VSSC_G
VSSC_G VSSC_G VSSC_G
VSSC_H
VSSC_H
VSSC_H
VSSC_H
VSSC_H VSSC_H VSSC_H VSSC_H
VSSC_J
VSSC_J
VSSC_K
VSSC_K VSSC_K VSSC_K
VSSC_L
VSSC_M
VSSC_M
VSSC_N VSSC_N VSSC_N
VSSC_
VSSC_P
VSS
AVSS
B13 C12
B14
L
F13
EF
D12
E13
G13
F4
4
F5
5
F6
6
F7
7
F10
10
F11
11
F12
12
G5
5
G6
6
G7
7
G8
8
G9
9
G10
10
G11
11
G12
12
H5
5
H6
6
H7
7
H8
8
H9
9
H10
10
H11
11
H12
12
J9
9
J12
12
K2
2
K6
6
K13
13
K14
14
L5
5
M8
8
M14
14
N9
9
N11
11
N12
12
P3
3
P
P4
4
TPM Enable ALL TPM/TCM Disable
@
POP
@
@
@
@
@
POP
POP
POP
@
@
POP
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
H BCM5882 (2/2)
H BCM5882 (2/2)
H BCM5882 (2/2)
US
US
US
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
-6611P
-6611P
-6611P
35 64Wedn
35 64Wedn
35 64Wedn
1
of
of
of
A
1 1
.3V_RUN
+3
R66
R66
1
@
1
@
0_0402_5%~D
0_0402_5%~D
.5V_RUN
+1
2 2
2
2
R66
R66 0_0402_5%~D
0_0402_5%~D
1 2
PC PC PC PC
IE_PRX_MMITX_P615 IE_PRX_MMITX_N615
IE_PTX_MMIRX_P615 IE_PTX_MMIRX_N615
1 2
+V
DDH_SD
4.
4.
0.
0.
7U_0603_10V6K~D
7U_0603_10V6K~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
C561
C561
C562
C562
1
1
2
2
CLK_
PCIE_MMI15
CLK_
PCIE_MMI#15
4.
4. 7U_0603_10V6K~D
7U_0603_10V6K~D
1
C556
C556
2
C569 0.
C569 0.
1 2
C571 0.
C571 0.
1 2
C567 0.
C567 0.
1 2
C568 0.
C568 0.
1 2
0.
0.
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
1
C557
C557
2
2
1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
MMI#17
PLTRST_
ICLK_REQ#15
MM
C558
C558
BLM
BLM
1 2
R677 191_0402_1%
R677 191_0402_1%
B
L44
L44
1 2
18BD601SN1D_0603~D
18BD601SN1D_0603~D
PC
IE_PRX_MMITX_P6_C IE_PRX_MMITX_N6_C
PC PC
IE_PTX_MMIRX_P6_C IE_PTX_MMIRX_N6_C
PC
+PE_
+PE_
VDDH
~D
~D
VDDH
_0402_16V4Z~D
_0402_16V4Z~D
0.1U
0.1U
16
9
32
2 1
6 7 5 4 3
33
13
14 31
2
2
C559
C559
1
1
_0402_16V7K~D
_0402_16V7K~D
0.01U
0.01U
U38
U38
3.3V
DDH VDDH PE_VDDH
MMI_
KP
PE_REFCL PE_REFCL
KM
PE_TXP PE_TXM PE_RXP PE_RXM PE_REXT
GPAD
PE_RST#
MUL MUL
SD_C
TI-IO1 TI-IO2
O
O
Z600FJ0LN_QFN32_5X5~D
Z600FJ0LN_QFN32_5X5~D
C560
C560
SKT_V VCC_OUT
MMI_
MMI_ MMI_ MMI_ MMI_ MMI_
MS
MD/MS_BS
MM
SD_CD#
SD_W
SD_D SD_D
MS_ MS_
DVDD AVDD
_CD#
I_CLK
C
+O
Z_DVDD
Z_AVDD
+O
10 8
VCC
+SKT_
17
CC
15
SD/M
MCDAT1_R
28
1
2 D0 D1 D2 D3 D4 D5 D6 D7
PI
MCDAT2_R
SD/M
26
SD/M
MCDAT0_R
29 27 25
SD/M
MCDAT3_R
24
MCDAT4_R
SD/M
23
SD/M
MCDAT5_R
22
MCDAT6_R
SD/M
21
SD/M
MCDAT7_R
20
11
SD/M
MCCMD_R
19
/MMC_CLK_R
SD
18 12 30
4.7U_0603_10V6K~D
4.7U_0603_10V6K~D
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C566
C566
1
1
C565
C565
2
2
R663 33_0402_5%
R663 33_0402_5%
1 2
R664 33_0402_5%
R664 33_0402_5%
1 2
R665 33_0402_5%
R665 33_0402_5%
1 2
R668 33_0402_5%
R668 33_0402_5%
1 2
R669 33_0402_5%
R669 33_0402_5%
1 2
R670 33_0402_5%
R670 33_0402_5%
1 2
R672 33_0402_5%
R672 33_0402_5%
1 2
R673 33_0402_5%
R673 33_0402_5%
1 2
R674 33_0402_5%
R674 33_0402_5%
1 2
R676 33_0402_5%
R676 33_0402_5%
1 2
1
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C573
C573
~D
~D ~D
~D ~D
~D
~D
~D ~D
~D ~D
~D ~D
~D ~D
~D
~D
~D ~D
~D
1
2
4.
4. 7U_0603_10V6K~D
7U_0603_10V6K~D
C574
C574
SD/M SD/M SD/M
SD/M SD/M SD/M SD/M SD/M
SD/M
/MMC_CLK
SD SD/M SDWP
1
2
MCDAT1 MCDAT2 MCDAT0
MCDAT3 MCDAT4 MCDAT5 MCDAT6 MCDAT7
MCCMD
MCCD#
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
4.
4. 7U_0603_10V6K~D
7U_0603_10V6K~D
C563
C563
1
C564
C564
2
.3V_RUN_CARD
+3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
D
MCDAT3
SD/M SD/M
MCCMD
+3
.3V_RUN_CARD
4.
4.
10K_0402_5%~D
10K_0402_5%~D
12
7U_0603_10V6K~D
7U_0603_10V6K~D
1
C572
C572
C570
C570
R826
R826
2
SD
/MMC_CLK
SD/M SD/M SD/M
SD/M SD/M SD/M SD/M
SD/M SDWP SD/M SDWP
MCDAT0 MCDAT1 MCDAT2
MCDAT4 MCDAT5 MCDAT6 MCDAT7
MCCD#
MCCD#
E
JSD
JSD
1
CONN@
1
CONN@
14
/SD1
DAT3
12
SD2
CMD/
10
SD3
VSS1/
9
VCC/SD4
8
SD5
CLK/
6
VSSS2/SD6
GND/
4
/SD7
DAT0
3
/SD8
DAT1
15
DAT2
/SD9
13
DAT4
/MMC10
11
/MMC11
DAT5
7
DAT6
/MMC12
5
/MMC13
DAT7
16
CD
_WP_SW/GND
17
_WP_SW/GND
CD
19
CD_SW
/SD
20
WP_
SW/SD
2
CD_SW
_TAISOL/SD
1
SW_TAISOL/SD
WP/
18
GND_
SW
T-SOL_156-4000000901_NR~D
T-SOL_156-4000000901_NR~D
>ŝŶŬŽŶĞ
3 3
4 4
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
OZ600F
OZ600F
OZ600F
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
J0
J0
J0
-6591P
-6591P
-6591P
E
36 64Wedn
36 64Wedn
36 64Wedn
of
of
of
5
+3
.3V_RUN
CARD2_DET#
USB_M
PCIE
D D
_MCARD2_DET#
R694
R694
R695
R695
1 2
12
100K_0402_5%~D
100K_0402_5%~D
+3
.3V_PCIE_WWAN
100K_0402_5%~D
100K_0402_5%~D
DDR_XDP_
DDR_XDP_
WAN_SMBCLK12,13,15,28
WAN_SMBDAT12,13,15,28
Mini WWAN/GPS/LTE/UWB H=5.2
+3
.3V_PCIE_WWAN
MI
C59
C59 C59
C59
.5V_RUN
1
2
33P
33P
_0402_50V8J~D
_0402_50V8J~D
C612
C612
7
7
1 2
9
9
1 2
1 2
R725
R725
33P
33P
_0402_50V8J~D
_0402_50V8J~D
C593
C593
1
2
22U
22U
_0805_6.3VAM~D
_0805_6.3VAM~D
NI1CLK_REQ#
CL
K_PCIE_MIN I1# K_PCIE_MIN I1
CL
IE_PRX_WANTX_N1
PC PC
IE_PRX_WANTX_P1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
IE_PTX_WANRX_N1_C
PC PC
IE_PTX_WANRX_P1_C
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
PCIE
0_0402_5%~D
0_0402_5%~D
0.
0. 047U_0402_16V4Z~D
047U_0402_16V4Z~D
1
C594
C594
2
33P
33P
_0402_50V8J~D
_0402_50V8J~D
C613
C613
1
C
C 614
614
2
_MCARD2_DET#_R
330U
330U
330U
330U
1
1
_D2E_6.3VM_R25~D
_D2E_6.3VM_R25~D
_D2E_6.3VM_R25~D
_D2E_6.3VM_R25~D
+
+
+
+
@
@
C615
C615
C1176
C1176
2
2
PWR Rail
MI
NI1CLK_REQ#15
CL
K_PCIE_MIN I1#15
C
K_PCIE_MIN I115
L
IE_PRX_WANTX_N115
PC PC
IE_PRX_WANTX_P115
PC
IE_PTX_WANRX_N115
P
IE_PTX_WANRX_P115
C
_MCARD2_DET#17
PCIE
C C
+1
.3V_PCIE_WWAN
+3
0.
0.
0.
0. 047U_0402_16V4Z~D
047U_0402_16V4Z~D
047U_0402_16V4Z~D
047U_0402_16V4Z~D
1
1
2
B B
1
C611
C611
C610
C610
2
2
+3.3V
+3.3Vaux
+1.5V
SIM Card Pu
M_PWR
+SI
UIM
A A
_RESET _CLK
UIM
1
6
6
C61
C61 1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
M1
CONN@
M1
CONN@
JSI
JSI
1
VCC
2
RST
3
CLK
4
NC
MOLEX_475531001~D
MOLEX_475531001~D
>ŝŶŬŽŶĞ
5
sh-Push
5
GND
6
VPP
7
I/O
8
NC
9
GND
10
GND
INI1
INI1
JM
JM
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
MOLEX_48338-1088~D
MOLEX_48338-1088~D
>ŝŶŬŽŶĞ
Voltage Tolerance
+-9%
+-9%
+-5%
UIM
_VPP _DATA
UIM
+3
.3V_PCIE_WWAN
CONN@
CONN@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
GND2
D_WWAN_OUT#
LE
Primary Power
Peak Normal
1000 750
330
500
UIM
UIM
R719
R719
_RESET
_CLK
33P
33P
_0402_50V8J~D
_0402_50V8J~D
1
2
1157
1157
R
R
R1158
R1158
1 2
@
@
C628
C628
4
12
0_0402_5%~D
0_0402_5%~D
12
0_0402_5%~D
0_0402_5%~D
_DATA
UIM UIM
_CLK _RESET
UIM UIM
_VPP
WW
AN_RADIO_DIS#
1 2
R704
R704
0_0402_5%~D
0_0402_5%~D
WW
AN_SMBCLK AN_SMBDAT
WW
USBP5­USBP5+
CARD2_DET#
USB_M
D_WWAN_OUT#LED_WWAN_OUT#
LE
USB_M
CARD2_DET#
.3V_PCIE_WWAN
+3
G
G
2
_0402_5%~D
_0402_5%~D
100K
100K
13
D
S
D
S
Q77
Q77
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Aux Power
250 (Wake enable) 5 (Not wake enable)
250
NA
375
U40
U40
1
2
3
33P
33P
_0402_50V8J~D
_0402_50V8J~D
@
@
1
RV05-4.TCT_SOT23-6~D
RV05-4.TCT_SOT23-6~D
S
S
C629
C629
2
4
.3V_PCIE_WWAN
+3
2.2K_0402_5%~D
2.2K_0402_5%~D
@
@
12
R11
R11
59
59
.5V_RUN
+1 +SI
M_PWR
USBP5­USBP5+
USB_M
1 2
R697
R697
Normal
@
@
2.2K_0402_5%~D
2.2K_0402_5%~D
@
@
12
R11
R11
60
60
WW
AN_SMBCLK
AN_SMBDAT
WW
WW
AN_RADIO_DIS# 42
H_PLTRST#_EC 14,17,35,38,42,43
PC
17 17
CARD2_DET# 18
PC
IE_MCARD2_DET#
0_0402_5%~D@
0_0402_5%~D@
RELESS_LED# 42,46
WI
_VPP
UIM
6
5
4
+SI
M_PWR
UIM
_DATA
33P
33P
33P
33P
_0402_50V8J~D
_0402_50V8J~D
_0402_50V8J~D
_0402_50V8J~D
@
@
@
@
1
1
C631
C631
C630
C630
2
2
3
1 2
0_0402_5%~D@
0_0402_5%~D@
R693
R693
WL
AN_RADIO_DIS#42
D31
D31
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
R
R
N_RADIO_DIS#_R
WLA
21
2
Mini WLAN/WIMAX H=4
.3V_WLAN
+3
_WAKE#
PCIE
_WAKE#29,38,42
PCIE
COEX2
_WLAN_ACTIVE _BT_ACTIVE
COEX1
NI2CLK_REQ#15
MI
CL
K_PCIE_MIN I2#15 K_PCIE_MIN I215
CL
DEBUG_RX43
HOST_
MSC
PCIE
_PRX_WLANTX_N215 _PRX_WLANTX_P215
PCIE
C596
0.
0. 047U_0402_16V4Z~D
047U_0402_16V4Z~D
PCIE
PCH_CL
PCH_CL
C604
C604
C596 C598
C598
_MCARD1_DET#18
_CLK115
_DATA115
R707
R707
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C605
C605
2
2
IE_PTX_WLANRX_N215 IE_PTX_WLANRX_P215
PC
H_CL_RST1#15
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
@
1
C603
C603
2
COEX2
_0402_50V8J~D
_0402_50V8J~D
33P
33P
+1
COEX2 COEX1
_WLAN_ACTIVE
@
@
C600
C600
.5V_RUN
0.
0. 047U_0402_16V4Z~D
047U_0402_16V4Z~D
1
C601
C601
2
_WLAN_ACTIVE44 _BT_ACTIVE44
PC PC
1
2
.3V_WLAN
+3
0.
0. 047U_0402_16V4Z~D
047U_0402_16V4Z~D
1
1
C602
C602
2
2
1/2 Minicard Flash Card H=4
COEX2
_WLAN_ACTIVE
NI3CLK_REQ#15
MI
CL
K_PCIE_MIN I3#15 K_PCIE_MIN I315
CL
PC
IE_PRX_WPANTX_N515 IE_PRX_WPANTX_P515
PC
C617
C617
IE_PTX_WPANRX_N515
PC PCIE_PTX_WPANRX_P515
PC
IE_MCARD3_DET#18
+3
.3V_RUN
+1
.5V_RUN
+3
.3V_PCIE_FLASH
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
C61
C61
9
9
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
@
@
1
1
C62
C62
0
0
2
1
C621
C621
2
2
1 2
C618
C618
1 2
1 2
R711 100K_0402_5%~DR711 100K_0402_5%~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1
C623
C623
C62
C62
2
2
2
2
R700
R700 R702
R702
LK43
PC PC
0.
0.
PC
1 2
PC
1 2
0.
0.
1 2
0_0402_5%~D
0_0402_5%~D
0.
0.
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C607
C607
C606
C606
2
_WAKE#
PCIE
1 2
R709
R709
MI
NI3CLK_REQ#
K_PCIE_MIN I3#
CL CL
K_PCIE_MIN I3
PCIE
_PRX_WPANTX_N5 _PRX_WPANTX_P5
PCIE
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
PCIE_PTX_WPANRX_N5_C
IE_PTX_WPANRX_P5_C
PC
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
PCIE
_MCARD3_DET#
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C62
C62
C62
C62
4
4
5
5
2
1 2
0_0402_5%~D
0_0402_5%~D
1 2
0_0402_5%~D
0_0402_5%~D
IE_PRX_WLANTX_N2 IE_PRX_WLANTX_P2
1U_0402_10V7K~D
1U_0402_10V7K~D
IE_PTX_WLANRX_N2_C IE_PTX_WLANRX_P2_C
1U_0402_10V7K~D
1U_0402_10V7K~D
IE_MCARD1_DET#
4.
4. 7U_0603_6.3V6K~D
7U_0603_6.3V6K~D
1
C608
C608
2
.3V_PCIE_FLASH
+3
0_0402_5%~D
0_0402_5%~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1
C62
C62
6
6
2
JM
JM
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
LOTES_AAA-PCI-073-P02-A
LOTES_AAA-PCI-073-P02-A
>ŝŶŬŽŶĞ
2
JM
JM
INI2
CONN@
INI2
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
GND2
MOLEX_48338-1088~D
MOLEX_48338-1088~D
>ŝŶŬŽŶĞ
INI3
CONN@
INI3
CONN@
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND2
1
PCIE
+3
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
WI
MAX_LED#
W
N_LED#
LA
.3V_PCIE_FLASH
+3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
54
USB_M
.3V_WLAN
+1
R710
R710
USBP6­USBP6+ USB_M
_MCARD1_DET#
CARD1_DET#
.5V_RUN
MSD
ATA
WLA
N_RADIO_DIS#_R
R703
R703
USBP4­USBP4+PC USB_M
AX_LED#
WIM
N_LED#
WLA
@
@
0_0402_5%~D
0_0402_5%~D
1 2
WIMAX_LED# STUDY FOR DEBUG
R705
R705
R718
R718
_0402_5%~D
_0402_5%~D
1 2
1 2
100K
100K
CARD3_DET#
USB_M
PCH_PL
12
0_0402_5%~D
0_0402_5%~D
CARD3_DET#
R712
R712
1
2
1 2
R692
R692
1 2
R698
R698
0_0402_5%~D@
0_0402_5%~D@
PC
IE_MCARD1_DET#
USB_M
CARD1_DET#
PCH_PL
12
0_0402_5%~D
0_0402_5%~D
CARD1_DET#
R70
R70
6
6
100K_0402_5%~D
100K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q12
Q12
4A
4A
R708
R708
.5V_RUN
+1
TRST#_EC
USBP6-
USBP6+
12
100K_0402_5%~D@
100K_0402_5%~D@
WPAN Noise
USB_MCARD3_DET#
C627
@C627
@
4700P_0402_25V7K~D
4700P_0402_25V7K~D
PCIE
R699
R699
R701
R701
TRST#_EC
.3V_WLAN
+3
4
61
1 2
17 17
100K_0402_5%~D
100K_0402_5%~D
_MCARD1_DET#
1 2
1 2
MSD
5
Q12
Q12
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Mini Card
Mini Card
Mini Card
LA
LA
LA
-6611P
-6611P
-6611P
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1
+3
.3V_ALW_PCH
.3V_RUN
+3
100K_0402_5%~D@
100K_0402_5%~D@
100K_0402_5%~D
100K_0402_5%~D
1 2
4700P_0402_25V7K~D
4700P_0402_25V7K~D
C595
C595
HOST_
DEBUG_TX 43
USBP4
17
­17
USBP4+
USB_M
CARD1_DET# 18
ATA 43
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
WI
WI
RELESS_LED#
RELESS_LED#
3
4B
4B
_MCARD3_DET#
PCIE
0_0402_5%~D@
0_0402_5%~D@
.3V_ALW_PCH
+3
/PROPRIETARY
37 64Wedn
37 64Wedn
37 64Wedn
of
of
of
5
4
3
2
1
WŽǁĞƌŽŶƚƌŽůĨŽƌDŝŶŝĐĂƌĚϮ
.3V_SUS
+3
RUN_O
TRST#_EC14,17,35,37,42,43
.3V_RUN
+3
+3
.3V_RUN
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C633
C633
2
1
2
R717 0_0402_5%
R717 0_0402_5%
N11,42,45,50
1 2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C634
C634
.5V_RUN
+1
1
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C635
C635
EXPRCRD_ST
~D
~D
PCH_PL
_A
LW
D D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
WOWL42
AUX_EN_
C C
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
MC
ARD_WWAN_PWREN42
B B
+15V
Q39
Q39
A
A
2
12
R71
R71
6
6
100K_0402_5%~D
100K_0402_5%~D
+15V_A
Q41
Q41
A
A
2
12
6
6
R72
R72 100K_0402_5%~D
100K_0402_5%~D
100K
100K
12
R713
R713
_0402_5%~D
_0402_5%~D
61
WŽǁĞƌŽŶƚƌŽůĨŽƌDŝŶŝĐĂƌĚϭ
LW
100K
100K
12
_0402_5%~D
_0402_5%~D
ARD_WWAN_PWREN#
MC
61
3
.3V_ALW
+
100K
100K
D
D
6
S
2 1
G
G
3
12
3
5
4
S
45
Q38
Q38 S
S
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
1
2
.3V_ALW
+3
100K
100K
_0402_5%~D
_0402_5%~D
R722
R722
D
D MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
Q41B
Q41B
12
R714
R714
_0402_5%~D
_0402_5%~D
D
D MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
3
Q39B
Q39B
5
4
R721
R721
3
.3V_WLAN
+
12
4700P
4700P
_0402_25V7K~D
_0402_25V7K~D
C632
C632
+3
Q40
Q40
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
D
D
6
S
S
45 2 1
G
G
3
4700P
4700P
1
_0402_25V7K~D
_0402_25V7K~D
C644
C644
2
R715
R715 20K
20K
_0402_5%~D
_0402_5%~D
.3V_PCIE_WWAN
12
S
S
13
D
D
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q73
Q73
S
S
@
@
R720
R720
0_0805_5%
0_0805_5%
1 2
R72
R72
3
3
1K_0402_5%~D
1K_0402_5%~D
M
ARD_WWAN_PWREN#
C
2
G
G
PCH_PL
~D
~D
WŽǁĞƌŽŶƚƌŽůĨŽƌDŝŶŝĐĂƌĚϯ
LW
+15V_A
100K
100K
12
R728
R728
_0402_5%~D
_0402_5%~D
61
Q43
Q43
A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
MCARD_MISC_PWREN42
A A
A
2
12
R73
R73
3
3
100K_0402_5%~D
100K_0402_5%~D
.3V_ALW
+3
100K
100K
D
D
6
S
_0402_5%~D
_0402_5%~D
12
R729
R729
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q43
Q43
B
B
5
4
S
Q42
Q42
2 1
S
S
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
G
G
3
45
4700P
4700P
1
_0402_25V7K~D
_0402_25V7K~D
2
.3V_PCIE_FLASH
+3
12
0
0
R73
R73 20K_0402_5%~D
20K_0402_5%~D
C650
C650
BCLK43
CARD_SM
CARD_SM
BDAT43
džƉƌĞƐƐĂƌĚWtZ^t
U41
U41
BY_R#
TRST#_EC
17
2
12
20
1 6
19
4
5 13 14 16
TP
TP
-17
USBP10
USBP10
+17
.3V_CARDAUX
+3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_SUS
2.
2. 2K_0402_5%~D
2K_0402_5%~D
12
R731
R731
12
AUXOUT
AUXIN
IN IN
6
6
C64
C64
R732
R732
OUT
3.3V OUT
1.5V
PERST#
CPPE#
CPUSB#
RCLKEN
GND
PAD
.3V_CARD
+3
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
3.3V
1.5V
SHDN# STBY# SYSRST# OC#
NC NC NC NC NC
S2231MRGPR-2_QFN20_4X4~D
S2231MRGPR-2_QFN20_4X4~D
2.
2. 2K_0402_5%~D
2K_0402_5%~D
15 3 11
8 10 9
18
7 21
R724
R724
R727
R727
4
1
PCIE_PTX_EXPRX_N315 PCIE_
4
1
L49
L49
C64
C64
CARD_RESET#
EXPRCRD_CPPE# CPUSB#
1 2
0_0402_5%~D@
0_0402_5%~D@
1 2
0_0402_5%~D@
0_0402_5%~D@
DLW
DLW
21SN900SQ2L_0805_4P~D
21SN900SQ2L_0805_4P~D
1
9
9
2
PTX_EXPRX_P315
3
3
2
2
PCIE PCIE_
+1
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
2
PCIE
EXPCLK
CLK_ CLK_
_PRX_EXPTX_N315
PRX_EXPTX_P315
C647 0.
C647 0. C648 0.
C648 0.
.5V_CARD
1
C637
C637
2
EXPRCRD_DET
_WAKE#29,37,42
_REQ#15
PCIE_EXP#15 PCIE_EXP15
1 2 1 2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
C638
C638
#18
1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
+3
.3V_CARD
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
1
1
C640
C640
2
2
EXPRCRD_DET USBP10 USBP10 CPUSB#
CARD_SM CARD_SM
CARD_RESET#
EXPRCRD_CPPE#
_PTX_EXPRX_N3_C
PCIE PCIE_PTX_EXPRX_P3_C
C641
C641
.3V_CARDAUX
+3
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C642
C642
2
+1
.5V_CARD
_D­_D+
BCLK BDAT
1
2
#
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
C643
C643
1
5
5
C64
C64
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TY
TY
>ŝŶŬŽŶĞ
CONN@
CONN@
JEXP1
JEXP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 GND GND
CO_2-2041070-6~D
CO_2-2041070-6~D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
IE-SATA SW / PCIE PWR
IE-SATA SW / PCIE PWR
IE-SATA SW / PCIE PWR
PC
PC
PC
LA
LA
LA
-6611P
-6611P
-6611P
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
38 64Wedn
38 64Wedn
38 64Wedn
of
of
1
of
5
D D
C C
USBP1_
D+
USBP1_
D-
D73
D73
@
@
4
L52
L52
DLW
DLW
USBP1+17
USBP1-17
SB_SIDE_PWR
+U
150U
2
3
U2BT_SOT23-3~D
U2BT_SOT23-3~D
1
PESD5V0
PESD5V0
150U
1
_B2_6.3V-M~D
_B2_6.3V-M~D
+
+
C657
C657
2
4
4
1
1
R737
R737
R739
R739
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C658
C658
2
USBP1_ USBP1_
3
21SN900SQ2L_0805_4P~D
21SN900SQ2L_0805_4P~D
3
3
2
2
1 2
0_0402_5%~D@
0_0402_5%~D@
1 2
0_0402_5%~D@
0_0402_5%~D@
D­D+
1 2 3
SUYIN_020173GR004M57QZL
SUYIN_020173GR004M57QZL
JU
JU
SB1
SB1
VBUS D­D+ GND4G1
USBP1_
USBP1_
CONN@
CONN@
G4 G3 G2
2
D+
D-
8 7 6 5
1
>ŝŶŬŽŶĞ
B B
A A
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Ti
tle
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
1
1
1
USB x
USB x
USB x
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
39 64We
39 64We
39 64We
of
of
1
of
5
D D
ESATA_PTX_
ESATA_PTX_
ESATA_PRX_
ESATA_PRX_
C C
4
ESATA Repeater
ESATA_PW
.3V_RUN
+3
ESATA_PTX_
DRX_P4_C14
ESATA_PTX_
DRX_N4_C14
ESATA_PRX_
DTX_N4_C14
ESATA_PRX_
DTX_P4_C14
1 2
R741 0_0402_5%
R741 0_0402_5%
DRX_P4_C
C664 0.
C664 0.
DRX_N4_C
C663 0.
C663 0.
DTX_N4_C
C666 0.
C666 0.
DTX_P4_C
C665 0.
C665 0.
+3
.3V_RUN
10K
10K
@
@
12
12
_0402_5%~D
_0402_5%~D
R1586
R1586
0_0402_5%
0_0402_5%
12
12
R1588
R1588
~D
~D
12
12
12
12
10K
10K
@
@
_0402_5%~D
_0402_5%~D
R1587
R1587
0_0402_5%
0_0402_5%
R1585
R1585
~D
~D
ESATA_PTX_
ESATA_PTX_
ESATA_PRX_
ESATA_PRX_
RSAVE
~D
~D
DRX_P4
01U_0402_16V7K~D
01U_0402_16V7K~D
DRX_N4
01U_0402_16V7K~D
01U_0402_16V7K~D
DTX_N4
01U_0402_16V7K~D
01U_0402_16V7K~D
DTX_P4
01U_0402_16V7K~D
01U_0402_16V7K~D
+ESATA_
EQ1
+ESATA_
EQ2
18
13 17 19 21
AX4951BECTP+TGH7_TQFN20_4X4~D
AX4951BECTP+TGH7_TQFN20_4X4~D
M
M
3
.3V_RUN
+3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1
C66
C66
2
2
1
1
X76M@
X76M@
U44
U44
7
EN CAD
1
AINP
2
AINM
4
BOUTM
5
BOUTP
3
GND GND GND GND EP
VCC VCC VCC VCC
AOUTP AOUTM
BINP
BINM
6 10 16 20
9
PA
8
PB
ESATA_PTX_
15
ESATA_PTX_
14
ESATA_PRX_
11
ESATA_PRX_
12
+ESATA_
+ESATA_
ESATA_PE1 ESATA_PE2
DRX_P4_RP DRX_N4_RP
DTX_P4_RP DTX_N4_RP
DEW2
DEW1
@
@
@
@
X76M
X76M
X76M
0_0402_5%
0_0402_5%
12
~D
~D
10K
10K
12
_0402_5%~D
_0402_5%~D
R1589
R1589
X76@
X76@
R1591
R1591
X76M
12
12
0_0402_5%~D
0_0402_5%~D
R1590
R1590
X76@ R1592
X76@
10K_0402_5%~D
10K_0402_5%~D
R1592
C662
C662
0_0402_5%~D
@
0_0402_5%~D
@
R74
R74
2
2
1 2
@
@
0_0402_5%
0_0402_5%
12
R745
R745
~D
~D
2
0_0402_5%~D
0_0402_5%~D
R74
R74
3
3
1 2
0_0402_5%
0_0402_5%
12
~D
~D
@
@
R746
R746
R1589 R1590
R1591 R1592
1
SA00003LH1L SA00003ZX0L
MAXIM TI
pop
depop
popdepop
+U
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
OUT OUT
T-PAD
3
2
D72
D72
ILIM
T1#
T#2
1 2
3
2
SB_SIDE_PWR
10 9 8 7 6 11
USBP2_
USBP2_
USBP2_
USBP2_
+5
V_ALW
10U
10U
_0805_10V4Z~D
_0805_10V4Z~D
C669
C669
1
2
B B
A A
5
PJP7
PJP7
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
C670
C670
2
MP_43X79
MP_43X79
JU
JU
112
+
USB_SI
ESATA_USB_
USBP2+17
USBP2-17
V_ALW_FUSE
5
DE_EN#42
PWR_EN#42
4
U45
U45
1
GND
FAUL
2
IN
3
IN
4
EN1# EN2#5FAUL
PS2560DRCR-PG1.1_SON10_3X3~D
PS2560DRCR-PG1.1_SON10_3X3~D
T
T
LW21SN900SQ2L_0805_4P~D
LW21SN900SQ2L_0805_4P~D
L50 D
L50 D
4
4
1
1
1 2
R734
R734
1 2
R735
R735
2
3
0U2BT_SOT23-3~D
0U2BT_SOT23-3~D
1
PESD5V
PESD5V
+SATA_
SIDE_PWR
+SATA_
ESATA_PTX_
ESATA_PTX_
ESATA_PRX_
ESATA_PRX_
SIDE_PWR
150U
150U
_B2_6.3V-M~D
_B2_6.3V-M~D
1
+
+
2
DRX_P4_RP
DRX_N4_RP
DTX_N4_RP
DTX_P4_RP
1
C667
C667
2
C671
C671
C672
C672
C673
C673
C674
C674
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
C668
C668
1 2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
SATA_PTX_
SATA_PTX_
SATA_PRX_
SATA_PRX_
USBP2_ USBP2_
DRX_P4
DRX_N4
DTX_N4
DTX_P4
JESA1
JESA1
CONN@
CONN@
1
VBUS
D-
2
D-
USB
D+
USB
3
D+
4
GND
5
GND
6
A+
ESATA
ESATA
7
A-
8
GND
9
B-
10
B+
11
GND
12
GND
13
GND
14
GND
15
GND
TY
TY
CO_2129160-3
CO_2129160-3
>ŝŶŬŽŶĞ
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
USB/E
USB/E
USB/E
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
SATA/IO
SATA/IO
SATA/IO
-6611P
-6611P
-6611P
1
40 64Wedn
40 64Wedn
40 64Wedn
of
of
of
B_OC0# 17
US
B_OC1# 17
US
12
7
7
R74
R74
24.9K_0402_1%~D
24.9K_0402_1%~D
D+
D-
D-
D+
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
>ŝŶŬŽŶĞ
O
O
CK1
CONN@
CK1
CONN@
JD
JD
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Sh
ield_G
155
Shield_G
156
Sh
ield_G
157
ield_G
Sh
158
Sh
ield_G
JAE_WD2F144WB3R300~D
JAE_WD2F144WB3R300~D
PWR2 PWR2 PWR2
GND2
Shield_G Sh
ield_G Shield_G Sh
ield_G
ield_G
Sh Sh
ield_G
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70
70
72
72
74
74
76
76
78
78
80
80
82
82
84
84
86
86
88
88
90
90
92
92
94
94
96
96
98
98
100
100
102
102
104
104
106
106
108
108
110
110
112
112
114
114
116
116
118
118
120
120
122
122
124
124
126
126
128
128
130
130
132
132
134
134
136
136
138
138
140
140
142
142
144
144
149 150 151 152
159 160 161 162 163 164
DPC_CA_
DO
DPC_ DPC_DO
DPC_DO DPC_DO
DPC_DO DPC_DO
DPC_DO DPC_DO
DPC_DO DPC_DO
DPC_PCH_
SATA_PRX_ SATA_PRX_
SATA_PTX_ SATA_PTX_
DOCK_
DET_R#
1
2
DET
CK_LANE_P0 CK_LANE_N0
CK_LANE_P1 CK_LANE_N1
CK_LANE_P2 CK_LANE_N2
CK_LANE_P3 CK_LANE_N3
CK_AUX CK_AUX#
DOCK_HPD
DKTX_P5 DKTX_N5
DKRX_P5 DKRX_N5
C703
0.
C703
0. 1U_0603_50V4Z~D
1U_0603_50V4Z~D
DOCK_
AC_OFF 42,57
DO
CK_LOM_SPD100LED_ORG# 32
CA_
DET 27
DPC_
1U_0402_10V7K~D
C691 0.
C691 0. C680 0.
C680 0.
C682 0.
C682 0. C684 0.
C684 0.
C693 0.
C693 0. C686 0.
C686 0.
C688 0.
C688 0. C694 0.
C694 0.
C697 0.
C697 0. C698 0.
C698 0.
C699 0.
C699 0. C700 0.
C700 0.
+DOCK_PWR_BAR
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
1U_0402_10V7K~D
1U_0402_10V7K~D
12
CK_AUX 27
DPC_DO
CK_AUX# 27
DPC_DO
CK_SRC# 57
ACAV_DO
DAT_
DDC2_DOCK 25
CLK_
DDC2_DOCK 25
01U_0402_16V7K~D
01U_0402_16V7K~D
12
01U_0402_16V7K~D
01U_0402_16V7K~D
12
01U_0402_16V7K~D
01U_0402_16V7K~D
1 2
01U_0402_16V7K~D
01U_0402_16V7K~D
1 2
17
USBP8+
USBP8-
17
USBP9+
17 17
USBP9-
KBD 43
CLK_ DAT_KBD
43
BREATH_L
ED# 43,46
CK_LOM_ACTLED_YEL# 32
DO
LOM_TRD0+ 32
DOCK_
DOCK_
LOM_TRD0- 32
LOM_TRD1+ 32
DOCK_
DOCK_
LOM_TRD1- 32
_VCT
+LOM
LOM_TRD2+ 32
DOCK_ DOCK_
LOM_TRD2- 32
LOM_TRD3+ 32
DOCK_
LOM_TRD3- 32
DOCK_
DCIN_IS+ 55
DOCK_
DCIN_IS- 55
DOCK_
POR_RST# 43
DOCK_
DOCK_DET#
DPC_PCH_
PCH_
DPC_
DPC_PCH_ DPC_PCH_
DPC_PCH_ DPC_PCH_
DPC_PCH_ DPC_
PCH_
SATA_PRX_ SATA_PRX_
SATA_PTX_ SATA_PTX_
+LOM
_VCT
1
@
@
C701
C701 1U
1U
2
D32
D32
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
R
R
1 2
R755
R755
AC_OFF
DOCK_
2
DOCK25
DOCK25
DOCK25
MSE43
BCLK#30 LRCK#30
DI30
DO#30
12MHZ#30
D042
AD142
AD242 AD342
DRQ1#42
SMB_CLK43
PSID47
4.
4. 7U_0805_25V6K~D
7U_0805_25V6K~D
@
@
C1162
C1162
DPD_CA_
CK25
RQ42
SLI
CE_BAT_PRES#
0.
0. 1U_0603_50V4Z~D
1U_0603_50V4Z~D
1
2
DOCK_DET_1
DET
DPD_ DPD_DO
DPD_DO DPD_DO
DPD_DO DPD_DO
DPD_DO DPD_DO
DPD_DO DPD_DO
BLUE_
RED_DO
GRE
EN_DOCK
3
C702
C702
DO
CK_LANE_P0 CK_LANE_N0
CK_LANE_P1 CK_LANE_N1
CK_LANE_P2 CK_LANE_N2
CK_LANE_P3 CK_LANE_N3
CK_AUX CK_AUX#
DOCK
CK
2
1
D33
D33
@
@
M24.TCT_SOT23-3~D
M24.TCT_SOT23-3~D S
S
DOCK_
LOM_SPD10LED_GRN#32
CA_
DET27
DPD_
1U_0402_10V7K~D
12 12
12 12
12 12
12 12
1
2
DOCK_
CE_BAT_PRES#42,47,57
SLI
OCK_PWR_BAR
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D 1U_0402_10V7K~D
1U_0402_10V7K~D
CK_AUX27
DPD_DO
DPD_DO
CK_AUX#27
+N
BDOCK_DC_IN_SS
BLUE_
RED_DO
EN_DOCK25
GRE
HSYNC_ VSYNC_
CLK_
MSE43
DAT_
DAI_ DAI_
DAI_
DAI_
DAI_
D_LA D_L
D_L D_L
FRAME#42
D_L
KRUN#42
D_CL
D_SERI
D_DL
PCI_DOCK17
CLK_
DOCK_
SMB_DAT43
DOCK_
SMB_ALERT#43,47,57
DOCK_
DOCK_
PWR_BTN#43
1
2
C690 0.
LANE_P016
DPD_PCH_
DPD_PCH_
LANE_N016
LANE_P116
DPD_PCH_
LANE_N116
DPD_PCH_
DPD_PCH_
LANE_P216 LANE_N216
DPD_PCH_
LANE_P316
DPD_PCH_
DPD_PCH_
LANE_N316
B B
DPD_PCH_
DOCK_HPD16
7
7
R75
R75
110K_0402_1%~D
110K_0402_1%~D
A A
DPD_PCH_
Cl
ose to DOCK
Its for Enhance ESD on dock issue.
DPD_PCH_
DOCK_HPD
12
PCI_DOCK
CLK_
12
R75
R75
6
6
33_0402_5%~D
33_0402_5%~D
1
C704
C704
_0402_50V8J~D
_0402_50V8J~D
12P
12P
2
C690 0. C679 0.
C679 0.
C681 0.
C681 0. C683 0.
C683 0.
C692 0.
C692 0. C685 0.
C685 0.
C687 0.
C687 0. C689 0.
C689 0.
DOCK_HPD
033U_0402_16V7K~D
033U_0402_16V7K~D
0.
0.
+D
C695
C695
LANE_P0 16 LANE_N0 16
LANE_P1 16 LANE_N1 16
LANE_P2 16 LANE_N2 16
LANE_P3 16 LANE_N3 16
DKTX_P5_C 14 DKTX_N5_C 14
DKRX_P5_C 14 DKRX_N5_C 14
_0402_6.3V6K~D
_0402_6.3V6K~D
21
+3.3V_ALW
100K_0402_5%~D
100K_0402_5%~D
1
DOCK_
DPC_PCH_
se to DOCK
12
DOCK_HPD 16
R75
R75 110K_0402_1%~D
110K_0402_1%~D
1
C696
C696
033U_0402_16V7K~D
033U_0402_16V7K~D
0.
0.
2
Clo Its for Enhance ESD on dock issue.
DPC_PCH_
DOCK_HPD
DET# 42
8
8
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
DOCKING
DOCKING
DOCKING
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
CONN
CONN
CONN
-6611P
-6611P
-6611P
41 64Wedn
41 64Wedn
41 64Wedn
of
of
of
5
.3V_ALW
LI
ARD_MISC_PWREN38
DCIN_
2S_NB_CODEC#30
USH_PW
OCK_PWR_BAR57 PANEL_ ENVDD_PCH16,
PSI
PBAT_
AUD_NB_
LCD_ CCD_O
SLI
CE_BAT_PRES#41,47,57
SLI
CHARGE_ DEFA
D_SATA_PCIE#_DET29
BC
SLP_
LA
SYS_
TUR_PWR_ALRT#55
SIO
RELESS_LED#37,46
WI
PCH_PCI
AN_RADIO_DIS#37
WL
RELESS_ON#/OFF31
WI
AN_RADIO_DIS#37
PCH_DPWROK16
D_CL_SIO#
CRT_
CBL_DET#47
_WAKE#29,37,38
PCIE
USB_SI
R_STATE#34
BKEN_EC24
LCD_
DISABLE#47
D_
PRES#47,
DOCKED32
DOCK_
VCC_TEST_EN24
FF24 NB_SENSE30,31
PWR_EN#40
MO
DULE_ON57
CE_BAT_ON57
MODULE_BATT57
ULT_OVRDE57
CPU_DET
ZODD_
M5882_ALERT#34
SUSACK#16
ME_CSW_DEV#18
N_DISABLE#_R32
CHARGE_ LED_MASK#46
_EXT_WAKE#18
E_WAKE#16
ADIO_DIS#44
SYS_
CPU_VT
+3
12
R805
R805 100K
100K
1
6
6
C71
C71
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
SWITCH25
DE_EN#40
TST24
DET#41
MUTE#30
PBATT57
ECT#7
WAKE#29
R1132
R1132
EN57
R797 0_0402_5%
R797 0_0402_5%
PWROK7,16
T_ON52,56
_0402_5%~D
_0402_5%~D
807
807
R
R
1 2
1 2
+3
.3V_ALW
_WAKE#
1 2
R800
R800
PCIE
10K_0402_5%~D
10K_0402_5%~D
DCIN_
CBL_DET#
100K_0402_5%~D
100K_0402_5%~D
CPU_DET
100K_0402_5%~D
100K_0402_5%~D
SLI
CE_BAT_PRES#
100K_0402_5%~D
100K_0402_5%~D
DYN_
TUR_PWR_ALRT#
_0402_5%~D
_0402_5%~D
USB_SI
10K_0402_5%~D
10K_0402_5%~D
ESATA_USB_
10K_0402_5%~D
10K_0402_5%~D
WI
100K_0402_5%~D
100K_0402_5%~D
SP_TPM
10K_0402_5%~D@
10K_0402_5%~D@
LCD_
100K_0402_5%~D
100K_0402_5%~D
SYS_
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
VGA
ECT#
DE_EN#
PWR_EN#
RELESS_ON#/OFF
_LPC_EN
TST
LED_MASK#
VGA_
_ID
0
MC
EN_I
EN_D
24
57
ARD_WWAN_PWREN38
MC
AUD_HP_
ESATA_USB_
DULE_BATT_PRES#47,57
MO CHARGE_
MO
DYN_
ID
WW
BT_R
1 2
R759
R759
1 2
R761
R761
1 2
R763
R763
1 2
R760
+3
.3V_ALW2
+3
.3V_RUN
R760
R796 10K
R796 10K
R768
R768
R769
R769
R766
R766
R772
R772
R767
R767
R775
R775
.3V_ALW
+3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
D D
C C
B B
Discrete
UMA 1
4
12
10_0402_5%~D
10_0402_5%~D
SWITCH
CRT_
ARD_MISC_PWREN
MC
CBL_DET#
DCIN_ LI
D_CL_SIO#
PCIE
_WAKE#
USB_SI
DE_EN#
EN_I
2S_NB_CODEC#
R_STATE#
USH_PW
OCK_PWR_BAR
EN_D PANEL_
BKEN_EC ENVDD_PCH LCD_
TST
DISABLE#
PSID_ PBAT_PRES# DOCKED
DET#
DOCK_
MUTE#
AUD_NB_
ARD_WWAN_PWREN
MC LCD_
VCC_TEST_EN
FF
CCD_O AUD_HP_
NB_SENSE
PWR_EN#
ESATA_USB_
DULE_ON
MO SLI
CE_BAT_ON CE_BAT_PRES#
SLI MO
DULE_BATT_PRES#
MODULE_BATT
CHARGE_ CHARGE_
PBATT
DEFA
ULT_OVRDE
ECT#
CPU_DET
MO
D_SATA_PCIE#_DET
ZODD_
WAKE#
882_ALERT#
BCM5
SUSACK#_
0_0402_5%~D
0_0402_5%~D
VGA_
ID
ME_CSW_DEV#
SLP_
N_DISABLE#_R
LA
EN
CHARGE_ SYS_
LED_MASK#
DYN_
TUR_PWR_ALRT#
RELESS_LED#
WI
E_WAKE#
PCH_PCI WL
AN_RADIO_DIS#
WI
RELESS_ON#/OFF
ADIO_DIS#
BT_R WW
AN_RADIO_DIS#
PWROK
SYS_
CPU_VTT_ON
1 2
R802
R802
3
.3V_ALW
+3
GPIOI1
GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7
LAD LAD LAD LA
ME#
ESET#
DLAD0 DLAD1 DLAD2 DLAD3
_CLK
OUT
P_LDO
VSS
1
C706
C706
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
SIO
B6
3
0.
75V_DDR_VTT_ON
A60
SIO
1
A6
SIO
5
B6
IMV
A6
2
1 2
B6
6
R765
R765
3
A6
AUX_EN_
B67
0
3 4 5 6 7
0
2 3 4 5 6 7
6
1
0 1 2 3
D
LK
0# 1#
RQ
E#
1#
RQ
NT#
AT
D
65
IN
EP
WL
A64
SIO
A5
SIO
B6 A6 B7 A7 B8
A8 B9 B10 A10 B11 A11 B12 A12
B60 A57 B64 B68 A9 B1 A18 A44
B34 B39 B51
A27 A26 B26 B25 A21 B22 A28 B2 A23 A22 B21 A32 B35
B2 B2 A2 A2 B23 A1 B24 A20
A29 B31 A30
A4
B56
B19
B46
B27 C1
0
9 8 5 4
9
IO_PSID_SELECT
GP MO DOCK_ DOCK_
ME_ MASK_
8V_RUN_PWRGD
1. D_SATA_DIAG_OUT#
LE
P_ALERT#_R
TEM
RUN_O SPI_
5048_GP 5048_GP 5048_GP 5048_GP 5048_GP 5048_GP 5048_GP 5048_GP
5048_GP 5048_GP 5048_GP
LPC LPC LPC LPC LPC PCH_ CLK CLKRUN# LPC LPC IRQ_ CLK EC
_32KHZ_ECE5048
D_LA D_LA D_LA D_LA D_LFR D_CL D_DL D_SERI
BC
_INT#_ECE5048 _DAT_ECE5048
BC BC
_CLK_ECE5048
RUNPWR
SP_TPM
R804
R804
+CA
1
C70
C70
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
_SLP_A#
_SLP_S4# _SLP_S3# P_PGOOD
0_0402_5%~D
0_0402_5%~D
WOWL
AN_LAN_DISB#
_SLP_LAN# _SLP_SUS#
DC_EN
HP_DET MIC_DET
FWP
SATA_LED#
1 2
R773
R773
N
RUN_O
WP#_SEL
IOL0
R1567 10K
R1567 10K
IOL1
R1568 10K
R1568 10K
1 2
IOL2
R1569 0_0402_5%
R1569 0_0402_5%
1 2
IOL3
R1570 0_0402_5%
R1570 0_0402_5%
1 2
IOL4
R1571 0_0402_5%
R1571 0_0402_5%
1 2
IOL5
R1572 0_0402_5%
R1572 0_0402_5%
1 2
IOL6
R1573 0_0402_5%
R1573 0_0402_5%
1 2
IOL7
R1574 0_0402_5%
R1574 0_0402_5%
1 2
I0M1
R1575 0_0402_5%
R1575 0_0402_5%
1 2
I0M3
R1576 0_0402_5%
R1576 0_0402_5%
1 2
I0M4
R1577 0_0402_5%
R1577 0_0402_5%
1 2
_LAD0 _LAD1 _LAD2 _LAD3 _LFRAME#
TRST#_EC
PL
_PCI_5048
_LDRQ0# _LDRQ1#
SERIRQ
_SIO_14M
D0 D1 D2 D3
AME# KRUN# DRQ1#
RQ
OK
_LPC_EN
12
1K_0402_5%~D
1K_0402_5%~D
P_LDO
+CAP_LDO trace width 20 mils
1
C71
C71
4
4
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
7
7
_SLP_A# 16,51
SIO
75V_DDR_VTT_ON 50
0. _SLP_S4# 16
SIO SIO
_SLP_S3# 16
P_PGOOD 53
IMV
IM
VP_VR_ON 53
AC_OFF_EC
DOCK_
WOWL 38
AUX_EN_
AN_LAN_DISB# 32
WL
SIO
_SLP_LAN# 16,32 _SLP_SUS# 16
SIO
IO_PSID_SELECT 47
GP MO
DC_EN 29
DOCK_
HP_DET 30
DOCK_
MIC_DET 30
ME_
FWP 14
MASK_
SATA_LED# 46
1.
8V_RUN_PWRGD 50
LE
D_SATA_DIAG_OUT# 46
0_0402_5%~D
0_0402_5%~D
N 11,38,45,50
SPI_
WP#_SEL 14
_0402_5%~D@
_0402_5%~D@
12
_0402_5%~D
_0402_5%~D
LPC
_LAD0 14,34,35,43
LPC
_LAD1 14,34,35,43
LPC
_LAD2 14,34,35,43 _LAD3 14,34,35,43
LPC
_LFRAME# 14,34,35,43
LPC
PC
H_PLTRST#_EC 14,17,35,37,38,43
CLK
_PCI_5048 17
CLKRUN#
_LDRQ0# 14
LPC LPC
_LDRQ1# 14
Q_SERIRQ 14,34,35,43
IR CLK_
SIO_14M 15
EC
_32KHZ_ECE5048 43
D0 41
D_LA
D1 41
D_LA D_LA
D2 41 D3 41
D_LA
AME# 41
D_LFR
KRUN# 41
D_CL
DRQ1# 41
D_DL
RQ 41
D_SERI
BC
_INT#_ECE5048 43
BC
_DAT_ECE5048 43
_CLK_ECE5048 43
BC
RUNPWR
OK 7,43
SP_TPM_LPC_EN 34,35
1
C705
LID
_CL# 31,46
B5
A17
B30
A43
U46
U46
B52
GPIOA
0
A49
GPIOA
1
B53
2
GPIOA
A50
3
GPIOA
B54
GPIOA
4
A51
GPIOA
5
B55
6
GPIOA
A52
7
GPIOA
A33
0
GPIOB
B36
GPIOB
1
A34
2
GPOC
B37
3
GPOC
A35
GPOC
4
B38
5
GPOC
A36
6/TACH4
GPOC
A37
7
GPIOC
B40
GPIOD
0
A38
1
GPIOC
B41
0
GPIOC
A39
7
GPIOB
B42
6
GPIOB
A40
GPIOB
5
B43
4
GPIOB
A41
GPIOB
3
B44
2
GPIOB
B32
1
GPIOD
A31
GPIOD
2
B33
3
GPIOD
B15
GPIOD
4
A15
5
GPIOD
B16
GPIOD
6
A16
GPIOD
7
A1
OE0/RXD
GPI
B2
GPI
OE1/TXD
A2
2/RTS#
GPIOE
B3
GP
IOE3/DSR#
A3
4/CTS#
GPIOE
B45
GPIOE
5/DTR#
A42
GP
6/RI#
IOE
B4
IOE7/DCD#
GP
A59
GPIOF
0
B62
1
GPIOF
EC
A58
GPIOF
2
B61
IOF3/TACH8
GP
A56
GP
IOF4/TACH7
B59
GPIOF
5
A55
6
GPIOF
B58
GPIOF
7
B47
/TACH5
GPIOG0
A4
5
GPIOG1
B4
8
GPIOG2
A4
6
GPIOG3
~D
~D
B4
9
GPIOG4
7
A4
GPIOG5
B5
0
GPIOG6
A48
/TACH6
GPIOG7
B13
GPIOH
0
A13
1
GPIOH
A53
SYSO
PT1/GPIOH2
B57
SYSO
PT0/GPIOH3
B14
GPIOH4
A14
GPIOH
5
B17
GPIOH6
B18
GPIOH
0_0402_5%~D@
0_0402_5%~D@
7
A54
VCC1
VCC1
VCC1
VCC1
VCC1
CE5048-LZY_DQFN132_11X11~D
CE5048-LZY_DQFN132_11X11~D
E
E
2
14.318M
C705 10U
10U
_0805_6.3V6M~D
_0805_6.3V6M~D
GPIOI2
1/TACH1
GPIOJ GPIOJ
2/TACH2
1/TACH3
GPIOK
GP
IOL0/PWM7 IOL1/PWM8
GP
IOL2/PWM0
GP GP
IOL3/PWM1 IOL4/PWM3
GP GP
IOL5/PWM2
GP
IOL7/PWM5
GPIOM 3/PWM4
GPIOM
4/PWM6
GPIOM
LFRA
LR
CLKRUN#
LDRQ LDRQ
SER_I
HZ/GPIOM0
CLK
32/GPIOM2
DLFRAM DCLKRUN#
DLDRQ
DSER_I
BC_I
BC_D BC
PWRG
TEST_P
CA
DB
DB
Version 0.4
Version 0.4
/TACH0
GPIOJ
GPIOJ GPIOJ GPIOJ GPIOJ GPIOJ
GPIOK
GPIOK GPIOK GPIOK GPIOK GPIOK GPIOK
GPIOL
PCIC
1
2
~D
~D ~D@
~D@ ~D
~D ~D@
~D@ ~D
~D ~D
~D
~D@
~D@ ~D
~D ~D
~D
16,35,43
C708
C708
0.
0.
2
1U_0402_10V7K~D
1U_0402_10V7K~D
ACAV_
DOCK_
TEMP
_ALERT# 18
10P_0402_50V8J~D
10P_0402_50V8J~D
1
C70
C70
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
I
N_NB 43,55,57
AC_OFF_EC 57
CLK_
SIO_14M
10_0402_5%
10_0402_5%
C71
C71
R794
R794
1
1
C710
.3V_ALW
5
P
B
A
G
U47
U47
3
TC
TC
CLK
R795
R795 10_0402_5%
10_0402_5%
_0402_50V8J~D
_0402_50V8J~D
10P
10P
C710
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
C711
C711
1 2
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
4
2 1
O
D34
D34
R
R
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
7SH08FU_SSOP5~D
7SH08FU_SSOP5~D
_PCI_5048
12
~D
~D
1
C713
C713
2
AC_OFF 41,57
DOCK_
12
R770
R770
_0402_5%~D
_0402_5%~D
33K
33K
AN_LAN_DISB#
WL
ME_
D_CL
D_SERI
D_DL
RUN_O
CPU_VT
75V_DDR_VTT_ON
0.
SLI
R771
R771
FWP
R793
R793
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KRUN#
R777
R777
RQ
R780
R780
DRQ1#
R782
R782
N
R786
R786
T_ON
R789
R789
R790
R790
CE_BAT_ON
R791
R791
12
100K_0402_5%~D@
100K_0402_5%~D@
12
1K_0402_5%~D@
1K_0402_5%~D@
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
12
100K_0402_5%~D
100K_0402_5%~D
+3
+3
.3V_ALW
.3V_RUN
9
9
+3
1
2
12
~D
~D
1
2
2
2
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DELL CONFIDENTIAL
C
C
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mpal Electronics, Inc.
mpal Electronics, Inc.
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Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
ECE5048
ECE5048
ECE5048
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
42 64Wedn
42 64Wedn
42 64Wedn
of
of
1
of
.3V_ALW
+3
1 2
R814 100K_0402_5%
R814 100K_0402_5%
R816 100K_0402_5%
R816 100K_0402_5%
R817 100K_0402_5%
R817 100K_0402_5%
R818 2.2K
R818 2.2K
R820 2.
R820 2.
R821 100K_0402_5%
R821 100K_0402_5%
R827 2.2K
R827 2.2K
D D
R828 2.2K
R828 2.2K
C C
B B
1 2
1 2
1 2
1 2
7 8
ACES_85204-06001~D
ACES_85204-06001~D
JT
AG_RST#
G1
@
G1
@
JDE
JDE
7
G1
8
G2
ACES_85204-06001~D
ACES_85204-06001~D
12
12
2K
2K
12
@
@
JTA
JTA
G1 G2
+3
1
1
2
2
3
3
4
4
5
5
6
6
32 KHz Clock
_XTAL2
MEC
MEC
_XTAL1
A A
WůĂĐĞĐůŽƐĞůLJƉŝŶϮϵ
CL
K_PCI_MEC
4.7P
4.7P
_0402_50V8C~D
_0402_50V8C~D
5
BC
_DAT_ECE5048
~D
~D
BC
_DAT_EMC4022
~D
~D
_DAT_ECE1117
BC
~D
~D
SMBDAT
PBAT_
_0402_5%~D
_0402_5%~D
SMBCLK
PBAT_
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
G2
G2
.3V_ALW
12
12
LPC_LDRQ
~D@
~D@
CHARG
ER_SMBDAT
CHARG
ER_SMBCLK
.3V_ALW
+3
49.9_0402_1%
49.9_0402_1%
12
~D
~D
1
1
2
2
3
3
4
4
5
5
6
6
10K_0402_5%
10K_0402_5%
R824
R824
JTAG_RST# citcuit close to U51.B57
~D
~D
100_0402_5%~
100_0402_5%~
1
@
@
R836
R836
#_MEC
10K_0402_5%
10K_0402_5%
12
R857
R857
~D
~D
0.1U_0402_16V
0.1U_0402_16V C735
C735
2
D
D
4Z~D
4Z~D
+3
.3V_ALW
10K_0402_5%
10K_0402_5%
12
12
R847
R847
~D
~D
LK
MSC MSDATA
1 2
R853 0_0402_5%~DR853 0_0402_5%~D
1 2
R855 0_0402_5%~
R855 0_0402_5%~
C741
C741
1 2
33P_0402_50V
33P_0402_50V
8J~D
8J~D
Y6
Y6
G
G
1
G
G
HZ_12.5PF_Q13MC1461000~D
HZ_12.5PF_Q13MC1461000~D
32.768K
32.768K
C743
C743
1 2
8J~D
8J~D
39P_0402_50V
39P_0402_50V
12
10_0402_5%~
10_0402_5%~
@
@
R885
R885
@
@
1
D
D
C747
C747
2
5
10K_0402_5%
10K_0402_5%
12
R858
R858
~D
~D
10K_0402_5%
10K_0402_5%
R848
R848
~D
~D
34
2
+3.3V_RUN
PCH
35,42
1
2
L1_SMBDATA15
SM
L1_SMBCLK15
SM
PBAT_
DOCK
_CLK_ECE504842
BC
BC
_DAT_ECE504842
BC
_INT#_ECE504842
_CLK_EMC402222
BC
BC
_DAT_EMC402222
BC
_INT#_EMC402222
BC
_CLK_ECE111744
_DAT_ECE111744
BC
_INT#_ECE111744
BC
_PLTRST#_EC14,17,35,37,38,42
R859
R859
10K_0402_5%
10K_0402_5%
12
~D
~D
10K_0402_5%
10K_0402_5%
12
~D
~D
1
1
2
2
R849
R849
D
D
R860
R860
100K_0402_5%
100K_0402_5%
@
@
12
R850
R850
~D
~D
HO HO
1.05V
VCC
10K_0402_5%
10K_0402_5%
~D
~D
1 2
JT JTA JT JTA
ST_DEBUG_TX ST_DEBUG_RX
_VTTPWRGD52,56
SAPWROK56
R861
R861
A
G_TDI G_TMS
AG_CLK
G_TDO
JTA
JTA
G1
G1
@SHORT PADS~D
@SHORT PADS~D
@
@
_32KHZ_ECE504842
EC
ĞƉŽƉƵůĂƚĞĚZϴϲϳĨŽƌϱϬϮϴƵƐĞ
.3V_ALW
+3
R875
R875 33K_0402_5%
33K_0402_5%
BOARD_ID
@
@
R1179
R1179
10K_0402_5%
10K_0402_5%
1 2
PR
OCHOT#_EC
1 2
R812 100K
R812 100K
need to discuss with BIOS the pop option.
1 2
1
2
~D
~D
2
G
G
_0402_5%~D@
_0402_5%~D@
R1181 0_0402_5%~
R1181 0_0402_5%~
4700P_0402_25V
4700P_0402_25V
C744
C744
7K~D
7K~D
13
D
D
S
S
.3V_ALW
+3
5
B
A
3
CLK_
TP_SIO44
DA
T_TP_SIO44
CL
K_KBD41
DAT
_KBD41
CLK_
MSE41
DAT
_MSE41
SMBDAT47
PBAT_
_POR_RST#41
S_
ON45
SU
BREAT PCH_A
PWM_EC24
BIA_
HDDC_EN28
_SLP_S5#16
SIO
ACAV_
SIO
_EXT_SMI#17
SI
O_RCIN#18
IRQ
_SERIRQ14,34,35,42
K_PCI_MEC17
CL
LPC_LF
LPC_LA LPC_LA LPC_LA LPC_LA
CLKRUN#16,
_EXT_SCI#18
SIO
MEC
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
@
@
Q47
Q47
1 2
P
G
SMBCLK47
BEEP30
RAME#14,34,35,42
U50
U50
TC
TC
AUX_ H_LED#41,46 LW_ON45
D014,34,35,42 D114,34,35,42 D214,34,35,42 D314,34,35,42
_XTAL2
~D
~D
1 2
4
O
7SH08FU_SSOP5~D
7SH08FU_SSOP5~D
ON32
IN_NB42, 55,57
R1068 0_0402_5%
R1068 0_0402_5%
1 2
R867 0_0402_5%
R867 0_0402_5%
*
4
C720
C720
0.1U_0402_16V
0.1U_0402_16V
1.05V
_0.8V_PWROK 14,53
L1_SMBDATA
SM
L1_SMBCLK
SM
TP_SIO
CLK_
T_TP_SIO
DA
K_KBD
CL
_KBD
DAT CLK_
MSE
_MSE
DAT PBAT_
SMBDAT
PBAT_
SMBCLK
A
G_TDI
JT
G_TDO
JTA
AG_CLK
JT
G_TMS
JTA
AG_RST#
JT
C736
C736
0.1U_0402_16V
0.1U_0402_16V
1 2
DOCK
_POR_RST#
SUS_
ON
AUX_
ON
BREAT
H_LED#
PCH_A
LW_ON
BIA_
PWM_EC
HDDC_EN
_CLK_ECE5048
BC
_DAT_ECE5048
BC BC
_INT#_ECE5048 _CLK_EMC4022
BC BC
_DAT_EMC4022
BC
_INT#_EMC4022
BC
_CLK_ECE1117
B
_DAT_ECE1117
C
_INT#_ECE1117
BC BEEP
_SLP_S5#
SIO
IN_NB
ACAV_
SIO
_EXT_SMI#
SI
O_RCIN#
LPC_LDRQ
#_MEC
IRQ
_SERIRQ
PCH
_PLTRST#_EC
CL
K_PCI_MEC
LPC_LF
RAME# D0
LPC_LA
D1
LPC_LA
D2
LPC_LA
D3
LPC_LA CLKRUN#
_EXT_SCI#
SIO
MEC
_XTAL1
C_XTAL2_R
ME
12
~D@
~D@
R875 C744
240K 4700p 130K 4700p
4700p
62K
4700p
33K
4700p
8.2K 4700p
4.3K
2K
4700p
1K
4700p
D
D
4
4Z~D
4Z~D
+RTC
H_PR
~D
~D
_CELL
R815
R815 0_0402_5%~
0_0402_5%~
1 2
1
2
U51
U51
PS/2 INT
PS/2 INT
A5
IO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GP
B6
IO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
GP
A37
IO110/PS2_CLK2/GPTP-IN6
GP
B40
IO111/PS2_DAT2/GPTP-OUT6
GP
A38
IO112/PS2_CLK1A
GP
B41
IO113/PS2_DAT1A
GP
A39
IO114/PS2_CLK0A
GP
B42
IO115/PS2_DAT0A
GP
B59
IO154/I2C1C_DATA/PS2_CLK1B
GP
A56
IO155/I2C1C_CLK/PS2_DAT1B
GP
JTAG INTERFACE
JTAG INTERFACE
A51
IO145/I2C1K_DATA/JTAG_TDI
GP
B55
IO146/I2C1K_CLK/JTAG_TDO
GP
B56
IO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GP
A53
IO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
GP
B57
G_RST#
JTA
4Z~D
4Z~D
FAN PWM & TACH
FAN PWM & TACH
B22
IO050/FAN_TACH1
GP
A21
IO051/FAN_TACH2
GP
B23
IO052/FAN_TACH3
GP
B24
IO053/PWM0
GP
A23
IO054/PWM1
GP
B25
IO055/PWM2
GP
A24
IO056/PWM3
GP
BC-LINK
BC-LINK
A43
IO123/BCM_A_CLK
GP
B45
IO122/BCM_A_DAT
GP
A42
IO121/BCM_A_INT#
GP
A12
IO022/BCM_B_CLK
GP
B13
IO023/BCM_B_DAT
GP
A13
IO024/BCM_B_INT#
GP
B20
IO044/BCM_C_CLK
GP
A18
IO043/BCM_C_DAT
GP
B19
IO042/BCM_C_INT#
GP
A20
IO047/LSBCM_D_CLK
GP
B21
IO046/LSBCM_D_DAT
GP
A19
IO045/LSBCM_D_INT#
GP
A16
IO032/GPTP-IN3/BCM_E_CLK
GP
B16
IO31/GPTP-OUT2/BCM_E_DAT
GP
A15
IO30/GPTP-IN2/BCM_E_INT#
GP
HOST INTERFACE
HOST INTERFACE
A6
IO011/nSMI
GP
A27
IO061/LPCPD#
GP
9
B2
LDRQ#
A28
IRQ
SER_
B30
ESET#
LR
A29
_CLK
PCI
B31
ME#
LFRA
0
A3
LAD0
2
B3
LAD1
1
A3
LAD2
3
B3
LAD3
2
A3
CLKRUN#
A33
IO100/nEC_SCI
GP
MASTER CLOCK
MASTER CLOCK
A61
XTAL1
A62
XTAL2
B62
GPIO160/32KHZ_OUT
B34
NC1
A64
NC2
B68
NC3
REV
X00 X01 X02 A00
OCHOT# 7,53,55
D
D
TC_CELL_VBAT
+R
0.1U_0402_16V
0.1U_0402_16V
C723
C723
4Z~D
4Z~D
ERFACE
ERFACE
15mil
3
+3
.3V_ALW
B64
A11
A22
B35
A41
A58
A52
A26
[1]
[2]
[3]
VBAT
VTR
VTR
VTR
VTR[4]
VTR[5]
VTR[6]
VTR[7]B3VTR[8]
GP
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GP
GP
SMBUS INTERFACE
SMBUS INTERFACE
IO012/I2C1H_DATA/I2C2D_DATA
GP
IO013/I2C1H_CLK/I2C2D_CLK
GP
IO141/I2C1F_DATA/I2C2B_DATA
GP
GP
DELL PWR SW INF
DELL PWR SW INF
DB Version 0.12
DB Version 0.12
]
]
D
VSS[1
AGN
B66
B11
VSS[4
least 15mil
B60
3V6K~D
3V6K~D
C739
C739
4.7U_0603_6.
4.7U_0603_6.
B12
P
+VR_CA
1
2
VR_CAP
VSS_RO
B54
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C727
C727
C724
C724
2
2
MISC INTERFACE
MISC INTERFACE
IO021/RC_ID1
GP
IO020/RC_ID2
GP
IO025/UART_CLK
GP
IO120/UART_TX
GP
IO124/GPTP-OUT5/UART_RX
IO040/GPTP-OUT3/HSPI_CS2
IO142/I2C1F_CLK/I2C2B_CLK
_PRW GD
VCC
IO060/KBRST
GP
IO101/ECGP_SCLK
GP
IO103/ECGP_MISO
GP
IO105/ECGP_MOSI
GP
IO102/HSPI_SCLK
GP
IO104/HSPI_MISO
GP
IO106/HSPI_MOSI
GP
IO116/MSDATA
GP
IO117/MSCLK
GP
IO127/A20M
GP
IO153/LED3
GP
IO156/LED1
GP
IO157/LED2
GP
nFW
CHOT#/PWM4
PRO
IO001/ECSPI_CS1
GP
IO002/ECSPI_CS2
GP
IO014/GPTP-IN7/HSPI_CS1
IO015/GPTP-OUT7
GP
IO016/GPTP-IN8
GP IO017/GPTP-OUT8
GP
IO026/GPTP-IN1
GP IO027/GPTP-OUT1
GP
IO041
GP
IO107/nRESET_OUT
GP
IO125/GPTP-IN5
GP
IO126
GP
IO151/GPTP-IN4
GP IO152/GPTP-OUT4
GP
IO003/I2C1A_DATA
GP
IO004/I2C1A_CLK
GP
IO005/I2C1B_DATA
GP
IO006/I2C1B_CLK
GP
IO130/I2C2A_DATA
GP
IO131/I2C2A_CLK
GP
IO132/I2C1G_DATA
GP
IO140/I2C1G_CLK
GP
IO143/I2C1E_DATA
GP
IO144/I2C1E_CLK
GP
BGPO
I_IN2 #
VC
_OUT
VCI
I_IN1 #
VC
I_IN0 #
VC
_OVRD_ IN
VCI
VCI_IN 3#
PECI
PECI
PECI_VREF
PECI
I2S
I2S
I2S_D AT I2S_C LK
I2S_W S
EP
C5055-LZY_DQFN132_11X11~D
C5055-LZY_DQFN132_11X11~D
ME
ME
C1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
10U_0805_6.3V
10U_0805_6.3V
0.1U_0402_16V
0.1U_0402_16V
1
1
C728
C728
C729
C729
6M~D
6M~D
4Z~D
4Z~D
2
2
SYSTEM
A10
BOAR
B10
DDR_ON
B14
ST_DEBUG_TX
HO
B44
ST_DEBUG_RX
HO
B46
RUNPW
B26
EN_
INVPWR
A25
PCH
B36 B37
XF
R_ID_BIT #
B38
DDR_HVRE
A34
DYN_T
A35
CPU
A36
MSD
A40
C
MS
B43
_A20GATE
SIO
A45
PS_I
A55
T1_LED#
BA
A57
T2_LED#
BA
B61
FWP
B65
P
OCHOT#_EC
PR
A46
B2
DOCK
_SMB_ALERT#
A2 B8 B18
ME
_SUS_PWR_ACK
A8
_SUS_PWRGD
1.5V
B9
APWROK
PM_
A9
1.05V
A14
W_PWRGD_3V_5V
AL
B15
DEVI
A17
RESET
B39
A_O
N
A44
PCH_RS
B47
AC_
PRESENT
A54
SIO
_PWRBTN#
B58
DOCK
A3
DO
CK
B4
D_SMBDAT
LC
A4
D_SMBCLK
LC
B5
BAY_SM
B7
BAY_SM
A7
_SMBDAT
DAI
B48
_SMBCLK
DAI
B49
CHARG
A47
CHARG
B50
CAR
B52
CARD_S
A49
USH
B53
USH_S
A50
A59
0
RESET
B63 A60 A63 B67 B1 A1
B51 A48
B17 B27 B28
RUN_ON
_OUT#
_ON_SW#
LAT ALW
I_INT1#
VC POW ACAV_ DOCK
+PEC PECI
ZϴϲϰΘZϴϲϱĨŽƌDϱϬϰϱ ƐŚŽƵůĚďĞƉŽƉƵůĂƚĞĚ
0.1U_0402_16V
0.1U_0402_16V
0.1U_0402_16V
0.1U_0402_16V
1
1
C730
C730
4Z~D
4Z~D
2
_ID
D_ID
ROK
_SATA_MOD_EN#
F_RST_GATE
UR_CURRNT_SET#
1.5V_S3_GATE ATA LK
D
#
_A_PWRGD
CE_DET#
_OUT#
MRST#
_SMB_DAT _SMB_CLK
BDAT BCLK
ER_SMBDAT ER_SMBCLK
D_SMBDAT
MBCLK
_SMBDAT
MBCLK
ON
ER_SW_IN#
IN
_PWR_SW#
I_VREF
_EC_R
R864 100K_0402_5%
R864 100K_0402_5% R865 100K_0402_5%
R865 100K_0402_5%
_ENABLE#45
+3.3V_M
2
G
G
1
C731
C731
4Z~D
4Z~D
2
2
DDR_ON
HO
HO
RUNPW EN_
PCH
DDR_HVRE DYN_T CPU
MSD MSC SIO
PS_I
BA BA
~D
~D
~D
~D ~D
~D
ME
1.5V PM_
1.05V AL DEVI RESET A_O PCH_RS AC_ SIO
ƚƌĂĐĞǁŝĚƚŚϮϬŵŝůƐ
1 2
R863 43_0402_5%~
R863 43_0402_5%~
1 2 1 2
RUNPWROK
2
G
G
12
R893
R893 100K_0402_5%
100K_0402_5%
WRGD#
PCH_P
13
D
D
Q48
Q48
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
S
S
0.1U_0402_16V
0.1U_0402_16V
C725
C725
4Z~D
4Z~D
ST_DEBUG_TX 37
ST_DEBUG_RX 37
ROK 7,42
INVPWR 24
_SATA_MOD_EN# 14
UR_CURRNT_SET# 55
1.5V_S3_GATE 11 ATA 37 LK 37
_A20GATE 18
D 47 T1_LED# 46 T2_LED# 46
_SUS_PWR_ACK 16
_SUS_PWRGD 49
APWROK 16
_A_PWRGD 51
W_PWRGD_3V_5V 48
CE_DET# 29
N 45,51
PRESENT 16
_PWRBTN# 16
ALW
ACAV_IN 22,55,57
+3.3V_RUN
~D
~D
0.1U_0402_16V
0.1U_0402_16V
1
C726
C726
4Z~D
4Z~D
2
49,50
F_RST_GATE 7
R9501K_0402_5%
R9501K_0402_5%
12
R9521K_0402_5%
R9521K_0402_5%
12
R9581K_0402_5%
R9581K_0402_5%
12
_OUT# 16
MRST# 14,16
_SMB_DAT 41
DOCK
_SMB_CLK 41
DOCK
BAY_SM
BAY_SM
CHARG
CHARG
ER_SMBCLK 55
CAR
D_SMBDAT 3 8
CA
MBCLK 38
RD_S
_SMBDAT 34
USH
MBCLK 34
USH_S
ON 48
~D@
~D@ ~D@
~D@
12
R799
R799 10K_0402_5%
10K_0402_5%
13
D
D
Q45
Q45
S
S
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
PCH_P
2
0.1U_0402_16V
0.1U_0402_16V
1
C732
C732
4Z~D
4Z~D
2
Bat2 = Amber LED Bat1 = Blue LED
20mA drive pins
O
L_MUTE 31
V
_SMB_ALERT# 41,47,57
DOCK
L_UP 31
VO
L_DOWN 31
VO
XF
BDAT 29,47 BCLK 2 9,47
ER_SMBDAT 55
PECI
D
D
R863 close to U51& least 250mils
+3
~D
~D
SYSTEM
_ID
WRGD# 22
CHIPSET_ID for BID function
2
POW
ER_SW_IN#22
DOCK
_PWR_SW#22
R_ID_BIT #
R1578 100K
R1578 100K
+1.05V_RUN_V
TT
R862
R862 0_0402_5%~
0_0402_5%~
1 2
_EC 18
1
C737
C737
0.1U_0402_16V
0.1U_0402_16V
2
+3
.3V_ALW
1 2
1
2
R871
R871 1K_0402_5%
1K_0402_5%
4700P_0402_25V
4700P_0402_25V
7K~D
7K~D
.3V_ALW
~D
~D
1 2
FWP
#
C742
C742
1 2
1=JTAG interface Reset disabled 0=Reset JTAG interface
1
_CELL
+RTC
12
R810
R810 100K_0402_5%
100K_0402_5%
ER_SW_IN#
POW
DOCK
LAT
_ON_SW#
12
D
D
4Z~D
4Z~D
R872
R872 10K_0402_5%
10K_0402_5%
R879
R879
@
@
10K_0402_5%
10K_0402_5%
_PWR_SW#
_0402_5%~D
_0402_5%~D
+3
~D
~D
~D
~D
+RTC
+RTC
@
@
.3V_ALW
1
2
_CELL
12
1
2
_CELL
12
1
2
R811
R811
C722
C722 1U_0402_6.3V
1U_0402_6.3V
R819
R819 100K_0402_5%
100K_0402_5%
1 2
R825 10K
R825 10K
C734
C734 1U_0402_6.3V
1U_0402_6.3V
R870
R870 100K
100K
R877 10K
R877 10K
C740
C740 1U_0402_6.3V
1U_0402_6.3V
DYN_T
PCH_A
DOCK
1.05V
DELL CO
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
Date: Sheet
Date: Sheet
Date: Sheet
@
@
C721
C721
1U_0402_6.3V
1U_0402_6.3V
~D
~D
1 2
1 2
10K
10K
_0402_5%~D
_0402_5%~D
6K~D
6K~D
C733
C733
@
@
1U_0402_6.3V
1U_0402_6.3V
6K~D
~D
~D
6K~D
6K~D
_0402_5%
_0402_5%
~D
~D
1 2
6K~D
6K~D
PRESENT
AC_
LC
D_SMBCLK
LC
D_SMBDAT
DOCK
_SMB_DAT
_SMB_CLK
DOCK
_SMB_ALERT#
DOCK
CE_DET#
DEVI
VO
L_MUTE
VO
L_UP
VO
L_DOWN
BAY_SM
BDAT
BCLK
BAY_SM
UR_CURRNT_SET#
I_INT1#
VC
K_KBD
CL
_KBD
DAT
CLK_
MSE
DAT
_MSE
DAI_SMBDAT
_SMBCLK
DAI
ATA
MSD
N
A_O
AUX_
ON
DDR_ON
SUS_ON
LW_ON
_POR_RST#
INVPWR
EN_
_0.8V_PWROK
RE
SET_OUT#
CPU1.5V_S3_GATE
6K~D
1 2
_0402_5%~D
_0402_5%~D
C738
C738
@
@
1U_0402_6.3V
1U_0402_6.3V
1 2
_0402_5%~D@
_0402_5%~D@
R835 10K_0402_5%
R835 10K_0402_5%
R418 2.
R418 2.
R420 2.
R420 2.
R838 2.
R838 2.
R841 2.
R841 2.
1 2
R762 10K_0402_5%
R762 10K_0402_5%
R1118 100K
R1118 100K
R1121 100K
R1121 100K
R1122 100K
R1122 100K
R1123 100K
R1123 100K
R854 2.
R854 2.
R856 2.
R856 2.
R837 10K_0402_5%
R837 10K_0402_5%
R1156 100K
R1156 100K
R845 4.
R845 4.
R846 4.7K_0402_5%~DR846 4.7K_0402_5%~D
R851 4.
R851 4.
R852 4.
R852 4.
R886 2.2K
R886 2.2K
R884 2.2K
R884 2.2K
1 2
R869 10K_0402_5%
R869 10K_0402_5%
1 2
R873 100K_0402_5%~DR873 100K_0402_5%~D
R874 2.7K
R874 2.7K
R876 100K_0402_5%
R876 100K_0402_5%
R878 100K_0402_5%
R878 100K_0402_5%
R880 100K_0402_5%
R880 100K_0402_5%
R881 100K_0402_5%
R881 100K_0402_5%
R882 100K_0402_5%~DR882 100K_0402_5%~D
R883 10K_0402_5%
R883 10K_0402_5%
R843 8.2K
R843 8.2K
R889 100K_0402_5%
R889 100K_0402_5%
NFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EMC5055
EMC5055
EMC5055
LA-6611P
LA-6611P
LA-6611P
1
6K~D
6K~D
PO
WER_SW#_MB 31,44
DOCK
_PWR_BTN# 41
6K~D
6K~D
_ON_SW_BTN# 31
LAT
12
12
2K_0402_5%~D
2K_0402_5%~D
12
2K_0402_5%~D
2K_0402_5%~D
12
2K_0402_5%~D
2K_0402_5%~D
12
2K_0402_5%~D
2K_0402_5%~D
12
12
12
12
12
2K_0402_5%~D
2K_0402_5%~D
12
2K_0402_5%~D
2K_0402_5%~D
12
12
12
7K_0402_5%~D
7K_0402_5%~D
12
12
7K_0402_5%~D
7K_0402_5%~D
12
7K_0402_5%~D
7K_0402_5%~D
12
_0402_5%~D
_0402_5%~D
12
_0402_5%~D
_0402_5%~D
12
12
12
12
12
12
12
12
12
43 64Wednes
43 64Wednes
43 64Wednes
+3
.3V_ALW_PCH
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D
_0402_5%~D@
_0402_5%~D@
of
of
of
~D
~D
.3V_ALW
+3
~D
~D
~D
~D
+RTC
+5V_RUN
+3.3V_
~D
~D
~D
~D
~D
~D
~D
~D
~D
~D
~D
~D
~D
~D
_CELL
RUN
0.3
0.3
0.3
5
dŽƵĐŚWĂĚ
+3.3
V_TP
2.2K_0402_5%~D
2.2K_0402_5%~D
4.7K_0402_5%~D
D D
T_TP_SIO43
DA
CLK_
TP_SIO43
C C
4.7K_0402_5%~D
12
12
R90
R90
R90
R90
2
2
3
3
L54 BLM
L54 BLM
L55 BLM
10P
10P
10P
10P
1
_0402_50V8J~D
_0402_50V8J~D
_0402_50V8J~D
_0402_50V8J~D
C751
C751
C752
C752
2
L55 BLM
1
2
18AG601SN1D_0603~D
18AG601SN1D_0603~D
12
18AG601SN1D_0603~D
18AG601SN1D_0603~D
12
4
+3.3
V_TP
~D
~D
~D@
~D@
C750
C750
+3
10P
10P
_0402_50V8J~D
_0402_50V8J~D
.3V_ALW
1
C749
C749
2
10P
10P
_0402_50V8J~D
_0402_50V8J~D
+3
1
2
.3V_RUN
TP_DATA
TP_CLK
+3.3
V_TP
1 2
R1161 0_0603_5%
R1161 0_0603_5%
1 2
R1162 0_0603_5%
R1162 0_0603_5%
1
5
5
C75
C75
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
WůĂĐĞĐůŽƐĞƚŽ:dWϭϳ
3
dŽƵĐŚWĂĚŽŶŶWŝƚĐŚсϬϱ
1
CONN@
1
CONN@
JTP
JTP
1
PS
2_CLK_TS 2_DAT_TS
PS
+3.3
V_TP
TP_DATA TP_C
LK
TP_C
LK
TP_DATA
S
S D05.TCT_SOD323-2~D
D05.TCT_SOD323-2~D
@
@
D36
D36
2 1
2 1
WůĂĐĞĐůŽƐĞƚŽ:dWϭĐŽŶŶĞĐƚŽƌ
2 3 4 5 6 7 8
TYCO_2041070-8
TYCO_2041070-8
>ŝŶŬŽŶĞ
S
S D05.TCT_SOD323-2~D
D05.TCT_SOD323-2~D
@
@
D37
D37
1 2 3 4 5
9
6
G1
10
7
G2
8
2
ůƵĞdŽŽƚŚ
33
@
33
@
R11
R11
1K_0402_5%~D
1K_0402_5%~D
+3
.3V_BT
1 2
R11
R11
34
@
34
@
1K_0402_5%~D
1K_0402_5%~D
1 2
BT_C
COEX2
CO
BT_C
+3
+3
EX1 OEX_STATUS234
BT_PRI
BT_R _WLAN_ACTIVE37
BT_PRI
.3V_RUN
.3V_ALW
D
ET#17
BT_
_BT_ACTIVE37
_STATUS34
BT_ACTI
VE46
ADIO_DIS#42
-17
USBP11 USBP11
+17
OEX_STATUS2
_STATUS
POW
R1129
R1129
R1130
R1130
+3
.3V_BT
1 2
0_0603_5%~D
0_0603_5%~D
1 2
0_0603_5%~D@
0_0603_5%~D@
10K
10K
33P
33P
12
_0402_5%~D
_0402_5%~D
_0402_50V8J~D
_0402_50V8J~D
R904
R904
C753
C753
1
2
1
2
100P_0402_50V8J~D
100P_0402_50V8J~D
0.
0.
@C754
@
C754
WŽǁĞƌ^ǁŝƚĐŚĨŽƌĚĞďƵŐ
ER_SW#_MB31,43
100P
100P
_0402_50V8J~D
_0402_50V8J~D
1
@
@
C759
C759
2
1
1 2
C748
C748
1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
CONN@
1
CONN@
JBT
JBT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
13
11
G1
12
14
12
G2
LOTES_YBA-WTB-015-K01~D
LOTES_YBA-WTB-015-K01~D
>ŝŶŬŽŶĞ
2
112
1
@
1
@
PWRSW
PWRSW
@SHORT PADS~D
@SHORT PADS~D
Place on Bottom
<ĞLJďŽĂƌĚ
KB_DET#18
.3V_ALW
B B
BC
BC_D
+3
V_RUN
+5
_INT#_ECE111743
AT_ECE111743
_CLK_ECE111743
BC
<ŽŶŶWŝƚĐŚсϭϬŵŵ
KB_DET#
2_CLK_TS
PS PS2_
DAT_TS
CONN@
CONN@
JKB1
JKB1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
CO_1-2041084-0~D
CO_1-2041084-0~D
TY
TY
>ŝŶŬŽŶĞ
.3V_ALW
+5
V_RUN
1
C75
C75
8
8
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
A A
5
WůĂĐĞĐůŽƐĞƚŽ:<ϭϰ
+3
1
C756
C756
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
WůĂĐĞĐůŽƐĞƚŽ:<ϭϯ
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Int KB/Touc
Int KB/Touc
Int KB/Touc
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
h PAD/BT
h PAD/BT
h PAD/BT
44 64Wedn
44 64Wedn
44 64Wedn
of
of
1
of
5
нϯϯsͺ>tͺW,^ŽƵƌĐĞ
.3V_ALW2
+3
12
@
@
7
7
R90
R90 100K_0402_5%~D
100K_0402_5%~D
_ENABLE20
D D
@
@
A
A
Q51
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PCH_AL
Q51
W_ON43
2
ALW
LW
_ON_3.3V#
A
61
LW
+15V_A
12
@
@
R905
R905
_0402_5%~D
_0402_5%~D
100K
100K
ALW
3
@
@
Q51
Q51
B
B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
.3V_ALW
+3
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
_ENABLE
4
3
2
1
/ŶƚĞƌĨĂĐĞ
@
@
Q49
Q49
D
D
6
S
S
45 2 1
G
G
3
1
@
@
C762
C762 3300P
3300P
2
.3V_ALW_PCH
+3
10U
10U
_0805_6.3V6M~D
_0805_6.3V6M~D
C760
C760
1
2
_0402_50V7K~D
_0402_50V7K~D
12
R908
R908
@
@
20K
20K
PJP6
PJP6
PAD-OPEN1x1m
PAD-OPEN1x1m
_0402_5%~D
_0402_5%~D
.3V_ALW
+3
3
3
12
RUN_O
N_ENABLE#43
D
D
MN66D0LDW-7_SOT363-6~D
MN66D0LDW-7_SOT363-6~D
RUN_O
+3
.3V_ALW2
12
R909
R909 100K
100K
_0402_5%~D
_0402_5%~D
N_ENABLE#
RUN_O
61
Q52A
Q52A
2
N11,38,42,50
+15V_A
LW
12
R906
R906 100K
100K
_RUN_ENABLE
5V
3
B
B
Q52
Q52 DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
_0402_5%~D
_0402_5%~D
нϱsͺZhE^ŽƵƌĐĞ
+5
Q50
Q50
V_ALW
S
S
I4164DY-T1-GE3_SO8~D
I4164DY-T1-GE3_SO8~D
8 7
5
+5
V_RUN 1 2
10U_0805_10V4Z~D
10U_0805_10V4Z~D
36
4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
C76
C76
3
3
2
12
1
R91
R91
0
0
C76
C76
20K_0402_5%~D
20K_0402_5%~D
1
1
2
нϯϯsͺ^h^^ŽƵƌĐĞ
+3
.3V_ALW2
12
R91
R91
5
5
100K_0402_5%~D
100K_0402_5%~D
N_3.3V#
C C
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
N43
SUS_O
SUS_O
61
Q53
Q53
A
A
2
+15V_A
LW
12
R911
R911 100K
100K
3
Q53
Q53
B
B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
_0402_5%~D
_0402_5%~D
SUS_ENABL
+3
.3V_ALW
E
6
2 1
Q54
Q54
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
S
S
D
D
S
S
45
10U
10U
_0805_6.3V6M~D
_0805_6.3V6M~D
C765
C765
G
G
3
1
C767
C767
_0402_25V7K~D
_0402_25V7K~D
4700P
4700P
2
+3
.3V_SUS
12
1
R914
R914
_0402_5%~D
_0402_5%~D
20K
20K
2
+15V_A
2
G
G
LW
12
R912
R912
_0402_5%~D
_0402_5%~D
100K
100K
3V_RUN_ENABLE
3.
13
D
D
Q56
Q56 S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
нϯϯsͺZhE^ŽƵƌĐĞ
.3V_ALW
+3
Q55
Q55
TMS4920NR2G_SO8~D
TMS4920NR2G_SO8~D
N
N
8 7
5
.3V_RUN
+3
1 2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
36
4
470P_0402_50V7K~D
470P_0402_50V7K~D
C766
C766
1
2
12
C764
C764
1
R913
R913
_0402_5%~D
_0402_5%~D
20K
20K
2
ŝƐĐŚĂƌŐŝƌĐƵŝƚ
+3.3
нϯϯsͺD^ŽƵƌĐĞ
LW
R918
R918 100K
100K
A_O
_0402_5%~D
_0402_5%~D
N_3.3V#
+15V_A
12
R917
R917 100K
100K
A_ENABL
3
B
B
Q57
Q57 DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
_0402_5%~D
_0402_5%~D
E
+3
.3V_ALW2
12
61
A
A
Q57
B B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
N43,51
A_O
Q57
2
.3V_ALW
+3
Q58
Q58 S
S
I3456DDV-T1-GE3_TSOP6~D
I3456DDV-T1-GE3_TSOP6~D
D
D
6
S
S
45 2 1
G
G
3
1
C770
C770 4700P
4700P
_0402_25V7K~D
_0402_25V7K~D
2
V_M
+3.3
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
12
1
R919
R919
@
@
C76
C76
20K
20K
_0402_5%~D
_0402_5%~D
8
8
2
N_3.3V#
A_O
V_M
12
R916
R916 39_0603_5%
39_0603_5%
~D
~D
+3 .3V_M_CHG
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
13
D
D
Q60
2
Q60
G
G
S
S
+15V_A
2
G
G
LW
12
R920
R920 100K
100K
_0402_5%~D
_0402_5%~D
1.
5V_RUN_ENABLE
13
D
D
Q62
Q62 S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
ŝƐĐŚĂƌŐŝƌĐƵŝƚ
.3V_SUS
+3
12
R92
R92
2
@
2
@
1K_0402_5%~D
1K_0402_5%~D
+3 .3V_SUS_CHG
@
@
S
S
13
D
D
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q65
N_3.3V#
SUS_O
A A
Q65
2
G
G
ALW
S
S
_ON_3.3V#
.3V_ALW_PCH
+3
2
G
G
12
13
+3 .3V_ALWPCH_CHG
D
D
S
S
R928
R928
@
@
1K
1K
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
_0402_5%~D
_0402_5%~D
@
@
RUN_O
Q66
Q66
N_ENABLE#
V_RUN
+5
12
+5 V_RUN_CHG
13
D
D
2
G
G
S
S
R923
R923
@
@
1K
1K
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
+1
_0402_5%~D
_0402_5%~D
@
@
Q67
Q67
2
G
G
.5V_RUN
12
13
+1 .5V_RUN_CHG
D
D
S
S
@
@
R924
R924 1K
1K
_0402_5%~D
_0402_5%~D
@
@
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q68
Q68
.3V_RUN
+3
12
R929
R929 39_0603_5%
39_0603_5%
~D
~D
+3 .3V_RUN_CHG
S
S
13
D
D
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q69
Q69
2
G
G
S
S
_RUN
+1.05V
12
R925
R925
@
@
39_0402_5%
39_0402_5%
~D
~D
+1 .05V_RUN_CHG
RUN_ON_CPU1.5VS3#7,11
@
@
S
S
13
D
D
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q70
Q70
2
G
G
S
S
.5V_CPU_VDDQ
+1
2
G
G
12
R92
R92
6
6
220_0402_5%~D
220_0402_5%~D
+1.5V_CPU_VDDQ_CHG
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
13
D
D
Q71
Q71
S
S
.75V_DDR_VTT
+0
12
+DDR_
CHG
13
D
D
2
G
G
S
S
R927
R927 22_0603_5%
22_0603_5%
S
S SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
Q72
Q72
~D
~D
2
G
G
+15V_A
LW
12
R930
R930 100K
100K
_0402_5%~D
_0402_5%~D
05V_RUN_ENABLE
1.
13
D
D
Q64
Q64
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
S
S
нϭϱsͺZhE^ŽƵƌĐĞ
V_MEM
+1.5
6
2 1
нϭϬϱsͺZhE^ŽƵƌĐĞ
_M
+1.05V
Q63
Q63
I4164DY-T1-GE3_SO8~D
I4164DY-T1-GE3_SO8~D
S
S
8 7
5
Q59
Q59
TGS4141NT1G_TSOP6~D
TGS4141NT1G_TSOP6~D
N
N
D
D
S
S
45
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
C76
C76
G
G
9
9
3
1
C771
C771 4700P
4700P
_0402_25V7K~D
_0402_25V7K~D
2
1 2 36
4
1
2
1
2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
C77
C77
3
3
+1
.5V_RUN
1
2
+1.05V_RUN
10U
10U
12
_0805_6.3V6M~D
_0805_6.3V6M~D
C772
C772
12
20K
20K
_0402_5%~D
_0402_5%~D
R931
R931
R92
R92
1
1
20K_0402_5%~D
20K_0402_5%~D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PO
PO
PO
WER CONTROL
WER CONTROL
WER CONTROL
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
45 64Wedn
45 64Wedn
45 64Wedn
of
of
1
of
5
+3.
3V_ALW
12
R932
R932 10K_0402_5%~
10K_0402_5%~
Q74B
Q74B
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
3
A_LED#
3
5
4
D
D
100K_0402_5%~
100K_0402_5%~
4
5
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
Q78B
Q78B
T#14
LED_
WI
MASK_SAT
SATA_DIAG_OUT#42
RELESS_LED#37,42
SATA_AC
BT_AC
MASK_SAT
A_LED#42
TIVE44
12
R959
R959
D D
C C
D59
D59
R
R
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
D62
D62
B751S40T1_SOD523-2~D
B751S40T1_SOD523-2~D
R
R
+3.
MASK_BASE_LED
21
21
MASK_BASE_LED
3V_ALW
12
R937
R937 100K_0402_5%~
100K_0402_5%~
DM
DM
D
D
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
S#
LED Cir
B B
Mask All LEDs (Sniffer Function) Mask Base MB LEDs (Lid Closed)
Mask LEDs (Lid Opened)
Do not
4
,>ƐŽůƵƚŝŽŶĨŽƌtŚŝƚĞ>
+5V_ALW
D
D
Q74A
Q74A
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
61
2
2
S#
1 3
R934
R934
Q75
Q75 PDT
PDT
A114EU_SC70-3~D
A114EU_SC70-3~D
1 2
t/Z>^^>ƐŽůƵƚŝŽŶĨŽƌtŚŝƚĞ>
+5V_ALW
Q78A
Q78A
61
2
cuit Control Table
LED_MASK# LID_CL#
SYS_
0 10
2
SATA_LED
4.7K_0402_5%~D
4.7K_0402_5%~D
Q79
Q79 PDT
PDT
1 3
1 2
R939
R939
X
11
SATA_LED
A114EU_SC70-3~D
A114EU_SC70-3~D
4.7K_0402_5%~D
4.7K_0402_5%~D
EMI CLIP
CLIP
CLIP EMI_CLIP
EMI_CLIP
1
1
WLAN
31
_LED 31
BREAT
GND
47K_0402_5%~
47K_0402_5%~
H_LED#41,43
1
3
R954
R954
2
R938
R938 100K_0402_5%~
100K_0402_5%~
D
D
Q83A
1 2
1U_0402_16V4Z~D
1U_0402_16V4Z~D
BAT2_LED
4
BAT1_LED
61
Q95A
Q95A
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
61
Q101A
Q101A
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
+5V_ALW
Q82A
Q82A
3V_ALW
+3.
Q89A
Q89A
Q89B
Q89B
+5V_ALW
12
+5V_ALW
12
2
5
Q82B
Q82B
2
5
R953
R953 100K_0402_5%~
100K_0402_5%~
R956
R956 100K_0402_5%~
100K_0402_5%~
61
MASK_BASE_LED
+5V_ALW
3
4
SYS_LED_M
R945
R945 100K_0402_5%~
100K_0402_5%~
1 2
MASK_BASE_LED
61
+3.
3V_ALW
3
4
SYS_LED_M
D
D
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
SYS_LED_M
D
D
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
MASK_BASE_LEDS#
SYS_LED_M
D_CL#31,42
LI
+3.
3V_ALW
DM
DM
N66D0LDW-7_SOT363-6~D
3V_ALW
5
P
A2Y
G
3
5
P
A2Y
G
3
1 2
1
U55
U55
NC
N
N
N66D0LDW-7_SOT363-6~D
1 2
C774
C774
1
0.
0.
NC
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
C775
C775
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
4
C7SZ04P5X-G_SC70-5~D
C7SZ04P5X-G_SC70-5~D
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
2
2
12
R940
R940
D
D
47K_0402_5%~
47K_0402_5%~
#43
BAT2_LED
BAT1_LED
+3.
3V_ALW
12
D
D
5
A2Y
3
N
N
C7SZ04P5X-G_SC70-5~D
C7SZ04P5X-G_SC70-5~D
R947
R947
47K_0402_5%~
47K_0402_5%~
#43
C777
C777
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
1 2
1
U57
U57
P
NC
4
G
C7SZ04P5X-G_SC70-5~D
C7SZ04P5X-G_SC70-5~D
N
N
D
D
BREAT
U54
U54
+3.
12
H_LED#_R
DM
DM
S#
12
R942
R942 100K_0402_5%~
100K_0402_5%~
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
4
ASK#
D
D
DM
DM
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
12
R948
R948 100K_0402_5%~
100K_0402_5%~
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
DM
DM
4
ASK#
Q95B
Q95B
4
5
ASK#
Q101B
Q101B
4
5
ASK#42
Q83A
N66D0LDW-7_SOT363-6~D
N66D0LDW-7_SOT363-6~D
61
2
D
D
Q83B
Q83B
3
5
Q92A
Q92A
2
61
2
S#
D
D
Q92B
Q92B
3
2
5
+5V_ALW
3
2
1 3
+5V_ALW
3
2
1 3
SYS_LED_MASK#
D_CL#
LI
1
2
+3.3V_ALW
+5V_ALW
2
1 3
R941
R941
+5V_ALW
2
1 3
3V_ALW
+3.
Q88
Q88 PDT
PDT
A114EU_SC70-3~D
A114EU_SC70-3~D
1 3
3V_ALW
+3.
Q93
Q93
A114EU_SC70-3~D
A114EU_SC70-3~D
PDT
PDT
1 3
Q94
Q94 PDT
PDT
A114EU_SC70-3~D
A114EU_SC70-3~D
1 2
R955 2K_0402_5%~
R955 2K_0402_5%~
Q96
Q96
A114EU_SC70-3~D
A114EU_SC70-3~D
PDT
PDT
C778
C778
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
U58
U58
MASK_BASE_LED
4
O
C7SH08FU_SSOP5~D
C7SH08FU_SSOP5~D
T
T
BREAT
1 2
R957 560_0402_5%~DR 957 560_0402_5%~D
5
P
B
A
G
3
1 2
R946
R946
1
Q81
Q81
A114EU_SC70-3~D
A114EU_SC70-3~D
PDT
PDT
4.7K_0402_5%~D
4.7K_0402_5%~D
Q84
Q84
A114EU_SC70-3~D
A114EU_SC70-3~D
PDT
PDT
1 2
150_0402_5%~D
150_0402_5%~D
R949
R949 2K_0402_5%~
2K_0402_5%~
1 2
R951
R951 150_0402_5%~
150_0402_5%~
1 2
BREAT
H_WHITE_LED
D
D
H_WHITE_LED_SNIFF
LT
LT
WůĂĐĞ>ϭĐůŽƐĞƚŽ^tϭ
S#
ĂƚƚĞƌLJ>
BAT
T
dŽ>ďŽĂƌĚ
BA
dŽ>ƉĂŶĞů
D
D
BA
TT_WHITE_LED 24
D
D
BAT
_YELLOW_LED 24
T
BREAT
LED1
LED1
W-C193TS5_WHITE~D
W-C193TS5_WHITE~D
_WHITE 31
TT_YELLOW 31
H_WHITE_LED 24
12
ark
Fiducial M
FD1
FD1
@
@ 1
FIDUCIAL
FIDUCIAL
MARK~D
A A
MARK~D
FD2
FD2
@
@ 1
FIDUCIAL
FIDUCIAL
MARK~D
MARK~D
FD3
@FD3
@ 1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
@
@
FD4
FD4
1
MARK~D
MARK~D
FIDUCIAL
FIDUCIAL
H3
@H3
@
H2
@H2
@
H_2P8
H_2P8
H_2P8
H_2P8
1
1
@
@
@
@
H16
H16
H15
H15
_3P4
_3P4
_2P8
_2P8
H
H
H
H
1
1
5
@ H4
@
H_2P0
H_2P0
@
@
H
H
_2P3
_2P3
H4
H17
H17
H5
@H5
@
H_2P8
H_2P8
1
@
@
H18
H18
_3P4
_3P4
H
H
1
>s^ƐƚĂŶĚŽĨĨ
@
@
@
@
H6
H6
H7
H7
_C5
_C5
CLIP
CLIP
CLIP
CLIP
1
1
@
@
@
@
H19
H19
H20
H20
_2P3
_2P3
_2P8
_2P8
H
H
H
H
1
1
1
@
@
@
@
H10
H10
H9
@ H9
@
_2P8
_C5
_C5
1
@
@
_2P8
_2P8
H
H
_2P8
H
H
H_2P8
H_2P8
@
@
H21
H21
H
H
1
1
H22
H22
_2P0X2P5
_2P0X2P5
1
H
H
1
4
_2P8
_2P8
@
@
@
@
H11
H11
@
@
H
H
_2P8
_2P8
H13
H13
H12
H12
_2P6
_2P6
_2P6
_2P6
H
H
H
H
1
H24
H24
1
1
@
@
H25
H25
_2P8
_2P8
H
H
1
1
@
@
H26
H26
_2P8
_2P8
H
H
@
@
H27
H27
_2P8
_2P8
H
H
1
W,ƐƚĂŶĚŽĨĨ
@
@
@
@
H28
H28 IP_C5
IP_C5
CL
CL
CL
CL
1
1
H29
H29 IP_C5
IP_C5
DELL CO
Title
Titl
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1
3
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
PAD & ME & LED
PAD & ME & LED
PAD & ME & LED
6611P
6611P
6611P
LA-
LA-
LA-
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
0.3
0.3
46 64Wednes
46 64Wednes
46 64Wednes
0.3
of
of
of
5
+3.
3V_ALW
2nd Battery Connector
PBATT
PBATT
2
2
1
1
D
D
D D
12
PC141
PC141
2200P_0402_50V7K~
2200P_0402_50V7K~
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
SUYIN_150010GR006M500ZR
SUYIN_150010GR006M500ZR
Z Z5305 Z5306
5304
3V_ALW
+3.
Primary Battery Connector
1
1
PBATT
PBATT
9
GND
8
GND
7
7
-DCIN_
+DCIN_
JACK
JACK
6
6
5
5
4
4
3
3
2
2
1
1
12
PC13
PC13
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
5
D
D
12
PC3
PC3
SUYIN_200277MR009F515ZR~D
SUYIN_200277MR009F515ZR~D
2200P_0402_50V7K~
2200P_0402_50V7K~
C C
B B
Link Done
PJPD
PJPD
C1
C1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
MOLEX_87438-0743~D
MOLEX_87438-0743~D
A A
Z4304 Z4305 Z4306
+5V_ALW
PD9
PD9
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
@
@
PR14
PR14
D
D
0_0402_5%~
0_0402_5%~
1 2
PC5
PC5
@
@
PL3
PL3
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
1
12
PC10
PC10
2
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PL4
PL4
FB
FB
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
1 2
NB_PSI
3
47U_0402_6.3V6-K~D
47U_0402_6.3V6-K~D .
.
@
@
1
1 2
PD10
PD10
2
0603M260APT_0603
0603M260APT_0603 VZ
VZ
@
@
2
3
PD34
PD34
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
GND
PD2
PD2
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
GND
D
GND
DCIN_CB
12
PC12
PC12
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
1
PR106
PR106
100_0402_5%~
100_0402_5%~
1 2
2
3
1
100_0402_5%~
100_0402_5%~
1 2
L_DET# 42
12
PR17
PR17
7K_0805_5%~D
7K_0805_5%~D
@
@
4.
4.
3
PD33
PD33
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
D
D
PD3
PD3
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
PR4
PR4
+DC_
2
1
100_0402_5%~
100_0402_5%~
1 2
2
3
1
D
D
100_0402_5%~
100_0402_5%~
1 2
BLM18BD
BLM18BD
IN
PC6
PC6
022U_0805_50V7K~D
022U_0805_50V7K~D
0.
0.
PD32
PD32
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
PR77
PR77
PD4
PD4
@
@
PR3
PR3
PL2
PL2
102SN1D_0603~D
102SN1D_0603~D
1 2
3
D
D
A204U_SOT323~D
A204U_SOT323~D D
D
+DC_
4
2
ESD Diodes
1
PR105
PR105
100_0402_5%~
100_0402_5%~
D
D
1 2
2
3
ESD Diodes
1
D
D
PR5
PR5
D
D
100_0402_5%~
100_0402_5%~
1 2
12
DC_IN+ Source
IN
12
PR15
PR15
_0402_5%~D
_0402_5%~D 1M
1M
10K_0402_5%~
10K_0402_5%~ D
D
12
PR19
PR19
1M_0402_5%~
1M_0402_5%~
4
2
3
@
@
1
PD7
PD7
24_SOT23
24_SOT23
SM
SM
PQ4
PQ4
FDS6679AZ_SO8~D
FDS6679AZ_SO8~D
1
S
2
S
3
S
4
G
PR18
PR18
1 2
D
D
<BOM Structure>
<BOM Structure>
8
D
7
D
6
D
5
D
SO
FT_START_GC 57
MBA
D
D
PR10
PR10
1 2
100K_0402_1%~
100K_0402_1%~
D
D
PR12
PR12
1 2
15K_0402_1%~
15K_0402_1%~
PC7
PC7
TT+_C
BAY_SMBC BAY_SMBD
PBAT_SM PBAT_SM
12
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
LK 29, 43 AT 29,43
PBATT
BCLK 43 BDAT 43
@
@
1 2
0_0402_5%~
0_0402_5%~
D
D
1 3
2
B
B
12
PC8
PC8
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+_C
PR7
PR7
D
D
S
S
PQ2
PQ2 FD
FD
G
G
2
C
C
PQ3
PQ3 MM
MM
ST3904-7-F_SOT323~D
ST3904-7-F_SOT323~D
E
E
3 1
PC9
PC9
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
FB
FB
PAD
PAD
12
PC136
PC136
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
FB
FB
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
FB
FB
12
PC2
PC2
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
33_0402_5%~
33_0402_5%~
1 2
V301N_NL_SOT23-3~D
V301N_NL_SOT23-3~D
IN_SS
+DC_
D
D
12
12
PR16
PR16
100K_0402_5%~
100K_0402_5%~
3
PL19
PL19
1 2
PJP51
PJP51
2 1
-OPEN 2x2m~D
-OPEN 2x2m~D
PL20
PL20
1 2
PL1
PL1
1 2
PJP43
PJP43
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
+5V
_ALW
2
3
PD6
PD6
DA204U_SOT323~D
DA204U_SOT323~D
PR9
PR9
PC11
PC11
10U_1206_25V6M~D
10U_1206_25V6M~D
1
D
D
+5V_ALW
12
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
T+
MPBAT
PBATT
GND
D
D
PR11
PR11
<BOM Structure>
<BOM Structure>
10K_0402_1%~
10K_0402_1%~
PR13
PR13
1 2
10K_0402_5%~
10K_0402_5%~
+
SLIC
+3.
3V_ALW
D
D
PR108
PR108
100K_0402_5%~
100K_0402_5%~
+3.
PR2
PR2
E_BAT_PRES#41,42,57
3V_ALW
+3.
PR8
PR8
2K_0402_5%~D
2K_0402_5%~D
2.
2.
+5V_ALW
PD8
PD8
@
@
A204U_SOT323~D
A204U_SOT323~D D
D
12
3V_ALW
12
100K_0402_5%~D
100K_0402_5%~D
R
R
B751V-40_SOD323-2~D
B751V-40_SOD323-2~D
1 2
2
3
1
D@
D@
PD5
PD5
@
@
1 2
NB
_PSID_TS5A63157
MO
0_0402_5%~
0_0402_5%~
PSID
DULE_BATT_PRES# 42,57
PR6
PR6
@
@ 1 2
_PSID41
DOCK
_DISABLE# 42
PBAT_PR
@
@
PQ1
PQ1
N338P_NL_SOT23-3~D
N338P_NL_SOT23-3~D
FD
FD
1
3
1
3
1 3
2
2
2
D
D
12
PC4
PC4 1500P_0402_7K~
1500P_0402_7K~
2
ES# 42,57
@
@
1
2
2
D
D
PU1
PU1
NO
GND
NC3CO
S5A63157DCKR_SC70-6~D
S5A63157DCKR_SC70-6~D
T
T
.3V_RTC_LDO
+3
B715F_SOT323~D
B715F_SOT323~D
R
R
DO
CK_SMB_ALERT# 41,43,57
6
IN
5
V+
4
M
+CO
2
PD1
PD1
1
GPIO
+5V_ALW
PS_ID 43
1
INCELL
12
Z4012
3
_PSID_SELECT 42
COIN RTC Battery
PR1
PR1
D
D
1K_0402_5%~
1K_0402_5%~
INCELL
+CO
C_CELL
+RT
1
PC1
PC1
_0603_10V4Z~D
_0603_10V4Z~D
1U
1U
2
Move to power schematic
LL CONFIDENTIAL/PROPRIETARY
DE
Title
e
e
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
Date: Sheet
Date: Sheet
Date: Sheet
Link Done
JRTC1
JRTC1
1
1
G
22G
TY
TY
CO_2-1775293-2~D
CO_2-1775293-2~D
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
+DCIN
+DCIN
+DCIN
6611P
6611P
6611P
LA-
LA-
LA-
1
3 4
0.1
0.1
47 57Wednes
47 57Wednes
47 57Wednes
0.1
of
of
of
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO
+D
123
12
PC31
PC31
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
1 2
PR36
PR36
7_1206_5%~D
7_1206_5%~D
4.
4.
ALWO
THERM_STP#22
C1_PWR_SRC
5
4
123
3
D
PQ7
PQ7
POWER56-8
POWER56-8
G
S
1
AON6788_1N
AON6788_1N
N43
+5V_ALW
3V_ALW
+3.
PU2 PR22
SN0608098
MAX8878
D
D
12
PC15
PC15
PC14
PC14
2200P_0402_50V7K~
2200P_0402_50V7K~
5
PQ12
PQ12
4
AON7408L_D
AON7408L_D
2
PR42
PR42
2K_0402_5%~
2K_0402_5%~
PR43
PR43
0_0402_5%~D
0_0402_5%~D
@
@
un-pop
10_ohm
12
12
PC17
PC17
PC16
PC16
1U_0805_50V7M~D
1U_0805_50V7M~D
0.
0.
FN8-5~D
FN8-5~D
D
D
12
12
@
@
+5V_ALW
_1206_25V6M~D
_1206_25V6M~D
10U
10U
PC29
PC29
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
_UGATE
12
+15V_ALW
_1206_25V6M~D
_1206_25V6M~D
10U
10U
(100mA,20mils ,Via NO.=1)
4
12
PC18
PC18
@
@
A_3V5V
GND
D
D
PR44
PR44
1 2
200K_0402_5%~
200K_0402_5%~
PAD
PAD
12
_1206_25V6M~D
_1206_25V6M~D
10U
10U
169K_0402_1%~
169K_0402_1%~
+5V_ALW
+5V_ALW
12
PC41
PC41
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PJP49
PJP49
-OPEN1x1m
-OPEN1x1m
D
D
PR20
PR20
1 2
0_0805_5%~
0_0805_5%~
+3.
12
PC25
PC25
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+3
.3V_RTC_LDO
GND
A_3V5V
PR30
PR30
1 2
EN_3V_5V
_PHASE
PC34
PC34
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
P
2
3
PD11
PD11
54SW-7-F_SOT323-3~D
54SW-7-F_SOT323-3~D
BAT
BAT
2
3
PD12
PD12
54SW-7-F_SOT323-3~D
54SW-7-F_SOT323-3~D
BAT
BAT
+15V_ALW
12
3V_ALW2
D
D
12
5V_BOOT_1
D
D
PR21
PR21
0_0805_5%~
0_0805_5%~
@
@
PR23
PR23
0_0402_5%~
0_0402_5%~
+5V_ALW
+5V
_FB1
POK1
GND
PR34
PR34
1_0603_5%~
1_0603_5%~
1 2
+5V_ALW
0.
0.
1U_0603_25V7K~D
1U_0603_25V7K~D
1 2
1
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
1 2
1
P
PC43
PC43
1 2
A_3V5V
PC39
PC39
PC42
PC42
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
D
D
LDOR
D
D
+5
_LGATE
12
P
+5V_ALW
12
PC26
PC26
GND
EFIN
PU2
PU2
9
VSW
10
VOU
11
VFB1
12
TR
13
PGOOD
14
EN1
15
DRVH1
16
LL1
V_ALW_BOOT
PR46
PR46
200K_0402_1%~
200K_0402_1%~
WŽƉϭϬKŚŵĨŽƌDyϭϳϬϮϬ
PJP45
PJP45
1 2
2
-OPEN1x1m
-OPEN1x1m
PAD
PAD
PC24
PC24
_0402_6.3V4Z~D
_0402_6.3V4Z~D 1U
1U
A_3V5V
T1
P1
I
PAD
33
3
12
2P
+5V_ALW
7
8
EFIN
LDOR
1
VBST117DRVL118V5
PD13
PD13
1
BAT
BAT
2
D
D
12
GND
0_0402_5%~
0_0402_5%~
+5V_3V_R
0.
0.
1U_0603_25V7K~D
1U_0603_25V7K~D
VIN
EN_3V_5V
+3.3V_ALW2
0_0603_5%~
0_0603_5%~
1
2
3
5
6
4
2
3
ILT
VIN
LDO
_LDO
NSEL
VREF
VREF
V5F
EN
TO
REF
TRI
VOU
SKI
PGOOD
DRVH2
B
D
DRV
SECF
GND21PGN
DRVL223VBST2
SN
SN
0608098_QFN32_5X5~D
0608098_QFN32_5X5~D
19
20
22
24
SECFB
+3
.3V_ALW_BOOT
A_3V5V
GND
12
2
PC40
PC40
+5V_ALW
1U_0603_10V6K~D
1U_0603_10V6K~D
54CW_SOT323~D
54CW_SOT323~D
PR47
PR47 39K_0402_5%~
39K_0402_5%~
1 2
A_3V5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
3
12
7U_0603_6.3V6K~D
7U_0603_6.3V6K~D
4.
4. PR24
PR24
@
@
1 2
PR25
PR25
@
@
0_0402_5%~
0_0402_5%~
1 2
PC28
PC28
EF
1 2
1 2
@
@
PR26
PR26
IN2
P2 T2
PSEL
2
EN2
LL2
A_3V5V
GND
D
D
@
@
10_0603_5%~
10_0603_5%~
D
D
D
D
D
D
32 31 30 29 28 27 26 25
1_0603_5%~
1_0603_5%~
1 2
1 2
+5V_VC
PR22
PR22
REFIN2
182K_0402_1%~
182K_0402_1%~
1 2
+3.
3V_OUT2
PR31
PR31
POK2 EN_3V_5V +3.
3V_ALW_UGATE
3V_ALW_PHASE
+3.
PR35
PR35
PJP46
PJP46
PAD
PAD
-OPEN1x1m
-OPEN1x1m
ϯϯsŽůƚнͲϱй
C1
D
D
12
12
PC27
PC27
_0603_10V6K~D
_0603_10V6K~D 1U
1U
12
A_3V5V
GND
PR27
PR27
D
D
0_0402_5%~
0_0402_5%~
PR28
PR28
@
PR29
PR29
D
D
D
D
0_0402_5%~D
0_0402_5%~D
12
12
PC35
PC35
3.3V_BOOT
_1
@
1 2
0_0402_5%~
0_0402_5%~
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+3.
GND
A_3V5V
GND
3V_ALW_LGATE
D
D
A_3V5V
POK2
POK1
12
PC30
PC30
@
@
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
+3.
3V_ALWP
D
D
PR40
PR40
100K_0402_1%~
100K_0402_1%~
@
@
1 2
+3.
3V_ALWP
D
D
PR41
PR41
1 2
100K_0402_1%~
100K_0402_1%~
12
0_0402_5%~
0_0402_5%~
PR45
PR45
4
4
2
D
D
12
12
12
PC20
PC20
PC21
PC19
PC19
2200P_0402_50V7K~
2200P_0402_50V7K~
8
D6D5D7D
PQ6
PQ6
G
S
S
S
3
2
1
8
D6D5D7D
G
PQ8
PQ8
S
S
S
3
2
1
@
@
D
D
ALW_PW
PC21
0.1U_0805_50V7M~D
0.1U_0805_50V7M~D
S8884 1N SO8
S8884 1N SO8 FD
FD
PL6
PL6
H_FDVE1040-H-4R7M=P3_10A_20%~D
H_FDVE1040-H-4R7M=P3_10A_20%~D
4.7U
4.7U
12
@
@
PC32
PC32
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PR37
PR37
@
@
4.
4.
7_1206_5%~D
7_1206_5%~D
1 2
S6690AS-T1-G 1N SO8
S6690AS-T1-G 1N SO8 FD
FD
RGD_3V_5V 43
12
PC22
PC22
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
10U
10U
10U
10U
12
D
D
PR33
PR33
0_0402_5%~
0_0402_5%~
D
D
@
@
PR39
PR39
0_0402_5%~
0_0402_5%~
GND
A_3V5V
LL CONFIDENTIAL/PROPRIETARY
DE
Title
e
e
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
dŚĞƌŵĂůĞƐŝŐŶƵƌƌĞŶƚϯϴ WĞĂŬĐƵƌƌĞŶƚϱϰ
12
KWͺD/Eϲϱ
PC23
PC23
&ƐǁсϯϬϬ<,nj
@
@
_1206_25V6M~D
_1206_25V6M~D
10U
10U
3V_ALWP
+3.
12
12
PC37
PC37
@
@
1U_0402_10V7K~D
1U_0402_10V7K~D
12
0.
0.
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
DC/DC +3V/ +5
DC/DC +3V/ +5
DC/DC +3V/ +5
LA-6611P
LA-6611P
LA-6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
+3.
1
3V_ALWP
PC38
PC38
330U_D3L_6.3VM_R25~D
330U_D3L_6.3VM_R25~D
1
+
+
2
V
V
V
48 57Wednes
48 57Wednes
48 57Wednes
0.1
0.1
0.1
of
of
of
PJP44
PJP44
+PW
R_SRC
D D
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
ϱsŽůƚнͲϱй dŚĞƌŵĂůĞƐŝŐŶƵƌƌĞŶƚϭϬϰ WĞĂŬƵƌƌĞŶƚϭϰϴ KWͺD/Eϭϳϴ
&ƐǁсϰϬϬ<,nj
PQ5
FN8-5~D
FN8-5~D
NC
PL5
PL5
3.0U
3.0U
1 2
PJP47
PJP47
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
PJP48
PJP48
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
PJP50
PJP50
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
PJP9
PJP9
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
X7629631L90
X7629631L91
PQ5
H_HMP1362-3R0-R_17A_20%~D
H_HMP1362-3R0-R_17A_20%~D
@
@
@
@
AON7408L_D
AON7408L_D
+5V
C C
B B
A A
_ALWP
P
+5V_ALW
1
+
+
PC33
PC33
PC36
PC36
2
@
@
_D3L_6.3VM_R25~D
_D3L_6.3VM_R25~D
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
330U
330U
12
D
D
PR32
PR32
12
@
@
0_0402_5%~
0_0402_5%~
12
D
D
PR38
PR38
0_0402_5%~
0_0402_5%~
GND
A_3V5V
P
+5V_ALW
+3.3V_ALWP
Main
2nd
5
5
4
3
2
1
+1.5V_SUS_P(TPS51318)
1.5 Volt +/-5% Thermal Design Current: 9.8A Peak current: 13.9
D D
PJP10
+1.
5V_PWR_SRC
PC46
PC46
@
@
_1206_25V6M~D
_1206_25V6M~D
10U
10U
TP
S51318_BST_1
D
D
12
D
D
GND
PR55
PR55
0_0402_5%~
0_0402_5%~
12
PC47
PC47
DDR_O
A_TPS_1.5V
12
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PC48
PC48
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+1.
PC50
PC50
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
1 2
N 43,50
5V_VX
12
12
PC378
PC378
1 2
PC45
PC45
PC44
PC44
@
@
_0805_6.3V4Z~D
_0805_6.3V4Z~D
22U
22U
17
VCCA
GND
COM
VFB
VOU
SS
16
VIN
VIN
VBST
PGOOD
P
T
EN
FSET
MOD
E
N
IMO
D
D
PGN
SW
PGN
1003055RUWR_QFN17_3P5X3P5~D
1003055RUWR_QFN17_3P5X3P5~D
SN
SN
9
7
8
+1. 5V_VX
0_0402_5%~D@
0_0402_5%~D@
12
TPS51318_BST
15
1.5V_SU
14
1.
5V_DDR_EN
13
TPS51318_F
12
TPS51318_M
11
S51318_IMON
TP
10
3.
3.
S_PWRGD
SET
ODE
GND
PU3
+3.
_0402_6.3V6K~D
_0402_6.3V6K~D 1U
1U
5V_SUS_P
3V_ALW
OMP
PU3
1
2
3
B
4
5
6
PR57
PR57
PC49
PC49
A_TPS_1.5V
12
680P_0402_50V7K~D
680P_0402_50V7K~D
PC52
PC52
2K_0402_1%~D
2K_0402_1%~D
12
1 2
PC53
PC53
12
GND
GND
12
D
D
A_TPS_1.5V
PC51
PC51
100P_0402_50V8J~D
100P_0402_50V8J~D
5.6K_0402_5%~D
5.6K_0402_5%~D
PR49
PR49
12
PR52
PR52
12
0_0402_5%~
C C
5V_SUS_P +1.
0_0402_5%~
PR53
PR53
1800P_0402_50V7K~
1800P_0402_50V7K~
D
D
1 2
TPS51318_C
TPS51318_VF
+1.
TPS51318_SS
12
PC54
PC54
PR54
PR54
33K_0402_1%~D
33K_0402_1%~D
01U_0402_25V7K~D
01U_0402_25V7K~D
1.
1.
0.
0.
A_TPS_1.5V
GND
_1206_25V6M~D
_1206_25V6M~D
10U
10U
PR48
PR48
3_0603_1%~D
3_0603_1%~D
1 2
PR51
PR51
GND
12
PR56
PR56
@
@
A_TPS_1.5V
0_0402_5%~
0_0402_5%~
12
22.1K_0402_1%~D@
22.1K_0402_1%~D@
A_TPS_1.5V
33K_0402_1%~D
33K_0402_1%~D
1.
1.
_1206_25V6M~D
_1206_25V6M~D
10U
10U
@
@
PR50
PR50
1 2
PJP10
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
12
+1.
5V_VX
12
@
@
0.
0.
@
@
4.
4.
1 2
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
0.42U
0.42U
PC55
PC55
1U_0603_25V7K~D
1U_0603_25V7K~D
PR58
PR58
7_0805_5%~D
7_0805_5%~D
+5V_ALW
PL7
PL7
12
12
12
PC381
PC381
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
12
PC56
PC56
PC382
PC382
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
22U
22U
22U
22U
12
12
PC58
PC58
PC57
PC57
@
@
_1206_25V6M~D
_1206_25V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
10U
10U
22U
22U
OCP_MIN:16.7A
12
PC60
PC60
PC59
PC59
@
@
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
22U
22U
22U
22U
+1.
5V_SUS_P
12
12
12
PC62
PC62
PC61
PC61
@
@
@
@
_1206_25V6M~D
_1206_25V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
10U
10U
22U
22U
12
12
PC63
PC63
_1206_6.3V6M~D
_1206_6.3V6M~D
22U
22U
12
PC64
PC64
PC65
PC65
1U_0603_25V7K~D
1U_0603_25V7K~D
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
0.
0.
PJP12
+3.
3V_ALW
PJP11
PJP11
GND
A_TPS_1.5V
1 2
PAD
PAD
-OPEN1x1m
-OPEN1x1m
4
B B
A A
5
D
D
12
PR59
PR59
100K_0402_1%~
100K_0402_1%~
1.5V_SUS_PWRGD 43
5V_SUS_P
+1.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
3
PJP12
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
PJP13
PJP13
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
5V_MEM
+1.
DELL CO
Title
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
+1.5
+1.5
+1.5
6611P
6611P
6611P
LA-
LA-
LA-
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
V_MEM
V_MEM
V_MEM
1
0.1
0.1
49 57Wednes
49 57Wednes
49 57Wednes
0.1
of
of
of
5
4
3
2
1
+1.8V_RUNP
1.8 Volt +/-5% Thermal Design Current: 0.99 A Peak current: 1.415 A
+3.
3V_ALW
PJP14
PJP14
@
@
D D
C C
PAD
PAD
GND
A_1.8V
2 1
-OPEN 2x2m~D
-OPEN 2x2m~D
@
@
PJP15
PJP15
1 2
PAD
PAD
-OPEN1x1m
-OPEN1x1m
PC70
PC70
1 2
012U_0402_16V7K~D
012U_0402_16V7K~D
0.
0.
.8V_RUNP +1
PC66
PC66
1 2
_0805_6.3V6M~D
_0805_6.3V6M~D
10U
10U
PR65
PR65
2K_0402_5%~
2K_0402_5%~
PC67
PC67
@
@
_0805_6.3V4Z~D
_0805_6.3V4Z~D
22U
22U
PR63
PR63
10_0402_1%~
10_0402_1%~
12
D
D
12
PC68
PC68
1 2
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
12
D
D
12
PR68
PR68
A_1.8V
GND
1.
1.
43K_0402_1%~D
43K_0402_1%~D
D
D
1K_0402_1%~
1K_0402_1%~
GND
PR66
PR66
PC72
PC72
+1.
A_1.8V
8V_PWR_SRC
0.
0.
018U_0402_50V7K~D
018U_0402_50V7K~D
12
100P_0402_50V8J~D
100P_0402_50V8J~D
12
PC71
PC71
PC69
PC69
1 2
1U_0402_16V7K~D
1U_0402_16V7K~D
.
.
+1.
+1.
12
12
+1. 8V_VDD
8V_FB
8V_COMP
PR60
PR60 0_0603_5%~
0_0603_5%~
12
11
10
9
57.
57.
6K_0402_1%~D
6K_0402_1%~D
PR69
PR69
D
D
PU4
PU4
VDD
D
AGN
FB
P
COM
A_1.8V
GND
15
16
14
VIN13VIN
PGND
PS51311RGTR_QFN16_3X3~D
PS51311RGTR_QFN16_3X3~D
T
T
E
MOD
8
8V_MODE +1.
1 2
SW
6SW7
17
D
PGN
PGOOD
5
0.
0.
8V_SW
+1.
TPAD
1
EN
2
RES
3
4
VBST
SW
PC73
PC73
22U_0603_10V7K~D
22U_0603_10V7K~D
+1.
+1
+1.
12
8V_EN
.8V_VBST
PR67
PR67
8V_VBST_1
PR61
PR61
24k
24k
_0402_1%~D
_0402_1%~D
12
PR64
PR64
10K_0402_5%~
10K_0402_5%~
3_0603_1%~D
3_0603_1%~D
1 2
3.
3.
2UH
2UH
~D
~D
12
PC74
PC74
@
@
680P_0603_50V8J
680P_0603_50V8J
12
PR70
PR70
@
@
7_0805_5%~D
7_0805_5%~D
4.
4.
O
N 11,38,42,45
RUN_
12
+3
.3V_RUN
D
D
8V_RUN_PWRGD 42
1.
PL8
PL8
_#A915AY-H-2R0M=P3_3.3A_20%~D
_#A915AY-H-2R0M=P3_3.3A_20%~D
12
OCP_MIN: 1.698 A
PC75
PC75
PC76
PC76
1 2
_0805_6.3V4Z~D
_0805_6.3V4Z~D
22U
22U
1 2
22U_0805_6.3V4Z~D
22U_0805_6.3V4Z~D
~D
~D
12
PC77
PC77
47P_0402_50V8J
47P_0402_50V8J
+1
.8V_RUNP
B B
PJP17
PJP17
DC
+1.
5V_MEM
A A
5
2 1
PAD
PAD
-OPEN 2x2m~D
-OPEN 2x2m~D
75V_P
+0.
_1+0.75V_VTT_PWR_SRC
PC82
PC82
1 2
PC83
PC83
_0805_6.3V6M~D
_0805_6.3V6M~D
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
10U
10U
PC81
PC81
PC80
PC80
1 2
1 2
_0805_6.3V6M~D
_0805_6.3V6M~D
_0805_6.3V6M~D
_0805_6.3V6M~D
10U
10U
10U
10U
12
DDR3 Termination
PU5
PU5
1
VDDQ
2
VLD
3
VTT
5
VTTSNS
SNS
OIN
VTTREF
D
PGN
4
4
10
VIN
8
GND
6
9
S5
7
S3
GND
R
R
T9026GFP_MSOP10~D
T9026GFP_MSOP10~D
11
+5V_ALW
12
_DDR_REF
+V
PC78
PC78 1U_0603_10V6K~D
1U_0603_10V6K~D
PC79
PC79
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+0.
75V_S3
@
@
PJP16
PJP16
+1
0.75Volt +/-5% Thermal Design Current: 0.7A Peak current: 1A
PJP18
PJP18
+0.
1 2
+0.
75V_S5
75V_P
12
PR720_0402_5%~
PR720_0402_5%~
D @
D @
12
PR710_0402_5%~D @PR710_0402_5%~D @
2 1
-OPEN 2x2m~D
-OPEN 2x2m~D
PAD
PAD
DDR_O
N 43,49
0.75V_DDR_VTT_ON 42
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
.75V_DDR_VTT
+0
.8V_RUNP
2 1
-OPEN 2x2m~D
-OPEN 2x2m~D
PAD
PAD
VOUT=1.8V L=3.3uF Fsw=290KHz D=0.092 Input Ripple Current=TDC*(D*(1-D))^0.5=0.884A Output Ripple Current=1.707A Output Ripple Voltage=1.707*15m=20.5mV
2
+1
.8V_RUN
DELL CO
Title
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
5V_DDR_VT/+1.8V_RUN
5V_DDR_VT/+1.8V_RUN
5V_DDR_VT/+1.8V_RUN
+0.7
+0.7
+0.7
6611P
6611P
6611P
LA-
LA-
LA-
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
0.1
0.1
50 57Wednes
50 57Wednes
50 57Wednes
0.1
of
of
of
+0.75V_DDR_VTT
5
4
3
2
1
+1.05V_M
D D
PC84
PC84
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
12
GND
A_1.05VM
PC91
PC91
100P_0402_50V8J~D
100P_0402_50V8J~D
C C
05V_MP +1.
PR76
PR76
5.6K_0402_5%~D
5.6K_0402_5%~D
0_0402_5%~
0_0402_5%~
PR81
PR81
12
PR80
PR80
12
1800P_0402_50V7K~
1800P_0402_50V7K~
D
D
12
PC92
PC92
680P_0402_50V7K~D
680P_0402_50V7K~D
2K_0402_1%~D
2K_0402_1%~D
12
1 2
PC93
PC93
12
12
D
D
PR82
PR82
67K_0402_1%~D
67K_0402_1%~D
2.
2.
GND
A_1.05VM
GND
.05VM_COMP
+1
05VM_VFB
+1.
12
PC94
PC94
A_1.05VM
+
1.
+1.
05V_MP
05VM_SS
01U_0402_25V7K~D
01U_0402_25V7K~D
0.
0.
3V_ALW
+3.
17
VCCA
GN
COM
VFB
VOU
SS
16
VIN
VIN
15
VBST
14
P
D
GOOD
13
EN
P
T
D
PGN
7
0_0402_5%~D@
0_0402_5%~D@
12
12
FSET
11
E
MOD
10
IMO
N
D
PGN
SW
SN
SN
1003055RUWR_QFN17_3P5X3P5~D
1003055RUWR_QFN17_3P5X3P5~D
9
8
<BOM Structure>
<BOM Structure>
+1. 05VM_VX
05VM_BST
+1.
1.05VA_PW
05VM_EN
+1.
05VM_FSET
+1.
+
.05VM_MODE
1
+1
.05VM_IMON
3.
3.
RGD
GND
PR74
PR74
3_0603_1%~D
3_0603_1%~D
1 2
22.
22.
1K_0402_1%~D
1K_0402_1%~D
PR79
PR79
@
@
12
PR84
PR84
@
@
A_1.05VM
+1.
12
1 2
GND
A_1.05VM
33K_0402_1%~D
33K_0402_1%~D
1.
1.
PU6
PU6
1
2
3
4
5
6
PR85
PR85
05VM_BST_1
D
D
PR83
PR83
GND
10K_0402_1%~
10K_0402_1%~
1 2
A_1.05VM
+1.
05VM_VX
PC90
PC90
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
PR75
PR75
0_0402_5%~
0_0402_5%~
PR78
PR78
@
@
@
@
D
D
12
12
0_0402_5%~D
0_0402_5%~D
05V_PWR_SRC
+1.
SIO_SLP_A#
A_ON 43,
05VM_VX
+1.
12
@
@
PC95
PC95
0.
0.
1U_0603_25V7K~D
1U_0603_25V7K~D
@
@
PR86
PR86
68K_0805_1%~D
68K_0805_1%~D
7.
7.
1 2
12
12
PC85
PC85
PC86
PC86
@
@
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
10U
10U
10U
10U
16,42
45
PL9
PL9
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
0.42U
0.42U
12
PC87
PC87
_1206_25V6M~D
_1206_25V6M~D
10U
10U
12
12
PC88
PC88
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PC96
PC96
PC97
PC97
_0603_6.3V6M~D
_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U
10U
PJP19
PJP19
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
12
PC89
PC89
+5V
_ALW
ϭϬϱsŽůƚнͲϱй dŚĞƌŵĂůĞƐŝŐŶƵƌƌĞŶƚϮϳ WĞĂŬĐƵƌƌĞŶƚϯϵ KWͺD/Eϰϳ
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+1.
05V_MP
12
12
12
PC99
PC99
PC98
PC98
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
22U
22U
22U
22U
12
12
PC101
PC101
PC100
PC100
_0805_6.3V6M
_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U
22U
12
12
PC102
PC102
_0805_6.3V6M
_0805_6.3V6M
22U
22U
12
PC103
PC103
PC104
PC104
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
22U
22U
22U
22U
12
PC106
PC106
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
D
D
PC107
PC107
6800P_0402_25V7K~
6800P_0402_25V7K~
12
PC105
PC105
_0805_6.3V6M
_0805_6.3V6M
22U
22U
B B
+3.
3V_ALW
D
D
12
PR87
PR87
100K_0402_1%~
100K_0402_1%~
1.05VA_PWRGD
A A
5
PR88
PR88
@
@
12
0_0402_5%~D
0_0402_5%~D
1.05V_A_PW
4
RGD 43
GND
A_1.05VM
3
PJP20
PJP20
1 2
-OPEN1x1m
-OPEN1x1m
PAD
PAD
+1.
05V_MP
PJP21
PJP21
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
PJP22
PJP22
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
2
+1.
05V_M
DELL CO
Title
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
+1
+1
+1
LA-6611P
LA-6611P
LA-6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
.05V_M
.05V_M
.05V_M
1
0.1
0.1
51 57Wednes
51 57Wednes
51 57Wednes
0.1
of
of
of
5
4
3
2
1
+1.05VTT
PC108
PC108
1U
1U
_0402_6.3V6K~D
A_1.05VTT
100P_0402_50V8J~D
100P_0402_50V8J~D
12
PC116
PC116
680P_0402_50V7K~
680P_0402_50V7K~
2K_0402_0.5%~D
2K_0402_0.5%~D
12
1 2
1800P_0402_50V7K~
1800P_0402_50V7K~
PC117
PC117
_0402_6.3V6K~D
D
D
12
D
D
12
5%~D
5%~D
PR130
PR130
20K_0402_0.
20K_0402_0.
GND
A_1.05VTT
12
+1.
05VTT_VX
17
A
VCC
GND
COM
P
VFB
U
T
VO
SS
7
0_0402_5%~D@
0_0402_5%~D@
05VTT_PWRGD
16
N VI
VIN
VBST
PGOOD
EN
FSET
D
E
MO
IMON
D
D N
PGN
SW
PG
SN
SN
1003055RUWR_QFN17_3P5X3P5~D
1003055RUWR_QFN17_3P5X3P5~D
9
8
+1. 05VTT_VX
12
PR101
PR101
31K_0402_1%~D
31K_0402_1%~D
9.
9.
1 2
@
@
PR103
PR103
PR104
PR104
3K_0402_1%~D
3K_0402_1%~D
13.
13.
+1.
05VTT_BST
15
05VTT_PWRGD
+1.
14
05VTT_EN
+1.
13
.05VTT_FSET
+1
12
+1.
05VTT_MODE
11
.05VTT_IMON
+1
10
12
0_0402_5%~D
0_0402_5%~D
12
3.
3.
3_0603_1%~D
3_0603_1%~D
GND
+5
PR89
PR89
1 2
1K_0402_1%~D
1K_0402_1%~D
22.
22.
@
@
PR92
PR92
12
PR97
PR97
@
@
A_1.05VTT
V_RUN
1.05V_VT
PC114
PC114
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
1 2
@
@
0_0402_5%~
0_0402_5%~
1 2
12
1 2
GND
A_1.05VTT
33K_0402_1%~D
33K_0402_1%~D
1.
1.
TPWRGD 43,56
PR91
PR91
D
D
GND
PR95
PR95
0_0402_5%~
0_0402_5%~
D
D
A_1.05VTT
PU7
PU7
3V_ALW
+3.
1
2
05VTT_COMP
+1.
+1.
+1.
PC118
PC118
12
GND
A_1.05VTT
PR96
PR96
09K_0402_5%~D
09K_0402_5%~D
3.
3.
05VTT_VFB
05VTT_SENSE
05VTT_SS
+1.
12
01U_0402_25V7K~D
01U_0402_25V7K~D
0.
0.
3
4
5
6
PR98
PR98
+1.
D D
GND
PC115
PC115
PR90
PR90
6K_0402_5%~D
6K_0402_5%~D
5.
5.
12
PR93
PR93
12
0_0402_5%~
0_0402_5%~
D
D
PR94
PR94
05VTT_SENSE +1.
C C
@
@
PC377
PC377
_0805_6.3V4Z~D
_0805_6.3V4Z~D
22U
22U
+
05VTT_PWR_SRC
1.
1 2
@
@
U_VTT_ON 42,56
CP
+1.
05VTT_VX
12
@
@
PC119
PC119
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PR99
PR99
@
@
7.
7.
68K_0805_1%~D
68K_0805_1%~D
1 2
PC376
PC376
1 2
PC109
PC109
_1206_25V6M~D
_1206_25V6M~D
22U_0805_6.3V4Z~D
22U_0805_6.3V4Z~D
10U
10U
0.42U
0.42U
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
12
PL10
PL10
PC110
PC110
_1206_25V6M~D
_1206_25V6M~D
10U
10U
12
+1.
05VTT_SENSE
12
GND
PC111
PC111
12
D
D
PR100
PR100
10_0402_5%~
10_0402_5%~
A_1.05VTT
12
12
PC112
PC112
_1206_25V6M~D
_1206_25V6M~D
10U
10U
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PC129
PC129
PC120
PC120
_0805_6.3V6M
_0805_6.3V6M
22U
22U
22U_0805_6.3V6M
22U_0805_6.3V6M
PR102
PR102
1 2
0_0402_5%~
0_0402_5%~
PR118
PR118
1 2
0_0402_5%~
0_0402_5%~
PJP23
PJP23
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
12
PC113
PC113
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
_ALW
+5V
ϭϬϱsŽůƚнͲϱй dŚĞƌŵĂůĞƐŝŐŶƵƌƌĞŶƚϵϮ WĞĂĐŬĐƵƌƌĞŶƚϭϯϭ KWͺD/Eϭϱϴ
05VTTP
+1.
12
12
12
PC121
PC121
_0805_4V6M~D
_0805_4V6M~D
47U
47U
D
D
D
D
12
12
PC122
PC122
_0805_6.3V6M
_0805_6.3V6M
22U
22U
12
PC130
PC130
PC123
PC123
_0805_6.3V6M
_0805_6.3V6M
22U
22U
22U_0805_6.3V6M
22U_0805_6.3V6M
VTT_
VTT_
12
PC124
PC124
_0805_4V6M~D
_0805_4V6M~D
47U
47U
SENSE 10
GND 10
12
PC126
PC126
PC125
PC125
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
_0805_6.3V6M
22U
22U
22U
22U
12
PC128
PC128
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
D
D
PC131
PC131
6800P_0402_25V7K~
6800P_0402_25V7K~
12
PC127
PC127
_0805_6.3V6M
_0805_6.3V6M
22U
22U
B B
PJP25
A_1.05VTT
PJP25
PAD
PAD
-OPEN1x1m
-OPEN1x1m
12
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
L95870A +1.05V_RUN_VTT
L95870A +1.05V_RUN_VTT
L95870A +1.05V_RUN_VTT
IS
IS
IS
LA-6611P
LA-6611P
LA-6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
0.1
0.1
52 57Wednes
52 57Wednes
52 57Wednes
0.1
of
of
of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
DELL CO
Title
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PJP24
PJP24
1 2
PAD-OPEN 43X118
PAD-OPEN 43X118
PJP26
+1.
A A
05VTTP
5
PJP26
1 2
-OPEN 43X118
-OPEN 43X118
PAD
PAD
.05V_RUN_VTT
+1
GND
4
5
PC281
PC281
1 2
0.
0.
01U_0402_25V7K~D
01U_0402_25V7K~D
PC278
PC278
1 2
.
.
1U_0402_16V7K~D
1U_0402_16V7K~D
PR109
PR122
PR122
1 2
_VCC
10_0402_5%~D
10_0402_5%~D
1 2
@
@
PC150
PC150
10_0402_5%~D
10_0402_5%~D
1 2
75_0402_5%~D@
75_0402_5%~D@
1 2
1 2
PR146
PR146
@
@
0_0402_5%~
0_0402_5%~
PC205
PC205
1 2
12
1000P_0402_50V7K~
1000P_0402_50V7K~
GNDA
PR157
PR157
PC167
PC167
PR171
PR171
@
@
_VCC
PR109
9K_0402_1%~D
9K_0402_1%~D
5.
5.
1 2
TJ0EG103FA~D
TJ0EG103FA~D
10_0402_5%~D
10_0402_5%~D
2U_0603_10V7K~D
2U_0603_10V7K~D
2.
2.
1 2
PR132
PR132
D
D
D
D
D
D
+VGFX_GNDSB
PC163
PC163
_VCC
7.5K_0402_1%~D
7.5K_0402_1%~D
+VG
12
D
D
+GFX_POKB
12
D
D
PJP28
PJP28
1 2
-OPEN1x1m
-OPEN1x1m
PAD
PAD
D D
Layout Note: PC142 close to PIN19
PR121
PR121
@
@
0_0402_5%~
0_0402_5%~
+5V_ALW
C C
PR149
PR149
1 2
VSS_AXG_SENSE11
B B
VCC
_AXG_SENSE11
+VCC_GFXCORE
PR158
PR158
VP_PGOOD42
IM
A A
12
PC277
PC277
@
@
_0603_10V6K~D
_0603_10V6K~D 1U
1U
VSSSEN
VCCS
PR142
PR142
10_0402_5%~D
10_0402_5%~D
1 2
10_0402_5%~D
10_0402_5%~D
1 2
C_PWR_SRC
+VC
10_0402_5%~D@
10_0402_5%~D@
PR137
PR137
1 2
SE10
ENSE10
1 2
10_0402_5%~D@
10_0402_5%~D@
+1
.05V_RUN_VTT
ROCHOT#7,43
H_P
GNDA
10_0402_5%~D
10_0402_5%~D
PR153
PR153
1 2
PC165
PC165
@
@
1000P_0402_50V7K~
1000P_0402_50V7K~
10_0402_5%~D
10_0402_5%~D
PR156
PR156
1 2
+3
.3V_RUN
D
D
1 2
10K_0402_1%~
10K_0402_1%~
5
_VCC
+G
D
D
PR165
PR165
PC142
PC142
FX_CSPB154
GNDA
PC269
PC269
+V
D
D
0_0402_5%~
0_0402_5%~
10K_0402_1%_ER
10K_0402_1%_ER
core_VDD
12
GNDA
2U_0603_10V7K~D
2U_0603_10V7K~D
2.
2.
PR138
PR138
1000P_0402_50V7K~
1000P_0402_50V7K~
PR139
PR139
PR143
PR143
1 2
43P_0402_50V8J
43P_0402_50V8J
_VCC
1000P_0402_50V7K~
1000P_0402_50V7K~
12
D
D
12
1000P_0402_50V7K~
1000P_0402_50V7K~
GNDA_VCC
PR166
PR166
@
@
1 2
0_0402_5%~
0_0402_5%~
GNDA
12
PH1
PH1
PC143
PC143
1 2
1.05V_0.
IM
100K_0402_5%~D
100K_0402_5%~D
12
12
PC158
PC158
1000P_0402_50V7K~
1000P_0402_50V7K~
GNDA
_VCC
D
D
FX_FBB
+V
core_POKA
PR330
PR330
1 2
0_0402_5%~
0_0402_5%~
D
D
PR111
PR111
09K_0402_1%~D
09K_0402_1%~D
3.
3.
8V_PWROK43
VP_VR_ON42
+VG
+V
core_GNDSA
12
PC149
PC149
1000P_0402_50V7K~
1000P_0402_50V7K~
GNDA
_VCC
8.45K_0402_1%~D
8.45K_0402_1%~D
PR140
PR140
D
D
X_CSNB54
+GF
+1
12
FX_TONB
D
D
+V
12
core_VRHOT#
+V
FX_FBB
+VG
+VGF
FX_BSTB54
+G
+G
+G
+G
.05V_RUN_VTT
DALERT_N10
VI
@
@
PR131
PR131
core_FBA
X_GNDSB
FX_LXB54
FX_DHB54
FX_DLB54
VID
DSCLK10
VI
PR110
PR110
PR112
PR112
PR115
PR115
1 2
PR129
PR129
1 2
PU9
PU9
2
3
4
5
6
7
8
9
10
SOUT10
4
12
12.7K_0402_1%~D
12.7K_0402_1%~D
12
12.7K_0402_1%~D
12.7K_0402_1%~D
12
12.7K_0402_1%~D
12.7K_0402_1%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D@
0_0402_5%~D@
41
TPAD
TON
GNDS
A
FBA
T#
VRHO
FBB
B
GNDS
CSPB1
CSNB
POKB
PC173
PC173
1 2
130_0402_1%~D
130_0402_1%~D
PR159
PR159
PR160
PR160
130_0402_1%~D@
130_0402_1%~D@
PR162
PR162
54.9_0402_1%~D
54.9_0402_1%~D
1 2
PR164
PR164
1 2
PR167 0_0402_5%~DPR167 0_0402_5%~D
1 2
PR168
PR168
4
P1_SW
P2_SW
P3_SW
core_CSPA3+Vcore_CSPA2+Vcore_CSNA
core_VCC+Vcore_EN
+V
+V
1
40
38
EN
VCC
CSPA339CSPA2
M
M
AX17511GTL+T_TQFN40_5X5~D
AX17511GTL+T_TQFN40_5X5~D
BSTB11LXB12DHB13DLB14V
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
12
12
12
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
3
ATE3
UG
+5V_ALW
PC138
PC138 _0603_10V6K~D
_0603_10V6K~D
1U
1U
12
X_THERMB
core_CSPA1
core_CSPAAVE
+V
+V
37
36
SPA1
CSNA
C
DDB
15
core_VDD +V
35
CSPAAVE
+VGF
34
RMB
THE
O
VDI
16
core_VDIO +V
core_THERMA+Vcore_SR V +
32
33
SR
RMA
THE
T#
ALER
CLK18POKA
17
core_CLK
core_ALERT#
+V V +
core_PWMA +V
31
WMA
DRVP
AXB
IM
IM
AXA
BSTA2
LXA2
DHA2
DLA
VD
DLA
DHA1
LXA1
BSTA1
19
core_POKA +V
D
PU8
PU8
5
6
2
3
9
PR123
PR123
62K_0402_1%~D
62K_0402_1%~D
5.
5.
PH2
PH2
SM0B104F4251RZ~D
SM0B104F4251RZ~D
100K_0402_1%_T
100K_0402_1%_T
+G
FX_IMAXB
30
+V
core_IMAXA
29
BOST2
28
P2_SW
27
UGA
26
LGAT2
25
2
+V
core_VDD
24
A
23
1
22
21
20
1
BST
VDD
8
SKIP
DH
7
PWM
LX
4
DL
GND
EP
M
M
AX17491GTA+T_TQFN8_3X3~D
AX17491GTA+T_TQFN8_3X3~D
PR124
PR124
PR125
1 2
1 2
TE2
PR125
1 2
5.62K_0402_1%~D
5.62K_0402_1%~D
PR133
PR133
PH3
PH3
@
@
1 2
GNDA
100K_0402_1%_TSM0B104F4251RZ~D
100K_0402_1%_TSM0B104F4251RZ~D
12
PC160
PC160
UG
ATE1
BOST1
P1_SW
D
D
1 2
1K_0402_5%~
1K_0402_5%~
D
D
1 2
10K_0402_1%~
10K_0402_1%~
_VCC
2U_0603_10V7K~D
2U_0603_10V7K~D
2.
2.
LGATE1
BOST3
LGATE3
+V
core_VCC
D
D
PR126
PR126
1 2
107K_0402_1%~
107K_0402_1%~
D
D
PR134
PR134
1 2
154K_0402_1%~
154K_0402_1%~
PR141
PR141
2.
2.
2_0603_5%~D
2_0603_5%~D
PR161
PR161
2.
2.
2_0603_5%~D
2_0603_5%~D
PR107
PR107
2.
2.
2_0603_5%~D
2_0603_5%~D
P3_SW
PR127
PR127
PR135
PR135
12
BT1_1
12
BT3_1
12
1 2
165K_0402_1%
165K_0402_1%
core_IMAXA
+V
+G
FX_IMAXB
D
D
1 2
105K_0402_1%~
105K_0402_1%~
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
BT2_1
12
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
1 2
12
PC176
PC176
@
@
1000P_0402_50V7K~
1000P_0402_50V7K~
PC137
PC137
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
1 2
12
PC140
PC140
@
@
1000P_0402_50V7K~
1000P_0402_50V7K~
PC157
PC157
1 2
@
@
PC161
PC161
1000P_0402_50V7K~
1000P_0402_50V7K~
PC174
PC174
D
D
D
D
@
@
PQ11
PQ11
@
@
4
D
D
PQ9,PQ11,PQ13 PQ10,PQ14,PQ15
Main
2nd
X7629631L
X7629631L89
88
AO
N6414AL
MDU2657RH
AON6704L
MDU2653RH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PQ15
PQ15
2
D
D
12
PC147
PC147
4.7U_0805_25VAK
4.7U_0805_25VAK
core_CSPA3
+V
_VCC
GNDA
+V
core_CSNA
12
PC148
PC148
7U_0805_25VAK
7U_0805_25VAK
4.
4.
+V
core_CSPA2
GNDA
_VCC
core_CSNA
+V
PR173
PR173
@
@
_VCC
1000P_0402_50V7K~
1000P_0402_50V7K~
1000P_0402_50V7K~
1000P_0402_50V7K~
12
PC132
PC132
PC133
PC133
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0. 2200P_0402_50V7K~
2200P_0402_50V7K~
12
D
D
PC139
PC139
@
@
12
1500P_0603_50V7K~
1500P_0603_50V7K~
@
@
PC145
PC145
@
@
1 2
1000P_0402_50V7K~
1000P_0402_50V7K~
12
12
PC151
PC151
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0. 2200P_0402_50V7K~D
2200P_0402_50V7K~D
12
D
D
PC159
PC159
@
@
12
1500P_0603_50V7K~
1500P_0603_50V7K~
PR148
PR148
@
@
PC164
PC164
@
@
1 2
1000P_0402_50V7K~
1000P_0402_50V7K~
12
PC276
PC276
7U_0805_25VAK
7U_0805_25VAK
4.
4.
12
D
D
PC175
PC175
@
@
12
1500P_0603_50V7K~
1500P_0603_50V7K~
1_1206_5%
1_1206_5%
@
@
PC178
PC178
1 2
D
D
PC180
PC180
@
@
1 2
D
D
12
PC134
PC134
PR117
PR117
1_1206_5%
1_1206_5%
D
D
PC152
PC152
7U_0805_25VAK
7U_0805_25VAK
4.
4.
1_1206_5%
1_1206_5%
D
D
12
PC226
PC226
4.7U_0805_25VAK
4.7U_0805_25VAK
7U_0805_25VAK
7U_0805_25VAK
4.
4.
+VCC_
12
241
5
123
PC214
PC214
DFN
DFN
AON6414AL 1N
AON6414AL 1N
FN8-5
FN8-5
AON6704L_D
AON6704L_D
DFN
DFN
AON6414AL 1N
AON6414AL 1N
123
2
PC168
PC168
7U_0805_25VAK
7U_0805_25VAK
4.
4.
AON6414AL 1N DFN
AON6414AL 1N DFN
FN8-5
FN8-5
AON6704L_D
AON6704L_D
12
7U_0805_25VAK
7U_0805_25VAK
4.
4.
AON6704L_DFN8-5
AON6704L_DFN8-5
+V
GNDA
core_CSNA
+V
GNDA_VCC
12
PC192
PC192
core_CSPA1
@
@
PQ9
PQ9
3 5
@
@
PQ10
PQ10
4
3 5
241
5
123
PQ13
PQ13
@
@
3 5
241
5
@
@
PQ14
PQ14
4
+VCC_
12
12
PC135
PC135
7U_0805_25VAK
7U_0805_25VAK
4.
4.
PR113
PR113
PC146
PC146
0.
0.
22U_0402_16V7K~D
22U_0402_16V7K~D
12
PWR_SRC
1
12
PC154
PC154
PC153
PC153
PC169
PC169
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
0.
0.
22U_0402_16V7K~D
22U_0402_16V7K~D
4.7U_0805_25VAK
4.7U_0805_25VAK
PR144
PR144
PC166
PC166
22U_0402_16V7K~D
22U_0402_16V7K~D
0.
0.
12
PC170
PC170
PR169
PR169
PC179
PC179
12
2
_25V_M_R0.7~D
_25V_M_R0.7~D
100U
100U
12
12
D
D
12
PC171
PC171
2200P_0402_50V7K~
2200P_0402_50V7K~
P1_SW
12
2K_0402_0.
2K_0402_0.
3.
3.
DELL CO
Title
e
e
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
Date: Sheet
Date: Sheet
Date: Sheet
1
PWR_SRC
PL11
PL11
0.42U
0.42U
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
1 2
P3_SW
12
2K_0402_0.
2K_0402_0.
5%~D
5%~D
PR120
PR120
3.
3.
24K_0402_1%~D
24K_0402_1%~D
@
@
PC144
PC144
1 2
1000P_0402_50V7K~
1000P_0402_50V7K~
1
+
+
+
+
PC155
PC155
PC156
PC156
2
100U_25V_M_R0.7~D
100U_25V_M_R0.7~D
PL12
PL12
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
0.42U
0.42U
1 2
P2_SW
2K_0402_0.
2K_0402_0.
5%~D
5%~D
PR152
PR152
12
24K_0402_1%~D
24K_0402_1%~D
3.
3.
@
@
PC162
PC162
1 2
1000P_0402_50V7K~
1000P_0402_50V7K~
12
12
PC172
PC172
7U_0805_25VAK
7U_0805_25VAK
4.
4.
7U_0805_25VAK
7U_0805_25VAK
4.
4.
PL13
PL13
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
0.42U
0.42U
1 2
5%~D
5%~D
PR176
PR176
12
24K_0402_1%~D
24K_0402_1%~D
@
@
PC177
PC177
1 2
1000P_0402_50V7K~
1000P_0402_50V7K~
_25V_M_R0.7~D
_25V_M_R0.7~D
100U
100U
D
D
12
1
+
+
2
+VCC_
12
D
D
1 2
PAD
PAD
D
D
PR170
PR170 1_0402_5%~
1_0402_5%~
12
PR114
PR114 1_0402_5%~
1_0402_5%~
PJP27
PJP27
-OPEN 4x4m
-OPEN 4x4m
12
PR145
PR145 1_0402_5%~
1_0402_5%~
PWR_SRC
+V
CC_CORE
D
D
+PW
+V
CC_CORE
D
D
CC_CORE
+V
D
D
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Vcore
Vcore
Vcore
DB-609
DB-609
DB-609
1
53 57Wednes
53 57Wednes
53 57Wednes
of
of
of
R_SRC
0.1
0.1
0.1
5
D D
C C
FX_DHB53
+G
FX_BSTB53
+G
+G
FX_LXB53
FX_DLB53
+G
B B
PR189
PR189
2_0603_5%~D
2_0603_5%~D
2.
2.
4
12
0.
0.
GBT1_1
1 2
12
PC203
PC203
4700P_0402_25V7K~
4700P_0402_25V7K~
PC197
PC197
22U_0603_10V7K~D
22U_0603_10V7K~D
3
VGF
X_PWR_SRC
+
PJP29
PJP29
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
12
PQ21
PQ24
PQ24
@
@
PQ25
PQ25
@
@
4
D
D
PQ21
FN8~D
FN8~D
FN8~D
AON6414AL_D
AON6414AL_D
3 5
241
5
FN8-5
FN8-5
AON6704L_D
AON6704L_D
123
FN8~D
@
@
AON6414AL_D
AON6414AL_D
3 5
241
5
PQ26
PQ26
FN8-5
4
FN8-5
@
@
AON6704L_D
AON6704L_D
123
PC193
PC193
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PC194
PC194
12
~D
~D
PC198
PC198
@
@
12
470P_0603_50V8J
470P_0603_50V8J
12
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PR193
PR193
@
@
2_1206_1%~D
2_1206_1%~D
2.
2.
12
12
PC195
PC195
_1206_25VAK~D
_1206_25VAK~D
10U
10U
12
PC196
PC196
PC204
PC204
_1206_25VAK~D
_1206_25VAK~D
10U
10U
10U_1206_25VAK~D
10U_1206_25VAK~D
PL15
PL15
0.36U
0.36U
H_FDUE1040J-H-R36M=P3_33A_20%~D
H_FDUE1040J-H-R36M=P3_33A_20%~D
1
GP1_SW GP1_Vo
2
12
1.
1.
37K_0402_1%~D
37K_0402_1%~D
PR190
PR190
+PW
4
3
R_SRC
2
C_GFXCORE
+VC
D
_D2_2VM_R4.5M~D
_D2_2VM_R4.5M~D
470U
470U
+
+
PC202
PC202
_D2_2VM_R4.5M~D
_D2_2VM_R4.5M~D
470U
470U
D
1
PC199
PC199
2
2200P_0402_50V7K~
2200P_0402_50V7K~
1
12
+
+
PC206
PC206
2
@
@
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
1
12
+
+
PC201
PC201
2
PC200
PC200
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
1
12
D
+G
FX_CSPB153
PQ21,PQ24 PQ25,P Q26
Main
X7629631L
2nd
X7629631L89
A A
5
88
N6414AL
AO
MDU2657RH
AON6704L
MDU2653RH
X_CSNB53
+GF
_VCC
GNDA
1000P_0402_50V7K~D
1000P_0402_50V7K~D
4
10K_0402_1%_ER
10K_0402_1%_ER
PC207
PC207
1 2
PC282 0.068U_0402_16V7K~DPC 282 0.068U_0402_16V7K~D
1 2
PC208
PC208
1 2
0.
0.
33U_0402_10V6K
33U_0402_10V6K
PR201
PR201
@
@
40.
40.
2K_0402_1%~D
2K_0402_1%~D
1 2
TJ0EG103FA~D
TJ0EG103FA~D
0_0402_5%~
0_0402_5%~
12
PH4
PH4
2.
2.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3
PR192
PR192
12
D
D
PR203
PR203
12
1K_0402_1%~D
1K_0402_1%~D
D
PR191
PR191
0_0402_5%~
0_0402_5%~
DELL CO
Title
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
L95870A +1.05V_RUN_VTT
L95870A +1.05V_RUN_VTT
L95870A +1.05V_RUN_VTT
IS
IS
IS
LA-6611P
LA-6611P
LA-6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
0.1
0.1
54 57Wednes
54 57Wednes
54 57Wednes
0.1
of
of
of
5
PD14@
PD14@
2 1
SBR3A40SA-13_SM
SBR3A40SA-13_SM
A2
A2
PQ27
PQ27
SI4835D
SI4835D
DY-T1-E3_SO8~D
DY-T1-E3_SO8~D
8
PR206
PR206
0_0402_5%~
0_0402_5%~
@
@
7
5
12
D
D
+DC_
IN_SS
D D
DC
_BLOCK_GC57
1 2 36
4
_GC57
CSS
E3 AC_OK=17.7 Volt
C C
B B
+SDC_IN=19.5V-->ACIN=2.66V ACIN>2.4V-->ACOK High
BQ24765_IINP22
PJP34
PJP34
1 2
-OPEN1x1m
-OPEN1x1m
PAD
_CHG
PAD
GNDA
0.
0.
_CHG
GNDA
PR226
PR226
~D
~D
12
PC229
PC229
220P_0402_50V8J
220P_0402_50V8J
PR218
PR218
49.
49.
9K_0402_1%~D
9K_0402_1%~D
12
PC216
PC216
12
01U_0402_25V7K~D
01U_0402_25V7K~D
1 2
PR224
PR224
200K_0402_5%~
200K_0402_5%~
12
7K_0402_5%~D
7K_0402_5%~D
PC228
PC228
4.
4. 120P_0402_50VN
120P_0402_50VN
1 2
1 2
PR207
PR207
0_0402_5%~
0_0402_5%~
@
@
S
DC_IN
+
D
D
PR217
PR217
1 2
316K_0402_1%~
316K_0402_1%~
D
D
PO~D
PO~D
DC_IN
+S
D
D
NT
NT
D
D
2200P_0402_50V7K~
2200P_0402_50V7K~
PC227
PC227
1 2
56P_0402_50V8~
56P_0402_50V8~
GNDA_CHG
R4502PT1G_SOT23-3~D
R4502PT1G_SOT23-3~D
zEͺdhZͺhZZEdͺ^dη
ϲϱt
ϵϬt
A A
DYN_
TUR_CURRNT_SET#
,ŝŐŚ
>Žǁ
PR295
PR295
_0402_1%~D
_0402_1%~D
2M
2M
T
1 2
PQ38
PQ38
U002N06_SOT323-3~D
U002N06_SOT323-3~D
RH
RH
bq24765_REF
D
D
12
PR259
PR259
100K_0402_1%~
100K_0402_1%~
12
PR261
PR261
1K_0402_1%~D
1K_0402_1%~D
PR260
PR260
2K_0402_1%~D
2K_0402_1%~D
93.
93.
13
D
D
42.
2
G
G
5
42.
S
S
12
ICREFICOU
~D
~D
12
PC279
PC279
100P_0402_50V8J
100P_0402_50V8J
@
@
12
PC210
PC210
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PQ29
PQ29
PC212
PC212
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
1 2
GNDA
_CHG
12
PC225
PC225
10K_0402_5%~
10K_0402_5%~
12
PC234
PC234
_0603_10V6K~D
_0603_10V6K~D 1U
1U
@
@
PC245
PC245
1 2
01U_0402_25V7K~D
01U_0402_25V7K~D
0.
0.
4
2
G
G
PR209
PR209
1 2
7.
7.
5K_0402_5%~D
5K_0402_5%~D
D
D
PR228
PR228
1 2
1 2
4
0.
0.
01_1206_1%~D
01_1206_1%~D
4
3
13
D
D
S
S
SSP_1 C
@
@
10K_0402_5%~
10K_0402_5%~
D
D
12
0_0402_5%~
0_0402_5%~
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
1 2
bq24765_II
PR225
PR225
bq24765_REF
D
D
CHARG
CHARG
+5V_ALW
~D
~D
@
@
PC244
PC244
100P_0402_50V8J
100P_0402_50V8J
8
PU12B
PU12B
5
P
+
O
6
-
G
LM
LM
4
PR205
PR205
2
G
G
PR208
PR208
12
PC213
PC213
NP
chg_F
BO
chg_EAI
chg_EAO
E
chg_C
ER_SMBDAT43
ER_SMBCLK43
7
393DR_SO8~D
393DR_SO8~D
1
2
13
D
D
S
S
_1
CSSN
D
D
12
PQ28
PQ28 NT
NT
R4502PT1G_SOT23-3~D
R4502PT1G_SOT23-3~D
D
D
PR210
PR210
0_0402_5%~
0_0402_5%~
bq24765_REF
ICREF
chg_EAO
chg_EAI
chg_F
10K_0402_1%~
10K_0402_1%~
PL_PHO
NT
NT
GD4161PT1G_TSOP6~D
GD4161PT1G_TSOP6~D
S
S
G
G
D
D
12
PR211
PR211
100K_0402_1%~
100K_0402_1%~
_CHG
GNDA
1
2
3
4
5
6
7
8
9
10
11
BO
12
+5V_ALW
PR474
PR474
D
D
T
2
PQ30A
PQ30A
1
PU11
PU11
PGN
DCIN_
DCIN_
DCIN_
CSSN
CSSP
VREF
ICRE
ACI
EAO
EAI
FBO
PR212
PR212
N
12
61
D
D
NT
NT
D
D
100K_0402_1%~
100K_0402_1%~
35
TP
D
P
P
P
F
2N7002D
2N7002D
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
65
PQ30B
PQ30B
GD4161PT1G_TSOP6~D
GD4161PT1G_TSOP6~D
S
S
D
D
42
G
G
12
3
0_0402_5%~
0_0402_5%~
1 2
34
33
32
D
D
D
PGN
PGN
PGN
SDA15VICM
SCL
CE
16
13
14
E
bq24765_IINP
chg_C
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
3
5
4
PQ58A
PQ58A
3
PL16
PL16
FB
FB
MJ4516HS720NT_2P~D
MJ4516HS720NT_2P~D
R_SRC
+PW
_DCIN_IS+ 41
DOCK
_DCIN_IS- 41
DOCK
@
@
PR216
PR216
D
D
SS_GC 57
DK_C
31
30
PHASE
PHASE
29
PHASE
28
PHASE
27
PHASE
BOOT
DCIN_
VDD
ICO
CSO
CSO
AGN
ACO
MB
VDDS
17
BQ24765R
BQ24765R
PQ58B
PQ58B
A
P
UT
P
N
VFB
D
K
2.
2.
BOOT
1 2
26
DCIN_A
25
bq24765_LDO
24
T
ICOU
23
22
21
VFB
20
19
GNDA
18
UVR_QFN34_7X3P5~D
UVR_QFN34_7X3P5~D
12
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
GNDA
_CHG
PR337
@ PR337
@ 1 2
0_0402_5%~D
0_0402_5%~D
1 2
PR336
PR336
0_0402_5%~
0_0402_5%~
D
D
@
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PR219
PR219
2_0603_1%~D
2_0603_1%~D
_CHG
+5V_ALW
PC223
PC223
DYN_
TUR_PWR_ALRT#
ROCHOT#
H_P 7,43
12
PC217
PC217
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
BOOT_D
PR331
PR331
@
@
1 2
0_0402_5%~
0_0402_5%~
@
@
1U
1U
_0603_10V6K~D
_0603_10V6K~D
100_0402_5%~
100_0402_5%~
1 2
PJP33
PJP33
1 2
-OPEN 4x4m
-OPEN 4x4m
PAD
PAD
+V
CHGR_phase
PD15
PD15
54HT1G_SOD323-2~D
54HT1G_SOD323-2~D
BAT
BAT
1 2
D
D
12
PC280
PC280
PR230
PR230
D
D
_CHG
GNDA
0_0402_5%~D
0_0402_5%~D
12
PR221
PR221
@
@
12
CHGR
+V
PC224
PC224
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC242
PC242
100P_0402_50V8J~D
100P_0402_50V8J~D
~D
~D
PC209
PC209
47P_0402_50V8J
47P_0402_50V8J
PC222
PC222
1U
1U
_0603_10V6K~D
_0603_10V6K~D
1 2
12
PR332
PR332
10K_0402_1%~
10K_0402_1%~
PL_PH
O
_CHG
GNDA
bq24765_REFVFB
12
12
bq24765_REF
+DC_
D
D
PR235
PR235
232K_0402_1%~
232K_0402_1%~
12
PR241
PR241
6K_0402_1%~D
6K_0402_1%~D
22.
22.
12
PC211
PC211
@
@
+5V_ALW
D
D
T
D
D
PR215
PR215
10K_0402_5%~
10K_0402_5%~
12
8K_0402_1%~D
8K_0402_1%~D
@
@
15.
15.
IN
12
PR237
PR237
12
PR242
PR242
CHAG
12
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
3.3U
3.3U
12
1 2
bq24765_LDO
12
PR222
PR222
D
D
12
47K_0402_1%~
47K_0402_1%~
12
2K_0402_1%~D
2K_0402_1%~D
42.
42.
2
ER_SRC
PL17
12
D
D
GNDA
PR236
PR236
1M_0402_1%~D
1M_0402_1%~D
1 2
+5V_ALW
8
3
P
+
2
-
G
4
PL17
_CHG
DCIN_A
PU12A
PU12A
LM
LM
H_SPC-1040R-3R3 HF_7.5A_30%~D
H_SPC-1040R-3R3 HF_7.5A_30%~D
PC230
PC230
1000P_0603_50V7K~
1000P_0603_50V7K~
PR234
PR234
7_1206_5%~D
7_1206_5%~D
4.
4.
PR214
PR214
@
@
10K_0402_1%~D
10K_0402_1%~D
ACAV_IN 22,43,57
~D
~D
PC243
PC243
100P_0402_50V8J
100P_0402_50V8J
2
D
D
12
12
PC219
PC219
PC218
PC218
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
2200P_0402_50V7K~
2200P_0402_50V7K~
Maximum charging current support 6A Fsw=700kHz
0.
0.
+V
CHGR_L
12
0.
0.
1U_0603_25V7K~D
1U_0603_25V7K~D
1
O
393DR_SO8~D
393DR_SO8~D
PC240
PC240
1 2
PR232
PR232
0_0402_5%~D
0_0402_5%~D
1_0805_5%~
1_0805_5%~
1U_0805_50V7M~D
1U_0805_50V7M~D
0.
0.
+3.
3V_ALW
D
D
12
PR238
PR238
@
@
100K_0402_1%~
100K_0402_1%~
PR213
PR213
4
3
12
0.
0.
12
PC221
PC221
PC220
PC220
_1206_25V6M~D
_1206_25V6M~D
10U
10U
PR227
PR227
01_1206_1%~D
01_1206_1%~D
PC241
PC241
1 2
1U_0603_25V7K~D
1U_0603_25V7K~D
12
D
D
PC215
PC215
1 2
bq24765_REF
D
D
12
PR239
PR239
10K_0402_1%~
10K_0402_1%~
12
PR243
PR243
2K_0402_1%~D
2K_0402_1%~D
@
@
41.
41.
12
_1206_25V6M~D
_1206_25V6M~D
10U
10U
1
2
D
D
PR233
PR233
0_0402_5%~
0_0402_5%~
DELL CO
Title
e
e
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
CHGR
+V
12
PC236
PC236
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
+CHG
1 2
PR240
PR240
0_0402_5%~
0_0402_5%~
@
@
12
PC237
PC237
_1206_25V6M~D
_1206_25V6M~D
10U
10U
R_DC_IN 57
D
D
12
12
PC238
PC238
_1206_25V6M~D
_1206_25V6M~D
10U
10U
ACAV_I
ACAV_I
12
PR231
PR231
@
@
PC239
PC239
_1206_25V6M~D
_1206_25V6M~D
10U
10U
2
G
G
N
@
@
PQ34
PQ34
U002N06_SOT323-3~D
U002N06_SOT323-3~D
RH
RH
N_NB 42, 43,57
12
8K_1206_5%~D
8K_1206_5%~D
1.
1.
13
D
D
S
S
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
ger
ger
ger
Char
Char
Char
6611P
6611P
6611P
LA-
LA-
LA-
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
55 57Wednes
55 57Wednes
55 57Wednes
0.1
0.1
0.1
of
of
of
5
0.9V 0.85V VCCSA_VID_1 0 1
D D
output voltage adjustable network
de-pop for BGA1023 0.85V
C C
D
D
1
PC249
PC249
PAD
PAD
-OPEN 43X118
-OPEN 43X118
+3.
3V_ALW
B B
PJP35
PJP35
12
2200P_0402_50V7K~
2200P_0402_50V7K~
CCSA_PWR_SRC
+V
2
2
PC248
PC248
1 2
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
2
PC247
PC247
PC246
PC246
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
_1206_25V6M~D
1
1
10U
10U
10U
10U
H_VC
CSA_VID111
CSA_PWR_SRC
+VC
GNDA
4
SAPWROK43
VCC
PC250
PC250
2.
2.
2U_0603_10V7K~D
2U_0603_10V7K~D
1 2
_VCCSA
+5
V_RUN
PC251
PC251
0.
0.
22U_0402_10V6K~D
22U_0402_10V6K~D
3300P_0402_50V7K~
3300P_0402_50V7K~
@
@
0_0402_5%~
0_0402_5%~
12
PR264
PR264
PR266
PR266
1K_0402_5%~
1K_0402_5%~
PR258
PR258
0_0402_5%~
0_0402_5%~
@
@
10_0402_1%~
10_0402_1%~
19
20
21
22
23
24
PC383
PC383
12
D
D
PR303
PR303
D
D
+1.
D
D
12
D
D
PU13
PU13
PGN
PGN
PGN
VIN
VIN
VIN
12
4.
4.
05V_RUN
PR263
PR263
@
@
10K_0402_5%~
10K_0402_5%~
1 2
+5
V_RUN
D
D
1 2
PR244
PR244
100K_0402_5%~
100K_0402_5%~
D
D
PC252
PC252
1 2
12
18
17
ILT
DRV
V5F
V5
D
D
D
PS51461RGER_QFN24_4X4~D
PS51461RGER_QFN24_4X4~D
T
T
GND
VREF
2
1
12
PR247
PR247
99K_0402_1%~D
99K_0402_1%~D
_0603_10V6K~D
_0603_10V6K~D 1U
1U
D
D
12
+VC
+VC
CSA_PWRGD
CSA_PWRGD
16
3
PGOOD
P
COM
PC262
PC262
01U_0402_25V7K~D
01U_0402_25V7K~D
0.
0.
12
15
VID1
SLEW
4
1 2
CSA_VID1
+VC
PR333
PR333 0_0402_5%~
0_0402_5%~
+VCCSA_VID0
14
0
VID
T
VOU
5
12
PR250
PR250 100K_0402_5%~
100K_0402_5%~
@
@
D
D
13
EN
BST
SW
SW
SW
SW
SW
E
TP
MOD
6
@
@
@
@
66.
66.
3
+VC
CSA_EN
12
11
10
9
8
7
25
D
D
PR251
PR251
5K_0402_1%~D
5K_0402_1%~D
12
GNDA_VCCSA
1.
05V_RUN
+
@
@
1 2
1 2
+VC
CSA_BT
+VC
CSA_PHASE
PR335
PR335
@
@
33K_0402_5%~
33K_0402_5%~
+V
CCSA_VID1
12
PR252
PR252
@
@
5K_0402_1%~D
5K_0402_1%~D
7.
7.
PR249
PR249 10K_0402_5%~
10K_0402_5%~
PR300
PR300 1K_0402_5%~
1K_0402_5%~
@
@
PR255
PR255
0_0402_5%~
0_0402_5%~
1 2
@
@ 1 2
0_0402_5%~
0_0402_5%~
PR245
PR245
2.
2.
2_0603_1%~D
2_0603_1%~D
1 2
12
D
D
D
D
D
D
D
D
PR254
PR254
D
D
+V
CCSA_BT_1
0.
0.
22U_0603_10V7K~D
22U_0603_10V7K~D
12
PC254
PC254
@
@
1000P_0603_50V7K~
1000P_0603_50V7K~
12
PR248
PR248
@
@
2.
2.
2_1206_1%~D
2_1206_1%~D
12
@
@
PR334
PR334
D
D
0_0402_5%~
0_0402_5%~
de-pop for BGA1023 0.85V
12
@
@
PR265
PR265
0_0402_5%~
0_0402_5%~
D
D
1.05V_VT
TPWRGD 43,52
CPU
_VTT_ON 42,52
PC253
PC253
1 2
0.42U
0.42U
H_ETQP4LR42AFM_17A_20%~D
H_ETQP4LR42AFM_17A_20%~D
D
D
PL18
PL18
H_V
CCSA_VID0 11
12
2
1
ϭϬϱsŽůƚнͲϱй dŚĞƌŵĂůĞƐŝŐŶƵƌƌĞŶƚϰϮ WĞĂĐŬĐƵƌƌĞŶƚϲ KWͺD/EϳϮ
CCSA_P
D
D
12
12
12
12
PC255
PC255
PC259
PC181
PC181
PC182
PC182
1 2
1 2
PC258
@
@
_0805_6.3V4Z~D
_0805_6.3V4Z~D
22U
22U
PC258
@
@
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
22U_0805_6.3V4Z~D
22U_0805_6.3V4Z~D
PR253
PR253
0_0402_5%~
0_0402_5%~
PR256
PR256
0_0402_5%~
0_0402_5%~
PC259
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
_1206_6.3V6M~D
22U
22U
22U
22U
PR267
PR267
12
100_0402_1%~
100_0402_1%~
D
D
12
12
D
D
+V
CCSA_SENSE 11
ND_VCC_SA 11
+G
PC257
PC257
PC256
PC256
2200P_0402_50V7K~
2200P_0402_50V7K~
D
D
12
PC260
PC260
_1206_6.3V6M~D
_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U
22U
+V
12
A A
PJP38
CSA_P
+VC
PJP38
1 2
PAD
PAD
-OPEN 4x4m
-OPEN 4x4m
5
+VCC_SA
GNDA_VCCSA
PJP37
PJP37
PAD
PAD
-OPEN1x1m
-OPEN1x1m
12
DELL CO
Titl
Titl
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
NFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
e
e
Co
L95870A 0.8V_VCC_SA
L95870A 0.8V_VCC_SA
L95870A 0.8V_VCC_SA
IS
IS
IS
LA-6611P
LA-6611P
LA-6611P
day, January 26, 2011
day, January 26, 2011
day, January 26, 2011
1
0.1
0.1
56 57Wednes
56 57Wednes
56 57Wednes
0.1
of
of
of
5
+V
CHGR
D
D
12
270
270
PC264
PC264
PR
PR
1 2
1U_0603_25V7K~D
1U_0603_25V7K~D
100K_0402_5%~
100K_0402_5%~
0.
0.
12
D
PR277
PR277
@
@
+V
CHGR
D
D
D
D
SLIC
E_BAT_ON42
ULT_OVRDE42
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
1 2
PR321
PR321
0_0402_5%~D
0_0402_5%~D
@
@
D
PR273
PR273
10K_0402_5%~
10K_0402_5%~
61
2
D
D
D
D
279
279 PR
PR
1 2
100K_0402_5%~
100K_0402_5%~
12
D
D
PR286
PR286
10K_0402_5%~
10K_0402_5%~
3
5
4
PD30
PD30
12
R
R
B751V-40_SOD323~D
B751V-40_SOD323~D
PD31
PD31
12
R
R
B751V-40_SOD323~D
B751V-40_SOD323~D
1 2
0_0402_5%~
0_0402_5%~
PQ57
PQ57
N338P_NL_SOT23-3~D
N338P_NL_SOT23-3~D
FD
FD
1
3
1
3
1 3
2
2
2
12
PC272
PC272 1500P_0402_7K~
1500P_0402_7K~
5
2N7002D
2N7002D
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
2N7002D
2N7002D
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
PR294
PR294
@
@
PC266
PC266
PQ42A
PQ42A
12
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
PQ49B
PQ49B
+3.3V_ALW2
D D
CHARG
E_MODULE_BATT42
1 2
0_0402_5%~
0_0402_5%~
C C
ARGE_PBATT42
CH
1 2
PR293
PR293
0_0402_5%~
0_0402_5%~
@
@
CHARG
E_EN
1 2
PR
PR
328
328
0_0402_5%~
0_0402_5%~
@
@
DEFA
B B
12
12
PD28
PD28
PD29
PD29
A A
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
E_BAT_PRES#,42, 47
SLIC
PQ39
PQ39
DY-T1-E3_SO8~D
DY-T1-E3_SO8~D
SI4835D
SI4835D
1 2 3 6
4
PQ44
PQ44
DY-T1-E3_SO8~D
DY-T1-E3_SO8~D
SI4835D
SI4835D
1 2 3 6
4
@
@
PR285
PR285
0_0402_5%~
0_0402_5%~
1 2
PBATT
D
D
12
PR290
PR290
200K_0402_1%~
200K_0402_1%~
61
2
12
D
D
D
D
PR288
PR288
@
@
499K_0402_1%~
499K_0402_1%~
+DC_IN
1 2
PR310
PR310
100K_0402_5%~D
ACA
V_DOCK_SRC#41
DOCK_SMB_ALERT# 41, 43,47
100K_0402_5%~D
DC_IN
+S
ACAV_IN22,43,55
3V_ALW2
+3.
D
D
8 7
5
8 7
5
2N7002D
2N7002D
3
PQ47B
PQ47B
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
5
4
D
D
PD24
PD24
1 2
+
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
2N7002D
2N7002D
PQ51A
PQ51A
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
PR298
PR298
@
@
0_0402_5%~
0_0402_5%~
1 2
PR307 47_0805_5%~DPR307 47_0805_5%~D
1U_0603_50V4Z~D
1U_0603_50V4Z~D
0.
0.
SO
FT_START_GC47
1 2
@
@
PR314
PR314
0_0402_5%~
0_0402_5%~
D
D
_BLOCK_GC55
DC
1 2
@
@
PR318
PR318
0_0402_5%~
0_0402_5%~
1 2
@
@
PR319
PR319
0_0402_5%~
0_0402_5%~
D
D
2N7002D
2N7002D
PQ47A
PQ47A
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
5
D
D
PBAT_
PC271
PC271
1 2
0_0402_5%~
0_0402_5%~
CD
D
D
PR297
PR297 20K_0402_1%~
20K_0402_1%~
1 2
61
1 2
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
2N7002D
2N7002D
3
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
4
1 2
PRES#42,47
@
@
PR312
PR312
3301_SDC_IN
2
PD22
PD22
PQ51B
PQ51B
+DOCK_PWR_BAR
12
ACA
D
D
PC273
PC273
1U_0603_25V7K~D
1U_0603_25V7K~D
0.
0.
SLIC
+DC_
+CHG
CD
VDK_SRC
12
D
D
2
PD25
PD25
E_BAT_PRES#41,42, 47
R_DC_IN55
3301_DCIN
ERC1
IN_SS
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
1 2
61
1 2
12
0_0402_5%~
0_0402_5%~
ACAVI P33ALW2
4
PR280
PR280 20K_0402_1%~
20K_0402_1%~
2N7002D
2N7002D
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
PQ48A
PQ48A
@
@
PR296
PR296
PR299
PR299
@
@
1 2
0_0402_5%~
0_0402_5%~
PU14
PU14
1 2 3 4 5 6 7
N
8 9
37
CSS
DK_C
4
D
D
PD26
PD26
1 2
B751V-40_SOD323~D
B751V-40_SOD323~D R
R
D
D
1 2
1 2
PR302
PR302
PR305
PR305
@
@
N
DC_I
C
SS_G ERC1
K_SRC
ACAVD GND SDC_
IN
_BLK_GC
DC ACAV_IN P33A
LW2
TP
_GC55
SS_GC55
PC274
PC274
047U_0603_25V7K~D
047U_0603_25V7K~D
0.
0.
2N7002D
2N7002D
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
PQ48B
PQ48B
2N7002D
2N7002D
PQ50B
PQ50B
W-T/R7_SOT363-6~D
W-T/R7_SOT363-6~D
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D
0_0402_5%~D
D
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12
3
4
1 2
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R
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4
PR472
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0_0402_5%~
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35
36
34
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GC
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5
1 2
0_0402_5%~
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5
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31
32
30
33
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16
15
14
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12
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12
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390K_0402_5%~
12
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12
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12
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28
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3
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4
12
D
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PR284
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620K_0402_5%~
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61
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61
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26
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PR324
PR324
1 2
@
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
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5
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DELL CONFIDENTIAL/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
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Title
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Titl
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Size Document Number Rev
Size Document Number Rev
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Date: Sheet
Date: Sheet
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6611P
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day, January 26, 2011
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1
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2
11,56 7/22/2010 Modify net name Change +0.8V_VCC_SA to +VCC_SA
HW
COMPAL
X01
Change capacitors from 10uF_0805_10V_Y5V to 10uF_0805_6.3V_X5R: C305,C316,C387,C1181, C705,C728,C760,C764, C765,C768,C769,C772,CC135,CH58,CH73,CH80
Change capacitors from 10uF_0805_6.3V to 10uF_0603_6.3V: C475,C638,C641,C643
X01
3
22,25,28 32,42,43 45,11,20 37,11,
HW
7/22/2010
COMPAL
Follow PPM recommendation to change material
Change resistors to 0402 size: RC134, RH201,RH253,RH208,RH213 Delete RH192 and add PJP52
4HW X01
5
C C
6
7
8
9HW X01
10 HW X01
18 7/22/2010 Follow Intel Design Guide Rev1.0 Change RH149 to 1k and RH150 to 4.7k
22 7/22/2010 Change MAX8731_IINP connection Change to VCP
22 7/22/2010 Per SMSC request Add R404 10K pull down of TEST1 pin
26 7/22/2010 For Safety request Add D4 and R5 co-lay with F2,
40 7/22/2010 Change ESATA repeater Add R1585~R1588, and change U44 to MAX4951BECTP
30 7/22/2010 Change codec to ZB version Change Codec part number to SA00003ZZ1L and stuff C962
HW
HW
HW X01
HW
HW11 X01
7/22/201014,29,43 Modify Module Bay circuit
34 7/22/2010 Change RFID capacitors for more popular Change C502,C505 from 1uF to 0.1uF
B B
24,46 7/22/2010 Correct net name for LED signal
COMPAL
COMPAL
COMPAL
COMPAL
SMSC
COMPAL
COMPAL
COMPAL
COMPALHW
COMPALHW
COMPALHW
De-pop RH36,RH283,RH21,RH24,CH1,CH6De-pop PCH XDP7/22/201014
Change net name ODD_DET# to PCH_SATA_MOD_EN#, r and USB_MCARD3_DET# to remove R1069,R1182,R1188,R425, Add R513,Q76,Q123B, change BAY SM bus PU rail to +3.3V_ALW
Modify signal name BREATH_BLUE_LED to BREATH_WHITE_LED and BREATH_BLUE_LED_SNIFF to BREATH_WHITE_LED_SNIFF
Add R1132 and add net name SUSACK#_ECAdd 0 ohm resistor for SUSACK#42 7/22/2010
X01
X01
X01
X0112
X0113
X0114
15
16
17 X01
18
19
A A
20
32 Remove useless resistors Remove R556, R558, R559, R560 and short it.7/22/2010
32,28,29 38,45
10 CC129~CC134 D2T LESR5M EOL Change CC129~CC134 to SGA00004X0L7/22/2010
37 Modify Module Bay circuit
7 7/22/2010 For support XDP device De-pop RC9
42 7/22/2010 Base on GPIO map to modify Change SLICE_BAT_PRES# pull up power rail from +3.3V_ALW2 to +3.3V_ALW
HW COMPAL
HW COMPAL
7/22/2010
HW COMPAL
HW COMPAL
INTELHW
Change part for Halogen free Change Q18,Q27,Q30,Q34,Q38,Q40,Q42,Q49,Q54,Q58 to HF part7/22/2010
COMPALHW
De-pop C627,R712
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
C
C
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mpal Electronics, Inc.
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Tit
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
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P.I.R 1
P.I.R 1
P.I.R 1
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Base on GPIO map to modify Add R889 for CPU1.5V_S3_GATE pull down
Remove RH238,RH172 and change connection form SLP_ME_CSW_DEV# from GPIO45 to GPIO28
1
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23 HW
24 PWM function Remove R1139,R1140 and add D68,D69, pop R1137
7/22/2010
COMPAL
X01
37,46 Modify LED circuit Remove R1578,R1579,R1580,D42,D60,D61, add Q77,Q124,R705,R718,R71924 HW X01COMPAL7/22/2010
25 15,32 EOL concern Change Y3 and YH2 from 1Y725000CE1A to 7A25000110HW
26
27 36 Add discharge circuit for +3.3V_RUN_CARD7/22/2010 Add R826 on +3.3V_RUN_CARD
C C
31,42,46 Remove mute function and LED Remove R1109,Q119,Q105,Q102,R1059,R1061
28
HW X01
HW X01
HW COMPAL
HW
17,18,43 To solve back drive issue
29
HW
30 HW X01
31 29,45 For cost saving Add PJP63,RH202, no stuff QH4,Q49,RH278,R908
32 42 Follow GPIO 0720
18 Add pull up for PCH GPIO1 Change RH254 to 10K and pull high to +3.3V_RUN
HW X01
HW X01
4333
B B
35 14
36 24,40 Change material for small size Change C300,C669 from 1206 16V to 0805 10V
7/22/2010 COMPAL X01
COMPAL
Change part for Halogen free part7/22/201024,27,46
Change QC5 to NTR4501NT1G, U21,U24,U54,U55,U57 change to NC7SZ04P5X-G, Q21 change to FDC654P-G
O2-Mirco
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
7/22/2010
COMPAL
COMPAL
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COMPALHW
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Follow GPIO 0720
Part leverage select Change D16,D59,D62 to SC100000S0L34 28,46
Remove USB_OC7# signal and RH254, change connection from PCH GPIO1 to GPIO14,and change RH164 pull up power rail from +3.3V_RUN to +3.3V_ALW_PCH
Add DYN_TUR_PWR_ALRT# up power rail and change R796 pull from +3.3V_RUN to +3.3V_ALW
Add DYN_TUR_CURRNT_SET# up power rail and change R837 pull from +3.3V_RUN to +3.3V_ALW
Change RH43,RH44,RH45 to 200 ohmFollow Intel XDP design guide
X01
X01
X01
X01
X01
X01
37
39,40 Remove useless capacitors Remove C1151~C1154
38 37 Add 0 ohm R on PCIE_MCARD2_DET# Add R725
HW COMPAL
HW COMPAL
39 43 Follow GPIO MAP 0720 Add R1578 for XFR.
42 Add 0 ohm for TEMP_ALERT# Add R77340
A A
42
4441 Solution +1.5V_RUN voltage drop issue Change Q59 from SI3456BDV to NTGS4141NT1GHW COMPAL7/22/2010
46 Add pull down 100k on BT_ACTIVE Add R9597/27/2010HW COMPAL
HW COMPAL
5
7/22/2010
7/22/2010
7/22/2010
7/22/2010
X01
X01
COMPALHW
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
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Tit
Tit
le
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
EE
EE
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P.I.R 2
P.I.R 2
P.I.R 2
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esday, Januar y 26, 2011
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45 7/27/2010 BID change Change R875 to 130K
45
46
47 7/28/2010 Remove RTC_DET# PAID. Remove RH31, add T132
48 7/28/2010 Follow connector list change FAN connector to SP02000TI00
C C
49 7/28/2010 Follow connector list Re-link RJ45 symbol
50 7/28/2010 Follow connector list Chnage keyboard connector to pitch 1
51
52
43
22 7/27/2010 Chnage thermal diode connection Remove C268
18,30 7/28/2010 Remove SPEAKER_DET# PAID.
14,47
22
33
44
34 7/28/2010 Remove Broadcom debug connector Remove JBRCM1 and add R666 no stuff
47 7/28/2010 Change RTC connector Change to TYCO_2-1775293-2
53 43 08/05/2010 Change signal net name Change 0.8V_VCCPWROK net name to VCCSAPWROK
54
HW
HW
HW X01COMPAL
HW X01
HW X01
HW COMPAL
HW X01
HW
HW X01
HW X01
HW X01
55
B B
56
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPALHW
COMPALHW
X01
X01
Chnage SPEAKER_DET# to GPIO17, and change speaker connector to SP02000H900
X01
X01
Change R1183~R1186 to L78~L81 pop C973~C976,C267,C283 and C28430 08/13/2010 Fix Speaker EMI issue
Fix USB EMI issue pop L50,L52,depop R737,R739,R734,R73508/13/201039,40
Chnage ODD repesater to MAX4951B and R1174,R1176,R1169,R1171 to 0 ohmChange ODD repeater 29 08/13/2010
X01
X01
57
58 22
62 08/16/2010 Crystal EA Change C743=39pF CH2,CH3=15pF CH18,CH19=10pF and YH2 to SJ100008E0L14 15 43
A A
43
HW
1459 08/13/2010 Change TAA topology redefine JP1 TAA pin define
10 08/16/201060
HW COMPAL
HW COMPAL
08/13/2010
08/13/2010 COMPAL
COMPALHW
EOL concern Change Y6 to SJ132P7KW1L same as YH1
Change FAN conn type for ME request change FAN connector to SP02000CB0L
Follow PPDG1.2 Vcore 2.2uf 0402
QTY from 55 to 35 pcs
COMPALHW
remove CC199,CC103,CC120,CC142,CC141,CC171,CC139,CC134,CC133,CC200
CC101,CC128,CC153,CC102,CC126,CC105 16pcs
depop 4 pcs CC152,CC121,CC127 and CC160
Change RH150 to 0 ohm RH149 to 2.2K ohm08/16/20101861 Follow INTEL DG DF_TVS pull high value
HW COMPAL
HW COMPAL
1464 08/17/2010 reserve Resistance and Cap for SPI EA Add CH107,CH108,R935
HW COMPAL
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
Add C286reserve cap for CPU remote diode08/17/20102263
X01
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
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Tit
Tit
Tit
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
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EE
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P.I.R 3
P.I.R 3
P.I.R 3
LA
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esday, Januar y 26, 2011
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68 42 HW 8/24/2010 RF noise pop R794 R795 to 10 ohm,C712 C713 to 10p
1469 8/25/2010 Improve SPI power path Always pop C745
70 36 8/25/2010 O2 recommend add cap for +PE_VDDH add C559 0.1uF C560 0.01uF
71 14 18 8/26/2010 Follow INTEL DPDG reserve RH31,RH355 for GPIO19/GPIO28
72 14 8/27/2010 COMPAL remove double reserve cap for BIT_CLK remove CH100
C C
73 16 8/27/2010 reserve ME_SUS_PWR_ACK pull down reserve RH145
HW
HW
HW X01
HW
HW X01
74 26 HW 8/27/2010 Follow INTEL HDMI DG remove R1164,R458,R1128-->20K add R1593 depop D65
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
75 11 HW 8/30/2010 COMPAL Change QC5 VGS to 20V part Change QC5 to SB00000HK0L
76 37 9/1/2010 Depop SIM card ESD diode Depop U40
HW
HW
78 24 HW
79 10/6/2010 Follow DG1.5 and schematic check list rev1 Add RH41,depop RC96 and RC97,change RH177 to 10K X0214,18
HW Intel
10/6/2010 AUO panel can't adjust brightness Change R1137 from 100k to 10k X02
COMPAL
COMPAL
COMPAL
80 IDT10/6/2010 To solve pop noise and detect issue Add U6,Q33,Q46,D70,D71,R425,R33,R38,R430,R352,R1088,C967,C307,C308,R161
B B
81 32,42 10/11/2010 LOM Cable Detect function
82
42 10/11/2010 COMPAL Change Board ID to X02 Change R875 to 62K X02
HW COMPAL
HW
Improve SPI EA for SPI_CLK 8/23/2010 Change R899 and R897 to 56 ohm66 14
Change Speaker CONN to SP021007221Follow connector list8/23/20103067
X01
X01
X01
X01
X01
X01
X01
X01
X01
Change RB751V to HF part10/6/201077 Change D63,D64,D68,D69 to SCS00004L0L24
X02
X02HW30,31 add U15, C478 change TP_DET# netname to WLAN_LAN_DISB# JTP1 pin1 change to GND
X02
83
84
46
24, 3085 10/19/2010 EMI EMI issue for PWM and DMIC_CLK Add L83,change R1582 to L82 X02
86 30 10/19/2010 Change Codec rev to YA Change U72 to SA00003ZZ2L X02
HW
HW
HW
COMPAL
COMPALHW
HW COMPAL
88 10/19/201039,40 PT ESD test result Change U91,U92 to D72,D73. Pop D73
A A
HW ESD
89 10/19/2010 Compal PT ESD test result remove D7,D8,DE1~DE4
Follow Intel check list rev1.210/11/2010
LED brightness test result
Add @RH332Intel17
X02
Change R957 to 560,R941,R939,R934 to 4.7k,R955,R949 to 2K X0210/11/2010
Change U31 to SA00003SI2LChange LAN stepping to C010/19/20103287 X02
X02
X02HW24
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
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Date: Sheet
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P.I.R 4
P.I.R 4
P.I.R 4
LA
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91 28 Support SSD hard drive Add PJP64,C399,C402
92 Non-support Latitude on depop SW2,C740,R877
93
94 HDMI SDVO CTRL PU same as 14" del D65,R1593
95
31,43
22 HW
26
30,42
96 10/26/2010
97 11/1/2010 COMPAL
C C
98 11/1/2010
99 HW
100 HW COMPAL
101
102
103 HW
104 X02
105 X02HW
B B
106
41 EMI dock clk issue pop R756=33ohm C704=12pf
18 Follow schmaitc check list depop RH174 RH175 X02
14 11/8/2010 For easy control TAA/nonTAA BOM Add R936 colay R895,R944 colay R897,R943 colay R900
15 11/8/2010 DF416400 AMT_Run MEflow Stress test fai depop RH296 RH297,pop QH5 RH302,RH303
25 11/10/2010 COMPAL Pericom VGA SW high EOS failure rate Change C321,C318 from 0.1uF to 0.01uF(pin4,pin23) X02
6-11,14-21 11/10/2010 COMPAL Change CPU PCH PN to QS sample X02Change UH4 PN to SA00004IW1L ,U1 PN to SA00004EL1L
46 11/10/2010 ME Change KB screw hole Change H12 H13 from 2.3 to 2.6 X02
22 11/10/2010 COMPAL Thermal request change OTP set to 94 degree Change R406 to 1.4k
28 11/18/2010 COMPAL Follow Intel CRB SMBUS PU value Change R501 R502 from 2.2k to 10k
HW
HW
HW
HW
HW X02
HW
HW
HW
HW
HW
HW
10/19/2010
10/19/2010
10/19/2010 Change OTP set to 91 degree Change R406 to 1.15k
10/20/2010
10/20/2010 GPIO map change AUD_NB_MUTE to AUD_NB_MUTE#
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
change AUD_NB_MUTE to AUD_NB_MUTE#
Follow Intel CRB FAB2 PCH XDP schematic14
Add @RH284
COMPAL
COMPAL
De-pop R499,R500,C393,Q28,R905,R907,C762,Q51For cost saving(+5V_HDD / +3.3V_ALW_PCH)COMPAL11/19/201028,45
X02
X02
X02
X02
X02
X02
X02
X02
X02
107
108
43
43109
34-35200
202
14 1/5/2011 For cost saving De-pop RH47,RH48,RH49,RH288
203 22 1/18/2011 Change R385 to 10KSame as 14 A00
A A
204
HW
HW
HW
HW COMPAL
HW COMPAL
HW COMPAL
12/23/2010 COMPAL SW WHQL request USB debug need USB port1 A00Change USB port0 to port117,39
12/27/2010
COMPAL12/27/2010
COMPALHW
Change Board ID to A00 Change R875 to 33k
To solve backdrive issue Pop Q45COMPAL
Change USH chip to CID7 Change U33 to SA00003AO2L12/27/2010
del U6,Q33,Q46,D70,D71,R425,R33,R38,R430,R352,R1088,C967,C307,C308,R1611/3/2011 remove MIC external detect30-31201
A00
A00
A00
A00
A00
A00Change R902 to 2.2KDF445509:TP will malfunction intermittently.COMPAL1/21/2011HW44
DELL CONFIDENTIAL/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Tit
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
EE
EE
EE
P.I.R 5
P.I.R 5
P.I.R 5
LA
LA
LA
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7
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Charger 7/15 Compal
+DCIN 8/4 Compal Follow Macallan 14
System can't recognize battery issue Change PU11 pin 15 connection from CHARGER_SMBCLK to CHARGER_SMBDAT
for new battery cell
3/5V 8/4 Compal Follow Macallan 14
+DCIN 8/4 Compal RTC remove detect function
+VCC_SA 8/4 Compal Follow Macallan 14
(7/29 EE mail)
VCCSA not fix at 0.8V. change net name from +0.8V_VCC_SA to +VCC_SA
Charger 8/4 Compal Follow Macallan 14
Selector 8/4 Compal Follow Macallan 14
Charger 8/4 Compal
Intel8/18VCCSA5611 Change VID settingIntel change BGA1023 VID table
Vcore, VGFX
8/18
Maxim12 53,54
Vcore, VGFX 8/1813
Leakage issue on PD16
Follow Macallan 14 Add adapter protection circuit for turbo mode
VID0 0 VID1 1 voltage from 0.8V to 0.85V
Reserve 0402 cap pad for transient fine tune
change setting for Pass2 sample
Change PU11 pin 16 connection from CHARGER_SMBDAT to CHARGER_SMBCLK
Change PL1 from SM01002078L to SM010009C8L and add PL20 Change PL19 from SM01002078L to SM010009C8L
Change PC24 from 4.7u/6.3V/0805 (SE093475K8L) to 4.7u/6.3V/0603 (SE107475K8L)
Delete JRTC1 pin2 RTC_DET# connection
Change +0.8V_VCC net name to +VCCSA_P Change 0.8V_VCCPWROK net name to VCCSAPWROK
Depop PD14 SBR3A40SA (SC100003J00)
Change PD16 from SBR3A40SA (SC100003J00) to ES2AA (SC100005A0L)
Add PU11 pin8 connection ICREF Add PU11 pin23 connection ICOUT Add PR259,PR260,PR261,PR295, PR331,PR332 Add PC279,PC280 Add PQ38
Add PC281 and PC282 0402 cap location
Change PR330 from 2_ohm to 0_ohm Change PR127 from 150K_ohm to 165K_ohm Change PR135 from 100K_ohm to 105K_ohm Change PR157 from 8.66K_ohm to 10.2K_ohm Change PR190 from 1.43K_ohm to 1.37K_ohm Change PR192 from 2_ohm to 0_ohm de-pop PR201 Change PR110 PR112 PR115 from 12.7K_ohm to 13.3K_ohm
Change PQ9 form CSD86350Q5D to PQ9 AON6414AL + PQ10 AON6704L
53,54 Compal
A A
17 55
Vcore, VGFX 8/1814
VCCSA 8/23
56 TI
VCCSA
8/2316
Charger 8/24 Dell
5
TI15 56 Change Thermal pad to PGND
Change PQ9 PQ10 PQ11 to prevent COS issue
For batter output voltage accuracy Add PC383 from PR247 pin2 to PU13 pin2
Add turbo mode adapter protection by H_PROCHOT#
4
Change PQ10 form CSD86350Q5D to PQ11 AON6414AL + PQ15 AON6704L Change PQ11 form CSD86350Q5D to PQ3 AON6414AL + PQ14 AON6704L
Change PU13 pin 25 from GNDA_VCCSA to PGND
Add PR336 PR337 for pop opton to select H_PROCHOT# or DYN_TUR_PWR_ALRT#
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19 47 +DCIN 9/1 Dell reduce leakage current
VCCSA 9/1
51 Compal 22u/1206/6.3V COS issue
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10/2021
22 1.05V_RUN_VTT 10/2052 Compal
23 10/20
C C
24 11/05
25 53 11/05
26 53,54
27 57
28 55
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55
29
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Vcore,VGFX 11/05 Maxim
Selector 11/10 Compal
Charger 11/10 Compal Change adapter protection circuit
Charger Pop PR336
11/10 Compal
Intel20 56 Intel update VCCSA voltage change only
for UL ULV type. our project is SV type hence keep no change
22u/1206/6.3V COS issue
TI
TI IC OCP setting value change (as PT memo) Change PR83 from SD03457628L 57.6K_ohm 0402 to SD03410028L 10K_ohm 0402
Maxim Initial voltage accurate53 Vcore
Maxim
Load line modify Transient compensation
Load line modify Transient compensation
Fine tune main and media battery switching to slice battery transient time (follow 14")
trip point. (Adapter rated current + 0.75A) (follow 14")
Change adapter protection event to HW from SW
Change PR2 PR108 from 10K_ohm to 100K_ohm
de-pop PR250 PR251 PR252 PR333 PR334 PR335 pop PR264 PR265 PR266 PR300
Change PC98~PC105 from 22u/1206 (SE077226M8L) to 22u/0805 (SE00000110L)
Change PC120~PC127 PC129 PC130 from 22u/1206 (SE077226M8L) to 22u/0805 (SE00000110L)
PR110 PR112 PR115 change from 13.3K_ohm to 12.7K_ohm PR109 change from 6.49K_ohm to 5.9K_ohm
PR140 change from 9.76K_ohm to 8.45K_ohm PC281 pop 10n
PR157 change form 10.2K_ohm to 7.5K_ohm PC282 pop 68nF
Change PC270 and PC265 from 1uF (SE00000698L) to 0.22uF (SE000005Z8L)
Change PR295 from 1.87M (SD00000WN0L) to 649K (SD03464938L) Change PR261 from 73.2K (SD00000B18L) to 95.3k (SD03495328L)
De-pop PR332 PR337
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Do
<Do
<Do
c> 0.3
C
c> 0.3
C
c> 0.3
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
of
of
64 64Wednesday, January 26, 2011
64 64Wednesday, January 26, 2011
64 64Wednesday, January 26, 2011
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