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LA-6611P PAL70
Schematic
65 pgs3.15 Mb0

Compal LA-6611P PAL70 Schematic

A
B
C
D
E
ϯD>>EϭϯΗhD
COMPAL CONFIDENTIAL
BGA Sandy Bridge +
PAL70
1 1
PCB NO :
BOM P/N :
O MAP Version 1010
GPI
MODEL NAM
E :
LA-6611P (DAA
43XXXXXXLXX
00001W10)
FCBGA PCH Cougar Point-M
2010-01-21
REV
: 1.0(A00)
Items R1 P/N R3 P/N

CPU 2.5G SA00004EL2L SA00004EL3L CPU 2.6G SA00004EM2L SA00004EM3L CPU 2.7G SA00004F02L SA00004F03L CPU 2.1G SA00004KP1L SA00004KP2L PCH SA00004IW2L SA00004IW3L LAN SA00003SI4L SA00003SI5L
   

USH SA00003AO1L SA00003AO2L
@ : Nopop Component
DdLJƉĞ
Ϯϱ'WhdWDEdD/^td
2 2
Ϯϱ'WhdWDEdD/^t^W/
Ϯϱ'WhdWD/^dDE
Ϯϱ'WhdWD/^dDEt^W/
Ϯϱ'WhdWD/^dD/^
Ϯϱ'WhdWD/^dD^/t^W/
Ϯϲ'WhdWDEdD/^td
Ϯϲ'WhdWDEdD/^t^W/
Ϯϲ'WhdWD/^dDE
3 3
Ϯϲ'WhdWD/^dDEt^W/
Ϯϲ'WhdWD/^dD/^
Ϯϲ'WhdWD/^dD^/t^W/
Ϯϳ'WhdWDEdD/^td
Ϯϳ'WhdWDEdD/^t^W/
Ϯϳ'WhdWD/^dDE
Ϯϳ'WhdWD/^dDEt^W/
Ϯϳ'WhdWD/^dD/^
4 4
Ϯϳ'WhdWD/^dD^/t^W/
KDWE
ϰϯϭϵϯϰϯϭ>Ϭϲ
ϰϯϭϵϯϰϯϭ>Ϭϯ
ϰϯϭϵϯϰϯϭ>ϭϱ
ϰϯϭϵϯϰϯϭ>Ϭϳ
ϰϯϭϵϯϰϯϭ>Ϭϰ
ϰϯϭϵϯϰϯϭ>ϭϲ
ϰϯϭϵϯϰϯϭ>Ϭϴ
ϰϯϭϵϯϰϯϭ>Ϭϱ
ϰϯϭϵϯϰϯϭ>ϭϳ
ϭΛ ϮΛ
*
*
*
*
*
*
ϯΛ ϰΛ
*
*
*
*
*
*
*
*
*
*
*
*
**
**
*
*
**
**
*
*
**
**
*
*
dWD dD
tŝƚŚ^W/
ϱΛ
*
*
*
*
*
*
*
*
*
tŝƚŚd
ϲΛ
*
*
*
*
*
*
*
*
*
MB PC
MB PC
B
B
Part Number Description
Part Number Description
DAA00001W00
DAA00001W00
PCB PAL70 LA6611
PCB PAL70 LA6611
DELL CONFIDENTIAL/PROPRIETA
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
Comp
Comp
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Comp
Cover
Cover
Cover
LA-6611P
LA-6611P
LA-6611P
nesday, January 26, 2011
nesday, January 26, 2011
nesday, January 26, 2011
Sheet
Sheet
Sheet
164Wed
164Wed
164Wed
E
RY
of
of
of
Block Diagram
A
Compal confidential
B
Model: PAL70
C
D
E
Memory BUS (DDR3)
1066/1333MH
1 1
Sandy B
idge
r
z
DDRIII-DIMM X2
BA
NK 0, 1, 2, 3, 4 ,5 ,6 ,7
page 12~13
LVDS CONN
page 24
CRT CONN
/K
VGA
2 2
3 3
DOCKING
RT
PO
page 41
DAI
USB
SATA
LAN
DOCK
ni Card
EXPRESS
Card
page 38 page 37page 37page 37
USB
CPU ITP Por
PCH ITP Por
1/2 Mi
page 7
page 14
Flas
USB
t
t
PCIE
h
Thermal
GUARDIAN III EMC4022
4 4
WiFi ON/OFF
DC/DC Inte
Powe SW & LED
page 45
r On/Off
page 46
page 22
/K
rface
A
For MB/Dock Video Switch PI3V712-AZLE
page 25
HDMI CONN
page 26
C
SDX
page 36 page 36
PCIE
ni Card
1/2 Mi
Smart
RFID
FAN
page 22
WLA
USB
Card
page 34
page 34
N
Card reader
OZ600FJ0LN
PCI Exp
PCIEPCIE
ini Card
Full M
TD
Fingerprint CONN
WWAN
USB
A8034HN
page 34
page 23
/UWB
SMSC SIO
E5028
EC
page 42
ress BUS
Optio
FP_USB
BC BUS
B
LVDS
VGA
DPB
DP
C
DPD
PCIE x1
n
CB
SSX35B
page 35
TPM1
M5882
page 34~35
USB
.2
USH
BC
SMSC KBC
ME
C5055
page 43
page 44 page 44
KB CONNTP CONN
4MB (Socket
BGA CPU
1023 pins
COUGAR POIN
LPC BUSChina TPM1.2
FDI
x 8
Lane
INTEL
BGA
SP
I
G1)
page 6~11
DMI
x 4
Lane
USB
T-M
page 14~21
HD Audio I/F
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
page 14
ector
E
page 14
ector
PCIE
E
TA Repeater
SA
MAX4951BECTP+
Module
E-
page 29
page 29
W25X64Z
64M 4K s
W25X16Z
16M 4K s
C
SATA
PCI Exp
BT
Camera
SATA Repeater MAX4951BECTP+
ress BUS
HDD
page 28
D
page 44
page 24
page 14
HDA Codec 92H
D
Troug
h LVDS Cable
E-SATA
USB
page 40
B
US
page 39
l Lewisville
Inte
DOCK LAN
T.Speaker
IN
page 30
82579LM
LAN PI3L720
90B2
page 30
HeadPhone &
Tr
MIC Jack
/K
DAI
To Dock
ing side
Dig. MIC
Trough LVDS Cable
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
UMA Block
UMA Block
UMA Block
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
Diagram
Diagram
Diagram
E
page 32
SWITCH
page 32
ansformer
page 33
RJ4
5
page 33
/PROPRIETARY
264We
264We
264We
of
of
of
5
4
3
2
1
State
ATES
Signal
SLP
SLP
SLP
#
S4#
S3
HIGH
HIGH
W HIGH HIGH HIGH ON ON ON OFF
LO
LOW
LOW HIGH HIGHLOW
LOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
S4
S5#
STATE#
HIGH HIGH
HIG
H
SLP M#
HIG
HIGH
H
ALWAYS PLANE
ON
M PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
USB PORT#
0
1
2
3
4
5
6
7
DESTINA
T
ION
JUSB1 (Ext Right Side)
none
Right Side (ESA
TA)
none
WLAN/WIMAX
WWAN/UWB
Flash
USH->BIO
POWER ST
S0 (
Full ON) / M0
D D
S3 (Suspend to RAM) / M1
S4 (Suspend to DISK) / M1 ON ON OFF
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
(Suspend to RAM) / M-OFF
S3
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
DOCKING8
PM T
ABLE
C C
pow plane
State
S0
S3
S5 S4/AC
S4/AC don't exist
S5
B B
SATA
TA 0
SA
SATA
1
SATA 2
SATA 3
4
A A
SATA
SATA 5
+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
r
e
+3.3V_RTC_LDO
ON
ON
DESTINAT
HDD
ODD/ E3 Module Bay
NA
NA
ESATA
k
Doc
5
V_SUS
+3.3
+1.5V_MEM
ON ON
ON
OFF
OFFOFF
ION
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
OFF
OFF
4
+3.3
+1.
V_M
05V_M
ON
ON
ON
V_M
+3.3
+1.05V_M
(M-OFF)
ON
OFF
OFF
OFFOFF
Stack up
Thickness
Layer
SolderMask
Add Plating
Top/L1(signal)
Prepreg
Core
L3(IN1)
Prepreg
L4(IN2)
Core
L5(GND2)
Prepreg
L6(IN3)
Core
L7(IN4)
Prepreg
L8(VCC)
Core
L9(IN5)
Prepreg
L10(IN6) 0.5oz 0.65
Core 3mil 3.09
L11(GND3) 0.5oz
Prepreg
Bottom/L12(signal)
Add Plating
SolderMask
Overall Thickness
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
(Material SPEC.) Unit : mil
min 0.4
1.30
0.5oz(0.68)
1080LRC
0.5oz
3mil
0.5oz
1080LRC+1080
1oz
3mil
1oz
1080HRC
0.5oz
6mil
0.5oz
1080HRC
1oz
3mil
1oz
1080LRC+1080
1080LRC 2.65
0.5oz(0.68)
1.30
min 0.4
1.36mm+/-10%
3
Thickness (Actuality) Unit : mil
0.50
1.05
0.65
2.65
0.65
3.09
0.65
5.1
1.35
3.09
1.35
2.90
0.65
6
0.65
2.90
1.35
3.09
1.35
5.1
0.65
0.65
1.05
0.50
53.36
USH
2
9
DOCKING
10 Express car
11
12
13
Bluetooth
Cam
none
0
1
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 N
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
d
era
BIO
NA
DESTINAT
MI
NI CARD-1 WWAN
MI
NI CARD-2 WLAN
Express car
ION
d
E3 Module Bay (USB3)
1/
2vMINI CARD-3 PCIE
MMI
10/100/1G LOM
one
/PROPRIETARY
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
and Config.
and Config.
and Config.
Index
Index
Index
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
1
364We
364We
364We
of
of
of
5
+V_DDR_REF
ADAPTER
D D
+0.75V_DDR_VT
4
TPS51206
(PU5
)
T
3
N
HDDC_E
2
ODD_MOD
SI
3456BDVSI3456BDV
(Q
30)@(Q27)
SN1003055
(PU7
)
S
M3K7002F
S
@(QH4)
1
+1
.05V_RU
N_VTT
SI
4164DY
(Q63)
AO
V_CPU_VDDQ
+1.5
+PWR_SRC
BAT
TERY
V_RUN
+1.5
CHARG
ER
C C
V_RUN
+1.8
4728L
(QC3)
NTGS4144
(Q
59)
1.5V_R
UN_ENABLE
ALWON
TPS51311
(PU4
+3.
3V_SUS
3456BDV
SI
(Q
MA
X17511
)
(PU9
B B
VP_VR_ON IM
+VCC_CORE
+V
CC_GFXCORE
IS
L95870A
U13)
(P
VTT_ON
CPU_
+0.
8V_VCC_SA
FDC654P
(Q21)
NVPWR
EN_I
+BL_
PWR_SRC
_WOWL
AUX_EN
SI
3456BDV
(Q38)
WWAN_PWREN
MCARD_
SI
3456BDV
(Q40)
5V_MEM
+1.
)
54)
MC
ARD_PCIE_BKT_PWREN
+1.
RUN_O
05V_M
SUS_ON
S13456
(
Q42)
N
+5V_HDD
MAX17020
)
(PU2
3V_ALW
+3.
AUX_ON
SI
3456
(Q34) (Q55)
+5V_
MOD
SN1003055
(PU3
SN1003055
(PU6
PCH
_ALW_ON
RUN_ON
NTM
)
)
S4920
PJP6
SI
3456BDV
(Q
49)
3
A_ON
SI
3456BDV
58)
(Q
+5V_
+15V
ALW
_ALW
+3.
3V_ALW_PCH
SI
ALW_ENABLE
+5V_
RUN_O
EN_LCDPWR
3456BDV
18)
(Q
ALW_PCH
N
05V_RUN
+1.
4164DY
SI
(Q50)
+5V_RUN
3V_WLAN
+3.
A A
5
4
+3.3
+3.
Pop option
V_RUN
3V_PCIE_WWAN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3V_PCIE_FLASH
+3.
3
+3.
3V_LAN
+3.3
V_RUN
2
+3.3V_M
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+LCDVDD
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Power
Power
Power
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
Rail
Rail
Rail
1
464We
464We
464We
of
of
of
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBC LK
MEM_
SMBDATA
PCH
D D
N_SMBCLK
2.2K
B4
A3
B5
A4
LA
LAN_SMBDATA
2.2K
DOCK_
SMB_CLK
DOCK_SMB_DAT
_SMBCLK
LCD
LCD_SMDATA
+3.3V_ALW_PCH
C8
G12
M16E14
SM
L1_SMBDATA
SM
L1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
2N7002
2N7002
SMBUS Address [C8]
DDR_X
DDR_XDP_WAN_SMBDAT
2.2K
2.2K
+3.3V_ALW
127
129
DOCKING
2.2K
2.2K
+LCD_VDD
Keep pull up only for PWM LCD
3
DP_WAN_SMBCLK
SMBUS Address
APR_EC: 0x48 SPR_EC: 0x70 MSLICE_EC: 0x72 USB: 0x59 AUDIO: 0x34 SLICE_BATTERY: 0x17 SLICE_CHARGER: 0x13
202
200
202
200
2
MMA
DI
DI
MMB
30
32
WWAN
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
1
2.2K
G Se
+3.3V_RUN
nsor
SMBUS Address [TBD]
2.2K
14
13
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
7
6
M9
L9
7
8
10
9
31
32
8
9
ERY
BATT CONN
USH
x
press card
E
ger
Char
Module Bay
E3
A/D,
D/A
converter
SMBUS Address [0x16]
SMBUS Address [0xa4]
SMBUS Address [TBD]
SMBUS Address [0x12]
SMBUS Address [0xd2]
SMBUS Address [0x30]
3
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Co
US TOPOLOGY
US TOPOLOGY
US TOPOLOGY
SMB
SMB
SMB
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
564We
564We
564We
1
of
of
of
KBC
A56
1C1CB59
PBA
T_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
1E
B53
B B
C 5055
ME
1E
A49
2B
B52
2B
SMBCLK
USH_
USH_S
MBDAT
CARD_S
MBCLK
CARD_SMBDAT
2.2K
2.2K
2.2K
B50
1G
A47
1G
R_SMBCLK
CHARGE
CHARGER_SMBDAT
2.2K
2.2K
B7
_SMBDAT
A7
BAY
BAY_SMBCLK
2D
A A
2D
2.2K
2.2K
B49
B48
DAI_SMBCLK
DAI_SMBDAT
2A
2A
5
2.2K
5
;ϭͿW'ͺZKDWK;'ϰͿƵƐĞϰŵŝůĐŽŶŶĞĐƚƚŽW'ͺ/KDW/ƚŚĞŶƵƐĞϰŵŝůĐŽŶŶĞĐƚƚŽZϮ ;ϮͿW'ͺ/KDWKƵƐĞϭϮŵŝůĐŽŶŶĞĐƚƚŽZϮ
U1A
U1A
_CRX_PTX_N0
DMI
_CRX_PTX_N016 _CRX_PTX_N116
DMI DMI
_CRX_PTX_N216 _CRX_PTX_N316
D D
C C
B B
DMI
DMI
_CRX_PTX_P016 _CRX_PTX_P116
DMI
I
_CRX_PTX_P216
DM
_CRX_PTX_P316
DMI
_CTX_PRX_N016
DMI DMI
_CTX_PRX_N116
DMI
_CTX_PRX_N216 _CTX_PRX_N316
DMI
_CTX_PRX_P016
DMI DMI
_CTX_PRX_P116 _CTX_PRX_P216
DMI DMI
_CTX_PRX_P316
FDI_
CTX_PRX_N016 CTX_PRX_N116
FDI_ FDI_
CTX_PRX_N216 CTX_PRX_N316
FDI_ FDI_
CTX_PRX_N416
FDI_
CTX_PRX_N516
FDI_
CTX_PRX_N616
FDI_
CTX_PRX_N716
CTX_PRX_P016
FDI_ FDI_
CTX_PRX_P116 CTX_PRX_P216
FDI_ FDI_
CTX_PRX_P316
FDI_
CTX_PRX_P416 CTX_PRX_P516
FDI_ FDI_
CTX_PRX_P616 CTX_PRX_P716
FDI_
_FSYNC016
FDI FDI
_FSYNC116
I_INT16
FD
_LSYNC016
FDI FDI
_LSYNC116
;ϭͿWͺKDW/KƵƐĞϰŵŝůƚƌĂĐĞƚŽZϭ ;ϮͿWͺ/KDWKƵƐĞϭϮŵŝůƚŽZϭ
DMI
_CRX_PTX_N1
DMI DMI
_CRX_PTX_N2
DMI
_CRX_PTX_N3
DMI
_CRX_PTX_P0 _CRX_PTX_P1
DMI DMI
_CRX_PTX_P2
I
_CRX_PTX_P3
DM
DMI
_CTX_PRX_N0 _CTX_PRX_N1
DMI DMI
_CTX_PRX_N2 _CTX_PRX_N3
DMI
DMI
_CTX_PRX_P0 _CTX_PRX_P1
DMI DMI
_CTX_PRX_P2 _CTX_PRX_P3
DMI
CTX_PRX_N0
FDI_ FDI_
CTX_PRX_N1 CTX_PRX_N2
FDI_ FDI_
CTX_PRX_N3 CTX_PRX_N4
FDI_ FDI_
CTX_PRX_N5
FDI_
CTX_PRX_N6 CTX_PRX_N7
FDI_
FDI_
CTX_PRX_P0 CTX_PRX_P1
FDI_ FDI_
CTX_PRX_P2 CTX_PRX_P3
FDI_ FDI_
CTX_PRX_P4
FDI_
CTX_PRX_P5 CTX_PRX_P6
FDI_ FDI_
CTX_PRX_P7
FDI
_FSYNC0 _FSYNC1
FDI
FD
I_INT
FDI
_LSYNC0 _LSYNC1
FDI
EDP_CO
MP
W11
AC9
W10
AC8
AA11 AC12
AA10
AG8
AD2
AG11
AG4
AC3 AC4
AE11
AC1
AE10
M2
DMI
_RX#[0]
P6
_RX#[1]
DMI
P1
DMI
_RX#[2]
P10
I
_RX#[3]
DM
N3
DMI
_RX[0]
P7
_RX[1]
DMI
P3
DMI
_RX[2]
P11
_RX[3]
DMI
K1
DMI
_TX#[0]
M8
DMI
_TX#[1]
N4
DMI
_TX#[2]
R2
_TX#[3]
DMI
K3
DM
I_TX[0]
M7
DM
I_TX[1]
P4
I_TX[2]
DM
T3
I_TX[3]
DM
U7
I0_TX#[0]
FD FD
I0_TX#[1]
W1
I0_TX#[2]
FD
AA6
I0_TX#[3]
FD
W6
I1_TX#[0]
FD
V4
FD
I1_TX#[1]
Y2
I1_TX#[2]
FD
I1_TX#[3]
FD
U6
FDI
0_TX[0] 0_TX[1]
FDI
W3
FDI
0_TX[2]
AA7
0_TX[3]
FDI
W7
FDI
1_TX[0]
T4
1_TX[1]
FDI
AA3
1_TX[2]
FDI FDI
1_TX[3]
FDI
0_FSYNC 1_FSYNC
FDI
U11
FD
I_INT
0_LSYNC
FDI
1_LSYNC
FDI
AF3
eDP
_COMP IO
e
P_ICOMPO
D
_HPD
eDP
eD
P_AUX#
AF4
P_AUX
eD
eDP
_TX#[0 ]
eDP
_TX#[1 ] _TX#[2 ]
eDP
AE7
eDP
_TX#[3 ]
eDP
_TX[0]
AA4
_TX[1]
eDP eDP
_TX[2]
AE6
eDP
_TX[3]
SANDY
SANDY
4
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
PEG PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
ICOMPI
ICOMPO
RCOMPO
_
RX#[0] RX#[1] RX#[2] RX#[3] RX#[4] RX#[5] RX#[6] RX#[7] RX#[8]
RX#[9] RX#[10] RX#[11] RX#[12] RX#[13] RX#[14] RX#[15]
RX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8]
RX[9] RX[10] RX[11] RX[12] RX[13] RX[14] RX[15]
TX#[0] TX#[1] TX#[2] TX#[3] TX#[4] TX#[5] TX#[6] TX#[7] TX#[8] TX#[9]
TX#[10] TX#[11] TX#[12] TX#[13] TX#[14] TX#[15]
TX[0]
_
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9] TX[10] TX[11] TX[12] TX[13] TX[14] TX[15]
G3 G1 G4
H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7
K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6
G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4
F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4
PEG_
PEG_
PEG_
DMI Intel(R) FDI DP
DMI Intel(R) FDI DP
PEG_ PEG_ PEG_ PEG_ PEG_ PEG_
PEG_ PEG_ PEG_
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_ PEG_ PEG_
PEG_
COMP
3
2
U1I
U1I
BG
17
VSS[181]
21
BG
VSS[182]
BG
24
VSS[183]
BG
28
184]
VSS[
37
BG
VSS[185]
BG
41
VSS[186]
45
BG
VSS[187]
BG
49
VSS[188]
53
BG
VSS[189]
9
BG
VSS[190]
C2
9
VSS[191]
C3
5
VSS[192]
C4
0
VSS[193]
0
D1
VSS[194]
4
D1
VSS[195]
D1
8
VSS[196]
D2
2
VSS[197]
6
D2
VSS[198]
9
D2
VSS[199]
D3
5
VSS[200]
D4
VSS[201]
D4
0
VSS[202]
3
D4
VSS[203]
6
D4
VSS[204]
D5
0
VSS[205]
4
D5
VSS[206]
8
D5
VSS[207]
D6
VSS[208]
E2
5
VSS[209]
9
E2
VSS[210]
E3
VSS[211]
5
E3
VSS[212]
0
E4
VSS[213]
F13
VSS[214]
F15
VSS[215]
F19
VSS[216]
F29
VSS[217]
F35
VSS[218]
F40
VSS[219]
F55
VSS[220]
G4
8
VSS[221]
1
G5
VSS[222]
G6
VSS[223]
1
G6
VSS[224]
H1
0
VSS[225]
H1
4
VSS[226]
H1
7
VSS[227]
1
H2
VSS[228]
H4
VSS[229]
H5
3
VSS[230]
8
H5
VSS[231]
J1
VSS[232]
J49
VSS[233]
J55
VSS[234]
1
K1
VSS[
235]
1
K2
VSS[236]
1
K5
VSS[237]
K8
VSS[238]
L16
VSS[239]
L20
VSS[240]
L22
VSS[241]
L26
VSS[242]
L30
VSS[243]
L34
VSS[244]
L38
VSS[245]
L43
VSS[246]
L48
VSS[247]
L61
VSS[248]
1
M1
VSS[249]
M1
5
VSS[250]
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
VSS
VSS
VSS[2 VSS[2 VSS[2 VSS[ VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[2 VSS[3 VSS[3
VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_
VSS_NCTF_
NCTF
NCTF
VSS_NCTF_ VSS_NCTF_ VSS_NCTF_ VSS_NCTF_
1
M4
51]
M58
52]
M6
53]
N1
2
54]
N17
55]
N21
56]
N25
57]
N28
58]
N33
59]
N36
60]
N40
61]
N43
62]
N47
63]
N48
64]
N51
65]
N52
66]
N56
67]
N61
68]
P14
69]
P16
70]
P18
71]
P21
72]
P58
73]
P59
74]
P9
75]
R17
76]
R20
77]
R4
78]
R46
79]
T1
80]
T47
81]
T50
82]
T51
83]
T52
84]
T53
85]
T55
86]
T56
87]
U13
88]
U8
89]
V20
90]
V61
91]
W13
92]
W15
93]
W18
94]
W21
95]
W46
96]
W8
97]
Y4
98]
Y47
99]
Y58
00]
Y59
01]
A5
1
A57
2
BC61
3
BD3
4
BD59
5
BE4
6
BE58
7
BG5
8
BG57
9
C3
10
C58
11
D59
12
E1
13
E61
14
WŽŵƉĞŶƐĂƚŝŽŶ
.05V_RUN_VTT
+1
12
RC1
RC1
~D
~D
24.9_0402_1%
24.9_0402_1%
MP
EDP_CO
A A
ĞWͺKDW/KĂŶĚ/KDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƐŚŽƌƚĞĚŶĞĂƌďĂůůƐĂŶĚ ƌŽƵƚĞĚǁŝƚŚƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞфϮϱŵŽŚŵƐ
5
4
W'ŽŵƉĞŶƐĂƚŝŽŶ
+1
.05V_RUN_VTT
12
RC2
RC2
24.9_0402_1%
24.9_0402_1%
~D
~D
PEG_
COMP
W'ͺ/KDW/ĂŶĚZKDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƐŚŽƌƚĞĚĂŶĚƌŽƵƚĞĚ ǁŝƚŚͲŵĂdžůĞŶŐƚŚсϱϬϬŵŝůƐͲƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞсϰϯŵŽŚŵƐ W'ͺ/KDWKƐŝŐŶĂůƐƐŚŽƵůĚďĞƌŽƵƚĞĚǁŝƚŚͲŵĂdžůĞŶŐƚŚсϱϬϬŵŝůƐ ͲƚLJƉŝĐĂůŝŵƉĞĚĂŶĐĞсϭϰϱŵŽŚŵƐ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (1/6)
ndy Bridge (1/6)
ndy Bridge (1/6)
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
664W edn
664W edn
664W edn
of
of
1
of
5
+1
OK_AND
F49
C57
C49
A48
C45
D45
C48
B46
BE45
D44
12
2
G
G
U1B
U1B
PROC
PROC
CATE
PECI
PROCHO
THERMT
SYNC
PM_
UNCOREPW
SM_
DRAMPWROK
RESET#
75_0402_1%
75_0402_1%
RC4
RC4
~
~ D
D
1 2
RC10
RC10
43_0402_5%
43_0402_5%
.5V_CPU_VDDQ
RC64
RC64
39_0402_5%
39_0402_5%
1 2 13
D
D
QC1
QC1
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
S
S
S
S
_SELECT#
_DETECT#
RR#
T#
RIP#
RGOOD
PCH_PL
~D
~D
&ŽůůŽǁ'ZĞǀϬϳϭ^DͺZDWtZK<ƚŽƉŽůŽŐLJ
D D
+3
.3V_ALW_PCH
.05V_RUN_VTT
+1
1 2
RC
1 2
RC
1 2
RC
RC
C C
H_PRO
HERMTRIP#22
H_T
B B
H_CPUPW
RUNPWR
1 2
18 200_0402_5%~D
18 200_0402_5%~D
RC
RC
_
DRAM_PWRGD16
PM
126 56_0402_5%~D@RC126 56_0402_5%~D@
128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@
44 62_0402_5%~D
44 62_0402_5%~D
CHOT#43,53,55
RGD18
H_T
H_CAT
H_PRO
H_PM
ƵĨĨĞƌĞĚƌĞƐĞƚƚŽWh
A A
PCH_PL
TRST#14,17
5
+3
.3V_ALW_PCH
5
OK42,43
HERMTRIP#
CPU_DET
ƉůĂĐĞZϭϮϵŶĞĂƌWh
RC
RC
1
B
2
A
3
N_CPU1.5VS3#11,45
RUN_O
ERR#
CHOT#
EDS 1.0 SNB_IVB# -> PROC_SELECT#
ECT#42
H_CAT
H_PECI18
H_PRO
1 2
RC
RC
57 56_0402_5%~D
57 56_0402_5%~D
ůŽƐĞƚŽhϭ
RC
RC
129 0_0402_5%~D
129 0_0402_5%~D
_SYNC16
1 2
25 0_0402_5%~D
25 0_0402_5%~D
+3
1
2
H_
1 2
H_PM
VC
CPWRGOOD _0_R
DRAM_PWRGD_CPU
PM_
TRST#_R
PCH_PL
.3V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC14
CC14
0
0
2
5
P
NC
PCH_PL
4
Y
A
G
UC1
UC1
3
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
CC
CC
156
156
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
P
RUNPWR
4
O
G
UC2
UC2
C1G09GW_TSSOP5~D
C1G09GW_TSSOP5~D
74AH
74AH
ERR#
CHOT#_R
HERMTRIP#_R
T
_SYNC
+1
TRST#_BUF
.05V_RUN_VTT
4
200_0402_5%
200_0402_5%
12
RC12
RC12
~D
~D
1 2
RC
RC
28 130_0402_5%~D
28 130_0402_5%~D
~D
~D
SANDY
SANDY
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
TRST#_R
0_0402_5%
0_0402_5%
12
@
@
RC11
RC11
~D
~D
4
DRAM_PWRGD_CPU
PM_
DP
LL_REF_CLK
LL_REF_CLK#
DP
BC
DRAMRST#
SM_
SM_ SM_ SM_
BCLK
BCLK
LK_ITP
BC
LK_ITP#
RCOMP[0] RCOMP[1] RCOMP[2]
PRDY# PREQ#
TCK TMS
TRST#
TDO
DBR#
BP
M#[0] M#[1]
BP BP
M#[2] M#[3]
BP BP
M#[4] M#[5]
BP BP
M#[6]
BP
M#[7]
#
TDI
MISC THERMAL
MISC THERMAL
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
ǀŽŝĚƐƚƵďŝŶƚŚĞWtZ'ƉĂƚŚǁŚŝůĞƉůĂĐŝŶŐƌĞƐŝƐƚŽƌƐZϮϱΘZϭϯϬ
CPU_DM
J3 H2
AG3 AG1
N59 N58
AT30
BF44 BE43 BG43
N5 N5
L56 L55 J58
M6 L59
K58
G58 E55 E59 G55 G59 H60 J59 J61
VC
I I#
CPU_DM
CPU_DPL
L
CPU_DPL
L#
XDP_ITP
CLK_ CLK_
XDP_ITP#
DRAMRST#_CPU
DDR3_
SM_
RCOMP0 RCOMP1
SM_ SM_
RCOMP2
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XDP_PRDY
3
XDP_PREQ
5
XDP_TCL XDP_TM XDP_TRST#
XDP_TDI
0
XDP_TDO
XDP_DBRESET#
CPWRGOOD _0_R
3
+3
.3V_ALW_PCH
12
RC
124
@RC124
@
1K_0402_5%~D
1K_0402_5%~D
PWROK_XDP
SYS_
+1
.05V_RUN_VTT
1
2
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CC65
CC65
2
WůĂĐĞŶĞĂƌ:yWϭ
H_CPUPW
RGD
_PWRBTN#_R14,16
SIO
09
CFG
PWROK16,42
SYS_
XDP#17
PLTRST_
dŚĞƌĞƐŝƐƚŽƌĨŽƌ,KK<ϮƐŚŽƵůĚďĞƉůĂĐĞĚ ƐƵĐŚƚŚĂƚƚŚĞƐƚƵďŝƐǀĞƌLJƐŵĂůůŽŶ&'ϬŶĞƚ
1 2
13 0_0402_5%~D
13 0_0402_5%~D
RC
RC
1 2
RC
RC
15 0_0402_5%~D
15 0_0402_5%~D
1 2
16 0_0402_5%~D
16 0_0402_5%~D
RC
RC
1 2
RC
RC
17 0_0402_5%~D
17 0_0402_5%~D
DĂdžϱϬϬŵŝůƐ
#
#
K
S
_R
_R
_R
RC
RC
T128 P
T128 P T131 P
T131 P T129 P
T129 P T130 P
T130 P T125 P
T125 P T126 PAD~D@ T126 PAD~D@ T107 P
T107 P T127 PAD~D@ T127 PAD~D@
12
130
130
RC
RC 10K_0402_5%~D
10K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
26 0_0402_5%~D
26 0_0402_5%~D
AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
3
CPU_DMI 15
CLK_ CLK_
CPU_DMI# 15
CLK_
CPU_DPLL 15 CPU_DPLL# 15
CLK_
4.
4. 99K_0402_1%~D
99K_0402_1%~D
DDR_HVREF
DDR_HVREF
XDP_DBRESET#
RC50
RC50
12
_RST_PCH15
_RST_GATE43
XDP_DBRESET#
RCOMP2
SM_ SM_RCOMP1 SM_
RCOMP0
1 2
RC
48 0_0402_5%~D@RC48 0_0402_5%~D@
S
S
G
G
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
CC
CC
1
177
177
2
RC
RC
RC
D
D
13
QC2
QC2
SS138W-7-F_SOT323-3~D
SS138W-7-F_SOT323-3~D
B
B
46 0_0402_5%~D
46 0_0402_5%~D
47 0_0402_5%~D@RC47 0_0402_5%~D@
1 2
1 2
14,16
XDP_TDO
140_0402_1%
140_0402_1%
12
~D
~D
RC
RC
5 1K_0402_5%~D
5 1K_0402_5%~D 6 0_0402_5%~D
6 0_0402_5%~D
RC
RC RC
RC
7 1K_0402_5%~D
7 1K_0402_5%~D 9 0_0402_5%~D@RC9 0_0402_5%~D@
RC
8 1K_0402_5%~D
8 1K_0402_5%~D
RC
RC
DDR_HVREF
_R
1 2
23 0_0402_5%~D
23 0_0402_5%~D
RC
RC
_R
1 2
RC
RC
24 0_0402_5%~D
24 0_0402_5%~D
25.
25. 5_0402_1%~D
5_0402_1%~D
12
RC43
RC43
RC42
RC42
2
1 2 1 2 1 2 1 2
1 2
DDR3_
DRAMRST# 12
_RST
200_0402_1%
200_0402_1%
12
RC45
RC45
~D
~D
1
+1
.05V_RUN_VTT
#
CLK_ CLK_
CLK_
CLK_
XDP XDP#
XDP_ITP
XDP_ITP#
XDP_PREQ XDP_PRDY
#
H_CPUPW
RGD_XDP
PWRBTN#_XDP
CFD_ XDP_HO
OK2
PWROK_XDP
SYS_
XDP
CLK_ CLK_
XDP#
XDP_RST#
_R
XDP_DBRESET#
XDP_TDO XDP_TRST# XDP_TDI
S
XDP_TM
XDP_TCL
K
RH
109 0_0402_5%~D@RH109 0_0402_5%~D@
108 0_0402_5%~D@RH108 0_0402_5%~D@
RH
1 2
1 2
RH10
RH10
12
RH10
RH10
12
1
OBSFN_
2
OBSFN_
3
D
GN
4
OBSDATA_
5
OBSDATA_
6
GND
7
OBSDATA_
8
OBSDATA_
9
GND
10
HOOK
0
11
HOOK
1
12
HOOK
2
13
3
HOOK
14
4
HOOK
15
HOOK
5
16
VCCOBS_
17
6
HOOK
18
7
HOOK
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
MOLEX_52435-2671
70_0402_5%~D
70_0402_5%~D 60_0402_5%~D
60_0402_5%~D
WhWĨŽƌ:d'ƐŝŐŶĂůƐ
XDP_TDIXDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_TM
XDP_TDI
XDP_PREQ
XDP_TDO
XDP_TCL
XDP_TRST#
RC
RC
S
RC27 51_0402_1%~DRC27 51_0402_1%~D
_R
RC29 51_0402_1%~DRC29 51_0402_1%~D
#
RC
RC
RC
K
RC40
RC40
RC41
RC41
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (2/6)
ndy Bridge (2/6)
ndy Bridge (2/6)
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
12
19 1K_0402_5%~D
19 1K_0402_5%~D
32 51_0402_1%~D@RC32 51_0402_1%~D@
35 51_0402_1%~D
35 51_0402_1%~D
12
12
12
12
12
51_0402_1%
51_0402_1%
12
51_0402_1%
51_0402_1%
+1
/PROPRIETARY
-6611P
-6611P
-6611P
1
P1
@
P1
@
JXD
JXD
A0 A1
A[0] A[1]
A[2] A[3]
AB
27 28
GND
CLK_ CLK_
.3V_RUN
+3
.05V_RUN_VTT
~D
~D
~D
~D
764W edn
764W edn
764W edn
of
of
of
CPU_ITP 15 CPU_ITP# 15
5
U1C
D D
C C
B B
DDR_A_
D[0..63]12
BS012
DDR_A_ DDR_A_
BS112
DDR_A_
BS212
DDR_A_
CAS#12 RAS#12
DDR_A_ DDR_A_WE#12
DDR_A_ DDR_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_
A_
A_
BS0 BS1 BS2
CAS# RAS# WE#
U1C
D0
AG6
SA_DQ
AJ10
AT13
AY13
AY17
AT48 AY48
AY53
AT54
BF36
AT41
AJ6
AL6
AJ8 AL8 AL7
AP6 AU6 AV9 AR6 AP8
BC7 BB7
BA7 BA9 BB9
9
[0] [1]
SA_DQ
[2]
SA_DQ SA_DQ
[3]
SA_DQ
[4]
SA_DQ
[5] [6]
SA_DQ
[7]
SA_DQ SA_DQ
[8]
SA_DQ
[9] [10]
SA_DQ
[11]
SA_DQ SA_DQ
[12] [13]
SA_DQ SA_DQ
[14] [15]
SA_DQ
[16]
SA_DQ SA_DQ
[17] [18]
SA_DQ
[19]
SA_DQ
[20]
SA_DQ SA_DQ
[21] [22]
SA_DQ
[23]
SA_DQ
[24]
SA_DQ
[25]
SA_DQ SA_DQ
[26] [27]
SA_DQ SA_DQ
[28] [29]
SA_DQ SA_DQ
[30] [31]
SA_DQ
[32]
SA_DQ SA_DQ
[33] [34]
SA_DQ SA_DQ
[35] [36]
SA_DQ SA_DQ
[37]
SA_DQ
[38]
SA_DQ
[39] [40]
SA_DQ
[41]
SA_DQ SA_DQ
[42] [43]
SA_DQ SA_DQ
[44] [45]
SA_DQ SA_DQ
[46]
SA_
[47]
DQ
[48]
SA_DQ
[49]
SA_DQ
[50]
SA_DQ SA_DQ
[51] [52]
SA_DQ SA_DQ
[53] [54]
SA_DQ SA_DQ
[55]
SA_DQ
[56] [57]
SA_DQ SA_DQ
[58] [59]
SA_DQ SA_DQ
[60] [61]
SA_DQ SA_DQ
[62]
SA_DQ
[63]
0]
SA_BS[ SA_BS[
1] 2]
SA_BS[
SA_CAS# SA_RAS# SA_W
E#
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
SANDY
SANDY
D1 D2
AP11
D3 D4 D5 D6 D7 D8
AR11
D9 D10 D11 D12 D13 D14 D15
AU13
D16 D17 D18
BA13
D19
BB11
D20 D21 D22 D23 D24
AV14
D25
AR14
D26 D27
AR19
D28
BA14
D29
AU14
D30
BB14
D31
BB17
D32
BA45
D33
AR43
D34
AW48
D35
BC48
D36
BC45
D37
AR45
D38 D39 D40
BA49
D41
AV49
D42
BB51
D43 D44
BB49
D45
AU49
D46
BA53
D47
BB55
D48
BA55
D49
AV56
D50
AP50
D51
AP53
D52
AV54
D53 D54
AP56
D55
AP52
D56
AN57
D57
AN53
D58
AG56
D59
AG53
D60
AN55
D61
AN52
D62
AG55
D63
AK56
BD37
BA28
BE3
BD39
4
_
CLK_DDR0
M
AU36
K[0]
SA_CL
K#[0]
SA_CL
SA_CKE[
0]
SA_CL
K[1]
K#[1]
SA_CL
1]
SA_CKE[
SA_CS#
[0] [1]
SA_CS#
DT[0]
SA_O
DT[1]
SA_O
S#[0]
SA_DQ
S#[1]
SA_DQ SA_DQ
S#[2] S#[3]
SA_DQ SA_DQ
S#[4] S#[5]
SA_DQ SA_DQ
S#[6]
SA_DQ
S#[7]
S[0]
SA_DQ SA_DQ
S[1]
SA_
S[2]
DQ
S[3]
SA_DQ
S[4]
SA_DQ
S[5]
SA_DQ SA_DQ
S[6] S[7]
SA_DQ
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
A[0]
SA_M SA_M
A[1]
SA_M
A[2]
SA_M
A[3]
SA_M
A[4] A[5]
SA_M SA_M
A[6] A[7]
SA_M SA_M
A[8] A[9]
SA_M
SA_M
A[10] A[11]
SA_M SA_M
A[12]
SA_M
A[13] SA_MA[14] SA_M
A[15]
AV36 AY26
AT40 AU40 BB26
BB40 BC41
AY40 BA41
AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55
AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54
BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26
CLK_DDR#0
M_ DDR_CKE0
CLK_DDR1
M_ M_
CLK_DDR#1
DDR_CKE1
DDR_CS0 DDR_CS1
DT0
M_O
DT1
M_O
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_
A_ DDR_A_ DDR_A_ DDR_A_
DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_A_
_DIMMA
_DIMMA
_DIMMA# _DIMMA#
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15
CLK_DDR0 12
M_ M_
CLK_DDR#0 12
CKE0
DDR_
M_
CLK_DDR1 12 CLK_DDR#1 12
M_ DDR_CKE1
DDR_CS0 DDR_CS1
DT0 12
M_O M_O
DT1 12
DDR_A_
DDR_A_
DDR_A_
_DIMMA 12
_DIMMA 12
_DIMMA# 12 _DIMMA# 12
DQS#[0..7] 12
DQS[0..7] 12
MA[0..15] 12
3
DDR_B_
D[0..63]13
DDR_B_
BS013 BS113
DDR_B_ DDR_B_
BS213
CAS#13
DDR_B_ DDR_B_
RAS#13 WE#13
DDR_B_
DDR_B_ DDR_B_ DDR_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_
D0
AL4
D1
AL1
B_
D2
AN3
D3
AR4
D4
AK4
D5
AK3
D6
AN4
D7
AR1
D8
AU4
D9
AT2
D10
AV4
D11
BA4
D12
AU3
D13
AR3
D14
AY2
D15
BA3
D16
BE9
D17
BD9
D18
BD13
D19
BF12
D20
BF8
D21
BD10
D22
BD14
D23
BE13
D24
BF16
D25
BE17
D26
BE18
D27
BE21
D28
BE14
D29
BG14
D30
BG18
D31
BF19
D32
BD50
D33
BF48
D34
BD53
D35
BF52
D36
BD49
D37
BE49
D38
BD54
D39
BE53
D40
BF56
D41
BE57
D42
BC59
D43
AY60
D44
BE54
D45
BG54
D46
BA58
D47
AW59
D48
AW58
D49
AU58
D50
B_
AN61
D51
AN59
D52
AU59
D53
AU61
D54
AN58
D55
AR58
D56
AK58
D57
AL58
D58
AG58
D59
AG59
D60
AM60
D61
AL59
D62
AF61
D63
AH60
BS0
BG39
BS1
BD42
BS2
AT22
CAS#
AV4
3
RAS#
BF4
0
WE#
BD45
2
D
D
U1
U1
[0]
SB_DQ SB_DQ
[1] [2]
SB_DQ
[3]
SB_DQ SB_DQ
[4]
SB_DQ
[5]
SB_DQ
[6] [7]
SB_DQ
[8]
SB_DQ SB_DQ
[9]
SB_DQ
[10] [11]
SB_DQ
[12]
SB_DQ SB_DQ
[13] [14]
SB_DQ SB_DQ
[15] [16]
SB_DQ
[17]
SB_DQ SB_DQ
[18] [19]
SB_DQ
[20]
SB_DQ
[21]
SB_DQ SB_DQ
[22] [23]
SB_DQ
[24]
SB_DQ
[25]
SB_DQ
[26]
SB_DQ SB_DQ
[27] [28]
SB_DQ SB_DQ
[29] [30]
SB_DQ SB_DQ
[31] [32]
SB_DQ
[33]
SB_DQ SB_DQ
[34] [35]
SB_DQ SB_DQ
[36] [37]
SB_DQ SB_DQ
[38]
SB_DQ
[39]
SB_DQ
[40] [41]
SB_DQ
[42]
SB_DQ SB_DQ
[43] [44]
SB_DQ SB_DQ
[45] [46]
SB_DQ SB_DQ
[47]
SB_
[48]
DQ
[49]
SB_DQ
[50]
SB_DQ
[51]
SB_DQ SB_DQ
[52] [53]
SB_DQ SB_DQ
[54] [55]
SB_DQ SB_DQ
[56]
SB_DQ
[57] [58]
SB_DQ SB_DQ
[59] [60]
SB_DQ SB_DQ
[61] [62]
SB_DQ SB_DQ
[63]
SB_BS[
0] 1]
SB_BS[ SB_BS[
2]
SB_CAS# SB_RAS# SB_WE#
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
M_
CLK_DDR2
BA34
SB_CL
K[0]
K#[0]
SB_CL
SB_CKE[
SB_CL
K[1]
SB_CL
K#[1]
SB_CKE[
_CS#[0]
SB SB
_CS#[1]
DT[0]
SB_O
DT[1]
SB_O
SB_DQ
S#[0] S#[1]
SB_DQ
S#[2]
SB_DQ SB_DQ
S#[3] S#[4]
SB_DQ SB_DQ
S#[5] S#[6]
SB_DQ SB_DQ
S#[7]
S[0]
SB_DQ SB_DQ
S[1]
SB_
S[2]
DQ
S[3]
SB_DQ
S[4]
SB_DQ
S[5]
SB_DQ SB_DQ
S[6] S[7]
SB_DQ
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_M
A[0] A[1]
SB_M SB_M
A[2]
SB_M
A[3]
SB_M
A[4]
SB_M
A[5] A[6]
SB_M SB_M
A[7] A[8]
SB_M SB_M
A[9]
A[10]
SB_M SB_M
A[11] A[12]
SB_M SB_M
A[13]
SB_M
A[14]
SB_MA[15]
_
CLK_DDR#2
M
AY34 AR22
0]
BA36 BB36 BF27
1]
BE41 BE47
AT43 BG47
AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59
AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61
BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22
DDR_CKE2
M_
CLK_DDR3 CLK_DDR#3
M_ DDR_CKE3
DDR_CS2 DDR_CS3
DT2
M_O
DT3
M_O
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_
B_ DDR_B_ DDR_B_ DDR_B_
DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_ DDR_B_
_DIMMB
_DIMMB
_DIMMB# _DIMMB#
DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15
1
_
CLK_DDR2 13
M
CLK_DDR#2 13
M_ DDR_CKE2
CLK_DDR3 13
M_ M_
CLK_DDR#3 13
DDR_CKE3
DDR_CS2 DDR_CS3
M_O
DT2 13 DT3 13
M_O
DDR_B_
DDR_B_
DDR_B_
_DIMMB 13
_DIMMB 13
_DIMMB# 13 _DIMMB# 13
DQS#[0..7] 13
DQS[0..7] 13
MA[0..15] 13
A A
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
ndy Bridge (3/6)
ndy Bridge (3/6)
ndy Bridge (3/6)
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
864W edn
864W edn
864W edn
of
of
1
of
5
4
3
2
1
&'^ƚƌĂƉƐĨŽƌWƌŽĐĞƐƐŽƌ
CFG
2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
U1E
U1E
CFG
07
CFG
T11
T11
PAD~D@
PAD~D@
T13
T13
PAD~D@
PAD~D@
T17
T17
PAD~D@
PAD~D@ PAD~D@
PAD~D@
T18
T18 T15
T15
PAD~D@
+V
CC_CORE
H_CPU_
H_CPU_
H_CPU_
H_CPU_
+D
12
+D
12
RSVD3
RSVD1
RSVD2
RSVD4
IMM0_1_VREF_CPU
IMM0_1_CA_CPU
EDS 1.0 RSVD_12 -> VCC_DIE_SENSE
1 2
120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
C C
B B
CC_GFXCORE
+V
RC
RC
RC
RC
RC
RC
1 2
122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
1 2
121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
1 2
123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
96 1K_0402_5%~D@RC96 1K_0402_5%~D@
97 1K_0402_5%~D@RC97 1K_0402_5%~D@
T19
T19 T9 PAD~
T9 PAD~ T10
T10 T12
T12 T14
T14 T21
T21 T20
T20
MM0_1_VREF_CPU
+DI
+DI
MM0_1_CA_CPU
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
T22PAD~D @T22PAD~D @
T25PAD~D @T25PAD~D @ T26PAD~D @T26PAD~D @ T27PAD~D @T27PAD~D @ T28PAD~D @T28PAD~D @ T29PAD~D @T29PAD~D @ T30PAD~D @T30PAD~D @ T31PAD~D @T31PAD~D @ T32PAD~D @T32PAD~D @ T33PAD~D @T33PAD~D @ T34PAD~D @T34PAD~D @ T35PAD~D @T35PAD~D @ T36PAD~D @T36PAD~D @ T37PAD~D @T37PAD~D @ T38PAD~D @T38PAD~D @ T39PAD~D @T39PAD~D @ T40PAD~D @T40PAD~D @ T41PAD~D @T41PAD~D @ T42PAD~D @T42PAD~D @ T43PAD~D @T43PAD~D @ T44PAD~D @T44PAD~D @
D@
D@
H_CPU_ H_CPU_
H_CPU_ H_CPU_
0
CFG
1 2
CFG
3
CFG CFG
4 5
CFG CFG
6 7
CFG CFG
8
CFG
9 10
CFG
11
CFG
12
CFG CFG
13 14
CFG CFG
15 16
CFG CFG
17
RSVD3 RSVD4
RSVD1 RSVD2
CC_DIESENSE
TP_V
+D
IMM0_1_VREF_CPU IMM0_1_CA_CPU
+D
PU_RSVD8
TP_C TP_
PU_RSVD9
C
PU_RSVD10
TP_C TP_C
PU_RSVD11 PU_RSVD12
TP_C
PU_RSVD13
TP_C
PU_RSVD14
TP_C TP_C
PU_RSVD15
TP_C
PU_RSVD16 PU_RSVD17
TP_C
PU_RSVD18
TP_C
PU_RSVD19
TP_C TP_C
PU_RSVD20 PU_RSVD21
TP_C
PU_RSVD22
TP_C TP_C
PU_RSVD23
TP_C
PU_RSVD24
TP_C
PU_RSVD25 PU_RSVD26
TP_C
PU_RSVD27
TP_C
BA19 AV19
AT2 BB2 BB1
AY BA2
AY AU1 AU2 BD2 BD2 BD2 BD2 BG BE2 BG BE2
BF2 BE2
B50
[0]
CFG
C51
CFG
[1]
B54
[2]
CFG
D53
[3]
CFG
A51
CFG
[4]
C53
[5]
CFG
C55
[6]
CFG
H49
[7]
CFG
A55
CFG
[8]
H51
[9]
CFG
K49
[10]
CFG
K53
[11]
CFG
F53
[12]
CFG
G53
CFG
[13]
L51
[14]
CFG
F51
CFG
[15]
D52
[16]
CFG
L53
CFG
[17]
H43
VCC_VAL
1 1 9
21
2
22
9 1 1 2 5 6
22
2
26
6 3 4
VSS_VAL
VAXG_ VSSAXG_
VCC_DI
RSVD6 RSVD7
RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
_SENSE
_SENSE
VAL_SENSE
VAL_SENSE
E_SENSE
RESERVED
RESERVED
K43
H45 K45
F48
H48 K48
DC_T DC_ DC_T DC_T
_TEST_A58
DC DC
_TEST_A59
_TEST_C59
DC DC
_TEST_A61
_TEST_C61
DC DC
_TEST_D61
DC_T
EST_BD61 DC_TEST_ DC_TEST_
EST_BG61
DC_T DC_T
EST_BG59
EST_BG58
DC_T
DC_T DC_T DC_TEST_ DC_T DC_TEST_ DC_T
RSVD28 RSVD29
RSVD30 RSVD31 RSVD32 RSVD33
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38
RSVD39 RSVD40
RSVD41 RSVD42 RSVD43 RSVD44
RSVD45
EST_A4 EST_C4
T
EST_D3 EST_D1
BE61 BE59
EST_BG4 EST_BG3
EST_BG1
EST_BD1
TP_C
PU_RSVD28
BE7
TP_C
PU_RSVD29
BG
7
TP_C
PU_RSVD30
N4
2
PU_RSVD31
TP_C
L42
TP_C
PU_RSVD32
L45
PU_RSVD33
TP_C
L47
PU_RSVD34
TP_C
3
M1
PU_RSVD35
TP_C
4
M1
PU_RSVD36
TP_C
4
U1
TP_C
PU_RSVD37
W1
4
PU_RSVD38
TP_C
3
P1
TP_C
PU_RSVD39
AT4
9
TP_C
PU_RSVD40
4
K2
PU_RSVD41
TP_C
AH2
TP_C
PU_RSVD42
AG
13
PU_RSVD43
TP_C
14
AM
TP_C
PU_RSVD44
AM
15
TP_C
PU_RSVD45
0
N5
TP
_DC_TEST_A4
A4 C4
_TEST_C4_D3
DC
D3
T
_DC_TEST_D1
P
D1
C_TEST_A58
TP_D
A58 A59
_TEST_A59_C59
DC
C59 A61
_TEST_A61_C61
DC
C61
TP_D
C_TEST_D61
D61
TP
_DC_TEST_BD61
BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3
BE3
BG1 BE1
BE1
BD1
BE59_BE61
DC_TEST_
DC
_TEST_BG59_BG61
_DC_TEST_BG58
TP
_DC_TEST_BG4
TP
DC_TEST_
BE3_BG3
BE1_BG1
DC_TEST_
_DC_TEST_BD1
TP
T45
T45 T46
T46
T47
T47 T48
T48 T49
T49 T50
T50
T51
T51 T52
T52 T53
T53 T55
T55 T109 P
T109 P
T110 P
T110 P T111 P
T111 P
T112 P
T112 P T113 P
T113 P T114 P
T114 P T115 P
T115 P
T116 P
T116 P
T117 P
T117 P
T118 P
T118 P T119 P
T119 P
T120 P
T120 P T121 P
T121 P
T122 P
T122 P T123 P
T123 P
T124 P
T124 P
PAD~D@
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@ PAD~D@
PAD~D@
AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@ AD~D@
AD~D@
AD~D@
AD~D@
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
definition matches socket pin map definition 0:Lane Reversed
CFG
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is connected to the Embedded Display Port
CFG
CFG
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
@
@
1K
1K
12
RC51
RC51
_0402_1%~D
_0402_1%~D
4
1K
1K
12
@
@
_0402_1%~D
_0402_1%~D
RC52
RC52
6
5
1K_0402_1%~D
1K_0402_1%~D
1K
1K
12
12
@RC54
@
@
@
_0402_1%~D
_0402_1%~D
RC54
RC53
RC53
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
SANDY
SANDY
CFG
7
@
@
1K
1K
12
RC56
RC56
_0402_1%~D
_0402_1%~D
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
Sa
Sa
Sa
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
ndy Bridge (4/6)
ndy Bridge (4/6)
ndy Bridge (4/6)
964We
964We
964We
1
of
of
of
5
CC_CORE
+V
D D
C C
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC67
CC67
CC75
CC75
1
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC94
CC94
CC
CC
1
104
104
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
122
122
124
124
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
148
148
151
151
2
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC
CC
CC76
CC76
1
1
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
1
2
1
123
123
2
2
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC95
CC95
CC96
CC96
1
1
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
127
127
125
125
2
@
@
CC
CC
1
152
152
2
@
@
2.
2.
2.
2.
2.
2.
2.
2.
2.
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC87
CC87
CC77
CC77
1
2
2.
2.
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC97
CC97
CC
CC
1
100
100
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
1
143
143
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
154
154
157
157
2
2U_0402_6.3V6M~D
CC71
CC71
CC72
CC72
1
1
2
2
2.
2.
2.
2.
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC98
CC98
CC99
CC99
1
1
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
C
C
1
C
C 201
201
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
1
155
155
160
160
2
2
@
@
2.
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC8
CC8
CC73
CC73
1
1
1
8
8
2
2
2
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
C
C
CC
CC
1
1
C
C 121
121
198
198
2
2
@
@
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC
C
C
1
1
C
C
158
158
159
159
2
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
111
111
110
B B
110
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
115
115
116
116
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
C
C C
C 112
112
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
C
C C
C 117
117
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC 113
113
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC 118
118
2
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
114
114
181
181
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
CC
CC
119
119
186
186
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC
C
C C
C
183
183
182
182
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
C
C
CC
CC
C
C 187
187
189
189
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
1
CC
CC
CC
CC
185
185
184
184
2
1
CC
CC 188
188
2
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC
CC 190
190
2
2
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1
+
+
9
9
CC12
CC12 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
A A
1
+
+
CC13
CC13 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
0
0
1
+
+
131
131
CC
CC 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
1
+
+
CC13
CC13 470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
2
2
4
U1F
CC_CORE
+V
U1F
53A
A26
]
VCC[1
A29
VCC[2
]
A31
3
]
VCC[
A34
]
VCC[4
A35
VCC[5
]
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
2.
2. 2U_0402_6.3V6M~D
2U_0402_6.3V6M~D
CC74
CC74
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC
CC
CC
CC
194
194
192
192
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC19
CC19
1
CC
CC
7
7
193
193
2
2.2U_0402_6.3V6M~D
CC
CC
CC
CC
1
1
1
106
106
191
191
2
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC19
CC19
1
5
5
2
A38
2.2U_0402_6.3V6M~D
2.2U_0402_6.3V6M~D
CC
CC 196
196
]
VCC[6
A39
VCC[7
]
A42
]
VCC[8
C26
]
VCC[9
C27
VCC[1
0]
C32
VCC[1
1]
C34
VCC[1
2]
C37
3]
VCC[1
C39
4]
VCC[1
C42
VCC[1
5]
D27
VCC[1
6]
D32
7]
VCC[1
D34
8]
VCC[1
D37
VCC[1
9]
D39
0]
VCC[2
D42
VCC[2
1]
E26
2]
VCC[2
E28
3]
VCC[2
E32
VCC[2
4]
E34
5]
VCC[2
E37
6]
VCC[2
E38
7]
VCC[2
F25
VCC[2
8]
F26
9]
VCC[2
F28
0]
VCC[3
F32
1]
VCC[3
F34
2]
VCC[3
F37
VCC[3
3]
F38
4]
VCC[3
F42
VCC[3
5]
G42
6]
VCC[3
H25
VCC[3
7]
H26
8]
VCC[3
H28
9]
VCC[3
H29
VCC[4
0]
H32
1]
VCC[4
H34
VCC[4
2]
H35
3]
VCC[4
H37
VCC[4
4]
H38
VCC[4
5]
H40
VCC[4
6]
J25
7]
VCC[4
J26
8]
VCC[4
J28
VCC[4
9]
J29
0]
VCC[5
J32
VCC[5
1]
J34
2]
VCC[5
J35
VCC[5
3]
J37
VCC[
4]
5
J38
5]
VCC[5
J40
6]
VCC[5
J42
7]
VCC[5
K26
VCC[5
8]
K27
9]
VCC[5
K29
VCC[6
0]
K32
1]
VCC[6
K34
VCC[6
2]
K35
VCC[6
3]
K37
4]
VCC[6
K39
VCC[6
6]
K42
7]
VCC[6
L25
VCC[6
8]
L28
9]
VCC[6
L33
VCC[7
0]
L36
VCC[7
1]
L40
VCC[7
2]
N26
VCC[7
3]
N30
4]
VCC[7
N34
VCC[7
5]
N38
6]
VCC[7
CORE SUPPLY
CORE SUPPLY
3
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO
PEG AND DDRSENSE LINES SVID QUIET RAILS
PEG AND DDRSENSE LINES SVID QUIET RAILS
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
POWER
POWER
VCCIO
VCCPQE VCCPQE
VIDALERT#
VCC_SENSE VSS_SENSE
VCCIO_SENSE
VSS_SENSE_
VCCIO VCCIO VCCIO VCCIO VCCIO
O
VCCI VCCIO VCCIO
VCCIO VCCIO
_SEL
VIDSCL VIDSOUT
VCCIO
2
8.5A
AF46
[1]
AG48
[3]
AG50
[4]
AG51
[5]
AJ17
[6]
AJ21
[7]
AJ25
[8]
AJ43
[9]
AJ47
[10]
AK50
[11]
AK51
[12]
AL14
[13]
AL15
[14]
AL16
[15]
AL20
[16]
AL22
[17]
AL26
[18]
AL45
[19]
AL48
[20]
AM16
[21]
AM17
[22]
AM21
[23]
AM43
[24]
AM47
[25]
AN20
[26]
AN42
[27]
AN45
[28]
AN48
[29]
AA14
[30]
AA15
[31]
AB17
[32]
AB20
[33]
AC13
[34]
AD16
[35]
AD18
[36]
AD21
[37]
AE14
[38]
AE15
[39]
AF16
[40]
AF18
[41]
AF20
[42]
AG15
[43]
AG16
[44]
AG17
[45]
AG20
[46]
AG21
[47]
AJ14
[48]
AJ15
[49]
+1
.05V_RUN_VTT_F
W16
50
W17
51
BC22
1
2
1
2
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC69
CC69
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC 243
243
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 244
244
0_0402_5%
0_0402_5%
1
2
1
2
1
2
RC65
RC65
CC79
CC79
CC238
CC238
CC245
CC245
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U
1U
1U
1U
1U
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
RC62
RC62
0_0402_5%
0_0402_5%
12
~D
~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC80
CC80
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC 233
233
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 246
246
12
~D
~D
.05V_RUN_VTT
+1
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC81
CC81
CC82
CC82
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
234
234
236
236
2
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC228
CC228
1
1
247
247
2
2
H_CPU_
.05V_RUN_VTT
+1
1U
1U
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
CC83
CC83
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
237
237
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
229
229
2
EŽƚĞWůĂĐĞƚŚĞWhƌĞƐŝƐƚŽƌƐĐůŽƐĞƚŽWh ZϭϱϱϱĐůŽƐĞƚŽWhϯϬϬͲϭϱϬϬŵŝůƐ
SVIDALRT#
+3
.3V_ALW_PCH
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC84
CC84
CC85
CC85
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC227
CC227
1
1
109
109
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
230
230
231
231
2
2
1 2
61 43_0402_5%~D
61 43_0402_5%~D
RC
RC
12
RC69
RC69 10K
10K
_0402_5%~D
_0402_5%~D
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC86
CC86
CC70
CC70
1
1
2
CC
CC
1
226
226
2
CC
CC
1
232
232
2
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC93
CC93
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
239
239
2
EŽƚĞWůĂĐĞƚŚĞWh ƌĞƐŝƐƚŽƌƐĐůŽƐĞƚŽWh ZϭϱϱϴĐůŽƐĞƚŽWhϯϬϬͲϭϱϬϬŵŝůƐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC23
CC23
5
5
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC78
CC78
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC
CC
+
+
107
107
2
Voltage Rail
VCC
AM25
[1]
AN22
[2]
A44 B43
K
C44
VCCSENSE_R
F43
VSSSENSE_R
3
G4
VTT_SENSE_
AN16
VSSIO
AN17
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC
CC 573
573
2
H_CPU_
SVIDALRT#
K
VIDSCL VIDSOUT
RC
RC RC
RC
R
RC
RC
132 0_0402_5%~D
132 0_0402_5%~D
_SENSE_R
1 2
RC133 0_0402_5%~DRC133 0_0402_5%~D
1 2
.05V_RUN_VTT
+1
12
VIDSCLK 53
WůĂĐĞZϲϲĂŶĚZϳϬŶĞĂƌWh
67 0_0402_5%~D
67 0_0402_5%~D
1 2
68 0_0402_5%~D
68 0_0402_5%~D
1 2
RC63
RC63 130_0402_1%
130_0402_1%
VTT_SENSE VTT_GN
D 52
~D
~D
+V
52
VIDSO
CC_CORE
12
12
UT 53
RC66
RC66 100_0402_1%~D
100_0402_1%~D
VCCSENSE 53
VSSSENSE 5
RC70
RC70 100_0402_1%~D
100_0402_1%~D
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM 1.5
Description
*
3
5A to Mem controller(+1.5V_CPU_VDDQ) 5-6A to 2 DIMMs/channel 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
1
.05V_RUN_VTT
+1
1U
1U
1U
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC90
CC90
1
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
RC60
RC60 75_0402_1%
75_0402_1%
CC91
CC91
1
2
Voltage
1U _0402_6.3V6K~D
_0402_6.3V6K~D
~D
~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CC92
CC92
1
2
VI
DALERT_N 53
S0 Iccmax Current (A)
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CC89
CC89
1
2
1
CC
CC
+
+
108
108
2
+1
.05V_RUN_VTT
12
CPU Power Rail Table
0.65-1.3
1.05
0.0-1.1
1.8
1.5
0.65-0.9
53
8.5
33
1.2
10
6
12-16
*
S
S
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
Sa
Sa
Sa
-6611P
-6611P
-6611P
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
ndy Bridge (5/6)
ndy Bridge (5/6)
ndy Bridge (5/6)
10 64Wedn
10 64Wedn
10 64Wedn
1
of
of
of
5
D D
CC_GFXCORE
+V
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC13
CC13
CC13
CC13
1
1
1
8
8
7
7
2
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
285
285
284
284
2
C C
B B
A A
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
286
286
2
CC_SA
+V
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
1
4
4
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
C
1
1
288
288
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
1
2
2
2
1 2
RC
RC
137 0_0402_5%~D
137 0_0402_5%~D
C C
C 289
289
1
2
1
287
287
2
ϰϮϬZĞŵŽǀĞϮϲϱϭϳϯĚƵĞƚŽWŽǁĞƌĐŝƌĐƵŝƚĂůƌĞĂĚLJŚĂƐ WϮϬϭWϮϬϮ
CC26
CC26
1
3
3
2
RUN_O
5V_S3_GATE43
CPU1.
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC14
CC14
CC14
CC14
1
1
4
4
5
5
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
290
290
291
291
2
2
.8V_RUN
+1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC26
CC26
CC26
CC26
1
1
1
1
0
0
2
2
5
CC14
CC14
1
6
6
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC18
CC18
0
0
77 0_0402_5%~D@RC77 0_0402_5%~D@
RC
1 2
RC
RC
79 0_0402_5%~D
79 0_0402_5%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC14
CC14
1
C
C C
C 280
280
7
7
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
C
C
1
C
C
292
292
293
293
2
VCC_AXG
VSS_AXG_SENSE53
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC
CC 174
174
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC16
CC16
1
1
8
8
2
2
+G
ND_VCC_SA 56
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC1
CC1
6
6 9
9
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC
CC 281
281
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
1
296
296
2
2
_SENSE53
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CC
CC 175
175
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC17
CC17
1
1
0
0
2
2
1 2
N38,42,45,50
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC28
CC28
1
CC
CC
3
3
282
282
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
297
297
294
294
2
1.2A
330U_V_2.5MV~D
330U_V_2.5MV~D
CC
CC
+
+
176
176
6A
10U
10U
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CC17
CC17
1
CC
CC
+
+
172
172
2
4
+3
.3V_ALW2
12
RC74
RC74
_0402_5%~D
_0402_5%~D
100K
100K
RUN_O
61
QC4
QC4
A
A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
U1G
U1G
33A
AA46
VAXG[
AB47
VAXG[
AB50
VAXG[
AB51
VAXG[
AB52
VAXG[
AB53
VAXG[
AB55
VAXG[
AB56
VAXG[
AB58
VAXG[
AB59
VAXG[
AC61
VAXG[
AD47
VAXG[
AD48
VAXG[
AD50
VAXG[
AD51
VAXG[
AD52
VAXG[
AD53
VAXG[
AD55
VAXG[
AD56
VAXG[
AD58
VAXG[
AD59
VAXG[
AE46
VAXG[
N45
VAXG[
P47
VAXG[
P48
VAXG[
P50
VAXG[
P51
VAXG[
P52
VAXG[
P53
VAXG[
P55
VAXG[
P56
VAXG[
P61
VAXG[
T48
VAXG[
T58
VAXG[
T59
VAXG[
T61
VAXG[
U46
VAXG[
V47
VAXG[
V48
VAXG[
V50
VAXG
[
V51
VAXG[
V52
VAXG[
V53
VAXG[
V55
VAXG[
V56
VAXG[
V58
VAXG[
V59
VAXG[
W50
VAXG[
W51
VAXG[
W52
VAXG[
W53
VAXG[
W55
VAXG[
W56
VAXG[
W61
VAXG[
Y48
VAXG[
Y61
VAXG[
F45
VAXG_
G45
VSSAXG_
BB3
VCCPLL
BC1
VCCPLL
BC4
VCCPLL
L17
VCCSA[1
L21
VCCSA[2
N16
VCCSA[3
N20
VCCSA[4
N22
VCCSA[5
P17
VCCSA[6
P20
VCCSA[7]
R16
VCCSA[8
R18
VCCSA[9]
R21
VCCSA[1
U15
VCCSA[1
V16
VCCSA[1
V17
VCCSA[1
V18
VCCSA[1
V21
VCCSA[1
W20
VCCSA[16]
SANDY
SANDY
-BRIDGE_BGA1023~D
-BRIDGE_BGA1023~D
4
N_CPU1.5VS3#
1] 2] 3] 4] 5] 6] 7] 8] 9] 10] 11] 12] 13] 14] 15] 16] 17] 18] 19] 20] 21] 22] 23] 24] 25] 26] 27] 28] 29] 30] 31] 32] 33] 34] 35] 36] 37] 38] 39] 40] 41] 42] 43] 44] 45] 46] 47] 48] 49] 50] 51] 52] 53] 54] 55] 56]
SENSE
SENSE
[1] [2] [3]
] ] ] ] ] ]
]
0] 1] 2] 3] 4] 5]
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
LW
+15V_A
100K
100K
12
RC72
RC72
_0402_5%~D
_0402_5%~D
RUN_O
3
4
4
B
B
QC
QC DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
4
RUN_O
N_CPU1.5VS3# 7,45
VREF
SM_
VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[ VDDQ[
VDDQ[
10] 11]
VDDQ[ VDDQ[
12] 13]
VDDQ[ VDDQ[
14] 15]
VDDQ[
16]
VDDQ[ VDDQ[
17] 18]
VDDQ[ VDDQ[
19] 20]
VDDQ[ VDDQ[
21]
VDDQ[
22]
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
POWER
POWER
VDDQ[ VDDQ[ VDDQ[ VDDQ[
VCCDQ[ VCCDQ[
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_
SENSE LINES
SENSE LINES
VCCSA_SENSE
VCCSA_VI VCCSA_VI
VDDQ
D[0] D[1]
23] 24] 25] 26]
A
A
8 7 6 5
3
QC3
QC3
O4728L_SO8~D
O4728L_SO8~D
4
1
CC
CC 4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
V_MEM
+1.5
N_CPU1.5VS3
нϭϱsͺWhͺsY^ŽƵƌĐĞ
_SM_VREF_CNT
+V
AY43
5A
AJ28
1]
AJ33
2]
AJ36
3]
AJ40
4]
AL30
5]
AL34
6]
AL38
7]
AL42
8]
AM33
9]
AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33
AM28
1]
AN26
2]
BC43 BA43
U10
D48
H_VCCSA_
D49
нsͺ^DͺsZ&ƐŚŽƵůĚŚĂǀĞϭϬŵŝů ƚƌĂĐĞǁŝĚƚŚ
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
250
250
2
DŝĚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
161
161
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC
CC
+
+
167
167
>ŽǁͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ
2
VID1_R
1 2
RC138 0_0402_5%~DRC138 0_0402_5%~D
3
1 2 3
136
136
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
251
251
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
1
162
162
2
.5V_CPU_VDDQ
+1
CCSA_SENSE 56
+V
H_VCCSA_
1
2
1
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC252
CC252
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC 163
163
1
2
+1
.5V_CPU_VDDQ
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
CC135
CC135
+1
.5V_CPU_VDDQ
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
1
253
253
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC
CC 164
164
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC574
CC574
VID0
20K
20K
12
_0402_5%~D
_0402_5%~D
1
2
1
2
H_VCCSA_ H_VCCSA_
2
1 2
134 0_0402_5%~D@RC134 0_0402_5%~D@
RC
QC5
_DDR_REF
+V
@
@
RC73
RC73
RUN_O
N_CPU1.5VS3
CC
202 0.1U_0402_10V7K~D@CC202 0.1U_0402_10V7K~D@
173 0.1U_0402_10V7K~D@CC173 0.1U_0402_10V7K~D@
CC
149 0.1U_0402_10V7K~D
149 0.1U_0402_10V7K~D
CC
CC
150 0.1U_0402_10V7K~D
150 0.1U_0402_10V7K~D
CC
CC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
255
255
254
254
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC166
CC166
CC
CC
1
165
165
2
VID0 56 VID1 56
1U_0402_6.3V6K~D
CC
CC
CC257
CC257
1
1
256
256
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC
CC
CC
CC
1
1
179
179
178
178
2
2
QC5
R4503NT1G_SOT23-3~D
R4503NT1G_SOT23-3~D
NT
NT
1
12
12
12
12
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC
CC
CC
CC
1
1
258
258
259
259
2
2
_SM_VREF_CNT
+V
3
100K
100K
12
RC78
RC78
_0402_5%~D
_0402_5%~D
2
+1.5
V_MEM
U1H
U1H
A13
]
VSS[1
A17
VSS[2
]
A21
]
VSS[3
A25
VSS[4
]
A28
5
]
VSS[
A33
]
VSS[6
A37
VSS[7
]
A40
]
VSS[8
A45
VSS[9
]
A49
0]
VSS[1
A53
1]
VSS[1
A9
VSS[1
2]
AA1
VSS[1
3]
AA13
VSS[1
4]
AA50
5]
VSS[1
AA51
6]
VSS[1
AA52
VSS[1
7]
AA53
VSS[1
8]
AA55
9]
VSS[1
AA56
0]
VSS[2
AA8
VSS[2
1]
AB16
2]
VSS[2
AB18
VSS[2
3]
AB21
4]
VSS[2
AB48
5]
VSS[2
AB61
VSS[2
6]
AC10
7]
VSS[2
AC14
8]
VSS[2
AC46
9]
VSS[2
AC6
VSS[3
0]
AD17
1]
VSS[3
AD20
2]
VSS[3
AD4
3]
VSS[3
AD61
4]
VSS[3
AE13
VSS[3
5]
AE8
6]
VSS[3
AF1
VSS[3
7]
AF17
8]
VSS[3
AF21
VSS[3
9]
AF47
0]
VSS[4
AF48
1]
VSS[4
AF50
VSS[4
2]
AF51
3]
VSS[4
AF52
VSS[4
4]
AF53
5]
VSS[4
AF55
VSS[4
6]
AF56
VSS[4
7]
AF58
VSS[4
8]
AF59
9]
VSS[4
AG10
0]
VSS[5
AG14
VSS[5
1]
AG18
2]
VSS[5
AG47
VSS[5
3]
AG52
4]
VSS[5
AG61
VSS[5
5]
AG7
VSS[
6]
5
AH4
7]
VSS[5
AH58
8]
VSS[5
AJ13
9]
VSS[5
AJ16
VSS[6
0]
AJ20
1]
VSS[6
AJ22
VSS[6
2]
AJ26
3]
VSS[6
AJ30
VSS[6
4]
AJ34
VSS[6
5]
AJ38
6]
VSS[6
AJ42
VSS[6
7]
AJ45
8]
VSS[6
AJ48
VSS[6
9]
AJ7
0]
VSS[7
AK1
VSS[7
1]
AK52
VSS[7
2]
AL10
VSS[7
3]
AL13
VSS[7
4]
AL17
5]
VSS[7
AL21
VSS[7
6]
AL25
7]
VSS[7
AL28
VSS[7
8]
AL33
9]
VSS[7
AL36
VSS[8
0]
AL40
1]
VSS[8
AL43
VSS[8
2]
AL47
VSS[8
3]
AL61
VSS[84]
AM13
VSS[8
5]
AM20
VSS[86]
AM22
VSS[8
7]
AM26
8]
VSS[8
AM30
VSS[8
9]
AM34
0]
VSS[9
ANDY-BRIDGE_BGA1023~D
ANDY-BRIDGE_BGA1023~D
S
S
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1
VSS
VSS
ndy Bridge (6/6)
ndy Bridge (6/6)
ndy Bridge (6/6)
Sa
Sa
Sa
LA
LA
LA
-6611P
-6611P
-6611P
1
AM38
1]
VSS[9
AM4
VSS[9
2]
AM42
3]
VSS[9
AM45
VSS[9
4]
AM48
9
5]
VSS[
AM58
6]
VSS[9
AN1
VSS[9
7]
AN21
8]
VSS[9
AN25
VSS[9
9]
AN28
00]
VSS[1
AN33
01]
VSS[1
AN36
VSS[1
02]
AN40
VSS[1
03]
AN43
VSS[1
04]
AN47
05]
VSS[1
AN50
06]
VSS[1
AN54
VSS[1
07]
AP10
VSS[1
08]
AP51
09]
VSS[1
AP55
10]
VSS[1
AP7
VSS[1
11]
AR13
12]
VSS[1
AR17
VSS[1
13]
AR21
14]
VSS[1
AR41
15]
VSS[1
AR48
VSS[1
16]
AR61
17]
VSS[1
AR7
18]
VSS[1
AT14
19]
VSS[1
AT19
VSS[1
20]
AT36
21]
VSS[1
AT4
22]
VSS[1
AT45
23]
VSS[1
AT52
24]
VSS[1
AT58
VSS[1
25]
AU1
26]
VSS[1
AU11
VSS[1
27]
AU28
28]
VSS[1
AU32
VSS[1
29]
AU51
30]
VSS[1
AU7
31]
VSS[1
AV17
VSS[1
32]
AV21
33]
VSS[1
AV22
VSS[1
34]
AV34
35]
VSS[1
AV40
VSS[1
36]
AV48
VSS[1
37]
AV55
VSS[1
38]
AW13
39]
VSS[1
AW43
40]
VSS[1
AW61
VSS[1
41]
AW7
42]
VSS[1
AY14
VSS[1
43]
AY19
44]
VSS[1
AY30
VSS[1
45]
AY36
VSS[
46]
1
AY4
47]
VSS[1
AY41
48]
VSS[1
AY45
49]
VSS[1
AY49
VSS[1
50]
AY55
51]
VSS[1
AY58
VSS[1
52]
AY9
53]
VSS[1
BA1
VSS[1
54]
BA11
VSS[1
55]
BA17
56]
VSS[1
BA21
VSS[1
57]
BA26
58]
VSS[1
BA32
VSS[1
59]
BA48
60]
VSS[1
BA51
VSS[1
61]
BB53
VSS[1
62]
BC13
VSS[1
63]
BC5
VSS[1
64]
BC57
65]
VSS[1
BD12
VSS[1
66]
BD16
67]
VSS[1
BD19
VSS[1
68]
BD23
69]
VSS[1
BD27
VSS[1
70]
BD32
71]
VSS[1
BD36
VSS[1
72]
BD40
VSS[1
73]
BD44
VSS[174]
BD48
VSS[1
75]
BD52
VSS[176]
BD56
VSS[1
77]
BD8
78]
VSS[1
BE5
VSS[1
79]
BG13
80]
VSS[1
/PROPRIETARY
11 64Wedn
11 64Wedn
11 64Wedn
of
of
of
5
RD
RD
1 0_0402_5%~D
1 0_0402_5%~D
_DDR_REF
+V
+D
DQS#[0..7]8
DDR_A_
DDR_A_
D[0..63]8
DDR_A_
DQS[0..7]8
DDR_A_
MA[0..15]8
D D
IMM0_1_VREF_CPU
WŽƉƵůĂƚĞZϭĨŽƌ/ŶƚĞůZϯ sZ&YŵƵůƚŝƉůĞŵĞƚŚŽĚƐDϭ
ůůsZ&ƚƌĂĐĞƐƐŚŽƵůĚ ŚĂǀĞϭϬŵŝůƚƌĂĐĞǁŝĚƚŚ
7 0_0402_5%~D@RD7 0_0402_5%~D@
RD
1 2 1 2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DD
+1.5
V_MEM
1U_0402_6.
1U_0402_6.
1U_0402_6.
1U_0402_6.
1
1
CD3
CD3
CD4
CD4
3V6K~D
3V6K~D
3V6K~D
3V6K~D
2
2
+1.5
C C
V_MEM
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD7
CD7
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD8
CD8
10U_0603_6.
10U_0603_6.
1
3V6M~D
3V6M~D
2
CD9
CD9
1
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
1U_0402_6.
1U_0402_6.
CD5
CD5
3V6K~D
3V6K~D
1
2
1U_0402_6.
1U_0402_6.
1
CD6
CD6
3V6K~D
3V6K~D
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD10
CD10
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD11
CD11
1
2
330U
330U
_0603_6.3V6M~D
_0603_6.3V6M~D
@
@
_SX_2VY~D
_SX_2VY~D
CD13
CD13
CD1
CD1
1
1
2
2
2
2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DDϮϬϯϮϬϰ
.75V_DDR_VTT
+0
B B
A A
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
CD17
CD17
CD18
CD18
2
2
5
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
CD20
CD20
CD19
CD19
2
2 10K_0402_5%~D
2 10K_0402_5%~D
RD
RD
1 2
1 2
RD
RD
3 10K_0402_5%~D
3 10K_0402_5%~D
4
2.
2. 2U
2U _0603_6.3V6K~D
_0603_6.3V6K~D
1
2
CD1
CD1
MM0_1_VREF_DQ
+DI
0.1U
0.1U
_0402_16V4Z~D
_0402_16V4Z~D
1
CD2
CD2
2
EŽƚĞ ŚĞĐŬǀŽůƚĂŐĞƚŽůĞƌĂŶĐĞŽĨ sZ&ͺYĂƚƚŚĞ/DDƐŽĐŬĞƚ
_DIMMA8
DDR_A_
M_
CLK_DDR08 CLK_DDR#08
M_
DDR_A_
DDR_A_
DDR_A_
DDR_CKE0
BS28
BS08
WE#8
CAS#8
_DIMMA#8
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD22
CD22
1
2
DDR_CKE0
1
CD14
CD14
+
+
2
DDR_CS1
+3.3V_RUN
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD21
CD21
1
2
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
A_
DDR_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
_DIMMA
DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
M_
CLK_DDR0
M_
CLK_DDR#0
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_CS1
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_ DDR_A_
DDR_A_D56 DDR_A_
DDR_A_ DDR_A_
+1.5
D0 D1
D2 D3
D8 D9
DQS#1 DQS1
D10 D11
D16 D17
DQS#2 DQS2
D18 D19
D24 D25
D26 D27
BS2
MA12 MA9
MA8 MA5
MA3 MA1
MA10 BS0
WE# CAS#
MA13
_DIMMA#
D32 D33
DQS#4 DQS4
D34 D35
D40 D41
D42 D43
D48 D49
DQS#6 DQS6
D50 D51
D57
D58 D59
V_MEM
/DD,сϰϬŵŵ
4
3
JD
JD
IMMA1
IMMA1
1
VREF_D
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
9
DQ
25
VSS
27
DQS1
#
29
DQS1
31
VSS
33
0
DQ1
35
1
DQ1
37
VSS
39
DQ1
6
41
DQ1
7
43
VSS
45
#
DQS2
47
DQS2
49
VSS
51
8
DQ1
53
9
DQ1
55
VSS
57
4
DQ2
59
DQ2
5
61
VSS
63
DM3
65
VSS
67
6
DQ2
69
7
DQ2
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/
BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
AP
A10/
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1
#
123
VDD
125
TEST
127
VSS
129
DQ3
2
131
3
DQ3
133
VSS
135
#
DQS4
137
DQS4
139
VSS
141
4
DQ3
143
DQ3
5
145
VSS
147
DQ4
0
149
1
DQ4
151
VSS
153
DM5
155
VSS
157
DQ4
2
159
3
DQ4
161
VSS
163
8
DQ4
165
DQ4
9
167
VSS
169
DQS6
#
171
DQS6
173
VSS
175
DQ5
0
177
DQ51
179
VSS
181
DQ56
183
DQ5
7
185
VSS
187
DM7
189
VSS
191
DQ5
8
193
9
DQ5
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013022-2~D
TYCO_2-2013022-2~D
Q
CONN@
CONN@
VREF_C
VSS DQ4 DQ5 VSS
DQS0
DQS0
VSS DQ6 DQ7
VSS DQ1 DQ
VSS
DM1
RESET#
VSS DQ1 DQ1
VSS DQ2 DQ2
VSS
DM2
VSS DQ2 DQ2
VSS DQ2 DQ2
VSS
DQS3
DQS3
VSS DQ3 DQ3
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1 RAS#
VDD
ODT
VDD ODT
VDD
VSS DQ3 DQ3
VSS
DM4
VSS DQ3 DQ3
VSS DQ4 DQ4
VSS
DQS5
DQS5
VSS DQ4 DQ4
VSS DQ5 DQ5
VSS
DM6
VSS DQ5 DQ5
VSS DQ6 DQ61
VSS
DQS7
DQS7
VSS DQ6 DQ6
VSS
EVENT#
SDA
SCL
VTT
GND1
V_MEM
+1.5
2 4 6 8 10
#
12 14 16 18 20 22
2
24
1
3
26 28 30 32 34
4
36
5
38 40
0
42
1
44 46 48 50
2
52
3
54 56
8
58
9
60 62
#
64 66 68
0
70
1
72
74 76 78
A15
80
A14
82 84
A11
86
A7
88 90
A6
92
A4
94 96
A2
98
A0
100 102 104 106 108 110 112 114
S0#
116
0
118 120
1
122
NC
124 126
A
128 130
6
132
7
134 136 138 140
8
142
9
144 146
4
148
5
150 152
#
154 156 158
6
160
7
162 164
2
166
3
168 170 172 174
4
176
5
178 180
0
182 184 186
#
188 190 192
2
194
3
196 198 200 202 204
206
ϮͲϯƚŽϭ/DDƐĐŚĂŶŶĞů
D4
DDR_A_ DDR_A_
D5
DDR_A_
DQS#0 DQS0
DDR_A_
DDR_A_
D6 D7
DDR_A_
DDR_A_
D12
DDR_A_
D13
DRAMRST#_R
DDR3_
A_
D14
DDR_
D15
DDR_A_
D20
DDR_A_ DDR_A_
D21
D22
DDR_A_ DDR_A_
D23
DDR_A_
D28
DDR_A_
D29
DQS#3
DDR_A_
DQS3
DDR_A_
D30
DDR_A_ DDR_A_
D31
_DIMMA
DDR_CKE1
MA15
DDR_A_ DDR_A_
MA14
DDR_A_
MA11 MA7
DDR_A_
DDR_A_
MA6 MA4
DDR_A_
MA2
DDR_A_ DDR_A_
MA0
M_
CLK_DDR1
M_
CLK_DDR#1
DDR_A_
BS1 RAS#
DDR_A_
_DIMMA#
DDR_CS0 M_O
DT0
M_O
DT1
DDR_A_
D36 D37
DDR_A_
DDR_A_
D38 D39
DDR_A_
D44
DDR_A_ DDR_A_
D45
DQS#5
DDR_A_ DDR_A_
DQS5
DDR_A_
D46 D47
DDR_A_
DDR_A_
D52
DDR_A_
D53
DDR_A_
D54 D55
DDR_A_
D60
DDR_A_ DDR_A_D61
DDR_A_DQS#7 DDR_A_
DQS7
DDR_A_
D62 D63
DDR_A_
DDR_XDP_WAN_SMBDAT
WAN_SMBCLK
DDR_XDP_
+0.75V_DDR_VTT+0.75V_DDR_VTT
DDR3_
DDR_CKE1
M_
CLK_DDR1 8
CLK_DDR#1 8
M_
DDR_A_
DDR_A_
DDR_CS0
M_O
M_O
DRAMRST#_R13
2
DRAMRST#_R
DDR3_
_DIMMA 8
BS1 8
RAS# 8
_DIMMA# 8
DT0 8
DT1 8
MM0_1_VREF_CA
+DI
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD15
CD15
1
2
WAN_SMBDAT 13,15,28,37
DDR_XDP_
DDR_XDP_WAN_SMBCLK 13,15,28,37
1
2
>ŝŶŬŽŶĞ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
1 2
RD
RD
28 1K_0402_1%~D
28 1K_0402_1%~D
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD16
CD16
1
+1.5
V_MEM
12
RD27
RD27
_0402_1%~D
_0402_1%~D
1K
1K
DDR3_
DRAMRST# 7
RD290_0402_5%
~D
~D
~D @
~D @
DELL CONFIDENTIAL
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RD290_0402_5%
12
+V
RD310_0402_5%
RD310_0402_5%
12
+DI
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Co
DDRIII-S
DDRIII-S
DDRIII-S
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
_DDR_REF
MM0_1_CA_CPU
/PROPRIETARY
ODIMM SLOT1
ODIMM SLOT1
ODIMM SLOT1
12 64We
12 64We
12 64We
1
of
of
of
5
DDR_B_
DQS#[0..7]8
DDR_B_
D[0..63]8
DDR_B_
DQS[0..7]8
DDR_B_
D D
MA[0..15]8
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DD
V_MEM
+1.5
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
C C
V_MEM
+1.5
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
1
2
B B
1
CD25
CD25
CD26
CD26
2
2
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CD30
CD30
CD29
CD29
CD31
CD31
1
2
1
1
2
2
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
CD28
CD28
CD27
CD27
2
10U
10U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
_0603_6.3V6M~D
CD34
CD32
CD32
CD34
CD33
CD33
1
1
2
2
330U
330U
10U
10U
_0603_6.3V6M~D
_0603_6.3V6M~D
_SX_2VY~D
_SX_2VY~D
@
@
1
CD36
CD36
CD35
CD35
1
+
+
2
2
>ĂLJŽƵƚEŽƚĞ WůĂĐĞŶĞĂƌ:/DDϮϬϯϮϬϰ
.75V_DDR_VTT
+0
1U
1U
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
2
A A
CD40
CD40
CD39
CD39
2
5
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
1
1
CD41
CD41
CD42
CD42
2
2
4
ůůsZ&ƚƌĂĐĞƐƐŚŽƵůĚ ŚĂǀĞϭϬŵŝůƚƌĂĐĞǁŝĚƚŚ
WŽƉƵůĂƚĞZϭĨŽƌ/ŶƚĞůZϯ sZ&YŵƵůƚŝƉůĞŵĞƚŚŽĚƐDϭ
EŽƚĞ ŚĞĐŬǀŽůƚĂŐĞƚŽůĞƌĂŶĐĞŽĨ sZ&ͺYĂƚƚŚĞ/DDƐŽĐŬĞƚ
.3V_RUN
+3
RD5 10K_0402_5%~DRD5 10K_0402_5%~D
4
+DI
+3.3V_RUN
12
MM0_1_VREF_DQ
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
1
CD23
CD23
2
DDR_CKE2
M_ M_
DDR_CS3
_DIMMB#8
12
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
2
_DIMMB8
DDR_B_
CLK_DDR28 CLK_DDR#28
DDR_B_
DDR_B_
DDR_B_
10K_0402_5%
10K_0402_5%
RD6
RD6
~D
~D
3
ϮͲϯƚŽϭ/DDƐĐŚĂŶŶĞů
V_MEM
CD24
CD24
BS28
BS08
WE#8
CAS#8
1
2
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_CKE2
DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
M_ M_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_
DDR_
CS3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_D51
DDR_B_D56 DDR_B_
DDR_B_ DDR_B_
+0.75V_DDR_VTT
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
CD43
CD43
+1.5
D0 D1
D2 D3
D8 D9
DQS#1
B_
DQS1
D10 D11
D16 D17
DQS#2 DQS2
D18 D19
D24 D25
D26 D27
_DIMMB
BS2
MA12 MA9
MA8 MA5
MA3 MA1
CLK_DDR2 CLK_DDR#2
MA10 BS0
WE# CAS#
MA13
_DIMMB#
D32 D33
DQS#4 DQS4
D34 D35
D40 D41
D42 D43
D48 D49
DQS#6 DQS6
D50
D57
D58 D59
1
2
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
CD44
CD44
JD
JD
IMMB1
IMMB1
1
VREF_D
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1
#
29
DQS1
31
VSS
33
DQ1
0
35
DQ1
1
37
VSS
39
6
DQ1
41
7
DQ1
43
VSS
45
DQS2
#
47
DQS2
49
VSS
51
DQ1
8
53
9
DQ1
55
VSS
57
4
DQ2
59
5
DQ2
61
VSS
63
DM3
65
VSS
67
6
DQ2
69
DQ2
7
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12
/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10
/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ3
2
131
3
DQ3
133
VSS
135
DQS4
#
137
DQS4
139
VSS
141
4
DQ3
143
DQ3
5
145
VSS
147
DQ4
0
149
DQ4
1
151
VSS
153
DM5
155
VSS
157
DQ4
2
159
3
DQ4
161
VSS
163
8
DQ4
165
DQ4
9
167
VSS
169
DQS6
#
171
DQS6
173
VSS
175
DQ5
0
177
DQ51
179
VSS
181
6
DQ5
183
DQ5
7
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ5
9
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013297-2~D
TYCO_2-2013297-2~D
CONN@
CONN@
Q
DQS0
RESET#
DQS3
VREF_C
DQS5
DQS7
EVENT#
DQS0
DQ1 DQ1
DQ1 DQ1
DQ2 DQ2
DQ2 DQ2
DQ2 DQ2
DQS3
DQ3 DQ3
CKE1
RAS#
ODT
ODT
DQ3 DQ3
DQ3 DQ3
DQ4 DQ4
DQS5
DQ4 DQ4
DQ5 DQ5
DQ54 DQ5
DQ6 DQ6
DQS7
DQ62 DQ6
GND1
/DD,сϴŵŵ
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DQ4 DQ5 VSS
VSS DQ6 DQ7 VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA SCL VTT
VSS
A15 A14
A11
S0#
V_MEM
+1.5
2
DDR_B_
4
DDR_B_
6 8
DDR_B_
10
#
2 3
4 5
0 1
2 3
8 9
#
0 1
A7
A6 A4
A2 A0
0
1
NC
A
6 7
8 9
4 5
#
6 7
2 3
5
0 1
#
3
12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206
DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_CKE3
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
M_ M_
DDR_B_ DDR_B_
DDR_CS2 M_O
M_O
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_B_ DDR_B_D61
DDR_B_ DDR_B_
DDR_B_ DDR_B_
DDR_XDP_WAN_SMBDAT DDR_XDP_
+0.75V_DDR_VTT
>ŝŶŬŽŶĞ
D4 D5
DQS#0 DQS0
D6 D7
D12 D13
_
DRAMRST#_R
D14 D15
D20 D21
D22 D23
D28 D29
DQS#3 DQS3
D30 D31
MA15 MA14
MA11 MA7
MA6 MA4
MA2 MA0
CLK_DDR3 CLK_DDR#3
BS1 RAS#
_DIMMB#
DT2
DT3
D36 D37
D38 D39
D44 D45
DQS#5 DQS5
D46 D47
D52 D53
D54 D55
D60
DQS#7 DQS7
D62 D63
2
_DIMMB
WAN_SMBCLK
2
DRAMRST#_R 12
DDR3_
DDR_CKE3
_DIMMB 8
CLK_DDR3 8
M_
CLK_DDR#3 8
M_
DDR_B_
BS1 8
RAS# 8
DDR_B_
DDR_CS2
_DIMMB# 8
M_O
DT2 8
DT3 8
M_O
MM0_1_VREF_CA
+DI
2.
2. 2U_0603_6.3V6K~D
2U_0603_6.3V6K~D
1
CD37
CD37
2
DDR_XDP_
DDR_XDP_WAN_SMBCLK 12,15,28,37
1
0.
0. 1U_0402_16V4Z~D
1U_0402_16V4Z~D
1
CD38
CD38
2
WAN_SMBDAT 12,15,28,37
DELL CONFIDENTIAL
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
Co
Co
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Co
DDRIII-S
DDRIII-S
DDRIII-S
LA
LA
LA
-6611P
-6611P
dnesday, January 26, 2011
dnesday, January 26, 2011
dnesday, January 26, 2011
-6611P
/PROPRIETARY
ODIMM SLOT2
ODIMM SLOT2
ODIMM SLOT2
13 64We
13 64We
13 64We
1
of
of
of
5
S_CLR1
CMO
Shunt
Open
ME_
CLR1
TPM setting
Shunt
Clear
Keep
Open
D D
TC
_CELL
+R
12
RH38
RH38 330K
330K
_0402_1%~D
_0402_1%~D
PCH_I
12
@
@
RH39
RH39
_0402_1%~D
_0402_1%~D
330K
330K
setting
CMOS
Clear
CMOS
Keep CM
OS
ME RTC Registers
ME RTC Registers
NTVRMEN
W,ͺͺ^zEŝƐƐĂŵƉůĞĚ ĂƚƚŚĞƌŝƐŝŶŐĞĚŐĞŽĨZ^DZ^dηƉŝŶ ^ŽƐŝŐŶĂůƐŚŽƵůĚďĞWhƚŽƚŚĞ>tz^ƌĂŝů
.3V_ALW_PCH
+3
12
RH66
RH66
_0402_5%~D
_0402_5%~D
1K
1K
PCH_AZ
_SYNC
12
2
@
2
@
RH28
RH28 100K_0402_5%~D
100K_0402_5%~D
KŶŝĞW>>sZŝƐƐƵƉƉůŝĞĚďLJ ϭϱsǁŚĞŶƐĂŵƉůĞĚŚŝŐŚϭϴs ǁŚĞŶƐĂŵƉůĞĚůŽǁ
/EdsZDEͲ/ŶƚĞŐƌĂƚĞĚ^h^ϭϭs sZDŶĂďůĞ
Ύ
,ŝŐŚͲŶĂďůĞ/ŶƚĞƌŶĂůsZƐ >ŽǁͲŶĂďůĞdžƚĞƌŶĂůsZƐ
1
1
C C
SPI_
DO32
I_CLK32
SP
PCH_
_CS0#
SPI
+3.3
V_M
@
@
ME
ME
CONN@
CONN@
JP1
JP1
112 334 556 778 9910 111112
G113G2 G315G4 G517G6
CO_5-1775013-4~D
CO_5-1775013-4~D
TY
TY
1 SHORT PADS~D
1 SHORT PADS~D
1 2
CH
CH
5 1U_0402_6.3V6K~D
5 1U_0402_6.3V6K~D
2 4 6 8
PCH_SPI
10 12
14 16 18
>ŝŶŬŽŶĞ
B B
5@
5@
R933 0_0402_5%
R933 0_0402_5%
1 2
R894 33_0402_5%
R894 33_0402_5%
1 2
R898 0_0402_5%
R898 0_0402_5%
1 2
SPI_
PCH_SPI
PCH_SPI
WP#_SEL42
_CS0#
_DIN
2
2
I_DIN32
SP
_CS1_R#
R890
R890
5@
5@
3.
3.
3K_0402_5%~D
3K_0402_5%~D
~D
~D
+RTC
PCH_SPI
~D5@
~D5@
~D@
~D@
SPI_
SPI_
_CELL
1 2
_CS0_R#
DIN64
WP#0
1 2
22 20K_0402_5%~D
22 20K_0402_5%~D
RH
RH
1 2
23 20K_0402_5%~D
23 20K_0402_5%~D
RH
RH
1 2
11 1M_0402_5%~D
11 1M_0402_5%~D
RH
RH
1
1
@
@
CMO
CMO
CH4
CH4
DK^ƉůĂĐĞŶĞĂƌ/DD
_CODEC_SDOUT30
PCH_AZ
CODEC_SYNC30
PCH_AZ_
CODEC_RST#30
PCH_AZ_
PCH_AZ_
CODEC_BITCLK30
27P_0402_50V8J~D
27P_0402_50V8J~D
X76ROM@
X76ROM@
U52
U52
1
/CS
2
DO
3
/WP
GND4DIO
25Q64BVSSIG_SO8~D
25Q64BVSSIG_SO8~D
W
W
S1 SHORT PADS~D
S1 SHORT PADS~D
1 2
1U_0402_6.
1U_0402_6.
101
@CH101
@
CH
8
VCC
7
D
/HOL
6
CLK
5
ϮϬϬD/>^Kϴ
ϲϰDď&ůĂƐŚZKD
R888
R888
5@
5@
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
U53
X76ROM@U53
PCH_SPI
_CS1#
R935
R935
PCH_SPI
SPI_
_DIN
WP#_SEL
A A
1 2
R895 33_0402_5%
R895 33_0402_5%
1 2
1 2
R936 0_0402_5%
R936 0_0402_5%
R896 0_0402_5%
R896 0_0402_5%
1 2
PCH_SPI
0_0402_5%
0_0402_5%
~D
~D
~D6@
~D6@
_CS1_R#
~D5@
~D5@
~D@
~D@
SPI_
R936 colay R895 for TAA
1
/CS
DIN32
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q16BVSSIG_SO8~D
W25Q16BVSSIG_SO8~D
ϮϬϬD/>^Kϴ
X76ROM@
VCC
/HOLD(IO3)
CLK
IO0)
DI(
8
7
6
5
ϭϲDď&ůĂƐŚZKD
5
2
2
3V6K~D
3V6K~D
1 2
29 33_0402_5%~D
29 33_0402_5%~D
RH
RH
1 2
RH
RH
26 33_0402_5%~D
26 33_0402_5%~D
1 2
27 33_0402_5%~D
27 33_0402_5%~D
RH
RH
1 2
25 33_0402_5%~D
25 33_0402_5%~D
RH
RH
1
2
SPI_
I_CLK64
SP
SPI_
SPI_
HOLD#1
SPI_CLK32
SPI_DO32
4
SPKR
H
H
35 10K_0402_5%~D@
35 10K_0402_5%~D@
R
R
No Reboot Strap
Low = Default
SPKR
High = No Reboot
CH2
CH2
15P_0402_50V
15P_0402_50V
CH3
CH3
15P_0402_50V
15P_0402_50V
PCH_AZ
PCH_AZ
PCH_AZ_
PCH_AZ
V_M
+3.3
5@
5@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R891
R891
3.
3.
1 2
HOLD#0
DO64
+3.3
V_M
1 2
~D
~D
1 2
1 2
R944 0_0402_5%
R944 0_0402_5%
~D 5@
~D 5@
1 2
1 2
R943 0_0402_5%~D6@R943 0_0402_5%~D6@
4
+3
.3V_RUN
12
12
8J~D
8J~D
8J~D
8J~D
12
_SDOUT
_SYNC_Q
RST#
_BITCLK
C74
C74
6
6
1 2
5@
5@
3K_0402_5%~D
3K_0402_5%~D
~D
~D
1 2
1 2
C745
C745
1 2
1U_0402_16V4Z~D
1U_0402_16V4Z~D
0.
0.
R892
R892
5@
5@
3K_0402_5%~D
3K_0402_5%~D
3.
3.
R944 colay R897 for TAA
5@
5@
+3
.3V_RUN
YH1
YH1
768KHZ_12.5PF_Q13MC1461000~D
768KHZ_12.5PF_Q13MC1461000~D
32.
32.
1
G
G
G
G
RH
RH
PCH_AZ
FWP42
ME_
+3
.3V_ALW_PCH
USB30
5@
5@
R89756_0402_5%
R89756_0402_5%
R90033_0402_5%
R90033_0402_5%
PCH_SPI
R89956_0402_5%
R89956_0402_5%
PCH_SPI
R90133_0402_5%~D 5@ R 90133_0402_5%~D 5@
PCH_SPI_CLK
~D6@
~D6@
PCH_SPI
_CLK
_DO
1
2
_DO
RH
RH
2
34
1 2
286 0_0402_5%~D
286 0_0402_5%~D
_CODEC_SDIN030
RH
RH
1 2
RH
_SMI#29
SP
I_CLK64
CH
CH 27P_0402_50V8J~D
27P_0402_50V8J~D
@
@
R943 colay R900 for TAA
TRST#_EC17,35,37,38,42,43
PCH_PL
RH
RH
37 10K_0402_5%~D
37 10K_0402_5%~D
50 1K_0402_5%~D
50 1K_0402_5%~D
287 1K_0402_5%~D@RH287 1K_0402_5%~D@
108
108
12
41 1M_0402_5%~D
41 1M_0402_5%~D
_SYNC_Q
PCH_AZ
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
PCH_AZ
_SYNC_Q
12
12
RH2
RH2 10M_0402_5%
10M_0402_5%
PCH_RT
SRTCRST
IN
TRUDER#
PCH_I
PCH_AZ
PCH_AZ
SPKR
SPKR30
PCH_AZ_
PCH_AZ
1 2
T132 P
T132 P
B30_SMI#
US
PCH_J
PCH_J
PCH_J
PCH_J
PCH_SPI
PCH_SPI
PCH_SPI
PCH_SPI
PCH_SPI
+3
SP
I_CLK32
1
107
107
CH
CH 27P_0402_50V8J~D
27P_0402_50V8J~D
2
@
@
PCH_RT
PCH_RT
.3V_ALW_PCH
3
G
G
2
13
D
S
D
S
QH7
QH7
CX1
~D
~D
CX2
CRST#
#
NTVRMEN
_BITCLK
_SYNC
RST#
_CODEC_SDIN0
PCH_AZ
AD~D@
AD~D@
TAG_TCK
TAG_TMS
TAG_TDI
TAG_TDO
_CLK
_CS0#
_CS1#
_DO
_DIN
12
RH
RH
0_0603_5%~D
0_0603_5%~D
+3
3
_RUN
+1.05V
0.1U
0.1U
@
@
_0402_16V4Z~D
_0402_16V4Z~D
CH6
CH6
1
2
_SYNC
PCH_AZ
SIO
_PWRBTN#_R
_SDOUT
@
@
288
288
.3V_ALW_PCH_JTAG
36 10K_0402_5%~D@RH36 10K_0402_5%~D@
RH
RST#16,43
PCH_RSM
UH4A
UH4A
0
A2
RTCX1
0
C2
RTCX2
D20
RTCRST
#
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
H7
H1
Y14
U3
#
SRTCRST
IN
TRUDER#
VRMEN
INT
CLK
HDA_B
YNC
HDA_S
SPKR
HDA_R
ST#
DIN0
HDA_S
HDA_S
DIN1
DIN2
HDA_S
HDA_S
DIN3
DO
HDA_S
OCK_EN# / GPIO33
HDA_D
OCK_RST# / GPIO13
HDA_D
J3
G_TCK
JTA
JTA
G_TMS
K5
JTA
G_TDI
JTA
G_TDO
T3
I_CLK
SP
CS0#
SPI_
T1
CS1#
SPI_
V4
SPI_
MOSI
SPI_MISO
2CPMS-QMVY-A1_FCBGA989~D
2CPMS-QMVY-A1_FCBGA989~D
BD8
BD8
/ŶƚĞůƌĞǀŝĞǁĨĞĞĚďĂĐŬ
RH59 51_0402_1%~DRH59 51_0402_1%~D
44 200_0402_1%~D
44 200_0402_1%~D
RH
RH
45 200_0402_1%~D
45 200_0402_1%~D
RH
RH
43 200_0402_1%~D
43 200_0402_1%~D
RH
RH
+3.3V_RUN
8.2K_0402_5%~D
8.2K_0402_5%~D
@RH295
@
12
RH295
SPI_MOSI
,ŝŐŚŶĂďůĞ/ŶƚĞůŶƚŝͲdŚĞĨƚdĞĐŚŶŽůŽŐLJ >ĞĨƚĨůŽĂƚŝŶŐŝƐĂďůĞ/ŶƚĞůŶƚŝͲdŚĞĨƚdĞĐŚŶŽůŽŐLJ
PCH_RSM
12
12
12
12
PCH_SPI
+3
.3V_ALW_PCH
12
RST#
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
_DO
.3V_ALW_PCH
+3
0.1U
0.1U
@
@
_0402_16V4Z~D
_0402_16V4Z~D
CH1
CH1
1
2
RH
24 1K_0402_5%~D@RH24 1K_0402_5%~D@
FW FW FW FW
LPC
LPC
H4 / LFRAME#
FW
LD
RQ1# / GPIO23
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP SATA1TXN
SATA1TXP
SATA2RXN SATA2RXP SATA2TXN
SATA2TXP
SATA3RXN SATA3RXP SATA3TXN
SATA3TXP
SATA4RXN SATA4 SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN SATA5RXP SATA5TXN
SATA5TXP
SATAICO
SATAICO
SATA3RCO
SATA3CO
SATA3RBI
SATALED#
SATA0G
P / GPIO21
SATA1GP / GPIO19
12
RH48
RH48
@
@
2
,ϭĐůƐŽĞƚŽ:yWϮ,ϲĐůƐŽĞƚŽ:yWϮ
12
H0 / LAD0 H1 / LAD1 H2 / LAD2 H3 / LAD3
LDRQ
SERIR
RXP
MPO
MPI
MPO
MPI
PCH_J
12
RH49
RH49
@
@
100_0402_1%~D
100_0402_1%~D
2
1.05V
+3
XDP_DBRESET#7,
16
RSMR
C38 A38 B37 C37
D36
E36
0#
K36
V5
Q
AM AM AP7 AP5
AM AM AP1 AP1
AD7 AD5 AH5 AH4
AB8 AB1 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11
Y10
AB12
AB13
AH1
AS
P3
V14
P1
TAG_TCK
PCH_J
TAG_TMS
TAG_TDI
PCH_J
PCH_J
TAG_TDO
~D
~D
12
RH47
RH47
@
@
100_0402_1%
100_0402_1%
RSMR
_0.8V_PWROK43,53
_PWRBTN#_R7,16
SIO
.3V_ALW_PCH
ST#_XDP
LP
C_LAD0
LP
C_LAD1 C_LAD2
LP
C_LAD3
LP
C_LFRAME#
LP
C_LDRQ0#
LP LP
C_LDRQ1#
IRQ_
3 1
10 8
1 0
0
+SATA_
+SATA3
RBIAS_
SATA_ACT#
HDD_DET
BBS_BI
~D
~D
100_0402_1%
100_0402_1%
ST#_XDP
SERIRQ
SATA3
T0_R
PCH_PL
1
+1.05V
_RUN
RH
284 0_0402_5%~D@RH284 0_0402_5%~D@
1 2
283 1K_0402_5%~D@RH283 1K_0402_5%~D@
RH
1 2 1 2
RH
21 0_0402_5%~D@RH21 0_0402_5%~D@
RSMR
ST#_XDP
DBRESET#
XDP_
PCH_J
TAG_TDO
PCH_J
TAG_TDI TAG_TMS
PCH_J
TAG_TCK
PCH_J
LPC
LP
C_LDRQ0# 42
L
C_LDRQ1# 42
P
IR
Q_SERIRQ 34,35,42,43
PSATA_PRX_ PSATA_PRX_
PSATA_PTX_
PSATA_PTX_
SATA_O
SATA_O SATA_O SATA_O
ESATA_PRX_
ESATA_PRX_ ESATA_PTX_ ESATA_PTX_
SATA_PRX_
SATA_PRX_ SATA_PTX_ SATA_PTX_
COMP
1 2
40 37.4_0402_1%~D
40 37.4_0402_1%~D
RH
RH
_COMP
1 2
42 49.9_0402_1%~D
42 49.9_0402_1%~D
RH
RH
1 2
RH
RH
46 750_0402_1%~D
46 750_0402_1%~D
#_R
1 3
1 BSS138W-7-F_SOT323-3~D
1 BSS138W-7-F_SOT323-3~D
QH
QH
TRST#7,17
+3.3V_RUN
_0.8V_PWROK_R
1.05V RBTN#_XDP
PCH_PW
_LAD0 34,35,42,43
LPC LPC
_LAD1 34,35,42,43 _LAD2 34,35,42,43
LPC LPC
_LAD3 34,35,42,43
_LFRAME# 34,35,42,43
DTX_N0_C 28
DTX_P0_C 28 DRX_N0_C 28 DRX_P0_C 28
DD_PRX_DTX_N1_C 29 DD_PRX_DTX_P1_C 29 DD_PTX_DRX_N1_C 29 DD_PTX_DRX_P1_C 29
DTX_N4_C 40
DTX_P4_C 40 DRX_N4_C 40 DRX_P4_C 40
DKTX_N5_C 41
DKTX_P5_C 41
DKRX_N5_C 41
DKRX_P5_C 41
SATA_ACT#
46
1 2
RH290 0_0402_5%~DRH290 0_0402_5%~D
D
S
D
S
G
G
2
+1.05V
+1.05V
SERIRQ
IRQ_
2K_0402_5%~D
2K_0402_5%~D
,
KDŽĚƵůĞĂLJ
Ͳ^d
K<
_RUN
_RUN
+3
.3V_RUN
^ͺ/dϬͲ/K^KKd^dZW/dϬ
7K_0402_5%~D
7K_0402_5%~D
4.
4.
T0_R
BBS_BI
12
^dϬ'WWƐŝŵƵůĂƚĞƐƚŚĞĚƌŝǀĞƐƚĂƚƵƐ
RH31
RH31
&ŽƌƉƌŽƉĞƌĨƵŶĐƚŝŽŶŽĨƚŚĞŚŽƚƉůƵŐ ƚŚŝƐZϭϱϵϳŵƵƐƚďĞΗEŽ^ŚƵŶƚΗ ǁŚĞŶƌĞƐƉĞĐƚŝǀĞĚƌŝǀĞŝƐƌĞŵŽǀĞĚ ĂŶĚΗ^ŚƵŶƚΗĂĨƚĞƌƚŚĞƌĞƐƉĞĐƚŝǀĞ ĚƌŝǀĞŝƐƉůƵŐŐĞĚŝŶ
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1/8)
1/8)
1/8)
-6611P
-6611P
-6611P
1
P2
@
P2
@
JXD
JXD
1
OBSFN_
A0
2
A1
OBSFN_
3
GND
4
OBSDATA_
A[0]
5
A[1]
OBSDATA_
6
GND
7
A[2]
OBSDATA_
8
OBSDATA_
A[3]
9
GND
10
HOOK
0
11
1
HOOK
12
HOOK
2
13
OOK
3
H
14
4
HOOK
15
HOOK
5
16
AB
VCCOBS_
17
HOOK
6
18
7
HOOK
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS TCK124GND
25
GND
26
TCK0
MOLEX_52435-2671
MOLEX_52435-2671
12
RH30
RH30 10K
10K
PCH_SATA_
GND
+3
12
RH288.
RH288.
_0402_5%~D
_0402_5%~D
HDD_DET
27 28
.3V_RUN
# 28
MOD_EN# 43
/PROPRIETARY
14 64Wedn
14 64Wedn
14 64Wedn
of
of
of
5
D D
&ŽůůŽǁ'ϬϵĞǀŝĐĞĚŽǁŶΘdžƉƌĞƐƐDŝŶŝĐĂƌĚ ƚŽƉŽůŽŐLJ
IE_PRX_WANTX_N137
PC PC
MiniWWAN (Mini Card 1)--->
MiniWLAN (Mini Card 2)--->
EXPRESS Card--->
E3 Module Bay--->
1/2vMINI CARD-3 PCIE (Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
MiniWWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI Card--->
B B
MiniWPAN (Mini Card 3)--->
Express card--->
MiniWLAN (Mini Card 2)--->
eModule Bay--->
A A
IE_PRX_WANTX_P137
PC
IE_PTX_WANRX_N137 IE_PTX_WANRX_P137
PC
_PRX_WLANTX_N237
PCIE PCIE
_PRX_WLANTX_P237
PC
IE_PTX_WLANRX_N237 IE_PTX_WLANRX_P237
PC
PCIE
_PRX_EXPTX_N338
PCI
PRX_EXPTX_P338
E_
_PTX_EXPRX_N338
PCIE
PTX_EXPRX_P338
PCIE_
PC
IE_PRX_EMBTX_N429 IE_PRX_EMBTX_P429
PC
IE_PTX_EMBRX_N429
PC PC
IE_PTX_EMBRX_P429
PCI
_PRX_WPANTX_N537
E
_PRX_WPANTX_P537
PCIE
_PTX_WPANRX_N537
PCIE PCIE
_PTX_WPANRX_P537
IE_PRX_MMITX_N636
PC PC
IE_PRX_MMITX_P636
PC
IE_PTX_MMIRX_N636
PC
IE_PTX_MMIRX_P636
IE_PRX_GLANTX_N732
PC PC
IE_PRX_GLANTX_P732
PC
IE_PTX_GLANRX_N732 IE_PTX_GLANRX_P732
PC
K_PCIE_MIN I1#37
CL
K_PCIE_MIN I137
CL
.3V_ALW_PCH
+3
MI
NI1CLK_REQ#37
PCIE_LAN#32
CLK_ CLK_
PCIE_LAN32
NCLK_REQ#32
LA
CLK_
PCIE_MMI#36 PCIE_MMI36
CLK_
+3
ICLK_REQ#36
MM
K_PCIE_MIN I3#37
CL
K_PCIE_MIN I337
CL
.3V_ALW_PCH
+3
NI3CLK_REQ#37
MI
PCIE_EXP#38
CLK_
CLK_
+3
.3V_ALW_PCH
EXPCLK
CL
K_PCIE_MIN I2#37
K_PCIE_MIN I237
CL
.3V_ALW_PCH
+3
NI2CLK_REQ#37
MI
.3V_ALW_PCH
+3
CLK_PCIE_EMB#29 CLK_
PCIE_EMB29
+3
.3V_ALW_PCH
EMBCL
CLK_
CPU_ITP#7
CPU_ITP7
CLK_
W/ZYƉŽǁĞƌƌĂŝů
.3V_RUN
PCIE_EXP38
_REQ#38
K_REQ#29
307 0_0402_5%~D
307 0_0402_5%~D
RH
RH
308 0_0402_5%~D
308 0_0402_5%~D
RH
RH
81 10K_0402_5%~D
81 10K_0402_5%~D
RH
RH
RH
RH
82 0_0402_5%~D
82 0_0402_5%~D
RH
RH
83 0_0402_5%~D
83 0_0402_5%~D
RH
RH
85 0_0402_5%~D
85 0_0402_5%~D 86 0_0402_5%~D
86 0_0402_5%~D
RH
RH
87 10K_0402_5%~D
87 10K_0402_5%~D
RH
RH
88 0_0402_5%~D
88 0_0402_5%~D
RH
RH
90 0_0402_5%~D
90 0_0402_5%~D
RH
RH RH
RH
152 10K_0402_5%~D
152 10K_0402_5%~D
RH
RH
92 0_0402_5%~D
92 0_0402_5%~D 93 0_0402_5%~D
93 0_0402_5%~D
RH
RH
94 10K_0402_5%~D
94 10K_0402_5%~D
RH
RH
95 0_0402_5%~D
95 0_0402_5%~D
RH
RH RH96 0_0402_5%~DRH96 0_0402_5%~D RH
RH
97 10K_0402_5%~D
97 10K_0402_5%~D
98 10K_0402_5%~D
98 10K_0402_5%~D
RH
RH
RH310 0_0402_5%~DRH310 0_0402_5%~D
312 0_0402_5%~D
312 0_0402_5%~D
RH
RH RH104 10K_0402_5%~DRH104 10K_0402_5%~D
RH
RH
280 0_0402_5%~D
280 0_0402_5%~D 281 0_0402_5%~D
281 0_0402_5%~D
RH
RH
ƐƵƐƉĞŶĚϬϯϰϱϲϳ ĐŽƌĞϭϮ
5
1 2
1 2
4
UH4B
C
IE_PRX_WANTX_N1
P
IE_PRX_WANTX_P1
PC PC
IE_PTX_WANRX_N1 IE_PTX_WANRX_P1
PC
IE_PRX_WLANTX_N2
PC
IE_PRX_WLANTX_P2
PC PC
IE_PTX_WLANRX_N2 IE_PTX_WLANRX_P2
PC
_PRX_EXPTX_N3
PCIE PCIE_
PRX_EXPTX_P3
PCIE
_PTX_EXPRX_N3
PCIE_
PTX_EXPRX_P3
IE_PRX_EMBTX_N4
PC PC
IE_PRX_EMBTX_P4 IE_PTX_EMBRX_N4
PC PC
IE_PTX_EMBRX_P4
PC
IE_PRX_WPANTX_N5
PC
IE_PRX_WPANTX_P5 IE_PTX_WPANRX_N5
PC
IE_PTX_WPANRX_P5
PC
PC
IE_PRX_MMITX_N6 IE_PRX_MMITX_P6
PC PC
IE_PTX_MMIRX_N6 IE_PTX_MMIRX_P6
PC
PC
IE_PRX_GLANTX_N7 IE_PRX_GLANTX_P7
PC PC
IE_PTX_GLANRX_N7 IE_PTX_GLANRX_P7
PC
PC
12 12 12
12 12
12 12
12 12 12
12 12 12
12 12 12
12 12 12
12 12
4
IE_MINI1# IE_MINI1
PC
NI1CLK_REQ#
MI
_LAN#
PCIE PCI
_LAN
E
LA
NCLK_REQ#
IE_MMI#
PC PC
IE_MMI
ICLK_REQ#
MM
PC
IE_MINI3# IE_MINI3
PC
MI
NI3CLK_REQ#
_EXP#
PCIE
_EXP
PCIE
EXPCLK
_REQ#
IE_MINI2#
PC PC
IE_MINI2
MI
NI2CLK_REQ#
G_B_CLKRQ#
PE
PCIE
_EMB# _EMB
PCIE
K_REQ#
EMBCL
BCLK_ITP#
CLK_ CLK_BCLK_ITP
UH4B
4
BG3
PERN1
4
BJ3
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY3
2
PETP2
6
BG3
PERN3
BJ3
6
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
4
AY3
PETN4
BB34
PETP4
BG3
7
PERN5
BH37
PERP5
6
AY3
PETN5
BB36
PETP5
BJ3
8
PERN6
8
BG3
PERP6
AU36
PETN6
AV36
PETP6
0
BG4
PERN7
0
BJ4
PERP7
AY4
0
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW3
8
PETN8
AY3
8
PETP8
Y40
CLKO
UT_PCIE0N
Y39
UT_PCIE0P
CLKO
J2
IECLKRQ0# / GP IO73
PC
AB49
UT_PCIE1N
CLKO
AB47
UT_PCIE1P
CLKO
M1
PC
IECLKRQ1# / GP IO18
AA48
UT_PCIE2N
CLKO
AA47
CLKO
UT_PCIE2P
V10
IECLKRQ2# / GP IO20
PC
Y37
CLKO
UT_PCIE3N
Y36
UT_PCIE3P
CLKO
A8
PC
IECLKRQ3# / GP IO25
Y43
UT_PCIE4N
CLKO
Y45
CLKO
UT_PCIE4P
L12
PC
IECLKRQ4# / GP IO26
V45
UT_PCIE5N
CLKO
V46
CLKO
UT_PCIE5P
L14
PCIECLKR Q5# / GPIO44
AB42
CLKO
UT_PEG_B_N
AB40
UT_PEG_B_P
CLKO
E6
G_B_CLKRQ# / GPIO56
PE
V40
CLKOUT_PCIE6N
V42
CLKO
UT_PCIE6P
T13
PC
IECLKRQ6# / GP IO45
V38
CLKO
UT_PCIE7N
V37
UT_PCIE7P
CLKO
K12
IECLKRQ7# / GP IO46
PC
AK14
CLKO
UT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
3
B_ALERT#
PCH_SM
SMBCL
SMBDATA
SM
L0CLK
SML
0DATA
CL_C
DATA1
CL_
RST1#
CL_
UT_DMI_N UT_DMI_P
UT_DP_N
UT_DP_P
N_DMI_N
N_DMI_P
N_GND1_N N_GND1_P
N_DOT_96P
N_SATA_N N_SATA_P
FCLK14IN
XTAL2
5_IN
AL25_OUT
LK_RCOMP
E12
H14
K
C9
A12
C8
G12
C13
E14
M16
M7
LK1
T11
P10
M10
AB37 AB38
AV22 AU22
AM12 AM13
BF18 BE18
BJ30 BG30
G24 E24
AK7 AK5
K45
H45
V47 V49
Y47
K43
F47
H47
K49
MEM_
MEM
DDR_HVREF
LA
N_SMBCLK
LA
N_SMBDATA
GPIO7
1_SMBCLK
SML
SML
1_SMBDATA
PCH_CL
PCH_CL
PCH_CL
G_A_CLKRQ#
PE
CLK_ CL
K_
CLK_ CLK_
CLK_ CLK_
CLK_
CLK_ CLK_
CLK_ CLK_
CLK_
CLK_
AL25_IN
XT XTAL25_OUT
LK_RCOMP
XC
PCI_
TCM
SIO
_14M
PCI_
TPM
JETWAY_14M
SMBCLK
_SMBDATA
_RST_PCH
4
_CLK1
_DATA1
_RST1#
CPU_DMI# CPU_DMI
CPU_DPLL# CPU_DPLL
BUF_DMI# BUF_DMI
BUF_BCLK
BUF_DOT96# BUF_DOT96
BUF_CKSSCD# BUF_CKSSCD
PCH_14M
PCI_LOOPBACK
ERT# / GPIO11
SMBAL
L0ALERT# / GPIO60
SM
SMBUSController
SMBUSController
1ALERT# / PCHHOT# / GPIO74
SML
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
L1CLK / GPIO58
SM
1DATA / GPIO75
SML
Link
Link
G_A_CLKRQ# / GPIO47
PE
CLKO
CLKO
CLKO
CLKO
CLKO CLKO
CLKI
CLKI
CLKI
CL
KIN_DOT_96N
CLKI
CLKI
CLKI
CLKIN_PCILOOPBACK
XC
CLKO
UTFLEX0 / GPIO64
CLKO
UTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
UT_PEG_A_N UT_PEG_A_P
CLKI
RE
XT
2
SMBCLK
MEM_
MEM
_SMBDATA
DDR_HVREF
N_SMBCLK 32
LA
LA
N_SMBDATA 32
S
L1_SMBCLK 43
M
L1_SMBDATA 43
SM
Intel review feed back
PC
H_CL_CLK1 37
H_CL_DATA1 37
PC
_RST1# 37
PCH_CL
CPU_DMI# 7
CLK_ CLK_
CPU_DMI 7
CLK_
CPU_DPLL# 7
CLK_
CPU_DPLL 7
PCI_LOOPBACK 17
CLK_
1 2
RH
RH
100 90.9_0402_1%~D
100 90.9_0402_1%~D
311 22_0402_5%~D4@RH311 22_0402_5%~D4@
RH
313 22_0402_5%~D
313 22_0402_5%~D
RH
RH
RH
RH
314 22_0402_5%~D
314 22_0402_5%~D
RH
315 22_0402_5%~D@RH315 22_0402_5%~D@
12
12
12
12
2
_RST_PCH 7
.3V_RUN
+3
A
A
QH5
QH5
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
3
4
B
B
QH5
QH5
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1 2
296 0_0402_5%~D@RH296 0_0402_5%~D@
RH
1 2
297 0_0402_5%~D@RH297 0_0402_5%~D@
RH
SM
L1_SMBCLK
SM
L1_SMBDATA
_RST_PCH
DDR_HVREF
4
GPIO7
SMBCLK
MEM_
MEM
_SMBDATA
B_ALERT#
PCH_SM
PE
G_A_CLKRQ#
ϴϮϱϳϳƌĞĨĞƌĞŶĐĞĚĞƐŝŐŶWhƚŽ нϯϯsͺ
LA
N_SMBCLK
LA
N_SMBDATA
BUF_DMI#
CLK_
BUF_DMI
CLK_
CLK_
BUF_BCLK
CLK_
BUF_DOT96# BUF_DOT96
CLK_
CLK_
BUF_CKSSCD#
CLK_
BUF_CKSSCD
CLK
_PCH_14M
74 10K_0402_5%~D
74 10K_0402_5%~D
RH
RH RH
RH
75 10K_0402_5%~D
75 10K_0402_5%~D
91 10K_0402_5%~D
91 10K_0402_5%~D
RH
RH
76 10K_0402_5%~D
76 10K_0402_5%~D
RH
RH
77 10K_0402_5%~D
77 10K_0402_5%~D
RH
RH
78 10K_0402_5%~D
78 10K_0402_5%~D
RH
RH
79 10K_0402_5%~D
79 10K_0402_5%~D
RH
RH
183 10K_0402_5%~D
183 10K_0402_5%~D
RH
RH
>K<dZD/Ed/KEĨŽƌ&/DĂŶĚŶĞĞĚĐůŽƐĞƚŽW,
RH
RH
309 0_0402_5%~D
309 0_0402_5%~D
12
RH99
RH99 1M_0402_5%~D
_RUN
+1.05V
CLK_PCI_TPM_CHA 35
SIO_14M 42
CLK_
PCI_TPM 34
CLK_
AY_CLK14M 35
JETW
1M_0402_5%~D
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
1
DDR_XDP_
WAN_SMBCLK 12,13,28,37
DDR_XDP_
WAN_SMBDAT 12,13,28,37
1 2
298 2.2K_0402_5%~D
298 2.2K_0402_5%~D
RH
RH
1 2
299 2.2K_0402_5%~D
299 2.2K_0402_5%~D
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
1 2 1 2
1 2
1 2 1 2
1 2 1 2
1 2
12
300 1K_0402_5%~D
300 1K_0402_5%~D
12
301 10K_0402_5%~D
301 10K_0402_5%~D
12
302 2.2K_0402_5%~D
302 2.2K_0402_5%~D
12
303 2.2K_0402_5%~D
303 2.2K_0402_5%~D
12
304 10K_0402_5%~D
304 10K_0402_5%~D
12
80 10K_0402_5%~D
80 10K_0402_5%~D
12
305 2.2K_0402_5%~D
305 2.2K_0402_5%~D
12
306 2.2K_0402_5%~D
306 2.2K_0402_5%~D
12
YH2
YH2
25MHZ_12PF_7A25000111~D
25MHZ_12PF_7A25000111~D
2
CH18
CH18
1
_0402_50V8J~D
_0402_50V8J~D
10P
10P
/PROPRIETARY
2/8)
2/8)
2/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
12
+3
.3V_ALW_PCH
+3.3V
_LAN
2
1
15 64Wedn
15 64Wedn
15 64Wedn
CH19
CH19
_0402_50V8J~D
_0402_50V8J~D
10P
10P
of
of
of
5
+3
.3V_ALW_PCH
D D
+3
.3V_RUN
C C
+1
.05V_RUN
RH
RH
RH
RH
SUSACK#42
14
B B
A A
XDP_DBRESET#7,
PM_
PCH_RSM
ME_SUS_PWR_ACK43
SIO
SIO
+3
DRAM_PWRGD7
PWROK7,42
SYS_
RESET_O
PM_
APWROK43
RST#14,43
_PWRBTN#_R7,14
_PWRBTN#43
RESENT43
AC_P
.3V_ALW_PCH
UT#43
1 2
318 10K_0402_5%~D@RH318 10K_0402_5%~D@
RH
1 2
RH
RH
144 10K_0402_5%~D
144 10K_0402_5%~D
1 2
RH
RH
142 10K_0402_5%~D
142 10K_0402_5%~D
1 2
RH
319 10K_0402_5%~D@RH319 10K_0402_5%~D@
1 2
140 10K_0402_5%~D
140 10K_0402_5%~D
RH
RH
1 2
137 8.2K_0402_5%~D
137 8.2K_0402_5%~D
RH
RH
DMI
_CTX_PRX_N06 _CTX_PRX_N16
DMI DMI
_CTX_PRX_N26 _CTX_PRX_N36
DMI
DMI
_CTX_PRX_P06 _CTX_PRX_P16
DMI DMI
_CTX_PRX_P26 _CTX_PRX_P36
DMI
_CRX_PTX_N06
DMI
_CRX_PTX_N16
DMI
_CRX_PTX_N26
DMI DMI
_CRX_PTX_N36
_CRX_PTX_P06
DMI
_CRX_PTX_P16
DMI
_CRX_PTX_P26
DMI DMI
_CRX_PTX_P36
1 2
111 49.9_0402_1%~D
111 49.9_0402_1%~D
1 2
112 750_0402_1%~D
112 750_0402_1%~D
1 2
RH
114 0_0402_5%~D@RH114 0_0402_5%~D@
1 2
116 0_0402_5%~D
116 0_0402_5%~D
RH
RH
1 2
RH
RH
117 0_0402_5%~D
117 0_0402_5%~D
1 2
118 0_0402_5%~D
118 0_0402_5%~D
RH
RH
1 2
320 0_0402_5%~D
320 0_0402_5%~D
RH
RH
1 2
120 0_0402_5%~D
120 0_0402_5%~D
RH
RH
1 2
RH
RH
121 0_0402_5%~D
121 0_0402_5%~D
1 2
RH
RH
139 8.2K_0402_5%~D
139 8.2K_0402_5%~D
5
SUS_STAT#
E
_SUS_PWR_ACK
M
PCH_PCI
SIO
PCH_RI
CLKRUN#
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI DMI DMI DMI
DMI
_COMP_R
CPY
RBIAS_
PM_
ME
1 2
122 0_0402_5%~D
122 0_0402_5%~D
RH
RH
/LPCPD#
E_WAKE#
_SLP_LAN#
#
_CTX_PRX_N0 _CTX_PRX_N1 _CTX_PRX_N2 _CTX_PRX_N3
_CTX_PRX_P0 _CTX_PRX_P1 _CTX_PRX_P2 _CTX_PRX_P3
_CRX_PTX_N0 _CRX_PTX_N1 _CRX_PTX_N2 _CRX_PTX_N3
_CRX_PTX_P0 _CRX_PTX_P1 _CRX_PTX_P2 _CRX_PTX_P3
SUSACK#_
XDP_DBRESET#
SYS_
PWROK_R
PCH_PW
PM_
APWROK_R
DRAM_PWRGD_R
PCH_RSM
RST#_R
_SUS_PWR_ACK_R
_PWRBTN#_R
_PWRBTN#_R
SIO
SIO
AC_P
RESENT
OW#
PCH_BATL
#
PCH_RI
PCH_DPW
RESET_O
_SUS_PWR_ACK_R
ME
PCH_RSM
ME
_SUS_PWR_ACK
UH4C
UH4C
BC24
0RXN
DMI
BE20
1RXN
DMI
BG18
2RXN
DMI
BG20
DMI
3RXN
BE24
DMI
0RXP
BC20
1RXP
DMI
BJ18
DMI
2RXP
BJ20
3RXP
DMI
AW24
DMI
0TXN
AW20
1TXN
DMI
BB18
DMI
2TXN
AV18
3TXN
DMI
AY24
DMI
0TXP
AY20
DMI
1TXP
AY18
2TXP
DMI
AU18
3TXP
DMI
BJ24
DMI
_ZCOMP
BG25
DMI
_IRCOMP
BH21
2RBIAS
DMI
R
C12
SUSACK#
K3
SYS_
RESET#
P12
SYS_
PWROK
ROK
L22
PWRO
L10
APWRO
B13
DRAMP
C21
RSMRST#
K16
SUSWARN#
0
E2
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BA
TLOW# / GPIO72
0
A1
RI#
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
ROK
UT#
RST#
K
WROK
4
1 2
RH
RH
113 0_0402_5%~D
113 0_0402_5%~D
1 2
321 0_0402_5%~D@RH321 0_0402_5%~D@
RH
1 2
RH
RH
323 0_0402_5%~D
323 0_0402_5%~D
1 2
322 10K_0402_5%~D
322 10K_0402_5%~D
RH
RH
1 2
RH
145 10K_0402_5%~D@RH145 10K_0402_5%~D@
K
/SUSPWRDNACK/GPIO30
4
RST#_R
PCH_RSM
SYS_
PWROK
R
SUSACK#_
FDI_
BJ14
I_RXN0
FD
I_RXN1
FD
I_RXN2
FD FD
I_RXN3 I_RXN4
FD FD
I_RXN5 I_RXN6
FD FD
I_RXN7
RXP0
FDI_ FDI_
RXP1 RXP2
FDI_ FDI_
RXP3 RXP4
FDI_ FDI_
RXP5
FDI_
FDI
FDI
FDI
FDI
FDI
FDI
DSWV
CLKRUN#
SUSCLK
S5# / GPIO63
SLP_
_LAN# / GPIO29
SLP
RXP6
FDI_
RXP7
FDI
_INT
_FSYNC0
_FSYNC1
_LSYNC0
_LSYNC1
RMEN
DPWR
WAKE#
/ GPIO32
/ GPIO61
/ GPIO62
SLP_S4#
SLP_
SLP_
SLP_SUS#
PMSY
NCH
OK
S3#
A#
DMI
DMI
SUS_STAT#
System Power Management
System Power Management
AY14 BE14 BH13 BC12 BJ12 BG10 BG9
BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DSWO
FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_
FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_ FDI_
FD
I_INT
FDI
FDI
FDI
FDI
DVREN
PCH_DPW
PCH_PCI
CLKRUN#
SUS_STAT#
SUSCLK
_SLP_S5#
SIO
SIO
_SLP_S4#
_SLP_S3#
SIO
_SLP_A#
SIO
SIO
_SLP_SUS#
_SYNC
H_PM
_SLP_LAN#
SIO
3
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: RH127 STUFFED, RH129 UNSTUFFED
Disabled
LOW: RH129 STUFFED, RH127 UNSTUFFED
CTX_PRX_N0 CTX_PRX_N1 CTX_PRX_N2 CTX_PRX_N3 CTX_PRX_N4 CTX_PRX_N5 CTX_PRX_N6 CTX_PRX_N7
CTX_PRX_P0 CTX_PRX_P1 CTX_PRX_P2 CTX_PRX_P3 CTX_PRX_P4 CTX_PRX_P5 CTX_PRX_P6 CTX_PRX_P7
_FSYNC0
_FSYNC1
_LSYNC0
_LSYNC1
RH
RH
127 330K_0402_1%~D
127 330K_0402_1%~D
129 330K_0402_1%~D@RH129 330K_0402_1%~D@
RH
ROK
E_WAKE#
/LPCPD#
1 2
1 2
PCH_DPW
PCH_PCI
CLKRUN#
T56
T56
T57
T57
T58
T58
_SLP_S5# 43
SIO
T59 PAD~DT59 PAD~D
SIO_SLP_S4# 42
T60
T60
SIO
_SLP_S3# 42
T61
T61
_SLP_A# 42,51
SIO
T62 PAD~DT62 PAD~D
SIO_SLP_SUS# 42
T63
T63
H_PM_SYNC 7
O_SLP_LAN# 32,42
SI
FDI_
CTX_PRX_N0 6 CTX_PRX_N1 6
FDI_ FDI_
CTX_PRX_N2 6 CTX_PRX_N3 6
FDI_ FDI_
CTX_PRX_N4 6
FDI_
CTX_PRX_N5 6 CTX_PRX_N6 6
FDI_ FDI_
CTX_PRX_N7 6
FDI_
CTX_PRX_P0 6 CTX_PRX_P1 6
FDI_
CTX_PRX_P2 6
FDI_
CTX_PRX_P3 6
FDI_ FDI_
CTX_PRX_P4 6
FDI_
CTX_PRX_P5 6 CTX_PRX_P6 6
FDI_
CTX_PRX_P7 6
FDI_
I_INT 6
FD
FDI
_FSYNC0 6
FDI
_FSYNC1 6
_LSYNC0 6
FDI
FDI
_LSYNC1 6
ROK 42
E_WAKE# 42
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
3
35,42,43
+3
.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
RH31
RH31
RH316
RH316
7
7
CLK_DDC2
G_
.3V_RUN
PANEL_ ENVDD_PCH
BIA_
LDDC_ LDDC_
2.37K_0402_1%~D
2.37K_0402_1%~D
LCD_ LCD_
LCD_ LCD_ LCD_
LCD_ LCD_ LCD_
2
5
4
PWM_PCH
LVD
_IBG
ACLK-_PCH ACLK+_PCH
A0-_PCH A1-_PCH A2-_PCH
A0+_PCH A1+_PCH A2+_PCH
+3
G_
DAT_DDC2
PANEL_
BKEN_PCH24
ENVDD_PCH24,
42
BIA_
PWM_PCH24
CLK_PCH24
LDDC_ LDDC_
DATA_PCH24
RH
RH
125
125
1 2
Minimum speacing of 20mils for LVD_IBG
ACLK-_PCH24
LCD_
ACLK+_PCH24
LCD_
LCD_
A0-_PCH24
LCD_
A1-_PCH24 A2-_PCH24
LCD_
LCD_
A0+_PCH24 A1+_PCH24
_CELL
LCD_ LCD_
A2+_PCH24
+RTC
13" support one channel LVDS
PCH_CRT
_BLU25
PCH_CRT PCH_CRT PCH_CRT
_HSYNC25
PCH_CRT PCH_CRT
_VSYNC25
1 2
RH
RH
131 150_0402_1%~D
131 150_0402_1%~D
1 2
RH
RH
132 150_0402_1%~D
132 150_0402_1%~D
1 2
RH133 150_0402_1%~DRH133 150_0402_1%~D
1 2
RH134 100K_0402_5%~DRH134 100K_0402_5%~D
PCH_CRT
_GRN25
PCH_CRT
_RED25
CLK_DDC2
G_ G_DAT_DDC2
RH
RH
123 20_0402_1%~D
123 20_0402_1%~D
1 2 1 2
124 20_0402_1%~D
124 20_0402_1%~D
RH
RH
RH
RH
1K_0402_0.5%~D
1K_0402_0.5%~D
_BLU
PCH_CRT
PCH_CRT
_GRN
PCH_CRT
_RED
ENVDD_PCH
HSYN VSYNC
126
126
12
2
NO CO
NNECT FOR DISCRETE
CONNE
CT FOR UMA
PCH_CRT
61
A
A
QH6
QH6
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
B
B
QH6
QH6 DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PCH_CRT
3
In
BKEN_PCH
CLK_PCH DATA_PCH
_BLU _GRN _RED
C
CRT_
IREF
2
M45
AF37 AF36
AE48 AE47
AK39 AK40
AN48 AM47 AK47
AJ48
AN47 AM49 AK49
AJ47
AF40 AF39
AH45 AH47 AF49 AF45
AH43 AH49 AF47 AF43
N48
M40
M47 M49
J47
5
P4
T40 K47
T45 P39
P49 T49
T39
T43 T42
_DDC_CLK
_DDC_DAT
PCH_CRT
PCH_CRT
_DDC_CLK 25
_DDC_DAT 25
tel request DDPB can not support eDP
UH4D
UH4D
BKLTEN
L_
VDD_EN
L_
L_BKLTCTL
DDC_CLK
L_ L_
DDC_DATA
RL_CLK
L_CT L_CT
RL_DATA
LVD
_IBG
D_VBG
LV
LV
D_VREFH
LV
D_VREFL
LV
DSA_CLK# DSA_CLK
LV
SA_DATA#0
LVD LVD
SA_DATA#1
LV
SA_DATA#2
D
SA_DATA#3
LVD
DSA_DATA0
LV LV
DSA_DATA1 DSA_DATA2
LV LV
DSA_DATA3
LV
DSB_CLK# DSB_CLK
LV
SB_DATA#0
LVD LVD
SB_DATA#1 SB_DATA#2
LVD LVD
SB_DATA#3
LV
DSB_DATA0
LV
DSB_DATA1 DSB_DATA2
LV LV
DSB_DATA3
CR
T_BLUE CRT_ CRT_
CRT_ CRT_DDC_DATA
CRT_ CRT_
DAC_IREF CRT_
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
GREEN RED
DDC_CLK
HSYNC VSYNC
IRTN
LVDS
LVDS
CRT
CRT
TVCLKINN
SDVO_
TVCLKINP
SDVO_
STALLN
SDVO_ SD
VO_STALLP
SDVO_
INTN
INTP
SDVO_
SDVO_
CTRLCLK
CTRLDATA
SDVO_
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0 DD
PB_0P DDPB_1 DD
PB_1P DDPB_
PB_2P
DD DDPB_3
PB_3P
DD
DDPC_CT
RLCLK
RLDATA
DDPC_CT
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0 DDPC_0 DDPC_1 DDPC_1 DDPC_2 DDPC_2 DDPC_3 DDPC_3
Digital Display Interface
Digital Display Interface
DDPD_CT
RLCLK
RLDATA
DDPD_CT
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0 DDPD_0 DDPD_1 DDPD_1 DDPD_2 DDPD_2P DDPD_3 DDPD_3P
DELL CONFIDENTIAL
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
Date: Sheet
Date: Sheet
Date: Sheet
1
_CTRLCLK
PCH_SDVO
PCH_SDVO
N
N
N
2
N
N P N P N P N P
N P N P N
N
AP43 AP45
AM42 AM40
AP39 AP40
P38 M39
AT4 AT4 AT4
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
P46 P42
AP4 AP4 AT3
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
M43 M36
AT45 AT4 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
_CTRLDATA
9 7 0
7 9 8
3
RH
RH
351 2.2K_0402_5%~D
351 2.2K_0402_5%~D
RH
RH
352 2.2K_0402_5%~D
352 2.2K_0402_5%~D
PC
PCH_SDVO
HDMI
TM TMDSB_ TM TMDSB_ TM TMDSB_ TM TM
PCH_DDPC_
PCH_DDPC_
DPC_PCH_ DPC_PCH_ DPC_PCH_
DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_ DPC_PCH_
PCH_DDPD_
DPD_PCH_DOCK_AUX# 27 DPD_PCH_ DPD_PCH_DOCK_HPD 41
DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_ DPD_PCH_LANE_P2 41 DPD_PCH_ DPD_PCH_LANE_P3 41
/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
3/8)
3/8)
3/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
12
12
H_SDVO_CTRLCLK 26
_CTRLDATA 26
B_PCH_HPD 26
DSB_PCH_N2 26
PCH_P2 26
DSB_PCH_N1 26
PCH_P1 26
DSB_PCH_N0 26
PCH_P0 26 DSB_PCH_CLK# 26 DSB_PCH_CLK 26
CTRLCLK 27
CTRLDATA 27
DOCK_AUX# 27 DOCK_AUX 27 DOCK_HPD 41
LANE_N0 41 LANE_P0 41 LANE_N1 41 LANE_P1 41 LANE_N2 41 LANE_P2 41 LANE_N3 41 LANE_P3 41
CTRLCLK 27
PCH_DDPD_
CTRLDATA 27
DOCK_AUX 27
LANE_N0 41 LANE_P0 41 LANE_N1 41 LANE_P1 41 LANE_N2 41
LANE_N3 41
16 64Wedn
16 64Wedn
16 64Wedn
of
of
of
+3
.3V_RUN
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
5
+3
.3V_RUN
PCI_
PCI_
_
PCI
PCI_
PCI_
LVD
S_CBL_DET#
CAM_
MIC_CBL_DET#
BT_D
PCH_G
PCI_
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1#
ET#
PIO3
GNT3#
1 2
H
H
324 8.2K_0402_5%~D
324 8.2K_0402_5%~D
R
D D
C C
R
1 2
325 8.2K_0402_5%~D
325 8.2K_0402_5%~D
RH
RH
1 2
RH
RH
326 8.2K_0402_5%~D
326 8.2K_0402_5%~D
1 2
RH
RH
329 8.2K_0402_5%~D
329 8.2K_0402_5%~D
1 2
RH
RH
327 10K_0402_5%~D
327 10K_0402_5%~D
1 2
330 10K_0402_5%~D
330 10K_0402_5%~D
RH
RH
1 2
RH
RH
331 10K_0402_5%~D
331 10K_0402_5%~D
1 2
RH
RH
328 10K_0402_5%~D
328 10K_0402_5%~D
1 2
332 10K_0402_5%~D@RH332 10K_0402_5%~D@
RH
12
3
@
3
@
RH33
RH33 1K_0402_5%~D
1K_0402_5%~D
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
Low = A16 swap
High = Default
PLTRST_
USH#34 MMI#36
PLTRST_ PLTRST_
XDP#7 LAN#32
PLTRST_ PLTRST_
EMB#29
ALL_INT28
HDD_F
335 0_0402_5%~D
335 0_0402_5%~D
RH
RH
1 2
336 0_0402_5%~D
336 0_0402_5%~D
RH
RH
1 2
RH337 0_0402_5%~DRH337 0_0402_5%~D
1 2
338 0_0402_5%~D
338 0_0402_5%~D
RH
RH
1 2
RH339 0_0402_5%~DRH339 0_0402_5%~D
1 2
CLK_PCI_504842
PCI_MEC43
CLK_
CLK_PCI_DOCK41
PCI_LOOPBACK15
CLK_
PCIE BT_D
CAM_
1 2
334 0_0402_5%~D
334 0_0402_5%~D
RH
RH
160 22_0402_5%~D
160 22_0402_5%~D
RH
RH RH
RH
102 22_0402_5%~D
102 22_0402_5%~D 103 22_0402_5%~D
103 22_0402_5%~D
RH
RH
1 2
105 22_0402_5%~D
105 22_0402_5%~D
RH
RH
4
UH4E
UH4E
BG2
6
TP1
6
BJ2
TP2
BH25
TP3
BJ1
6
TP4
BG1
6
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
RSVD
A# B# C# D#
Q1# / GPIO50 Q2# / GPIO52 Q3# / GPIO54
T1# / GPIO51 T2# / GPIO53 T3# / GPIO55
QE# / GPIO2 QF# / GPIO3 QG# / GPIO4 QH# / GPIO5
UT_PCI0
UT_PCI2 UT_PCI3 UT_PCI4
RSVD
PCI
PCI
B21
TP21
M20
TP22
6
AY1
TP23
BG4
6
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ3
2
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG3
2
TP32
AV26
TP33
BB26
TP34
AU28
TP35
0
AY3
TP36
AU26
TP37
6
AY2
TP38
AV28
TP39
0
AW3
TP40
PCI_
PIRQA# PIRQB#
PCI_
PIRQC#
PCI_
PIRQD#
PCI_
PCI_
REQ1# _MCARD2_DET#
_MCARD2_DET#37
ET#44
S_CBL_DET#24
LVD
MIC_CBL_DET#24
12 12
12
PCIE
ET#
BT_D
BBS_BI
T1
GNT3#
PCI_
LVD
S_CBL_DET#
PIO3
PCH_G
MIC_CBL_DET#
CAM_ FFS_PCH
T104PAD~D @T104PAD~D @
PCH_PL
I_5048
PC PCI_MEC
DOCK
PCI_
PCI_
LOOPBACKOUT
TRST#
_INT
K40
PIRQ
K38
PIRQ
H38
PIRQ
G38
PIRQ
C46
RE
C44
RE
E40
RE
D47
GN
E42
GN
F46
GN
G42
PIR
G40
PIR
C42
PIR
D44
PIR
K1
0
PME#
C6
PLTRST#
H49
CLKO
H43
CLKOUT_PCI1
J48
CLKO
K42
CLKO
H40
CLKO
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
USB
USB
3
RSVD1 RSVD2 RSVD3 RSVD4
RSVD5 RSVD6
RSVD7 RSVD8
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22
RSVD23 RSVD24
RSVD25
RSVD26 RSVD27
RSVD28 RSVD29
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5 USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
USBP10 USBP10 USBP11 USBP11 USBP12 USBP12 USBP13 USBP13
USBRBIAS#
USBRBIAS
OC
0# / GPIO59
OC
1# / GPIO40 OC2# / GPIO41 OC
3# / GPIO42 OC4# / GPIO43
OC5
# / GPIO9
6# / GPIO10
OC OC
7# / GPIO14
2
AY7 AV7 AU3 BG4
AT10 BC8
AU2 AT4 AT3 AT1
3
AY AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6
AV5
0
AV1
AT8
AY
5
BA2
2
AT1 BF3
C2
4
A2
4
USBP1-
C2
5
USBP1+
5
B2
USBP2-
6
C2
USBP2+
A2
6 8
K2 H2
8
USBP4-
8
E2
USBP4+
D2
8
USBP5-
8
C2
N
N P N P N P N P
USBP5+
8
A2
USBP6 USBP6+ USBP7­USBP7+ USBP8­USBP8+ USBP9­USBP9+ USBP10 USBP10 USBP11 USBP11 USBP12 USBP12
USBRBIAS
USB_O USB_O USB_O USB_O USB_OC4# USB_O USB_OC6# SIO
_EXT_SMI#
C0# C1# C2# C3#
C5#
-
­+
­+
­+
W
1 2
22.6_0402_1%~D
22.6_0402_1%~D
thin 500 mils
i
RH
RH
9
C2
9
B2 N2
8
8
M2 L30
0
K3 G3
0
E3
0 C30 A30 L32 K32 G32 E32 C32 A32
C3
3
3
B3
A14 K20 B17 C16 L16 A16 D14 C14
USBP1­USBP1+ USBP2­USBP2+
USBP4­USBP4+ USBP5­USBP5+ USBP6­USBP6+ USBP7­USBP7+ USBP8­USBP8+ USBP9­USBP9+ USBP10 USBP10 USBP11 USBP11 USBP12 USBP12
151
151
B_OC0# 40
US US
B_OC1# 40
_EXT_SMI# 43
SIO
39
----->Ri
ght Side
----->Right Side (ESATA)
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash H
----->US
CK
----->DO
----->DOCK
----->Express Card
----->Blue Tooth mera
----->Ca
- 38 + 38
- 44 + 44
- 24 + 24
39
40
40
37
37
37
37
37
37
34
34
41
41
41
41
C0#
USB_O
C1#
USB_O USB_O
C3#
USB_O
C4#
USB_O
C5# C6#
USB_O
C2#
USB_O
SIO_EXT_SMI#
RPH1
RPH1
4 5 3 6 2 7 1 8
10K
10K
4R_5%~D
4R_5%~D
_1206_8P
_1206_8P
RPH2
RPH2
4 5 3 6 2 7 1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
1 2
164 10K_0402_5%~D
164 10K_0402_5%~D
RH
RH
.3V_ALW_PCH
+3
1
.3V_RUN
+3
A A
PCH_PL
PCH_PLTRST#
TRST#7,14
5
1
B
2
A
102
102
CH
CH
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
5
UH3
UH3
P
PCH_PL
4
O
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
TRST#_EC
PCH_PLTRST#_EC 14,35,37,38,42,43
4
BBS_BI
T1
12
342
@RH342
@
RH
1K_0402_5%~D
1K_0402_5%~D
BBS_BIT1 Boot BIOS Location
*
3
SATA_SLPD (BBS_BIT0)
00
01
10
11
LPC
Reserved (NAND)
PCI
SPI
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
/PROPRIETARY
4/8)
4/8)
4/8)
-6611P
-6611P
-6611P
1
17 64Wedn
17 64Wedn
17 64Wedn
of
of
of
Boot BIOS Strap
5
.3V_ALW_PCH
+3
1 2
RH
RH
355 4.7K_0402_5%~D
355 4.7K_0402_5%~D
1 2
353 1K_0402_5%~D@RH353 1K_0402_5%~D@
RH
D D
ENABLED - HIGH (RH238 UNSTUFFED) DEFAULT DISABLED - LOW (RH238 STUFFED)
+3
.3V_ALW_PCH
PLL ON DIE VR ENABLE
1 2
177 10K_0402_5%~D
177 10K_0402_5%~D
RH
RH
SLP_
SIO
_EXT_WAKE#
ME_CSW_DEV#
SIO
_EXT_SCI#
_EXT_SCI#43
SIO
PM_
RH
RH
SI
IO_L
LED
B_DET#31
SIO
_EXT_WAKE#42
LANPHY_ENABLE32
Integrated Clock Chip Enable
ICC_EN#
C C
HIGH: DISABLED [DEFAULT] LOW: ENABLED
+3
.3V_ALW_PCH
1 2
354 1K_0402_5%~D
354 1K_0402_5%~D
RH
RH
PCH_G
PIO15
PCIE
_MCARD1_DET#37
EXPRCRD_DET
SLP_
ME_CSW_DEV#42
USB_M
M
E
CARD1_DET#37
GPIO15
Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
PCH_G
5
PCH_G
PCH_G
PCH_G
PCH_G
TEM
P_ALERT#
ME
DIA_DET#
GPIO17
IO_LOOP#
B_DET#
LED
KB_DET#
PIO37
PIO36
PIO36
PIO37
PIO16
Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad.
1 2
174 10K_0402_5%~D@RH174 10K_0402_5%~D@
RH
B B
1 2
175 10K_0402_5%~D@RH175 10K_0402_5%~D@
RH
+3.3V_RUN
RH
RH
RH265 10K_0402_5%~DRH265 10K_0402_5%~D
A A
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
RH
RH
RH
RH
RH
RH
+3
.3V_ALW_PCH
12
171 10K_0402_5%~D@RH171 10K_0402_5%~D@
12
173 1K_0402_1%~D@RH173 1K_0402_1%~D@
12
12
1 2
1 2
269 8.2K_0402_5%~D
269 8.2K_0402_5%~D
1 2
163 10K_0402_5%~D
163 10K_0402_5%~D
1 2
273 10K_0402_5%~D
273 10K_0402_5%~D
12
170 10K_0402_5%~D
170 10K_0402_5%~D
RH
RH
TEMP
FFS_IN
_ALERT#42
KB_DET#44
4
1 2
263 10K_0402_5%~D
263 10K_0402_5%~D
O
_EXT_SCI#
1 2
RH
RH
259 0_0402_5%~D
259 0_0402_5%~D
PCH_G
IO_L
#38
OOP#
B_DET#
LED
_EXT_WAKE#
SIO
_LANPHY_ENABLE
PM
PCH_G
PCH_G
GPIO1
ME
DIA_DET#
IE_MCARD1_DET#
PC
EXPRCRD_DET
ME_CSW_DEV#
SLP_
PCH_G
USB_M
PCH_G
PCH_G
TPM_
TPM_
FFS_IN
P_ALERT#
TEM
KB_DET#
TPM_ID0
4
OOP#31
DIA_DET#31
T228
+3
.3V_RUN
UH4F
SI
PIO1
PIO15
PIO16
7
PIO34
CARD1_DET#
PIO36
PIO37
ID0
ID1
T2
VSS_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
O
_EXT_SCI#_R
#
1
NCTF_
2
3
4
5
6
7
8
9
10
11
12
13
14
UH4F
T7
# / GPIO0
BMBUSY
A42
TA
CH1 / GPIO1
H36
TA
CH2 / GPIO6
E38
CH3 / GPIO7
TA
C1
0
GPIO8
C4
N_PHY_PWR_CTRL / GPIO12
LA
G2
5
GPIO1
U2
P / GPIO16
SATA4G
D40
CH0 / GPIO17
TA
T5
SC
LOCK / GPIO22
E8
IO24 / MEM_LED
GP
E16
7
GPIO2
P8
8
GPIO2
K1
P_PCI# / GPIO34
ST
K4
5
GPIO3
V8
SATA2G
P / GPIO36
M5
SATA3G
P / GPIO37
N2
SL
OAD / GPIO38
M3
SDATAOUT0
V13
SDATAOUT1
V3
P / GPIO49
SATA5G
D6
7
GPIO5
A4
VSS_NCTF_
A44
VSS_NCTF_
A45
VSS_NCTF_
A46
VSS_NCTF_
A5
VSS_NCTF_
A6
VSS_NCTF_
B3
VSS_NCTF_
B47
VSS_NCTF_
BD1
VSS_NCTF_
BD49
VSS_NCTF_
BE1
VSS_NCTF_
BE49
VSS_NCTF_
BF1
VSS_NCTF_
BF49
VSS_NCTF_14
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
EĞĞĚƚŽŵŽĚŝĨLJĨŽůůŽǁdWDKDĐŽŶĨŝŐ
+3.3V_RUN
1 2
1 2
1@
1@
RH267
RH267 10K_0402_5%~D
10K_0402_5%~D
2@
2@
0
0
RH27
RH27 10K_0402_5%~D
10K_0402_5%~D
+3.3V_RUN
TPM_ID1
/ GPIO39
/ GPIO48
1
2
3
4
5
6
7
8
9
10
11
12
13
12
12
GPIO
GPIO
3@
3@
RH268
RH268 20K_0402_5%~D
20K_0402_5%~D
4@
4@
271
271
RH
RH
2.2K_0402_5%~D
2.2K_0402_5%~D
3
CH4 / GPIO68
TA
TA
CH5 / GPIO69
TA
CH6 / GPIO70
CH7 / GPIO71
TA
ATE
A20G
PECI
RCIN#
PWRGD
PROC
THRM
TRIP#
IT3_3V#
IN
TVS
DF_
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
15
VSS_NCTF_
16
VSS_NCTF_
17
VSS_NCTF_
VSS_
18
NCTF_
19
VSS_NCTF_
VSS_NCTF_
20
VSS_NCTF_
21
VSS_NCTF_
22
23
VSS_NCTF_
NCTF
NCTF
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_32
Chi
24
25
26
27
28
29
30
31
na TPM
No TPM, No China TPM
USH2.0
3
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK1
AH1
AK1
P3
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
2
NTACTL
ESS_DET#
CO
PCH_G
PIO69
PCIE
_MCARD3_DET#
CARD2_DET#
USB_M
SIO
_A20GATE
H_PECI
SIO
_RCIN#
H_CPUPW
PCH_T
HRMTRIP#_R
IT3_3V#
IN
TVS
DF_
1
0
0
NC_1
7
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_
NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
VSS_NCTF_
_A20GATE 43
SIO
_R
1 2
RH
159 0_0402_5%~D@RH159 0_0402_5%~D@
SIO
RGD
H_CPUPW
@
15
16
17
18
19
20
21
22
23
24
Layout note: Trace wide 10mil & length 30mil
25
All NCTF pins should have thick
26
traces at 45°from the pad.
27
28
29
30
31
32
ESS_DET# 34
CONTACTL
IE_MCARD3_DET# 37
PC
USB_M
CARD2_DET# 37
_RCIN# 43
RGD 7
T106PAD~D@T106PAD~D
T108PAD~D @T108PAD~D @
1 2
RH
RH
261 0_0402_5%~D
261 0_0402_5%~D
262 56_0402_5%~D
262 56_0402_5%~D
RH
RH
1
CH97
CH97
0.
0.
1U_0402_16V4Z~D
1U_0402_16V4Z~D
2
+1
.05V_RUN_VTT
12
PECI_
H_PECI
EC 43
+V
7
CCDFTERM
2.2K_0402_5%~D
2.2K_0402_5%~D
RH149
RH149
CONTACTL
_A20GATE
SIO
_RCIN#
SIO
PCH_G
PCH_G
EXPRCRD_DET
GPIO27 (EXPRCRD_DET#)
ĞĨĂƵůƚсŽŶŽƚĐŽŶŶĞĐƚ;ĨůŽĂƚŝŶŐͿ ,ŝŐŚ;ϭͿсŶĂďůĞƐƚŚĞŝŶƚĞƌŶĂůsĐĐsZDƚŽŚĂǀĞĂĐůĞĂŶ ƐƵƉƉůLJĨŽƌĂŶĂůŽŐƌĂŝůƐEŽŶĞĞĚƚŽƵƐĞ ŽŶͲďŽĂƌĚĨŝůƚĞƌĐŝƌĐƵŝƚ >Žǁ;ϬͿсŝƐĂďůĞƐƚŚĞsĐĐsZDEĞĞĚƚŽƵƐĞŽŶͲďŽĂƌĚ ĨŝůƚĞƌĐŝƌĐƵŝƚƐĨŽƌĂŶĂůŽŐƌĂŝůƐ
PCH_G
12
150 0_0402_5%~D
150 0_0402_5%~D
RH
RH
ESS_DET#
PIO1
PIO34
PIO69
1 2
1
1 2
256 10K_0402_1%~D
256 10K_0402_1%~D
RH
RH
RH
RH
158 10K_0402_5%~D
158 10K_0402_5%~D
RH
RH
203 10K_0402_5%~D
203 10K_0402_5%~D
RH
RH
254 10K_0402_5%~D
254 10K_0402_5%~D
1 2
165 10K_0402_5%~D
165 10K_0402_5%~D
RH
RH
#
1 2
241 10K_0402_5%~D
241 10K_0402_5%~D
RH
RH
1 2
RH
RH
260 1.5K_0402_1%~D
260 1.5K_0402_1%~D
DF_TVSDF_TVS_R
.3V_RUN
+3
12
12
12
DMI & FDI Termination Voltage
0
0
0
1
ID1TPM_ID0
TPM_
11
NV_CLE
DELL CONFIDENTIAL
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
Date: Sheet
Date: Sheet
2
Date: Sheet
Set to Vss when LOW
Set to Vcc when HIGH
/PROPRIETARY
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
o
5/8)
5/8)
5/8)
PCH (
PCH (
PCH (
LA
LA
LA
-6611P
-6611P
-6611P
1
18 64Wedn
18 64Wedn
18 64Wedn
of
of
of
5
+1.05V
_RUN
10U
10U
_0805_4VAM~D
_0805_4VAM~D
1
D D
_RUN
+1.05V
50 mA
+3
.3V_RUN
+1.05V
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH51
CH51
2
C C
B B
@
@
_RUN
1
2
+1.05V
RH24
RH24
10U
10U
_0805_4VAM~D
_0805_4VAM~D
2
1 2
7
7
1
CH44
CH44
2
_RUN
RH
195 0.022_0805_1%@RH195 0.022_0805_1%@
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+1
4.555A
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH32
CH32
CH30
CH30
1
2
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
1U
1U
1
_0402_6.3V6K~D
_0402_6.3V6K~D
CH45
CH45
CH46
CH46
2
_+1.5V_1.8V_RUN
+1.05V
1 2
+1.05V
_RUN
.05V_RUN_VTT
1U
1U
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
_0402_6.3V6K~D
CH33
CH33
CH31
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+1.05V
CH47
CH47
1
2
_RUN
1
2
1
2
@
@
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
+VC
CH31
+V
CH40
CH40
_0805_4VAM~D
_0805_4VAM~D
10U
10U
CH48
CH48
CAPLL_FDI
1
2
1
2
CCAPLLEXP
4
UH4G
UH4G
AA23 AC23 AD21 AD23
AF21
AF23 AG21 AG23 AG24 AG26 AG27 AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
1]
VCCCORE[ VCCCORE[
2] 3]
VCCCORE[ VCCCORE[
4]
RE[
5]
VCCCO
6]
VCCCORE[ VCCCORE[
7] 8]
VCCCORE[ VCCCORE[
9] 10]
VCCCORE[
11]
VCCCORE[ VCCCORE[
12]
VCCCORE[
13]
VCCCORE[
14] 15]
VCCCORE[
16]
VCCCORE[ VCCCORE[
17]
VCCIO
[28]
EXP
VCCAPLL
[15]
VCCIO
[16]
VCCIO
[17]
VCCIO
[18]
VCCIO
[19]
VCCIO
[20]
VCCIO
[21]
VCCIO
VCCIO
[22]
VCCIO
[23]
VCCIO
[24]
[25]
VCCIO
VCCIO
[26]
C3_3[3]
VC
2]
VCCVRM[
VccA
FDIPLL
VCCIO
[27]
[2]
VCCDMI
B
B
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
POWER
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
VCCTX_
VCCTX_
VCCTX_
VCCTX_
DMI
DMI
VCCDFT
VCCDFT
VCCDFT
VCCDFT
DFT / SPI HVCMOS
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALV
VSSALVDS
LVDS[1]
LVDS[2]
LVDS[3]
LVDS[4]
VC
C3_3[6]
VC
C3_3[7]
VCCVRM[
VCCDMI
VCCCLKDM
ERM[1]
ERM[2]
ERM[3]
ERM[4]
VCCSPI
3
.3V_RUN
+3
LH1
+V
CCADAC
0.
0.
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
01U_0402_16V7K~D
U48
U47
AK36
DS
7
AK3
AM37
AM38
AP36
AP37
V33
V34
AT16
3]
AT20
[1]
AB36
I
AG16
AG17
AJ16
AJ17
V1
01U_0402_16V7K~D
1
1
CH34
CH34
2
2
+1
.8V_RUN_LVDS
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH
CH
1
103
103
2
1
CH43
CH43
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
+1.05V
CH
CH
49 1U_0402_6.3V6K~D
49 1U_0402_6.3V6K~D
1 2
+1
.05V_RUN_CLKDMI
10U_0603_4VAM~D
CH50
CH50
1
2
1
CH52
CH52
0.
0.
2
1
2
10U_0603_4VAM~D
@
@
1
CH
CH 106
106
2
1U_0402_10V7K~D
1U_0402_10V7K~D
+3.3
CH54
CH54
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH35
CH35
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
2
+3
_+1.5V_1.8V_RUN
100N
100N
CCDFTERM
+V
V_M
LH1
12
LM18PG181SN1_0603~D
LM18PG181SN1_0603~D
B
B
10U
10U
_0805_4VAM~D
_0805_4VAM~D
1
CH36
CH36
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH
CH
CH
CH
1
104
104
105
105
2
.3V_RUN
1 2
H_HK1608R10J-T_5%_0603~D
H_HK1608R10J-T_5%_0603~D
1 2
RH
276 0_0805_5%~D@RH276 0_0805_5%~D@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
.3V_RUN
+3
100N
100N
H_HK1608R10J-T_5%_0603~D
H_HK1608R10J-T_5%_0603~D
LH9
LH9
2
2
PJP5
PJP5
LH8
LH8
12
+1
.05V_RUN_VTT
_RUN
+1.05V
+3
.3V_RUN
.8V_RUN
+1
+1
2
.8V_RUN
1
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax Current (A)
0.001
5
5
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
1.05VccIO 2.925
VccASW
VccSPI
VccDSW3_3 0.003
1.05
3.3
3.3
1.01
0.020
1.8 0.19+VCCDFTERM
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
VccVRM 1.8 / 1.5
0.119
0.01
0.16
1.05VccClkDMI 0.02
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.06
+1.05V
_+1.5V_1.8V_RUN
+1.05V_RUN
1
+
+
@
@
CH41
CH41
_D2_2VM_R6M~D
_D2_2VM_R6M~D
330U
330U
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
+
+
2
@
@
CH42
CH42
_D2_2VM_R6M~D
_D2_2VM_R6M~D
330U
330U
2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
PCH (
PCH (
PCH (
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
LA
/PROPRIETARY
6/8)
6/8)
6/8)
-6611P
-6611P
-6611P
1
19 64Wedn
19 64Wedn
19 64Wedn
of
of
of
_RUN
/ŶƚĞůƌĞǀŝĞǁĨĞĞĚďĂĐŬ
12
197 0_0603_5%~D
197 0_0603_5%~D
RH
RH
12
198 0_0603_5%~D@RH198 0_0603_5%~D@
RH
RH199 0_0603_5%~D@RH199 0_0603_5%~D@
12
4
.5V_RUN
+1
+1
.8V_RUN
+1.05V
A A
5
5
_RUN
+1.05V
.3V_ALW_PCH
+3
+3
.3V_ALW2
D D
.05V_RUN
+1
.3V_RUN
+3
LH4
LH4
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
C C
+1
.05V_RUN_VCCA_A_DPL
LH6
LH6
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
.05V_RUN
+1
B B
+1.05V_M
A A
1 2
1 2
LH7
LH7
10U
10U
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
1 2
RH
248 0.022_0805_1%@RH248 0.022_0805_1%@
1 2
RH
RH
201 0_0402_5%~D
201 0_0402_5%~D
1 2
H
H
253 0_0402_5%~D@
253 0_0402_5%~D@
R
R
@
@
LH3
LH3
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
+3
.3V_RUN_VCC_CLKF33
1
CH73
CH73
2
1 2
279 0_0805_5%~D@RH279 0_0805_5%~D@
RH
220U
220U
1
_B2_2.5VM_R35M~D
_B2_2.5VM_R35M~D
CH94
CH94
+
+
2
_M_VCCSUS
+1.05V
+1
5
@
@
10U
10U
CH5
CH5
_0805_6.3V6M~D
_0805_6.3V6M~D
8
8
1
CH74
CH74
2
_0402_6.3V6K~D
_0402_6.3V6K~D
_0805_6.3V6M~D
_0805_6.3V6M~D
1U
1U
10U
10U
+1
.05V_RUN_VCCA_B_DPL
.05V_RUN_VCCA_A_DPL
+1
.05V_RUN_VCCA_B_DPL
+1
220U
220U
1U
1U
1
_0402_6.3V6K~D
_0402_6.3V6K~D
_B2_2.5VM_R35M~D
_B2_2.5VM_R35M~D
CH92
CH92
1
+
+
2
2
+1.05V
.05V_RUN_VTT
4.
4.
1
7U_0603_6.3V6K~D
7U_0603_6.3V6K~D
CH85
CH85
2
1
.05V_RUN
+1
2
+1.05V
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH95
CH95
CH93
CH93
1
2
_RUN
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH96
CH96
1
2
0.
0.
0.
0.
1
1
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
CH86
CH86
2
2
CH87
CH87
_M
1
2
1 2
RH
200 0.022_0805_1%@RH200 0.022_0805_1%@
1
CH5
CH5
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH67
CH67
1
2
1
2
CH79
CH79 1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
5
5
CH57
CH57
@
@
22U
22U
_0805_6.3VAM~D
_0805_6.3VAM~D
CH64
CH64
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH68
CH68
1
2
CH78
CH78
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
CH81
CH81
1 2
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
CH84
CH84
1
2
4
1
2
1
@
@
CH61
CH61
1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
2
22U
22U
_0805_6.3VAM~D
_0805_6.3VAM~D
CH65
CH65
1
2
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
CH69
CH69
1
2
+1.05V
+1
.05V_RUN_VCCA_A_DPL
+1
.05V_RUN_VCCA_B_DPL
+VCCSST
+1
.05V_M_VCCSUS
1
@
@
CH83
CH83
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
_CELL
+RTC
1
2
4
CCACLK
+V
CCDSW3_3
+V
+P
CH_VCCDSW
+3
.3V_RUN_VCC_CLKF33
CCAPLL_CPY_PCH
+V
CCSUS1
+V
+V
CCRTCEXT
_+1.5V_1.8V_RUN
0.
0.
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH89
CH89
CH88
CH88
2
3
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
1
CH56
CH56
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH59
CH59
2
1
CH70
CH70
_0603_10V6K~D
_0603_10V6K~D
1U
1U
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH76
CH76
2
+1.05V
POWER
C3_3[5]
[14]
[7]
POWER
_3
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
3
VC
VC
VC
CSUS3_3[10]
VC
VC
VC
VC
VC
VC
VC
VCCAPLL
VCCASW[
VCCASW[
VCCASW[21]
VCCSUSHDA
DMI2
]
1]
2]
3]
4]
5]
6]
7]
8]
9]
10]
11]
12]
13]
14]
Clock and Miscellaneous
Clock and Miscellaneous
15]
16]
17]
[
18]
19]
20]
4]
A
B
FCLKN[1] FCLKN[2] FCLKN[3]
] ]
C_IO
CPURTC
CPURTC
VCCIO
O
VCCI
VCCIO
VCCIO
VCCIO
CSUS3_3[7]
CSUS3_3[8]
CSUS3_3[9]
CSUS3_3[6]
VCCIO
V5REF_
DCPSUS[4
CSUS3_3[1]
V5REF
CSUS3_3[2]
CSUS3_3[3]
CSUS3_3[4]
CSUS3_3[5]
C3_3[1]
VC
C3_3[8]
VC
C3_3[4]
VC
VC
C3_3[2]
VCCIO
VCCIO
VCCIO
VCCIO
SATA
VCCVRM[
VCCIO
VCCIO
VCCIO
SUS
N26
[29]
P26
[30]
P28
[31]
T27
[32]
T29
[33]
T23
T24
V23
V24
P24
T26
[34]
+P
CH_V5REF_SUS
M26
+V
CCA_USBSUS
AN23
]
AN24
CH_V5REF_RUN
+P
4
P3
N20
N22
P20
P22
AA16
W16
T34
.3V_RUN
+3
AJ2
AF13
[5]
AH13
[12]
AH14
[13]
AF14
[6]
AK1
AF11
1]
AC16
[2]
AC17
[3]
AD17
[4]
T21
22]
V21
23]
T19
P32
+1.05V
+1.05V
_M
.3V_ALW_PCH
+3
_+1.5V_1.8V_RUN
1
CH91
CH91
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
UH4J
UH4J
9
AD4
VCCACLK
T16
VCCDSW3
V1
2
DCPSUSBYP
T38
VC
BH23
VCCAPLL
AL29
VCCIO
AL24
DCPSUS[3
AA19
VCCASW[
AA21
VCCASW[
AA24
VCCASW[
AA26
VCCASW[
AA27
VCCASW[
AA29
VCCASW[
AA31
VCCASW[
AC26
VCCASW[
AC27
VCCASW[
AC29
VCCASW[
AC31
VCCASW[
AD29
VCCASW[
AD31
VCCASW[
W21
VCCASW[
W23
VCCASW[
W24
VCCASW[
W26
VCCASW
W29
VCCASW[
W31
VCCASW[
W33
VCCASW[
N1
6
DCPRTC
Y49
VCCVRM[
BD47
VCCADPLL
BF47
VCCADPLL
AF17
VCCIO
AF33
VCCDIF
AF34
VCCDIF
AG34
VCCDIF
AG3
3
VCCSSC
V16
DCPSST
T17
DCPSUS[1
V19
DCPSUS[2
BJ8
V_PRO
2
A2
VCCRTC
D82CPMS-QMVY-A1_FCBGA989~D
D82CPMS-QMVY-A1_FCBGA989~D
B
B
1U
1U _0402_6.3V6K~D
_0402_6.3V6K~D
1
CH90
CH90
2
_RUN
.3V_ALW_PCH
+3
+
.3V_ALW_PCH
3
+3
.3V_RUN
+1.05V
2
0.
0. 1U_0402_10V7K~D
1U_0402_10V7K~D
1
CH60
CH60
2
1
CH66
CH66
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
1
CH72
CH72
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
2
1
CH75
CH75
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
2
_RUN
1
CH77
CH77 1U
1U
_0402_6.3V6K~D
_0402_6.3V6K~D
2
+V
CCSATAPLL
1
CH80
CH80 10U
10U
_0805_6.3V6M~D
_0805_6.3V6M~D
2
1
CH82
CH82
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
2
2
.3V_ALW_PCH
+3
@
@
+1.05V
.3V_ALW_PCH
+3
.3V_RUN
+3
+1.05V
1
2
2
RH20
RH20
0_0402_5%~D
0_0402_5%~D
1 2
D
D
1 3
QH4
QH4
@
@
+3
RB
RB
751S40T1_SOD523-2~D
751S40T1_SOD523-2~D
CH_V5REF_SUS
+P
0.
0.
1U_0402_10V7K~D
1U_0402_10V7K~D
CCA_USBSUS
+V
RB
RB
751S40T1_SOD523-2~D
751S40T1_SOD523-2~D
+P
CH_V5REF_RUN
1U
1U
_0603_10V6K~D
_0603_10V6K~D
G
G
2
.3V_ALW_PCH+5V_ALW_PCH
+1.05V
_RUN
_RUN
V_ALW
+5
S
S
SM3K7002FU_SC70-3~D
SM3K7002FU_SC70-3~D
_ENABLE45
ALW
@
@
LH5
LH5
H_LBR2012T100M_20%~D
H_LBR2012T100M_20%~D
10U
10U
1 2
DELL CONFIDENTIAL
C
C
C
mpal Electronics, Inc.
mpal Electronics, Inc.
mpal Electronics, Inc.
o
o
Title
Tit
Tit
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
o
LA
LA
LA
esday, Januar y 26, 2011
esday, Januar y 26, 2011
esday, Januar y 26, 2011
+5
S
S
1
CH98
CH98
2
1U_0402_10V7K~D
1U_0402_10V7K~D
0.
0.
21
DH2
DH2
1
CH63
CH63
2
1
@
@
2
+3
.3V_RUN+5V_RUN
21
DH3
DH3
1
CH71
CH71
2
_RUN
7/8)
7/8)
7/8)
PCH (
PCH (
PCH (
-6611P
-6611P
-6611P
1
V_ALW_PCH
12
12
CRB 0.7 10ohm 0603 trace width 20mil.
CH62
CH62
_0402_6.3V6K~D
_0402_6.3V6K~D
1U
1U
12
/PROPRIETARY
278
278 RH
RH
@
@
20K_0402_5%~D
20K_0402_5%~D
RH
RH
208
208
10_0402_5%~D
10_0402_5%~D
RH
RH
213
213
10_0402_5%~D
10_0402_5%~D
20 64Wedn
20 64Wedn
20 64Wedn
of
of
of
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