COMPAL LA-6601P Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-6601P (DAA00002000)

TBD

PAR00

Compal Confidential

2 2

Voyager

Schematic Document

Rev: 1.0(A00)

2010-11-30

3 3

@ : Nopop Component

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-6601P

1 63Tuesday, November 30, 2010

E

1.0

A

Compal Confidential

Project Code : PAR00 File Name : LA-6601P

1 1

2 2

3 3

4 4

LVDS Panel Conn

P.26 P.26 P.25

eDP Panel Conn

P.24

mini DP Conn

P.29

HDMI 1.4

P.28 P.28P.28

Conn

SIM Card

P.38

Wireless Display DMC (Full)

Port 2

Port 4

Card Reader

Card Reader/B

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

P.48~P57

LVDS MUX

DP

Rediver

CRT Conn

HDMI Rediver

8 in 1 Socket

P.15

P.46

P.47

A

LVDS MUX

DisplayPort

DP MUXDP MUX

P.24 P.23

DP MUX

P.29

CRT MUX

P.27 P.27

HDMI MUX

P.38

USB 3.0/2.0 Host Ctrl.

USB 3.0 /2.0 Combo Conns x 2

LVDS

P.29

P.30

Port 6

P.39

B

eDP

DP (DIS)

LVDS (DIS)

LVDS

DP (DIS)

DP

CRT (DIS)

CRT

HDMI (DIS) HDMI

Port 1

LAN(GbE)

AR8151

RJ45

B

LVDS MUX

LVDS

LVDS to DP SW

STDP4028

P.33

ENE 3810

HDMI to LVDS SW

P.25

P.32

DisplayPort

LVDS

DisplayPort

CRT

HDMI

Port 3

Mini Card-1 WLAN (Half)

P.38

USB Port 4

P.44

Touch Pad

C

HDMI 1.3 input Conn

STDP6038

P.31

Sandy Bridge

PEG x16 (DIS)

MXM III Conn.

P.14

LVDS

DisplayPortMini Card -2

CRT

HDMI

PCIE BUS

SPI

SPI ROM

P.15

ENE KB930

PS2 SPI

Int.KBD

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

2C 35W 4C 45W

rPGA 988 Socket

(UMA)

100MHz

2.7GT/s

Cougar Point

BGA 989 Balls

BIOS ROM

Intel

Processor

Intel

PCH

LPC Bus

Media / Mode Buttons

P.44P.42 P.42P.46

P.4~9

DMI x4 gen 2FDI x8

100MHz 5GB/s

P15~22

P.44

D

Free Fall Sensor

(DDRIII) Memory Bus

Dual Channel

1.5V DDRIII 1066/1333 MHz

SATA3.0

SATA2.0

USB2.0

HD Audio

D

E

P.36 P.45 P.5

Fan Control

CPU XDP Conn.

204pin DDRIII SO-DIMM x4

BANK 0, 1, 2, 3 P.10~13

SATA Port 0

SATA HDD-1 Conn.

P.36

SATA

SATA Port 1

SATA Port 2

SATA Port 4

USB Port 9

USB Port 7

USB Port 0

USB Port 1

USB Port 2 USB Port 3

USB Port 6

USB Port 8

Rediver

P.36

SATA ODD Conn.

ESATA Redriver

3D IR

USB 2.0 Conn x 2 dual-stack

Digital Camera ( LVDS port3/eDP port2 )

AlienFX/ELC

BT 2.1 /BT 3.0

SATA HDD-2 Conn.

P.37

USB / eSATA Conn.

USB Charger

P.46

P.40

P.41

P.38

P.26,24

Array Mics x2

Audio Codec

IDT 92HD73

P.34

S/PIDF Jack x1

MIC Jack x1

Amplifier x2 HeadPhone Jack x2 MAX9724

Amplifier x1 MAX9736

P.34

Int. Speaker

P.35

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-6601P

E

5W x2

2 63Tuesday, November 30, 2010

P.35

P.36

P.37

P.34

P.35

P.34

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5%

100K +/- 5% 200K +/- 5%

NC

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

max

EC AD3

0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

A

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

0.4

1.0

USB PORT#

0

1

2

3

4

DESTINATION

JUSB1

JUSB2

eDP CAMERA

LVDS CAMERA

JMINI1 (WLAN)

SMBUS Control Table

SOURCE

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMBCLK PCH_SMBDATA PCH

MEM_SMBCLK MEM_SMBDATA

KB930

PCH

MIINI1 BATT SODIMM

X X

V V

MINI2

V

X X

X

X X

EXPRESS CARD

X

X X X

V

X X

X

V

MXM

V

X

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

USB

DESTINATION

PCH_LOOPBACK

EC

None

5

6

7

8

9 JESATA

10

11

12

13

1 1

DESTINATION

HDD1

HDD2

ODD

NA

ESATA

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

DESTINATIONDIFFERENTIAL

None

10/100/1G LAN

MINI CARD-2 DMC

MINI CARD-1 WLAN

CARD READER

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

CLK_14M

None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

JMINI2 (DMC)

AlienFX/ELC

IR SENSOR

Bluetooth

None

DESTINATION

10/100/1G LAN

MINI CARD-2 DMC

MINI CARD-1 WLAN

CARD READER

None

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_A

None

USB 3.0

None

MXM

Symbol Note :

: means Digital Ground

: means Analog Ground

SATA5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

None

Lane 6

Lane 7

Lane 8

USB 3.0

None

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-6601P

1.0

3 63Tuesday, November 30, 2010

1.0

5

JCPU1A

DMI_CRX_PTX_N017 DMI_CRX_PTX_N117 DMI_CRX_PTX_N217

D D

C C

B B

DMI_CRX_PTX_N317

DMI_CRX_PTX_P017 DMI_CRX_PTX_P117 DMI_CRX_PTX_P217 DMI_CRX_PTX_P317

DMI_CTX_PRX_N017 DMI_CTX_PRX_N117 DMI_CTX_PRX_N217 DMI_CTX_PRX_N317

DMI_CTX_PRX_P017 DMI_CTX_PRX_P117 DMI_CTX_PRX_P217 DMI_CTX_PRX_P317

FDI_CTX_PRX_N017 FDI_CTX_PRX_N117 FDI_CTX_PRX_N217 FDI_CTX_PRX_N317 FDI_CTX_PRX_N417 FDI_CTX_PRX_N517 FDI_CTX_PRX_N617 FDI_CTX_PRX_N717

FDI_CTX_PRX_P017 FDI_CTX_PRX_P117 FDI_CTX_PRX_P217 FDI_CTX_PRX_P317 FDI_CTX_PRX_P417 FDI_CTX_PRX_P517 FDI_CTX_PRX_P617 FDI_CTX_PRX_P717

FDI_FSYNC017 FDI_FSYNC117

FDI_INT17

FDI_LSYNC017 FDI_LSYNC117

EDP_AUXP23 EDP_AUXN23

EDP_TX0P23 EDP_TX1P23 EDP_TX2P23 EDP_TX3P23

EDP_TX0N23 EDP_TX1N23 EDP_TX2N23 EDP_TX3N23

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

EDP_COM

EDP_HPD#_Q

EDP_AUXP EDP_AUXN

EDP_TX0P EDP_TX1P EDP_TX2P EDP_TX3P

EDP_TX0N EDP_TX1N EDP_TX2N EDP_TX3N

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev1p0

CONN@

4

PEG_COMP

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

PEG_GTX_C_HRX_N0

K33

PEG_GTX_C_HRX_N1

M35

PEG_GTX_C_HRX_N2

L34

PEG_GTX_C_HRX_N3

J35

PEG_GTX_C_HRX_N4

J32

PEG_GTX_C_HRX_N5

H34

PEG_GTX_C_HRX_N6

H31

PEG_GTX_C_HRX_N7

G33

PEG_GTX_C_HRX_N8

G30

PEG_GTX_C_HRX_N9

F35

PEG_GTX_C_HRX_N10

E34

PEG_GTX_C_HRX_N11

E32

PEG_GTX_C_HRX_N12

D33

PEG_GTX_C_HRX_N13

D31

PEG_GTX_C_HRX_N14

B33

PEG_GTX_C_HRX_N15

C32

PEG_GTX_C_HRX_P0

J33

PEG_GTX_C_HRX_P1

L35

PEG_GTX_C_HRX_P2

K34

PEG_GTX_C_HRX_P3

H35

PEG_GTX_C_HRX_P4

H32

PEG_GTX_C_HRX_P5

G34

PEG_GTX_C_HRX_P6

G31

PEG_GTX_C_HRX_P7

F33

PEG_GTX_C_HRX_P8

F30

PEG_GTX_C_HRX_P9

E35

PEG_GTX_C_HRX_P10

E33

PEG_GTX_C_HRX_P11

F32

PEG_GTX_C_HRX_P12

D34

PEG_GTX_C_HRX_P13

E31

PEG_GTX_C_HRX_P14

C33

PEG_GTX_C_HRX_P15

B32

PEG_HTX_GRX_N0

M29

PEG_HTX_GRX_N1

M32

PEG_HTX_GRX_N2

M31

PEG_HTX_GRX_N3

L32

PEG_HTX_GRX_N4

L29

PEG_HTX_GRX_N5

K31

PEG_HTX_GRX_N6

K28

PEG_HTX_GRX_N7

J30

PEG_HTX_GRX_N8

J28

PEG_HTX_GRX_N9

H29

PEG_HTX_GRX_N10

G27

PEG_HTX_GRX_N11

E29

PEG_HTX_GRX_N12

F27

PEG_HTX_GRX_N13

D28

PEG_HTX_GRX_N14

F26

PEG_HTX_GRX_N15

E25

PEG_HTX_GRX_P0

M28

PEG_HTX_GRX_P1

M33

PEG_HTX_GRX_P2

M30

PEG_HTX_GRX_P3

L31

PEG_HTX_GRX_P4

L28

PEG_HTX_GRX_P5

K30

PEG_HTX_GRX_P6

K27

PEG_HTX_GRX_P7

J29

PEG_HTX_GRX_P8

J27

PEG_HTX_GRX_P9

H28

PEG_HTX_GRX_P10

G28

PEG_HTX_GRX_P11

E28

PEG_HTX_GRX_P12

F28

PEG_HTX_GRX_P13

D27

PEG_HTX_GRX_P14

E26

PEG_HTX_GRX_P15

D25

Near MXM Connector

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

Intel(R) FDI

PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

eDP

3

CC1 0.22U_0402_16V 7K~DCC1 0.22U_0402_16V7K~D

1 2

CC2 0.22U_0402_16V 7K~DCC2 0.22U_0402_16V7K~D

1 2

CC3 0.22U_0402_16V 7K~DCC3 0.22U_0402_16V7K~D

1 2

CC4 0.22U_0402_16V 7K~DCC4 0.22U_0402_16V7K~D

1 2

CC5 0.22U_0402_16V 7K~DCC5 0.22U_0402_16V7K~D

1 2

CC13 0.22U_0402_16V7K~DCC13 0.22U_0402_16V7K~D

1 2

CC6 0.22U_0402_16V 7K~DCC6 0.22U_0402_16V7K~D

1 2

CC7 0.22U_0402_16V 7K~DCC7 0.22U_0402_16V7K~D

1 2

CC8 0.22U_0402_16V 7K~DCC8 0.22U_0402_16V7K~D

1 2

CC9 0.22U_0402_16V 7K~DCC9 0.22U_0402_16V7K~D

1 2

CC10 0.22U_0402_16V7K~DCC10 0.22U_0402_16V7K~D

1 2

CC11 0.22U_0402_16V7K~DCC11 0.22U_0402_16V7K~D

1 2

CC12 0.22U_0402_16V7K~DCC12 0.22U_0402_16V7K~D

1 2

CC14 0.22U_0402_16V7K~DCC14 0.22U_0402_16V7K~D

1 2

CC15 0.22U_0402_16V7K~DCC15 0.22U_0402_16V7K~D

1 2

CC16 0.22U_0402_16V7K~DCC16 0.22U_0402_16V7K~D

1 2

CC17 0.22U_0402_16V7K~DCC17 0.22U_0402_16V7K~D

1 2

CC18 0.22U_0402_16V7K~DCC18 0.22U_0402_16V7K~D

1 2

CC19 0.22U_0402_16V7K~DCC19 0.22U_0402_16V7K~D

1 2

CC20 0.22U_0402_16V7K~DCC20 0.22U_0402_16V7K~D

1 2

CC21 0.22U_0402_16V7K~DCC21 0.22U_0402_16V7K~D

1 2

CC22 0.22U_0402_16V7K~DCC22 0.22U_0402_16V7K~D

1 2

CC23 0.22U_0402_16V7K~DCC23 0.22U_0402_16V7K~D

1 2

CC24 0.22U_0402_16V7K~DCC24 0.22U_0402_16V7K~D

1 2

CC25 0.22U_0402_16V7K~DCC25 0.22U_0402_16V7K~D

1 2

CC26 0.22U_0402_16V7K~DCC26 0.22U_0402_16V7K~D

1 2

CC27 0.22U_0402_16V7K~DCC27 0.22U_0402_16V7K~D

1 2

CC28 0.22U_0402_16V7K~DCC28 0.22U_0402_16V7K~D

1 2

CC29 0.22U_0402_16V7K~DCC29 0.22U_0402_16V7K~D

1 2

CC30 0.22U_0402_16V7K~DCC30 0.22U_0402_16V7K~D

1 2

CC31 0.22U_0402_16V7K~DCC31 0.22U_0402_16V7K~D

1 2

CC32 0.22U_0402_16V7K~DCC32 0.22U_0402_16V7K~D

1 2

CC33 0.22U_0402_16V7K~DCC33 0.22U_0402_16V7K~D

1 2

CC34 0.22U_0402_16V7K~DCC34 0.22U_0402_16V7K~D

1 2

CC35 0.22U_0402_16V7K~DCC35 0.22U_0402_16V7K~D

1 2

CC36 0.22U_0402_16V7K~DCC36 0.22U_0402_16V7K~D

1 2

CC37 0.22U_0402_16V7K~DCC37 0.22U_0402_16V7K~D

1 2

CC38 0.22U_0402_16V7K~DCC38 0.22U_0402_16V7K~D

1 2

CC39 0.22U_0402_16V7K~DCC39 0.22U_0402_16V7K~D

1 2

CC40 0.22U_0402_16V7K~DCC40 0.22U_0402_16V7K~D

1 2

CC41 0.22U_0402_16V7K~DCC41 0.22U_0402_16V7K~D

1 2

CC42 0.22U_0402_16V7K~DCC42 0.22U_0402_16V7K~D

1 2

CC43 0.22U_0402_16V7K~DCC43 0.22U_0402_16V7K~D

1 2

CC44 0.22U_0402_16V7K~DCC44 0.22U_0402_16V7K~D

1 2

CC45 0.22U_0402_16V7K~DCC45 0.22U_0402_16V7K~D

1 2

CC46 0.22U_0402_16V7K~DCC46 0.22U_0402_16V7K~D

1 2

CC47 0.22U_0402_16V7K~DCC47 0.22U_0402_16V7K~D

1 2

CC48 0.22U_0402_16V7K~DCC48 0.22U_0402_16V7K~D

1 2

CC49 0.22U_0402_16V7K~DCC49 0.22U_0402_16V7K~D

1 2

CC50 0.22U_0402_16V7K~DCC50 0.22U_0402_16V7K~D

1 2

CC51 0.22U_0402_16V7K~DCC51 0.22U_0402_16V7K~D

1 2

CC52 0.22U_0402_16V7K~DCC52 0.22U_0402_16V7K~D

1 2

CC53 0.22U_0402_16V7K~DCC53 0.22U_0402_16V7K~D

1 2

CC54 0.22U_0402_16V7K~DCC54 0.22U_0402_16V7K~D

1 2

CC55 0.22U_0402_16V7K~DCC55 0.22U_0402_16V7K~D

1 2

CC56 0.22U_0402_16V7K~DCC56 0.22U_0402_16V7K~D

1 2

CC57 0.22U_0402_16V7K~DCC57 0.22U_0402_16V7K~D

1 2

CC58 0.22U_0402_16V7K~DCC58 0.22U_0402_16V7K~D

1 2

CC59 0.22U_0402_16V7K~DCC59 0.22U_0402_16V7K~D

1 2

CC60 0.22U_0402_16V7K~DCC60 0.22U_0402_16V7K~D

1 2

CC61 0.22U_0402_16V7K~DCC61 0.22U_0402_16V7K~D

1 2

CC62 0.22U_0402_16V7K~DCC62 0.22U_0402_16V7K~D

1 2

CC63 0.22U_0402_16V7K~DCC63 0.22U_0402_16V7K~D

1 2

CC64 0.22U_0402_16V7K~DCC64 0.22U_0402_16V7K~D

1 2

PEG_GTX_HRX_P[0..15] 14 PEG_GTX_HRX_N[0..15] 14

PEG_HTX_C_GRX_P[0..15] 14 PEG_HTX_C_GRX_N[0..15] 14

PEG_GTX_HRX_N0 PEG_GTX_HRX_N1 PEG_GTX_HRX_N2 PEG_GTX_HRX_N3 PEG_GTX_HRX_N4 PEG_GTX_HRX_N5 PEG_GTX_HRX_N6 PEG_GTX_HRX_N7 PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15

PEG_GTX_HRX_P0 PEG_GTX_HRX_P1 PEG_GTX_HRX_P2 PEG_GTX_HRX_P3 PEG_GTX_HRX_P4 PEG_GTX_HRX_P5 PEG_GTX_HRX_P6 PEG_GTX_HRX_P7 PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15

PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15

2

JCPU1I

M34

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186 VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

1

HPD Inversion for eDP

+VCCP

12

R1472

R1472 1K_0402_5%~D

1K_0402_5%~D

EDP_HPD#_Q

13

D

2

G

D

Q9

Q9 BSS138_SOT23~D

BSS138_SOT23~D

S

EDP_HPD#23

A A

EDP_HPD#

Note: Place pull up resistor within 2 inches of CPU

5

4

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

+VCCP

1 2

RC35 24.9_0402_1%~DRC35 24.9_0402_1%~D

1 2

RC36 24.9_0402_1%~DRC36 24.9_0402_1%~D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

PEG_COMP

EDP_COM

2

Sandy Bridge_rPGA_Rev1p0

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-6601P

4 63Tuesday, November 30, 2010

1

1.0

+VCCP

0.1U_0402_16V4Z~D

1

@

CC67

2

Place near JXDP1

D D

C C

B B

The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net

H_PROCHOT#44,49

H_THRMTRIP#19

5

+3VALW

@

CC66

1 2

RC27 1K_0402_5%~D@RC27 1K_0402_5%~D@

CFG107

0_0402_5%~D@

CFG117

PBTN_OUT#17,44

CFG07 VGATE56

PCH_SMBDATA10,11,12,13,16,37,38 PCH_SMBCLK10,11,12,13,16,37,38

PCH_JTAG_TCK15

H_SNB_IVB#19

RC41 56_0402_5%

H_CPUPWRGD

0_0402_5%~D@

CFG0

1K_0402_5%~D

T1PAD~D @T1PAD~D @

H_PECI19,44

1 2

SYS_PWROK_XDP

12 12

RC22

@RC22

@

1K_0402_5%~D

1 2 1 2

RC23

RC23 RC24

RC24

1 2 1 2

RC26 0_0402_5%~D@R C26 0_0402_5%~D@

1 2

RC30

@RC30

@

0_0402_5%~D

H_SNB_IVB#

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

CFG10_R

RC130_0402_5%~D@ RC130_0402_5%~D@ RC15

RC15

CFG11_R

XDP_BPM#4 XDP_BPM#5

XDP_BPM#6 XDP_BPM#7

H_CPUPWRGD_XDP CFD_PWRBTN#_X DP

XDP_HOOK2 SYS_PWROK_XDP

XDP_TCK1 XDP_TCK_R

C26

AN34

AL33

AN33

AL32

AN32

+VCCP +VCCP

JCPU1B

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

4

JXDP1

@JXDP1

@

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

MISCTHERMALPWR MANAGEMENT

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

CLOCKS

DDR3

MISC

DDR3

MISC

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

VCC_OBS_CD

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

BCLK

BCLK#

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

A28 A27

A16 A15

R8

AK1 A5 A4

CLK_CPU_DMI_R

CFG16_R

RC3 0_0402_5%~D@RC3 0_0402_5%~D@

CFG17_R

RC5 0_0402_5%~D@RC5 0_0402_5%~D@

CFG0_R

RC7 0_0402_5%~D@RC7 0_0402_5%~D@

CFG1_R

RC9 0_0402_5%~D@RC9 0_0402_5%~D@

CFG2_R

RC10 0_0402_5%~D@RC10 0_0402_5%~D@

CFG3_R

RC12 0_0402_5%~D@RC12 0_0402_5%~D@

CFG8_R

RC14 0_0402_5%~D@RC14 0_0402_5%~D@

CFG9_R

RC16 0_0402_5%~D@RC16 0_0402_5%~D@

CFG4_R

RC17 0_0402_5%~D@RC17 0_0402_5%~D@

CFG5_R

RC18 0_0402_5%~D@RC18 0_0402_5%~D@

CFG6_R

RC20 0_0402_5%~D@RC20 0_0402_5%~D@

CFG7_R

RC21 0_0402_5%~D@RC21 0_0402_5%~D@

CLK_CPU_ITP CLK_CPU_ITP#

XDP_RST#_R XDP_DBRESET#

XDP_TDO XDP_TRST#_R XDP_TDI XDP_TMS_R

CLK_CPU_DMI#_R

CLK_CPU_DPLL_R CLK_CPU_DPLL#_R

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

RC28 0_0402_5%~D@RC28 0_0402_5%~D@

RC31 0_0402_5%~D@RC31 0_0402_5%~D@ RC29 0_0402_5%~D@RC29 0_0402_5%~D@

3

1 2 1 2

RC25

1K_0402_5%~D

PLT_RST#

@RC25

@

12

1 2

1 2 1 2

RC37 33_0402_5%~DRC37 33_0402_5%~D

1 2

RC38 33_0402_5%~DRC38 33_0402_5%~D

1 2

RC39 0_0402_5%~DRC39 0_0402_5%~D

1 2

RC40 0_0402_5%~DRC40 0_0402_5%~D

1 2

H_DRAMRST# 6

PCH_PWROK17,44

SYSTEM_PWROK17,44

CFG16 7 CFG17 7

CFG0 7 CFG1 7

CFG2 7 CFG3 7

CFG8 7 CFG9 7

CFG4 7 CFG5 7

CFG6 7 CFG7 7

CLK_CPU_ITP 16 CLK_CPU_ITP# 16

PCH_JTAG_TDO 15

PCH_JTAG_TDI 15 PCH_JTAG_TMS 15

CLK_CPU_DMI 16 CLK_CPU_DMI# 16

CLK_CPU_DPLL 16 CLK_CPU_DPLL# 16

RC113 0_0402_5%~DRC113 0_0402_5%~D

1 2

RC74 0_0402_5%~D@RC74 0_0402_5%~D@

1 2

RC4

200_0402_1%

PM_DRAM_PWR GD17

XDP_DBRESET#

H_CPUPWRGD_R

2

+3VALW

0.1U_0402_16V4Z~D

+3VS+3V_PCH

12

PLT_RST#18,33,35,38,39,44

12

RC6

@RC6

@

10K_0402_5%~D

1

2

UC5

MC74VHC1G09DFT2G_SC70-5

1 2

UC5

RUN_ON_CPU1.5VS3#9,47

+3VS

5

1

NC

2

A

3

RC421K_0402_5%~D RC421K_0402_5%~D

RC4410K_0402_5%~D RC4410K_0402_5%~D

P

G

0.1U_0402_16V4Z~D

1

CC65

2

5

B

4

Y

VCC

A

G

3

1 2

13

D

2

G

S

+VCCP

CC68

1 2

0.1U_0402_16V4Z~D

BUFO_CPU_RST# BUF_CPU_RST#

4

Y

UC2

SN74LVC1G07DCKR_SC70-5~D

+3VS

H_PROCHOT#

12

Processor Pullups

1

+1.5V_CPU_VDDQ

12

RC8

RC8 200_0402_1%

200_0402_1%

VDDPWRGOOD

RC19

RC19 39_0402_1%

39_0402_1%

RC12 CRB 1.1K CHECK LIST 0.7 --> 4.75K INTEL recommand 1.1K

QC1

QC1 SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

PDG 0.71 rev -->200

RC32

RC32 75_0402_5%

75_0402_5%

1 2

RC33 43_0402_1%RC33 43_0402_1%

1 2

+VCCP

RC4362_0402_5% RC4362_0402_5%

PU/PD for JTAG signals

RC121 0_0402_5%~D@RC121 0_0402_5%~D@

AP29

PRDY#

PREQ#

H_PM_SYNC17

H_CPUPWRGD19

VDDPWRGOOD

A A

1 2

RC49 0_0402_5%~DRC49 0_0402_5%~D

1 2

RC53 0_0402_5%~DRC53 0_0402_5%~D

1 2

RC57 130_0402_1%~DRC57 130_0402_1%~D

H_PM_SYNC_R

H_CPUPWRGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

AM34

AP33

V8

AR33

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWR OK

RESET#

TRST#

DBR#

BPM#[0]

JTAG & BPM

BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK TMS

TDO

TDI

XDP_PREQ#_R

AP27

XDP_TCK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI_R

AR28

XDP_TDO_R

AP26

XDP_DBRESET#_R

AL35

XDP_BPM#0_R

AT28

XDP_BPM#1_R

AR29

XDP_BPM#2_R

AR30

XDP_BPM#3_R

AT30

XDP_BPM#4_R

AP32

XDP_BPM#5_R

AR31

XDP_BPM#6_R

AT31

XDP_BPM#7_R

AR32

1 2

RC125 0_0402_5%~D@RC125 0_0402_5%~D@

1 2

RC126 0_0402_5%~D@RC126 0_0402_5%~D@

1 2

RC127 0_0402_5%~D@RC127 0_0402_5%~D@

1 2

RC128 0_0402_5%~D@RC128 0_0402_5%~D@

1 2

RC50 0_0402_5%~D@RC50 0_0402_5%~D@

1 2

RC51 0_0402_5%~D@RC51 0_0402_5%~D@

1 2

RC56 0_0402_5%~DRC56 0_0402_5%~D

1 2

RC59 0_0402_5%~D@RC59 0_0402_5%~D@

1 2

RC61 0_0402_5%~D@RC61 0_0402_5%~D@

1 2

RC62 0_0402_5%~D@RC62 0_0402_5%~D@

1 2

RC63 0_0402_5%~D@RC63 0_0402_5%~D@

1 2

RC64 0_0402_5%~D@RC64 0_0402_5%~D@

1 2

RC65 0_0402_5%~D@RC65 0_0402_5%~D@

1 2

RC66 0_0402_5%~D@RC66 0_0402_5%~D@

1 2

RC67 0_0402_5%~D@RC67 0_0402_5%~D@

1 2

XDP_PRDY#XDP_PRDY#_R XDP_PREQ#

XDP_TCK_R XDP_TMS_R XDP_TRST#_R

XDP_TDI XDP_TDO

XDP_DBRESET# 17

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

1 2

RC55140_0402_1% RC55140_0402_1%

RC5825.5_0402_1%~D RC5825.5_0402_1%~D

RC60200_0402_1% RC60200_0402_1%

XDP_TMS

XDP_TDI_R

XDP_PREQ#_R

XDP_TDO_R

XDP_TCK

XDP_TRST#

1 2

+VCCP

RC4551_0402_5% RC4551_0402_5%

RC4651_0402_5% RC4651_0402_5%

RC4751_0402_5% @RC4751_0402_5% @

RC4851_0402_5% RC4851_0402_5%

RC5251_0402_5% RC5251_0402_5%

RC5451_0402_5% RC5451_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-6601P

5 63Tuesday, November 30, 2010

1

1.0

5

4

3

2

1

Need to confired

when Intel spec release.

JCPU1C

M_CLK_DDR0

DDR_A_D[0..63]10,12

D D

C C

B B

DDR_A_CAS#10,12 DDR_A_RAS#10,12 DDR_A_WE#10,12

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS010,12 DDR_A_BS110,12 DDR_A_BS210,12

AP11 AN11

AL12 AM12 AM11

AL11

AP12 AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10 AF10

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0]

SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

SA_ODT[0]

SA_ODT[1] RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_CLK_DDR#0 DDR_CKE0_DIMMA

M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA

M_CLK_DDR4 M_CLK_DDR#4 DDR_CKE4_DIMMC

M_CLK_DDR5 M_CLK_DDR#5 DDR_CKE5_DIMMC

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS4_DIMMC# DDR_CS5_DIMMC#

M_ODT0 M_ODT1 M_ODT4 M_ODT5

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 12 M_CLK_DDR#0 12 DDR_CKE0_DIMMA 12

M_CLK_DDR1 12 M_CLK_DDR#1 12 DDR_CKE1_DIMMA 12

M_CLK_DDR4 10 M_CLK_DDR#4 10 DDR_CKE4_DIMMC 10

M_CLK_DDR5 10 M_CLK_DDR#5 10 DDR_CKE5_DIMMC 10

DDR_CS0_DIMMA# 12 DDR_CS1_DIMMA# 12 DDR_CS4_DIMMC# 10 DDR_CS5_DIMMC# 10

M_ODT0 12 M_ODT1 12 M_ODT4 10 M_ODT5 10

DDR_A_DQS#[0..7] 10,12

DDR_A_DQS[0..7] 10,12

DDR_A_MA[0..15] 10,12

DDR_B_D[0..63]11,13

DDR_B_BS011,13 DDR_B_BS111,13 DDR_B_BS211,13

DDR_B_CAS#11,13 DDR_B_RAS#11,13 DDR_B_WE#11,13

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AM5 AM6 AR3

AN3 AN2 AN1

AN9

AN8 AR6 AR5 AR9

AJ11

AH11

AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

JCPU1D

M_CLK_DDR2

AE2

SB_CLK[0]

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34]

AP3

SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40] SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

SB_CS#[0]

SB_CS#[1] RSVD_TP[17] RSVD_TP[18]

SB_ODT[0]

SB_ODT[1] RSVD_TP[19] RSVD_TP[20]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_CLK_DDR#2 DDR_CKE2_DIMMB

M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB

M_CLK_DDR6 M_CLK_DDR#6 DDR_CKE6_DIMMD

M_CLK_DDR7 M_CLK_DDR#7 DDR_CKE7_DIMMD

DDR_CS2_DIMMB# DDR_CS3_DIMMB# DDR_CS6_DIMMD# DDR_CS7_DIMMD#

M_ODT2 M_ODT3 M_ODT6 M_ODT7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 13 M_CLK_DDR#2 13 DDR_CKE2_DIMMB 13

M_CLK_DDR3 13 M_CLK_DDR#3 13 DDR_CKE3_DIMMB 13

M_CLK_DDR6 11 M_CLK_DDR#6 11 DDR_CKE6_DIMMD 11

M_CLK_DDR7 11 M_CLK_DDR#7 11 DDR_CKE7_DIMMD 11

DDR_CS2_DIMMB# 13 DDR_CS3_DIMMB# 13 DDR_CS6_DIMMD# 11 DDR_CS7_DIMMD# 11

M_ODT2 13 M_ODT3 13 M_ODT6 11 M_ODT7 11

DDR_B_DQS#[0..7] 11,13

DDR_B_DQS[0..7] 11,13

DDR_B_MA[0..15] 11,13

Sandy Bridge_rPGA_Rev1p0

CONN@

QC2

BSS138_SOT23~D

D

S

D

S

H_DRAMRST#5

A A

H_DRAMRST#

4.99K_0402_1%~D

RC77

12

DDR3_DRAMRST#_R

13

DG 0.7 Figure 57 RC124=1K

G

2

DRAMRST_CNTRL

1

CC69

0.047U_0402_16V4Z~D

2

+1.5V

12

RC75

1K_0402_5%~D

RC76 1K_0402_5%~DRC76 1K_0402_5%~D

1 2

12

RC720_0402_5%~D RC720_0402_5%~D

RC730_0402_5%~D @RC730_0402_5%~D @

DDR3_DRAMRST# 10,11,12,13

DRAMRST_CNTRL_PCH 16

DRAMRST_CNTRL_EC 44

Sandy Bridge_rPGA_Rev1p0

CONN@

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT .

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-6601P

6 63Tuesday, November 30, 2010

1

1.0

5

4

3

2

1

CFG Straps for Processor

D D

JCPU1E

L7

RSVD28

AG7

RESERVED

RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

VCC_DIE_SENSE

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

KEY

CFG0

CFG05

CFG1

+VCC_GFXCORE_AXG

VCC_AXG_VAL_SENSE

12

RC79 49.9_0402_1%@RC79 49.9_0402_1%@

+VCC_CORE

VCC_VAL_SENSE

12

RC80 49.9_0402_1%@RC80 49.9_0402_1%@

VSS_AXG_VAL_SENSE

1 2

RC90 49.9_0402_1%@RC90 49.9_0402_1%@

RC91 49.9_0402_1%@RC91 49.9_0402_1%@

C C

+V_DDR_REFA

+V_DDR_REFB

B B

RC82 0_0402_5%~D@RC82 0_0402_5%~D@ RC83 0_0402_5%~D@RC83 0_0402_5%~D@

1 2

1 2 1 2

VSS_VAL_SENSE

12

RC84

1K_0402_1%~D

INTEL 12/28 rec ommand to add 1k pull down

VCCP_PWRCTRL52

CFG15 CFG25 CFG35 CFG45 CFG55 CFG65 CFG75 CFG85 CFG95 CFG105 CFG115

T51PAD~D@ T51PAD~D@ T52PAD~D@ T52PAD~D@ T53PAD~D@ T53PAD~D@ T54PAD~D@ T54PAD~D@

CFG165 CFG175

+V_DDR_REFA_R +V_DDR_REFB_R

RC85

1K_0402_1%~D

1 2

RC88 0_0402_5%~DRC88 0_0402_5%~D

CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE

T19PAD~D @T19PAD~D @

T25PAD~D @T25PAD~D @ T26PAD~D @T26PAD~D @ T27PAD~D @T27PAD~D @ T28PAD~D @T28PAD~D @ T30PAD~D @T30PAD~D @ T32PAD~D @T32PAD~D @ T33PAD~D @T33PAD~D @ T34PAD~D @T34PAD~D @ T35PAD~D @T35PAD~D @ T37PAD~D @T37PAD~D @ T38PAD~D @T38PAD~D @ T39PAD~D @T39PAD~D @ T40PAD~D @T40PAD~D @ T41PAD~D @T41PAD~D @ T42PAD~D @T42PAD~D @ T43PAD~D @T43PAD~D @

T44PAD~D @T44PAD~D @ T45PAD~D @T45PAD~D @

H_VCCP_SEL

T49PAD~D @T49PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

Sandy Bridge_rPGA_Rev1p0

CONN@

T2 PAD~D@T2 PAD~D@ T3 PAD~D@T3 PAD~D@ T4 PAD~D@T4 PAD~D@ T5 PAD~D@T5 PAD~D@ T6 PAD~D@T6 PAD~D@

T7 PAD~D@T7 PAD~D@ T8 PAD~D@T8 PAD~D@ T9 PAD~D@T9 PAD~D@

T10 PAD~D@T10 PAD~D@ T11 PAD~D@T11 PAD~D@ T12 PAD~D@T12 PAD~D@ T13 PAD~D@T13 PAD~D@

T14 PAD~D@T14 PAD~D@ T15 PAD~D@T15 PAD~D@ T16 PAD~D@T16 PAD~D@ T17 PAD~D@T17 PAD~D@ T18 PAD~D@T18 PAD~D@

T20 PAD~D@T20 PAD~D@ T21 PAD~D@T21 PAD~D@ T22 PAD~D@T22 PAD~D@ T23 PAD~D@T23 PAD~D@ T24 PAD~D@T24 PAD~D@

T29 PAD~D@T29 PAD~D@ T31 PAD~D@T31 PAD~D@

T36 PAD~D@T36 PAD~D@

CLK_RES_ITP 16 CLK_RES_ITP# 16

T46 PAD~D@T46 PAD~D@ T47 PAD~D@T47 PAD~D@ T48 PAD~D@T48 PAD~D@

T50 PAD~D@T50 PAD~D@

CFG[6:5]

CFG2

1K_0402_1%~D

@RC78

@

12

RC78

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition 0:Lane Reversed

CFG4

1K_0402_1%~D

12

RC81

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6 CFG5

1K_0402_1%~D

@RC87

@

@RC86

@

12

RC87

RC86

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1K_0402_1%~D

@RC89

@

12

RC89

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB de assertion

CFG7

0: PEG Wait for BIOS for training

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT .

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-6601P

7 63Tuesday, November 30, 2010

1

1.0

5

4

POWER

JCPU1F

POWER

3

2

1

+VCC_CORE

94A

AG35

D D

+VCC_CORE

10U_0805_4VAM~D

CC82

1

2

+VCC_CORE

22U_0805_6.3VAM~D

1

2

1

2

+VCC_CORE

1

2

22U_0805_6.3VAM~D

CC117

22U_0805_6.3VAM~D

CC116

470U_D2_2VM_R4.5M~D

CC132

+

C C

B B

A A

10U_0805_4VAM~D

CC90

CC89

1

2

22U_0805_6.3VAM~D

CC119

CC118

1

2

22U_0805_6.3VAM~D

@

CC129

1

2

470U_D2_2VM_R4.5M~D

1

CC136

CC133

+

2

10U_0805_4VAM~D

CC70

CC85

1

2

22U_0805_6.3VAM~D

CC120

CC121

1

2

22U_0805_6.3VAM~D

@

CC131

CC130

1

2

470U_D2_2VM_R4.5M~D

1

CC134

CC137

+

2

10U_0805_4VAM~D

1

2

22U_0805_6.3VAM~D

1

2

470U_D2_2VM_R4.5M~D

1

+

2

10U_0805_4VAM~D

CC91

CC86

CC122

CC135

CC87

1

2

22U_0805_6.3VAM~D

1

2

22U_0805_6.3VAM~D

CC123

CC124

1

2

10U_0805_4VAM~D

@

CC84

CC83

CC71

1

2

22U_0805_6.3VAM~D

CC126

CC125

1

2

22U_0805_6.3VAM~D

CC127

CC128

1

2

22U_0805_6.3VAM~D

CC115

CC114

CC113

1

2

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev1p0

CONN@

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30

PEG AND DDR

VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

SENSE LINES SVID

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

CORE SUPPLY

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCSENSE_R VSSSENSE_R

8.5A

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

22U_0805_6.3VAM~D

1

2

22U_0805_6.3VAM~D

1

2

330U_D2_2VM_R6M~D

1

+

2

RC98 0_0402_5%~DRC98 0_0402_5%~D RC99 0_0402_5%~DRC99 0_0402_5%~D

VCCIO_SENSE 52 VSSIO_SENSE 52

22U_0805_6.3VAM~D

CC73

CC74

CC72

CC96

CC110

CC74

1

2

1

2

1

+

2

1 2 1 2

1

2

22U_0805_6.3VAM~D

CC97

CC98

1

2

330U_D2_2VM_R6M~D

1

@

CC112

CC111

+

2

RC94 43_0402_1%RC94 43_0402_1%

1 2

RC92 0_0402_5%~DRC92 0_0402_5%~D

1 2

RC96 0_0402_5%~DRC96 0_0402_5%~D

1 2

22U_0805_6.3VAM~D

CC75

22U_0805_6.3VAM~D

CC99

22U_0805_6.3VAM~D

CC76

1

2

22U_0805_6.3VAM~D

CC100

1

2

+VCC_CORE

CC77

CC101

22U_0805_6.3VAM~D

CC88

1

2

22U_0805_6.3VAM~D

CC102

1

2

+VCCP

75_0402_1%~D

12

RC93

12

100_0402_1%~D

12

100_0402_1%~D

1

2

1

2

RC97

RC100

22U_0805_6.3VAM~D

130_0402_1%~D

12

22U_0805_6.3VAM~D

CC80

CC78

CC103

RC95

CC80

CC79

1

2

1

2

1

2

22U_0805_6.3VAM~D

CC104

CC105

1

2

Note: Place the PU resistors close to CPU 300 - 1500mils

VCCSENSE 56 VSSSENSE 56

22U_0805_6.3VAM~D

CC81

CC92

1

2

22U_0805_6.3VAM~D

CC106

CC107

1

2

VR_SVID_ALRT# 56 VR_SVID_CLK 56

VR_SVID_DAT 56

+VCCP

22U_0805_6.3VAM~D

CC95

CC94

CC93

1

2

22U_0805_6.3VAM~D

CC108

CC109

1

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT .

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

LA-6601P

8 63Tuesday, November 30, 2010

1

1.0

5

+3VALW

12

RC102

100K_0402_5%~D

22U_0805_6.3VAM~D

1U_0402_6.3V6K~D

2

G

CC146

@

CC154

CC175

6

22U_0805_6.3VAM~D

CC147

1

2

22U_0805_6.3VAM~D

@

CC155

1

2

330U_D2_2.5VM_R6M~D

1

CC176

+

2

RUN_ON_CPU1.5VS3#

DMN66D0LDW-7_SOT363-6~D

D

QC5A

S

1

33A

3A

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Sandy Bridge_rPGA_Rev1p0

CONN@

D D

RC104 0_0402_5%~D@RC104 0_0402_5%~D@

SUSP#20,44,47,52,53,54

CPU1.5V_S3_GATE44

+VCC_GFXCORE_AXG

22U_0805_6.3VAM~D

CC140

1

2

C C

B B

22U_0805_6.3VAM~D

CC148

1

2

470U_D2_2VM_R4.5M~D

1

+

CC156

2

+1.8VS

RC109 0_0805_5% R C109 0_0805_5%

1 2

RC107 0_0402_5%~DRC107 0_0402_5%~D

1 2

CC178

0.1U_0402_10V7K~D

22U_0805_6.3VAM~D

CC142

CC141

1

2

22U_0805_6.3VAM~D

CC150

CC149

1

2

470U_D2_2VM_R4.5M~D

1

+

@

CC158

CC157

2

1 2

1

@CC178

@

2

22U_0805_6.3VAM~D

CC144

CC145

CC143

1

2

22U_0805_6.3VAM~D

@

CC152

CC151

CC153

1

2

@

CC159

+1.8VS_VCCPLL

1U_0402_6.3V6K~D

10U_0805_4VAM~D

CC174

1

CC172

2

4

B+_BIAS

12

RC101

100K_0402_5%~D

3

D

5

G

S

4

RUN_ON_CPU1.5VS3# 5,47

POWER

SENSE

GRAPHICS

1.8V RAIL

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

QC3

AO4728L_SO8~D

RUN_ON_CPU1.5VS3

DMN66D0LDW-7_SOT363-6~D

QC5B

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VREFMISC

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

DDR3 -1.5V RAILS

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

SA RAIL

VCCSA_SENSE

FC_C22

VCCSA_VID1

8 7 6 5

1 2 3

4

0.1U_0603_25V7K~D

330K_0402_1%

12

RC105

1

CC139

2

VCC_AXG_SENSE

AK35

VSS_AXG_SENSE

AK34

AL1

+V_SM_VREF should have 10 mil trace width

5A

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

6A

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCSA_SEL 55

+V_SM_VREF_CNT

10U_0805_4VAM~D

1

2

10U_0805_4VAM~D

1

CC167

2

10U_0805_10V4Z~D

CC138

1

12

2

VCC_AXG_SENSE 56 VSS_AXG_SENSE 56

10U_0805_4VAM~D

1

CC160

CC161

2

10U_0805_4VAM~D

1

CC168

2

3

20K_0402_5%~D

RC103

+1.5V

100_0402_1%~D

12

RC112

100_0402_1%~D

12

RC116

10U_0805_4VAM~D

1

CC162

CC163

2

+VCCSA

330U_D2_2VM_R6M~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D

1

+

@

CC169

CC170

2

10K_0402_5%~D

RC111

1 2

RC106 0_0402_5%~D@RC106 0_0402_5%~D@

1 2

+V_SM_VREF

10U_0805_4VAM~D

1

CC164

2

CC171

RC120 0_0402_5%~DRC120 0_0402_5%~D

H_FC_C22 55

123

QC4

NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

330U_D2_2VM_R6M~D

10U_0805_4VAM~D

1

CC166

1

+

CC165

2

1 2

0_0402_5%~D

12

@

RC110

12

RC108

RC108 100K_0402_5%~D

100K_0402_5%~D

CC173 0.1U_0402_10V7K~DCC173 0.1U_0402_10V7K~D

12

CC177 0.1U_0402_10V7K~DCC177 0.1U_0402_10V7K~D

12

CC181 0.1U_0402_10V7K~DCC181 0.1U_0402_10V7K~D

12

CC182 0.1U_0402_10V7K~DCC182 0.1U_0402_10V7K~D

12

J8

@J8

@

1 2

PAD-OPEN 4x4m

PJP30 OPEN

VSS_AXG_SENSE 56

VCCSA_SENSE 55

2

+V_SM_VREF_CNT

+1.5V

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

Sandy Bridge_rPGA_Rev1p0

CONN@

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

LA-6601P

9 63Tuesday, November 30, 2010

1

1.0

5

DDR_A_DQS#[0..7]6,12 DDR_A_DQS[0..7]6,12

DDR_A_D[0..63]6,12 DDR_A_MA[0..15]6,12

D D

Layout Note: Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

1

2

+1.5V

10U_0603_6.3V6M~D

C C

B B

1

2

+0.75VS

1U_0402_6.3V6K~D

1

CD4

CD3

CD5

2

10U_0603_6.3V6M~D

1

CD8

CD9

CD7

Layout Note: Place near JDIMM1.203,204

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

CD17

CD18

1

2

RD1

100_0402_1%~D

RD3

100_0402_1%~D

1U_0402_6.3V6K~D

CD6

10U_0603_6.3V6M~D

CD10

1

2

1U_0402_6.3V6K~D

CD19

1

2

+1.5V

12

10U_0603_6.3V6M~D

CD12

CD11

1

2

1U_0402_6.3V6K~D

CD20

+V_DDR_REFA

All VREF traces should have 10 mil trace width

10U_0603_6.3V6M~D

@

CD13

330U_SX_2VY~D

1

CD14

+

2

10K_0402_5%~D

4

+V_DDR_REFA

SA0

1

0

RD35

RD6

10K_0402_5%~D

RD2 0_0402_5%~DRD2 0_0402_5%~D

1 2

DDR_CKE4_DIMMC6

DDR_CS5_DIMMC#6

SA1

001

DIMM1

1

DIMM2

DIMM3

1

DIMM4

+3VS

RD36

@ RD36

@

10K_0402_5%~D

1 2

+3VS

RD7

1 2

RD7

10K_0402_5%~D

1 2

@RD6

@

3

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

GND2

+1.5V+1.5V

2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

DM1

VSS

VSS DM2 VSS

VSS

VDD

A15 A14

VDD

A11

VDD

VDD CK1

VDD BA1

VDD

S0#

VDD

VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

SDA SCL

VTT

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22 24 26 28

DDR3_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20DDR_A_D16

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_CKE5_DIMMC

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11DDR_A_MA12

84

DDR_A_MA7DDR_A_MA9

86

A7

88

DDR_A_MA6DDR_A_MA8

90

A6

DDR_A_MA4DDR_A_MA5

92

A4

94

DDR_A_MA2

96

A2

DDR_A_MA0

98

A0

100

M_CLK_DDR5

102

M_CLK_DDR#5

104 106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDR_CS4_DIMMC#

114

M_ODT4

116 118

M_ODT5

120 122

NC

124 126 128

DDR_A_D36

130

DDR_A_D37

132 134 136 138

DDR_A_D38

140

DDR_A_D39

142 144

DDR_A_D44

146

DDR_A_D45

148 150

DDR_A_DQS#5

152

DDR_A_DQS5

154 156

DDR_A_D46

158

DDR_A_D47

160 162

DDR_A_D52

164

DDR_A_D53

166 168 170 172

DDR_A_D54

174

DDR_A_D55

176 178

DDR_A_D60

180

DDR_A_D61

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196

M_THERMAL#

198

PCH_SMBDATA

200

PCH_SMBCLK

202 204

+0.75VS

206

JDIMM1

+DIMM0_VREF

DDR_A_D0

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

DDR_A_D1

CD2

CD1

1

2

M_CLK_DDR46 M_CLK_DDR#46

DDR_A_BS06,12

DDR_A_WE#6,12 DDR_A_CAS#6,12

DDR_A_D2

2

DDR_A_D3

DDR_A_D8 DDR_A_D9 DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE4_DIMMC

DDR_A_BS2

DDR_A_BS26,12

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR4 M_CLK_DDR#4

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS5_DIMMC#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

+0.75VS

CD21

1

CD22

1

2

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

TYCO_2-2013287-1

Link Done

2

DDR3_DRAMRST# 6,11,12,13

DDR_CKE5_DIMMC 6

M_CLK_DDR5 6 M_CLK_DDR#5 6

DDR_A_BS1 6,12 DDR_A_RAS# 6,12

DDR_CS4_DIMMC# 6 M_ODT4 6

M_ODT5 6

+VREF_CA

2.2U_0603_6.3V6K~D

CD15

1

2

M_THERMAL# 11,12,13,44

PCH_SMBDATA 5, 11,12,13,16,37,38

PCH_SMBCLK 5,11,12,13,16,37,38

1

2 (H8)

JDIMM1 (H4)

CPU

+1.5V

12

RD4

1K_0402_1%~D

0.1U_0402_16V4Z~D

12

CD16

RD5

1K_0402_1%~D

3 (H5.2)

4 (H9.2)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-6601P

10 63Tuesday, November 30, 2010

1

1.0

5

4

3

2

1

+1.5V

RD14 0_0402_5%~DRD14 0_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

CD27

1

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

DDR_CKE6_DIMMD6

DDR_B_BS26,13

M_CLK_DDR66 M_CLK_DDR#66

DDR_B_BS06,13

DDR_B_WE#6,13 DDR_B_CAS#6,13

DDR_CS7_DIMMD#6

SA0

SA1

001

DIMM1

1

DIMM2

1

DIMM3

0

1

DIMM4

0

+3VS

RD19

10K_0402_5%~D

1 2

12

RD37

@ RD37

@

10K_0402_5%~D

+3VS

12

0.1U_0402_16V4Z~D

CD26

DDR_CKE6_DIMMD

DDR_B_BS2

M_CLK_DDR6 M_CLK_DDR#6

DDR_CS7_DIMMD#

1

2

+DIMM1_VREF

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

+0.75VS

0.1U_0402_16V4Z~D

CD46

1

2

+1.5V

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

RAS#

ODT0

ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

GND2

CK1#

+1.5V

2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS DM1

VSS

VSS DM2 VSS

VSS

VDD

A15 A14

VDD

A11

VDD

VDD CK1

VDD BA1

VDD

S0#

VDD

VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

SDA SCL

VTT

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44 46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE7_DIMMD

74 76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

DDR_B_MA4

92

A4

94

DDR_B_MA2

96

A2

DDR_B_MA0

98

A0

100

M_CLK_DDR7

102

M_CLK_DDR#7

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDR_CS6_DIMMD#

114

M_ODT6

116 118

M_ODT7

120 122

NC

124 126 128

DDR_B_D36

130

DDR_B_D37

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196

M_THERMAL#

198

PCH_SMBDATA

200

PCH_SMBCLK

202 204

+0.75VS

206

CPU

DDR3_DRAMRST# 6,10,12,13

DDR_CKE7_DIMMD 6

M_CLK_DDR7 6 M_CLK_DDR#7 6

DDR_B_BS1 6,13 DDR_B_RAS# 6,13

DDR_CS6_DIMMD# 6 M_ODT6 6

M_ODT7 6

+VREF_CB

2.2U_0603_6.3V6K~D

CD40

1

2

M_THERMAL# 10,12,13,44

PCH_SMBDATA 5, 10,12,13,16,37,38

PCH_SMBCLK 5,10,12,13,16,37,38

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

2.2U_0603_6.3V6K~D

205

CD47

GND1

TYCO_2-2013298-1

Link Done

+V_DDR_REFB

RD38

10K_0402_5%~D

RD20

@RD20

@

10K_0402_5%~D

12

RD15

100_0402_1%~D

DDR_B_DQS#[0..7]6,13

DDR_B_DQS[0..7]6,13

D D

C C

+1.5V

B B

DDR_B_D[0..63]6,13

DDR_B_MA[0..15]6,13

+1.5V

1U_0402_6.3V6K~D

CD28

CD29

1

2

10U_0603_6.3V6M~D

CD34

CD32

CD33

1

2

+0.75VS

1

2

Layout Note: Place near JDIMMB.203,204

1U_0402_6.3V6K~D

CD42

1

2

Layout Note: Place near JDIMMB

1U_0402_6.3V6K~D

CD30

CD31

1

2

10U_0603_6.3V6M~D

CD36

CD37

CD35

CD43

CD37

1

2

1U_0402_6.3V6K~D

CD45

CD44

1

2

10U_0603_6.3V6M~D

@

CD38

1

2

RD16

100_0402_1%~D

330U_SX_2VY~D

1

CD39

+

2

12

All VREF traces should have 10 mil trace width

0.1U_0402_16V4Z~D

CD41

JDIMM2 (H8)

1 (H4)

3 (H5.2)

4 (H9.2)

+1.5V

12

RD17

1K_0402_1%~D

12

RD18

1K_0402_1%~D

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-6601P

11 63Tuesday, November 30, 2010

1

1.0

5

DDR_A_DQS#[0..7]6,10

DDR_A_DQS[0..7]6,10

DDR_A_D[0..63]6,10

DDR_A_MA[0..15]6,10

D D

Layout Note: Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

CD53

1

2

+1.5V

10U_0603_6.3V6M~D

CD57

1

C C

B B

1

2

Layout Note: Place near JDIMM1.203,204

+0.75VS

1U_0402_6.3V6K~D

CD67

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CD58

CD56

CD55

CD54

1

2

10U_0603_6.3V6M~D

CD60

CD59

1

2

1U_0402_6.3V6K~D

CD69

CD68

1

2

10U_0603_6.3V6M~D

@

CD62

CD63

CD61

1

2

1U_0402_6.3V6K~D

CD70

330U_SX_2VY~D

1

CD64

+

2

10K_0402_5%~D

4

+V_DDR_REFA

SA0

1

0

RD32

@ RD 32

@

RD40

+3VS

RD28 0_0402_5%~DRD28 0_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

CD51

1

2

DDR_CKE0_DIMMA6

DDR_A_BS26,10

M_CLK_DDR06 M_CLK_DDR#06

DDR_A_BS06,10

DDR_A_WE#6,10 DDR_A_CAS#6,10

DDR_CS1_DIMMA#6

SA1

001

DIMM1

1

DIMM2

DIMM3

1

DIMM4

12

RD39

@RD39

@

10K_0402_5%~D

+3VS

12

RD33

10K_0402_5%~D

1 2

3

JDIMM3

+0.75VS

JDIMM3

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

TYCO_2-2013289-1

Link Done

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

GND2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS DM1

VSS

VSS DM2 VSS

VSS

VDD

A15 A14

VDD

A11

A7

VDD

A6 A4

VDD

A2

A0 VDD CK1

VDD BA1

VDD

S0#

VDD

NC VDD

VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

SDA SCL

VTT

+DIMM3_VREF

DDR_A_D0

0.1U_0402_16V4Z~D

DDR_A_D1

CD52

1

DDR_A_D2

2

DDR_A_D3

DDR_A_D8 DDR_A_D9 DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

CD71

CD72

1

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

+1.5V+1.5V

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20DDR_A_D16 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11DDR_A_MA12 DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8 DDR_A_MA4DDR_A_MA5

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

M_THERMAL# PCH_SMBDATA PCH_SMBCLK

+0.75VS

2

DDR3_DRAMRST# 6,10,11,13

DDR_CKE1_DIMMA 6

M_CLK_DDR1 6 M_CLK_DDR#1 6

DDR_A_BS1 6,10 DDR_A_RAS# 6,10

DDR_CS0_DIMMA# 6 M_ODT0 6

M_ODT1 6

+VREF_CC

M_THERMAL# 10,11,13,44

PCH_SMBDATA 5,10,11,13,16,37, 38

PCH_SMBCLK 5,10,11,13,16,37,38

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

CD65

1

2

CPU

CD66

+1.5V

12

RD30

RD30 1K_0402_1%~D

1K_0402_1%~D

12

RD31

RD31 1K_0402_1%~D

1K_0402_1%~D

2 (H8) 1 (H4)

JDIMM3 (H5.2)

4 (H9.2)

1

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMC

LA-6601P

12 63Tuesday, November 30, 2010

1

1.0

5

4

3

2

1

+1.5V

12

RD44

1K_0402_1%~D

12

RD45

1K_0402_1%~D

2 (H8) 1 (H4)

3 (H5.2)

RD41 0_0402_5%~DRD41 0_0402_5%~D

+V_DDR_REFB

DDR_B_DQS#[0..7]6,11

DDR_B_DQS[0..7]6,11

D D

C C

B B

DDR_B_D[0..63]6,11

DDR_B_MA[0..15]6,11

+1.5V

1U_0402_6.3V6K~D

CD78

CD79

1

2

+1.5V

10U_0603_6.3V6M~D

CD84

CD83

CD82

1

2

Layout Note: Place near JDIMM4.203,204

+0.75VS

1U_0402_6.3V6K~D

CD92

CD93

1

2

Layout Note: Place near JDIMMB

1U_0402_6.3V6K~D

CD81

CD80

1

2

10U_0603_6.3V6M~D

CD86

CD85

1

2

1U_0402_6.3V6K~D

CD95

CD94

1

2

10U_0603_6.3V6M~D

330U_SX_2VY~D

1

@

CD88

CD87

CD89

1

+

2

10K_0402_5%~D

1 2

2.2U_0603_6.3V6K~D

CD76

1

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

DDR_CKE2_DIMMB6

DDR_B_BS26,11

M_CLK_DDR26 M_CLK_DDR#26

DDR_B_BS06,11

DDR_B_WE#6,11 DDR_B_CAS#6,11

DDR_CS3_DIMMB#6

SA0

SA1

001

DIMM1

1

DIMM2

1

DIMM3

0

1

DIMM4

0

+3VS

12

RD46

@ RD 46

@

RD48

10K_0402_5%~D

RD50

10K_0402_5%~D

1 2

12

RD49

10K_0402_5%~D

+3VS

@RD49

@

12

0.1U_0402_16V4Z~D

CD77

+DIMM4_VREF

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10

DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

+0.75VS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D CD96

CD96

1

2

+1.5V

JDIMM4

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

CD97

GND1

TYCO_2-2013310-1

VREF_CA

Link Done

DQS0#

DQS0

DQ12 DQ13

RESET#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

EVENT#

GND2

+1.5V

2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS DM1

VSS

VSS DM2 VSS

VSS

VDD

A15 A14

VDD

A11

VDD

VDD CK1

VDD BA1

VDD

S0#

VDD

VSS

VSS DM4 VSS

VSS

VSS DM6 VSS

VSS

SDA SCL

VTT

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44 46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE3_DIMMB

74 76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

DDR_B_MA4

92

A4

94

DDR_B_MA2

96

A2

DDR_B_MA0

98

A0

100

M_CLK_DDR3

102

M_CLK_DDR#3

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDR_CS2_DIMMB#

114

M_ODT2

116 118

M_ODT3

120 122

NC

124 126 128

DDR_B_D36

130

DDR_B_D37

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196

M_THERMAL#

198

PCH_SMBDATA

200

PCH_SMBCLK

202 204

+0.75VS

206

CPU

DDR3_DRAMRST# 6,10,11,12

DDR_CKE3_DIMMB 6

M_CLK_DDR3 6 M_CLK_DDR#3 6

DDR_B_BS1 6,11 DDR_B_RAS# 6,11

DDR_CS2_DIMMB# 6 M_ODT2 6

M_ODT3 6

+VREF_CD

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

CD91

CD90

1

2

M_THERMAL# 10,11,12,44

PCH_SMBDATA 5, 10,11,12,16,37,38

PCH_SMBCLK 5,10,11,12,16,37,38

JDIMM4 (H9.2)

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMD

LA-6601P

13 63Tuesday, November 30, 2010

1

1.0

5

PEG_HTX_C_GRX_N[0..15]4

PEG_HTX_C_GRX_P[0..15]4

PEG_GTX_HRX_N[0..15]4

PEG_GTX_HRX_P[0..15]4

D D

+5VMXM

PAD-OPEN 4x4m

+5V_MXM

J12

@J12

@

12

Add R7 increase NV MXM PEG Swing

C C

B B

A A

DGPU_ENVDD26 DGPU_BKL_EN26 VGA_PNL_PWM26

VGA_LCD_DAT26

VGA_LCD_CLK26

LVDS DDC Module have 4.7K Pull-UP

+3V_MXM

SPDIF_OUT34,35

VIN+49

R594 0_0402_5%~DR594 0_0402_5%~D

VIN-49

R596 0_0402_5%~DR596 0_0402_5%~D

PEG_HTX_C_GRX_N[0..15]

PEG_HTX_C_GRX_P[0..15]

PEG_GTX_HRX_N[0..15]

PEG_GTX_HRX_P[0..15]

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~DC70.1U_0402_16V4Z~D

C328

1

C7

2

+5V_MXM

100mil(2.5A, 5VIA)

R7 0_0402_5%~DR7 0_0402_5%~D

1 2

R9 10K_0402_5%~D@R9 10K_0402_5%~D@ R10 36K_0402_1%@R10 36K_0402_1%@

1 2

.1U_0402_16V7K~D

1 2

VGA_DISABLE#

VGA_HDMI_CEC

VGA_LCD_DAT VGA_LCD_CLK

1 2 1 2

PEG_GTX_HRX_N15 PEG_GTX_HRX_P15

PEG_GTX_HRX_N14 PEG_GTX_HRX_P14

PEG_GTX_HRX_N13 PEG_GTX_HRX_P13

PEG_GTX_HRX_N12 PEG_GTX_HRX_P12

PEG_GTX_HRX_N11 PEG_GTX_HRX_P11

PEG_GTX_HRX_N10 PEG_GTX_HRX_P10

PEG_GTX_HRX_N9 PEG_GTX_HRX_P9

PEG_GTX_HRX_N8 PEG_GTX_HRX_P8

PEG_GTX_HRX_N7 PEG_GTX_HRX_P7

PEG_GTX_HRX_N6 PEG_GTX_HRX_P6

PEG_GTX_HRX_N5 PEG_GTX_HRX_P5

PEG_GTX_HRX_N4 PEG_GTX_HRX_P4

PEG_GTX_HRX_N3 PEG_GTX_HRX_P3

C852

@C852

@

+3V_MXM

5

1

2

B+_MXM

JMXM1A

1

PWR_ SRC

3

PWR_ SRC

5

PWR_ SRC

7

PWR_ SRC

9 11 13 15 17

19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161

1

2

3

4

E1 E2

PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC

GND GND GND GND GND

E3 E4

GND GND GND GND 5V 5V 5V 5V 5V GND GND GND GND PEX_STD _SW# VGA_DISAB LE# PNL_PW R_EN PNL_BL_ EN PNL_BL_ PWM HDMI_CEC DVI_HPD LVDS_DD C_DAT LVDS_DD C_CLK GND OEM OEM OEM OEM GND PEX_RX1 5# PEX_RX1 5 GND PEX_RX1 4# PEX_RX1 4 GND PEX_RX1 3# PEX_RX1 3 GND PEX_RX1 2# PEX_RX1 2 GND PEX_RX1 1# PEX_RX1 1 GND PEX_RX1 0# PEX_RX1 0 GND PEX_RX9 # PEX_RX9 GND PEX_RX8 # PEX_RX8 GND PEX_RX7 # PEX_RX7 GND PEX_RX6 # PEX_RX6 GND PEX_RX5 # PEX_RX5 GND PEX_RX4 # PEX_RX4 GND PEX_RX3 # PEX_RX3 GND

JAE_MM70-314-310B1-1

CONN@

U51

VIN+ VINGND VS

INA219AIDCNRG4_SOT23-8

VGA_LCD_CLK VGA_LCD_DAT DGPU_PWROK VGA_HDMI_CEC VGA_DISABLE# VGA_WAKE#

PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC PWR_ SRC

PRSNT_R #

PWR_ GOOD

PWR_ LEVEL TH_OVER T#

TH_ALER T#

PEX_TX1 5#

PEX_TX1 5

PEX_TX1 4#

PEX_TX1 4

PEX_TX1 3#

PEX_TX1 3

PEX_TX1 2#

PEX_TX1 2

PEX_TX1 1#

PEX_TX1 1

PEX_TX1 0#

PEX_TX1 0

PEX_TX9 #

PEX_TX8 #

PEX_TX7 #

PEX_TX6 #

PEX_TX5 #

PEX_TX4 #

PEX_TX3 #

Link Done

8

A1

7

A0

6

SDA

5

SCL

SMB_DAT SMB_CLK

4

R13 4.3K_0402_5%R13 4.3K_0402_5%

1 2

R14 4.3K_0402_5%R14 4.3K_0402_5%

1 2

R15

R15 R18 10K_0402_5%~DR18 10K_0402_5%~D

1 2

R19 10K_0402_5%~D@R19 10K_0402_5%~D@

1 2

R20 10K_0402_5%~D@R20 10K_0402_5%~D@

1 2

2 4 6 8 10 12 14 16 18

20

GND

22

GND

24

GND

26

GND

28

GND

30

GND

32

GND

34

GND

36

GND

38 40

WAKE #

42 44

PWR_ EN

46

RSVD

48

RSVD

50

RSVD

52

RSVD

54 56 58 60

TH_PW M

62

GPIO0

64

GPIO1

66

GPIO2

68 70 72

GND

74

OEM

76

OEM

78

OEM

80

OEM

82

GND

84 86 88

GND

90 92 94

GND

96 98 100

GND

102 104 106

GND

108 110 112

GND

114 116 118

GND

120 122

PEX_TX9

124

GND

126 128

PEX_TX8

130

GND

132 134

PEX_TX7

136

GND

138 140

PEX_TX6

142

GND

144 146

PEX_TX5

148

GND

150 152

PEX_TX4

154

GND

156 158

PEX_TX3

160

GND

For B+_MXM slave address : 1000010 please placemnet near R-sense

B+_MXM_A1 B+_MXM_A0 MXM_CURI2C_DATA MXM_CURI2C_CLK

4

10K_0402_5%~D

12

400mil(10A)

10U_1206_25V6M~DC210U_1206_25V6M~D

1

C2

2

VGA_PRSNT_R# VGA_WAKE# DGPU_PWROK VGA_ON

AC_BATT# VGA_TH_OVERT#

1 2

R8 10K_0402_5%~DR8 10K_0402_5%~D

VGA_SMB_DA1 VGA_SMB_CK1

SYSTEM

PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P11

PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P10

PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P3

680P_0603_50V7K~DC3680P_0603_50V7K~D

68P_0402_50V8J~DC468P_0402_50V8J~D

C3

1

2

ACIN17,41,44,50

EC_AC_BAT#44

VGA_PRSNT_R# 19

DGPU_PWROK 19 VGA_ON 16

R6940_0402_5%~D R6940_0402_5%~D

12

R6930_0402_5%~D R6930_0402_5%~D

12

MXM_CURI2C_CLK MXM_CURI2C_DATA VGA_DDC_DATA VGA_DDC_CLK

AC_BATT#

B+_MXM

0.1U_0603_25V7K~DC10.1U_0603_25V7K~D

2

C4

C1

1

2

+3V_MXM

R682

10K_0402_5%~D

1 2

B+_MXM_A0

R692

10K_0402_5%~D

1 2

+3V_MXM

R681

@R681

@

10K_0402_5%~D

1 2

B+_MXM_A1

R691

10K_0402_5%~D

1 2

VGA_SMB_DA1 VGA_SMB_CK1

3

R1818 3.3K_0402_5%@ R1818 3.3K_0402_5%@

1 2

R1819 3.3K_0402_5%@ R1819 3.3K_0402_5%@

1 2

R23 4.3K_0402_5%R23 4.3K_0402_5%

1 2

R24 4.3K_0402_5%R24 4.3K_0402_5%

1 2

R1816 10K_0402_5%~DR1816 10K_0402_5%~D

+3VALW

1

C1823

0.1U_0402_25V6K~D

2

5

U622

B

A

3

1

2

AC_BATT#

4

VCC

Y

G

MC74VHC1G09DFT2G_SC70-5

CLK_PEG_PCH#16 CLK_PEG_PCH16

J13

@J13

@

4.7U_0805_10V4Z~DC54.7U_0805_10V4Z~D

C5

12

PAD-OPEN 4x4m

HDMI

@R692

@

+3VMXM

+3V_MXM

12

VGA_TH_OVERT#

R5 0_0402_5%~DR5 0_0402_5%~D

1 2

R6 0_0402_5%~DR6 0_0402_5%~D

1 2

VGA_TZCLK-25 VGA_TZCLK+25

VGA_TZOUT2-25

LVDS

DMC

VGA_TZOUT2+25

VGA_TZOUT1-25 VGA_TZOUT1+25

VGA_TZOUT0-25 VGA_TZOUT0+25

GPU_HDMI_TXD2-28 GPU_HDMI_TXD2+28

GPU_HDMI_TXD1-28 GPU_HDMI_TXD1+28

GPU_HDMI_TXD0-28 GPU_HDMI_TXD0+28

GPU_HDMI_TXC-28 GPU_HDMI_TXC+28

GPU_HDMI_SDATA28

GPU_HDMI_SCLK28

VGA_DPD_N030 VGA_DPD_P030

VGA_DPD_N130 VGA_DPD_P130

VGA_DPD_N230 VGA_DPD_P230

VGA_DPD_N330 VGA_DPD_P330

VGA_DPD_AUXN/DDC30 VGA_DPD_AUXP/DDC30

VGA_PRSNT_L#19

+3V_MXM

10K_0402_5%~D

12

R11

S

SSM3K7002F_SC59-3~D

PEG_GTX_HRX_N2 PEG_GTX_HRX_P2

PEG_GTX_HRX_N1 PEG_GTX_HRX_P1

PEG_GTX_HRX_P0

CLK_PEG_PCH#_R CLK_PEG_PCH_R

VGA_TZCLKVGA_TZCLK+

VGA_TZOUT2VGA_TZOUT2+

VGA_TZOUT1VGA_TZOUT1+

VGA_TZOUT0VGA_TZOUT0+

GPU_HDMI_TXD2GPU_HDMI_TXD2+

GPU_HDMI_TXD1GPU_HDMI_TXD1+

GPU_HDMI_TXD0GPU_HDMI_TXD0+

GPU_HDMI_TXCGPU_HDMI_TXC+

GPU_HDMI_SDATA GPU_HDMI_SCLK

VGA_DPD_N0 VGA_DPD_P0

VGA_DPD_N1 VGA_DPD_P1

VGA_DPD_N2 VGA_DPD_P2

VGA_DPD_N3 VGA_DPD_P3

+3VALW

G

2

D

13

Q3

(Pull-UP 10K at PCH)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT .

3

2

10K_0402_5%~D

12

R16

TH_OVERT# 44

JMXM1B

163

GND

165

PEX_RX2 #

167

PEX_RX2

169

GND

171

PEX_RX1 #

173

PEX_RX1

175

GND

177

PEX_RX0 #

179

PEX_RX0

181

GND

183

PEX_REF CLK#

185

PEX_REF CLK

187

GND

189

RSVD

191

RSVD

193

RSVD

195

RSVD

197

RSVD

199

LVDS_UC LK#

201

LVDS_UC LK

203

GND

205

LVDS_UT X3#

207

LVDS_UT X3

209

GND

211

LVDS_UT X2#

213

LVDS_UT X2

215

GND

217

LVDS_UT X1#

219

LVDS_UT X1

221

GND

223

LVDS_UT X0#

225

LVDS_UT X0

227

GND

229

DP_C_L0 #

231

DP_C_L0

233

GND

235

DP_C_L1 #

237

DP_C_L1

239

GND

241

DP_C_L2 #

243

DP_C_L2

245

GND

247

DP_C_L3 #

249

DP_C_L3

251

GND

253

DP_C_AU X#

255

DP_C_AU X

257

RSVD

259

RSVD

261

RSVD

263

RSVD

265

RSVD

267

RSVD

269

RSVD

271

RSVD

273

RSVD

275

RSVD

277

RSVD

279

RSVD

281

GND

283

DP_A_L0 #

285

DP_A_L0

287

GND

289

DP_A_L1 #

291

DP_A_L1

293

GND

295

DP_A_L2 #

297

DP_A_L2

299

GND

301

DP_A_L3 #

303

DP_A_L3

305

GND

307

DP_A_AU X#

309

DP_A_AU X

310

PRSNT_L #

311

GND

JAE_MM70-314-310B1-1

CONN@

2

PEX_CLK _REQ#

VGA_DDC _DAT VGA_DDC _CLK

Link Done

1

+3V_MXM+3V_MXM

+3V_MXM

12

2

G

D

S

D

S

EC_SMB_DA144,48

EC_SMB_CK144,48

GND

PEX_TX2 #

PEX_TX2

GND

PEX_TX1 #

PEX_TX1

GND

PEX_TX0 #

PEX_TX0

GND

PEX_RST #

VGA_VSYNC VGA_HSYNC

GND

VGA_RED

VGA_GRE EN

VGA_BLU E

GND

LVDS_LC LK#

LVDS_LC LK

GND

LVDS_LT X3#

LVDS_LT X3

GND

LVDS_LT X2#

LVDS_LT X2

GND

LVDS_LT X1#

LVDS_LT X1

GND

LVDS_LT X0#

LVDS_LT X0

GND

DP_D_L0 #

DP_D_L0

GND

DP_D_L1 #

DP_D_L1

GND

DP_D_L2 #

DP_D_L2

GND

DP_D_L3 #

DP_D_L3

GND

DP_D_AU X#

DP_D_AU X DP_C_HP D DP_D_HP D

RSVD RSVD RSVD

GND

DP_B_L0 #

DP_B_L0

GND

DP_B_L1 #

DP_B_L1

GND

DP_B_L2 #

DP_B_L2

GND

DP_B_L3 #

DP_B_L3

GND

DP_B_AU X#

DP_B_AU X DP_B_HP D DP_A_HP D

GND

162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306

3V3

308

3V3

312

1 3

Q1

SSM3K7002F_SC59-3~D

PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_N0PEG_GTX_HRX_N0 PEG_HTX_C_GRX_P0

PEG_CLKREQ# PLTRST_VGA# VGA_DDC_DATA VGA_DDC_CLK VGA_CRT_VSYNC VGA_CRT_HSYNC

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_TXCLKVGA_TXCLK+

VGA_TXOUT2VGA_TXOUT2+

VGA_TXOUT1VGA_TXOUT1+

VGA_TXOUT0VGA_TXOUT0+

MXM_TX0N MXM_TX0P

MXM_TX1N MXM_TX1P

MXM_TX2N MXM_TX2P

MXM_TX3N MXM_TX3P

MXM_DPB_AUXN/DDC MXM_DPB_AUXP/DDC VGA_HDMI_DET MXM_DPB_HPD

VGA_DPC_N0 VGA_DPC_P0

VGA_DPC_N1 VGA_DPC_P1

VGA_DPC_N2 VGA_DPC_P2

VGA_DPC_N3 VGA_DPC_P3

VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC VGA_DPC_HPD VGA_DMC_HPD

+3V_MXM

40mil(1A)

2

G

D

S

D

S

1 3

Q2

SSM3K7002F_SC59-3~D

PEG_CLKREQ# 16 PLTRST_VGA# 18

VGA_DDC_DATA 27

VGA_DDC_CLK 27 VGA_CRT_VSYNC 27 VGA_CRT_HSYNC 27

VGA_CRT_R 27 VGA_CRT_G 27 VGA_CRT_B 27

VGA_TXCLK- 25 VGA_TXCLK+ 25

VGA_TXOUT2- 25 VGA_TXOUT2+ 25

VGA_TXOUT1- 25 VGA_TXOUT1+ 25

VGA_TXOUT0- 25 VGA_TXOUT0+ 25

MXM_TX0N 23 MXM_TX0P 23

MXM_TX1N 23 MXM_TX1P 23

MXM_TX2N 23 MXM_TX2P 23

MXM_TX3N 23 MXM_TX3P 23

MXM_DPB_AUXN/DDC 23

MXM_DPB_AUXP/DDC 23 VGA_HDMI_DET 28 MXM_DPB_HPD 23

VGA_DPC_N0 29 VGA_DPC_P0 29

VGA_DPC_N1 29 VGA_DPC_P1 29

VGA_DPC_N2 29 VGA_DPC_P2 29

VGA_DPC_N3 29 VGA_DPC_P3 29

VGA_DPC_AUXN/DDC 29

VGA_DPC_AUXP/DDC 29 VGA_DPC_HPD 29 VGA_DMC_HPD 30

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

MXMIII Connector A

LA-6601P

1

4.7K_0402_5%~DR24.7K_0402_5%~D

4.7K_0402_5%~DR14.7K_0402_5%~D

12

R1

R2

VGA_SMB_DA1

VGA_SMB_CK1

CRT

LVDS

eDP

mDP

1.0

14 63Tuesday, November 30, 2010

1.0

5

D D

+RTCVCC

1M_0402_5%~D

W=20mils

2

W=20mils

1 2

3

RH55

1K_0402_5%~D

SM_INTRUDER#

+RTCVCC

RH25 20K_0402_5%~DRH25 20K_0402_5%~D

+CHGRTC

+RTCBATT

HDA_SDOUT

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1M_0402_5%~D

12

R1960

RH36 0_0402_5%~D

1 2

PCH_SPI_CS# PCH_SPI_SO PCH_SPI_SO_R

1 2

RH23 20K_0402_5%~DRH23 20K_0402_5%~D

1 2

+5VS

G

2

HDA_SYNC

13

D

S

D

S

QH1

BSS138_SOT23~D

@

1 2

RH5351_0402_5% RH5351_0402_5%

12

RH40200_0402_5% @ RH40200_0402_5% @

RH39200_0402_5% @ RH39200_0402_5% @

RH38200_0402_5% @ RH38200_0402_5% @

100_0402_1%~D

12

RH46

RH58

0_0402_5%~D

1 2

RH62

0_0402_5%~D

SPI BIOS Pinout

(1)CS# (5)DIO (2)DO (6)CLK (3)WP# (7)HOLD # (4)GND (8)VCC

W25X32

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TMS

PCH_JTAG_TDO

100_0402_1%~D

12

RH45

+3V_PCH

3.3K_0402_5%

RH57

1 2

RH11

+RTCVCC

C C

HDA_SDOUT_AUDIO34

HDA_BITCLK_AUDIO34

HDA_RST_AUDIO#34

HDA_SYNC_AUDIO34

B B

A A

RTC Battery

W=20mils

1

1U_0603_10V4Z~D

CH7

1

CHN202UPT_SC70-3

2

RH30 33_0402_5%~DRH30 33_0402_5%~D

RH27 33_0402_5%~DRH27 33_0402_5%~D

RH28 33_0402_5%~DRH28 33_0402_5%~D

RH33 33_0402_5%~DRH33 33_0402_5%~D

+3V_PCH

PCH_SPI_CLK

RH59

@

33_0402_5%~D

1 2

22P_0402_50V8J~D

1

@

CH8

2

Reserve for EMI please close to U48

DH1

1 2

5

4

CMOS

1

12

COMS1

@COMS1

CH4

1U_0603_10V4Z~D

CH5

1U_0603_10V4Z~D

100_0402_1%~D

12

RH44

@

PCH_SPI_CS#_R

PCH_SPI_WP#

2

1

2

CLP1 & CLP2 place near DIMM

HDA_SDO44

+3V_PCH

@

SHORT PADS

12

ME1

@ME1

@

SHORT PADS

ME CMOS

HDA_SPKR34

HDA_SDIN034

1 2

RH50 0_0402_5%~DRH50 0_0402_5%~D

EDP_DETECT#25

PCH_JTAG_TCK5

PCH_JTAG_TMS5

PCH_JTAG_TDI5

PCH_JTAG_TDO5

RH54 3.3K_0402_5%RH54 3.3K_0402_5%

1 2

RH56 3.3K_0402_5%RH56 3.3K_0402_5%

1 2

U48

1

CS#

VCC

2

DO

HOLD#

3

WP#

CLK

4

GND

DI

W25Q32BVSSIG_SO8

SPI ROM FOR ME ( 4MByte )

4

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

EDP_DETECT#

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_HOLD#

8 7 6 5

HDA_SDOUT

PCH_SPI_WP#

PCH_SPI_HOLD# PCH_SPI_CLK_R

PCH_SPI_SI_R

0_0402_5%~D

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CougarPoint_Rev_1p0

1 2

PCH_SPI_CLK

RH6015_0402_5%~D RH6015_0402_5%~D

PCH_SPI_SI

RH61

3

CH218P_0402_50V8J~D CH218P_0402_50V8J~D

12

10M_0402_5%~D

12

RH2

CH318P_0402_50V8J~D CH318P_0402_50V8J~D

12

LPC_AD0

C38

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

JTAG

SPI

3

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

+3V_PCH

0.1U_0402_16V4Z~D

CH6

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

LPC_AD0 44 LPC_AD1 44 LPC_AD2 44 LPC_AD3 44

LPC_FRAME# 44

SERIRQ 44

SATA_PRX_DTX_N1 36 SATA_PRX_DTX_P1 36

SATA_PTX_DRX_N1 36 SATA_PTX_DRX_P1 36

SATA_PRX_DTX_N0 36 SATA_PRX_DTX_P0 36

SATA_PTX_DRX_N0 36 SATA_PTX_DRX_P0 36

SATA_PRX_DTX_N2 37 SATA_PRX_DTX_P2 37

SATA_PTX_DRX_N2 37 SATA_PTX_DRX_P2 37

SATA_PRX_DTX_N4 40 SATA_PRX_DTX_P4 40

SATA_PTX_DRX_N4 40 SATA_PTX_DRX_P4 40

1 2

RH41 37.4_0402_1%RH41 37.4_0402_1%

1 2

RH43 49.9_0402_1%RH43 49.9_0402_1%

1 2

RH48 750_0402_1%RH48 750_0402_1%

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_SATALED# 42

2

PCH_RTCX2

PCH_RTCX1

HDD2

HDD1

ODD

E-SATA

2

YH1

4

1

Far away hot sp ot

3

OSC

NC

2

OSC

NC

32.768KHZ_12.5PF_Q13MC14610002

1

SERIRQ

PCH_GPIO21

PCH_SATALED#

BBS_BIT0_R

INTVRMEN

H：Integrated VRM enable

*

L： Integrated VRM disable

HDA_SPKR

HDA_SDOUT

HDA_SDO

ME debug mode , this signal has a weak internal PD L=>security measures defined in the Flash

Descriptor will be in effect (default) H=>Flash Descriptor Security will be overridden

HDA_SYNC

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Huron River platfrom

+3V_PCH

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

RH32 10K_0402_5%~DRH32 10K_0402_5%~D

RH35 10K_0402_5%~DRH35 10K_0402_5%~D

RH47 10K_0402_5%~DRH47 10K_0402_5%~D

+RTCVCC

12

330K_0402_5%

PCH_INTVRMEN

330K_0402_5%

1 2

LOW=Default HIGH=No Reboot

RH42 1K_0402_5%~D@RH42 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

1 2

RH521K_0402_5%~D RH521K_0402_5%~D

12

HDA_SYNC

RH37 1K_0402_5%~D@RH37 1K_0402_5%~D@

*

12

@RH34

@

RH31

RH34

+3VS

+3V_PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-6601P

1

15 63Tuesday, November 30, 2010

+3VS

1.0

5

PCIE_PRX_GLANTX_N333

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

USB 3.0 --->

C C

PCIE_PRX_GLANTX_P333

PCIE_PTX_GLANRX_N333 PCIE_PTX_GLANRX_P333

PCIE_PRX_WANTX_N238 PCIE_PRX_WANTX_P238

PCIE_PTX_WANRX_N238 PCIE_PTX_WANRX_P238

PCIE_PRX_WLANTX_N138 PCIE_PRX_WLANTX_P138

PCIE_PTX_WLANRX_N138 PCIE_PTX_WLANRX_P138

PCIE_PRX_CARDTX_N435 PCIE_PRX_CARDTX_P435

PCIE_PTX_CARDRX_N435 PCIE_PTX_CARDRX_P435

PCIE_PRX_USB3TX_N639 PCIE_PRX_USB3TX_P639

PCIE_PTX_USB3RX_N639 PCIE_PTX_USB3RX_P639

10/100/1G LAN --->

CLK_PCIE_MINI2#38

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

CLK_PCIE_MINI238

CLK_PCIE_MINI1#38 CLK_PCIE_MINI138

Card Reader --->

B B

CLK_PCIE_USB30#39 CLK_PCIE_USB3039

USB 3.0 --->

CLK_CPU_ITP#5 CLK_CPU_ITP5

CLK_RES_ITP#7 CLK_RES_ITP7

XTAL25_IN

1

2

12P_0402_50V8J~D

CH24

XTAL25_OUT

RH117

12

1M_0402_5%~D

A A

1M_0402_5%~D

YH2

1 2

25MHZ_12PF_X5H025000DC1H-H

12P_0402_50V8J~D

CH23

1

2

5

+3V_PCH

CLK_PCIE_LAN#33 CLK_PCIE_LAN33

+3VS

LANCLK_REQ#33

MINI2CLK_REQ#38

+3V_PCH

MINI1CLK_REQ#38

CLK_PCIE_CD#35 CLK_PCIE_CD35

+3V_PCH

CDCLK_REQ#35

+3V_PCH

USB30_CLKREQ#39

+3V_PCH

VGA_ON14

CLK_CPU_ITP# CLK_CPU_ITP

CLK_RES_ITP# CLK_RES_ITP

+3VS

CH9 0.1U_0402_10V7K~DCH9 0.1U_0402_10V7K~D

1 2

CH14 0.1U_0402_10V7K~DCH14 0.1U_0402_10V7K~D

1 2

CH10 0.1U_0402_10V7K~DCH10 0.1U_0402_10V7K~D

1 2

CH15 0.1U_0402_10V7K~DCH15 0.1U_0402_10V7K~D

1 2

CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH12 0.1U_0402_10V7K~DCH12 0.1U_0402_10V7K~D

1 2

CH13 0.1U_0402_10V7K~DCH13 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~DCH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~DCH20 0.1U_0402_10V7K~D

1 2

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

RH93 0_0402_5%~DRH93 0_0402_5%~D RH94 0_0402_5%~DRH94 0_0402_5%~D RH95 10K_0402_5%~D@ RH95 10K_0402_5%~D@

RH96 0_0402_5%~DRH96 0_0402_5%~D RH97 0_0402_5%~DRH97 0_0402_5%~D RH100 10K_0402_5%~DRH100 10K_0402_5%~D

RH101 0_0402_5%~DRH101 0_0402_5%~D RH102 0_0402_5%~DRH102 0_0402_5%~D RH103 10K_0402_5%~DRH103 10K_0402_5%~D

RH104 0_0402_5%~DRH104 0_0402_5%~D RH106 0_0402_5%~DRH106 0_0402_5%~D RH107 10K_0402_5%~DRH107 10K_0402_5%~D

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

RH112 10K_0402_5%~DRH112 10K_0402_5%~D

RH114 0_0402_5%~DRH114 0_0402_5%~D RH115 0_0402_5%~DRH115 0_0402_5%~D RH116 10K_0402_5%~DRH116 10K_0402_5%~D

RH118 10K_0402_5%~D@RH118 10K_0402_5%~D@

RH119 0_0402_5%~DRH119 0_0402_5%~D RH120 0_0402_5%~DRH120 0_0402_5%~D

RH121 0_0402_5%~D@RH121 0_0402_5%~D@ RH122 0_0402_5%~D@RH122 0_0402_5%~D@

1 2

1 2 1 2 1 2

1 2

12 12 12

12 12

4

PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3 PCIE_PTX_GLANRX_N3_C PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2 PCIE_PTX_WANRX_N2_C PCIE_PTX_WANRX_P2_C

PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1 PCIE_PTX_WLANRX_N1_C PCIE_PTX_WLANRX_P1_C

PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

PCIE_PRX_USB3TX_N6 PCIE_PRX_USB3TX_P6 PCIE_PTX_USB3RX_N6_C PCIE_PTX_USB3RX_P6_C

4

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

PCIECLKREQ0#

PCIE_LAN# PCIE_LAN

LANCLK_REQ#

PCIE_MINI2# PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI1# PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD# PCIE_CD

CDCLK_REQ#

PEG_B_CLKREQ#

PCIE_USB30# PCIE_USB30

USB30_CLKREQ#

VGA_ON

CLK_BCLK_ITP# CLK_BCLK_ITP

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_1p0

CLK_PCH_14M CLK_PCI_LPBACK

33_0402_5%~D

RH86

@

1 2

1

2

Reserve for EMI please close t o UH1

3

PCH_LID_SW_IN# LID_SW_IN#

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

PCI-E*

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

33_0402_5%~D

RH89

@

22P_0402_50V8J~D

CH21

1 2

22P_0402_50V8J~D

@

22P_0402_50V8J~D

@

CH22

1

2

CLKOUT_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

CLKOUT_DP_N CLKOUT_DP_P

E12

SMBCLK

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT .

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

P10

PEG_CLKREQ#_R

M10

CLK_PEG_PCH#

AB37

CLK_PEG_PCH

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

CLK_CPU_DPLL#

AM12

CLK_CPU_DPLL

AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

KB_DET#

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

GPIO74

1 2

MEMORY

DRAMRST_CNTRL_PCH 6

RH87

10K_0402_5%~D

CLK_PEG_PCH# 14 CLK_PEG_PCH 14

CLK_CPU_DMI# 5 CLK_CPU_DMI 5

CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5

CLK_PCI_LPBACK 18

1 2

RH113 90.9_0402_1%RH113 90.9_0402_1%

KB_DET# 46

DMC_PCH_DET# 38

BT_DET# 38

CAM_DET# 24,26

2

EC_LID_OUT#

RH680_0402_5%~D RH680_0402_5%~D

RH710_0402_5%~D @RH710_0402_5%~D @

+3V_PCH

12

10K_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

VGA

DMN66D0LDW-7_SOT363-6~D

+1.05VS_VCCDIFFCLKN

2

EC_LID_OUT# 44

LID_SW_IN# 41,42,44

+3V_MXM

12

R21

2

G

QH2A

6

D

12

RH92

@RH92

@

10K_0402_5%~D

QH3A

SMBCLK

SMBDATA

SMBCLK

SMBDATA

SML0CLK

SML0DATA

DRAMRST_CNTRL_PCH

GPIO74

SML1CLK

SML1DATA

+3V_MXM

12

RH85

1K_0402_5%~D

5

G

3

4

D

S

QH2B

1 2

5

3

D

RH111

1 2

0_0402_5%~D

G

@RH111

@

QH2B

RH900_0402_5%~D @RH900_0402_5%~D @

+3VS

2.2K_0402_5%~D

RH98

1 2

QH3B

DMN66D0LDW-7_SOT363-6~D

4

S

RH76 10K_0402_5%~DRH76 10K_0402_5%~D

1 2

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

1 2

RH78 10K_0402_5%~DRH78 10K_0402_5%~D

1 2

RH79 10K_0402_5%~DRH79 10K_0402_5%~D

1 2

RH80 10K_0402_5%~DRH80 10K_0402_5%~D

1 2

RH81 10K_0402_5%~DRH81 10K_0402_5%~D

1 2

RH82 10K_0402_5%~DRH82 10K_0402_5%~D

1 2

RH83 10K_0402_5%~DRH83 10K_0402_5%~D

1 2

RH84 10K_0402_5%~DRH84 10K_0402_5%~D

1 2

DMN66D0LDW-7_SOT363-6~D

1

S

+3VS

2

G

6

1

D

S

RH105

@RH105

@

1 2

0_0402_5%~D

KB_DET#

CAM_DET#

DMC_PCH_DET#

BT_DET#

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

1

PEG_CLKREQ# 14

12

RH88

@RH88

@

10K_0402_5%~D

2.2K_0402_5%~D

RH99

1 2

PCH_SMBCLK 5,10,11,12,13,37,38

PCH_SMBDATA 5,10,11,12,13,37,38

R1745100K_0402_5%~D R1745100K_0402_5%~D

1 2

RH16610K_0402_5%~D RH16610K_0402_5%~D

1 2

RH10910K_0402_5%~D RH10910K_0402_5%~D

1 2

RH10810K_0402_5%~D RH10810K_0402_5%~D

1 2

LA-6601P

1

1 2

+3VS

16 63Tuesday, November 30, 2010

+3V_PCH

RH672.2K_0402_5%~D RH672.2K_0402_5%~D

RH692.2K_0402_5%~D RH692.2K_0402_5%~D

RH702.2K_0402_5%~D RH702.2K_0402_5%~D

RH722.2K_0402_5%~D RH722.2K_0402_5%~D

RH751K_0402_5%~D RH751K_0402_5%~D

RH16710K_0402_5%~D RH16710K_0402_5%~D

RH742.2K_0402_5%~D RH742.2K_0402_5%~D

RH732.2K_0402_5%~D RH732.2K_0402_5%~D

1.0

5

UH1C

D D

C C

B B

A A

DMI_CTX_PRX_N04 DMI_CTX_PRX_N14 DMI_CTX_PRX_N24 DMI_CTX_PRX_N34

DMI_CTX_PRX_P04 DMI_CTX_PRX_P14 DMI_CTX_PRX_P24 DMI_CTX_PRX_P34

DMI_CRX_PTX_N04 DMI_CRX_PTX_N14 DMI_CRX_PTX_N24 DMI_CRX_PTX_N34

DMI_CRX_PTX_P04 DMI_CRX_PTX_P14 DMI_CRX_PTX_P24 DMI_CRX_PTX_P34

+1.05VS

SG_AMD_BKL26,44

XDP_DBRESET#5

SYSTEM_PWROK5,44

PCH_PWROK5,44

PCH_APWROK44

PM_DRAM_PWR GD5

PCH_RSMRST#44

SUSWARN#44

PBTN_OUT#5,44

R1899

10K_0402_5%

2

ACIN14,41,44,50

QH11A

DMN66D0LDW-7_SOT363-6~D

QH11A

G

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

RH124 49.9_0402_1%RH124 49.9_0402_1%

1 2

RH125 750_0402_1%~DRH12 5 750_0 402_1%~D

4mil width and place within 500mil of the PCH

1 2

RH127 0_0402_5%~D@ RH127 0_0402_5%~D@

XDP_DBRESET#

1 2

RH129 0_0402_5%~DRH129 0_0402_5%~D

1 2

RH130 0_0402_5%~DRH130 0_0402_5%~D

1 2

RH131 0_0402_5%~DRH131 0_0402_5%~D

PM_DRAM_PWR GD

1 2

RH133 0_0402_5%~DRH133 0_0402_5%~D

1 2

RH134 0_0402_5%~D@ RH134 0_0402_5%~D@

1 2

RH135 0_0402_5%~DRH135 0_0402_5%~D

+3V_PCH

12

R1900

12

6

D

S

1

R1900 10K_0402_5%

10K_0402_5%

3

D

5

G

S

4

DMI_IRCOMP

RBIAS_CPY

SUSACK#_R

PM_PWROK_R

PCH_RSMRST#_R

GPIO30

PBTN_OUT#_R

ACIN_PCH

BATLOW#

RI#

ACIN_PCH

DMN66D0LDW-7_SOT363-6~D

GPIO3028

QH11B

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

CougarPoint_Rev_1p0

BATLOW#

RI#

WAKE#

GPIO30

RH143 10K_0402_5%~DRH143 10K_0402_5%~D

RH145 10K_0402_5%~DRH145 10K_0402_5%~D

RH146 1K_0402_5%~DRH146 1K_0402_5%~D

RH154 10K_0402_5%~D@RH154 10K_0402_5%~D@

1 2

4

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

+3V_PCH

FDI_CTX_PRX_N0

BJ14

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWODVREN

A18

PCH_DPWROK_R

E22

WAKE#

B9

N3

SUS_STAT#

G8

SUSCLK

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN - On Die DSW VR Enable

H：Enable

*

L：Disable

RH126 0_0402_5%~DRH126 0_0402_5%~D

RH159 0_0402_5%~D@RH159 0_0402_5%~D@

1 2

RH128 0_0402_5%~DRH128 0_0402_5%~D

PM_CLKRUN#

RH132 0_0402_5%~DRH132 0_0402_5%~D

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

DSWODVREN

12

If not using in tegrated LAN,signal may be left as NC.

FDI_CTX_PRX_N0 4 FDI_CTX_PRX_N1 4 FDI_CTX_PRX_N2 4 FDI_CTX_PRX_N3 4 FDI_CTX_PRX_N4 4 FDI_CTX_PRX_N5 4 FDI_CTX_PRX_N6 4 FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4 FDI_CTX_PRX_P1 4 FDI_CTX_PRX_P2 4 FDI_CTX_PRX_P3 4 FDI_CTX_PRX_P4 4 FDI_CTX_PRX_P5 4 FDI_CTX_PRX_P6 4 FDI_CTX_PRX_P7 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

1 2

T76 PAD~D@T76 PAD~D@

PM_SLP_S5# 41,44

PM_SLP_S4# 44

PM_SLP_S3# 41,44

PM_SLP_SUS# 44

H_PM_SYNC 5

+RTCVCC

12

RH147

RH147 330K_0402_5%

330K_0402_5%

@ RH151

@

330K_0402_5%

1 2

PCIE_WAKE# 33,38,39,44

SUSCLK_R 44

RH151

3

IGPU_BKLT_EN26

PCH_ENVDD26,44

PCH_INV_PWM26

PCH_LCD_CLK26

PCH_LCD_DATA26

RH144 2.37K_0402_1%~DRH144 2.37K_0402_1%~D

12

Minimum speacing of 20mils for LVD_IBG

PCH_TXCLK-25 PCH_TXCLK+25

PCH_TXOUT0-25 PCH_TXOUT1-25 PCH_TXOUT2-25

PCH_TXOUT0+25 PCH_TXOUT1+25 PCH_TXOUT2+25

PCH_RSMRST#_R

PCH_DPWROK 44

PCH_CRT_HSYNC27 PCH_CRT_VSYNC27

Can be left NC when IAMT is not support on the platfrom

+3VS

RH148 2.2K_0402_5%~DRH148 2.2K_0402_5%~D

RH152 2.2K_0402_5%~DRH152 2.2K_0402_5%~D

RH155 2.2K_0402_5%~DRH155 2.2K_0402_5%~D

RH157 2.2K_0402_5%~DRH157 2.2K_0402_5%~D

R78 8.2K_0402_5%@R78 8.2K_0402_5%@

RV1 2.2K_0402_5%~DRV1 2.2K_0402 _5%~D

RV2 2.2K_0402_5%~DRV2 2.2K_0402 _5%~D

PCH_TZCLK-25 PCH_TZCLK+25

PCH_TZOUT0-25 PCH_TZOUT1-25 PCH_TZOUT2-25

PCH_TZOUT0+25 PCH_TZOUT1+25 PCH_TZOUT2+25

PCH_CRT_BLU27 PCH_CRT_GRN27 PCH_CRT_RED27

PCH_CRT_DDC_CLK27

PCH_CRT_DDC_DAT27

RH136 33_0402_5%~DRH136 33_0402_5%~D

1 2

RH138 33_0402_5%~DRH138 33_0402_5%~D

1 2

1K_0402_0.5%~D

1 2

CTRL_CLK CTRL_DATA

LVDS_IBG

PCH_TXCLKPCH_TXCLK+

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

PCH_TZCLKPCH_TZCLK+

PCH_TZOUT0PCH_TZOUT1PCH_TZOUT2-

PCH_TZOUT0+ PCH_TZOUT1+ PCH_TZOUT2+

PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED

PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT

CRT_IREF

12

RH140

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

PCH_LCD_CLK

PCH_LCD_DATA

HSYNC VSYNC

2

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CougarPoint_Rev_1p0

1 2

R1696 10K_0402_5%~DR1696 10K_0402_5%~D

1 2

RH142 110K_0402_1%~DRH142 110K_0402_1%~D

1 2

RH149 150_0402_1%RH149 150_0402_1%

1 2

RH153 150_0402_1%RH153 150_0402_1%

1 2

RH156 150_0402_1%RH156 150_0402_1%

1 2

RH158 100K_0402_5%~DRH158 100K_0402_5%~D

1 2

RH123 100K_0402_5%~DRH123 100K_0402_5%~D

1 2

R1697 10K_0402_5%~DR1697 10K_0402_5%~D

LVDS

Digital Display Interface

CRT

PM_CLKRUN#

TMDS_B_HPD

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

PCH_ENVDD

IGPU_BKLT_EN

PCH_RSMRST#

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

HDMI

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

mDP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DMC HDMI

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

HDMICLK_NB HDMIDAT_NB

TMDS_B_HPD

TMDS_B_DATA2# TMDS_B_DATA2 TMDS_B_DATA1# TMDS_B_DATA1 TMDS_B_DATA0# TMDS_B_DATA0 TMDS_B_CLK# TMDS_B_CLK

PCH_DPC_CLK PCH_DPC_DAT

PCH_DPC_AUXN PCH_DPC_AUXP DP_HPD

PCH_DPC_N0 PCH_DPC_P0 PCH_DPC_N1 PCH_DPC_P1 PCH_DPC_N2 PCH_DPC_P2 PCH_DPC_N3 PCH_DPC_P3

PCH_DPD_CLK PCH_DPD_DAT

PCH_DMC_HPD

PCH_DPD_N0 PCH_DPD_P0 PCH_DPD_N1 PCH_DPD_P1 PCH_DPD_N2 PCH_DPD_P2 PCH_DPD_N3 PCH_DPD_P3

1

HDMICLK_NB 28

HDMIDAT_NB 28

TMDS_B_HPD 28

TMDS_B_DATA2# 28 TMDS_B_DATA2 28 TMDS_B_DATA1# 28 TMDS_B_DATA1 28 TMDS_B_DATA0# 28 TMDS_B_DATA0 28 TMDS_B_CLK# 28 TMDS_B_CLK 2 8

PCH_DPC_CLK 29

PCH_DPC_DAT 29

PCH_DPC_AUXN 2 9 PCH_DPC_AUXP 29

DP_HPD 29

PCH_DPC_N0 29 PCH_DPC_P0 29 PCH_DPC_N1 29 PCH_DPC_P1 29 PCH_DPC_N2 29 PCH_DPC_P2 29 PCH_DPC_N3 29 PCH_DPC_P3 29

PCH_DPD_CLK 30

PCH_DPD_DAT 30

PCH_DMC_HPD 30

PCH_DPD_N0 30 PCH_DPD_P0 30 PCH_DPD_N1 30 PCH_DPD_P1 30 PCH_DPD_N2 30 PCH_DPD_P2 30 PCH_DPD_N3 30 PCH_DPD_P3 30

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, AND OTHER PROPRIETARY INFORMATION OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-6601P

17 63Tuesday, November 30, 2010

1

1.0

5

D D

C C

B B

A A

CLK_PCI_LPBACK16

CLK_PCI_LPC44

+3VS

RH173 10K_0402_5%~D@RH173 10K_0402_5%~D@

CLK_PCI_LPBACK CLK_PCI_LPC

RPH3

8.2K_8P4R_5%

RPH5

8.2K_8P4R_5%

RPH4

8.2K_8P4R_5%

18

PCI_PIRQB#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

DMC_RADIO_OFF#

18 27

DGPU_SELECT#

36 45

HDMI_IN_PWMSEL#

18

PCI_PIRQA#

27 36 45

DGPU_HOLD_RST#

12

4

DGPU_SELECT#23,25,26,27,28 DGPU_PWR_EN47

DMC_RADIO_OFF#38 HDMI_IN_PWMSEL#26

WL_OFF#38

FFS_INT137 ODD_DA#37

DP_CBL_DET29

BT_ON#38

T123PAD~D @T123PAD~D @

RH164 22_0402_5%RH164 22_0402_5% RH165 22_0402_5%RH165 22_0402_5%

WL_OFF#

BT_ON#

FFS_INT1

ODD_DA#

1 2

12

T165PAD~D @T165PAD~D @ T166PAD~D @T166PAD~D @ T124PAD~D @T124PAD~D @

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# DGPU_SELECT# DGPU_PWR_EN

DMC_RADIO_OFF# HDMI_IN_PWMSEL# WL_OFF#

FFS_INT1 ODD_DA# DP_CBL_DET BT_ON#

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

BG26

BH25

BG16 AH38 AH37 AK43 AK45

AH12

AB46 AB45

AY16 BG46

BE28 BC30 BE32

BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

PLT_RST#5,33,35,38,39,44

UH1E

TP1

BJ26

TP2 TP3

BJ16

TP4 TP5 TP6 TP7 TP8 TP9

C18

TP10

N30

TP11

H3

TP12 TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18 TP19 TP20

B21

TP21

M20

TP22 TP23 TP24

TP25 TP26 TP27

BJ32

TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

CougarPoint_Rev_1p0

+3VS

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

USB

4

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

C33

USBRBIAS#

B33

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC6# / GPIO10 OC7# / GPIO14

O

A14 K20 B17 C16 L16 A16

OC5# / GPIO9

D14 C14

+3VS

C1805 .1U_0402_16V7K~DC1805 .1U_0402_16V7K~D

5

1

P

IN1

2

IN2

G

UH5

3

SN74AHC1G08DCKR_SC70-5

NV_ALE

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9

Within 500 mils

USBRBIAS

RH163 22.6_0402_1%RH163 22.6_0402_1%

USB_OC0# USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1 USB_OC2# USB_OC5# USB_OC6# USB3_SMI#

12

PCH_PLTRST#

USB20_N0 40 USB20_P0 40 USB20_N1 40 USB20_P1 40 USB20_N2 24 USB20_P2 24 USB20_N3 26 USB20_P3 26 USB20_N4 38 USB20_P4 38 USB20_N5 38 USB20_P5 38 USB20_N6 41 USB20_P6 41 USB20_N7 46 USB20_P7 46 USB20_N8 38 USB20_P8 38 USB20_N9 40 USB20_P9 40

1 2

USB_OC0# 40 USB_OC1# 40

1.5VDDR_VID0 54

1.5VDDR_VID1 54 USB_OC2# 40

USB3_SMI# 39

USB/B

eDP Camera

LVDS Camera

Mini Card(WLAN)

Mini Card(Mini2)

ELC LED

IR sensor

Bluetooth

USB/ESATA Conn.

(For USB Port 0) (For USB Port 1)

(For USB Port 9)

RSVD

PCI

10K_0402_5%~D

@RH169

@

RH169

1 2

100K_0402_5%~D

12

RH171

2

1

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

PLTRST_VGA#14

RH160 1K_0402_5%~D@ RH160 1K_0402_5%~D@

+3V_MXM

1 2

100K_0402_5%~D

12

@

RH170

100K_0402_5%~D

12

R28

USB_OC0# USB_OC2# USB3_SMI# USB_OC5#

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1 USB_OC6#

4

Y

*

+1.8VS

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

+3VS

C1806

.1U_0402_16V7K~D

5

2

P

B

1

A

G

UH6

3

NC7SZ08P5X_NL_SC70-5

+3V_PCH

RPH1

RPH2

12

DGPU_HOLD_RST#

PCH_PLTRST#

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT .

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-6601P

1

18 63Tuesday, November 30, 2010

1.0

5

+3VS

RH198

2

G

RH198

10K_0402_5%~D

1 2

1

D

QH5

QH5 SSM3K7002F_SC59-3~D

SSM3K7002F_SC59-3~D

S

3

High: CRT Plugged

CRT_DET

D D

CRT_DET#27

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

H：On-Die voltage regulator enable

*

L：On-Die PLL Voltage Regulator disable

RH177 1K_0402_5%~D@ RH177 1K_0402_5%~D@

1 2

PCH_GPIO28

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage

C C

(DC Coupling Mode)

+3VS

RH181 1K_0402_5%~D

1K_0402_5%~D

1 2

PCH_GPIO37

12

RH182

10K_0402_5%~D

@RH181

@

GPIO27

PCH_GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

RH186 10K_0402_5%~D@RH186 10K_0402_5%~D@

B B

1 2

PCH_GPIO27

SATA2GP/GPIO36

When Used as SATA2GP/SATA3GP for Mechanical Presence detect

- Use a weak external pull-up (150K-200K ohms) to Vcc3_3 check list Rev 1.0

*

+3VS

ODD_DETECT#

RH255 200K_0402_5%RH255 200K_0402_5%

12

4

UH1F

CRT_DET

DGPU_EDIDSEL#23,26,28

DGPU_HPD_INT#28

BT_RADIO_DIS#38

DGPU_PWROK14

ODD_EN#37

ODD_DETECT#37

VGA_PRSNT_R#14

VGA_PRSNT_L#14

HDD2_DETECT#36

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SCI#

EC_SCI#44

EC_SMI#

EC_SMI#44

BT_RADIO_DIS#

PCH_GPIO15

PCH_GPIO16

DGPU_PWROK

PCH_GPIO22

ODD_EN#

PCH_GPIO27

PCH_GPIO28

STP_PCI#

ODD_DETECT#

PCH_GPIO37

VGA_PRSNT_R#

VGA_PRSNT_L#

FFS_INT2

FFS_INT237

GPIO49

HDD2_DETECT#

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_Rev_1p0

3

2

1

DMI Termination Voltage

DGPU_BKL_PWM_SEL#

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

EDP_CAB_DET#

LVDS_CAB_DET#

PCH_PECI_R

0_0402_5%~D

KB_RST#

H_CPUPWRGD

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

1 2

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

GPIO

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

@

RH175

10K_0402_5%~D

12

DGPU_BKL_PWM_SEL# 26

EDP_CAB_DET# 23,24

LVDS_CAB_DET# 26

GATEA20 44

H_PECI 5,44

KB_RST# 44

H_CPUPWRGD 5

1 2

@ RH178

@

RH178

RH176390_0402_5% RH176390_0402_5%

H_THRMTRIP# 5

INIT3_3V

This signal has weak internal PU, can't pull low

NV_CLE

DGPU_HPD_INT#

DGPU_EDIDSEL#

VGA_PRSNT_L#

VGA_PRSNT_R#

CRT_DET#

PCH_GPIO16

STP_PCI#

KB_RST#

PCH_GPIO22

GPIO49

LVDS_CAB_DET#

GATEA20

ODD_EN#

HDD2_DETECT#

PCH_GPIO15

EC_SMI#

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal PU,Do not pull low

+1.8VS

12

RH161

2.2K_0402_5%~D

12

RH1621K_0402_5%~D RH1621K_0402_5%~D

CLOSE TO THE BRANCHING POINT

RH179 10K_0402_5%~DRH179 10K_0402_5%~D

1 2

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

RH184 10K_0402_5%~DRH184 10K_0402_5%~D

1 2

RH192 10K_0402_5%~DRH192 10K_0402_5%~D

1 2

RH194 10K_0402_5%~D@RH194 10K_0402_5%~D@

1 2

RH195 10K_0402_5%~DRH195 10K_0402_5%~D

1 2

RH196 10K_0402_5%~DRH196 10K_0402_5%~D

1 2

RH197 10K_0402_5%~DRH197 10K_0402_5%~D

1 2

RH229 10K_0402_5%~DRH229 10K_0402_5%~D

1 2

RH251 10K_0402_5%~DRH251 10K_0402_5%~D

1 2

RH174 10K_0402_5%~DRH174 10K_0402_5%~D

1 2

RH187 10K_0402_5%~DRH187 10K_0402_5%~D

1 2

RH188 10K_0402_5%~DRH188 10K_0402_5%~D

1 2

RH189 1K_0402_5%~DRH189 1K_0402_5%~D

1 2

RH190 10K_0402_5%~DRH190 10K_0402_5%~D

1 2

H_SNB_IVB# 5

+3VS

+3V_PCH

Layout note: Trace wide 10mil & length 30mil All NCTF pins should have thick traces at 45°from the pad.

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, TRADE SECRET, A ND OTHER PROPRI ETARY INFORMATI ON OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION O F DELL. IN ADDI TION, NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT

5

4

DELL'S EXPRESS WRITTEN CONSENT .

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-6601P

1

19 63Tuesday, November 30, 2010

1.0

COMPAL LA-6601P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual