Compal LA-6591P PAL50, LA-6593P PAL52 Schematic
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
LA-6591P (DA80000JV10)
MODEL NAME :
PAL50/52
LA-6593P HF (DA80000MB10)
BOM P/N :
GPIO MAP:{Macallan} GPIO Map 10102010.xlsx
2 2
43192831L01
E3 MACALLAN 14" UMA/ATG
rPGA Sandy Bridge +
FCBGA PCH Cougar Point-M
2011-1-6
REV : 1.0(A00)
@ : Nopop Component
3 3
4 4
MB PCB17@
MB PCB17@
Part Number Description
Part Number Description
Part Number Description
Part Number Description
DA80000JV10
DA80000JV10
MB PCB28@
MB PCB28@
DA80000MB10
DA80000MB10
PCB 0FD LA-6591P REV0 M/B UMA
PCB 0FD LA-6591P REV0 M/B UMA
PCB 0FD LA-6593P REV0 M/B UMA HF
PCB 0FD LA-6593P REV0 M/B UMA HF
A
B
CONN@ : ME controll and stuff by default
MB Type
TPM EN/ TCM DIS
TPM DIS/ TCM EN
TPM DIS/ TCM DIS
ATG TPM EN/ TCM DIS
ATG TPM DIS/ TCM EN
ATG TPM DIS/ TCM DIS 2@3@3@
TPM EN/ TCM DIS HF 1@ 3@4319BP31L01
BOM P/N
1@
2@
2@
1@
2@
3@
4@
3@
4@
7@
7@
7@
7@
7@
7@
43192831L01
43192831L02
43192831L04
43192831L11
43192831L12
43192831L13
8@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-6591P
LA-6591P
LA-6591P
1 66Monday, January 10, 2011
1 66Monday, January 10, 2011
1 66Monday, January 10, 2011
E
1.0
1.0
1.0
Block Diagram
A
B
Compal confidential Model: PAL50/52
C
D
E
Sandy Bridge
Memory BUS (DDR3)
1066/1333MHz
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
PAGE 12,13
4MB (Socket 988B)
1 1
On IO board
CRT CONN
DOCKING PORT
PAGE 40
DAI
2 2
EXPRESS
USB[8,9]
SATA5
DOCK LAN
1/2 Mini Card
Card
USB10
3 3
CPU XDP Port
PCH XDP Port
Thermal
GUARDIAN III
EMC4022
WiFi ON/OFF &
Power ON/OFF SW
4 4
DC/DC Interface
LED
PAGE 45
VGA
VGA
SDXC/MMC/MS
PCIE5
Flash
USB6
PAGE 7
PAGE 14
PAGE 22
PAGE 31
PAGE 44
A
PAGE 35
1/2 Mini Card
WLAN
Smart Card
PAGE 33
RFID
PAGE 33
PWM FAN
PAGE 22
For MB/DOCK
Video Switch
PI3V712-AZLE
HDMI CONN
PAGE 26
LVDS CONN
OZ600FJ0LN
PCIE2
Full Mini Card
WWAN/UWB
TDA8034HN
Fingerprint
CONN
SMSC SIO
ECE5028
PAGE 24
Card reader
PCI Express BUS
PCIE1PCIE3
USB5USB4
PAGE 33
PAGE 23
PAGE 41
B
PAGE 35
100MHz
Option
China TPM1.2
SSX44B
USH
BCM5882
FP_USB
BC BUS
VGA
DPB
DPC
DPD
LVDS
PCIE x1
LPC BUS
33MHz
PAGE 34PAGE 36PAGE 36PAGE 36PAGE 37
TPM1.2
PAGE 33,34
USB7
SMSC KBC
MEC5055
PAGE 42
PAGE 43 PAGE 43
KB CONNTP CONN
rPGA CPU
988 pins
FDI
Lane x 8
INTEL
COUGAR POINT-M
BGA
SPI
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
W25X64ZE
64M 4K sector
W25Q16BVSSIG
16M 4K sector
C
PAGE 6-11
DMI2
Lane x 4
PAGE 14-21
PAGE 14
PAGE 14
PCIE4
USB
PCI Express BUS
HD Audio I/F
E-Module
PAGE 29
Touch Screen
SATA
100MHz
SATA
SATA Repeater
MAX4951BE
PAGE 28
HDD
PAGE 28
PAGE 24
BT
PAGE 43
Camera
SATA Repeater
MAX4951BE
PAGE 39
HDA Codec
92HD90B2
MDC
RJ11
on IO board
D
Trough eDP Cable
E-SATA
USB Port
USB Port
USB Port
USB Port
PAGE 39
PAGE 38
PAGE 38
2560
2560
2062
on IO board
Intel Lewisville
PAGE 30
DOCK LAN
INT.Speaker
HeadPhone &
MIC Jack
DAI
To Docking side
PAGE 30
82579LM
PAGE 32
LAN SWITCH
PAGE 32
PI3L720
RJ45
on IO board
Dig.
MIC
Trough eDP Cable
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
UMA Block Diagram
UMA Block Diagram
UMA Block Diagram
LA-6591P
LA-6591P
LA-6591P
2 66Monday, January 10, 2011
2 66Monday, January 10, 2011
2 66Monday, January 10, 2011
E
1.0
1.0
1.0
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFL
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
OW HIGHLOW
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
USB PORT#
0
1
2
3
4
5
6
7
JUSB2 (Right side 1)
JUSB3 (Right side 2)
JESA1 (Right Side ESATA)
JUSB1 (Ext Left Side )
WLAN
WWAN
JMINI3(Flash)
USH->BIO
DESTINATION
DOCKING8
PM TABLE
C C
power
plane
State
S0
S3
+15V_ALW
+5V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
+3.3V_M +3.3V_M
+1.05V_M
ON
ON
+1.05V_M
(M-OFF)
ON
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
DESTINATION
HDD
ODD/ E3 Module Bay
NA
NA
ESATA
Dock
USH
9
10 Express card
11
12
13
0
1
DOCKING
Bluetooth
Camera
LCD Touch
BIO
NA
S5 S4/AC
S5 S4/AC don't exist
B B
ON
OFF
OFFOFF
OFF
OFF
ON
need to update Power Status and PM Table
A A
OFF
OFFOFF
UMA DP/HDMI Port
Port B
Port C
Port D
Connetion
MB HDMI Conn
Dock DP port 2
Dock DP port 1
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8 None
DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
Express card
E3 Module Bay (USB3)
1/2vMINI CARD-3 PCIE
MMI
10/100/1G LOM
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-6591P
LA-6591P
LA-6591P
3 66Monday, January 10, 2011
3 66Monday, January 10, 2011
3 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
4
3
2
1
EN_INVPWR
D D
FDC654P
Q21
+BL_PWR_SRC
HDDC_EN
MODC_EN
ADAPTER
SI3456BDVSI3456BDV
(Q30)(Q27)
BATTERY
+PWR_SRC
1.05V_VTTPWRGD
ISL95870AH
+VCC_SA
+5V_HDD
+5V_MOD
(PU13)
ALWON
+15V_ALW
C C
CHARGER
SN0608098
(PU2)
+5V_ALW
RUN_ON
SI4164DY
+3.3V_ALW
(Q50)
+5V_RUN
MAX17411
(PU9)
B B
RT8209BGQW
(PU3)
RT9026GFP
(PU5) SI3456
TPS51311
(PU4)
SN1003055
(PU7)
SN1003055RUWR
(PU16)
AUX_EN_WOWL
SI3456
(Q38)
PCH_ALW_ON
SI3456
(Q49)
SUS_ON
S13456
(Q54)
AUX_ON
SI3456
RUN_ON
NTMS4920
(Q34) (Q55)
M_ON
(Q58)
DDR_ON
1.05V_0.8V_PWROK
+VCC_CORE
CPU1.5V_S3_GATE
A A
+1.5V_MEM +0.75V_DDR_VTT
RUN_ON
AO4728
NTGS4141N
(QC3)
0.75V_VR_EN
(Q59)
RUN_ON
+1.8V_RUN
CPU_VTT_ON
+1.05V_RUN_VTT +1.05V_M
M_ON
RUN_ON
SI4164
(Q63)
Pop option
+3.3V_WLAN
+1.0V_LAN
+3.3V_ALW_PCH
+3.3V_M
Pop option
+3.3V_LAN+3.3V_SUS
+3.3V_RUN
+3.3V_M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-6591P
LA-6591P
LA-6591P
4 66Monday, January 10, 2011
4 66Monday, January 10, 2011
4 66Monday, January 10, 2011
1
1.0
1.0
1.0
+1.5V_CPU_VDDQ
5
+1.5V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
+1.05V_RUN
4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
B4
A3
B5
A4
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
C8
G12
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
@
@
2.2K
2.2K
2.2K
2.2K
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
SMBUS Address [C8]
127
129
DOCKING
3
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
202
200
202
200
2
DIMMA
DIMMB
53
51
53
51
XDP1
XDP2
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
SMBUS Address [TBD]
1
2.2K
G Sensor
WWAN
+3.3V_RUN
SMBUS Address [3B]
SMBUS Address [TBD]
2.2K
14
13
30
32
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
10
9
7
6
M9
L9
7
8
Charger
BATTERY
CONN
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
Express card
SMBUS Address [0x12]
SMBUS Address [TBD]
29
E3 Module Bay
30
8
A/D,D/A
9
converter
3
SMBUS Address [0xd2]
SMBUS Address [0x30]
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SMBUS TOPOLOGY
SMBUS TOPOLOGY
SMBUS TOPOLOGY
LA-6591P
LA-6591P
LA-6591P
5 66Monday, January 10, 2011
5 66Monday, January 10, 2011
5 66Monday, January 10, 2011
1
1.0
1.0
1.0
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5055
2B
2B
2.2K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
2.2K
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
2D
A A
2D
2.2K
2.2K
DAI_SMBCLK
B49
2A
2A
5
B48
DAI_SMBDAT
5
JCPU1A
JCPU1A
DMI_CRX_PTX_N016
DMI_CRX_PTX_N116
DMI_CRX_PTX_N216
D D
DMI_CRX_PTX_N316
DMI_CRX_PTX_P016
DMI_CRX_PTX_P116
DMI_CRX_PTX_P216
DMI_CRX_PTX_P316
DMI_CTX_PRX_N016
DMI_CTX_PRX_N116
DMI_CTX_PRX_N216
DMI_CTX_PRX_N316
DMI_CTX_PRX_P016
DMI_CTX_PRX_P116
DMI_CTX_PRX_P216
DMI_CTX_PRX_P316
FDI_CTX_PRX_N016
FDI_CTX_PRX_N116
FDI_CTX_PRX_N216
FDI_CTX_PRX_N316
FDI_CTX_PRX_N416
FDI_CTX_PRX_N516
FDI_CTX_PRX_N616
FDI_CTX_PRX_N716
FDI_CTX_PRX_P016
FDI_CTX_PRX_P116
C C
FDI_CTX_PRX_P216
FDI_CTX_PRX_P316
FDI_CTX_PRX_P416
FDI_CTX_PRX_P516
FDI_CTX_PRX_P616
FDI_CTX_PRX_P716
FDI_FSYNC016
FDI_FSYNC116
FDI_INT16
FDI_LSYNC016
FDI_LSYNC116
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
B B
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
4
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
PEG_COMP
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
PEG_RX[0]
L35
PEG_RX[1]
K34
PEG_RX[2]
H35
PEG_RX[3]
H32
PEG_RX[4]
G34
PEG_RX[5]
G31
PEG_RX[6]
F33
PEG_RX[7]
F30
PEG_RX[8]
E35
PEG_RX[9]
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
PEG_TX[0]
M33
PEG_TX[1]
M30
PEG_TX[2]
L31
PEG_TX[3]
L28
PEG_TX[4]
K30
PEG_TX[5]
K27
PEG_TX[6]
J29
PEG_TX[7]
J27
PEG_TX[8]
H28
PEG_TX[9]
G28
E28
F28
D27
E26
D25
3
2
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
1
F22
VSS234
F19
VSS235
E30
VSS236
E27
VSS237
E24
VSS238
E21
VSS239
E18
VSS240
E15
VSS241
E13
VSS242
E10
VSS243
E9
VSS244
E8
VSS245
E7
VSS246
E6
VSS247
E5
VSS248
E4
VSS249
E3
VSS250
E2
VSS251
E1
VSS252
D35
VSS253
D32
VSS254
D29
VSS255
D26
VSS256
D20
VSS257
D17
VSS258
C34
VSS259
C31
VSS260
C28
VSS261
C27
VSS262
C25
VSS263
C23
VSS264
C10
VSS265
C1
VSS266
B22
VSS267
B19
VSS268
B17
VSS269
B15
VSS270
B13
VSS271
B11
VSS272
B9
VSS273
B8
VSS274
B7
VSS275
B5
VSS276
B3
VSS277
B2
VSS278
A35
VSS279
A32
VSS280
A29
VSS281
A26
VSS282
A23
VSS283
A20
VSS284
A3
VSS285
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (1/6)
Sandy Bridge (1/6)
Sandy Bridge (1/6)
LA-6591P
LA-6591P
LA-6591P
6 66Monday, January 10, 2011
6 66Monday, January 10, 2011
6 66Monday, January 10, 2011
1
1.0
1.0
1.0
DP Compensation
+1.05V_RUN_VTT
12
RC1
RC1
24.9_0402_1%~D
24.9_0402_1%~D
EDP_COMP
eDP_COMPIO and I COMPO signals sh ould be shorted n ear
A A
balls and routed with typical im pedance <25 mohms
5
PEG_ICOMPI and R COMPO signals sh ould be shorted a nd routed
with - max lengt h = 500 mils - t ypical impedance = 43 mohms
PEG_ICOMPO signa ls should be rou ted with - max le ngth = 500 mils
- typical impeda nce = 14.5 mohms
+1.05V_RUN_VTT
4
PEG Compensation
12
RC2
RC2
24.9_0402_1%~D
24.9_0402_1%~D
PEG_COMP
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
5
Follow DG Rev0.71 SM_DRAMPWROK topology
+3.3V_ALW_PCH
UC2
UC2
RUNPWROK41,42
+3.3V_ALW_PCH
D D
+1.05V_RUN_VTT
C C
1 2
RC18 200_0402_5%~DRC18 200_0402_5%~D
PM_DRAM_PWR GD16
1 2
RC126 56_0402_5%~D@RC126 56_0402_5%~D@
1 2
RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@
1 2
RC44 62_0402_5%~DRC44 62_0402_5%~D
H_PROCHOT#42,52,54
H_THERMTRIP#22
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
1
2
RUN_ON_CPU1.5VS3#11,44
CPU_DETECT#41
H_PECI18
1 2
RC57 56_0402_5%~DRC57 56_0402_5%~D
1 2
RC129 0_0402_5%~DRC129 0_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC156
CC156
1 2
5
P
B
A
RUNPWROK_AND PM_DRAM_PWR GD_CPU
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
H_CATERR#
H_PROCHOT#_R
Close to JCBU1
H_THERMTRIP#_R
2
C26
AN34
AL33
AN33
AL32
AN32
+1.5V_CPU_VDDQ
1 2
13
D
D
G
G
S
S
JCPU1B
JCPU1B
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
39_0402_5%~D
39_0402_5%~D
12
RC64
RC64
QC1
QC1
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
place RC129 near CPU
H_PM_SYNC16
B B
H_CPUPWRGD18
1 2
RC25 0_0402_5%~DRC25 0_0402_5%~D
Buffered reset to CPU
A A
PCH_PLTRST#14,17
5
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWR GD_CPU
PCH_PLTRST#_R
+3.3V_RUN
UC1
UC1
1
2
5
NC
VCC
A
4
GND3Y
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
+1.05V_RUN_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC140
CC140
2
PCH_PLTRST#_BUF PCH_PLTRST#_R
RC4
75_0402_1%~D
RC4
75_0402_1%~D
12
1 2
RC10 43_0402_5%~DRC10 43_0402_5%~D
4
RC12
RC12
200_0402_5%~D
200_0402_5%~D
1 2
RC28 130_0402_5%~DRC28 130_0402_5%~D
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
12
RC11
@RC11
@
0_0402_5%~D
0_0402_5%~D
4
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
JTAG & BPM
JTAG & BPM
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
3
+3.3V_ALW_PCH
12
RC124
@RC124
@
1K_0402_5%~D
1K_0402_5%~D
SYS_PWROK_XDP
The resistor for HOOK2 should be placed
such that the st ub is very small on CFG0 net
H_CPUPWRGD
SIO_PWRBTN#_R14,16
CFG0
SYS_PWROK16,41
DDR_XDP_WAN_ SMBDAT12,13,14,15,28,36
DDR_XDP_WAN_ SMBCLK12,13,14,15,28,36
Keep R1132, R1133, R1136-R119
for slew rate control.
CPU_DMI
A28
CPU_DMI#
A27
CPU_DPLL
A16
CPU_DPLL#
A15
DDR3_DRAMRST#_CP U
R8
SM_RCOMP0
AK1
SM_RCOMP1
A5
SM_RCOMP2
A4
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCLK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI_R
AR28
XDP_TDO_R
AP26
XDP_DBRESET#_R
AL35
XDP_OBS0_R
AT28
XDP_OBS1_R
AR29
XDP_OBS2_R
AR30
AT30
XDP_OBS4_R XDP_OBS4
AP32
XDP_OBS5_R
AR31
XDP_OBS6_R
AT31
XDP_OBS7_R
AR32
For ESD concern, please put near CPU
Avoid stub in th e PWRGD path
while placing re sistors RC25 & R C130
1 2
RC13 0_0402_5%~DRC13 0_0402_5%~D
1 2
RC15 0_0402_5%~DRC15 0_0402_5%~D
1 2
RC16 0_0402_5%~DRC16 0_0402_5%~D
1 2
RC17 0_0402_5%~DRC17 0_0402_5%~D
Max 500mils
12
RC26 0_0402_5%~DRC26 0_0402_5%~D
1 2
RC30 0_0402_5%~DRC30 0_0402_5%~D
1 2
RC31 0_0402_5%~DRC31 0_0402_5%~D
1 2
RC33 0_0402_5%~DRC33 0_0402_5%~D
1 2
RC34 0_0402_5%~DRC34 0_0402_5%~D
1 2
RC36 0_0402_5%~DRC36 0_0402_5%~D
1 2
RC37 0_0402_5%~DRC37 0_0402_5%~D
1 2
RC38 0_0402_5%~DRC38 0_0402_5%~D
1 2
RC39 0_0402_5%~DRC39 0_0402_5%~D
VCCPWRGOOD_0_R
12
RC130
RC130
10K_0402_5%~D
10K_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1 2
RC5 1K_0402_5%~DRC5 1K_0402_5%~D
1 2
RC6 0_0402_5%~DRC6 0_0402_5%~D
1 2
RC7 1K_0402_5%~DRC7 1K_0402_5%~D
1 2
RC9 0_0402_5%~D@ RC9 0_0402_5%~D@
1 2
RC125 0_0402_5%~DRC125 0_0402_5%~D
1 2
RC127 0_0402_5%~DRC127 0_0402_5%~D
CLK_CPU_DMI 15
CLK_CPU_DMI# 15
CLK_CPU_DPLL 15
CLK_CPU_DPLL# 15
RC50
RC50
4.99K_0402_1%~D
4.99K_0402_1%~D
DDR_HVREF_RST_PCH15
DDR_HVREF_RST_GATE42
XDP_DBRESET#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3X DP_OBS3_R
XDP_OBS5
XDP_OBS6
XDP_OBS7
+1.05V_RUN_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
CC65
CC65
2
2
Place near JXDP1
CFG109
CFG119
1 2
RC48 0_0402_5%~D@RC48 0_0402_5%~D@
S
S
12
XDP_DBRESET# 14,16
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC66
CC66
XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFG10
CFG11
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_CPUPWRGD_XD P
CFD_PWRBTN#_X DP
SYS_PWROK_XDP
DDR_XDP_WAN_ SMBDAT_R1
DDR_XDP_WAN_ SMBCLK_R1
XDP_TCLK
D
D
13
QC2
QC2
G
G
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
2
1
CC177
CC177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
RC46 0_0402_5%~DRC46 0_0402_5%~D
RC47 0_0402_5%~D@RC47 0_0402_5%~D@
XDP_TDO_R XDP_TDO
+1.05V_RUN_VTT +1.05V_RUN_VTT
DDR3_DRAMRST# 12
DDR_HVREF_RST
1 2
1 2
1 2
RC23 0_0402_5%~DRC23 0_0402_5%~D
1 2
RC24 0_0402_5%~DRC24 0_0402_5%~D
200_0402_1%~D
200_0402_1%~D
25.5_0402_1%~D
25.5_0402_1%~D
140_0402_1%~D
140_0402_1%~D
12
RC42
RC42
12
12
RC45
RC45
RC43
RC43
2
JXDP1
@JXDP1
@
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
CLK_XDP
CLK_XDP#
XDP_TDIXDP_TDI_R
1
2
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
XDP_RST#_R
RH107 0_0402 _5%~DRH107 0_0402_5%~D
RH106 0_0402 _5%~DRH106 0_0402_5%~D
CLK_XDP_ITP9
CLK_XDP_ITP#9
RC8 1K_0402_5%~DRC8 1K_0402_5%~D
1 2
1 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
12
1 2
RH109 0_0402_5%~D@RH109 0_0402_5%~D@
1 2
RH108 0_0402_5%~D@RH108 0_0402_5%~D@
CFG16
CFG17
CFG0
CFG1
CFG2
CFG3
CFG8
CFG9
CFG4
CFG5
CFG6
CFG7
CLK_XDP
CLK_XDP#
XDP_RST#_RXDP_HOOK2
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
CFG16 9
CFG17 9
CFG0 9
CFG1 9
CFG2 9
CFG3 9
CFG8 9
CFG9 9
CFG4 9
CFG5 9
CFG6 9
CFG7 9
PLTRST_XDP# 17
CLK_CPU_ITP 15
CLK_CPU_ITP# 15
PU/PD for JTAG signals
+3.3V_RUN
XDP_DBRESET#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
RC19 1K_0402_5%~DRC19 1K_0402_5%~D
RC27 51_0402_1%~DRC27 51_0402_1%~D
RC29 51_0402_1%~DRC29 51_0402_1%~D
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
RC35 51_0402_1%~DRC35 51_0402_1%~D
RC40
RC40
RC41
RC41
12
12
12
12
12
12
51_0402_1%~D
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
+1.05V_RUN_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (2/6)
Sandy Bridge (2/6)
Sandy Bridge (2/6)
LA-6591P
LA-6591P
LA-6591P
7 66Monday, January 10, 2011
7 66Monday, January 10, 2011
7 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
JCPU1C
JCPU1C
D D
C C
B B
DDR_A_D[0..63]12
DDR_A_BS012
DDR_A_BS112
DDR_A_BS212
DDR_A_CAS#12
DDR_A_RAS#12
DDR_A_WE#12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
K2
M8
N8
N7
M9
N9
M7
V6
J1
J5
J4
J2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
4
M_CLK_DDR0
AB6
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 12
M_CLK_DDR#0 12
DDR_CKE0_DIMMA 12
M_CLK_DDR1 12
M_CLK_DDR#1 12
DDR_CKE1_DIMMA 12
DDR_CS0_DIMMA# 12
DDR_CS1_DIMMA# 12
M_ODT0 12
M_ODT1 12
DDR_A_DQS#[0..7] 12
DDR_A_DQS[0..7] 12
DDR_A_MA[0..15] 12
3
DDR_B_D[0..63]13
DDR_B_BS013
DDR_B_BS113
DDR_B_BS213
DDR_B_CAS#13
DDR_B_RAS#13
DDR_B_WE#13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
2
JCPU1D
JCPU1D
M_CLK_DDR2
AE2
SB_CLK[0]
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
AP3
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
1
M_CLK_DDR2 13
M_CLK_DDR#2 1 3
DDR_CKE2_DIMMB 13
M_CLK_DDR3 13
M_CLK_DDR#3 1 3
DDR_CKE3_DIMMB 13
DDR_CS2_DIMMB# 13
DDR_CS3_DIMMB# 13
M_ODT2 13
M_ODT3 13
DDR_B_DQS#[0..7] 13
DDR_B_DQS[0..7] 13
DDR_B_MA[0..15] 13
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
A A
Sandy Bridge_rPGA_Rev1p0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (3/6)
Sandy Bridge (3/6)
Sandy Bridge (3/6)
LA-6591P
LA-6591P
LA-6591P
8 66Monday, January 10, 2011
8 66Monday, January 10, 2011
8 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
4
3
2
1
CFG Straps for Processor
CFG2
D D
T22 PAD~D@T22 PAD~D@
T28 PAD~D@ T28 PAD~D@
T29 PAD~D@ T29 PAD~D@
T30 PAD~D@ T30 PAD~D@
T31 PAD~D@ T31 PAD~D@
T33 PAD~D@ T33 PAD~D@
T35 PAD~D@ T35 PAD~D@
T36 PAD~D@ T36 PAD~D@
T37 PAD~D@ T37 PAD~D@
T38 PAD~D@ T38 PAD~D@
T40 PAD~D@ T40 PAD~D@
T41 PAD~D@ T41 PAD~D@
T42 PAD~D@ T42 PAD~D@
T43 PAD~D@ T43 PAD~D@
T44 PAD~D@ T44 PAD~D@
T45 PAD~D@ T45 PAD~D@
T46 PAD~D@ T46 PAD~D@
T47 PAD~D@ T47 PAD~D@
T48 PAD~D@ T48 PAD~D@
T155 PAD~D@T155 PAD~D@
T52 PAD~D@ T52 PAD~D@
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD1
RSVD2
RSVD3
RSVD4
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
CFG07
CFG17
CFG27
CFG37
CFG47
CFG57
CFG67
CFG77
CFG87
CFG97
CFG107
CFG117
T9 PAD~D@ T9 PAD~D@
T10 PAD~D@T10 PAD~D@
T12 PAD~D@T12 PAD~D@
+VCC_GFXCORE
1 2
RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
+VCC_CORE
1 2
C C
B B
RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
RC96 1K_0402_5%~D@RC96 1K_040 2_5%~D@
RC97 1K_0402_5%~D@RC97 1K_040 2_5%~D@
1 2
1 2
1 2
1 2
RSVD1
RSVD3
RSVD2
RSVD4
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
T14 PAD~D@T14 PAD~D@
CFG167
CFG177
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
JCPU1E
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RESERVED
RESERVED
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
T1 PAD~D@ T1 PAD~D@
T2 PAD~D@ T2 PAD~D@
T3 PAD~D@ T3 PAD~D@
T4 PAD~D@ T4 PAD~D@
T5 PAD~D@ T5 PAD~D@
T6 PAD~D@ T6 PAD~D@
T7 PAD~D@ T7 PAD~D@
T8 PAD~D@ T8 PAD~D@
T11 PAD~D@T11 PAD~D@
T13 PAD~D@T13 PAD~D@ RC52
T15 PAD~D@T15 PAD~D@
T16 PAD~D@T16 PAD~D@
T17 PAD~D@T17 PAD~D@
T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@
T20 PAD~D@T20 PAD~D@
T21 PAD~D@T21 PAD~D@
T23 PAD~D@T23 PAD~D@
T24 PAD~D@T24 PAD~D@
T25 PAD~D@T25 PAD~D@
T26 PAD~D@T26 PAD~D@
T27 PAD~D@T27 PAD~D@
T32 PAD~D@T32 PAD~D@
T34 PAD~D@T34 PAD~D@
T39 PAD~D@T39 PAD~D@
CLK_XDP_ITP 7
CLK_XDP_ITP# 7
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
PCIE Port Bifurcation Straps
T49 PAD~D@T49 PAD~D@
T50 PAD~D@T50 PAD~D@
T51 PAD~D@T51 PAD~D@
T53 PAD~D@T53 PAD~D@
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG4
CFG6
CFG5
RC54
@RC54
@
1K_0402_5%~D
1K_0402_5%~D
12
RC51
@RC51
@
1K_0402_5%~D
1K_0402_5%~D
12
@RC52
@
1K_0402_5%~D
1K_0402_5%~D
follow DG0.9 change to 1Kohm 5%
12
12
RC53
@RC53
@
1K_0402_5%~D
1K_0402_5%~D
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CFG7
12
RC56
@RC56
@
1K_0402_5%~D
1K_0402_5%~D
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (4/6)
Sandy Bridge (4/6)
Sandy Bridge (4/6)
LA-6591P
LA-6591P
LA-6591P
9 66Monday, January 10, 2011
9 66Monday, January 10, 2011
9 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
+VCC_CORE
CC129
470U_D2_2V-M~D
470U_D2_2V-M~D
CC133
CC133
470U_D2_2V-M~D
470U_D2_2V-M~D
1
CC75
CC75
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC71
CC71
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC111
CC111
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC116
CC116
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC121
CC121
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
2 3
1
CC67
+VCC_CORE
+VCC_CORE
CC67
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC87
CC87
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC110
CC110
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC115
CC115
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC120
CC120
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC125
CC125
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
+
@+CC129
@
2 3
1
+
+
2 3
D D
C C
B B
A A
+
CC130
@+CC130
@
470U_D2_2V-M~D
470U_D2_2V-M~D
1
+
+
CC134
CC134
470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
1
CC68
CC68
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC72
CC72
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC112
CC112
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC117
CC117
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC122
CC122
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
+
+
2 3
1
CC76
CC76
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC88
CC88
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
2
1
2
1
2
CC131
CC131
470U_D2_2V-M~D
470U_D2_2V-M~D
CC113
CC113
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC118
CC118
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC123
CC123
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
+
+
CC132
CC132
470U_D2_2V-M~D
470U_D2_2V-M~D
2 3
1
CC77
CC77
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC73
CC73
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
2
1
2
1
2
4
CC114
CC114
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC119
CC119
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC124
CC124
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
3
POWER
JCPU1F
JCPU1F
+VCC_CORE
53A 8.5A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
H_CPU_SVIDALRT#
AJ29
VIDSCLK
AJ30
VIDSOUT
AJ28
SVID note: VIDAL ERT# trace
routing need to be routed betwee n
VIDSCLK and VIDS OUT signals
VCCSENSE_R
AJ35
VSSSENSE_R
AJ34
VTT_SENSE_R
B10
VSSIO_SENSE_R
A10
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC78
CC78
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC89
CC89
2
2
Note: Place the PU resistors clo se to CPU
R1555 close to C PU 300 - 1500mil s
1 2
RC67 0_0402_5%~DRC67 0_0402_5%~D
1 2
RC68 0_0402_5%~DRC68 0_0402_5%~D
1 2
RC132 0_0402_5%~DRC132 0_0402_5%~D
1 2
RC133 0_0402_5%~DRC133 0_0402_5%~D
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CC69
CC69
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
@CC90
@
1
CC90
2
H_CPU_SVIDALRT#
VIDSCLK 52
CC79
CC79
@CC91
@
CC91
1
CC80
CC80
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
@CC92
@
1
1
CC92
2
2
1 2
RC61 43_0402_5%~DRC 61 43_0402_5%~D
+1.05V_RUN_VTT
12
RC63
RC63
130_0402_1%~D
130_0402_1%~D
Place RC66, RC70near CPU
VTT_SENSE 51
VTT_GND 51
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC81
CC81
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
@CC93
@
CC93
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC82
CC82
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC107
CC107
+
+
2
CAD Note: Place the PU
resistors close to CPU
R1558 close to C PU 300 - 1500mil s
VIDSOUT 52
+VCC_CORE
12
RC66
RC66
100_0402_1%~D
100_0402_1%~D
12
RC70
RC70
100_0402_1%~D
100_0402_1%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC83
CC83
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC108
CC108
+
+
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC84
CC84
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC109
CC109
+
+
@
@
2
+1.05V_RUN_VTT
VCCSENSE 52
VSSSENSE 52
12
1
+1.05V_RUN_VTT
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC85
CC85
2
RC60
RC60
75_0402_1%~D
75_0402_1%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC70
CC70
2
VIDALERT_N 52
CC86
CC86
Iccmax current c hanged for PDDG Rev0.7
CPU Power Rail Table
Voltage Rail
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
+1.5V_MEM 1.5
Description
*
5A to Mem contro ller(+1.5V_CPU_V DDQ)
5-6A to 2 DIMMs/ channel
2-5A to +1.5V_RU N & +0.75V_DDR_V TT
Voltage
0.65-1.3
1.05
0.0-1.1
1.8
1.5
0.65-0.9
S0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16
*
Sandy Bridge_rPGA_Rev1p0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Sandy Bridge (5/6)
Sandy Bridge (5/6)
Sandy Bridge (5/6)
LA-6591P
LA-6591P
LA-6591P
10 66Monday, January 10, 2011
10 66Monday, January 10, 2011
10 66Monday, January 10, 2011
1
1.0
1.0
1.0
Sandy Bridge_rPGA_Rev1p0
DELL CONFIDENTIAL/PROPRIETARY
5
4
3
2
1
+1.5V_CPU_VDDQ Source
+15V_ALW+3.3V_ALW2
12
RC74
RC74
100K_0402_5%~D
61
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC139
CC139
CC148
CC148
1
2
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
1
CC176
CC176
+
+
2
100K_0402_5%~D
RUN_ON_CPU1.5VS3#
QC4A
QC4A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
JCPU1G
JCPU1G
26A
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
3A
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
5
POWER
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
D D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC144
CC144
1
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC152
CC152
1
2
10U_0805_4VAM~D
10U_0805_4VAM~D
1
2
1 2
RC77 0_0402_5%~D@RC77 0_0402_5%~D@
1 2
RC79 0_0402_5%~DRC79 0_0402_5%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC146
CC146
CC145
CC145
CC153
CC153
CC173
CC173
CC147
CC147
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CC174
CC174
2
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CC175
CC175
RUN_ON37,41,44,49
CPU1.5V_S3_GATE42 RUN_ON_CPU1.5VS3# 7,44
+VCC_GFXCORE
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC137
CC137
CC138
CC138
1
C C
B B
A A
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
2
+1.8V_RUN
1
1
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC141
CC141
CC151
CC151
1
1
2
2
+1.5V_MEM +1.5V_CPU_VDDQ
12
RC72
RC72
100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3
3
QC4B
QC4B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID1
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
FC_C22
QC3
QC3
AO4728L_SO8~D
AO4728L_SO8~D
8
7
6
5
4
1
CC136
CC136
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
AK35
AK34
AL1
+V_SM_VREF should
have 10 mil trace width
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
1
2
3
H_FC_C22
1 2
RC138 0_0402_5%~DRC138 0_0402_5%~D
20K_0402_5%~D
20K_0402_5%~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
12
CC135
CC135
1
2
VCC_AXG_SENSE 52
VSS_AXG_SENSE 52
+V_SM_VREF_CNT
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC161
CC161
2
2
10U_0805_4VAM~D
10U_0805_4VAM~D
1
2
@RC73
@
RC73
1
CC162
CC162
2
1
CC168
CC168
2
+V_DDR_REF
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CC164
CC164
CC163
CC163
2
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CC169
CC169
CC170
CC170
2
1 2
RC137 0_0402_5%~DRC137 0_0402_5%~D
VCCSA_VID_1 55
1 2
RC134 0_0402_5%~D@RC134 0_0402_5%~D@
RUN_ON_CPU1.5VS3
+1.5V_CPU_VDDQ
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC166
CC166
CC165
CC165
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@CC171
@
1
1
CC171
+
+
CC172
CC172
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
2
2
10K_0402_5%~D
10K_0402_5%~D
12
RC83
RC83
QC5
QC5
NTR4503NT1G_SOT23-3~D
NTR4503NT1G_SOT23-3~D
1
2
CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D
CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D
CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D
CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC167
CC167
+
+
2
+VCC_SA
+GND_VCC_SA 55
+VCCSA_SENSE 55
3
12
12
12
12
PJP1
@PJP1
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
PJP2
@PJP2
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+V_SM_VREF_CNT
12
RC78
RC78
100K_0402_5%~D
100K_0402_5%~D
+1.5V_MEM
JCPU1H
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Sandy Bridge (6/6)
Sandy Bridge (6/6)
Sandy Bridge (6/6)
LA-6591P
LA-6591P
LA-6591P
11 66Monday, January 10, 2011
11 66Monday, January 10, 2011
11 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
D D
DDR_A_DQS[0..7]8
DDR_A_MA[0..15]8
Layout Note:
Place near JDIMMA
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD3
CD3
2
C C
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD7
CD7
1
1
2
2
B B
+0.75V_DDR_VTT
A A
1U_0402_6.3V6K~D
1
1
CD4
CD4
CD5
CD5
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
CD8
CD8
Layout Note:
Place near JDIMMA.203,204
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
CD10
CD9
CD9
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD17
CD17
CD18
CD18
2
All VREF traces should
have 10 mil trace width
Populate RD1 for Intel DDR3
VREFDQ multiple methods M1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD6
CD6
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD11
CD11
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD19
CD19
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD12
CD12
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD20
CD20
2
+DIMM0_1_VREF_CPU
330U_SX_2VY~D
330U_SX_2VY~D
@CD13
@
1
CD14
CD14
CD13
+
+
2
+V_DDR_REF
4
1 2
RD1 0_0402_5%~DRD1 0_0402_5%~D
1 2
RD7 0_0402_5%~D@RD7 0_0402_5%~D@
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
1 2
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
+3.3V_RUN
+DIMM0_1_VREF_DQ
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
CD1
CD1
2
DDR_CKE0_DIMMA8
DDR_A_BS28
M_CLK_DDR08
DDR_A_BS08
DDR_A_WE#8
DDR_A_CAS#8
DDR_CS1_DIMMA#8
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CD21
CD21
2
3
JDIMM1
JDIMM1
1
VREF_DQ
3
DDR_A_D0
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_A_D1
1
CD2
CD2
DDR_A_D2
2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
CD22
CD22
+0.75V_DDR_VTT
2
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
FOX_AS0A626-U4SN-7F
FOX_AS0A626-U4SN-7F
CONN@
CONN@
change footprint.
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
NC
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
2-3A to 1 DIMMs/channel
+1.5V_MEM+1.5V_MEM
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR3_DRAMRST#_R
DDR_A_D14
DDR_A_D15
DDR_A_D20DDR_A_D16
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.75V_DDR_VTT
M_CLK_DDR1 8
M_CLK_DDR#1 8M_CLK_DDR#08
DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 8
M_ODT0 8
M_ODT1 8
2
JDIMMA H=5.2
DDR_CKE1_DIMMA 8
+DIMM0_1_VREF_CA
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
DDR_XDP_WAN_ SMBDAT 7,13,14,15,28,36
DDR_XDP_WAN_ SMBCLK 7,13,14,15,28,36
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CD15
CD15
CD16
CD16
1
2
DDR3_DRAMRST#_R
1 2
RD29 0_0402_5%~DRD29 0_0402_5%~D
1 2
RD31 0_0402_5%~D@RD31 0_0402_5%~D@
+1.5V_MEM
12
RD27
RD27
1K_0402_1%~D
1K_0402_1%~D
1 2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
+V_DDR_REF
+DIMM0_1_CA_CPU
1
DDR3_DRAMRST# 7DDR3_DRAMRST#_R13
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-6591P
LA-6591P
LA-6591P
12 66Monday, January 10, 2011
12 66Monday, January 10, 2011
12 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
All VREF traces should
have 10 mil trace width
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DQS[0..7]8
D D
C C
B B
A A
DDR_B_MA[0..15]8
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD29
CD29
1
2
Layout Note:
Place near JDIMMB.203,204
+0.75V_DDR_VTT
1
2
CD26
CD26
CD25
CD25
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD30
CD30
CD31
CD31
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD39
CD39
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD40
CD40
2
Layout Note:
Place near JDIMMB
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD27
CD27
CD28
CD28
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD32
CD32
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD34
CD34
CD33
CD33
1
1
2
CD41
CD41
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD42
CD42
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
Populate RD4 for Intel DDR3
VREFDQ multiple methods M1
330U_SX_2VY~D
330U_SX_2VY~D
@CD35
@
1
CD35
CD36
CD36
+
+
2
4
+DIMM0_1_VREF_DQ
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
+3.3V_RUN
RD5 10K_04 02_5%~DRD5 10K_0402_5%~D
12
CD23
CD23
DDR_CKE2_DIMMB8
DDR_CS3_DIMMB#8
+3.3V_RUN
1
2
DDR_B_BS28
M_CLK_DDR28
M_CLK_DDR#28
DDR_B_BS08
DDR_B_WE#8
DDR_B_CAS#8
12
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CD24
CD24
10K_0402_5%~D
10K_0402_5%~D
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+0.75V_DDR_VTT
RD6
RD6
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CD43
CD43
2
3
+1.5V_MEM
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
CD44
CD44
JDIMM2
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
FOX_AS0A626-U8SN-7F
FOX_AS0A626-U8SN-7F
CONN@
CONN@
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
2
2-3A to 1 DIMMs/channel
+1.5V_MEM
2
VSS
A15
A14
A11
S0#
A7
A6
A4
A2
A0
NC
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.75V_DDR_VTT
JDIMMB H=9.2
DDR3_DRAMRST#_R 12
DDR_CKE3_DIMMB 8
M_CLK_DDR3 8
M_CLK_DDR#3 8
DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 8
M_ODT2 8
M_ODT3 8
+DIMM0_1_VREF_CA
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
DDR_XDP_WAN_ SMBDAT 7,12,14,15,28,36
DDR_XDP_WAN_ SMBCLK 7,12,14,15,28,36
1
CD37
CD37
2
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CD38
CD38
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-6591P
LA-6591P
LA-6591P
13 66Monday, January 10, 2011
13 66Monday, January 10, 2011
13 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
CMOS settingCMOS_CLR1
Clear CMOSShunt
Open
ME_CLR1
Shunt
Open
D D
+RTC_CELL
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
*
Low - Enable External VRs
C C
PCH_AZ_CODEC_SDOUT30
PCH_AZ_CODEC_SYNC30
PCH_AZ_CODEC_BITCLK30
B B
Keep CMOS
TPM setting
Clear ME RTC Registers
Keep ME RTC Registers
12
RH38
RH38
330K_0402_5%~D
330K_0402_5%~D
PCH_INTVRMEN
12
RH39
@RH39
@
330K_0402_5%~D
330K_0402_5%~D
1
1
@
@
ME1 SHORT PADS~D
ME1 SHORT PADS~D
1 2
CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D
PCH_AZ_CODEC_RST#30
CH101
@CH101
@
27P_0402_50V8J~D
27P_0402_50V8J~D
+3.3V_RUN
12
RH295
@RH295
@
8.2K_0402_5%~D
8.2K_0402_5%~D
PCH_SPI_DO
2
2
1
2
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
+3.3V_ALW_PCH
12
PCH_AZ_SYNC
12
@RH282
@
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
+RTC_CELL
1 2
RH29 33_0402_5%~DRH29 33_0402_5%~D
1 2
RH26 33_0402_5%~DRH26 33_0402_5%~D
1 2
RH27 33_0402_5%~DRH27 33_0402_5%~D
1 2
RH25 33_0402_5%~DRH25 33_0402_5%~D
+3.3V_ALW_PCH
1 2
RH22 20K_0402_5%~DRH22 20K_0402_5%~D
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
1
1
@
@
CMOS1 SHORT PADS~D
CMOS1 SHORT PADS~D
1 2
CH4
CH4
CMOS place near DIMM
PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK
12
RH288
@RH288
@
0_0603_5%~D
0_0603_5%~D
+3.3V_ALW_PCH_JTAG
RH66
RH66
1K_0402_5%~D
1K_0402_5%~D
RH282
100K_0402_5%~D
100K_0402_5%~D
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
PCH_AZ_MDC_SDOUT31
RH59 51_0402_1%~DRH59 51_0402_1%~D
RH44 200_0402_1%~DRH44 2 00_0402_1%~D
RH45 200_0402_1%~DRH45 2 00_0402_1%~D
RH43 200_0402_1%~DRH43 200_0402_1%~D
12
12
12
12
SPI_MOSI
High: Enable Intel Anti-Theft Technology
Left floating: Disable Intel Anti-Theft Technology
CONN@
CONN@
JSPI1
JSPI1
A A
HRS_FH12-16S-0P5SH(55)~D
HRS_FH12-16S-0P5SH(55)~D
SPI_PCH_CS1#
1
1
PCH_SPI_CS1#
2
2
SPI_PCH_DO
3
3
PCH_SPI_DO
4
4
SPI_PCH_DIN
5
5
PCH_SPI_DIN
6
6
SPI_PCH_CLK
7
7
PCH_SPI_CLK
8
8
SPI_PCH_CS0#
9
9
PCH_SPI_CS0#
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
G1
18
G2
SPI_WP#_SEL41

+3.3V_SPI +3.3V_M
1 2
RH350 0_0402_5%~DRH350 0_0402_5%~D
1 2
RH345 0_0402_5%~DRH345 0_0402_5%~D
1 2
RH346 0_0402_5%~DRH346 0_0402_5%~D
1 2
RH347 0_0402_5%~DRH347 0_0402_5%~D
1 2
RH348 0_0402_5%~DRH348 0_0402_5%~D
1 2
RH349 0_0402_5%~DRH349 0_0402_5%~D
+3.3V_SPI
+3.3V_M
SPI_PCH_CS0# SPI_CS0#
SPI_PCH_DIN
5
PCH_AZ_MDC_SYNC31
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
R933 47_04 02_5%~DR933 47_0402_5%~D
R894 33_04 02_5%~DR894 33_0402_5%~D
R898 0_0402_5%~D@ R898 0_0402_5%~D@
1 2
1 2
SPI_DIN64
12
200 MIL SO8
R890
R890
64Mb Flash ROM
RH33 33_0402_5%~DRH33 33_0402_5%~D
RH31 1M_0402_5%~DRH31 1M_0402_5%~D
U52
1
/CS
2
DO
3
/WP
GND4DIO
W25Q64BVSSIG_SO8~D
W25Q64BVSSIG_SO8~D
SLP_ME_CSW_DE V#18,41
USB_MCARD1_DET#18,36
PCH_AZ_CODEC_SDIN030
PCH_PLTRST#_EC17,34,36,37,41,42
1 2
X76@U52
X76@
4
USB_OC0#_R17
USB_OC1#_R17
USB_OC2#17
USB_OC3#17
USB_OC4#17
USB_OC5#17
USB_OC6#17
SIO_EXT_SMI#17,42
EN_ESATA_RPTR#18
TEMP_ALERT#18,41
PCH_GPIO1518
SIO_EXT_SCI#_R18
PCH_RSMRST#_Q16,42
PCH_AZ_MDC_BITCLK31
PCH_AZ_MDC_RST#31
PCH_AZ_MDC_SDIN131
ME_FWP41
PCH_AZ_SYNC_Q
12
VCC
/HOLD
CLK
4
GPIO3618
GPIO3718
CH2
CH2
18P_0402_50V8J~D
18P_0402_50V8J~D
12
CH3
CH3
18P_0402_50V8J~D
18P_0402_50V8J~D
12
CH100
@CH100
@
27P_0402_50V8J~D
27P_0402_50V8J~D
SPKR30
+3.3V_ALW_PCH
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
+3.3V_SPI
12
8
7
SPI_CLK64SPI_WP#_SEL
6
SPI_DO64
5
Can be place in 0 height area.
HDD_DET#_R
BBS_BIT0_R
1
12
RH36 33_0402_5%~DRH36 33_0402_5%~D
RH50 1K_0402_5%~DRH50 1K_0402_5%~D
G
G
2
S
S
QH7
QH7
C746
C746
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
R891
R891
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
R899 33_04 02_5%~DR899 33_0402_5%~D
1 2
R901 33_04 02_5%~DR901 33_0402_5%~D
RH1 33_0402_5%~D@RH1 33_0402_5%~D@
RH3 33_0402_5%~D@RH3 33_0402_5%~D@
RH4 33_0402_5%~D@RH4 33_0402_5%~D@
RH5 33_0402_5%~D@RH5 33_0402_5%~D@
RH6 33_0402_5%~D@RH6 33_0402_5%~D@
RH7 33_0402_5%~D@RH7 33_0402_5%~D@
RH8 33_0402_5%~D@RH8 33_0402_5%~D@
RH9 33_0402_5%~D@RH9 33_0402_5%~D@
RH10 33_0402_5%~D@RH10 33_0402_5%~D@
RH12 33_0402_5%~D@RH12 33_0402_5%~D@
RH13 33_0402_5%~D@RH13 33_0402_5%~D@
RH14 33_0402_5%~D@RH14 33_0402_5%~D@
RH15 33_0402_5%~D@RH15 33_0402_5%~D@
RH16 33_0402_5%~D@RH16 33_0402_5%~D@
RH17 33_0402_5%~D@RH17 33_0402_5%~D@
RH18 33_0402_5%~D@RH18 33_0402_5%~D@
RH19 33_0402_5%~D@RH19 33_0402_5%~D@
RH20 33_0402_5%~D@RH20 33_0402_5%~D@
RH24 1K_0402_5%~D@RH24 1K_0402_5%~D@
YH1
YH1
2
G
G
34
G
G
32.768KHZ_12.5PF_Q13MC1461000~D
32.768KHZ_12.5PF_Q13MC1461000~D
1 2
RH286 0_0402_5%~DRH286 0_0402_5%~D
1 2
RH32 33_0402_5%~DRH32 33_0402_5%~D
1 2
RH34 33_0402_5%~DRH34 33_0402_5%~D
1 2
RH287 1K_0402_5%~D@ RH287 1K_0402_5%~D@
1 2
1 2
USB30_SMI#29
12
12
RH48
RH49
@ RH 48
@
@ RH 49
@
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
PCH_AZ_SYNC
13
D
D
SPI_PCH_CLK
SPI_PCH_DO
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RSMRST#_XDP
12
PCH_RTCX1
PCH_RTCX1
12
RH2
RH2
10M_0402_5%~D
10M_0402_5%~D
PCH_RTCX2
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_MDC_SDIN1
PCH_AZ_SDOUT
PCH_GPIO33
USB30_SMI#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
12
RH47
@ RH 47
@
100_0402_1%~D
100_0402_1%~D
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
SPI_PCH_CS1# SPI_CS1#
SPI_WP#_SEL
1 2
R935 47_04 02_5%~DR935 47_0402_5%~D
1 2
R895 33_04 02_5%~DR895 33_0402_5%~D
1 2
R896 0_0402_5%~D@R896 0_0402_5%~D@
3
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
DDR_XDP_WAN_ SMBDAT7,12,13,15,28,36
DDR_XDP_WAN_ SMBCLK7,12,13,15,28,36
A20
C20
D20
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
R888
R888
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_DIN32SPI_PCH_DIN
3
+3.3V_ALW_PCH
1.05V_0.8V_PWROK42,52
SIO_PWRBTN#_R7,16
UH4A
UH4A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
12
200 MIL SO8
16Mb Flash ROM
U53
X76@U53
X76@
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q16BVSSIG_SO8~D
W25Q16BVSSIG_SO8~D
1
CH1
@CH1
@
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
RH283 1K_0402_5%~D@RH283 1K_0 402_5%~D@
1 2
1 2
RH21 0_0402_5%~D@RH21 0_0402_5%~D@
RH284 0_0402_5%~D@RH284 0_0402_5%~D@
1 2
1 2
RH285 0_0402_5%~D@RH285 0_0402_5%~D@
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
/HOLD(IO3)
DI(IO0)
1.05V_0.8V_PWROK_R
PCH_PWRBTN#_X DP
DDR_XDP_WAN_ SMBDAT_R2
DDR_XDP_WAN_ SMBCLK_R2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
+3.3V_SPI
12
8
VCC
7
SPI_CLK32
6
CLK
SPI_DO32
5
2
+3.3V_ALW_PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
C38
A38
B37
C37
D36
E36
K36
IRQ_SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
+SATA_COMP
Y10
AB12
+SATA3_COMP
AB13
RBIAS_SATA3
AH1
SATA_ACT#
P3
HDD_DET#_R
V14
BBS_BIT0_R
P1
PCH_PLTRST#7,17
C745
C745
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
R892
R892
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
R897 33_04 02_5%~DR897 33_0402_5%~D
1 2
R900 33_04 02_5%~DR900 33_0402_5%~D
2
JXDP2
@JXDP2
@
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
LPC_LAD0 33,34,41,42
LPC_LAD1 33,34,41,42
LPC_LAD2 33,34,41,42
LPC_LAD3 33,34,41,42
LPC_LFRAME# 33,34,41,42
LPC_LDRQ0# 41
LPC_LDRQ1# 41
IRQ_SERIRQ 33,34,41,42
PSATA_PRX_DTX_N0_C 28
PSATA_PRX_DTX_P0_C 28
PSATA_PTX_DRX_N0_C 28
PSATA_PTX_DRX_P0_C 28
SATA_ODD_PRX_DTX_N1_C 29
SATA_ODD_PRX_DTX_P1_C 29
SATA_ODD_PTX_DRX_N1_C 29
SATA_ODD_PTX_DRX_P1_C 29
ESATA_PRX_DTX_N4_C 39
ESATA_PRX_DTX_P4_C 39
ESATA_PTX_DRX_N4_C 39
ESATA_PTX_DRX_P4_C 39
SATA_PRX_DKTX_N5_C 40
SATA_PRX_DKTX_P5_C 40
SATA_PTX_DKRX_N5_C 40
SATA_PTX_DKRX_P5_C 40
1 2
RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D
1 2
RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D
1 2
RH46 750_0402_1%~DRH46 750_0402_1%~D
SATA_ACT# 45
1 2
RH290 0_0402_5%~DRH290 0_0402_5%~D
D
S
D
S
1 3
QH1 BSS138W -7-F_SOT323-3~D
QH1 BSS138W -7-F_SOT323-3~D
G
G
2
SPI_PCH_CLK
SPI_PCH_DO
1
2
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
TMS
GND17
TD0
TDI
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
HDD
XDP_FN16
XDP_FN17
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
RSMRST#_XDP
XDP_DBRESET#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMSPCH_JTAG_TCK
IRQ_SERIRQ
PCH_AZ_SYNC_Q
PCH_GPIO33
BBS_BIT0_R
+3.3V_ALW_PCH
XDP_DBRESET# 7,16
+3.3V_RUN
RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D
RH37 10K_0402_5%~DRH37 10K_0402_5%~D
RH355 100K_0402_5%~DRH355 100K_0402_5%~D
RH51 4.7K_0402_5%~DRH51 4.7K_0402_5%~D
12
12
12
12
ODD/ E Module Bay
+3.3V_RUN
SPKR
RH35 10K_0402_5%~D@RH35 10K_0402_5%~D@
12
No Reboot Strap
Low = Default
SPKR
High = No Reboot
E-SATA
DOCK
+1.05V_RUN
+1.05V_RUN
+3.3V_RUN
12
RH30
RH30
10K_0402_5%~D
10K_0402_5%~D
PCH_SATA_MOD_EN# 42
HDD_DET# 28
BBS_BIT0 - BIOS BOOT STRAP BIT 0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/8)
PCH (1/8)
PCH (1/8)
LA-6591P
LA-6591P
LA-6591P
14 66Monday, January 10, 2011
14 66Monday, January 10, 2011
14 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
D D
Follow DG0.9 Device down & Express/Mini card
topology
PCIE_PRX_WANTX_N 136
MiniWWAN (Mini Card 1)--->
MiniWLAN (Mini Card 2)--->
EXPRESS Card--->
E3 Module Bay--->
1/2vMINI CARD-3 PCIE
(Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
MiniWWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI Card--->
B B
MiniWPAN (Mini Card 3)--->
Express card--->
MiniWLAN (Mini Card 2)--->
eModule Bay--->
A A
PCIE_PRX_WANTX_P 136
PCIE_PTX_WANRX_N 136
PCIE_PTX_WANRX_P 136
PCIE_PRX_WLANTX_ N236
PCIE_PRX_WLANTX_ P236
PCIE_PTX_WLANRX_ N236
PCIE_PTX_WLANRX_ P236
PCIE_PRX_EXPTX_N337
PCIE_PRX_EXPTX_P337
PCIE_PTX_EXPRX_N337
PCIE_PTX_EXPRX_P337
PCIE_PRX_EMBTX_N429
PCIE_PRX_EMBTX_P429
PCIE_PTX_EMBRX_N429
PCIE_PTX_EMBRX_P429
PCIE_PRX_WPANTX _N536
PCIE_PRX_WPANTX _P536
PCIE_PTX_WPANRX _N536
PCIE_PTX_WPANRX _P536
PCIE_PRX_MMITX_N635
PCIE_PRX_MMITX_P635
PCIE_PTX_MMIRX_N635
PCIE_PTX_MMIRX_P635
PCIE_PRX_GLANTX_N732
PCIE_PRX_GLANTX_P732
PCIE_PTX_GLANRX_N732
PCIE_PTX_GLANRX_P732
CLK_PCIE_MINI1#36
CLK_PCIE_MINI136
+3.3V_ALW_PCH
MINI1CLK_REQ#36
CLK_PCIE_LAN#32
CLK_PCIE_LAN32
LANCLK_REQ#32
CLK_PCIE_MMI#35
CLK_PCIE_MMI35
+3.3V_RUN
MMICLK_REQ#35
CLK_PCIE_MINI3#36
CLK_PCIE_MINI336
+3.3V_ALW_PCH
MINI3CLK_REQ#36
CLK_PCIE_EXP#37
CLK_PCIE_EXP37
+3.3V_ALW_PCH
EXPCLK_REQ#37
CLK_PCIE_MINI2#36
CLK_PCIE_MINI236
+3.3V_ALW_PCH
MINI2CLK_REQ#36
+3.3V_ALW_PCH
CLK_PCIE_EMB#29
CLK_PCIE_EMB29
+3.3V_ALW_PCH
EMBCLK_REQ#29
CLK_CPU_ITP#7
CLK_CPU_ITP7
RH307 0_0402_5%~DRH307 0_0402_5%~D
RH308 0_0402_5%~DRH308 0_0402_5%~D
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
RH82 0_0402_5%~DRH82 0_0402_5%~D
RH83 0_0402_5%~DRH83 0_0402_5%~D
RH85 0_0402_5%~DRH85 0_0402_5%~D
RH86 0_0402_5%~DRH86 0_0402_5%~D
RH87 10K_0402_5%~DRH87 10K_0402_5%~D
RH88 0_0402_5%~DRH88 0_0402_5%~D
RH90 0_0402_5%~DRH90 0_0402_5%~D
RH152 10K_0402_5%~DRH152 10K_0402_5%~D
RH92 0_0402_5%~DRH92 0_0402_5%~D
RH93 0_0402_5%~DRH93 0_0402_5%~D
RH94 10K_0402_5%~DRH94 10K_0402_5%~D
RH95 0_0402_5%~DRH95 0_0402_5%~D
RH96 0_0402_5%~DRH96 0_0402_5%~D
RH97 10K_0402_5%~DRH97 10K_0402_5%~D
RH98 10K_0402_5%~DRH98 10K_0402_5%~D
RH310 0_0402_5%~DRH310 0_0402_5%~D
RH312 0_0402_5%~DRH312 0_0402_5%~D
RH104 10K_0402_5%~DRH104 10K_0402_5%~D
RH280 0_0402_5%~DRH280 0_0402_5%~D
RH281 0_0402_5%~DRH281 0_0402_5%~D
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
5
1 2
1 2
4
UH4B
UH4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_MMI#
PCIE_MMI
MMICLK_REQ#
PCIE_MINI3#
PCIE_MINI3
MINI3CLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PEG_B_CLKRQ#
PCIE_EMB#
PCIE_EMB
EMBCLK_REQ#
CLK_BCLK_ITP#
CLK_BCLK_ITP
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
3
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
XCLK_RCOMP
PCI_TCM
SIO_14M
PCI_TPM
JETWAY_14M
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
PEG_A_CLKRQ#
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_DPLL#
CLK_CPU_DPLL
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
2
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH 7
LAN_SMBCLK 32
LAN_SMBDATA 32
SML1_SMBCLK 42
SML1_SMBDATA 42
PCH_CL_CLK1 36
PCH_CL_DATA1 36
PCH_CL_RST1# 36
CLK_CPU_DMI# 7
CLK_CPU_DMI 7
CLK_CPU_DPLL# 7
CLK_CPU_DPLL 7
CLK_PCI_LOOPBACK 17
1 2
RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D
RH311 22_0402_5%~D4@ RH311 22_0402_5%~D4@
RH313 22_0402_5%~DRH313 22_0402_5%~D
RH314 22_0402_5%~DRH314 22_0402_5%~D
RH315 22_0402_5%~D@RH315 22_0402_5%~D@
12
12
12
12
2
+3.3V_RUN
QH5A
QH5A
2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
6 1
5
3
4
QH5B
QH5B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1 2
RH296 0_0402_5%~D@RH296 0_0402_5%~D@
1 2
RH297 0_0402_5%~D@RH297 0_0402_5%~D@
SML1_SMBCLK
SML1_SMBDATA
DDR_HVREF_RST_PCH
GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
PEG_A_CLKRQ#
LAN_SMBCLK
LAN_SMBDATA
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
DDR_XDP_WAN_ SMBCLK 7,12,13,14,28,36
DDR_XDP_WAN_ SMBDAT 7,12,13,14,28,36
RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D
RH300 1K_0402_5%~DRH300 1K_0402_5%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
RH304 10K_0402_5%~DRH304 10K_0402_5%~D
RH80 10K_0402_5%~DRH80 10K_0402_5%~D
RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D
RH74 10K_0402_5%~DRH74 10K_0402_5%~D
RH75 10K_0402_5%~DRH75 10K_0402_5%~D
RH91 10K_0402_5%~DRH91 10K_0402_5%~D
RH76 10K_0402_5%~DRH76 10K_0402_5%~D
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
RH183 10K_0402_5%~DRH183 10K_0402_5%~D
CLOCK TERMINATION for FCIM and need close to PCH
RH309 0_0402_5%~DR H309 0_040 2_5%~D
12
RH99
RH99
1M_0402_5%~D
+1.05V_RUN
CLK_PCI_TPM_CHA 34
CLK_SIO_14M 41
CLK_PCI_TPM 33
JETWAY_CLK14M 34
1M_0402_5%~D
25MHZ_18PF_7A25000110~D
25MHZ_18PF_7A25000110~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/8)
PCH (2/8)
PCH (2/8)
LA-6591P
LA-6591P
LA-6591P
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
2
CH18
CH18
1
18P_0402_50V8J~D
18P_0402_50V8J~D
1
12
YH2
YH2
12
12
12
12
12
12
12
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_LAN
12
15 66Monday, January 10, 2011
15 66Monday, January 10, 2011
15 66Monday, January 10, 2011
2
CH19
CH19
1
18P_0402_50V8J~D
18P_0402_50V8J~D
1.0
1.0
1.0
5
+3.3V_ALW_PCH
1 2
RH318 10K_0402_5%~D@R H318 10K_ 0402_5%~D@
D D
+3.3V_RUN
1 2
RH144 10K_0402_5%~DRH144 10K_0402_5 %~D
1 2
RH142 10K_0402_5%~DRH142 10K_0402_5 %~D
1 2
RH319 10K_0402_5%~D@R H319 10K_ 0402_5%~D@
1 2
RH140 10K_0402_5%~DRH140 10K_0402_5 %~D
1 2
RH137 8.2K_0402_5%~DRH137 8.2K_0402_5%~D
SUS_STAT#/LPCPD#
ME_SUS_PWR_A CK
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_RI#
CLKRUN#
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_A CK_R
PCH_RSMRST#_Q
ME_SUS_PWR_A CK
4
1 2
RH113 0_0402_5%~DRH113 0_04 02_5%~D
SYS_PWROKRESET_OUT#
1 2
RH321 0_0402_5%~D@RH321 0_0402_5%~D@
SUSACK#_R
1 2
RH323 0_0402_5%~DRH323 0_0402_5%~D
1 2
RH322 10K_0402_5%~DRH322 10K_0402_5 %~D
1 2
RH145 10K_0402_5%~D@R H145 10K_ 0402_5%~D@
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
HIGH: R221 STUFFED,
R222 UNSTUFFED
Disabled
LOW: R221 STUFFED,
R222 UNSTUFFED
3
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
G_CLK_DDC2
RH316
RH316
12
12
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
RH317
RH317
61
QH6A
QH6A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
2
5
QH6B
QH6B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
4
2
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DATG_DAT_DDC2
PCH_CRT_DDC_CLK 25
PCH_CRT_DDC_DAT 25
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
1
+3.3V_RUN
RH351 2.2K_0402_5%~DRH351 2.2K_0402_5%~D
RH352 2.2K_0402_5%~DRH352 2.2K_0402_5%~D
12
12
L_DDC_DATA - LVDS Detected
LVDS is detected1
UH4C
UH4C
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_SUS#
H_PM_SYNC
SIO_SLP_LAN#
FDI_CTX_PRX_N0 6
FDI_CTX_PRX_N1 6
FDI_CTX_PRX_N2 6
FDI_CTX_PRX_N3 6
FDI_CTX_PRX_N4 6
FDI_CTX_PRX_N5 6
FDI_CTX_PRX_N6 6
FDI_CTX_PRX_N7 6
FDI_CTX_PRX_P0 6
FDI_CTX_PRX_P1 6
FDI_CTX_PRX_P2 6
FDI_CTX_PRX_P3 6
FDI_CTX_PRX_P4 6
FDI_CTX_PRX_P5 6
FDI_CTX_PRX_P6 6
FDI_CTX_PRX_P7 6
FDI_INT 6
FDI_FSYNC0 6
FDI_FSYNC1 6
FDI_LSYNC0 6
FDI_LSYNC1 6
RH127 330K_0402_1%~DRH127 330K_0402_1%~D
1 2
RH129 330K_0402_1%~D@RH129 330K_0402_1%~D@
1 2
PCH_PCIE_WAKE# 41
CLKRUN# 34,41,42
T56 PAD~DT56 P AD~D
T57 PAD~DT57 P AD~D
T58 PAD~DT58 P AD~D
SIO_SLP_S5# 42
T59 PAD~DT59 P AD~D
SIO_SLP_S4# 41
T60 PAD~DT60 P AD~D
SIO_SLP_S3# 41
T61 PAD~DT61 P AD~D
SIO_SLP_A# 41,50
T62 PAD~DT62 P AD~D
SIO_SLP_SUS# 41
T63 PAD~DT63 P AD~D
H_PM_SYNC 7
SIO_SLP_LAN# 32,41
3
+RTC_CELL
PCH_CRT_HSYNC25
PCH_CRT_VSYNC25
PANEL_BKEN_PCH24
BIA_PWM_PCH24
LDDC_CLK_PCH24
LDDC_DATA_PCH24
LCD_ACLK-_PCH24
LCD_ACLK+_PCH24
LCD_A0-_PCH24
LCD_A1-_PCH24
LCD_A2-_PCH24
LCD_A0+_PCH2 4
LCD_A1+_PCH2 4
LCD_A2+_PCH2 4
LCD_BCLK-_PCH24
LCD_BCLK+_PCH24
LCD_B0-_PCH24
LCD_B1-_PCH24
LCD_B2-_PCH24
LCD_B0+_PCH2 4
LCD_B1+_PCH2 4
LCD_B2+_PCH2 4
PCH_CRT_BLU25
PCH_CRT_GRN25
PCH_CRT_RED25
RH131 150_04 02_1%~DRH131 150_0402_1%~D
RH132 150_04 02_1%~DRH132 150_0402_1%~D
RH133 150_04 02_1%~DRH133 150_0402_1%~D
RH134 100K _0402_5%~DRH134 100K_0402_5%~D
DMI_COMP_R
RBIAS_CPY
1 2
PCH_RI#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
XDP_DBRESET#
SYS_PWROK_R
PM_APWROK_R
PM_DRAM_PWR GD_R
PCH_RSMRST#_R
ME_SUS_PWR_A CK_R
SIO_PWRBTN#_R
SIO_PWRBTN#_R
PCH_BATLOW#
DMI_CTX_PRX_N06
DMI_CTX_PRX_N16
DMI_CTX_PRX_N26
DMI_CTX_PRX_N36
DMI_CTX_PRX_P06
C C
+1.05V_RUN
SUSACK#41 PCH_DPWROK 41
B B
SYS_PWROK7,41
RESET_OUT#42
PM_APWROK42
PM_DRAM_PWR GD7
PCH_RSMRST#_Q14,42
ME_SUS_PWR_A CK42
SIO_PWRBTN#_R7,14
SIO_PWRBTN#42
AC_PRESENT42
+3.3V_ALW_PCH
A A
DMI_CTX_PRX_P16
DMI_CTX_PRX_P26
DMI_CTX_PRX_P36
DMI_CRX_PTX_N06
DMI_CRX_PTX_N16
DMI_CRX_PTX_N26
DMI_CRX_PTX_N36
DMI_CRX_PTX_P06
DMI_CRX_PTX_P16
DMI_CRX_PTX_P26
DMI_CRX_PTX_P36
1 2
RH111 49.9_0402_1%~DRH111 49.9_0402_1%~D
1 2
RH112 750_0402_1%~DRH112 750_0402_1%~D
1 2
RH114 0_0402_5%~D@RH114 0_0402_5%~D@
XDP_DBRESET#7,14
1 2
RH116 0_0402_5%~DRH116 0_0402_5%~D
1 2
RH117 0_0402_5%~DRH117 0_0402_5%~D
1 2
RH118 0_0402_5%~DRH118 0_0402_5%~D
1 2
RH320 0_0402_5%~DRH320 0_0402_5%~D
1 2
RH120 0_0402_5%~DRH120 0_0402_5%~D
1 2
RH121 0_0402_5%~DRH121 0_0402_5%~D
RH122 0_0402_5%~DRH122 0_0402_5%~D
1 2
RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D
5
SUSACK#_R
PCH_PWROK
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPW RDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
BJ14
FDI_RXN0
AY14
FDI_RXN1
BE14
FDI_RXN2
BH13
FDI_RXN3
BC12
FDI_RXN4
BJ12
FDI_RXN5
BG10
FDI_RXN6
BG9
FDI_RXN7
BG14
FDI_RXP0
BB14
FDI_RXP1
BF14
FDI_RXP2
BG13
FDI_RXP3
BE12
FDI_RXP4
BG12
FDI_RXP5
BJ10
DMI
DMI
System Power Management
System Power Management
4
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
LVDS is not detected0
ENVDD_PCH24,41
LDDC_CLK_PCH
LDDC_DATA_PCH
1 2
RH344 2.37K_0402_1%~DRH344 2.37K_0402_1%~D
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
G_CLK_DDC2
G_DAT_DDC2
RH123 20_0402_1%~DRH123 20_0402_1%~D
1 2
1 2
RH124 20_0402_1%~DRH124 20_0402_1%~D
1K_0402_0.5%~D
1K_0402_0.5%~D
1 2
1 2
1 2
1 2
PANEL_BKEN_PCH
ENVDD_PCH
BIA_PWM_PCH
L_IBG
HSYNC
VSYNC
CRT_IREF
12
RH126
RH126
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
UH4D
UH4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
2
LVDS
LVDS
Digital Display Interface
Digital Display Interface
CRT
CRT
Intel request DDPB can not support eDP
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PCH_SDVO_CTRLCLK 26
PCH_SDVO_CTRLDATA 26
HDMIB_PCH_HPD 26
TMDSB_PCH_N2 26
TMDSB_PCH_P2 26
TMDSB_PCH_N1 26
TMDSB_PCH_P1 26
TMDSB_PCH_N0 26
TMDSB_PCH_P0 26
TMDSB_PCH_CLK# 26
TMDSB_PCH_CLK 26
PCH_DDPC_CTRLCLK 27
PCH_DDPC_CTRLDAT A 27
DPC_PCH_DOCK_AUX# 27
DPC_PCH_DOCK_AUX 27
DPC_PCH_DOCK_HPD 40
DPC_PCH_LANE_N0 40
DPC_PCH_LANE_P0 40
DPC_PCH_LANE_N1 40
DPC_PCH_LANE_P1 40
DPC_PCH_LANE_N2 40
DPC_PCH_LANE_P2 40
DPC_PCH_LANE_N3 40
DPC_PCH_LANE_P3 40
PCH_DDPD_CTRLCLK 27
PCH_DDPD_CTRLDAT A 27
DPD_PCH_DOCK_AUX# 27
DPD_PCH_DOCK_AUX 27
DPD_PCH_DOCK_HPD 40
DPD_PCH_LANE_N0 40
DPD_PCH_LANE_P0 40
DPD_PCH_LANE_N1 40
DPD_PCH_LANE_P1 40
DPD_PCH_LANE_N2 40
DPD_PCH_LANE_P2 40
DPD_PCH_LANE_N3 40
DPD_PCH_LANE_P3 40
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/8)
PCH (3/8)
PCH (3/8)
LA-6591P
LA-6591P
LA-6591P
16 66Monday, January 10, 2011
16 66Monday, January 10, 2011
16 66Monday, January 10, 2011
1
1.0
1.0
1.0
+3.3V_RUN
5
4
3
2
1
PLTRST_USH#33
PLTRST_MMI#35
PLTRST_XDP#7
PLTRST_LAN#32
PLTRST_EMB#29
PCH_PLTRST#
5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
ATG_MAC_LCD_DET#
CAM_MIC_CBL_DET#
BT_DET#
PCH_GPIO3
RH335 0_0402_5%~DRH335 0_0402_5%~D
RH336 0_0402_5%~DRH336 0_0402_5%~D
RH337 0_0402_5%~DRH337 0_0402_5%~D
RH338 0_0402_5%~DRH338 0_0402_5%~D
RH340 0_0402_5%~DRH340 0_0402_5%~D
CLK_PCI_LOOPBACK15
+3.3V_RUN
5
UH3
UH3
1
P
B
2
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
HDD_FALL_INT28
1 2
1 2
1 2
1 2
1 2
CLK_PCI_502841
CLK_PCI_MEC42
CLK_PCI_DOCK40
CH102
CH102
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
4
O
PCIE_MCARD2_DET#36
BT_DET#43
ATG_MAC_LCD_DET#24
CAM_MIC_CBL_DET#24
1 2
RH334 0_0402_5%~DRH334 0_0402_5%~D
1 2
12
12
12
4
RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 33_0402_5%~DRH103 33_0402_5%~D
RH105 22_0402_5%~DRH105 22_0402_5%~D
PCH_PLTRST#_EC 14,34,36,37,41,42
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
BT_DET#
BBS_BIT1
PCI_GNT3#
ATG_MAC_LCD_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
FFS_PCH_INT
T104PAD~D @T104PAD~D @
PCH_PLTRST#
PCI_5028
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
UH4E
UH4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
RSVD
RSVD
PCI
PCI
USB
USB
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
0 0
0 1
1 0
1 1
LPC
Reserved (NAND)
PCI
SPI
3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USBP8ÂUSBP8+
USBP9ÂUSBP9+
USBP10ÂUSBP10+
USBP11ÂUSBP11+
USBP12ÂUSBP12+
USBP13ÂUSBP13+
USBRBIAS
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USBP0- 38
USBP0+ 38
USBP1- 38
USBP1+ 38
USBP2- 39
USBP2+ 39
USBP3- 31
USBP3+ 31
USBP4- 36
USBP4+ 36
USBP5- 36
USBP5+ 36
USBP6- 36
USBP6+ 36
USBP7- 33
USBP7+ 33
USBP8- 40
USBP8+ 40
USBP9- 40
USBP9+ 40
USBP10- 37
USBP10+ 37
USBP11- 43
USBP11+ 43
USBP12- 24
USBP12+ 24
USBP13- 24
USBP13+ 24
Within 500 mils
1 2
RH151
RH151
22.6_0402_1%~D
22.6_0402_1%~D
1 2
RH339 0_0402_5%~DRH339 0_0402_5%~D
1 2
RH341 0_0402_5%~DRH341 0_0402_5%~D
BBS_BIT1
12
----->Right Side 1
----->Right Side 2
----->Right Side (ESATA)
----->Left Side
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash
----->USH
----->DOCK
----->DOCK
----->Express Card
----->Blue Tooth
----->Camera
----->LCD Touch
USB_OC0# 39
USB_OC1# 31,39
USB_OC2# 14
USB_OC3# 14
USB_OC4# 14
USB_OC5# 14
USB_OC6# 14
SIO_EXT_SMI# 14,42
USB_OC0#_R 14
USB_OC1#_R 14
RH342
@RH342
@
1K_0402_5%~D
1K_0402_5%~D
2
+3.3V_ALW_PCH
RPH1
USB_OC0#
USB_OC1#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC2#
SIO_EXT_SMI#
RH41 10K_0402_5%~DRH41 10K_0402_5%~D
RPH1
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
RPH2
RPH2
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/8)
PCH (4/8)
PCH (4/8)
LA-6591P
LA-6591P
LA-6591P
17 66Monday, January 10, 2011
17 66Monday, January 10, 2011
17 66Monday, January 10, 2011
1
1.0
1.0
1.0
1 2
D D
C C
RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D
1 2
RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~DRH327 10K_0402_5 %~D
1 2
RH330 10K_0402_5%~DRH330 10K_0402_5 %~D
1 2
RH331 10K_0402_5%~DRH331 10K_0402_5 %~D
1 2
RH328 10K_0402_5%~DRH328 10K_0402_5 %~D
1 2
RH332 10K_0402_5%~D@R H332 10K_ 0402_5%~D@
PCI_GNT3#
12
RH333
@RH333
@
1K_0402_5%~D
1K_0402_5%~D
A16 swap overrid e Strap/Top-Bloc k
Swap Override jumper
PCI_GNT#3
B B
A A
PCH_PLTRST#7,14
Low = A16 swap
High = Default
5
+3.3V_ALW_PCH
D D
RH354 1K_0402_5%~DRH354 1K_0402_5%~D
1 2
PCH_GPIO15
PCH_GPIO15 TLS Confidentiality
Low = Intel ME Crypto Transport Layer
Security (TLS) cipher suite with no
confidentiality
High = Intel ME Crypto TLS cipher suite
with confidentiality
+3.3V_ALW_PCH
RH356
RH356
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
C C
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
+3.3V_ALW_PCH
B B
+3.3V_ALW_PCH
+3.3V_RUN
A A
SLP_ME_CSW_DE V#
RH353
@ RH353
@
1K_0402_5%~D
1K_0402_5%~D
1 2
KB_DET#
GPIO36
12
GPIO37
12
EN_ESATA_RPTR#
12
TEMP_ALERT#
12
MEDIA_DET#
12
GPIO17
IO_LOOP#
LEDB_DET#
GPIO17
12
SIO_EXT_WAKE#
5
1 2
RH177 10K_0402_5%~DRH177 10K_0402_5 %~D
1 2
RH170 10K_0402_5%~DRH170 10K_0402_5%~D
RH171, RH173 should be no pop as reverse strap.
RH171 10K_0402_5%~D@R H171 10K_0402_5%~D@
RH173 1K_0402_5%~D@RH173 1K_0402_5%~D@
RH265 10K_0402_5%~DRH265 10K_0402_5%~D
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH179 10K_0402_5%~DRH179 10K_0402_5%~D
1 2
RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D
1 2
RH163 10K_0402_5%~DRH163 10K_0402_5%~D
1 2
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
RH273 1K_0402_5%~D@RH273 1K_0402_5%~D@
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
SIO_EXT_SCI#_R14
SIO_EXT_SCI#42
IO_LOOP#31
LEDB_DET#31
SIO_EXT_WAKE#41
PM_LANPHY_ENABLE32
PCH_GPIO1514
EN_ESATA_RPTR#14
MEDIA_DET#31
PCIE_MCARD1_DET#36
E3_PAID_TS_DET#24
SLP_ME_CSW_DE V#14,41
USB_MCARD1_DET#14,36
FFS_INT228
TEMP_ALERT#14,41
KB_DET#43
+3.3V_RUN
TPM_ID0
GPIO3614
GPIO3714
1@ RH267
1@
1 2
2@ RH270
2@
1 2
4
SIO_EXT_SCI#
PCH_GPIO1
IO_LOOP#
LEDB_DET#
SIO_EXT_WAKE#
PCH_GPIO15
EN_ESATA_RPTR#
GPIO17
MEDIA_DET#
E3_PAID_TS_DET#
SLP_ME_CSW_DE V#
GPIO36
GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
RH267
10K_0402_5%~D
10K_0402_5%~D
TPM_ID1
RH270
10K_0402_5%~D
10K_0402_5%~D
4
1 2
RH259 0_0402_5%~DRH259 0_0402_5%~D
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
+3.3V_RUN
12
RH268
3@ R H268
3@
20K_0402_5%~D
20K_0402_5%~D
12
RH271
4@ R H271
4@
2.2K_0402_5%~D
2.2K_0402_5%~D
UH4F
UH4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
No TPM, No China TPM
China TPM
USH2.0
GPIO
GPIO
3
CPU/MISC
CPU/MISC
NCTF
NCTF
3
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
0
0
1 1
TPM_ID1TPM_ID0
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
0
1
CONTACTLESS_DET#
GPIO69
SIO_A20GATE
H_PECI_R
SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R
INIT3_3V#
DF_TVS
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
CONTACTLESS_DET# 33
PCIE_MCARD3_DET# 36
USB_MCARD2_DET# 36
SIO_A20GATE 42
1 2
RH159 0_0402_5%~D@RH159 0_0402_5%~D@
SIO_RCIN# 42
H_CPUPWRGD 7
T106@T106@
T108@T108@
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
RH261 0_0402_5%~DRH261 0_0402_5%~D
2
1 2
RH262 56_0402_5%~DR H262 56_04 02_5%~D
1
CH97
CH97
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
PECI_EC 42
H_PECI 7
+1.05V_RUN_VTT
12
1
+3.3V_RUN
CONTACTLESS_DET#
GPIO69
PLACE RH150 CLOS E TO THE BRANCHI NG POINT
( TO CPU and NVR AM CONNECTOR)
1 2
RH256 10K _0402_1%~DRH256 10K_0402_1%~D
1 2
RH260 1.5K_0402 _1%~DRH260 1.5K_0402_1%~D
SIO_A20GATE
SIO_RCIN#
PCH_GPIO1
SIO_EXT_SCI#
RH158 10K_0402_5%~DRH158 10K_0402_5 %~D
RH203 10K_0402_5%~DRH203 10K_0402_5 %~D
1 2
RH164 10K_0402_5%~DRH164 10K_0402_5 %~D
1 2
RH263 10K_0402_5%~DRH263 10K_0402_5 %~D
+VCCDFTERM
RH149 need to cl ose to CPU
12
RH149
RH149
2.2K_0402_5%~D
2.2K_0402_5%~D
DF_TVS_R
RH150 0_0402 _5%~DRH150 0_0402_5%~D
12
12
1 2
+3.3V_RUN
DF_TVS
DMI & FDI Termination Voltage
DF_TVS
Set to Vss when LOW
Set to Vcc when HIGH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/8)
PCH (5/8)
PCH (5/8)
LA-6591P
LA-6591P
LA-6591P
18 66Monday, January 10, 2011
18 66Monday, January 10, 2011
18 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
4
3
2
1
POWER
+1.05V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
D D
+1.05V_RUN
2
CH30
CH30
+1.05V_RUN
CH32
CH32
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
CH31
CH31
CH33
CH33
2
50 mA
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH47
CH47
+VCCAPLLEXP
1
CH40
CH40
2
@
@
10U_0805_4VAM~D
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH48
CH48
2
+VCCAPLL_FDI
1 2
RH247
@RH247
@
C C
B B
+1.05V_RUN
+3.3V_RUN
+1.05V_RUN
RH195 0.022_0805_1%@RH195 0.022_0805_1%@
1 2
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CH44
CH44
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH51
CH51
2
+VCCAPLL_FDI
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH46
CH46
CH45
CH45
2
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
+1.05V_RUN_VTT
1
2
UH4G
UH4G
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
DMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
DFT / SPI HVCMOS
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
+VCCADAC
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
2
+1.8V_RUN_LVDS
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH103
CH103
1
2
1
CH43
CH43
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH50
CH50
2
2
1
CH52
CH52
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH34
CH34
CH35
CH35
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH104
CH104
1
2
+1.05V_+1.5V_1.8V_RUN
1 2
CH49
CH49
10U_0603_4VAM~D
10U_0603_4VAM~D
LH9
LH9
@
@
HK1608R10J-T_0603~D
HK1608R10J-T_0603~D
CH106
CH106
+VCCDFTERM
CH54
CH54
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
LH1
LH1
BLM18PG181SN1_0603~D
BLM18PG181SN1_0603~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CH36
CH36
2
+3.3V_RUN
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
LH8
LH8
CH105
CH105
HK1608R10J-T_0603~D
HK1608R10J-T_0603~D
1
2
+3.3V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
12
+1.05V_RUN
1 2
RH276 0_0805_5%~D@RH276 0_0805_5%~D@
PJP51
PJP51
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
+3.3V_M
12
12
+3.3V_RUN
+1.8V_RUN
+1.05V_RUN_VTT
+3.3V_RUN
+1.8V_RUN
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax
Current (A)
0.001
5
5
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
1.05VccIO 2.925
VccASW
VccSPI
VccDSW3_3 0.003
1.05
3.3
3.3
1.01
0.020
1.8 0.19VccpNAND
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
0.119
0.01
VccVRM 1.8 / 1.5 0.16
1.05VccClkDMI 0.02
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.06
+1.5V_RUN
+1.8V_RUN
+1.05V_RUN
A A
RH197 0_0603_5%~DRH197 0_0603_5%~D
RH198 0_0603_5%~D@RH198 0_0603_5%~D@
RH199 0_0603_5%~D@RH199 0_0603_5%~D@
12
12
12
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
1
+
CH41
@+CH41
@
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
2
1
+
CH42
@+CH42
@
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/8)
PCH (6/8)
PCH (6/8)
LA-6591P
LA-6591P
LA-6591P
19 66Monday, January 10, 2011
19 66Monday, January 10, 2011
19 66Monday, January 10, 2011
1
1.0
1.0
1.0
5
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW2
D D
+1.05V_RUN
C C
+3.3V_RUN
1 2
RH215 0.022_0805_1%@RH215 0.022_0805_1%@
B B
+1.05V_M
RH248 0.022_0805_ 1%@RH248 0.022_0805 _1%@
A A
+1.05V_RUN
1 2
+1.05V_M_VCCSUS
1 2
RH201 0_0402_5%~DRH201 0_0402_5%~D
RH253 0_0402_5%~D@RH253 0_0402_5%~D@
Note: Check Inte l
+1.05V_RUN
+1.05V_RUN_VTT
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
5
1 2
LH3
@LH3
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
@CH58
@
1
+1.05V_RUN
CH58
2
+1.05V_M
LH4
LH4
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
1
CH85
CH85
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
LH6
LH6
1 2
1 2
LH7
LH7
+3.3V_RUN_VCC_CLKF33
1
CH73
CH73
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1
CH94
CH94
+
+
2
RH200 0.022_0805_ 1%@RH200 0.022_0805 _1%@
1
CH55
CH55
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH74
CH74
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH78
CH78
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH79
CH79
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CH96
CH96
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH86
CH86
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH92
CH92
1
+
+
2
2
1 2
@CH57
@
1
2
1
2
1 2
CH84
CH84
1
2
CH95
CH95
1
2
4
CH57
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CH64
CH64
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH67
CH67
2
CH81
CH81
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
+RTC_CELL
CH87
CH87
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH93
CH93
4
+VCCACLK
+VCCDSW3_3
+PCH_VCCDSW
1
+3.3V_RUN_VCC_CLKF33
2
+VCCAPLL_CPY_PCH
+VCCSUS1
1
@
@
CH61
CH61
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CH65
CH65
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH69
CH69
CH68
CH68
2
+VCCRTCEXT
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
+VCCSST
+1.05V_M_VCCSUS
1
CH83
@CH83
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
1
CH89
CH89
CH88
CH88
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05V_RUN_VCCA_A_DPL +1.05V_R UN_VCCA_B_DPL
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
AG33
V16
T17
V19
BJ8
A22
1
CH90
CH90
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1 2
RH279 0_0805_5%~D@RH279 0_0805_5%~D@
UH4J
UH4J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3[5]
VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]
VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCADPLLA
VCCADPLLB
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCSSC
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO
VCCRTC
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
3
POWER
POWER
N26
VCCIO[29]
P26
VCCIO[30]
P28
VCCIO[31]
T27
VCCIO[32]
T29
VCCIO[33]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
V5REF
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
VCCAPLLSATA
SATA USB
SATA USB
VCCASW[22]
VCCASW[23]
HDA
HDA
VCCASW[21]
VCCSUSHDA
3
CPURTC
CPURTC
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+PCH_V5REF_SUS
+VCCA_USBSUS
+PCH_V5REF_RUN
1
2
+1.05V_RUN_VCC_SATA
1
CH91
CH91
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
CH56
CH56
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH59
CH59
CH70
CH70
1U_0603_10V6K~D
1U_0603_10V6K~D
1
CH76
CH76
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
+3.3V_RUN
CH60
CH60
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH66
CH66
2
1
CH72
CH72
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH82
CH82
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
+1.05V_RUN
+3.3V_ALW_PCH
1
CH75
CH75
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH77
CH77
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+1.05V_M
2
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
1
CH80
@CH80
@
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
2
+1.05V_RUN
+3.3V_ALW_PCH
1
RH202
RH202
0_0402_5%~D
0_0402_5%~D
1 2
D
S
D
S
1 3
QH4
@
QH4
@
12
RH208
RH208
12
RH213
RH213
+VCCA_USBSUS
G
G
1
2
2
+3.3V_ALW_PCH+5V_ALW_PCH
21
DH2
DH2
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_SUS
1
CH63
CH63
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+3.3V_RUN+5V_RUN
21
DH3
DH3
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_RUN
1
CH71
CH71
1U_0603_10V6K~D
1U_0603_10V6K~D
2
1
CH62
@CH62
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+3.3V_RUN
+1.05V_RUN
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
ALW_ENABLE44
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
Note: Check Inte l
LH5
@LH5
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
+1.05V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
ize Document Number Rev
Size Document Number Rev
Size Document Number Rev
S
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (7/8)
PCH (7/8)
PCH (7/8)
LA-6591P
LA-6591P
LA-6591P
20 66Monday, January 10, 2011
20 66Monday, January 10, 2011
20 66Monday, January 10, 2011
1
+5V_ALW_PCH+5V_ALW
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
20K_0402_5%~D
20K_0402_5%~D
@RH278
@
12
RH278
CH98
CH98
1.0
1.0
1.0
5
D D
C C
B B
A A
UH4H
UH4H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
4
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
UH4I
UH4I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (8/8)
PCH (8/8)
PCH (8/8)
LA-6591P
LA-6591P
LA-6591P
21 66Monday, January 10, 2011
21 66Monday, January 10, 2011
21 66Monday, January 10, 2011
1
1.0
1.0
1.0
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