COMPAL LA-6501P Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-6501P (DA60000I100)

43190931L01

PIM10

Compal Confidential

2 2

Kenting Schematics Document

Intel Pine Trail-M ( Pineview-M + Tiger point )

2010-03-18

REV: 0.2

3 3

@ : Nopop Component

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-6501P

LA-6501P

LA-6501P

01 35Tuesday, April 27, 2010

01 35Tuesday, April 27, 2010

01 35Tuesday, April 27, 2010

E

0.2

0.2

0.2

A

B

C

D

E

Compal Confidential

Model Name : PIM10
Project Code : ANRPIM1000

1 1

Project Name : Kenting

LCD Conn.

CRT Conn

page 9

page 23

LVDS

RGB

Atom Processor N455

22x22mm

page 4,5,6

DMI X2 mode

Memory BUS(DDRIII)

1.5V/800MHz

DDRIII-DIMM X1

page 7

Thermal Sensor

W83L771AWG

page 5

Clock Generator
CK505

page 8

2 2

USB Port X1

page 23

Port 2

USB

NM10 Express chipset

LS-6501P

PCI-Express

17x17mm

Daughter board

page 10,11,12,13

USB

SATA

HDA

2.5" HDD

page 18

Port 7

Port 0

Card Reader
RTS5160
SD/MMC/MS

page 20

USB Port X1

(R)

page 23

Through LVDS cable

LPC BUS

MINI Card

3 3

Power ON/OFF

page 22 page 24

DC IN

page 26

BATT CONN/OTP

page 32

4 4

CHARGER

page 27

1.2VS

page 29

A

WLAN

page 14

PCIE-Port 2 PCIE-Port 1

USB Port 6

DC/DC Interface

3VALW/5VALW

page 28

1.8VS/0.9VS/

0.89VS

page 30

1.5V/VCCP

page 29

CPU CORE

page 31

10/100 Ethernet

RTL8105EL

page 19

RJ45

page 19

B

Int.KBD

page 21

ENE KBC
KB926

Touch Pad

page 22

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPI

page 21

SPI ROM

C

Audio Codec

ALC272-GR

page 16

Through power buttom cable

PWR buttom board

page 22

Compal Secret Data

Compal Secret Data

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

AMP & Speaker

page 17

Head Phone

page 17

LS-5732P

Port 3

CMOS CAM

page 9

Through LED cable

LED/B

LS-5733P

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

LA-6501P

LA-6501P

LA-6501P

02 35Monday, May 10, 2010

02 35Monday, May 10, 2010

02 35Monday, May 10, 2010

E

0.2

0.2

0.2

A

ZZZ

ZZZ

PCB

PCB

DA60000I100

DA60000I100

1 1

2 2

Voltage Rails

DescriptionPower Plane

VIN

B+

+CPU_CORE

+VCCP

+1.5VS

+1.5V

+0.89VS

+3VALW

+3VS

+5VALW

+5VS

+VS VS always on power rail ON ON*

+RTCBATT

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.75VS

VCCP switched power rail

1.5V switched power rail

1.5V power rail for DDR

CORE VOLTAGE FOR CPU VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

SIGNAL

SLP_S3#

SLP_S4#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

SLP_S5#

HIGHHIGHHIGH

HIGH

HIGH

LOW

B

+VALW

ON

ON

ON

ON

ON

S5

S3S1

N/A N/A N/A

ON

ON

ON

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFFON

OFF

OFFON

OFFOFFON

OFFOFFON

ON

OFF

OFF OFF+1.8VS 1.8V switched power rail

OFF

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFFON

ONON

+V +VS Clock

ON

ON

ON

OFF

ON

OFF

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

C

External PCI Devices

No PCI Device

EC SM Bus1 address

Device

Smart Battery

EEPROM(24C16/02)

D

IDSEL #DEVICE REQ/GNT #

EC SM Bus2 address

Address

1010 000X b

Device

W83L771AWG

EMC1402

E

PIRQ

Address

1001_100X b0001 011X b

100_1100X b

3 3

4 4

BOARD ID Table(Page 21)

VCC 3.3V +/-5%

ID

BRD ID

R01 (SSI)

0

R02 (PT)

1

*

2

R03 (ST)

R10 (X build)

3

4

Reserved

5

Reserved

6

Reserved

7 MP

A

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

NC

Tiger Point SM Bus address

Ra

Rb Vab (Min)

0

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

200K +/- 5%

NC

0.168V

0.375V

0.634V

0.958V

1.372V

1.851V

2.433V

B

0V

Vab (Type) Vab (Max)

0V

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.300V

0.155V

0.362V

0.621V

0.945V

1.359V

1.838V

2.420V

3.300V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

Compal Secret Data

Compal Secret Data

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

C

Compal Secret Data

Address

1101 001Xb

1010 000Xb

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-6501P

LA-6501P

LA-6501P

03 35Tuesday, April 27, 2010

03 35Tuesday, April 27, 2010

03 35Tuesday, April 27, 2010

E

0.2

0.2

0.2

5

PINEVIEW_M

U31A

U31A

DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R

D D

C C

CLK_CPU_EXP#<8>
CLK_CPU_EXP<8>

C906

C906

DMI_RX0<12>

DMI_RX#0<12>

DMI_RX1<12>

DMI_RX#1<12>

C907

C907

C908

C908

C909

C909

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

F3
F2
H4
G3

N7
N6

R10

R9

N10

N9

K2

J1

M4

L3

DMI_RX0_R

DMI_RX#0_R

DMI_RX1_R

DMI_RX#1_R

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

EXP_CLKINN
EXP_CLKINP

EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

DMI

DMI

Close to CPU

+1.5V

R93

12

XDP_TDI
XDP_TMS

@

@

D5

D5

PSOT24C_SOT23-3

PSOT24C_SOT23-3

1U_0603_10V4Z

1U_0603_10V4Z

3

R93

10K_0402_5%

10K_0402_5%

1 2

1

C78

C78

2

Direction

2

1

DRAM_PWROK

0_0402_5%

0_0402_5%

12

@

@

R136

R136

PM_1.5V_PWRGD

I

I

I

I

I

@

@

D7

D7

PSOT24C_SOT23-3

PSOT24C_SOT23-3

3

+5VALW

R142

R142
1K_0402_1%

1K_0402_1%

0.1U_0603_25V7K

0.1U_0603_25V7K

1

C178

C178

2

R158 1K_0402_1%@R158 1K_0402_1%@

PM_SLP_S4#<12,20>

SYSON<20,23,28>

B B

1 2

R163 1K_0402_1%R163 1K_0402_1%

1 2

2

B

B

Q83

Q83
MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

12

C

C

C

C

E

E

3 1

R294

R294
0_0603_5%

0_0603_5%

Q84

Q84
MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

2

B

B

E

E

3 1

Differential Clock Signal Table

Signal Name Description

BCLKP[0]
BCLKN[0]

HPL_CLKINP
HPL_CLKINN

EXP_CLKINP
EXP_CLKINN

REFCLKINP
REFCLKINN

REFSSCLKINP
REFSSCLKINN

A A

Differential Core Clock In

Differential Host Clock In

Differential DMI Clock In

Differential PLL Clock In

Differential Spread Spectrum Clock In

XDP_TDO

XDP_PREQ#

XDP_TRST#

XDP_TCK

5

2

3

@

@

D8

D8

PSOT24C_SOT23-3

PSOT24C_SOT23-3

1

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

EXP_RCOMPO

EXP_ICOMPI

EXP_RBIAS

1 OF 6

1 OF 6

12

0_0402_5%

0_0402_5%

@ R1188

@

Close to U31.AB4

R1188

Type

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

Diff Clk CMOS

2

1

4

G2
G1
H3
J2

L10
L9
L8

N11

RSVD_TP

P11

RSVD_TP

K3

RSVD

L2

RSVD

M2

RSVD

N2

RSVD

PM_1.5V_PWRGD <28>

4

+VCCP

R1172 49.9_0402_1%R1172 49.9_0402_1%
R1171 750_0402_1%R1171 750_0402_1%

T1T1
T2T2

H_PWRGD<5,12>

CPU_ITP<8>
CPU_ITP#<8>

DMI_TX0 <12>
DMI_TX#0 <12>
DMI_TX1 <12>
DMI_TX#1 <12>

XDP_PREQ#<5>
XDP_PRDY#<5>

XDP_BPM#3<5>
XDP_BPM#2<5>

XDP_BPM#1<5>
XDP_BPM#0<5>

R1173 1K _0402_1%@R1173 1K_0402_1%@

1 2

XDP_TDO<5>
XDP_TRST#<5>

XDP_TDI

XDP_TMS

XDP_TDO

XDP_PREQ#

XDP_TRST#

XDP_TCK

R1174 1 K_0402_1%@R1174 1K_0402_1%@

CPU_ITP
CPU_ITP#

PLTRST#

XDP_TDI<5>
XDP_TMS<5>

XDP_TCK<5>

1 2

0_0402_5%

0_0402_5%

R288

R288

R1182 51_0402_5%~DR1182 51_0402_5%~D

R1183 51_0402_5%~DR1183 51_0402_5%~D

R1184 51_0402_5%~DR1184 51_0402_5%~D

R1185 51_0402_5%~DR1185 51_0402_5%~D

R1186 51_0402_5%~DR1186 51_0402_5%~D

R1187 51_0402_5%~DR1187 51_0402_5%~D

SLPIOVR#<12>

PLTRST#<5,12,14,18,20>

XDP Reserve

DRAMRST#_R DRAMRST#

XDP_PREQ#
XDP_PRDY#

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

1 2

R1175

R1175

1 2

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

1 2

1 2

1 2

1 2

1 2

1 2

3

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DM[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..14]<7>

+1.5V

R1179

R1179
R1181

R1181

1

C256

C256

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

2

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS#0
DDR_CS#1

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_A_RAS#<7>

DDR_A_BS0<7>
DDR_A_BS1<7>
DDR_A_BS2<7>

DDR_CS#0<7>
DDR_CS#1<7>

CONN@

CONN@

JP80

JP80

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

1K_0402_1%@

1K_0402_1%@

T44T44

15
16
17
18
19
20
21
22
23
24
25
26

ACES_87151-24051

ACES_87151-24051

+VCCP

14
15
16
17
18
19
20
21
22
23
24
G1
G2

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

R1177

R1177

R1180

R1180

+1.5V

DDR_CKE0<7>
DDR_CKE1<7>

M_ODT0<7>
M_ODT1<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>
M_CLK_DDR1<7>
M_CLK_DDR#1<7>

12

12

.1U_0402_16V7K~D

.1U_0402_16V7K~D

C1102

C1102

1

2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_MA14

DRAM_PWROK
DRAMRST#_R

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

2

AH19

DDR_A_MA_0

AJ18

DDR_A_MA_1

AK18

DDR_A_MA_2

AK16

DDR_A_MA_3

AJ14

DDR_A_MA_4

AH14

DDR_A_MA_5

AK14

DDR_A_MA_6

AJ12

DDR_A_MA_7

AH13

DDR_A_MA_8

AK12

DDR_A_MA_9

AK20

DDR_A_MA_10

AH12

DDR_A_MA_11

AJ11

DDR_A_MA_12

AJ24

DDR_A_MA_13

AJ10

DDR_A_MA_14

AK22

DDR_A_WE#

AJ22

DDR_A_CAS#

AK21

DDR_A_RAS#

AJ20

DDR_A_BS_0

AH20

DDR_A_BS_1

AK11

DDR_A_BS_2

AH22

DDR_A_CS#_0

AK25

DDR_A_CS#_1

AJ21

DDR_A_CS#_2

AJ25

DDR_A_CS#_3

AH10

DDR_A_CKE_0

AH9

DDR_A_CKE_1

AK10

DDR_A_CKE_2

AJ8

DDR_A_CKE_3

AK24

DDR_A_ODT_0

AH26

DDR_A_ODT_1

AH24

DDR_A_ODT_2

AK27

DDR_A_ODT_3

AG15

DDR_A_CK_0

AF15

DDR_A_CK_0#

AD13

DDR_A_CK_1

AC13

DDR_A_CK_1#

AC15

DDR_A_CK_3

AD15

DDR_A_CK_3#

AF13

DDR_A_CK_4

AG13

DDR_A_CK_4#

AD17

RSVD

AC17

RSVD

AB15

RSVD

AB17

RSVD

AB4

RSVD

AK8

RSVD

AB11

T6T6
T7T7

AB13

AL28

AK28

AJ26

AK29

RSVD_TP
RSVD_TP

DDR_VREF
DDR_RPD
DDR_RPU

RSVD

NOTE

Place 0.1uF CAP close to CPU.

+1.5V

R88

@R88

@

10K_0402_5%

10K_0402_5%

1 2

DRAMRST# <7>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

U31B

U31B

DDR_A

DDR_A

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1

DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A_DM_6

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

2 OF 6

2 OF 6

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Pineview(1/3)-DMI,DDR

Pineview(1/3)-DMI,DDR

Pineview(1/3)-DMI,DDR

LA-6501P

LA-6501P

LA-6501P

1

AD3
AD2
AD4

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AB8
AD7
AA9

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AD8
AD10
AE8

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

AK5
AK3
AJ3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AG22
AG21
AD19

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

AE26
AG27
AJ27

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

AE30
AF29
AF30

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

AB27
AA27
AB26

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

04 35Monday, May 10, 2010

04 35Monday, May 10, 2010

04 35Monday, May 10, 2010

0.2

0.2

0.2

5

PINEVIEW_M

U31C

U31C

D12

T18T18
T8T8
T9T9
T10T10
T19T19
T20T20
T11T11

D D

C C

B B

T21T21
T12T12

T22T22
T16T16
T13T13
T23T23
T17T17
T14T14
T15T15
T24T24

R1198

R1198
1K_0402_1%

1K_0402_1%

T25T25

T26T26
T27T27
T28T28
T29T29

T30T30
T31T31
T32T32
T33T33

C10
D10
B11
B10
B12
C11

AA7
AA6

AA21

W21

V21

A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8

L11

R5
R6

T21

XDP_RSV D_00
XDP_RSV D_01
XDP_RSV D_02
XDP_RSV D_03
XDP_RSV D_04
XDP_RSV D_05
XDP_RSV D_06
XDP_RSV D_07
XDP_RSV D_08
XDP_RSV D_09
XDP_RSV D_10
XDP_RSV D_11
XDP_RSV D_12
XDP_RSV D_13
XDP_RSV D_14
XDP_RSV D_15
XDP_RSV D_16
XDP_RSV D_17

RSVD

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

VGA

VGA

PM_EXTT S#_1/DPRSLPVR

MISC

MISC

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GRE EN

CRT_BLU E

CRT_IRTN

CRT_DDC _DATA

CRT_DDC _CLK

DAC_IREF

REFCLKINP

REFCLKINN
REFSSCL KINP
REFSSCL KINN

PM_EXTT S#_0

PWRO K

RSTIN#

HPL_CLK INN
HPL_CLK INP

3 OF 6

3 OF 6

M30
M29

N31
P30
P29
N30

L31
L30

P28

Y30
Y29
AA30
AA31

K29
J30
L5
AA3

W8
W9

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

PM_EXTTS#1
PM_EXTTS#0
H_PWROK
PLTRST#

CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK

Close to Processor

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

+3VS

1

C914

C914

2

H_THERMDA

0.1U_0402_16V4Z~D

A A

C915

C915

1 2

0.1U_0402_16V4Z~D

H_THERMDC

2200P_0402_50V7K

2200P_0402_50V7K

5

CPU THERMAL SENSOR

U33

U33

1

VDD

2

D+

3

D-

4

T_CRIT_A#

W83L771AWG_TSSOP8

W83L771AWG_TSSOP8

Address:1001_100

SDA

ALERT#

GND

SCL

pin

8

7

6

5

0_0402_5%

0_0402_5%

H_PWROK

PM_EXTTS#0

EC_SMB_CK2

EC_SMB_DA2

10K_0402_5%

10K_0402_5%

4

GMCH_CRT_HSYNC <22>
GMCH_CRT_VSYNC <22>

GMCH_CRT_R <22>
GMCH_CRT_G <22>
GMCH_CRT_B <22>

GMCH_CRT_DATA <22>
GMCH_CRT_CLK <22>

R1189 665_0402_1%R1189 665_0402_1%

CPU_DREFCLK <8>
CPU_DREFCLK# <8>
CPU_SSCDREFCLK <8>
CPU_SSCDREFCLK# <8>

R1252

R1252

PM_EXTTS#0 <7>

PLTRST# <4,12,14,18,20>

CLK_CPU_HPLCLK# <8>
CLK_CPU_HPLCLK <8>

1 2

1 2

+3VS

12

R1195

R1195
10K_0402_5%

10K_0402_5%

EC_SMB_CK2 <20>

4

EC_SMB_DA2 <20>

12

+3VS

R1206

R1206

PM_DPRSLPVR <12>

R1193

@R1193

@

0_0402_5%

0_0402_5%

R1194

R1194

0_0402_5%

0_0402_5%

H_PROCHOT#

Close to Processor
pin

3

VGATE <8,12,20,30>

PCH_POK <12,20>

+VCCP

R1196

R1196
68_0402_5%

68_0402_5%

Place closed to chipset

GMCH_CRT_R

GMCH_CRT_G

GMCH_CRT_B

GMCH_ENBKL

1 2

1 2

1 2

100K_0402_5%

100K_0402_5%

LVDSAC-<9>

LVDSAC+<9>
LVDSA0-<9>
LVDSA0+<9>
LVDSA1-<9>
LVDSA1+<9>
LVDSA2-<9>
LVDSA2+<9>

GMCH_ENBKL<20>

EDID_CLK_LCD<9>

EDID_DAT_LCD<9>

GMCH_LVDDEN<9>

XDP_BPM#0<4>
XDP_BPM#1<4>
XDP_BPM#2<4>
XDP_BPM#3<4>

R1203

R1203

150_0402_1%

150_0402_1%
R1200

R1200
150_0402_1%

150_0402_1%
R1204

R1204
150_0402_1%

150_0402_1%
R1205

R1205

U31D

U31D

U25

LA_CLKN

U26

LA_CLKP

R23

LA_DATA N_0

R24

LA_DATA P_0

N26

LA_DATA N_1

N27

LA_DATA P_1

R26

LA_DATA N_2

R27

1

2

LA_DATA P_2

R22

LIBG

J28

LVBG

N22

LVREFH

N23

LVREFL

L27

LBKLT_E N

L26

LBKLT_C TL

L23

LCTLA_C LK

K25

LCTLB_D ATA

K23

LDDC_CL K

K24

LDDC_DA TA

H26

LVDD_EN

G11

BPM_1_0 #

E15

BPM_1_1 #

G13

BPM_1_2 #

F13

BPM_1_3 #

B18

BPM_2_0 #/RSVD

B20

BPM_2_1 #/RSVD

C20

BPM_2_2 #/RSVD

B21

BPM_2_3 #/RSVD

G5

RSVD

D14

TDI

D13

TDO

B14

TCK

C14

TMS

C16

TRST#

D30

THRMDA_ 1

E30

THRMDC_ 1

C30

THRMDA_ 2/RSVD

D31

THRMDC_ 2/RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

R1190

R1190

2.37K_0402_1%

2.37K_0402_1%

GMCH_ENBKL

R1192

R1192
100K_0402_5%

100K_0402_5%

T34T34
T35T35
T36T36
T37T37

T38T38

H_THERMDA
H_THERMDC

H_GTLREF

XDP_TDI
XDP_TDO
XDP_TCK

XDP_TMS
XDP_TRST#

C939

@ C939

@

1U_0603_10V4Z

1U_0603_10V4Z

XDP_TDI<4>
XDP_TDO<4>
XDP_TCK<4>
XDP_TMS<4>
XDP_TRST#<4>

R1197

R1197
1K_0402_1%

1K_0402_1%

R1201

R1201
2K_0402_1%

2K_0402_1%

2

PINEVIEW_M

PINEVIEW_M

LVDS

LVDS

4 OF 6

4 OF 6

REV = 1.1

REV = 1.1

CPU

CPU

placed within 0.5"
of processor pin.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1

H_SMI#

E7

SMI#
A20M#
FERR#

LINT0
LINT1

IGNNE#

ICH

ICH

STPCLK#

DPRSTP#

DPSLP#

INIT#
PRDY#
PREQ#

THERMTR IP#

PROCHOT #

CPUPW RGOOD

GTLREF

VSS

RSVD
RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

EXTBGRE F

H7
H6
F10
F11
E5
F8

G6
G10
G8
E11
F15

E13

C18
W1

A13
H27

L6
E17

H10
J10

K5
H5
K6

H30
H29
H28
G30
G29
F29
E29

L7
D20
H13
D18

K9
D19
K7

H_EXTBGREF

H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#

H_DPRSTP#
H_DPSLP#
H_INIT#
XDP_PRDY#
XDP_PREQ#

H_THERMTRIP#

H_PROCHOT#
H_PWRGD

H_GTLREF

CLK_CPU_BCLK#
CLK_CPU_BCLK

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

T39T39
T40T40

H_EXTBGREF

H_PWRGD <4,12>

CPU_BSEL0 <8>
CPU_BSEL1 <8>
CPU_BSEL2 <8>

CPU_VID0 <30>
CPU_VID1 <30>
CPU_VID2 <30>
CPU_VID3 <30>
CPU_VID4 <30>
CPU_VID5 <30>
CPU_VID6 <30>

C940

C940

@

@

1U_0603_10V4Z

1U_0603_10V4Z

H_SMI# <11>
H_A20M# <11>
H_FERR# <11>
H_INTR <11>
H_NMI <11>
H_IGNNE# <11>

H_STPCLK# <11>

H_DPRSTP# <12>
H_DPSLP# <12>

H_INIT# <11>
XDP_PRDY# <4>
XDP_PREQ# <4>

H_THERMTRIP# <11>

CLK_CPU_BCLK# <8>
CLK_CPU_BCLK <8>

+VCCP+VCCP

R1199

R1199
976_0402_1%

976_0402_1%

1

R1202

R1202

3.3K_0402_1%

3.3K_0402_1%

2

placed within 0.5"
of processor pin.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Pineview(2/3)-HOST,CRT,LVDS

Pineview(2/3)-HOST,CRT,LVDS

Pineview(2/3)-HOST,CRT,LVDS

LA-6501P

LA-6501P

LA-6501P

05 35Monday, May 10, 2010

05 35Monday, May 10, 2010

05 35Monday, May 10, 2010

1

0.2

0.2

0.2

5

U31E

1

2

T13
T14
T16
T18
T19
V13

V19
W14
W16
W18
W19

AK13
AK19

AK9

AL11
AL16
AL21
AL25

AK7

AL7

U10

W10
W11

AA10
AA11

AA19

V11

AC31

T30

T31

J31

A21

1

C952

C952

2

1U_0402_6.3V6K

1U_0402_6.3V6K

U31E

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

VCCA_DDR

U5

VCCA_DDR

U6

VCCA_DDR

U7

VCCA_DDR

U8

VCCA_DDR

U9

VCCA_DDR

V2

VCCA_DDR

V3

VCCA_DDR

V4

VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

VCCACRTDAC

VCC_GIO
VCCRING_EAST

C3

VCCRING_WEST

B2

VCCRING_WEST

C2

VCCRING_WEST
VCC_LGI

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

C954

C954

2

1U_0402_6.3V6K

1U_0402_6.3V6K

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

GFX/MCH

GFX/MCH

DDR

DDR

POWER

POWER

EXP\CRT\PLL

EXP\CRT\PLL

5 OF 6

5 OF 6

1

1

+

+

C995

C995

C927

C927

330U 2.5V Y

330U 2.5V Y

2

2

0.1U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V6K

GFX supply curr ent: 1.38A
Sustained GFX s upply current: 1.05A

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C930

C930

C929

C929

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCP

1

C409

C409

@

@

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

C942

C942

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C949

C949

C948

C948

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+0.89VS

1

C931

C931

2

1

C401

C401

@

@

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+VCC_CRT_DAC

1

1

C950

C950

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C951

C951

D D

+1.5V

22U_0805_6.3V6M

22U_0805_6.3V6M

C C

+1.5V

1

C933

C933

2

22U_0805_6.3V6M

22U_0805_6.3V6M

Display PLL SFR and CRT DAC supply
current: 0.154A

B B

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL
supply current: 0.33A

A A

DDR supply current: 2.27A

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1

C379

C379

2

Close to U31.AA19

+1.8VS

R1212

R1212

+VCCP

1

1

C273

C273

C928

C928

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR analog supply current: 1.32A

1U_0402_6.3V6K

1U_0402_6.3V6K

0_0603_5%

0_0603_5%

1 2

C941

C941

1U_0603_10V4Z

1U_0603_10V4Z

+3VS

GIO supply current:0.006A

+RING_EAST
+RING_WEST

+0.89VS

2

C946

C946

1

1

C947

C947

2.2U_0603_10V6K

2.2U_0603_10V6K

2

Close Chipset pin

5

CPU

CPU

LVDS

LVDS

DMI

DMI

VCCSFR_DMIHMPLL

1

C1000

C1000

2

10U_0805_10V6K~D

10U_0805_10V6K~D

4

VCCSENSE
VSSSENSE

VCCA

VCCP

VCCP
VCCP

VCCALVDS
VCCDLVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

RSVD

VCCP

4

1U_0402_6.3V6K

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

C29
B29
Y2

D4

B4
B3

V30
W31

T1
T2
T3

P2
AA1

E2

1U_0402_6.3V6K

VCCSENSE
VSSSENSE

Processor Core analog supply current: 0.08A

+VCCP

+VCC_ALVD
+VCC_DLVD

LVDS supply cur rent: 0.06A

+VCC_DMI

DMI analog supply current: 0.48A

+DMI_HMPLL

SFR & DMIHMPLL supply current: 0.104A

VCCSENSE

VSSSENSE

1

C919

C919

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+CPU_CORE

330U 2.5V Y

330U 2.5V Y

VCCSENSE <30>
VSSSENSE <3 0>

1

C391

C391

0.01U_0402_16V7K

0.01U_0402_16V7K

2

T41T41

+VCCP

R1218

R1218

1 2

100_0402_1%

100_0402_1%

R1219

R1219

1 2

100_0402_1%

100_0402_1%

1

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C920

C920

C916

C916

2

1U_0402_6.3V6K

1U_0402_6.3V6K

PLACE IN CAVITY

2 x 330uF(9mohm/2)

+

+

C921

C921

+1.5VS

+CPU_CORE

3

22U_0805_6.3V6M

22U_0805_6.3V6M

@

@

1

1

1

C922

C922

C917

C917

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

+

+

C918

C918

330U 2.5V Y

330U 2.5V Y

330U 2.5V Y

330U 2.5V Y

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C269

C269

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

@

@

+

+

C923

C923

2

+CPU_CORE

1

C271

C271

C272

C272

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

1

C924

C924

1

@

@

C925

C925

2

22U_0805_6.3V6M

22U_0805_6.3V6M

Close to U71.E2

Close to U71.D4

R1207

R1207

1 2

0_0603_5%

0_0603_5%

R1208

R1208

1 2

0_0603_5%

0_0603_5%

1U_0603_10V4Z

1U_0603_10V4Z

R1210

R1210

1 2

0_0805_5%

0_0805_5%

C937

C937

1U_0603_10V4Z

1U_0603_10V4Z

+1.8VS

R1213

R1213

1 2

MBK2012601_YZF

MBK2012601_YZF

R1215

R1215

1 2

0_0603_5%

0_0603_5%

R1216

R1216

1 2

0.1UH_MLF1608DR10KT_10%~D

0.1UH_MLF1608DR10KT_10%~D

R1217

R1217

1 2

0_0805_5%

0_0805_5%

Compal Secret Data

Compal Secret Data

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Close to U31.U10

1

C934

C934

2

1

1U_0603_10V4Z

1U_0603_10V4Z

2

Close to Pin T1

+VCC_CRT_DAC

C943

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C944

C944
1U_0603_10V4Z

1U_0603_10V4Z

2

1

C56

C56
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C953

C953
1U_0603_10V4Z

1U_0603_10V4Z

2

Deciphered Date

Deciphered Date

Deciphered Date

2

1

2

C943

+DMI_HMPLL

+VCC_ALVD

+VCC_DLVD

C926

C926

1U_0603_10V4Z

1U_0603_10V4Z

+RING_EAST

1

C932

C932
1U_0603_10V4Z

1U_0603_10V4Z

2

+RING_WEST

1

C935

C935
1U_0603_10V4Z

1U_0603_10V4Z

2

C938

C938

2

1

2

+VCC_DMI

2

1

PINEVIEW_M

PINEVIEW_M

U31F

U31F

REV = 1.1

REV = 1.1

A11

VSS

A16

VSS

A19

VSS

A29

RSVD_NCTF

A3

RSVD_NCTF

A30

RSVD_NCTF

A4

RSVD_NCTF

AA13

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA2

VSS

AA22

VSS

AA25

VSS

AA26

VSS

AA29

VSS

AA8

VSS

AB19

VSS

AB21

VSS

AB28

VSS

AB29

VSS

AB30

VSS

AC10

VSS

AC11

VSS

AC19

VSS

AC2

VSS

AC21
AC28
AC30
AD26

AD5

AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10

AG3
AH18
AH23
AH28

AH4

AH6

AH8

AJ1
AJ16
AJ31

AK1

AK2
AK23
AK30
AK31
AL13
AL19

AL2
AL23
AL29

AL3
AL30

AL9

B13

B16

B19

B22

B30

B31

B5
B9

C1
C12
C21
C22
C25
C31
D22

E1
E10
E19
E21
E25

E8
F17
F19

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

GND

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 6

6 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Pineview(3/3)-POWER,GND

Pineview(3/3)-POWER,GND

Pineview(3/3)-POWER,GND

LA-6501P

LA-6501P

LA-6501P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

T29

06 35Monday, May 10, 2010

06 35Monday, May 10, 2010

1

06 35Monday, May 10, 2010

0.2

0.2

0.2

5

4

3

2

1

Layout Note:

R284 0_0402_5%

R284 0_0402_5%

0.1U_0603_25V7K

0.1U_0603_25V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1134

C1134

1

2

Place near JDIMM1

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1124

C1124

C421

C421

1

1

2

2

DDR_CKE0<4>

DDR_A_BS2<4>

M_CLK_DDR0<4>
M_CLK_DDR#0<4>

DDR_A_BS0<4>

DDR_A_WE#<4>
DDR_A_CAS#<4>

DDR_CS#1<4>

+3VS

20mils

DDR_VREF_DQ

DDR_A_D0
DDR_A_D1

DDR_A_DM0

C1125

C1125

1

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS#1

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R347 10K_0402_5%R347 10K_0402_5%

1 2

1

1

C1131

C1131

C1130

C1130

2

2

.1U_0402_16V7K~D

.1U_0402_16V7K~D

+DIMM_VREF_DQ

DDR_A_DQS#[0..7]<4>

DDR_A_D[0..63]<4>

DDR_A_DM[0..7]<4>

D D

C C

B B

A A

DDR_A_DQS[0..7]<4>

DDR_A_MA[0..14]<4>

Layout Note:
Place near JDIMM1.1

+1.5V

12

R336

R336

1K_0402_1%

1K_0402_1%

12

R337

R337

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDIMM1

330U 2.5V Y

330U 2.5V Y

1

+

+

C969

C969

2

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

+0.75VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+DIMM_VREF_DQ

1

C1135

C1135

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+1.5V

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

C388

C388

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1122

C1122

1

1

2

2

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

1

C389

C389

C386

C386

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1120

C1120

C1121

C1121

C1119

C1119

1

1

2

2

Layout Note:
Place near JDIMM1.126

+1.5V

12

R339

R339

1K_0402_1%

1K_0402_1%

12

R338

R338

1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

C384

C384

2

1

1

C390

C390

C382

C382

2

2

+DIMM_VREF_CA

1

C1136

C1136

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

2

R287 0_0402_5%

R287 0_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1113

C1113

C1112

C1112

1

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1114

C1114

C1115

C1115

1

1

2

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1116

C1116

1

2

+1.5V +1.5V

CONN@

CONN@

JDIMM1

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

12

R349

R349

10K_0402_5%

10K_0402_5%

.1U_0402_16V7K~D

.1U_0402_16V7K~D

VTT1

205

G1

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F

G2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1

74
76
78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS#0

114

M_ODT0

116
118

M_ODT1

120
122
124

DDR_VREF_CA

126
128

DDR_A_D36

130

DDR_A_D37

132
134

DDR_A_DM4

136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

PM_EXTTS#0

198

CLK_SMBDATA

200

CLK_SMBCLK

202
204

206

+0.75VS

DRAMRST# <4>

DDR_CKE1 <4>

M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>

DDR_A_BS1 <4>
DDR_A_RAS# <4>

DDR_CS#0 <4>
M_ODT0 <4>

M_ODT1 <4>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

C1117

C1117

1

1

2

2

PM_EXTTS#0 <5>
CLK_SMBDATA <8>
CLK_SMBCLK <8>

Layout Note:
Place near JDIMM1

20mils

R286

R286

1 2

0_0402_5%

0_0402_5%

0.1U_0603_25V7K

0.1U_0603_25V7K

C422

C422

C1118

C1118

1

2

+DIMM_VREF_CA

DIMM_A(REV)
4H

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM A

DDRIII-SODIMM A

DDRIII-SODIMM A

LA-6501P

LA-6501P

LA-6501P

07 35Friday, May 07, 2010

07 35Friday, May 07, 2010

07 35Friday, May 07, 2010

1

0.2

0.2

0.2

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

+3VS

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

*

+VCCP

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

+VCCP

R138

R138

2.2K_04 02_5%

2.2K_04 02_5%

FSA

C C

B B

A A

CPU_BSEL 0<5>

R86

R86
1K_0402 _1%

1K_0402 _1%

FSB

CPU_BSEL 1<5>

10K_040 2_5%

10K_040 2_5%

FSC

CPU_BSEL 2<5>

C169 22P_04 02_50V8JC169 2 2P_0402_ 50V8J

14.318MH Z_16PF_7A1 4300083~D

14.318MH Z_16PF_7A1 4300083~D

C162 22P_04 02_50V8JC162 2 2P_0402_ 50V8J

1 2

12

1 2

R147

R147
0_0402_ 5%

0_0402_ 5%

12

+VCCP

1 2

12

1 2

R91

R91
0_0402_ 5%

0_0402_ 5%

12

+VCCP

R100

R100

1 2

12

1 2

R95

R95
0_0402_ 5%

0_0402_ 5%

12

For PCI2_TME:0= Overclocking of CPU and SRC al lowed
(ICS only) 1= Overclocking of CPU and SRC NO T allowed

12

Y6

Y6

Routing the trace at least 10mil

5

Reserved

R435

R435

10K_040 2_5%

10K_040 2_5%

R129

R129

10K_040 2_5%

10K_040 2_5%

R132

@R1 32

@

10K_040 2_5%

10K_040 2_5%

2

CLK_PCI_ LPC<20>

CLK_PCI_ ICH<10>

+3VS+3VS +3VS

R119

@R1 19

@

10K_040 2_5%

10K_040 2_5%

1 2

R117

R117

10K_040 2_5%

10K_040 2_5%

1 2

R140

R140

470_040 2_5%~D

470_040 2_5%~D

R141

@R1 41

@

1K_0402 _1%

1K_0402 _1%

R81

R81

470_040 2_5%~D

470_040 2_5%~D

R82

@R8 2

@

0_0402_ 5%

0_0402_ 5%

R97

@R9 7

@

470_040 2_5%~D

470_040 2_5%~D

R98

@R9 8

@

0_0402_ 5%

0_0402_ 5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : D OT96 / DOT96#
Pin28/29 : L CDCLK / LCDCLK#

CLK_XTAL_ IN

CLK_XTAL_ OUT

CLK_ENAB LE#<30>

Schematic Note:
33 ohm series-resistor need add for singal end clock.

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

1 2

ITP_EN PC I4_SEL PCI2_TME

1 2

+3VS

1 2
13

Q32

Q32

DTC124EK_ SC59

DTC124EK_ SC59

CLK_ICH_4 8M<1 2>

CLK_ICH_1 4M<12 >

CLK_EN

VGATE<5,12,20 ,30>

H_STP_CPU#<12>

H_STP_PCI#<12>

R109

R109

10K_040 2_5%

10K_040 2_5%

1 2

@R1 10

@

10K_040 2_5%

10K_040 2_5%

1 2

4

1 2

R78 0_0805_ 5%R78 0_0 805_5%

1 2

R131 0_0805 _5%R131 0_0 805_5%

CLK_EN

+1.05VM_C K505

+1.5VS

C392 10P_0402 _50V8J~DC392 10P_0402 _50V8J~D

1

1

C1012

C1012

@

@

2

2

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

R110

4

3

+3VM_CK50 5

C151

C151

10U_0805_10V6K~D

10U_0805_10V6K~D

1

C181

C181

2

+1.05VM_C K505

1

C163

C163

10U_080 5_10V6K~D

10U_080 5_10V6K~D

2

Co-Layout circuit

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

C175

C175

1

C198

C198

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

0.1U_0402_16V4Z~D

1

1

C197

C197

2

2

1

C936

C936

2

1

C152

C152

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

47P_0402_50V8J

47P_0402_50V8J

R94 0_0805_ 5%@ R94 0_0805_ 5%@

1 2

1

C153

C153

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

SA00003H720 (Realtek : RTM890N-397-VB-GRT)
SA000020H10 (ICS : ICS9LPRS387AKLFT)

+3VM_CK50 5

FSA

FSB

R13270_0402 _5% @ R13270_04 02_5% @

H_STP_CPU#

H_STP_PCI# _R

CLK_XTAL_ IN

CLK_XTAL_ OUT

33_0402 _5%

33_0402 _5%

FSC

PCI2_TME

PCI4_SEL

ITP_EN

U11

U11

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP5 56VTR_QFN72_ 10X10

SLG8SP5 56VTR_QFN72_ 10X10

3

12

C8325P_0402_ 50V8C C8325P_0402_ 50V8C

1 2

1 2

1 2

R150
0_0402_ 5%

0_0402_ 5%

C1013

C1013

@

@

+1.5VM_CK 505

+1.05VM_C K505

R116 0_040 2_5%@ R116 0_0 402_5%@

1 2

R118 0_040 2_5%R118 0_040 2_5%

1 2

R137

R137

1 2

33_0402 _5%

33_0402 _5%

R101

R101

1 2

33_0402 _5%

33_0402 _5%

@R150

@

R1334 33_04 02_5%R1334 33_0 402_5%

1 2

R1335

R1335

1 2

C199

C199

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C155

C155

2

1

C167

C167

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_10#

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

USB_1/CLKREQ_A#

2

+1.5VM_CK 505

R102 0_080 5_5%R102 0_080 5_5%

C154

C154

1 2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

1

C189

C189

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

C182

C182

2

1

C200

C200

0.1U_040 2_16V4Z~D

0.1U_040 2_16V4Z~D

2

C156

C156

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

2

10U_0805_10V6K~D

10U_0805_10V6K~D

1

2

1

2

+1.5VS

@

@

C945

C945
47P_040 2_50V8J

47P_040 2_50V8J

ICH_SMBDA TA<1 2>

ICH_SMBCL K<12>

Co-Layout circuit

Realtek(L.P.)

CLK_SMBD ATA

9

SDA

CLK_SMBC LK

10

SCL

CLK_CPU_ BCLK

71

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_9

SRC_9#

SRC_10

SRC_11

CLK_CPU_ BCLK#

70

CLK_CPU_ HPLCLK

68

CLK_CPU_ HPLCLK#

67

CPU_DREFCL K

24

CPU_DREFCL K#

25

CPU_SSCDRE FCLK

28

CPU_SSCDRE FCLK#

29

CLK_CPU_ EXP

32

CLK_CPU_ EXP#

33

35

36

CLK_PCIE _SATA

39

CLK_PCIE _SATA#

40

CLK_PCIE _WLAN

57

CLK_PCIE _WLAN#

56

61

60

CPU_ITP

64

CPU_ITP#

63

CLK_PCIE _LAN

44

CLK_PCIE _LAN#

45

CLK_PCIE _ICH

50

CLK_PCIE _ICH#

51

CLK_PCIE _WWAN

48

CLK_PCIE _WWAN#

47

37

41

WLAN_C LKREQ#

58

65

CLKREQ_L AN#

43

49

WWA N_REQ#11

46

21

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

CLK_SMBD ATA <7>

CLK_SMBC LK <7>

CLK_CPU_ BCLK <5>

CLK_CPU_ BCLK# <5>

CLK_CPU_ HPLCLK <5>

CLK_CPU_ HPLCLK# <5 >

CPU_DREFCL K <5>

CPU_DREFCL K# <5>

CPU_SSCDRE FCLK <5>

CPU_SSCDRE FCLK# <5>

CLK_CPU_ EXP <4>

CLK_CPU_ EXP# <4 >

CLK_PCIE _SATA <11>

CLK_PCIE _SATA# <11>

CLK_PCIE _WLAN <14>

CLK_PCIE _WLAN# <14>

CPU_ITP <4>

CPU_ITP# <4>

CLK_PCIE _LAN <18>

CLK_PCIE _LAN# <18>

CLK_PCIE _ICH <12>

CLK_PCIE _ICH# <12 >

CLK_PCIE _WWAN <1 4>

CLK_PCIE _WWAN# <14>

WLAN_C LKREQ# <14>

CLKREQ_L AN# <18>

WWA N_REQ#11 <14>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

ICS(L.P.)

ICS,Silego

2.2K_04 02_5%

2N7002DW -T/R7_SOT363 -6

2N7002DW -T/R7_SOT363 -6

2N7002DW -T/R7_SOT363 -6

2N7002DW -T/R7_SOT363 -6

2.2K_04 02_5%

6 1

+3VS

3

+3VS,+1.5VS

+3VS,+1.5VS

+3VS

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

+3VS

R112

Q10A

Q10A

Q10B

Q10B

R112

2

5

4

R108

R108

2.2K_04 02_5%

2.2K_04 02_5%

CLK_SMBD ATA

CLK_SMBC LK

De-pop R94,R118;pop
R102,C182,C156,C936,R116

De-pop R94,R116;pop
R102,C182,C156,C936,R118

De-pop R102,C182,C156,
C936,R118;pop R94,R116

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

WWA N_REQ#11

WLAN_C LKREQ#

CLKREQ_L AN#

H_STP_CPU#

H_STP_PCI# _R

DEVICE

CPU_VGA
DMI

PCIE_SATA
PCIE_WLAN

CPU_XDP
PCIE_LAN
PCIE_TigerPoint

R139

R139

10K_040 2_5%

10K_040 2_5%

12

R84

R84

10K_040 2_5%

10K_040 2_5%

12

R111

R111

10K_040 2_5%

10K_040 2_5%

12

R121

R121

10K_040 2_5%

10K_040 2_5%

12

R124

R124

10K_040 2_5%

10K_040 2_5%

12

REQ PORT LIST

DEVICEPORT

REQ_3#

REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

PCIE_WLAN

PCIE_LAN

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

LA-6501P

LA-6501P

LA-6501P

1

+3VS

0.2

0.2

08 35Friday, May 07, 20 10

08 35Friday, May 07, 20 10

08 35Friday, May 07, 20 10

0.2

5

4

3

2

1

+LCDVDD

R70

R70

470_0805_5%

GMCH_LVDDEN<5>

470_0805_5%

Q29A

Q29A

R72

R72

100K_0402_5%

100K_0402_5%

D D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

C C

+5VALW

12

61

1 2

2

3

5

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1 2

R63

R63
1M_0402_5%

1M_0402_5%

R73

R73

1 2

100K_0402_5%

100K_0402_5%

Q29B

Q29B

2

C395

C395

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

MIC_DATA<15>

MIC_CLK<15>

BKOFF#<20>

+3VS

W=60mils

Q3

Q3

S

S

G

G

AO3413_SOT23

AO3413_SOT23

2

D

D

W=60mils

1 3

@

@

C396

C396

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

LVDSA0+<5>
LVDSA0-<5>

LVDSA2+<5>
LVDSA2-<5>

L25

L25

FBMA-L10-160808 301LMT_0603

FBMA-L10-160808 301LMT_0603

1 2

BKOFF#

100P_0402_50V8J

100P_0402_50V8J

C229

C229

@

@

+LCDVDD

1

C394

C394

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

R60

R60

4.7K_0402_5%

4.7K_0402_5%

1

2

+3VS

12

@

@

1

C230

C230

2

100P_0402_50V8J

100P_0402_50V8J

LCD POWER CIRCUIT

+LCDVDD +LCDVDD_R +3VS +3VS_LCD +3VS +VMIC

L21

L21

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1 2

4.7U_0805_10V4Z~D

4.7U_0805_10V4Z~D

LCD/PANEL BD. Conn.

+CAM_VDD

+LCDVDD_R

CONN@

CONN@

JP24

JP24

42

GND

40

40

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

20

20

18

18

16

16

14

14

12

12

10

10

8

8

6

6

4

4

2

2

ACES_87242-4001-09

ACES_87242-4001-09

C398

C398

GMD

1

C397

C397

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

INVPWR_B+ +3VS_LCD +VMIC

41
39

39

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

1 2

LCD_TST

+CAM_VDD+3VS

R35

R35

0_0603_5%

0_0603_5%

LVDC+
LVDC-

1
C600

2

1

2

R69

R69

2.2K_0402_5%

2.2K_0402_5%

R1027 0_04 02_5%R1027 0_04 02_5%

1 2

R1026 0_04 02_5%R1026 0_04 02_5%

LCD_TST <20>

C600
100P_0402_50V8J

100P_0402_50V8J

W=20mils

C45

C45

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

+3VS

12

12

12

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

R65

R65

2.2K_0402_5%

2.2K_0402_5%

1

C231

C231

2

100P_0402_50V8J

100P_0402_50V8J

1 2

EDID_CLK_LCD <5>
EDID_DAT_LCD <5>

LVDSA1+ <5>
LVDSA1- <5>

LVDSAC+ <5>
LVDSAC- <5>

INVT_PWM <20>

L22

L22

FBMA-L11-201209-221LMA30T_0805

1

2

USBP3

USBN3

FBMA-L11-201209-221LMA30T_0805

C399

C399

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

R44

R44

1 2

0_0402_5%

0_0402_5%

@

@

WCM2012F2S-900T04_0805

WCM2012F2S-900T04_0805

4

4

1

1

L64

L64

R46

R46

1 2

0_0402_5%

0_0402_5%

3

2

1 2

3

2

L37

L37

1

C647

C647

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

2

USB20_P3 < 12>

USB20_N3 <12>

B B

L18

L18
FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

1

C85

C85

68P_0402_50V8J~D

68P_0402_50V8J~D

40mil

1

C829

@C829

@

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2

A A

5

12

@R1158

@

100K_0402_5%

100K_0402_5%

R1159 100K_0402_5%@R1159 100K_0402_5%@

BKOFF#

R1158

1 2

2

@

@

SI3457BDV-T1-E3_TSOP6~D

SI3457BDV-T1-E3_TSOP6~D

S

S

4 5

G

G

3

PWR_SRC_ON

INVPWR_B+B+

1

C393

C393

0.1U_0603_25V7K

0.1U_0603_25V7K

2

Q80

Q80

D

D

6

2
1

Q81

@

Q81

@

RHU002N06_SOT323-3~D

RHU002N06_SOT323-3~D

D

S

D

S

1 3

G

G

2

4

40mil

1

C830

@C830

@

0.1U_0603_50V4Z~D

0.1U_0603_50V4Z~D

2

LVDSAC+

LVDSAC-

@C232

@

@C233

@

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

C232

C233

1

1

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

LVDS/INVERTER

LVDS/INVERTER

LVDS/INVERTER

LA-6501P

LA-6501P

LA-6501P

09 35Friday, May 07, 2010

09 35Friday, May 07, 2010

09 35Friday, May 07, 2010

1

0.2

0.2

0.2

5

D D

R1232

R1232
33_0402_5%

33_0402_5%

C955

C955
22P_0402_50V8J

22P_0402_50V8J

PCI_RST#<20>

C C

CLK_PCI_ICH

12

@

@

1

@

@

2

B B

For EMI, close to TigerPoint

4

@R1154

@

100K_0402_5%

100K_0402_5%

1 2

R1154

R1322

@R1322

@

1 2

0_0402_5%

0_0402_5%

10K_0402_5%

10K_0402_5%

CLK_PCI_ICH<8>

R1233

R1233

@

@

R1234

R1234
10K_0402_5%

10K_0402_5%

@

@

10K_0402_5%

10K_0402_5%

R1243

R1243

@

@

3

+3VS

8.2K_0402_5%

8.2K_0402_5%

R1220

R1220

R12218.2K_0402_5% R12218.2K_0402_5%

R12228.2K_0402_5% R12228.2K_0402_5%
R12248.2K_0402_5% R12248.2K_0402_5%
R12238.2K_0402_5% R12238.2K_0402_5%
R12258.2K_0402_5% R12258.2K_0402_5%
R12268.2K_0402_5% R12268.2K_0402_5%
R12278.2K_0402_5% R12278.2K_0402_5%

R12288.2K_0402_5% R12288.2K_0402_5%

R12298.2K_0402_5% R12298.2K_0402_5%

R123010K_0402_5% R123010K_0402_5%
R123110K_0402_5% R123110K_0402_5%

R12358.2K_0402_5% R12358.2K_0402_5%
R12368.2K_0402_5% R12368.2K_0402_5%
R12378.2K_0402_5% R12378.2K_0402_5%
R12388.2K_0402_5% R12388.2K_0402_5%
R12398.2K_0402_5% R12398.2K_0402_5%
R12408.2K_0402_5% R12408.2K_0402_5%
R12418.2K_0402_5% R12418.2K_0402_5%
R12428.2K_0402_5% R12428.2K_0402_5%

R12448.2K_0402_5% R12448.2K_0402_5%

2

TGP

U34A

U34A

A5

C22

D10

G16

G14

C15

H10

D11

M13

B15
J12
A23

B7

B11
F14

A8

A10

A16

A18
E16

A20

A2

C9

B2
D7
B3

E8
D6
H8

F8

K9

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

GNT1#
GNT2#

REQ1#
REQ2#

GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

STRAP0#
RSVD01
RSVD02

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

PCI_DEVSEL#

CLK_PCI_ICH

PCI_IRDY#

PCI_SERR#
PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

PCI_REQ1#
PCI_REQ2#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

R12458.2K_0402_5% R12458.2K_0402_5%

TGP

PCI

PCI

AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9

1

1

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

H16
M15
C13
L16

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Tigerpoint(1/4)-PCI

Tigerpoint(1/4)-PCI

Tigerpoint(1/4)-PCI

LA-6501P

LA-6501P

LA-6501P

10 35Friday, May 07, 2010

10 35Friday, May 07, 2010

10 35Friday, May 07, 2010

1

0.2

0.2

0.2

5

D D

U34C

U34C

R12

RSVD03

AE20

RSVD04

AD17

RSVD05

AC15

RSVD06

AD18

RSVD07

Y12

RSVD08

AA10

RSVD09

AA12

RSVD10

Y10

RSVD11

AD15

RSVD12

W10

RSVD13

V12

C C

+3VS

R1250 8.2K_0402_5%R1250 8.2K_0402_5%

B B

AE21
AE18
AD19

U12

AC17
AB13
AC13
AB15

AB16
AE24
AE23

AA14

AD16
AB11
AB10

AD23

Y14

V14

RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD24
RSVD25
RSVD26

RSVD27
RSVD28

RSVD29
RSVD30
RSVD31

GPIO36

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

4

TGP

TGP

AE6

SATA0RXN

AD6

SATA0RXP
SATA0TXN

SATA1RXN
SATA1RXP
SATA1TXN

SATA

SATA

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

HOST

HOST

THRMTRIP#

SATA0TXP

SATA1TXP

SATALED#

A20GATE

A20M#

CPUSLP#

IGNNE#

INIT3_3V#

INIT#
INTR

FERR#

RCIN#

SERIRQ

SMI#

STPCLK#

3

3

NMI

AC7
AD7
AE8
AD8
AD9
AC9

AD4
AC4

AD11
AC11
AD25

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

SATA_ITX_C_DRX_N0_R
SATA_ITX_C_DRX_P0_R

SATARBIAS

SATA_LED#

GATEA20
H_A20M#

H_IGNNE#

H_INIT#
H_INTR
H_FERR#
H_NMI
KB_RST#
SERIRQ
H_SMI#
H_STPCLK#

CLK_PCIE_SATA# <8>
CLK_PCIE_SATA <8>

R1246 24.9_0402_1%R1246 24.9_0402_1%

SATA_LED# <22>

GATEA20 <20>
H_A20M# <5>

H_IGNNE# <5>

H_INIT# <5>
H_INTR <5>
H_FERR# <5>
H_NMI <5>
KB_RST# <20>
SERIRQ <20>
H_SMI# <5>
H_STPCLK# <5>

3

SATA_IRX_DTX_N0 <17>
SATA_IRX_DTX_P0 <17>

0.01U_0402_16V7K

0.01U_0402_16V7K

Close to TigerPoint
pin U16

+VCCP

C9560.01U_0402_16V7K C9560.01U_0402_16V7K
C957

C957

12

R1251

R1251

56_0402_5%

56_0402_5%

SATA_ITX_C_DRX_N0 <17>
SATA_ITX_C_DRX_P0 <17>

+3VS

R1247

SATA_LED#

GATEA20

SERIRQ

56 ohm±5% pull-up resistor has
to be within 1" from the Tiger
Point chipset.

H_THERMTRIP# <5>

R1247

10K_0402_5%

10K_0402_5%

R1248

R1248

10K_0402_5%

10K_0402_5%

R1249

R1249

10K_0402_5%

10K_0402_5%

2

1

ESD request

@

@

C450

C450

H_A20M#

C451

C451

+VCCP

R198

R198
56_0402_5%

56_0402_5%

H_FERR#

Close to TigerPoint
pin Y22

A A

5

4

H_IGNNE#

C452

C452

H_INIT#

C453

C453

H_INTR

C454

C454

H_FERR#

C455

C455

H_NMI

C456

C456

H_SMI#

C457

C457

H_STPCLK#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

@

@

100P_0402_50V8J

100P_0402_50V8J

1 2

Compal Secret Data

Compal Secret Data

2010/03/18 2011/03/18

2010/03/18 2011/03/18

2010/03/18 2011/03/18

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Tigerpoint(2/4)-HOST,SATA

Tigerpoint(2/4)-HOST,SATA

Tigerpoint(2/4)-HOST,SATA

LA-6501P

LA-6501P

LA-6501P

11 35Friday, May 07, 2010

11 35Friday, May 07, 2010

11 35Friday, May 07, 2010

1

0.2

0.2

0.2