Compal LA-6371P PAU00 Tablet 10 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

Tablet 10" M/B Schematics Document

Intel Pineview-M Processor with DDRIII + Tigerpoint

3 3

2010-05-07

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2010/5/7 2011/5/7

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-6371P

E

1 27Friday, May 07, 2010

0.1

A

B

C

D

E

Compal Confidential

Memory BUS(DDRIII)

Model Name : PAU00
File Name : LA-6371P

1 1

Intel

1.5V DDRIII 667

204pin DDRIII-SO-DIMM

page 7

Pineview-M

PCB

ZZZ1

Processor

PCB

LCD Conn.

page 9

LVDS

FCBGA559
22x22mm

page 4,5,6

DMI x2

100MHz

GEN1

2 2

Intel

USB 2.0

3.3V 48MHz

USB port0

USB port1

USB port3

USB port7

USB port4

USB conn x 1

Touch Screen

Camera

Mini Card-1

Mini Card-3
WWAN

Sub-board

page 9

Sub-board

page 14

Tigerpoint

PCI-Express x4 (PCIE1 2.5GT/S)

100MHz

NM10

HD Audio

3.3V 24MHz

port 1

MINI Card -1

WLAN

w/ Bluetooth

3 3

page 14

PCBGA 360pins
17x17mm

page 10,11,12,13

SATA (GEN1 1.5GT/S ,GEN2 3GT/S)

100MHz

Sub-board

Audio CKT
ALC269Q-VB

port 0

SATA SSD
Mini Card-2

Thermal Sensor

EMC1402

Clock Generator

CK505

SIM CONN

DMIC

Audio Jack / Speaker

page 14

page 5

page 8

LPC BUS

33MHz

Power ON/OFF

page 17

DC IN

page 19

DC/DC Interface

3VALW/5VALW

page 16

page 22

ALS

page 15

ENE KB926 E0

page 15

SPI ROM

page 15

0.89VP/1.8VP

BATT IN

4 4

CHARGER

page 20

page 21

A

0.75VSP

page 24

1.5V/VCCP

page 23

CPU_CORE

page 25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

G-Sensor

page 15

2010/5/7 2011/5/7

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA-6371P

E

2 27Friday, May 07, 2010

0.1

A

B

C

D

E

Voltage Rails

DescriptionPower Plane

VIN

B+

1 1

+CPU_CORE

+VCCP

+1.5VS

+1.8V

+0.89V Graphic core power rail

+3VALW

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON

+RTCVCC

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

ONONONONON

ON

ON

ON OFF

ON

ON

ON

ON

ON

S5

S3S1

ON

OFFON

OFF

OFF

OFF

OFFOFFON

OFFOFFON

OFF

ON

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFFON

ON*

ON

ON

External PCI Devices

DEVICE REQ/GNT # PIRQ

IDSEL #

No PCI Device

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

Address

100_11000001 011X b

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

2 2

STATE

Full ON

SIGNAL

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

3 3

SLP_S3#

SLP_S4#

SLP_S5#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

+V +VS Clock

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

ON

ON

ON

OFF

OFF

Tiger Point SM Bus address

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

Address

1101 001Xb

1010 000Xb

USB table

EHCI1

EHCI2

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Port11

Ext USB Conn.
Touch Screen

Camera
WWAN

WLAN

PCIE table

PCIE port1

PCIE port2

PCIE port3

PCIE port4

PCIE port5

PCIE port6

WLAN

SATA table

SATA port0

SATA port1

SATA port2

SATA port3

SATA port4

SATA port5

SSD

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2010/5/7 2011/5/7

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-6371P

E

3 27Friday, May 07, 2010

0.1

5

U71A

+VCCP

DMI_RX0_C
DMI_RX#0_C
DMI_RX1_C
DMI_RX#1_C

H4
G3

N7
N6

R10

R9

N10

N9

M4

F3
F2

K2

J1

L3

+VCCP

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

EXP_CLKINN
EXP_CLKINP

EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

PINEVIEW-M_FCBGA8559

H_PWRGD5,12

SLPIOVR#12

PLTRST#5,12,14,15

C435 0.1U_0402_16V7K

DMI_RX011
DMI_RX#011
DMI_RX111
DMI_RX#111

D D

C C

1 2

C436 0.1U_0402_16V7K

1 2

C437 0.1U_0402_16V7K

1 2

C438 0.1U_0402_16V7K

1 2

Close to CPU

CLK_CPU_EXP#8
CLK_CPU_EXP8

XDP Reserve

XDP_TDI

XDP_TMS

XDP_TDO

XDP_PREQ#

XDP_TRST#

XDP_TCK

B B

R341 51_0402_1%

1 2

R342 51_0402_1%

1 2

R343 51_0402_1%

1 2

R344 51_0402_1%

1 2

R345 51_0402_1%

1 2

R346 51_0402_1%

1 2

DRAM POWER OK Logic

+1.5V

+5VALW

R1483

1K_0402_5%

C1293

12

R1484
0_0402_5%

C

C

Q36

2

B

Q37

2

B

E

E

3 1

3 1

MMBT3904_SOT23

MMBT3904_SOT23

0.1U_0603_25V7K

1

2

SYSON15,16,23

PM_SLP_S4#12,15

A A

1 2

R1492 1K_0402_5%

1 2

R1487 1K_0402_5%

@

5

R1482

10K_0402_5%

1 2

12

1U_0603_10V6K

1

C1294

2

PINEVIEW_M

REV = 1.1

DMI

XDP_PREQ#5
XDP_PRDY#5

XDP_TDO5
XDP_TRST#5

DRAM_PWROK

12

R1486

0_0402_5%

@

4

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

EXP_RCOMPO

EXP_ICOMPI

EXP_RBIAS

1 OF 6

XDP_BPM#35
XDP_BPM#25

XDP_BPM#15
XDP_BPM#05

R354 1K_0402_5%

1 2

R347 1K_0402_5%

1 2

CPU_ITP8
CPU_ITP#8

R348

PLTRST#

1 2

XDP_TDI5
XDP_TMS5

XDP_TCK5

12

R370
0_0402_5%

@

DDR3_PG 23

4

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD
RSVD

XDP_PREQ#
XDP_PRDY#

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1

XDP_BPM#0

XDP_TDO

XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

G2
G1
H3
J2

Must be placed within 500 mils from Pineview-M pins

EXP_RCOMPO

L10
L9

EXP_RBIAS

L8

N11
P11

K3
L2
M2
N2

1K_0402_1%

DRAMRST#7

XDP_TRST#

XDP_TDI

T38
T39

XDP_TDO

DMI_TX0 11
DMI_TX#0 11
DMI_TX1 11
DMI_TX#1 11

R162 49.9_0402_1%
R203 750_0402_1%

JP16

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_87151-24051

R369

@

10K_0402_5%

DRAMRST# DRAMRST#_R

XDP_PREQ#

R1480

1 2

XDP_TMS
XDP_TCK

3

2

3

D40

1

PJDLC05C_SOT23-3

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

DDR_A_DQS#[0..7]7

DDR_A_DQS[0..7]7

0_0402_5%

2

D39

1

Issued Date

3

DDR_A_D[0..63]7

DDR_A_DM[0..7]7

DDR_A_MA[0..14]7

DDR_A_WE#7
DDR_A_CAS#7
DDR_A_RAS#7

DDR_A_BS07
DDR_A_BS17
DDR_A_BS27

DDR_CS#07
DDR_CS#17

DDR_CKE07
DDR_CKE17

M_ODT07
M_ODT17

M_CLK_DDR07
M_CLK_DDR#07
M_CLK_DDR17
M_CLK_DDR#17

+1.5V+1.5V

12

R50

1K_0402_1%

12

R142

1K_0402_1%

2

3

D38

1

PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

2010/5/7 2011/5/7

3

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS#0
DDR_CS#1

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

DRAM_PWROK
DRAMRST#_R

Place to close U31.AB4

DDR_REF
DDR_RPD

C1179

0.1U_0402_16V7K

R242

1

C1180

0.01U_0402_16V7K

2

R243

DDR_RPU

80.6_0402_1%

80.6_0402_1%

1

2

+1.5V

Compal Secret Data

Deciphered Date

T40
T41

DDR_RPU

DDR_RPD

2

AH19

AJ18
AK18
AK16

AJ14
AH14
AK14

AJ12
AH13
AK12
AK20
AH12

AJ11

AJ24

AJ10

AK22

AJ22
AK21

AJ20
AH20
AK11

AH22
AK25

AJ21

AJ25

AH10

AH9

AK10

AK24
AH26
AH24
AK27

AG15
AF15
AD13
AC13

AC15
AD15
AF13
AG13

AD17
AC17
AB15
AB17

AB4
AK8

AB11
AB13

AL28
AK28

AJ26

AK29

2

AJ8

U71B

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#

DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

RSVD_TP
RSVD_TP

DDR_VREF
DDR_RPD
DDR_RPU

RSVD

PINEVIEW-M_FCBGA8559

DDR_A

1

PINEVIEW_M

REV = 1.1

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1

DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A_DM_6

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

2 OF 6

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Pineview(1/3)-DMI,DDR

LA-6371P

AD3
AD2
AD4

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AB8
AD7
AA9

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AD8
AD10
AE8

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

AK5
AK3
AJ3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AG22
AG21
AD19

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

AE26
AG27
AJ27

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

AE30
AF29
AF30

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

AB27
AA27
AB26

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_DQS0

DDR_A_DQS#0

DDR_A_DM0

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_DQS1

DDR_A_DQS#1

DDR_A_DM1

DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_DQS2

DDR_A_DQS#2

DDR_A_DM2

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DM3

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_DQS4

DDR_A_DQS#4

DDR_A_DM4

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS5

DDR_A_DQS#5

DDR_A_DM5

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_DQS6

DDR_A_DQS#6

DDR_A_DM6

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_DQS7

DDR_A_DQS#7

DDR_A_DM7

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

1

4 27Friday, May 07, 2010

0.1

5

4

3

2

1

U71C

D12

T2
T12
T3
T4
T13
T5

D D

R1378

C C

B B

A A

T6
T7
T14

XDP_RSVD_09

T8
T15
T9
T16
T10

1 2

T17

1K_0402_5%

T11
T28

T37

T18
T19
T20
T21

T22
T23
T24

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

+3VS

0.1U_0402_16V7K

C79

1 2

2200P_0402_50V7K

1

2

C80

XDP_RSVD_00

A7

XDP_RSVD_01

D6

XDP_RSVD_02

C5

XDP_RSVD_03

C7

XDP_RSVD_04

C6

XDP_RSVD_05

D8

XDP_RSVD_06

B7

XDP_RSVD_07

A9

XDP_RSVD_08

D9

XDP_RSVD_09

C8

XDP_RSVD_10

B8

XDP_RSVD_11

C10

XDP_RSVD_12

D10

XDP_RSVD_13

B11

XDP_RSVD_14

B10

XDP_RSVD_15

B12

XDP_RSVD_16

C11

XDP_RSVD_17

L11

RSVD

AA7

RSVD_TP

AA6

RSVD_TP

R5

RSVD_TP

R6

RSVD_TP

AA21

RSVD_TP

W21

RSVD_TP

T21

RSVD_TP

V21

RSVD_TP

H_THERMDA

H_THERMDC

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

CRT_HSYNC
CRT_VSYNC

CRT_GREEN

VGA

CRT_DDC_DATA

CRT_DDC_CLK

REFCLKINN

REFSSCLKINP

REFSSCLKINN

PM_EXTTS#_1/DPRSLPVR

PM_EXTTS#_0

HPL_CLKINN
HPL_CLKINP

MISC

CRT_RED

CRT_BLUE

CRT_IRTN

DAC_IREF

REFCLKINP

PWROK

RSTIN#

M30
M29

N31
P30
P29
N30

GMCH_CRT_DATA

L31

GMCH_CRT_CLK

L30

P28

Y30
Y29
AA30
AA31

K29
J30
L5
AA3

W8
W9

To be placed <2 50 mils to U71 ball

GMCH_CRT_R

GMCH_CRT_G

GMCH_CRT_B

GMCH_ENBKL

To be placed <5 00 mils to U71 ball

3 OF 6

CPU THERMAL SENSOR

U2

GND

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

10K_0402_5%

R58

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR MSOP 8P SENSOR

Address:100_1100

SMCLK

SMDATA

ALERT#

GMCH_HSYNC
GMCH_VSYNC

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B

CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

0_0402_5%

PM_EXTTS#1
PM_EXTTS#0
H_PWROK
PLTRST#

CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK

H_PWROK

EC_SMB_CK2 15

EC_SMB_DA2 15

12

+3VS

T52
T53

R201 be placed <500 mils to U7 1.P28

T54
T57

R201 665_0402_1%

CPU_DREFCLK 8
CPU_DREFCLK# 8
CPU_SSCDREFCLK 8
CPU_SSCDREFCLK# 8

R200

PM_EXTTS#0 7

PLTRST# 4,12,14,15

R306

R307

1 2

150_0402_1%
R308

1 2

150_0402_1%
R309

1 2

150_0402_1%

R34

100K_0402_5%

R305

1 2

0_0402_5%

1 2

0_0402_5%

PM_DPRSLPVR 12

CLK_CPU_HPLCLK# 8
CLK_CPU_HPLCLK 8

@

PM_EXTTS#0

VGATE 8,12,25

PCH_OK 12

1

2

+3VS

12

R143
10K_0402_5%

Close to Processor
pin

LVDS_ACLK#9
LVDS_ACLK9
LVDS_A0#9
LVDS_A09
LVDS_A1#9
LVDS_A19
LVDS_A2#9
LVDS_A29

H_SMI#

C1171
470P_0402_50V7K

R151 be placed U71.R22

GMCH_ENBKL15
DPST_PWM9

LVDS_SCL9
LVDS_SDA9

GMCH_ENVDD9

XDP_TDI4
XDP_TDO4
XDP_TCK4
XDP_TMS4
XDP_TRST#4

H_PROCHOT#

2.37K_0402_1%

GMCH_ENBKL

XDP_BPM#04
XDP_BPM#14
XDP_BPM#24
XDP_BPM#34

H_THERMDA
H_THERMDC

+VCCP

R151

T48T25
T49
T50
T51

T55

XDP_TDI
XDP_TDO
XDP_TCK

XDP_TMS
XDP_TRST#

R202
68_0402_5%

Close to Processor
pin

H_GTLREF

C939

PINEVIEW_M

REV = 1.1

ICH

LVDS

CPU

4 OF 6

+VCCP

R144
1K_0402_1%

1

R155
2K_0402_1%

2

1U_0603_10V6K

U71D

U25

LA_CLKN

U26

LA_CLKP

R23

LA_DATAN_0

R24

LA_DATAP_0

N26

LA_DATAN_1

N27

LA_DATAP_1

R26

LA_DATAN_2

R27

LA_DATAP_2

R22

LIBG

J28

LVBG

N22

LVREFH

N23

LVREFL

L27

LBKLT_EN

L26

LBKLT_CTL

L23

LCTLA_CLK

K25

LCTLB_DATA

K23

LDDC_CLK

K24

LDDC_DATA

H26

LVDD_EN

G11

BPM_1_0#

E15

BPM_1_1#

G13

BPM_1_2#

F13

BPM_1_3#

B18

BPM_2_0#/RSVD

B20

BPM_2_1#/RSVD

C20

BPM_2_2#/RSVD

B21

BPM_2_3#/RSVD

G5

RSVD

D14

TDI

D13

TDO

B14

TCK

C14

TMS

C16

TRST#

D30

THRMDA_1

E30

THRMDC_1

C30

THRMDA_2/RSVD

D31

THRMDC_2/RSVD

PINEVIEW-M_FCBGA8559

placed within 0.5" of processor
pin and 5mils spacing.

SMI#
A20M#
FERR#

LINT0
LINT1

IGNNE#

STPCLK#

DPRSTP#

DPSLP#

INIT#
PRDY#
PREQ#

THERMTRIP#

PROCHOT#

CPUPWRGOOD

GTLREF

VSS

RSVD
RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

EXTBGREF

H_SMI#

E7

H_A20M#

H7

H_FERR#

H6

H_INTR

F10

H_NMI

F11

H_IGNNE#

E5

H_STPCLK#

F8

H_DPRSTP#

G6

H_DPSLP#

G10

H_INIT#

G8

XDP_PRDY#

E11

XDP_PREQ#

F15

H_THERMTRIP#

E13

H_PROCHOT#

C18

H_PWRGD

W1

H_GTLREF

A13
H27

L6
E17

CLK_CPU_BCLK#

H10

CLK_CPU_BCLK

J10

CPU_BSEL0

K5

CPU_BSEL1

H5

CPU_BSEL2

K6

CPU_VID0

H30

CPU_VID1

H29

CPU_VID2

H28

CPU_VID3

G30

CPU_VID4

G29

CPU_VID5

F29

CPU_VID6

E29

L7
D20
H13
D18

K9
D19

H_EXTBGREF

K7

H_EXTBGREF

C940

placed within 0.5" of processor
pin and 5mils spacing.

1U_0603_10V6K

T26
T27

1

2

H_SMI# 10
H_A20M# 10
H_FERR# 10
H_INTR 10
H_NMI 10
H_IGNNE# 10
H_STPCLK# 10

H_DPRSTP# 12
H_DPSLP# 12

H_INIT# 10
XDP_PRDY# 4
XDP_PREQ# 4

H_THERMTRIP# 10

H_PWRGD 4,12

CPU_BSEL0 8
CPU_BSEL1 8
CPU_BSEL2 8

CPU_VID0 25
CPU_VID1 25
CPU_VID2 25
CPU_VID3 25
CPU_VID4 25
CPU_VID5 25
CPU_VID6 25

+VCCP

R244
976_0402_1%

R156

3.3K_0402_1%

CLK_CPU_BCLK# 8
CLK_CPU_BCLK 8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2010/5/7 2011/5/7

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Pineview(2/3)-HOST,CRT,LVDS

LA-6371P

1

5 27Friday, May 07, 2010

0.1

5

AK13
AK19

AL11
AL16
AL21
AL25

AA10
AA11

W14
W16
W18
W19

AK9

AK7

W10
W11

T13
T14
T16
T18
T19
V13
V19

AL7

U10

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

VCCA_DDR

U5

VCCA_DDR

U6

VCCA_DDR

U7

VCCA_DDR

U8

VCCA_DDR

U9

VCCA_DDR

V2

VCCA_DDR

V3

VCCA_DDR

V4

VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

U71E

GFX/MCH

GFX supply current: 1.38A
Sustained GFX supply current: 1.05A

D D

DDR supply current 2.27A

+1.5V

1U_0402_6.3V6K

1

1

C188

C1287

2

2

22U_0805_6.3V6M

C C

+1.5V

1

1

C1288

C267

2

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

C186

C187

2

1U_0402_6.3V6K

DDR analog supp ly current: 1.3 2A

+VCCA_VCCD

C55

1U_0402_6.3V6K

1

2

1

2

C243

+0.89V

1

C85

2

1U_0402_6.3V6K

1

1

C236

2

2

C243 to closed U71.U10

22U_0805_6.3V6M

Display PLL SFR and CRT DAC su pply
current: 0.154A

1U_0402_6.3V6K

4.7U_0603_6.3V6K

Place closed U7 1.AA19

AA19

@

1

2

1U_0402_6.3V6K

V11

AC31

T30

T31

J31

C3
B2
C2

A21

1U_0603_10V6K

1

C77

2

1U_0402_6.3V6K

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

VCCACRTDAC

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI

PINEVIEW-M_FCBGA8559

2

1

C51

C15

1

2

0.1U_0402_16V7K

5 OF 6

10U_0603_6.3V6M

1

+

C276
330U_X_2VM_R6M

2

1

B B

A A

+1.8VS

R321

0_0603_5%

+VCCP

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL
supply current: 0.33A

+0.89V

1

2

C74

C81

2

1

2.2U_0603_10V6K

1U_0402_6.3V6K

1

C12890.1U_0402_16V7K

C1290

0.1U_0402_16V7K

2

2

12

1

1

C192

C189

2

2

1U_0603_10V6K

+3VS

GIO supply current: 0.006A

+RING_EAST
+RING_WEST

1

1

C70

C71

2

2

1U_0402_6.3V6K

+VCC_CRT_DAC

1U_0603_10V6K

1

1

C75

C76

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C50

1

C78

2

Close Chipset pin

5

PINEVIEW_M

DDR

EXP\CRT\PLL

REV = 1.1

POWER

DMI

4

CPU

VCCSENSE
VSSSENSE

VCCALVDS
VCCDLVDS

LVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

VCCSFR_DMIHMPLL

4

A23

VCC

A25

VCC

A27

VCC

B23

VCC

B24

VCC

B25

VCC

B26

VCC

B27

VCC

C24

VCC

C26

VCC

D23

VCC

D24

VCC

D26

VCC

D28

VCC

E22

VCC

E24

VCC

E27

VCC

F21

VCC

F22

VCC

F25

VCC

G19

VCC

G21

VCC

G24

VCC

H17

VCC

H19

VCC

H22

VCC

H24

VCC

J17

VCC

J19

VCC

J21

VCC

J22

VCC

K15

VCC

K17

VCC

K21

VCC

L14

VCC

L16

VCC

L19

VCC

L21

VCC

N14

VCC

N16

VCC

N19

VCC

N21

VCC

C29
B29
Y2

VCCA

+VCCP

D4

VCCP

B4

VCCP

B3

VCCP

Please closed U 71.D4

V30
W31

T1
T2
T3

P2

RSVD

AA1

E2

VCCP

3

1

C431

2

1U_0402_6.3V6K

+CPU_CORE

1U_0402_6.3V6K

1

C428

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C430

C429

2

2

Please closed U 71

+CPU_CORE

2 x 330uF(6mohm/2)

1

+

C275

2

330U_X_2VM_R6M

C1152

C1153

1

22U_0805_6.3V6M

2

VCCSENSE
VSSSENSE

Processor Core analog supply current: 0.08A

1

C1161

0.1U_0402_16V7K

2

+VCC_ALVD
+VCC_DLVD

+VCC_DMI

+DMI_HMPLL

1

0.1U_0402_16V7K

2

VCCSENSE 25
VSSSENSE 25

1

C391

0.01U_0402_16V7K

2

Please closed U 71.Y2

LVDS supply cur rent: 0.06A

DMI analog supply current: 0.48A

T56

SFR & DMIHMPLL supply current: 0.104A

+VCCP

C1162

1

2

+1.5VS

C278

+CPU_CORE

C1154

22U_0805_6.3V6M

1

+

2

330U_X_2VM_R6M

1

22U_0805_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

+VCCP

R20

1 2

0_0603_5%

R21

1 2

0_0603_5%

C64

1U_0603_10V6K

R28

1 2

0_0603_5%

C68

1U_0603_10V6K

R53

1 2

0_0805_5%

VCCSENSE

VSSSENSE

+1.8VS

R25

1 2

MBK1608601YZF_2P

R18

1 2

0_0603_5%

R27

1 2

0_0603_5%

2010/5/7 2011/5/7

R32

1 2

100_0402_1%
R31

1 2

100_0402_1%

+VCC_CRT_DAC

1

C239
1U_0603_10V6K

2

+DMI_HMPLL

1

C69
1U_0603_10V6K

2

R26

1 2

100NH +-5% LL1608-FSLR10J

+VCC_DLVD

1

C235
1U_0603_10V6K

2

Compal Secret Data

+RING_EAST

1

C242
1U_0603_10V6K

2

+RING_WEST

1

1

2

2

1

1

1U_0603_10V6K

2

2

+CPU_CORE

+VCC_ALVD

1

C56

2

Deciphered Date

C241
1U_0603_10V6K

+VCC_DMI

C237

+VCCA_VCCD

22U_0805_6.3V6M

2

1

PINEVIEW_M

U71F

REV = 1.1

A11

VSS

A16

VSS

A19

VSS

A29

RSVD_NCTF

A3

RSVD_NCTF

A30

RSVD_NCTF

A4

RSVD_NCTF

AA13

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA2

VSS

AA22

VSS

AA25

VSS

AA26

VSS

AA29

VSS

AA8

VSS

AB19

VSS

AB21

VSS

AB28

VSS

AB29

VSS

AB30

VSS

AC10

VSS

AC11

VSS

AC19

VSS

AC2

VSS

AC21
AC28
AC30
AD26

AD5

AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10

AG3
AH18
AH23
AH28

AH4

AH6

AH8

AJ1
AJ16
AJ31

AK1

AK2
AK23
AK30
AK31
AL13
AL19

AL2
AL23
AL29

AL3
AL30

AL9

B13

B16

B19

B22

B30

B31

B5
B9

C1
C12
C21
C22
C25
C31
D22

E1
E10
E19
E21
E25

E8
F17
F19

Title

Size Document Number Rev

Custom

Date: Sheet of

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 6

PINEVIEW-M_FCBGA8559

Compal Electronics, Inc.

Pineview(3/3)-POWER,GND

LA-6371P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

T29

1

6 27Friday, May 07, 2010

0.1

5

DDR_A_DQS#[0..7]4

DDR_A_D[0..63]4

DDR_A_DM[0..7]4

DDR_A_DQS[0..7]4

D D

C C

B B

A A

DDR_A_MA[0..14]4

Layout Note:
Place near JDIMM1

+1.5V

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

1

+

2

+0.75VS

0.1U_0402_16V7K

C128

2

330U_X_2VM_R6M

0.1U_0402_16V7K

C86

1

1

2

2

5

C94

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

2.2U_0603_6.3V6K

1

1

C129

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C87

C88

1

1

2

2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

1

C109

C110

C89

C130

2

2

0.1U_0402_16V7K

1

1

C90

2

2

4

+1.5V

12

R61

1K_0402_1%

R62

1K_0402_1%

+1.5V

R59

1K_0402_1%

R60

1K_0402_1%

0.1U_0402_16V7K

0.1U_0402_16V7K

C106

C105

1

2

0.1U_0402_16V7K

C107

1

1

2

2

4

12

12

+V_DDR3_VREF_CA

12

C108

+V_DDR3_VREF_DQ

0.1U_0402_16V7K

C421

1

2

0.1U_0402_16V7K

C424

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C117

1

2

@

C118

1

2

@

3

+V_DDR3_VREF_DQ

2.2U_0603_6.3V6K

1

C112

C111

2

DDR_CKE04

DDR_A_BS24

M_CLK_DDR04
M_CLK_DDR#04

DDR_A_BS04

DDR_A_WE#4
DDR_A_CAS#4

DDR_CS#14

+3VS

C116

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

DDR_A_D0

1

DDR_A_D1

DDR_A_DM0

2

DDR_A_D2

0.1U_0402_16V7K

DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS#1

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R66 10K_0402_5%

1 2

1

1

C141

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

2010/5/7 2011/5/7

+1.5V +1.5V

+0.75VS

12

R65

10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U2SN-7F

Compal Secret Data

Deciphered Date

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1

74
76
78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

2

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS#0

114

M_ODT0

116
118

M_ODT1

120
122
124
126
128

DDR_A_D36

130

DDR_A_D37

132
134

DDR_A_DM4

136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168

DDR_A_DM6

170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

PM_EXTTS#0

198

CLK_SMBDATA

200

CLK_SMBCLK

202
204

206

+0.75VS

Custom

Date: Sheet of

1

DRAMRST# 4

DDR_CKE1 4

M_CLK_DDR1 4
M_CLK_DDR#1 4

DDR_A_BS1 4
DDR_A_RAS# 4

DDR_CS#0 4
M_ODT0 4

M_ODT1 4

+V_DDR3_VREF_CA

0.1U_0402_16V7K

2.2U_0603_6.3V6K

PM_EXTTS#0 5
CLK_SMBDATA 8
CLK_SMBCLK 8

Title

DDRIII SO-DIMM A

Size Document Number Rev

LA-6371P

C1292

C1291

1

1

2

2

Compal Electronics, Inc.

1

7 27Friday, May 07, 2010

0.1

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

+3VS

R435

10K_0402_5%

1 2

CK_PWRGD

13

D

Q7

R52

FSC

R76

2.2K_0402_5%

FSA

1 2

R69
0_0402_5%

1K_0402_1%

1 2

1 2

R119
0_0402_5%

R98
10K_0402_5%

1 2

R84
0_0402_5%

2

G

SSM3K7002FU_SC70-3

S

+VCCP

12

R68

@

470_0402_5%

12

12

R73

@

1K_0402_5%

+VCCP

12

R113

470_0402_5%

12

R110

@

0_0402_5%

+VCCP

12

R92

@

470_0402_5%

12

12

R87

@

0_0402_5%

C161 22P_0402_50V8J

C164 22P_0402_50V8J

Routing the trace at least 10mil

Placed within 500 mil

5

CLK_ENABLE#25

C C

CPU_BSEL05

FSB

CPU_BSEL15

B B

CPU_BSEL25

A A

Reserved

+3VM_CK505

R1348 0_0603_5% @

+1.5VS

R1349 0_0603_5%

1

C1147

47P_0402_50V8J

@

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

CLK_XTAL_IN

12

Y1

14.318MHZ_16PF_7A14300083

CLK_XTAL_OUT

10U_0603_6.3V6M

2

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

4

+3VS

C1114

10U_0603_6.3V6M

1

2

+VCCP

C1102

10U_0603_6.3V6M

1

2

1 2

CLK_PCH_48M11

CLK_PCH_14M12

CLK_PCI_MINI14

CLK_PCI_LPC15

CLK_PCI_PCH10

+3VS+3VS +3VS

4

+1.5VM_CK505

1

C140

0.1U_0402_16V7K

2

+1.05VM_CK505

+1.5VM_CK505

R95

10K_0402_5%

@

1 2

R90

10K_0402_5%

1 2

1 2

1

C1119

0.1U_0402_16V7K

2

R85

10K_0402_5%

@

1 2

ITP_EN PCI4_SEL PCI2_TME

R89

10K_0402_5%

1 2

3

L29 FBMA-L11-201209-221LMA30T_0805
C1117

0.1U_0402_16V7K

1

2

L30 FBMA-L11-201209-221LMA30T_0805
C1110

0.1U_0402_16V7K

1

2

+3VM_CK505

12

12

C1146

47P_0402_50V8J

1

C1145

2

47P_0402_50V8J

+1.05VM_CK505

1

2

1

C174

10U_0603_6.3V6M

2

1

C175

10U_0603_6.3V6M

2

1

2

1

C139

0.1U_0402_16V7K

2

SA00003H730 (Realtek :RTM890N-397-VC-GRT)

1

C160

2

R1350 0_0402_5%

R1351 0_0402_5%

R75 33_0402_5%

1 2

C386 10P_0402_50V8J

@

1 2

C390 10P_0402_50V8J

@

1

C389

@

2

15P_0402_50V8J

15P_0402_50V8J

1 2

1 2

0.1U_0402_16V7K

1 2

@

1 2

1 2

R104

1 2

33_0402_5%

VGATE5,12,25

R88

1 2

R86

1 2

R80

1 2

1

C388

@

2

R71

10K_0402_5%

@

R77

10K_0402_5%

CK_PWRGD

33_0402_5%

PCI2_TME

33_0402_5%

33_0402_5%

+3VM_CK505

1

C169

2

+1.05VM_CK505

1

2

1 2

R376 0_0402_5%

1 2

R371 0_0402_5%

H_STP_CPU#12

H_STP_PCI#12

CLK_XTAL_IN

CLK_XTAL_OUT

C173

0.1U_0402_16V7K

FSA

FSB

FSC

@

PCI4_SEL

ITP_EN

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

RTM890N-397-VC-GRT_QFN72_10X10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

C172

0.1U_0402_16V7K

2

1

C138

0.1U_0402_16V7K

2

1

C167

0.1U_0402_16V7K

2

SRC_0#/DOT_96#

LCDCLK#/27M_SS

SRC_8#/CPU_ITP#

USB_1/CLKREQ_A#

1

C148

0.1U_0402_16V7K

2

1

C137

0.1U_0402_16V7K

2

9

SDA

10

SCL

71

CPU_0

70

CPU_0#

68

CPU_1

67

CPU_1#

24

SRC_0/DOT_96

25

28

LCDCLK/27M

29

32

SRC_2

33

SRC_2#

35

SRC_3

36

SRC_3#

39

SRC_4

40

SRC_4#

57

SRC_6

56

SRC_6#

61

SRC_7

60

SRC_7#

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

64

63

44

45

50

51

48

47

37

41

58

65

43

49

46

21

SRC_8/CPU_ITP

2010/5/7 2011/5/7

1

C146

0.1U_0402_16V7K

2

CLK_SMBDATA

CLK_SMBCLK

CLK_CPU_BCLK

CLK_CPU_BCLK#

CLK_CPU_HPLCLK

CLK_CPU_HPLCLK#

CLK_CPU_DREFCLK

CLK_CPU_DREFCLK#

CPU_SSCDREFCLK

CPU_SSCDREFCLK#

CLK_PCIE_WLAN

CLK_PCIE_WLAN#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_PCIE_PCH

CLK_PCIE_PCH#

CLK_CPU_EXP

CLK_CPU_EXP#

WLAN_CLKREQ#

Compal Secret Data

Deciphered Date

2

1

+3VS

R72

+3VS

2.2K_0402_5%

Q10A

6 1

2

5

3

Q10B

4

2N7002DW-T/R7_SOT363-6

PCH_SMBDATA12

1

C165

0.1U_0402_16V7K

2

PCH_SMBCLK12 CLK_SMBCLK 7

2N7002DW-T/R7_SOT363-6

R91

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SRC PORT LIST

CLK_CPU_BCLK 5

CLK_CPU_BCLK# 5

CLK_CPU_HPLCLK 5

CLK_CPU_HPLCLK# 5

CPU_DREFCLK 5

CPU_DREFCLK# 5

CPU_SSCDREFCLK 5

CPU_SSCDREFCLK# 5

CLK_PCIE_WLAN 14

CLK_PCIE_WLAN# 14

CLK_PCIE_SATA 10

CLK_PCIE_SATA# 10

CLK_PCIE_PCH 11

CLK_PCIE_PCH# 11

CPU_ITP 4

CPU_ITP# 4

CLK_CPU_EXP 4

CLK_CPU_EXP# 4

PORT

SRC1
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

WLAN_CLKREQ#PCI1_CLK

DEVICE

CPU_SSCDREFCLK

PCIE_WLAN
PCIE_SATA
PCIE_PCH
CPU_ITP
CLK_CPU_EXP
PCIE_LAN

R121 10K_0402_5%

12

REQ PORT LIST

DEVICEPORT

WLAN_CLKREQ# 14

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Title

Size Document Number Rev

C

LA-6371P

Date: Sheet of

PCIE_WLAN

PCIE_LAN

Compal Electronics, Inc.

Clock Generator CK505

1

CLK_SMBDATA 7

+3VS

8 27Friday, May 07, 2010

0.1

5

4

3

2

1

LCD POWER CIRCUIT

Touch Screen Conn.

D D

2N7002DW-T/R7_SOT363-6

GMCH_ENVDD5

+LCDVDD

12

3

Q4B

4

1 2

R175 0_0402_5%

100K_0402_5%

R582
300_0603_5%

5

12

R392

+3VALW

12

R580
100K_0402_5%

61

Q4A

2

2N7002DW-T/R7_SOT363-6

R581

1 2

4.7K_0402_5%

C1277

0.047U_0402_16V7K

1

2

2

C1115

+3VS

S

G

D

1 3

1

2

Place close to JLVDS1

W=60mils

1

C1116

Q16
AO3413_SOT23-3

+LCDVDD

C1118

4.7U_0603_6.3V6K

2

1

2

C1164

4.7U_0603_6.3V6K

W=60mils

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

+5VS

1 2

R101 0_0805_5%

USB20_P111
USB20_N111

40mil

+5VS_TS

JTS1

7

G2

5

6

5

G1

4

4

3

3

2

2

1

1

ACES_87151-05051

CONN@

C C

LCD/PANEL Conn.

JLVDS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

B B

14
15
16
17
18
19
20
21
22
23

31

24

G1

32

25

G2

33

26

G3

34

27

G4

35

28

G5

29
30

ACES_50406-03071-001

CONN@

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

LVDS_ACLK
LVDS_ACLK#

LVDS_A2
LVDS_A2#

LVDS_A1
LVDS_A1#

LVDS_A0
LVDS_A0#

LVDS_SDA
LVDS_SCL
BKOFF#
LVDS_PWM

+LCDVDD_L

R100 0_0805_5%

1 2

LVDS_ACLK 5
LVDS_ACLK# 5

LVDS_A2 5
LVDS_A2# 5

LVDS_A1 5
LVDS_A1# 5

LVDS_A0 5
LVDS_A0# 5

BKOFF# 15

+3VS
+LCDVDD

+LEDVDD

W=40mils

1

C1111

680P_0402_50V7K

2

LVDS_SCL

LVDS_SDA

+LEDVDD

L1

FBMA-L11-201209-221LMA30T_0805

1

C1112

68P_0402_50V8J

2

+3VS

R1180

1 2

1 2

2.2K_0402_5%

R1181

2.2K_0402_5%

12

220P_0402_50V7K

B+

LVDS_PWM DPST_PW M

LVDS_SCL 5

LVDS_SDA 5

LVDS_PWM

BKOFF#

C1156

R111

1 2

R112

1 2

12

12

0_0402_5%@

0_0402_5%

C1109

220P_0402_50V7K

INVT_PWM

DPST_PWM 5

INVT_PWM 15

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2010/5/7 2011/5/7

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

LVDS CONN.

LA-6371P

1

9 27Friday, May 07, 2010

0.1