Compal LA-6091P NAVD0 Schematic

ZZZ1

ZZZ1

D0DAZ@

D0DAZ@

PCB

PCB

ZZZ3

ZZZ3

LA-6091P

LA-6091P

D0DA@

D0DA@

A

ZZZ4

ZZZ4

LS-6094P

LS-6094P

D0DA@

D0DA@

ZZZ5

ZZZ5

LS-6095P

LS-6095P

D0DA@

D0DA@

B

PJP1

PJP1

45@

45@

DCIN

DCIN

DC301008S00

C

D

E

1 1

ZZZ2

ZZZ2

PCB

PCB

E0DAZ@

E0DAZ@

ZZZ6

ZZZ6

LA-6091P

LA-6091P

E0DA@

E0DA@

ZZZ8

ZZZ8

LS-6096P

LS-6096P

E0DA@

E0DA@

ZZZ7

ZZZ7

LS-6097P

LS-6097P

E0DA@

E0DA@

ZZZ9

ZZZ9

LS-6098P

LS-6098P

E0DA@

E0DA@

ZZZ10

ZZZ10

LS-6099P

LS-6099P

E0DA@

E0DA@

Compal Confidential

2 2

NAVD0 Schematics Document

Intel Pineview Processor with Tigerpoint + DDRII + NV OPTIMUS

3 3

2010-02-09

REV: 1.0

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1 46Wednesday, March 03, 2010

1 46Wednesday, March 03, 2010

1 46Wednesday, March 03, 2010

E

1.0

1.0

1.0

A

B

C

D

E

Compal Confidential

Clock Generator
CK505

page 13

Model Name : NAVD0
File Name : LA-6091P

1 1

Thermal Sensor

EMC1402

2 2

VGA
N11M-OP2

page 8,9,10,11,12

page 5

MINI Card x1
3G

page 24

CRT Conn.

page 15

LCD Conn.

page 14

WLAN

page 25

RGB

LVDS

PCI-Express

10/100 Ethernet

AR8132L

page 23

Pineview
FCBGA 559

DMI
X2 mode
GEN1

Tigerpoint

PCBGA360

22x22mm

page 4,5,6

17x17mm

page 17,18,19,20

LPC BUS

Memory BUS(DDRII)

1.8V DDRII 667

SATA

DDRII-SO-DIMM

USB

HDA

HDD Conn.

page 21

page 7

USB Port X2

page 23

BlueTooth

page 24

CMOS CAM

page 14

3G

page 24

HDMI Conn

3 3

page 16

Transfermer

Audio Codec
ALC272

Power ON/OFF

page 22

DC IN

page 36

BATT IN

page 37

DC/DC Interface

3VALW/5VALW

0.89VP/0.9VSP

page 34

page 39

page 41

1.8V/VCCP

CHARGER

4 4

VGA
DC/DC Interface

page 38

CPU_CORE

page 35

page 40

page 42

VGA_CORE/

1.5VSP

A

page 43

B

RJ45

ENE KBC
KB926

Int.KBD

page 32

Touch Pad

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 29

page32

C

SPI

SPI ROM

page 31

Compal Secret Data

Compal Secret Data

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AMP & INT
Speaker

page 29 page 28

D

To Audio Board
INT MIC

page 28

To Audio Board
HeadPhone &
MIC Jack

page 29

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

Card Reader
ENE UB6250

page 27

SD/MMC/MS
CONN

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

E

page 27

2 46Wednesday, March 03, 2010

2 46Wednesday, March 03, 2010

2 46Wednesday, March 03, 2010

1.0

1.0

1.0

A

1 1

B

C

D

E

Voltage Rails

S5

DescriptionPower Plane

VIN

B+

+CPU_CORE

+VCCP

+1.5VS

+1.8V

+0.89VS Graphic core power rail

+3VALW

+3VS

+5VALW

2 2

+5VS

+VSB VSB always on power rail ON

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

3 3

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

RTC power

SIGNAL

SLP_S3#

SLP_S4#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

SLP_S5#

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

S3S1

N/A N/A N/A

ON

ON OFF

ON

ON

ON

ON

ON

N/AN/AN/A

OFF

OFFON

OFF

OFFON

OFFOFFON

OFFOFFON

ON

OFF

OFF

ON ON*

OFF

OFF

ON ON*

OFF

OFFON

ON*

ON

ON

+V +VS Clock

ON

ON

ON

OFF

ON

OFF

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

BOARD ID Table(Page 31)

NAVD0

NAVE0

VCC

Ra

ID

0

1

2

3

5

6

7

3.3V
100K

BRD ID

R01 (EVT)

R02 (DVT)

R03 (PVT)

R10A (MP)

R01 (EVT)4

R02 (DVT)

R03 (PVT)

R10A (MP)

Rb Vab-Typ

Vab-Min

0

8.2K

0.216V

18K

0.436V
33K
56K

1.036V

1.453V 1.759V

100K

1.935V 2.341V

200K

2.500V

NC

0V

0V

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.3V

Vab-Max

0V

0.289V

0.538V

0.875V0.712V

1.264V

3.3V

External PCI Devices

DEVICE REQ/GNT #

IDSEL #

No PCI Device

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

ICH7M SM Bus address

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

Address

1101 001Xb

1010 000Xb

Device

EMC1402

PIRQ

Address

100_11000001 011X b

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

3 46Wednesday, March 03, 2010

3 46Wednesday, March 03, 2010

3 46Wednesday, March 03, 2010

E

1.0

1.0

1.0

5

PINEVIEW_M

U71A

U71A

DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R

D D

CLK_CPU_EXP#<13>
CLK_CPU_EXP<13>

F3
F2
H4

G3

N7
N6

R10

R9

N10

N9

K2

J1

M4

L3

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

EXP_CLKINN
EXP_CLKINP

EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

DMI

DMI

091105 change CPU Part Number to SA00003M870

C435

C435

DMI_RX0<19>

DMI_RX#0<19>

C C

DMI_RX1<19>

DMI_RX#1<19>

C436

C436

C437

C437

C438

C438

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

0.1U_0402_10V7K

0.1U_0402_10V7K

Close to CPU

FAN1 Conn

B B

FAN_SPEED1<31>

A A

EXP_RCOMPO

EXP_ICOMPI

DMI_RX0_R

DMI_RX#0_R

DMI_RX1_R

DMI_RX#1_R

+3VS

12

1

2

+5VS

4

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

EXP_RBIAS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD
RSVD

1 OF 6

1 OF 6

R256

R256
10K_0402_5%

10K_0402_5%

C311

C311
100P_0402_50V8J

100P_0402_50V8J

G2
G1
H3
J2

L10

R162

R162

L9

R203

R203

L8

N11

T38T38

P11

K3
L2
M2
N2

FAN_PWM<31>

1 2

0_0603_5%

0_0603_5%

Must be placed within 500 mils from Pineview-M pins

T39T39

40mil

+VCC_FAN1

091022 change JP12 to ACES_87213_0400G
2010 0105 change JP12 to ACES_85205-04001

0120 Change JP12 BOM structure from ME@ to CONN@

+VCC_FAN1

R817

R817

49.9_0402_1%

49.9_0402_1%
750_0402_1%

750_0402_1%

FAN_PWM

DMI_TX0 <19>
DMI_TX#0 <19>
DMI_TX1 <19>
DMI_TX#1 <19>

1
2
3
4
5
6

ACES_85205-04001

ACES_85205-04001

CONN@

CONN@

3

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DM[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..14]<7>

+1.8V

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS#0
DDR_CS#1

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

R243

R243
R242

R242

DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_A_RAS#<7>

DDR_A_BS0<7>
DDR_A_BS1<7>
DDR_A_BS2<7>

DDR_CS#0<7>
DDR_CS#1<7>

DDR_CKE0<7>
DDR_CKE1<7>

M_ODT0<7>
M_ODT1<7>

M_CLK_DDR0<7>

M_CLK_DDR#0<7>

M_CLK_DDR1<7>

M_CLK_DDR#1<7>

+1.8V

12

R50

R50

1K_0402_1%

1K_0402_1%

12

R142

JP12

JP12

1
2
3
4
G5
G6

R142

1K_0402_1%

1K_0402_1%

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

+1.8V

R369

R369
10K_0402_5%

10K_0402_5%

R370

R370
10K_0402_5%

10K_0402_5%

@

@

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

80.6_0402_1%

2

PINEVIEW_M

DDR_A

DDR_A

PINEVIEW_M

REV = 1.1

REV = 1.1

2 OF 6

2 OF 6

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1

DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A_DM_6

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

U71B

U71B

AH19

DDR_A_MA_0

AJ18

DDR_A_MA_1

AK18

DDR_A_MA_2

AK16

DDR_A_MA_3

AJ14

DDR_A_MA_4

AH14

DDR_A_MA_5

AK14

DDR_A_MA_6

AJ12

DDR_A_MA_7

AH13

DDR_A_MA_8

AK12

DDR_A_MA_9

AK20

DDR_A_MA_10

AH12

DDR_A_MA_11

AJ11

DDR_A_MA_12

AJ24

DDR_A_MA_13

AJ10

DDR_A_MA_14

AK22

DDR_A_WE#

AJ22

DDR_A_CAS#

AK21

DDR_A_RAS#

AJ20

DDR_A_BS_0

AH20

DDR_A_BS_1

AK11

DDR_A_BS_2

AH22

DDR_A_CS#_0

AK25

DDR_A_CS#_1

AJ21

DDR_A_CS#_2

AJ25

DDR_A_CS#_3

AH10

DDR_A_CKE_0

AH9

DDR_A_CKE_1

AK10

DDR_A_CKE_2

AJ8

DDR_A_CKE_3

AK24

DDR_A_ODT_0

AH26

DDR_A_ODT_1

AH24

DDR_A_ODT_2

AK27

DDR_A_ODT_3

AG15

DDR_A_CK_0

AF15

DDR_A_CK_0#

AD13

DDR_A_CK_1

AC13

DDR_A_CK_1#

AC15

DDR_A_CK_3

AD15

DDR_A_CK_3#

AF13

DDR_A_CK_4

AG13

DDR_A_CK_4#

AD17

RSVD

AC17

RSVD

AB15

RSVD

AB17

RSVD

AB4

RSVD

AK8

RSVD

AB11

T40T40
T41T41

AB13

AL28

AK28

AJ26

AK29

RSVD_TP
RSVD_TP

DDR_VREF
DDR_RPD
DDR_RPU

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

AD3
AD2
AD4

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AB8
AD7
AA9

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AD8
AD10
AE8

AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10

AK5
AK3
AJ3

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AG22
AG21
AD19

AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21

AE26
AG27
AJ27

AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27

AE30
AF29
AF30

AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28

AB27
AA27
AB26

AA24
AB25
W24
W22
AB24
AB23
AA23
W27

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

091105 change CPU Part Number to SA00003M870

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Pineview(1/3)

Pineview(1/3)

Pineview(1/3)

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

4 46Wednesday, March 03, 2010

4 46Wednesday, March 03, 2010

4 46Wednesday, March 03, 2010

1

1.0

1.0

1.0

5

PINEVIEW_M

U71C

U71C

D12

T2T2
T12T12
T3T3
T4T4

R1378

R1378

1 2

1K_0402 _5%

1K_0402 _5%

091211 d el T10/T11/T 28

T13T13
T5T5
T6T6
T7T7
T14T14

T8T8
T15T15
T9T9
T16T16

T17T17

T37T37

T18T18
T19T19
T20T20
T21T21

T22T22
T23T23
T24T24
T25T25

D D

C C

B B

AA21

W21

C10
D10
B11
B10
B12
C11

AA7
AA6

V21

A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8

L11

R5
R6

T21

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

RSVD

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

PINEVIEW_M

REV = 1.1

REV = 1.1

VGA

VGA

PM_EXTTS#_1/DPRSLPVR

MISC

MISC

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

REFCLKINP

REFCLKINN
REFSSCLKINP
REFSSCLKINN

PM_EXTTS#_0

PWROK

RSTIN#

HPL_CLKINN
HPL_CLKINP

3 OF 6

3 OF 6

091105 change CPU Part Number to SA00003M870

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

+3VS

1

C80

C80

C79

C79

1 2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_THERM DA

H_THERM DC

2200P_0 402_50V7K

2200P_0 402_50V7K

5

A A

CPU THERMAL SENSOR

U2

U2

GND

8

7

6

5

EC_SMB_ CK2

EC_SMB_ DA2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402 -1-ACZL-TR MSOP 8P SENSOR

EMC1402 -1-ACZL-TR MSOP 8P SENSOR

Address:100_1100

SMCLK

SMDATA

ALERT#

4

091202 m ove R247/R249 from CRT side to CPU side

R249 15_040 2_5%OP T@R249 15_0402_5%OPT@

M30

GMCH_CR T_VSYNC_R

M29

GMCH_CR T_R

N31

GMCH_CR T_G

P30

GMCH_CR T_B

P29
N30

L31
L30

P28

CPU_DRE FCLK

Y30

CPU_DRE FCLK#

Y29

CPU_SSC DREFCLK

AA30

CPU_SSC DREFCLK#

AA31

PM_EXTT S#1

K29

PM_EXTT S#0

J30

H_PW ROK

L5

PLTRST#

AA3

CLK_CPU _HPLCLK#

W8

CLK_CPU _HPLCLK

W9

1 2
1 2

R247 15_040 2_5%OP T@R247 15_0402_5%OPT@

GMCH_CR T_R <15>
GMCH_CR T_G <15>
GMCH_CR T_B <15>

GMCH_CR T_DATA <15>
GMCH_CR T_CLK <15>

R201 665_040 2_1%R201 665_0402_1%

0_0402_ 5%

0_0402_ 5%

R200

R200

PM_EXTT S#0 <7 >

PLTRST# <8,19,24,25,2 6,31>

Modify 08/04

H_A20M#

H_INTR

H_NMI

H_IGNNE#

H_STPCL K#

H_DPSLP #

H_INIT#

H_PW RGD

H_DPRST P#

091212 Add C5, C6, C7, C9, C11, C12, C13, C14
to prevent switch noise

C5 470P_04 02_50V8JC5 470P _0402_50V8J

1 2

C6 470P_04 02_50V8JC6 470P _0402_50V8J

1 2

C7 470P_04 02_50V8JC7 470P _0402_50V8J

1 2

C9 470P_04 02_50V8JC9 470P _0402_50V8J

1 2

C11 470P_04 02_50V8JC11 470P _0402_50V8J

1 2

C12 470P_04 02_50V8JC12 470P _0402_50V8J

1 2

C13 470P_04 02_50V8JC13 470P _0402_50V8J

1 2

C14 470P_04 02_50V8JC14 470P _0402_50V8J

1 2

C66 470P_04 02_50V8JC66 470P _0402_50V8J

1 2

XDP Reserve

XDP_TDI

XDP_TMS

XDP_TDO

XDP_PRE Q#

XDP_TRS T#

XDP_TCK

R58

R58

12

10K_040 2_5%

10K_040 2_5%

4

R341 51 +-1% 04 02R341 51 +-1% 04 02

1 2

R342 51 +-1% 04 02R342 51 +-1% 04 02

1 2

R343 51 +-1% 04 02R343 51 +-1% 04 02

1 2

R344 51 +-1% 04 02R344 51 +-1% 04 02

1 2

R345 51 +-1% 04 02R345 51 +-1% 04 02

1 2

R346 51 +-1% 04 02R346 51 +-1% 04 02

1 2

EC_SMB_ CK2 <8,9,31>

EC_SMB_ DA2 <8,9,31>

+3VS

3

U71D

U71D

GMCH_LV DS_ACLK#<14>

GMCH_LV DS_ACLK<14>
GMCH_CR T_HSYNC <15>
GMCH_CR T_VSYNC <15 >

CPU_DRE FCLK <13>
CPU_DRE FCLK# <13>
CPU_SSC DREFCLK <13>
CPU_SSC DREFCLK# <13>

H_PW ROK

PM_DPRS LPVR <19>

CLK_CPU _HPLCLK# <13>
CLK_CPU _HPLCLK <13>

091216 change value
to 470P

+VCCP

GMCH_LV DS_SCL<1 4>
GMCH_LV DS_SDA<14>

R305 0_0402_ 5%@R305 0_0402_ 5%@

1 2

R306 0_0402_ 5%R306 0_0402_ 5%

1 2

091214 Remove T77
T55 test point
for layout limitation

GMCH_LV DS_A0#<14>
GMCH_LV DS_A0<14>
GMCH_LV DS_A1#<14>
GMCH_LV DS_A1<14>
GMCH_LV DS_A2#<14>
GMCH_LV DS_A2<14>

2.37K_04 02_1%

2.37K_04 02_1%

+3VS

T53T53
T52T52
T54T54
T57T57
T58T58

12

R143

R143
10K_040 2_5%

10K_040 2_5%

GMCH_EN BKL

R213 0_0402_ 5%

R213 0_0402_ 5%

H_THERM DA
H_THERM DC

R307

R307

1 2

150_040 2_1%

150_040 2_1%
R308

R308

1 2

150_040 2_1%

150_040 2_1%
R309

R309

1 2

150_040 2_1%

150_040 2_1%
R34

R34

100K_04 02_5%

100K_04 02_5%

GMCH_EN BKL<31>

INVT_PW M<14 ,31>

GMCH_EN VDD<14>

Place closed to chipset

GMCH_CR T_R

GMCH_CR T_G

GMCH_CR T_B

GMCH_EN BKL

PM_EXTT S#0

R151

R151

VGATE <13 ,19,31,42>

PCH_POK <1 9,31>

T74T74
T75T75
T76T76

T48T48
T49T49
T50T50
T51T51

XDP_TDI
XDP_TDO
XDP_TCK

XDP_TMS
XDP_TRS T#

Close to Processor
pin

Security Class ification

Security Class ification

Security Class ification

2009/10/ 09 201 0/10/09

2009/10/ 09 201 0/10/09

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/ 09 201 0/10/09

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

U25

LA_CLKN

U26

LA_CLKP

R23

LA_DATAN_0

R24

LA_DATAP_0

N26

LA_DATAN_1

N27

LA_DATAP_1

R26

LA_DATAN_2

R27

LA_DATAP_2

LIBG

R22

LIBG

J28

LVBG

N22

LVREFH

N23

LVREFL

L27

@

@

LBKLT_EN

L26

LBKLT_CTL

L23

LCTLA_CLK

K25

LCTLB_DATA

K23

LDDC_CLK

K24

LDDC_DATA

H26

LVDD_EN

G11

BPM_1_0#

E15

BPM_1_1#

G13

BPM_1_2#

F13

BPM_1_3#

B18

BPM_2_0#/RSVD

B20

BPM_2_1#/RSVD

C20

BPM_2_2#/RSVD

B21

BPM_2_3#/RSVD

G5

RSVD

D14

TDI

D13

TDO

B14

TCK

C14

TMS

C16

TRST#

D30

THRMDA_1

E30

THRMDC_1

C30

THRMDA_2/RSVD

D31

THRMDC_2/RSVD

H_PROCH OT#

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Close to Processor
pin

2

091105 change CPU Part Number to SA00003M870

+VCCP

R202

R202
68_0402 _5%

68_0402 _5%

2

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

ICH

ICH

LVDS

LVDS

CPUPWRGOOD

CPU

CPU

4 OF 6

4 OF 6

H_GTLRE F

1

C939

2

@ C939

@

1U_0603_10V6K

1U_0603_10V6K

placed within 0.5"
of processor pin.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

SMI#

A20M#

FERR#

LINT0
LINT1

IGNNE#

STPCLK#

DPRSTP#

DPSLP#

INIT#
PRDY#
PREQ#

THERMTRIP#

PROCHOT#

GTLREF

VSS

RSVD
RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

EXTBGREF

+VCCP

R144

R144
1K_0402 _1%

1K_0402 _1%

R155

R155
2K_0402 _1%

2K_0402 _1%

Add 470PF on
H_SMI# for known issue 07/08

C1171 470P_ 0402_50V7KC1171 470P_ 0402_50V7K

H_SMI#

E7

H_A20M#

H7

H_FERR#GMCH_CR T_HSYNC_R

H6

H_INTR

F10

H_NMI

F11

H_IGNNE#

E5

H_STPCL K#

F8

G6
G10
G8
E11
F15

H_THERM TRIP#

E13

H_PROCH OT#

C18

H_PW RGD

W1

H_GTLRE F

A13
H27

L6
E17

H10
J10

CPU_BSE L0

K5

CPU_BSE L1

H5

CPU_BSE L2

K6

CPU_VID0

H30

CPU_VID1

H29

CPU_VID2

H28

CPU_VID3

G30

CPU_VID4

G29

CPU_VID5

F29

CPU_VID6

E29

L7
D20
H13
D18

K9
D19
K7

1

1 2

H_DPRST P#
H_DPSLP #

H_INIT#
XDP_PRD Y#
XDP_PRE Q#

CLK_CPU _BCLK#
CLK_CPU _BCLK

T26T26
T27T27

H_EXTBG REF

H_EXTBG REF

H_SMI# <18>
H_A20M# <18>
H_FERR# <18>
H_INTR <18>
H_NMI <18>
H_IGNNE# <18>
H_STPCL K# <18>

H_DPRST P# <19 >
H_DPSLP # <19>

H_INIT# < 18>

T78T78
T79T79

H_THERM TRIP# <18>

H_PW RGD <19>

T63T63

CPU_BSE L0 <13>
CPU_BSE L1 <13>
CPU_BSE L2 <13>

CPU_VID0 <42>
CPU_VID1 <42>
CPU_VID2 <42>
CPU_VID3 <42>
CPU_VID4 <42>
CPU_VID5 <42>
CPU_VID6 <42>

1

C940

C940

@

@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CLK_CPU _BCLK# <13 >
CLK_CPU _BCLK <13>

+VCCP

placed within 0.5"
of processor pin.

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Pineview(2/3)

Pineview(2/3)

Pineview(2/3)

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

5 46Wednesd ay, March 03, 20 10

5 46Wednesd ay, March 03, 20 10

5 46Wednesd ay, March 03, 20 10

1

R244

R244
976_040 2_1%

976_040 2_1%

R156

R156

3.3K_040 2_1%

3.3K_040 2_1%

1.0

1.0

1.0

5

U71E

W14
W16
W18
W19

U71E

T13

VCCGFX

T14

VCCGFX

T16

VCCGFX

T18

VCCGFX

T19

VCCGFX

V13

VCCGFX

V19

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

GFX/MCH

GFX/MCH

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

GFX supply current: 1.38A
Sustained GFX supply current: 1.05A

D D

+0.89VS

DDR supply current 2.27A

+1.8V

2.2U_0603_10V6K

2.2U_0603_10V6K

2

1

+1.8V

2.2U_0603_10V6K

1

+VCCP

2

22U_0805_6.3V6M

22U_0805_6.3V6M

R321 0_0402_5%R321 0_0402_5%

+VCCP

2.2U_0603_10V6K

2.2U_0603_10V6K

2.2U_0603_10V6K

C C

C267

C267

Display PLL SFR and CRT DAC s upply
current: 0.154A

B B

+1.8VS

DAC, GIO, LVDS, & LGIO, DPLL, HMPLL
supply current: 0.33A

A A

Modify to 2.2U 05/11

2.2U_0603_10V6K

C188

C188

2

C187

C187

1

2.2U_0603_10V6K

2

2

C186

C186

1

1

2.2U_0603_10V6K

2.2U_0603_10V6K

C85

C85

AK13
AK19

DDR analog supp ly current: 1. 32A

1

1

C243

C243

C55

C55

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C192

C192

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+3VS

GIO supply current: 0.006A

+RING_EAST
+RING_WEST

+0.89VS

1

2

C74

C74

C81

C81

2

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C189

C189

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C71

C71

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C236

C236

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCSFR_AB_DPL

1

2

+VCC_CRT_DAC

1

1

C70

C70

C76

C76

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AA10
AA11

AA19

AC31

1

C75

C75

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Close Chipset pin

5

VCCSM
VCCSM

AK9

VCCSM

AL11

VCCSM

AL16

VCCSM

AL21

VCCSM

AL25

VCCSM

AK7

VCCCK_DDR

AL7

VCCCK_DDR

U10

VCCA_DDR

U5

W10
W11

U6
U7
U8
U9
V2
V3
V4

V11

T30

T31
J31

C3
B2
C2

A21

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

VCCACRTDAC

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

5 OF 6

5 OF 6

DDR

DDR

EXP\CRT\PLL

EXP\CRT\PLL

091105 change CPU Part Number to SA00003M870

1

1

C78

C78

C77

C77

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

POWER

POWER

DMI

DMI

VCCSENSE

VSSSENSE

4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

CPU

CPU

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCSENSE
VSSSENSE

VCCA

VCCP

VCCP
VCCP

VCCALVDS
VCCDLVDS

LVDS

LVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

RSVD

VCCSFR_DMIHMPLL

VCCP

R32

R32

1 2

100_0402_1%

100_0402_1%

R31

R31

1 2

100_0402_1%

100_0402_1%

4

1U_0402_6.3V6K

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

C29
B29
Y2

D4

B4
B3

V30
W31

T1
T2
T3

P2
AA1

E2

1U_0402_6.3V6K

VCCSENSE
VSSSENSE

+VCCP

Processor Core analog supply current: 0.08A

+VCC_ALVD
+VCC_DLVD

LVDS supply cur rent: 0.06A

+VCC_DMI

+DMI_HMPLL

1

C1162

C1162

0.1U_0402_10V6K

0.1U_0402_10V6K

2

+CPU_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C428

C428

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C430

C430

C429

C429

2

2

PLACE IN CAVITY

VCCSENSE <42>
VSSSENSE <42 >

+1.5VS

1

C391

C391

0.01U_0402_16V7K

0.01U_0402_16V7K

2

DMI analog supply current: 0.48A

T56T56

SFR & DMIHMPLL supply current: 0.104A

+VCCP

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C431

C431

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

3

+CPU_CORE

1

1

C1152

C1152

C1153

C1154

C1154

C1153
22U_0805_6.3V6M

22U_0805_6.3V6M

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

C1160

C1160

0.1U_0402_10V6K

0.1U_0402_10V6K

R20 0_ 0402_5%R20 0_0402_5%

R21 0_ 0402_5%R21 0_0402_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

R28 0_ 0603_5%R28 0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.8VS

R25

R25

1 2

MBK1608601YZF_2P

MBK1608601YZF_2P

R18

R18

1 2

0.1UH +-10% MLF1608DR10KT

0.1UH +-10% MLF1608DR10KT

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

+CPU_CORE

330U 2.5V Y

330U 2.5V Y

1

1

0.1U_0402_10V6K

0.1U_0402_10V6K

2

2

1

C242

C242
1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C64

C64

2

12

1

C68

C68

2

+VCC_CRT_DAC

1

C239

C239
1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C69

C69
1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCC_ALVD

1

C56

C56

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C235

C235
1U_0402_6.3V6K

1U_0402_6.3V6K

2

Deciphered Date

Deciphered Date

Deciphered Date

+DMI_HMPLL

+VCC_DLVD

0_0402_5%

0_0402_5%

R26

R26

R27

R27

0_0402_5%

0_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

+

+

2

C1161

C1161

Close U71.D4

1

2

2

A11
A16
A19
A29

1

+

+

C275

C275

330U 2.5V Y

330U 2.5V Y

2

+RING_EAST

+RING_WEST

1

C241

C241
1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCC_DMI

1

C237

C237
1U_0402_6.3V6K

1U_0402_6.3V6K

2

C1155

C1155
1U_0402_6.3V6K

1U_0402_6.3V6K

C278

C278

A3

A30

A4
AA13
AA14
AA16
AA18

AA2
AA22
AA25
AA26
AA29

AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19

AC2
AC21
AC28
AC30
AD26

AD5

AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10

AG3
AH18
AH23
AH28

AH4

AH6

AH8

AJ1
AJ16
AJ31

AK1

AK2
AK23
AK30
AK31

AL13
AL19

AL2
AL23
AL29

AL3
AL30

AL9

B13

B16

B19

B22

B30

B31

B5
B9

C1
C12
C21
C22
C25
C31
D22

E1
E10
E19
E21
E25

E8
F17
F19

091105 change CPU Part Number to SA00003M870

Follow Intel check list change to 22uF 06/06

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

PINEVIEW_M

PINEVIEW_M

U71F

U71F

REV = 1.1

REV = 1.1

VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 6

6 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Pineview(3/3)

Pineview(3/3)

Pineview(3/3)

F24

VSS

F28

VSS

F4

VSS

G15

VSS

G17

VSS

G22

VSS

G27

VSS

G31

VSS

H11

VSS

H15

VSS

H2

VSS

H21

VSS

H25

VSS

H8

VSS

J11

VSS

J13

VSS

J15

VSS

J4

VSS

K11

VSS

K13

VSS

K19

VSS

K26

VSS

K27

VSS

K28

VSS

K30

VSS

K4

VSS

K8

VSS

L1

VSS

L13

VSS

L18

VSS

L22

VSS

L24

VSS

L25

VSS

L29

VSS

M28

VSS

M3

VSS

N1

VSS

N13

VSS

N18

VSS

N24

VSS

N25

VSS

N28

VSS

N4

VSS

N5

VSS

N8

VSS

P13

VSS

P14

VSS

P16

VSS

P18

VSS

P19

VSS

P21

VSS

P3

VSS

P4

VSS

R25

VSS

R7

VSS

R8

VSS

T11

VSS

U22

VSS

U23

VSS

U24

VSS

U27

VSS

V14

VSS

V16

VSS

V18

VSS

V28

VSS

V29

VSS

W13

VSS

W2

VSS

W23

VSS

W25

VSS

W26

VSS

W28

VSS

W30

VSS

W4

VSS

W5

VSS

W6

VSS

W7

VSS

Y28

VSS

Y3

VSS

Y4

VSS

T29

VSS

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1

1.0

1.0

6 46Wednesday, March 03, 2010

6 46Wednesday, March 03, 2010

6 46Wednesday, March 03, 2010

1.0

5

DDR_A_DQS#[0..7]<4>

DDR_A_D[0..63]<4>

DDR_A_DM[0..7]<4>

DDR_A_DQS[0..7]<4>

DDR_A_MA[0..14]<4>

D D

+1.8V

2

C128

C128

C129

C129

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

1

+

+

@

@

C94

C94

C106

C106

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9VS

1

1

1

C117

C117

C119

C119

2

B B

A A

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_MA13
M_ODT0
DDR_CS#0

DDR_A_BS0
DDR_A_MA10
DDR_A_MA3
DDR_A_MA5

M_ODT1
DDR_CS#1
DDR_A_CAS#
DDR_A_WE#

0.1U_0402_16V4Z

0.1U_0402_16V4Z

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

C86

C86

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP6

RP6

1 8
2 7
3 6
4 5

RP2

RP2

1 8
2 7
3 6
4 5

RP3

RP3

1 8
2 7
3 6
4 5

C121

C121

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

C87

C87

0.1U_0402_16V4Z

0.1U_0402_16V4Z

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

2

C110

C110

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

C105

C105

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C88

C88

C122

C122

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP5

RP5

18
27
36
45

RP4

RP4

18
27
36
45

RP1

RP1

18
27
36
45

47_0804_8P4R_5%

47_0804_8P4R_5%

2

C109

C109

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

C108

C108

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C115

C115

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_BS1

DDR_A_MA0
DDR_A_MA2

DDR_A_MA4DDR_A_RAS#

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11

DDR_A_MA14

DDR_A_MA12

DDR_A_MA9
DDR_A_MA8
DDR_A_MA1

2

C130

C130

1

1

C107

C107

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C91

C91

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place near JDIM1

2

1

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

1

C90

C90

C120

C120

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

091204 swap nets for layout

4

1

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil

1

C89

C89

C118

C118

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3

09/03

+DIMM_VREF

+1.8V

12

R61

R61

1K_0402_1%

1K_0402_1%

+DIMM_VREF

12

R62

R62

1K_0402_1%

1K_0402_1%

1

C439

C439

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C440

C440

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C441

C441

C442

C442

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Share +DIMM_VREF for

1.DDRII VREF

2.GMCH SM_VREF_0
SM_VREF_1

1

1

C445

C443

C443

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C445

C444

C444

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C116

C116

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

1

C446

C446

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C141

C141

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

20mils

1

C112

C112

2.2U 6.3V M X5R 0402

2.2U 6.3V M X5R 0402

2

DDR_CKE0<4>

DDR_A_BS2<4>

DDR_A_BS0<4>
DDR_A_WE#<4>

DDR_A_CAS#<4>

DDR_CS#1<4>

M_ODT1<4>

CLK_SMBDATA<13,24>

CLK_SMBCLK<13,24>

Follow Intel Layout checklist, add C141 05/12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C111

C111

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS#1

M_ODT1

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

CLK_SMBDATA
CLK_SMBCLK

2

+1.8V +1.8V

JDIM1

JDIM1

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

FOX_ASOA426-M2RN-7F

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DIMMA

1

091029 change JDIM1 to FOX_ASOA426-M2RN-7F
follow SJV03_MB_Conn_List_1029_Rev10(BTB)

DDR_A_D4
DDR_A_D5

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS#0

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

R66 10K_0402_5%R66 10K_0402_5%

1 2

R65 10K_0402_5%R65 10K_0402_5%

1 2

R64

R64

M_CLK_DDR0 <4>
M_CLK_DDR#0 <4>

1 2

DDR_CKE1 <4>

DDR_A_BS1 <4>
DDR_A_RAS# <4>
DDR_CS#0 <4>

M_ODT0 <4>

M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>

0_0402_5%

0_0402_5%

PM_EXTTS#0 <5>

DDR_CKE1

DDR_A_BS2

DDR_CKE0

R163

R163

1 2

47_0402_5%

47_0402_5%
R60

R60

1 2

47_0402_5%

47_0402_5%
R59

R59

1 2

47_0402_5%

47_0402_5%

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMMA

DDRII-SODIMMA

DDRII-SODIMMA

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

7 46Wednesday, March 03, 2010

7 46Wednesday, March 03, 2010

7 46Wednesday, March 03, 2010

1

1.0

1.0

1.0

5

PCIE_CTX_GRX_P0<19>
PCIE_CTX_GRX_N0<19>

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

DIS ONLY

VDD33

(+3VSDGPU)

PEX_VDD

(+1.05VSDGPU)

D D

NVVDD

(VGA_CORE)

IFPAB_IOVDD
(+1.8VSDGPU)

FBVDDQ

(+1.5VSDGPU)

PCIE_CRX_GTX_P0<19>
PCIE_CRX_GTX_N0<19>

C C

B B

A A

DGPU_HOLD_RST#

PEX_VDD can
ramp up any time

DIS@

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PEG_CLKREQ#<13>

PLTRST#<5,19,24,25,26,31>

DGPU_HOLD_RST#<31>

PLTRST# PLTRST_VGA#

C35 100P_0402_50V8J

C35 100P_0402_50V8J

1 2

OPT@

091212 Add C35 near U87
to prevent switch noise

OPT@

5

0.1U_0402_16V7K

0.1U_0402_16V7K

C736

1 2

C735

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K

CLK_PCIE_VGA<13>

CLK_PCIE_VGA#<13>

PLTRST_VGA#

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

DIS@

DIS@

1 2

R1526 0_0402_5%

R1526 0_0402_5%

VGA@C7 36

VGA@
VGA@C7 35

VGA@

+3VSDGPU

PEG_CLKREQ#

U87

U87

2

1

OPT@

OPT@

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

CLK_PCIE_VGA
CLK_PCIE_VGA#

1 2

R694 200_0402_5% @R6 94 200_0402_5% @

1 2

R695 2.49K_0402_1% VGA@R695 2.49K_0402_1% VGA@

VGA@

VGA@

10K_0402_5%

10K_0402_5%

1 2

R696

R696

+3VS

5

P

B

4

Y

A

12

G

R1490

3

R1490
100K_0402_5%

100K_0402_5%

VGA@

VGA@

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

AB10
AC10

AF10
AE10

AG10

PLTRST_VGA#

4

U30A

U30A

AD9

AE9

N11M-GE1-S-A2 _BGA533

N11M-GE1-S-A2 _BGA533

VGA@

VGA@

Part 1 of 5

Part 1 of 5

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_TERMP

PEX_RST_N

PEX_CLKREQ_N

PCI EXPRESS

PCI EXPRESS

GPIO

GPIO

JTAG_TRST_N

TEST

TEST

I2C DACADACB

I2C DACADACB

XTAL_OUTBUFF

CLK

CLK

091216 change GPU P/N to SA00003UD00

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF
DACA_RSET

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_VREF
DACB_RSET

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

TESTMODE

I2CA_SCL
I2CA_SDA

I2CB_SCL
I2CB_SDA

I2CC_SCL
I2CC_SDA

I2CH_SCL
I2CH_SDA

I2CS_SCL

I2CS_SDA

XTAL_SSIN

XTAL_OUT

XTAL_IN

3

N1

HDMI_DETECT_VGA

G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

AD2
AD1

AE2
AD3
AE3

AF1
AE1

U6
U4

T5
R4
T4

R6
V6

AF3
AG4
AE4
AF4
AG3

AD25

R1
T3

R2
R3

A2
B1

A3
A4

T1
T2

NV_INVTPWM
VGA_ENVDD
VGA_ENBKL

1 2

R685 0_0402_5%VGA@R685 0_0402_5%VGA@

1 2

R686 0_0402_5%VGA@R686 0_0402_5%VGA@

T31T31
T32T32

VGA_GPIO11

R684 10K_0402_5%

R684 10K_0402_5%

VGA_GPIO14

R687 10K_0402_5%

R687 10K_0402_5%

T68

T68

PAD

PAD

VGA_DEEP_IDLE_R

VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

DACA_VREF
DACA_RSET

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

TESTMODE

VGA_DDCCLK_C
VGA_DDCDATA_C

I2CB_SCL
I2CB_SDA

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

HDCP_SMB_CK1
HDCP_SMB_DAI

SMB_EC_CK2_R
SMB_EC_DA2_R

1 2

1 2

R682 124_0402_1%DIS@R682 124_0402_1%DIS@

HDMI_DETECT_VGA <16>

T33T33

VGA_ENVDD <14>
VGA_ENBKL <3 1>

@

@

@

@

1 2

R825 0_0402_5%@R825 0_0402_5%@

VGA_HSYNC <15>
VGA_VSYNC <15>

VGA_CRT_R <15>
VGA_CRT_B <1 5>
VGA_CRT_G <15>

DIS@

DIS@

12

C746 0.1U_0402_16V4Z

C746 0.1U_0402_16V4Z

1 2

R693 10K_0402_5%V GA@R693 10K_0402_5%V GA@

1 2

R674 10K_0402_5%V GA@R674 10K_0402_5%V GA@

1 2

R67510K_0402_5% @R67510K_0402_5% @

R689 2.2K_0402_5%VGA@R689 2.2K_0402_5%VGA@

1 2

R688 2.2K_0402_5%

R688 2.2K_0402_5%

1 2

VGA@

VGA@

I2CS is internal thermal sensor.

D11

E9

XTALOUT

E10

XTALIN

D10

R677

R677

10K_0402_5%

10K_0402_5%

VGA@

VGA@

GPU_VID0
GPU_VID1

091105 add TestPad on GPIO8/GPIO9
Follow NV review

091026 add GPIO18 usage
VGA_DEEP_IDLE output to EC

VGA_DEEP_IDLE <31>

CRT OUT

PAD

PAD

T73

T73

PAD

PAD

T72

T72

PAD

PAD

T71

T71

PAD

PAD

T70

T70

+3VS

R814 0_0402_5%

R814 0_0402_5%

1 2

12

2.2K_0402_5%

2.2K_0402_5%

DIS@

DIS@

1 2

R815 0_0402_5%

R815 0_0402_5%

DIS@

DIS@

12

R676

R676

10K_0402_5%

10K_0402_5%

VGA@

VGA@

+3VSDGPU

VGA@

VGA@

GPU_VID0 <43>
GPU_VID1 <43>

GPU_VID0

GPU_VID1

+3VSDGPU

R683

R683

R681

R681

2.2K_0402_5%

2.2K_0402_5%

VGA@

VGA@

EC_SMB_CK2
EC_SMB_DA2

2

N10M-GS
(40nm)

N11M-GE1/LP1
(40nm)

Ball Name

GPIO0
GPIO1

GPIO2

GPIO3

GPIO4

GPIO5
GPIO6
GPIO7

GPIO8

GPIO9

C26 100P_0402_50V8J@C26 100P_0402_50V8J@

C29 100P_0402_50V8J@C29 100P_0402_50V8J@

091022 follow NV OPTIMUS D.G.

Y5

Y5

C740

C740

27P_0402_50V8J

27P_0402_50V8J

VGA@

VGA@

091124 change crystal Y5 P/N to SJ127P0M800

091124 change C740/C739 to 27PF

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

27MHZ_20P_7A27000010

27MHZ_20P_7A27000010

VGA@

VGA@

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

3

C739

C739
27P_0402_50V8J

27P_0402_50V8J

VGA@

VGA@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VGA_DDCCLK_C
VGA_DDCDATA_C

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

2

GPIO6GPIO5

Device ID

0x0A74

1

Device ID

GB1-N11x
Normal
Function

General Purpose
HPD-C

LCD0_BL_PWM

LCD0_VDD

LCD0_BL_EN

GPU_VID0
GPU_VID1
GPU_VID2

OVERT

ALERT

1 2

1 2

0x0A7D

Function Description

Hot Plug detect for IFP link C
Panel Backlight Brightness
(PWM capable)

Panel power enable
Panel Backlight on/off
(PWM Capable)

GPU_VID0
GPU_VID1
GPU_VID2
Thermal Catastrophic
Overtemp

Thermal Alert

SMB_EC_CK2_R

SMB_EC_DA2_R

1

091212 Add C26, C29 near PR241
, PR242 to prevent switch noise

2

Q47A

Q47A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

OPT@

OPT@

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

L27 MBK1608121YZF_0603DIS@L27 MBK1608121YZF_0603D IS@

1 2
1 2

L28 MBK1608121YZF_0603DIS@L28 MBK1608121YZF_0603D IS@

L31

L31

L30 MBK1608121YZF_0603DIS@L30 MBK1608121YZF_0603D IS@

1 2
1 2

DIS@

DIS@

MBK1608121YZF_0603DIS@

MBK1608121YZF_0603DIS@

1

C737

C737

C738

C738

DIS@

DIS@

2

12P_0402_50V8J

12P_0402_50V8J

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

00

1

1

00

1

1

Ball Name

GPIO10
GPIO11
GPIO12
GPIO13

GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

091217 change R678/R679 from 4.7K to 2.2K

VGA_DDCCLK_C

VGA_DDCDATA_C

VGA_LVDS_SCL_C

VGA_LVDS_SDA_C

VGA_DEEP_IDLE_R

091026 add R824 10K PU to +3VSDGPU

DGPU_PWR_EN

61

5

Q47B

Q47B

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

1

C748

C748

DIS@

DIS@

2

2

12P_0402_50V8J

12P_0402_50V8J

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N11M-OP2 PCIE,GPIO,CLK

N11M-OP2 PCIE,GPIO,CLK

N11M-OP2 PCIE,GPIO,CLK

1

VGA_COREGPU_VID00GPU_VID1

0.8V

0.85V

1.0V

VGA_COREGPU_VID00GPU_VID1

0.8V

0.85V

0.9V

GB1-N11x
Normal
Function

MEM_VREF
SLI_SYNC
PWR_LEVEL
MEM_VID

PWR_CTRL1

HPD-E
FAN_PWM
Reserved
Reserved
HPD-D

OPT@

OPT@

3

C747

C747

DIS@

DIS@

12P_0402_50V8J

12P_0402_50V8J

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

Function Description

Memory VREF switch
SLI raster sync

AC power detect input
MEM_VID or Power supply
Control

Power supply control
Hot plug detect for IFP link E
Programmable Fan control

Hot plug detect for IFP link D

R691 150_0402_1%DIS@R691 150_0402_1%DIS@

1 2

R692 150_0402_1%DIS@R692 150_0402_1%DIS@

1 2

R690 150_0402_1%DIS@R690 150_0402_1%DIS@

1 2

R678 2.2K_0402_5%VGA@R678 2.2K_0402_5%VGA@

R679 2.2K_0402_5%VGA@R679 2.2K_0402_5%VGA@

R699 2.2K_0402_5%VGA@R699 2.2K_0402_5%VGA@

R698 2.2K_0402_5%VGA@R698 2.2K_0402_5%VGA@

R824 10K_0402_5%@R824 10K_0402_5%@

12

12

12

12

12

DGPU_PWR_EN <13,31,35>

EC_SMB_CK2 <5,9,31>

EC_SMB_DA2 <5,9,31>

VGA_DDCCLK <15>

VGA_DDCDATA <15>

VGA_LVDS_SCL <14>

VGA_LVDS_SDA <14>

1

2

12P_0402_50V8J

12P_0402_50V8J

1

P-State

Deep P12

P8

P0

P-State

Deep P12

P8

P0

8 46Wednesday, March 03, 2010

8 46Wednesday, March 03, 2010

8 46Wednesday, March 03, 2010

+3VSDGPU

1.0

1.0

1.0

5

FBAA[0..13]<12>

FBBA[2..5]<12>

FBADQM[0..7]<12>

FBADQS[0..7]<12>

FBADQS#[0..7]<12>

FBA_D[0..63]<12>

U30B

D D

C C

B B

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

U30B

D22

FBA_D0

E24

FBA_D1

E22

FBA_D2

D24

FBA_D3

D26

FBA_D4

D27

FBA_D5

C27

FBA_D6

B27

FBA_D7

A21

FBA_D8

B21

FBA_D9

C21

FBA_D10

C19

FBA_D11

C18

FBA_D12

D18

FBA_D13

B18

FBA_D14

C16

FBA_D15

E21

FBA_D16

F21

FBA_D17

D20

FBA_D18

F20

FBA_D19

D17

FBA_D20

F18

FBA_D21

D16

FBA_D22

E16

FBA_D23

A22

FBA_D24

C24

FBA_D25

D21

FBA_D26

B22

FBA_D27

C22

FBA_D28

A25

FBA_D29

B25

FBA_D30

A26

FBA_D31

U24

FBA_D32

V24

FBA_D33

V23

FBA_D34

R24

FBA_D35

T23

FBA_D36

R23

FBA_D37

P24

FBA_D38

P22

FBA_D39

AC24

FBA_D40

AB23

FBA_D41

AB24

FBA_D42

W24

FBA_D43

AA22

FBA_D44

W23

FBA_D45

W22

FBA_D46

V22

FBA_D47

AA25

FBA_D48

W27

FBA_D49

W26

FBA_D50

W25

FBA_D51

AB25

FBA_D52

AB26

FBA_D53

AD26

FBA_D54

AD27

FBA_D55

V25

FBA_D56

R25

FBA_D57

V26

FBA_D58

V27

FBA_D59

R26

FBA_D60

T25

FBA_D61

N25

FBA_D62

N26

FBA_D63

N11M-GE1-S-A2 _BGA533

N11M-GE1-S-A2 _BGA533

VGA@

VGA@

FBAA[0..13]

FBBA[2..5]

FBADQM[0..7]

FBADQS[0..7]

FBADQS#[0..7]

FBA_D[0..63]

Part 2 of 5

Part 2 of 5

MEMORY INTERFACE

MEMORY INTERFACE

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

FBAA4

F26

FBARAS#

J24

FBAA5

F25

FBA_BA1

M23

FBBA2

N27

FBBA4

M27

FBBA3

K26
J25

FBBACS0#

J27

FBAA11

G23

FBACAS#

G26

FBAWE#

J23

FBA_BA0

M25

FBBA5

K27

FBAA12

G25

FBA_RST

L24

FBAA7

K23

FBAA10

K24
G22

FBAA0

K25

FBAA9

H22

FBAA6

M26

FBAA2

H24

FBAA8

F27

FBAA3

J26

FBAA1

G24

FBAA13

G27

FBA_BA2

M24

FBBAODT0

K22

FBAACS0#

J22

FBAAODT0

L22

FBADQM0

C26

FBADQM1

B19

FBADQM2

D19

FBADQM3

D23

FBADQM4

T24

FBADQM5

AA23

FBADQM6

AB27

FBADQM7

T26

FBADQS#0

D25

FBADQS#1

A18

FBADQS#2

E18

FBADQS#3

B24

FBADQS#4

R22

FBADQS#5

Y24

FBADQS#6

AA27

FBADQS#7

R27

FBADQS0

C25

FBADQS1

A19

FBADQS2

E19

FBADQS3

A24

FBADQS4

T22

FBADQS5

AA24

FBADQS6

AA26

FBADQS7

T27

FB_VREF1

A16

F24
F23

N24
N23

M22

10K_0402_5%VGA@

10K_0402_5%VGA@

1 2

100112 change Q73 P/N from SB00000AR00 to SB00000DH00

change Q73,Q74,R821 from mount to @

EC_SMB_CK2<5,8,31>

A A

EC_SMB_DA2<5,8,31>

5

EC_SMB_CK2

EC_SMB_DA2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

@

@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

FBARAS# <12>

FBA_BA1 <12>

FBBA_CKE

FBBACS0# <12>

FBACAS# <12>
FBAWE# <1 2>
FBA_BA0 <12>

FBAA12 <12>

FBAA_CKE

12

R614

R614
10K_0402_5%

10K_0402_5%

VGA@

VGA@

FBAACS0# <12>

12

R607

R607
10K_0402_5%

10K_0402_5%

VGA@

VGA@

FBAA_CKE <12>

FBAAODT0 <12>

1.27V~0.9V

FBACLK0 <12>
FBACLK0# <12>

FBACLK1 <12>
FBACLK1# <12>

R615

R615

Q73A

Q73A

Q73B

Q73B

DGPU_PWRGD#

2

DGPU_PWRGD#

5

4

61

@

@

3

+1.5VSDGPU

VGA_HDMI_SCL <16>

VGA_HDMI_SDA <16>

091022 add for OPTIMUS

4

12

R613

R613
10K_0402_5%

10K_0402_5%

VGA@

VGA@

12

R608

R608
10K_0402_5%

10K_0402_5%

VGA@

VGA@

12

R609

R609
10K_0402_5%

10K_0402_5%

VGA@

VGA@

3

VGA_LVDS_ACLK

VGA_LVDS_ACLK#

2

2

C757

1

100K_0402_5%

100K_0402_5%

12

C757
12P_0402_50V8J

12P_0402_50V8J

1

@

@

VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#

IFPC_AUX
IFPC_AUX_N

+3VS

R821

R821

@

@

1 2

13

D

D

2

G

G

S

S

U30C

U30C

AC4

IFPA_TXC

AD4

IFPA_TXC_N

V5

IFPA_TXD0

V4

IFPA_TXD0_N

AA5

IFPA_TXD1

AA4

IFPA_TXD1_N

W4

IFPA_TXD2

Y4

IFPA_TXD2_N

AB4

IFPA_TXD3

AB5

IFPA_TXD3_N

AB3

IFPB_TXC

AB2

IFPB_TXC_N

W1

IFPB_TXD4

V1

IFPB_TXD4_N

W3

IFPB_TXD5

W2

IFPB_TXD5_N

AA2

IFPB_TXD6

AA3

IFPB_TXD6_N

AB1

IFPB_TXD7

AA1

IFPB_TXD7_N

G4

IFPC_AUX_I2CW_SCL

G5

IFPC_AUX_I2CW_SDA_N

P4

IFPC_L0

N4

IFPC_L0_N

M5

IFPC_L1

M4

IFPC_L1_N

L4

IFPC_L2

K4

IFPC_L2_N

H4

IFPC_L3

J4

IFPC_L3_N

D3

IFPD_AUX_I2CX_SCL

D4

IFPD_AUX_I2CX_SDA_N

F5

IFPD_L0

F4

IFPD_L0_N

E4

IFPD_L1

D5

IFPD_L1_N

C3

IFPD_L2

C4

IFPD_L2_N

B3

IFPD_L3

B4

IFPD_L3_N

F7

IFPE_AUX_I2CY_SCL

G6

IFPE_AUX_I2CY_SDA_N

D6

IFPE_L0

C6

IFPE_L0_N

A6

IFPE_L1

A7

IFPE_L1_N

B6

IFPE_L2

B7

IFPE_L2_N

E6

IFPE_L3

E7

IFPE_L3_N

N11M-GE1-S-A2 _BGA533

N11M-GE1-S-A2 _BGA533

VGA@

VGA@

091216 change GPU P/N to SA00003UD00

Q74

Q74
SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

@

@

FBBA_CKE <12>

FBA_RST < 12>

FBA_BA2 <12>
FBBAODT0 <12>

10mil

1

C634

C634

0.01U_0402_16V7K

0.01U_0402_16V7K

@

@

2

DGPU_PWRGD<16,31>

HDMI

LVDS

VGA_HDMI_TX2+<16>
VGA_HDMI_TX2-<16>
VGA_HDMI_TX1+<16>
VGA_HDMI_TX1-<16>
VGA_HDMI_TX0+<16>
VGA_HDMI_TX0-<16>
VGA_HDMI_CLK+<16>
VGA_HDMI_CLK-<16>

+1.5VSDGPU

12

R619

R619

1.3K_0402_1%

1.3K_0402_1%

@

@

12

R618

R618

1.3K_0402_1%

1.3K_0402_1%

@

@

C756

C756

12P_0402_50V8J

12P_0402_50V8J

VGA_LVDS_ACLK<14>
VGA_LVDS_ACLK#<14>

VGA_LVDS_A0<14>
VGA_LVDS_A0#<14>
VGA_LVDS_A1<14>
VGA_LVDS_A1#<14>
VGA_LVDS_A2<14>
VGA_LVDS_A2#<14>

DGPU_PWRGD

R822

R822

22K_0402_5%

22K_0402_5%

VGA@

VGA@

@

@

DGPU_PWRGD#

20100123 change R822 from OPT@ to VGA@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Part 3 of 5

Part 3 of 5

4.7K_0402_5%

4.7K_0402_5%

IFPC_AUX

4.7K_0402_5%

4.7K_0402_5%

IFPC_AUX_N

2

VGA@

VGA@

VGA@

VGA@

LVDS / TMDS

LVDS / TMDS

R652

R652

R654

R654

NCRFU

NCRFU

GENERAL STRAPSERIAL

GENERAL STRAPSERIAL

+3VSDGPU

+3VSDGPU

C15

NC

D15

NC

J5

NC

T6

RFU_1

W6

RFU_2

Y6

RFU_3

AA6

RFU_4

N3

RFU_5

STRAP0

C7

STRAP0

STRAP1

STRAP2

BUFRST_N

THERMDN

THERMDP

CEC

SPDIF

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET

IFPD_RSET

IFPE_RSET

DGPU_PWRGD

2

1 2

Q38A

Q38A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

VGA@

VGA@

5

Q38B

Q38B

1 2

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5V PULL UP IN CONNECTER SIDE

B9

A9

N5

D8

D9

N2

F9

B10

C9

A10

C10

AB6

R5

M6

F8

61

DGPU_PWRGD

VGA@

VGA@

3

STRAP1

STRAP2

PAD

PAD

T65

T65

PAD

PAD

T66

T66

PAD

PAD

T67

T67

SPDIF_IN

1 2

R620 36K_0402_5%

R620 36K_0402_5%

ROM_SCLK

ROM_SI

ROM_SO

1 2

R625 1K_0402_1%@R625 1K_0402_1%@

1 2

R621 1K_0402_1%VGA@R621 1K_0402_ 1%VGA@

1 2

R622 1K_0402_1%@R622 1K_0402_1%@

1 2

R649 1K_0402_1%@R649 1K_0402_1%@

+3VSDGPU

VGA@

VGA@

VGA_HDMI_SCL <16>

VGA_HDMI_SDA <16>

STRAP0 <11>

STRAP1 <11>

STRAP2 <11>

12

R634

R634
10K_0402_5%

10K_0402_5%

VGA@

VGA@

+3VSDGPU

ROM_SCLK < 11>

ROM_SI <11>

ROM_SO <11>

1

100112 change Q38 P/N from SB00000AR00 to SB00000DH00

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N11M-OP2 LVDS,Memory Bus

N11M-OP2 LVDS,Memory Bus

N11M-OP2 LVDS,Memory Bus

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1

12

R640

R640
10K_0402_5%

10K_0402_5%

VGA@

VGA@

1.0

1.0

9 46Wednesday, March 03, 2010

9 46Wednesday, March 03, 2010

9 46Wednesday, March 03, 2010

1.0

5

NEAR BGA

VGA_CORE

NEAR BALL

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

C619

C619

VGA@

D D

2

VGA@

0.1U_0402_10V7K

0.1U_0402_10V7K

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

N10M-GS: 15.8A
N11M-GE1:16.7A

091022 add C804 330U for VGA_CORE

1

2

C658

C658

VGA@

VGA@

1

2

1

2

C661

C661

VGA@

VGA@

+3VSDGPU

1

C665

C665

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C694

C694

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C657

C657

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

5

1U_0402_6.3V6K

1U_0402_6.3V6K

C690

C690

VGA@

VGA@

C689

C689

VGA@

VGA@

0.1U_0402_10V7K

0.1U_0402_10V7K

C660

C660

VGA@

VGA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

1

2

NEAR BALL

C C

120mA

NEAR BGA

NEAR BGA

+1.8VSDGPU

L33

L33

MBK1608121YZF_0603

MBK1608121YZF_0603

1 2

VGA@

VGA@

300mA

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

B B

NEAR BGA

+1.05VSDGPU

L22

L22

MBK1608121YZF_0603

MBK1608121YZF_0603

1 2

VGA@

VGA@

285mA

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

NEAR BGA

+3VSDGPU

A A

L24

VGA@L24

VGA@

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

220mA

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

0.047U_0402_25V7K

0.047U_0402_25V7K

1

C641

C641

VGA@

VGA@

2

0.047U_0402_25V7K

0.047U_0402_25V7K

1

+

+

C804

C804

VGA@

VGA@

2

0.047U_0402_25V7K

0.047U_0402_25V7K

NEAR BALL

1

C679

C679

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

NEAR BALL

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C692

C692

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C688

C688

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

NEAR BALL

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C662

C662

C656

C656

VGA@

VGA@

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

C652

C652

C653

C653

VGA@

VGA@

VGA@

VGA@

2

2

1

2

1

2

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C630

C629

C629

VGA@

VGA@

C632

C632

VGA@

VGA@

C627

C627

VGA@

VGA@

0.1U_0402_10V7K

0.1U_0402_10V7K

C635

C635

VGA@

VGA@

1

2

1

2

1

2

C630

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C628

C628

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C643

C643

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C646

C646

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

C693

C693

VGA@

VGA@

C687

C687

VGA@

VGA@

091212 Add C712 for +IFPC_IOVDD

1

C712

C712

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C651

C651

C717

C717

VGA@

VGA@

VGA@

VGA@

2

091212 Add C717 for +SP_PLLVDD

4

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C631

C631

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C622

C622

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C642

C642

VGA@

VGA@

2

1

C645

C645

VGA@

VGA@

2

+3VSDGPU

+IFPC_PLLVDD

4

+IFPA_IOVDD

+IFPA_IOVDD

+IFPC_IOVDD

+IFPDE_IOVDD

12

R62310K _0402_5%

R62310K _0402_5%

VGA@

VGA@

+IFPAB_PLLVDD

+IFPC_PLLVDD

1 2

R628 0_0402_5%

R628 0_0402_5%

+1.05VSDGPU

+IFPD_PLLVDD

VGA@

VGA@

@

12

R62710K_0402_5%@R62710K_0402_5%

+IFPE_PLLVDD

VGA@

VGA@

12

R62410K_0402_5%

R62410K_0402_5%

NEAR BGA

L23

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

220mA

J10
J12
J13

M11
M17

N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17

R11
R12
R13
R14
R15
R16
R17

T11
T17

U19

W9
W10
W12
W13
W18
W19

A12
B12
C12
D12
E12
F12

AG9

AD5

VGA@L23

VGA@

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

U30D

U30D

J9

L9

M9

N9

R9

T9

U9

V3

V2

J6

H6

P6

N6

D7

N11M-GE1-S-A2 _BGA533

N11M-GE1-S-A2 _BGA533

VGA@

VGA@

091216 change GPU P/N to
SA00003UD00

1

C663

C663

VGA@

VGA@

2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

PEX_SVDD_3V3

IFPA_IOVDD

IFPB_IOVDD

IFPC_IOVDD

IFPDE_IOVDD

IFPAB_PLLVDD

IFPC_PLLVDD

IFPD_PLLVDD

IFPE_PLLVDD

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C659

C659

VGA@

VGA@

2

Part 4 of 5

Part 4 of 5

3

PLACE UNDER GPU

A13

FBVDDQ

B13

FBVDDQ

C13

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

POWER

POWER

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_PLLVDD

VID_PLLVDD

SP_PLLVDD

PLLVDD

FB_PLLAVDD

FB_PLLAVDD

FB_DLLAVDD

DACA_VDD

DACB_VDD

FB_CAL_PD_VDDQ

VDD_SENSE

VDD_SENSE

D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

AG7
AF7
AE7
AD8
AD7
AC9

AF9

K6

+SP_PLLVDD

L6

K5

R19

AC19

T19

AG2

W5

B15

W15

E15

NEAR BALL

+3VSDGPU

+PEX_PLLVDD

+DACA_VDD

+DACB_VDD

R637 40.2_0402_1%VGA@R637 40.2_0402_1%VGA@

0.01U_0402_16V7K

0.01U_0402_16V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

R626 10K_ 0402_5%VGA@R626 10K _0402_5%VGA@

120mA

1

C678

C678

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

+IFPAB_PLLVDD

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

3

+DACA_VDD

NEAR BALL NEAR BGA

1

2

470P_0402_50V7K

470P_0402_50V7K

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C621

C621

VGA@

VGA@

2

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C648

C648

VGA@

VGA@

2

1

C650

C650

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

1

2

1

C644

C644

VGA@

VGA@

2

NEAR BALL

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C637

C637

VGA@

VGA@

2

NEAR BALL NEAR BGA

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C638

C638

VGA@

VGA@

2

NEAR BALL

0.1U_0402_10V7K

+1.05VS_PLL

12~16mil

+FB_PLLAVDD

The power is base on VRAM type.

C702

C702

VGA@

VGA@

0.1U_0402_10V7K

1

1

C714

C714

VGA@

VGA@

2

2

0.1U_0402_10V7K

091212 Add C714 for +1.05VS_PLL

0104 Modify FB_CAL_PD_VDDQ connect from +1.5VS to +1.5VSDGPU

1 2

+VGASENSE

4700P_0402_25V7K

4700P_0402_25V7K

1

2

0.1U_0402_10V7K

+1.5VSDGPU

+VGASENSE <43>

+FB_PLLAVDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C699

C701

C701

VGA@

VGA@

C699

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0.047U_0402_25V7K

0.047U_0402_25V7K

1

C620

C620

VGA@

VGA@

2

NEAR BGA

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C649

C649

VGA@

VGA@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C681

C681

VGA@

VGA@

2

+SP_PLLVDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1

C695

C695

VGA@

VGA@

2

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

C633

C633

VGA@

VGA@

2

0.047U_0402_25V7K

0.047U_0402_25V7K

1

C664

C664

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C640

C640

VGA@

VGA@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C682

C682

VGA@

VGA@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C716

C716

VGA@

VGA@

2

NEAR BGA

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1

C700

C700

VGA@

VGA@

2

2

NEAR BGA

1U_0402_6.3V6K

1U_0402_6.3V6K

NEAR BGA

1

2

C623

C623

VGA@

VGA@

0.047U_0402_25V7K

0.047U_0402_25V7K

1

C624

C624

C625

C625

VGA@

VGA@

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

C626

C626

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

C639

C639

VGA@

VGA@

2

1

C636

C636

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

MBK1608121YZF_0603

MBK1608121YZF_0603

1

1

C655

C655

C683

C683

VGA@

VGA@

VGA@

VGA@

2

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

C654

C654

C685

C685

VGA@

VGA@

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

C617

C617

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C698

C698

VGA@

VGA@

2

1

CLOSE TO GPU

+1.5VSDGPU

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

1

N10M-GS: 2.63A

C618

C618

VGA@

VGA@

N11M-GE1:2.55A

2

+1.05VSDGPU

2A

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C706

C706

VGA@

VGA@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+1.05VSDGPU

1

C708

C708

VGA@

VGA@

2

1

C647

C647

VGA@

VGA@

2

1

1

C709

C709

C707

C707

VGA@

VGA@

VGA@

VGA@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C710

C710

VGA@

VGA@

2

10U_0805_6.3V6M

10U_0805_6.3V6M

120mA

L21

L21

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

VGA@

VGA@

+1.05VSDGPU

12

L29

L29

VGA@

VGA@

1

C813

C813

@

@

2

091022 add C813 22U follow NV review

+1.05VSDGPU

VID_PLLVDD=45mA
SP_PLLVDD=45mA
PLLVDD=60mA

L32

L32

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

VGA@

VGA@

091212 Add C716 for +SP_PLLVDD

L20

L20

1 2

MBK1608121YZF_0603

MBK1608121YZF_0603

VGA@

VGA@

+1.05VSDGPU

+1.05VSDGPU

FB_PLLVDD=100mA
FB_DLLVDD=100mA

L34

L34

MBK1608121YZF_0603

MBK1608121YZF_0603

1

C703

C703

VGA@

VGA@

2

4.7U 6.3V K X5R 0603

4.7U 6.3V K X5R 0603

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VSDGPU

12

VGA@

VGA@

120mA

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

N11M-OP2 PWR

N11M-OP2 PWR

N11M-OP2 PWR

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1

1.0

1.0

10 46Wednesday, March 03, 2010

10 46Wednesday, March 03, 2010

10 46Wednesday, March 03, 2010

1.0

5

4

3

2

1

A total of 8 signals are required for GB1 strapping this includes

2 reference signals

6 physical strapping pins

4 logical strapping bits

U30E

U30E

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

D D

C C

Place Components Close to BGA

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

W16

GND_SENSE

E14

GND_SENSE

N11M-GE1-S-A2 _BGA533

N11M-GE1-S-A2 _BGA533

VGA@

VGA@

Part 5 of 5

Part 5 of 5

FB_CAL_TERM_GND

MULTI_STRAP_REF1_GND

MULTI_STRAP_REF0_GND

GND

GND

FB_CAL_PU_GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6

A15

B16

F11

F10

R617 40.2_0402_1%VGA@R617 40.2_0402_1%VGA@

1 2

R616 60.4_0402_1%

R616 60.4_0402_1%

1 2

VGA@

VGA@

12

R635

R635

40.2K_0402_1%

40.2K_0402_1%

VGA@

VGA@

12

R636

R636

40.2K_0402_1%

40.2K_0402_1%

VGA@

VGA@

091216 change GPU P/N to SA00003UD00

Resistor
Values

5Kohm

10Kohm

B B

15Kohm

20Kohm

25Kohm

30Kohm

35Kohm

45Kohm

Pull-up to VDD

1000

1001

1010

1011

1100

1101

1110

1111

Pull-down to GND

0000

0001

0010

0011

0100

0101

0110

0111

SUB_VENDOR

0

No VBIOS ROM (Default)

*

1

BIOS ROM is present

Panel USER Straps

User[3:0]

EDID used

*

Customer defined

FB_0_BAR_SIZE

0

*

256MB (Default)

1

Reserved

PEX_PLL_EN_TERM

0

*

Disable (Default)

1

Enable

XCLK_417

0

*

277MHz (Default)

1

Reserved

SMBUS_ALT_ADDR

0

*

0x9E (Default)

1

0x9C (Multi-GPU usage)

VGA_DEVICE

0

3D Device

1

*

VGA Device (Default)

3GIO_PADCFG

3GIO_PADCFG[3:0]

0110

A total of 24 logical strapping bits are available

+3VSDGPU

12

R646

R646

VGA@

VGA@

STRAP2<9>
STRAP1<9>
STRAP0<9>
ROM_SCLK<9>
ROM_SI<9>
ROM_SO<9>

STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO

12

R647

R647

@

@

FB Memory (DDR3)

LP1
(0x0A7D)
40nm

Samsung
800MHz
(defaul)

Hynix
800MHz

Physical
Strapping
Pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

N11M-GE1
LP1

K4W1G1646E-HC12

H5TQ1G63BFR-12C

Power
Rail

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

Memory/PKG

DDR3

Must be used 1% resister for driver calibration

*

Notebook Default

R642

R642

45.3K_0402_1%

45.3K_0402_1%

VGA@

VGA@

30K_0402_1%

30K_0402_1%

12

12

12

@

@

R644

R644

R643

R643

R645

R645

VGA@

VGA@

45.3K_0402_1%

45.3K_0402_1%

34.8K_0402_1%

34.8K_0402_1%

12

R648

R648

@

@

10K_0402_5%

34.8K_0402_1%

34.8K_0402_1%

10K_0402_5%

ROM_SO

PD 10K

12

12

R630

R630

@

@

R629

R629

VGA@

VGA@

15K_0402_1%

15K_0402_1%

12

12

R641

R641

R639

R639

@

@

@

@

15K_0402_1%

15K_0402_1%

2K_0402_5%

2K_0402_5%

12

12

R642

R642

R638

R638

SAM@

SAM@

VGA@

VGA@

20K_0402_1%

20K_0402_1%

STRAP1 use for 3GIO_PADCFG to set 35K pull up.
(PUN-04335-001_V10 HW9 update)

15K_0402_1%

15K_0402_1%

HY@

HY@

2K_0402_5%

2K_0402_5%

10K_0402_5%

10K_0402_5%

ROM_SIROM_SCLK STRAP0STRAP1STRAP2GPU

PD 15K

PD 15K

PD 15K64Mx16

PU 45K

PU 45K

X76

Logical
Strapping
Bit 3

XCLK_417

PCI_DEVID[4]

Logical
Strapping
Bit 2

Logical
Strapping
Bit 1

Logical
Strapping
Bit 0

FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE

SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM

RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]

USER[3] USER[2] USER[1] USER[0]

+1.5VS

FB_CAL_PU_GND FBCAL_PD_VDDQ

40.2 ohm

FBCAL_TERM_GNDFBVDDQ

40.2/60.4 ohm40.2 ohm

DG-04642-001-V01(May 22, 2009)

PU 35KN11M-GE1

PU 35K

PU 45KPD 10K PD 20K64Mx16

PU 45K

SLOT_CLOCK_CFG

0

*

A A

GPU and MCH don't share a common reference cloc k

1

GPU and MCH share a common reference clock (Default)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N11M-OP2 GND & STRAP

N11M-OP2 GND & STRAP

N11M-OP2 GND & STRAP

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

11 46Wednesday, March 03, 2010

11 46Wednesday, March 03, 2010

11 46Wednesday, March 03, 2010

1

1.0

1.0

1.0

5

N10x 40nm DDR3 MAPPING
NVIDIA COCUMENT FOR DA-3978 -001

FBAA[0..13]<9>

FBBA[2..5]<9>

FBADQM[0..7]<9>

FBADQS[0..7]<9>

FBADQS#[0..7]<9>

FBA_D[0..63]<9>

D D

C C

B B

A A

FBAA[0..13]

FBBA[2..5]

FBADQM[0..7]

FBADQS[0..7]

FBADQS#[0..7]

FBA_D[0..63]

FBA_BA0<9>
FBA_BA1<9>
FBA_BA2<9>

FBACLK0<9>
FBACLK0#<9>
FBAA_CKE<9>

FBAAODT0<9>
FBAACS0#<9>
FBARAS#<9>
FBACAS#<9>
FBAWE#<9>

FBA_RST<9>

+VRAM_VREFB

+VRAM_VREFA

R605

R605
240_0402_1%

240_0402_1%

VGA@

VGA@

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

FBA_BA0
FBA_BA1
FBA_BA2

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

FBADQS1
FBADQS3

FBADQM1
FBADQM3

FBADQS#1
FBADQS#3

FBA_RST

12

FBACLK0

FBACLK0#

FBACLK1

FBACLK1#

FBAA_CKE

U33

U33

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL
SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12

K4W1G1646E-HC12

SAM@

SAM@

U33

U33

H5TQ1G63BFR-12C

H5TQ1G63BFR-12C

HY@

HY@

VGA@

VGA@

243_0402_1%

243_0402_1%
R633

R633

1 2

12

R606

R606
243_0402_1%

243_0402_1%

VGA@

VGA@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

4

+VRAM_VREFB

+VRAM_VREFA

FBA_D9

E4

FBA_D14

F8

FBA_D8

F3

FBA_D12

F9

FBA_D10

H4

FBA_D13

H9

FBA_D11

G3

FBA_D15

H8

FBA_D24

D8

FBA_D30

C4

FBA_D26

C9

FBA_D29

C3

FBA_D28

A8

FBA_D25

A3

FBA_D27

B9

FBA_D31

A4

+1.5VSDGPU

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2
B10
D2
D9
E3
E9
F10
G2
G10

1

3

R612

R612
240_0402_1%

240_0402_1%

VGA@

VGA@

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

FBA_BA0
FBA_BA1
FBA_BA2

FBACLK0

FBAA_CKE

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

FBADQS2
FBADQS0

FBADQM2
FBADQM0

FBADQS#2
FBADQS#0

FBA_RST

12

K10

J10

L10

A11

T11

+1.5VSDGPU

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C615

C615

VGA@

VGA@

VGA@

VGA@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

+1.5VSDGPU

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

VGA@

VGA@

VGA@

VGA@

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.5VSDGPU

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

VGA@

VGA@

VGA@

VGA@
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

U32

U32

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK
CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1
NC/CE1
NCZQ1

A1

NC
NC

T1

NC
NC

100-BALL

100-BALL
SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12

K4W1G1646E-HC12

SAM@

SAM@

1

C697

C697

2

C696

C696

C691

C691

1

VGA@

VGA@
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C674

C674

C705

C705

1

VGA@

VGA@
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

U32

U32

H5TQ1G63BFR-12C

H5TQ1G63BFR-12C

HY@

HY@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C675

C675

VGA@

VGA@

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C614

C614

C602

C602

1

1

VGA@

VGA@

VGA@

VGA@
2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C607

C607

C606

C606

1

1

VGA@

VGA@

VGA@

VGA@

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

E4

DQL0

F8

DQL1

F3

DQL2

F9

DQL3

H4

DQL4

H9

DQL5

G3

DQL6

H8

DQL7

D8

DQU0

C4

DQU1

C9

DQU2

C3

DQU3

A8

DQU4

A3

DQU5

B9

DQU6

A4

DQU7

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2

VDDQ

A9

VDDQ

C2

VDDQ

C10

VDDQ

D3

VDDQ

E10

VDDQ

F2

VDDQ

H3

VDDQ

H10

VDDQ

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2

VSSQ

B10

VSSQ

D2

VSSQ

D9

VSSQ

E3

VSSQ

E9

VSSQ

F10

VSSQ

G2

VSSQ

G10

VSSQ

1

C600

C600

VGA@

VGA@

VGA@

VGA@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C684

C684

1

1

VGA@

VGA@

VGA@

VGA@

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C612

C612

1

1

VGA@

VGA@

VGA@

VGA@
2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

FBA_D21
FBA_D18
FBA_D20
FBA_D16
FBA_D22
FBA_D19
FBA_D23
FBA_D17

FBA_D4
FBA_D1
FBA_D5
FBA_D2
FBA_D6
FBA_D0
FBA_D7
FBA_D3

+1.5VSDGPU

+1.5VSDGPU

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C603

C603

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C680

C680

C673

C673

1

VGA@

VGA@
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C609

C609

C611

C611

1

VGA@

VGA@
2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

3

+VRAM_VREFD

+VRAM_VREFC

U31

U31

M9

VREFCA

H2

2

0

091126 swap nets for layout 091026 swap nets for layout

FBACLK1<9>
FBACLK1#<9>

FBBA_CKE<9>

FBBAODT0<9>
FBBACS0#<9>

10P_0402_50V8J

10P_0402_50V8J

1

1

C805

@C805

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C677

C677

1

1

VGA@

VGA@

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C610

C610

1

1

VGA@

VGA@
2

2

@

2

C704

C704

C806

C806

1

@

@

2

10P_0402_50V8J

10P_0402_50V8J

C613

C613

C807

C807

1

@

@

2

10P_0402_50V8J

10P_0402_50V8J

VGA@

VGA@

1

VGA@

VGA@
2

1

VGA@

VGA@
2

C604

C604

C676

C676

C608

C608

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

FBA_BA0
FBA_BA1
FBA_BA2

FBACLK1
FBACLK1#FBACLK0#

FBBA_CKE

FBBAODT0
FBBACS0#

FBARAS#
FBACAS#
FBAWE#

FBADQS4
FBADQS7

FBADQM4
FBADQM7

FBADQS#4
FBADQS#7

FBA_RST

12

R600

R600
240_0402_1%

240_0402_1%

VGA@

VGA@

091020 reserve C805/C806/C807
10P for RF solution

+1.5VSDGPU

1

VGA@

VGA@

+

+

2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL
SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12

K4W1G1646E-HC12

SAM@

SAM@

R611

R611

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

R610

R610

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

R602

R602

1.33K_0402_1%

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

1.33K_0402_1%

VGA@

C672

C672

VGA@

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

R601

R601

2

+VRAM_VREFD

+VRAM_VREFC

U34

FBA_D37

E4

DQL0

FBA_D36

F8

DQL1

FBA_D35

F3

DQL2

FBA_D32

F9

DQL3

FBA_D39

H4

DQL4

H9

DQL5

FBA_D38

G3

DQL6

FBA_D33

H8

DQL7

FBA_D61

D8

DQU0

FBA_D62

C4

DQU1

FBA_D56

C9

DQU2

FBA_D63

C3

DQU3

FBA_D58

A8

DQU4

FBA_D57

A3

DQU5

FBA_D59

B9

DQU6

FBA_D60

A4

DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSDGPU

+1.5VSDGPU +1.5VSDGPU

+1.5VSDGPU

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

U31

U31

H5TQ1G63BFR-12C

H5TQ1G63BFR-12C

HY@

HY@

12

+VRAM_VREFA +VRAM_VREFB

15MIL 15MIL

12

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C616

C616

VGA@

VGA@

2

12

+VRAM_VREFC +VRAM_VREFD

15MIL 15MIL

12

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C605

C605

VGA@

VGA@

2

FBAA0
FBAA1

4 5

FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11

7 6

FBAA12
FBAA13

FBA_BA0
FBA_BA1
FBA_BA2

FBACLK1
FBACLK1#
FBBA_CKE

FBBAODT0
FBBACS0#
FBARAS#
FBACAS#
FBAWE#

FBADQS5
FBADQS6

FBADQM5
FBADQM6

FBADQS#5
FBADQS#6

FBA_RST

12

R651

R651
240_0402_1%

240_0402_1%

VGA@

VGA@

U34

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

K4W1G1646E-HC12

K4W1G1646E-HC12

SAM@

SAM@

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

1.33K_0402_1%

1.33K_0402_1%

VGA@

VGA@

100-BALL

100-BALL
SDRAM DDR3

SDRAM DDR3

R604

R604

R603

R603

R653

R653

R650

R650

+1.5VSDGPU

12

12

12

12

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1

C601

C601

2

1

C686

C686

2

FBA_D42

E4

FBA_D46

F8

FBA_D40

F3

FBA_D45

F9

FBA_D41

H4

FBA_D47FBA_D34

H9

FBA_D44

G3

FBA_D43

H8

FBA_D50

D8

FBA_D53

C4

FBA_D48

C9

FBA_D52

C3

FBA_D51

A8

FBA_D54

A3

FBA_D49

B9

FBA_D55

A4

+1.5VSDGPU

B3
D10
G8
K3
K9
N2
N10
R2
R10

+1.5VSDGPU

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

U34

U34

H5TQ1G63BFR-12C

H5TQ1G63BFR-12C

HY@

HY@

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

VGA@

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

N11M-OP2 VRAM DDR3

N11M-OP2 VRAM DDR3

N11M-OP2 VRAM DDR3

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1

12 46Wednesday, March 03, 2010

12 46Wednesday, March 03, 2010

12 46Wednesday, March 03, 2010

of

of

of

1.0

1.0

1.0

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

4

Change C174 C175 to 10U_0603 05/14

+3VS

R1370_0603_5%R1370_0603_5%

R138

R138

+VCCP

1 2

1 2

0_0603_5%

0_0603_5%

+3VM_CK505

47P_0402_50V8J

47P_0402_50V8J

Add C1145 C1146 C1147 for EMI 06/12

3

10U_0603_6.3V6M

1

C1145

C1145

2

47P_0402_50V8J

47P_0402_50V8J

+1.05VM_CK505

1

C1146

C1146

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

C174

C174

C175

C175

1

C172

C172

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C139

C139

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C138

C138

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C167

C167

2

1

C148

C148

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C137

C137

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C146

C146

2

2

CLK_SMBDATA

CLK_SMBCLK

091212 Add C15 C16 near Q10
to prevent switch noise

C15 100P_0402_50V8J@C15 100P_0402_50V8J@

C16 100P_0402_50V8J@C16 100P_0402_50V8J@

1

C165

C165

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1 2

1 2

1

+3VS

R72

R72

2.2K_0402_5%

2.2K_0402_5%

Q10A

Q10A

+3VS

6 1

2

5

Q10B

Q10B

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

ICH_SMBDATA<19>

ICH_SMBCLK<19>

R91

R91

2.2K_0402_5%

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

1 1 1

+3VS

R435

R435

10K_0402_5%

10K_0402_5%

1 2

CLK_EN

13

Q31

Q31

R52

R52

FSC

R76

R76

2.2K_0402_5%

2.2K_0402_5%

FSA

1 2

R69

R69
0_0402_5%

0_0402_5%

1K_0402_1%

1K_0402_1%

1 2

1 2

R119

R119
0_0402_5%

0_0402_5%

R98

R98
10K_0402_5%

10K_0402_5%

1 2

R84

R84
0_0402_5%

0_0402_5%

2

DTC115EUA_SC70-3

DTC115EUA_SC70-3

+VCCP

12

R68

@R68

@

470_0402_5%

470_0402_5%

12

12

R73

R73

1K_0402_5%

1K_0402_5%

@

@

+VCCP

12

R113

R113

@

@

470_0402_5%

470_0402_5%

12

R110

R110

@

@

0_0402_5%

0_0402_5%

+VCCP

12

R92

@R92

@

470_0402_5%

470_0402_5%

12

12

R87

R87
0_0402_5%

0_0402_5%

@

@

CLK_ENABLE#<42>

C C

Rename 06/06

CPU_BSEL0<5>

Add 1K follow
Intel check list 05/11

B B

A A

FSB

CPU_BSEL1<5>

CPU_BSEL2<5>

Follow Intel check list change to 27P 06/05

C161 27P_0402_50V8JC161 27P_0402_50V8J

C164 27P_0402_50V8JC164 27P_0402_50V8J

Reserved

Change co-lay net name to +1.5VM_CK505 07/03

CLK_48M_CR<27>

H_STP_CPU#_R

H_STP_PCI#_R

1 2

R1348 0_0603_5%

R1348 0_0603_5%

@

@

1 2

R1349 0_0603_5%R1349 0_0603_5%

C1147

C1147

1 2

C386

C386

CLK_48M_CR

10U_0603_6.3V6M

10U_0603_6.3V6M

1

47P_0402_50V8J

47P_0402_50V8J

2

@

@

22P_0402_50V8J

22P_0402_50V8J

1 2

R376 0_0402_5%R376 0_0402_5%

H_STP_CPU#<19>

H_STP_PCI#<19>

091210 add C392/C393 22P for RF team

CLK_PCI_LPC<31>

CLK_PCI_PCH<17>

+3VS+3VS +3VS

R85

R85

10K_0402_5%

10K_0402_5%

@

@

1 2

ITP_EN PCI4_SEL PCI2_TME

R89

R89

10K_0402_5%

10K_0402_5%

1 2

+1.5VM_CK505

+VCCP

+1.5VS

22P_0402_50V8J

22P_0402_50V8J

@

@

R95

R95

10K_0402_5%

10K_0402_5%

@

@

1 2

R90

R90

10K_0402_5%

10K_0402_5%

1 2

+3VS

+1.5VS

0301Change R1349,R1351 BOM structure from LOW_CLK@ to mount
0301Change R1348,R1350 BOM structure from NOR_CLK@ to @

091020 change value of
C386 from 10P to 22P

CLK_PCH_48M<19>

CLK_PCH_14M<19>

0111Change BOM Structure of C390 from @ to mount

091020 change value of C390 from 10P to 22P

+3VS

@

@

12

R1528 10K_0402_5%

R1528 10K_0402_5%

12

R1529 10K_0402_5%R1529 10K_0402_5%

CLK_PCI_LPC

12

R1289

R1289

10_0402_5%

10_0402_5%

@

@

1

C388

C388
22P_0402_50V8J

22P_0402_50V8J

@

@

2

0301 Change BOM Structure of R1289 and C388/C389/C393/C390 from NOR_CLK@ to @

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK #

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

CLK_XTAL_IN

12

Y1

Y1

14.318MHZ_16PF_7A14300083

14.318MHZ_16PF_7A14300083

CLK_XTAL_OUT

1

C1119

C1119

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

091029 add R376 0_0402_5%
for EMI solution

H_STP_CPU#

H_STP_PCI#

C389

C389

Routing the trace at least 10mil

5

4

SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C160

C160

C140

C140

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R1350 0_0402_5%@R1350 0_0402_5%@

1 2

R1351 0_0402_5%R1351 0_0402_5%

1 2

R74

R74

FSA_R

1 2

22_0402_5%

22_0402_5%
R75

R75

1 2

22_0402_5%

22_0402_5%

R104

R104

1 2

33_0402_5%

33_0402_5%

1 2

C390 22P_0402_50V8J

C390 22P_0402_50V8J

@

@

VGATE<5,19,31,42>

R801 0_0402_5%R801 0_0402_5%

1 2

R802 0_0402_5%

R802 0_0402_5%

@

@

1 2

091015 add R801/R802 0ohm

1 2

1 2

1

1

2

R71

R71

10K_0402_5%

10K_0402_5%

1 2

@

@

R77

R77

10K_0402_5%

10K_0402_5%

1 2

C393

C393
22P_0402_50V8J

22P_0402_50V8J

2

@

@

C169

C169

+1.05VM_CK505

1

2

PCI2_TME

R86

R86

33_0402_5%

33_0402_5%

R80

R80

33_0402_5%

33_0402_5%

+3VM_CK505

1

2

VDD_SRC_IO

C173

C173

0.1U_0402_16V4Z

0.1U_0402_16V4Z

FSA

FSB

FSC

CLK_EN

@

@

1 2

R371 0_0402_5%

R371 0_0402_5%

H_STP_CPU#_R

H_STP_PCI#_R

CLK_XTAL_IN

CLK_XTAL_OUT

PCI4_SEL

ITP_EN

U4

U4

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VTR_QFN72_10X10

SLG8SP556VTR_QFN72_10X10

0303 change U4 P/N from SA00003H730 to SA00003H610

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

9

SDA

10

SCL

71

CPU_0

70

CPU_0#

68

CPU_1

67

CPU_1#

LCDCLK/27M

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_7

SRC_7#

SRC_9

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#

CLKREQ_4#

CLKREQ_6#

CLKREQ_7#

CLKREQ_9#

SLKREQ_10#

CLKREQ_11#

Compal Secret Data

Compal Secret Data

Compal Secret Data

24

25

28

29

32

33

35

36

39

40

57

56

61

60

64

63

44

45

50

51

48

47

37

41

58

65

43

49

46

21

Deciphered Date

Deciphered Date

Deciphered Date

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK#/27M_SS

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

USB_1/CLKREQ_A#

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

R1487

R1487

OPT@

OPT@

1 2

+3VS

10K_0402_5%

10K_0402_5%

PEG_CLKREQ#_R

CLK_SMBDATA

CLK_SMBCLK

CLK_CPU_BCLK

CLK_CPU_BCLK#

CLK_CPU_HPLCLK

CLK_CPU_HPLCLK#

CPU_DREFCLK

CPU_DREFCLK#

CPU_SSCDREFCLK

CPU_SSCDREFCLK#

CLK_PCIE_VGA

CLK_PCIE_VGA#

CLK_PCIE_WLAN

CLK_PCIE_WLAN#

CLK_PCIE_SATA

CLK_PCIE_SATA#

CLK_PCIE_PCH

CLK_PCIE_PCH#

CLK_CPU_EXP

CLK_CPU_EXP#

CLK_PCIE_LAN

CLK_PCIE_LAN#

CLK_PCIE_WWAN

CLK_PCIE_WWAN#

Add PEG_CLKREQ# 09/10/08
PU to +3VS

PEG_CLKREQ#_R PEG_CLKREQ#

WLAN_CLKREQ#

LAN_CLKREQ#

WWAN_CLKREQ#

2

Add CLK to GPU 09/10/08

DIS@

DIS@

1 2

R804 0_0402_5%

R804 0_0402_5%

Add WW AN_CLKREQ# 05/04

1 3

CLK_SMBDATA <7,24>

CLK_SMBCLK <7,24>

CLK_CPU_BCLK <5>

CLK_CPU_BCLK# <5>

CLK_CPU_HPLCLK <5>

CLK_CPU_HPLCLK# <5>

CPU_DREFCLK <5>

CPU_DREFCLK# <5>

CPU_SSCDREFCLK <5>

CPU_SSCDREFCLK# <5>

CLK_PCIE_VGA <8>

CLK_PCIE_VGA# <8>

CLK_PCIE_WLAN <25>

CLK_PCIE_WLAN# <25>

CLK_PCIE_SATA <18>

CLK_PCIE_SATA# <18>

CLK_PCIE_PCH <19>

CLK_PCIE_PCH# <19>

CLK_CPU_EXP <4>

CLK_CPU_EXP# <4>

CLK_PCIE_LAN <26>

CLK_PCIE_LAN# <26>

CLK_PCIE_WWAN <24>

CLK_PCIE_WWAN# <24>

WLAN_CLKREQ# <25>

Add LAN_CLKREQ# 091116

LAN_CLKREQ# <26>

WWAN_CLKREQ# <24>

R1488

R1488

OPT@

OPT@

2

G

G

Q63

Q63

D

D

OPT@

OPT@

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

S

12

10K_0402_5%

10K_0402_5%

DGPU_PWR_EN <8,31,35>

PEG_CLKREQ# <8>

SRC PORT LIST

PORT

SRC1
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

LAN_CLKREQ#

WLAN_CLKREQ#

WWAN_CLKREQ#

DEVICE

CPU_SSCDREFCLK

PCIE_VGA
PCIE_WLAN
PCIE_SATA
PCIE_PCH
CPU_ITP
CLK_CPU_EXP
PCIE_LAN
PCIE_WWAN

R1530 10K_0402_5%R1530 10K_0402_5%

R121 10K_0402_5%R121 10K_0402_5%

R107 10K_0402_5%R107 10K_0402_5%

12

12

12

REQ PORT LIST

DEVICEPORT

REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Clock Generator CK505

Clock Generator CK505

Clock Generator CK505

PCIE_VGA
PCIE_WLAN

PCIE_LAN
PCIE_WWAN

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

1

13 46Wednesday, March 03, 2010

13 46Wednesday, March 03, 2010

13 46Wednesday, March 03, 2010

+3VS

1.0

1.0

1.0

5

4

3

2

1

R1182 0_0402_5%@R1182 0_0402_5%@

LCD POWER CIRCUIT

+LCDVDD

D D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

GMCH_ENVDD<5>

100K_0402_5%

100K_0402_5%

C C

12

3

Q4B

Q4B

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

@

@

R174

R174

1 2

R577

R577
150_0603_5%

150_0603_5%

5

Q4A

Q4A

VGA_ENVDD<8>

+3VALW

12

R578

R578
47K_0402_5%

47K_0402_5%

R579 47K_0402_5%R579 47K_0402_5%

61

2

R700

R700

10K_0402_5%

10K_0402_5%

DIS@

DIS@

2

G

G

12

12

13

D

D

S

S

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

DIS@

DIS@

091015 follow NTV00 Design

+3VS

W=60mils

S

S

G

G

Q3

Q3

2

AO3413_SOT23-3

AO3413_SOT23-3

D

D

2

C1108

C1108

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

Q42

Q42

1 3

1

@

@

C1106

C1106

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

2009/10/07 Add Q42 and R700 for DIS only

+LCDVDD

1

2

W=60mils

C1105

C1105

0.1U_0402_16V4Z

0.1U_0402_16V4Z

USB20_N3_1

USB20_P3_1

091103 del C1167/C1168

2

3

WCM2012F2S-900T04_0805

WCM2012F2S-900T04_0805

R1183 0_0402_5%@R1183 0_0402_5%@

0111 Change BOM Structure of L3 from @ to mount and R1182/R1183 from mount to @

12

D6

L3

L3

USB20_N3

1

2

3

1

USB20_P3USB 20_P3

4

4

12

+3VS

USB20_N3 <19>

USB20_P3 <1 9>

R807

R807

1 2

0_0603_5%

0_0603_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+CAM_VCC

C1113

C1113

USB20_P3_1 USB20_N3_1

091203 change P/N of D6 to SC300000100

1

2

D6

1

GND

VCC

2

IO1

IO2

PRTR5V0U2X_SOT143

PRTR5V0U2X_SOT143

@

@

4

+CAM_VCC

3

091020 change JUMP J1 to R807 0ohm

OPTIMUS

100112 change Q47 P/N from SB00000AR00 to SB00000DH00

GMCH_LVDS_A0<5>
GMCH_LVDS_A0#< 5>

GMCH_LVDS_A1<5>
GMCH_LVDS_A1#< 5>

CMOS & LCD/PANEL BD. Conn.

Modify JLVDS1 08/04

JLVDS1

JLVDS1

1
2
3
4
5
6
7
8

9
10
11
12
13

B B

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

ACES_88341-3000B001

ACES_88341-3000B001

CONN@

CONN@

USB20_P3_1
USB20_N3_1

DMIC_CLK_LVDS
DMIC_DATA_LVDS

LVDS_ACLK
LVDS_ACLK#

LVDS_A2
LVDS_A2#

LVDS_A1
LVDS_A1#

LVDS_A0
LVDS_A0#

LVDS_SDA
LVDS_SCL
DISPOFF#
INVTPWM

+LCDVDD_L

+LEDVDD

20100106 add R1186 connect pin1 of JLVDS1 to GND

camera

DMIC_CLK_LVDS <28>

DMIC_DATA_LVDS <28>

56P_0402_50V8

56P_0402_50V8

0111 Change BOM Structure of C1306/C1307/C1308 from @ to mount

L2

L2

FBMA-L11-160808-221LMT 0603

FBMA-L11-160808-221LMT 0603

+3VS

FBMA-L11-160808-221LMT 0603

FBMA-L11-160808-221LMT 0603

2

C1111

C1111
330P_0402_50V7K

330P_0402_50V7K

1

R11860_0402_5% R11860_0402_5%

12

R11850_0402_5%

R11850_0402_5%

12

@

@

1

C1307

C1307

2

091130 combine Digital MIC into LVDS
follow NAV50 Pin definition

LVDS_SCL

LVDS_SDA

+3VS

+CAM_VCC

091020 change value of C1109 from 220P to 1200P

INVTPWM

DISPOFF#

Change P/N from SE071100J80 to SE071560J80

+LCDVDD

L1

L1

(20 MIL)

1

C1112

C1112
100P_0402_50V8J

100P_0402_50V8J

2

1 2

R1180 2.2K_0402_5%R1180 2.2K_0402_5%

1 2

R1181 2.2K_0402_5%R1181 2.2K_0402_5%

56P_0402_50V8

56P_0402_50V8

C1109 1200P_0402_50 V7KC1109 1200P_0402_50V7K

1 2

C1156 220P_0402_50V 7KC1156 220P_0402_50V7K

56P_0402_50V8

56P_0402_50V8

B+

C1306

C1306

C1308

C1308

+3VS

1

2

+LCDVDD

1

2

GMCH_LVDS_A2<5>
GMCH_LVDS_A2#< 5>

GMCH_LVDS_ACLK<5>
GMCH_LVDS_ACLK#<5>

GMCH_LVDS_SCL<5>
GMCH_LVDS_SDA<5>

INVT_PWM<5,31>

VGA_LVDS_A0#< 9>
VGA_LVDS_A0<9>

VGA_LVDS_A1#< 9>
VGA_LVDS_A1<9>

VGA_LVDS_A2#< 9>
VGA_LVDS_A2<9>

VGA_LVDS_ACLK#<9>
VGA_LVDS_ACLK<9>

VGA_LVDS_SCL<8>
VGA_LVDS_SDA<8>

GMCH_LVDS_A0

GMCH_LVDS_A0#

GMCH_LVDS_A1

GMCH_LVDS_A1#

GMCH_LVDS_A2

GMCH_LVDS_A2#

GMCH_LVDS_ACLK
GMCH_LVDS_ACLK# LVDS_ACLK#

GMCH_LVDS_SCL
GMCH_LVDS_SDA
INVT_PWM

091202 swap A0/A0#,A1/A1#,A2/A2#,ACLK/ACLK#
nets on RP7/RP8/RP9/RP10

091209 change BOM Structure of R1500 from OPT@ to VGA@

VGA_LVDS_A0#
VGA_LVDS_A0

VGA_LVDS_A1#
VGA_LVDS_A1

VGA_LVDS_A2#
VGA_LVDS_A2

VGA_LVDS_ACLK#
VGA_LVDS_ACLK

VGA_LVDS_SCL

091202 swap A0/A0#,A1/A1#,A2/A2#,ACLK/ACLK#
nets on RP11/RP12/RP13/RP14

2 3
1 4

RP7 0_0404_4P2R_5%OPT@RP 7 0_0404_4P2R_5%OPT@

2 3
1 4

RP8 0_0404_4P2R_5%OPT@RP 8 0_0404_4P2R_5%OPT@

2 3
1 4

RP9 0_0404_4P2R_5%OPT@RP 9 0_0404_4P2R_5%OPT@

2 3
1 4

RP10 0_0404_4P2R_5%OPT@RP10 0_0404_4P2R_5%OPT@

R1498

OPT@R1498

OPT@

1 2

0_0402_5%

OPT@R1499

OPT@

1 2

VGA@R1500

VGA@

1 2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

R1499
R1500

DIS ONLY

2 3
1 4

RP11 0_0404_4P2R_5%DIS@RP11 0_0404_4P2R_5%DIS@

2 3
1 4

RP12 0_0404_4P2R_5%DIS@RP12 0_0404_4P2R_5%DIS@

2 3
1 4

RP13 0_0404_4P2R_5%DIS@RP13 0_0404_4P2R_5%DIS@

2 3
1 4

RP14 0_0404_4P2R_5%DIS@RP14 0_0404_4P2R_5%DIS@

R1514

DIS@R1514

DIS@

1 2

0_0402_5%

DIS@R1515

DIS@

1 2

0_0402_5%
0_0402_5%

0_0402_5%

R1515

LVDS_A0
LVDS_A0#

LVDS_A1
LVDS_A1#

LVDS_A2
LVDS_A2#

LVDS_ACLK

LVDS_SCL
LVDS_SDA

INVTPWM

LVDS_A0#
LVDS_A0

LVDS_A1#
LVDS_A1

LVDS_A2#
LVDS_A2

LVDS_ACLK#
LVDS_ACLK

LVDS_SCL
LVDS_SDAVGA_LVDS_SDA

LED PANEL Conn.

R1464 0_0402_5% R1464 0_0402_5%

A A

BKOFF#<31>

5

R1465 10K_0402_5% R1465 10K_0402_5%

1 2

1 2

DISPOFF#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LVDS /INVERTER

LVDS /INVERTER

LVDS /INVERTER

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

14 46Wednesday, March 03, 2010

14 46Wednesday, March 03, 2010

14 46Wednesday, March 03, 2010

1

1.0

1.0

1.0

A

B

C

D

E

Close to CRT CONN for ESD.

CRT PORT

2

3

D18

D18

2

3

D17

D17

Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615

0120 Change L12,L14,L15 P/N from SM01000AL00 to SM010032020

1

1 1

2 2

CRT_R

CRT_G

CRT_B

12

R255

R255

R253

R253

150_0402_1%

150_0402_1%

C301 0.1U_0402_16V4ZC 301 0.1U_0402_16V4Z

CRT_HSYNC

Place closed to chipset

CRT_VSYNC

12

R250

R250

150_0402_1%

150_0402_1%

1 2

C298 0.1U_0402_16V4ZC 298 0.1U_0402_16V4Z

12

1 2

150_0402_1%

150_0402_1%

+5VS

5

P

A2Y

G

3

1

C310

C310

1

U11

U11

OE#

SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

1

C308

C308

2

2

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

CRT_HSYNC_1 CRT_HSYNC_2

4

+5VS

5

1

U10

U10

P

4

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

1

C303

C303

2

CRT_VSYNC_1 CRT_VSYNC_2

L15

L15

1 2

L14

L14

1 2

L12

L12

1 2

10P_0402_50V8J

10P_0402_50V8J

1 2

R1512 39_0402_1%R1512 39_0402_1%

1 2

R1513 39_0402_1%R1513 39_0402_1%

BK1608121YZF

BK1608121YZF

BK1608121YZF

BK1608121YZF

BK1608121YZF

BK1608121YZF

C307

C307

1

2

C306

C306

10P_0402_50V8J

10P_0402_50V8J

1

1

C304

C304

2

2

1 2

BK1608LL121-T_2P

BK1608LL121-T_2P

1 2

BK1608LL121-T_2P

BK1608LL121-T_2P

10P_0402_50V8J

10P_0402_50V8J

L44

L44

L45

L45

C1304

C1304

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

091013 Add R/L/C folloew NTV00

1

2

C1305

C1305

10P_0402_50V8J

10P_0402_50V8J

PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

091202 move R249/R247 to CPU side

1

PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

RED

GREEN

BLUE

JVGA_HS

JVGA_VS

1

2

High: CRT Plugged

CRT_DET<19>

CRT_DET

CRT_DET#

+3VS

1 2

13

D

D

2

G

G

S

S

R149

R149
10K_0402_5%

10K_0402_5%

Q11

Q11
2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

DIS ONLYOPTIMUS

+5VS

GMCH_CRT_R<5>

GMCH_CRT_G<5>

GMCH_CRT_B<5>

GMCH_CRT_HSYNC<5>

3 3

GMCH_CRT_DATA<5>

GMCH_CRT_CLK<5>

GMCH_CRT_VSYNC<5>

GMCH_CRT_DATA CRT_DAT

GMCH_CRT_CLK CRT_CLK

GMCH_CRT_R

GMCH_CRT_G

GMCH_CRT_B

GMCH_CRT_HSYNC

GMCH_CRT_VSYNC

+3VS +3VSDGPU

4

Q67B

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

OPT@

OPT@

Q67A

Q67A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

R1501

OPT@R1501

OPT@

1 2

R1502

OPT@R1502

OPT@

1 2

R1503

OPT@R1503

OPT@

1 2

R1504

OPT@R1504

OPT@

1 2

R1505

OPT@R1505

OPT@

1 2

5

3

OPT@Q67B

OPT@

CRT_CLK

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

CRT_R

CRT_G

CRT_B

CRT_HSYNC

CRT_VSYNC

VGA_CRT_R<8>

VGA_CRT_G<8>

VGA_CRT_B<8>

VGA_HSYNC<8>

VGA_VSYNC<8>

VGA_DDCDATA<8>

VGA_DDCCLK< 8>

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

VGA_HSYNC

VGA_VSYNC

VGA_DDCDATA CRT_DAT

VGA_DDCCLK

R1517

DIS@R1517

DIS@

1 2

R1518

DIS@R1518

DIS@

1 2

R1519

DIS@R1519

DIS@

1 2

R1520

DIS@R1520

DIS@

1 2

R1521

DIS@R1521

DIS@

1 2

5

4

Q72B

DIS@Q72B

2

Q72A

Q72A
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

DIS@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

DIS@

DIS@

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

3

CRT_R

CRT_G

CRT_B

CRT_HSYNC

CRT_VSYNC

+CRT_VCC

W=40mils

D3

D3

2 1

RB491D_SC59-3

RB491D_SC59-3

R1103 100K_0402_5%

R1103 100K_0402_5%

1 2

20100129 add F4 for +CRT_VCC

+CRT_VCC_1

091117 Change JCRT1 Symbol to
SUYIN_070546FR015M21TZR

+CRT_VCC

F4

F4

21

1.1A_6V_SMD1812P110TF

1.1A_6V_SMD1812P110TF

RED

CRT_DAT
GREEN

JVGA_HS
BLUE

JVGA_VS

CRT_CLK
CRT_DET#

C142 0.1U_0402_16V4ZC142 0.1U_0402_16V4Z

1 2

JCRT1

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015M21TZR

SUYIN_070546FR015M21TZR

CONN@

CONN@

16

G

G

17

G

G

100112 change Q72 P/N from SB00000AR00 to SB00000DH00

4 4

GMCH_CRT_DATA

GMCH_CRT_CLK

VGA_DDCDATA

VGA_DDCCLK

OPT@

OPT@

1 2

R248 2.2K_0402_5%

R248 2.2K_0402_5%

OPT@

OPT@

1 2

R245 2.2K_0402_5%

R245 2.2K_0402_5%

@

@

1 2

R1469 4.7K_0402_5%

R1469 4.7K_0402_5%

@

@

1 2

R1470 4.7K_0402_5%

R1470 4.7K_0402_5%

A

+3VS

CRT_DAT

CRT_CLK

1 2

R251 2.2K_0402_5%R251 2.2K_0402_5%

1 2

R252 2.2K_0402_5%R252 2.2K_0402_5%

B

+CRT_VCC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/09 2010/10/09

2009/10/09 2010/10/09

2009/10/09 2010/10/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

CRT PORT

CRT PORT

CRT PORT

NAVD0 LA-6091P

NAVD0 LA-6091P

NAVD0 LA-6091P

15 46Wednesday, March 03, 2010

15 46Wednesday, March 03, 2010

15 46Wednesday, March 03, 2010

E

1.0

1.0

1.0