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Compal
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LA-6061P NWQAA
Schematic
46 pgs760.18 Kb0

Compal LA-6061P NWQAA, Satellite A665 Schematic

A
1 1
B
C
D
E
NWQAA
2 2
Marseille 10
LA-6061P SchematicREV 2.0
3 3
4 4
Intel Processor(ARD) /PCH(HM55)
2010-03-24 Rev 2.0
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
C
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
145Wednesday, March 24, 2010
145Wednesday, March 24, 2010
145Wednesday, March 24, 2010
E
2.0
2.0
2.0
of
of
of
A
B
C
D
E
Fan Control
Intel Arrandale
1 1
CRT
page 14
rPGA-989
page 5,6,7,8,9,10
FDI X8
2.7GHz
DMI X4
2.5GHz
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 800/1066/1333 MT/s
APL5607
page 6
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
USB/B Right Left USB
USB port 0,1
page 25
BT conn
USB port 5
USB
LVDS Conn.
page 13
2 2
EC SMBus
HDMI-CEC
page 15
RJ45
page 28
HDMI Conn.
page 15
RTL8105E 10/100M RTL8111E 1G
Cardreader JMB385C/389C
3 3
Level Shifter
PCIe port 1
page 28
PCIe port5
page 29
page 15
PCIe 1x
1.5V 2.5GHz(250MB/s)
PCIe 1x
1.5V 2.5GHz(250MB/s)
Intel Ibex Peak
BGA-951
page 16,17,18,19,20,21,22,23,24
LPC BUS
3.3V 33 MHz
HD Audio
5V 480MHz
USB
5V 480MHz
PCIe 1x
1.5V 2.5GHz(250MB/s)
SATA port 1
5V 3GHz(300MB/s)
SATA port 4
5V 3GHz(300MB/s)
SATA port 5
5V 3GHz(300MB/s)
USB port 3
5V 480MHz
3.3V/1.5V 24MHz
page 26
PCIeMini Card WiMax
USB port 13
page 27
PCIeMini Card WLAN
SATA HDD
SATA ODD
eSATA
SATA port 1
SATA port 4
SATA port 5
page 25
PCIe port 2
page 27
page 25
page 25
USB
USB port 3
page 25
Clock Generator
RTM890N
FingerPrinter
USB port 2
page 25
Felica
USB port 9
page 26
PCIeMini Card
3G/TV#1 TV#2
USB port 12
PCIeMini Card JET
B-CAS
page 26
PCIe port 4
page 27
page 13
page 11,12
USB port 8
page 26
Int. Camera
USB port 11
page 13
page 27
page 27
SIM
Express Card USB
USB port 4USB port 10
page 27
Express Card PCIe
PCIe port 3
page 27
Light Pipe/B LS-6061P
Cap Sensor
RTC CKT.
page 16
& Light Sensor/B LS-6062P
LED/B
DC/DC Interface CKT.
page 34
4 4
Power Circuit DC/DC
page 35,36,37,38,39,40 41,42,43
LS-6063P Audio & USB/B
LS-6064P Finger Printer/B
LS-6065P
Power On/Off CKT.
page 33
A
Power/B_FPC DA300006F00
page 33
page 33
page 33
page 25
page 26
page 33
SPI ROM (4MB)
page 16
B
Debug Port
page 32
Touch Pad
page 33
ENE KB926 D3/E0
Int.KBD
page 32
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRO NICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
page 31
EC ROM (256KB)
page 32
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
C
CIR
page 31
Compal Secret Data
Compal Secret Data
Compal Secret Data
page 26
G-Sensor
EC SMBus
Deciphered Date
Deciphered Date
Deciphered Date
page 32
MIC Conn
page 13
D
MDC 1.5 Conn
HDA Codec
ALC269
page 30
SPK ConnInt.
page 30
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
JPIO (HP & MIC)
245Tuesday, March 23, 2010
245Tuesday, March 23, 2010
245Tuesday, March 23, 2010
E
page 25
of
of
of
2.0
2.0
2.0
5
D D
C C
B B
A A
4
B+
ISL62883HRZ
ADP3211AMNR2G
APW7138NITRL
RT8209BGQW
RT8205EGQW
VR_ON
GFXVR_EN
VTTP_EN
SUSP#
RT8209BGQW
SUSP#
SUSP#
MP2121DQ
SUSP
N-CHANNEL
SI4800
SUSP
N-CHANNEL
SI4800
3
Ipeak=5A, Imax=3.5A, Iocp min=7.9
BCPWON
P-CHANNEL
AO-3413
KB_LED
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=7.7
WOL_EN#
P-CHANNEL
AO-3413
P-CHANNEL
AO-3415
P-CHANNEL
AO-3413
FELICA_PWR
P-CHANNEL
AO-3413
LCD_ENVDD
BT_PWR#
Ipeak=18A, Imax=12.6A, Iocp min=19.8
Ipeak=7A, Imax=4.9A, Iocp min=7.7
Ipeak=15A, Imax=10.5A, Iocp min=16.5
SUSP
N-CHANNEL
FDS6676AS
SUSP
N-CHANNEL
FDS6676AS
SUSP or 0.75VR_EN#
G2992F1U
2
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A
DESIGN CURRENT 5A
DESIGN CURRENT 2A
DESIGN CURRENT 4A
DESIGN CURRENT 0.5A
DESIGN CURRENT 400mA
DESIGN CURRENT 300mA
DESIGN CURRENT 1.6A
DESIGN CURRENT 5A
DESIGN CURRENT 330mA
DESIGN CURRENT 4A
DESIGN CURRENT 1.5A
DESIGN CURRENT 180mA
DESIGN CURRENT 0.5A
DESIGN CURRENT 48A
DESIGN CURRENT 15A
DESIGN CURRENT 18A
DESIGN CURRENT 7A
DESIGN CURRENT 15A
DESIGN CURRENT 2A
DESIGN CURRENT 2A
DESIGN CURRENT 1.5A
+3VL +5VL
+5VALW
+1.8VS
+5VS
+5VS_L_BCAS
+5VS_LED
+3VS_HDP
+5VS_ODD
+3VALW
+3V_LAN
+3VS
+LCD_VDD
+BT_VCC
+FLICA_VCC
+CPU_CORE
+GFX_CORE
+VTT
+1.05VS
+1.5V
+1.5V_CPU
+1.5VS
+0.75VS
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFID ENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFID ENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AN D CONTAINS CONFID ENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Power Tree
Power Tree
Power Tree
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
345Tuesday, March 23, 2010
345Tuesday, March 23, 2010
345Tuesday, March 23, 2010
1
2.0
2.0
2.0
of
of
of
A
B
C
D
E
Voltage Rails
State
S0
S1
S3
S5 S4/AC
power plane
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
( O MEANS ON X MEANS OFF )
+RTCVCC
O
O
O
O
O
O
+B
O
O
O
O
O
X
+5VL
+3VL
O
O
O
O
O
X
+5VALW
+3VALW
+VSB
O
O
O
O
X
X
+1.5V
+5VS
+3VS
+1.5VS
+VGA_CORE
+CPU_CORE
+VTT
+1.05VS
+1.8VS
+1.1VS
+0.75VS
OO
OO
O
X
XX
X
X
XX
BTO Option Table
Function
description
explain
BTO
Function
description
explain
BTO
Function
description
explain
BTO
3G TV Tuner WIMAX
3G@ TV@ WIMAX@
Felica BLUE TOOTH
Felica BLUE TOOTH G-SENSOR
Felica
FELICA@
No Power Saving
MINI PCI-E SLOT
BLUE TOOTH
BT@
S3 Power Saving
S3 Power Saving
Power Saving
SLOT1SLOT2
G-SENSOR
G-SENSOR
GSENSOR@
PS@NOPS@
LAN
LAN Fingerprint Modem CIR KB Light
10/100M Giga
8105E@ 8111E@
Camera & Mic
Camera & Mic
Camera & Mic
CAM@
New Card
New Card
New Card
NEW@
Fingerprint
Fingerprint
FP@
HDMI
HDMI
CECUMA
IHDMI@ CEC@
Modem
Modem
MDC@
JMB385C
JMB385@
KB Light
CIR
KB Light
CIR
CIR@
Card reader
JMB385C/389C
JMB389C
JMB389@
KBL@
PCH SM Bus Address
HEX
A0 H
D2 H
0001 0110 bSmart Battery
Address
1010 0000 b 1010 0100 bA4 H 1101 0010 b
EC SM Bus2 Address
PowerPower
+3VS +3VS +3VS Light Sensor
Device
G-Sensor
B
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
G3 LOW LOWLOW
96 H
1001 0110 bPCH
40 H
0100 0000 b
52 H
0101 0010 b
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SIGNAL
D
SLP_S3# SLP_S4# SLP_S5#
HIGH HIGHHIGH
HIGH HIGHHIGH
LOW
LOW LOW
HIGH
HIGH
HIGH
LOW LOWLOW
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Notes List
Notes List
Notes List
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
445Tuesday, March 23, 2010
445Tuesday, March 23, 2010
445Tuesday, March 23, 2010
E
2.0
2.0
2.0
of
of
of
Power
+3VS
3 3
+3VS +3VS +3VS +3VS +3VS Clock Generator
Device
DDR SO-DIMM 0 DDR SO-DIMM 1 Clock Generator New Card WLAN/WIMAX
3G+3VS
EC SM Bus1 Address
Device Address Address
+3VL +3VL
4 4
+3VL Cap. Sensor Virtual I2C
HDMI-CEC 34 H 0011 0100 b
A
HEX HEX
16 H
HEXDevice AddressPower
5
@
@
@
@
D D
+VTT
R10
R10 68_0402_5%
68_0402_5%
@
@
1 2
H_CPURST#
C C
+1.5V_CPU
NOPS@
NOPS@
1 2
NOPS@ R29
NOPS@
1 2
R28
R28
1.1K_0402_1%
1.1K_0402_1%
DRAMPWROK
R29 3K_0402_1%
3K_0402_1%
PS@
PS@
R29
R29 750_0402_1%
750_0402_1%
C4871000P_0402_50V7K
C4871000P_0402_50V7K
12
C4881000P_0402_50V7K
C4881000P_0402_50V7K
12
DRAMPWROK
VTTPWROK_CPU
H_THERMTRIP#<21>
H_PWRGOOD<21>
DRAMPWROK<18>
VTTPWROK_CPU<39>
BUF_PLT_RST#<20>
PECI<21>
XDP_RST#_R
PMSYNCH<18>
+VTT
Power has removed VR_TT#
+VTT
H_PWRGOOD
1 2
R1 20_0402_1%R1 20_0402_1%
1 2
R2 20_0402_1%R2 20_0402_1%
1 2
R4 49.9_0402_1%R4 49.9_0402_1%
1 2
R3 49.9_0402_1%R3 49.9_0402_1%
1 2
R18 49.9_0402_1%R18 49.9_0402_1%
1 2
R9 68_0402_5%R9 68_0402_5%
1 2
R36 1K_0402_5%R36 1K_0402_5%
TAPPWRGD
R301.5K_0402_1% R301.5K_0402_1%
750_0402_1%
750_0402_1%
T41PAD T41PAD
H_PROCHOT#_D
H_CPURST#
H_PWRGOOD1_R
12
R250_0402_5% R250_0402_5%
VTTPWROK_CPU
BUF_PLT_RST#_R
R31
R31
4
H_COMP3 H_COMP2 H_COMP1 H_COMP0
TP_SKTOCC#
CATERR#
DRAMPWROK
JCPUB
JCPUB
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
3
MISC THERMAL
MISC THERMAL
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
PM_EXT_TS#[0] PM_EXT_TS#[1]
PRDY# PREQ#
TCK TMS
TRST#
TDO
TDI_M
TDO_M
DBR#
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
TDI
A16 B16
CLK_CPU_XDP_R
AR30
CLK_CPU_XDP#_R
AT30 E16
D16 A18
A17
SM_DRAMRST#_CPU
F6
SM_RCOMP_0
AL1
SM_RCOMP_1
AM1
SM_RCOMP_2
AN1
PM_EXTTS#0
AN15
PM_EXTTS#_R
AP15
XDP_PRDY#
AT28
XDP_PREQ#
AP27
XDP_TCK
AN28
XDP_TMS
AP28
XDP_TRST#
AT27
XDP_TDI_R
AT29
XDP_TDO_R
AR27
XDP_TDI_M
AR29
XDP_TDO_M
AP29
XDP_DBRESET#
AN25
XDP_BPM#0
AJ22
XDP_BPM#1
AK22
XDP_BPM#2
AK24
XDP_BPM#3
AJ24 AJ25 AH22 AK23 AH23
2
CLK_CPU_BCLK <21>
1 2
R41 0_0402_5%@R41 0_0402_5%@
1 2
R42 0_0402_5%@R42 0_0402_5%@
CLK_CPU_BCLK# <21>
CLK_PEG <17> CLK_PEG# <17>
CLK_CPU_XDP CLK_CPU_XDP#
Unused by Clarksfield rPGA989
R6 100_0402_1%R6 100_0402_1%
1 2
R7 24.9_0402_1%R7 24.9_0402_1%
1 2
R8 130_0402_1%R8 130_0402_1%
1 2
12
R12 0_0402_5%R12 0_0402_5%
Routed as a single daisy chain
R312 1K_0402_5%R312 1K_0402_5%
XDP_PRDY# XDP_PREQ# XDP_TCK XDP_TMS XDP_TRST# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_DBRESET# XDP_DBRESET#_R
DDR3 Compensation Signals Layout Note:Please these resistors near Processor
PM_EXTTS# <11,12>
12
+3VS
XDP_DBRESET# <18>
R358 0_0402_5%
R358 0_0402_5% R359 0_0402_5%
R359 0_0402_5% R360 0_0402_5%
R360 0_0402_5% R367 0_0402_5%
R367 0_0402_5% R370 0_0402_5%
R370 0_0402_5% R371 0_0402_5%
R371 0_0402_5% R373 0_0402_5%
R373 0_0402_5% R374 0_0402_5%
R374 0_0402_5% R375 0_0402_5%
R375 0_0402_5% R390 0_0402_5%
R390 0_0402_5%
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
@
@
1 2
XDP_PRDY#_R XDP_PREQ#_R XDP_TCK_R XDP_TMS_R XDP_TRST#_R XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R
1
+VTT
PM_EXTTS#0 PM_EXTTS#_R
XDP_TDI_R XDP_TDI
XDP_TDO_M
XDP_TDI_M
XDP_TDO_R
R15 10K_0402_5%R15 10K_0402_5% R13 10K_0402_5%R13 10K_0402_5%
1 2
R20 0_0402_5%R20 0_0402_5%
1 2
R21 0_0402_5%
R21 0_0402_5%
12
R23
R23
0_0402_5%
0_0402_5%
1 2
R26 0_0402_5%
R26 0_0402_5%
1 2
R27 0_0402_5%R27 0_0402_5%
12 12
@
@
@
@
XDP_TDO
JTAG MAPPING
Scan Chain (Default)
CPU Only
GMCH Only
STUFF -> R20, R23, R27 NO STUFF -> R21, R26
STUFF -> R20, R21 NO STUFF -> R23, R26, R27
STUFF -> R26, R27 NO STUFF -> R20, R21, R23
EMI request, close to JCPU
NOPS@
PS@
PS@
R127
R127
4
NOPS@
R19 0_0402_5%
R19 0_0402_5%
S
S
12
G
G
2
12
PS@
PS@
D
D
13
Q41
Q41
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
1
C140
C140
0.047U_0402_25V6K
0.047U_0402_25V6K
PS@
PS@
2
SM_DRAMRST# <11,12>
RST_GATE <21>
XDP Connector
SFF-24Pin
JXDP
XDP_PREQ#_R XDP_PRDY#_R
XDP_BPM#0_R XDP_BPM#1_R
XDP_BPM#2_R
H_PWRGOOD TAPPWRGD
+VTT
1
C1
C1
0.1U_0402_10V6K
0.1U_0402_10V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2
@
@
R32 1K_0402_5%@R32 1K_0402_5%@
1 2 1 2
R35 0_0402_5%@R35 0_0402_5%@
12
R1451_0402_5% R1451_0402_5%
12
R11
R11
51_0402_5%
51_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
XDP_BPM#3_R H_PWRGOOD_R
TAPPWRGD_R CLK_CPU_XDP CLK_CPU_XDP#
XDP_RST#_R XDP_DBRESET#_R
XDP_TDO XDP_TRST#_R XDP_TDI XDP_TMS_R
XDP_TCK_R
2
JXDP
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MOLEX_52435-2472
MOLEX_52435-2472
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
25
23
GND
26
24
GND
@
@
Compal Electronics, I n c.
Compal Electronics, I n c.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, I n c. CPU CLK/MISC/JTAG
CPU CLK/MISC/JTAG
CPU CLK/MISC/JTAG NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
1
545Wednesday, March 24, 2010
545Wednesday, March 24, 2010
545Wednesday, March 24, 2010
of
of
of
2.0
2.0
2.0
B B
For S3 CPU Power Saving
SM_DRAMRST#_CPU
100K_0402_5%
100K_0402_5%
+3VALW
PS@
PS@
1 2
C163 0.1U_0402_16V4Z
C163 0.1U_0402_16V4Z
PS@
PS@
5
U16
VTTPWROK<34,39>
A A
VTTPWROK
5
U16
1
P
IN1
O
2
IN2
G
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
3
@
12
R840_0402_5%@R840_0402_5%
4
R33 1.5K_0402_1%
R33 1.5K_0402_1%
PS@
PS@
DRAMPWROK
5
4
3
2
1
D D
DMI_PTX_CRX_N0<18> DMI_PTX_CRX_N1<18> DMI_PTX_CRX_N2<18> DMI_PTX_CRX_N3<18>
DMI_PTX_CRX_P0<18> DMI_PTX_CRX_P1<18> DMI_PTX_CRX_P2<18> DMI_PTX_CRX_P3<18>
DMI_CTX_PRX_N0<18> DMI_CTX_PRX_N1<18> DMI_CTX_PRX_N2<18> DMI_CTX_PRX_N3<18>
DMI_CTX_PRX_P0<18> DMI_CTX_PRX_P1<18> DMI_CTX_PRX_P2<18> DMI_CTX_PRX_P3<18>
C C
B B
FDI_CTX_PRX_N0<18> FDI_CTX_PRX_N1<18> FDI_CTX_PRX_N2<18> FDI_CTX_PRX_N3<18> FDI_CTX_PRX_N4<18> FDI_CTX_PRX_N5<18> FDI_CTX_PRX_N6<18> FDI_CTX_PRX_N7<18>
FDI_CTX_PRX_P0<18> FDI_CTX_PRX_P1<18> FDI_CTX_PRX_P2<18> FDI_CTX_PRX_P3<18> FDI_CTX_PRX_P4<18> FDI_CTX_PRX_P5<18> FDI_CTX_PRX_P6<18> FDI_CTX_PRX_P7<18>
FDI_FSYNC0<18> FDI_FSYNC1<18>
FDI_INT<18> FDI_LSYNC0<18>
FDI_LSYNC1<18>
JCPUA
JCPUA
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
PEG_COMP
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]
PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]
B26 A26 B27 A25
K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31
J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30
L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26
L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
PEG_RBIAS
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0] PEG_RX#[1]
DMI Intel(R) FDI
DMI Intel(R) FDI
PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]
PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]
PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX#[15]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
1 2
R38 49.9_0402_1%R38 49.9_0402_1%
1 2
R39 750_0402_1%R39 750_0402_1%
EN_DFAN1 FAN_SPEED1
EN_DFAN1<31>
@
@
12
C339 0.1U_0402_16V7K
C339 0.1U_0402_16V7K
@
@
12
C372 0.1U_0402_16V7K
C372 0.1U_0402_16V7K
@
@
12
C373 0.1U_0402_16V7K
C373 0.1U_0402_16V7K
+FAN1
10mil
+5VS
1A
1
C5
C5 10U_0805_10V4Z
10U_0805_10V4Z
2
FAN Control Circuit
2
C3
C3
10U_0805_10V4Z
10U_0805_10V4Z
U1
U1
1
EN
GND
2
VIN
GND
3
VOUT
GND
4
VSET
GND
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
C374 0.1U_0402_16V7K
C374 0.1U_0402_16V7K
C432 0.1U_0402_16V7K
C432 0.1U_0402_16V7K
@
@
@
@
1
8 7 6 5
12
12
+FAN1
2
C4 1000P_0402_25V8J@C41000P_0402_25V8J@
1
0.01U_0402_25V7K
0.01U_0402_25V7K
JFAN
JFAN
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N
ACES_85204-0300N
@
@
R34 10K_0402_5%R34 10K_0402_5%
12
+3VS
FAN_SPEED1 <31>
C6
C6
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
3
For ESD request at PVT
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
CPU DMI/FDI/PEG
CPU DMI/FDI/PEG
CPU DMI/FDI/PEG
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
645Wednesday, March 24, 2010
645Wednesday, March 24, 2010
645Wednesday, March 24, 2010
1
2.0
2.0
2.0
of
of
of
5
JCPUC
JCPUC
DDR_A_D[0..63]<11>
4
3
JCPUD
JCPUD
DDR_B_D[0..63]<12>
2
1
AA6
SA_CK[0]
AA7
SA_CK#[0]
P7
DDR_A_D0 DDR_A_D1
D D
C C
B B
DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>
DDR_A_CAS#<11> DDR_A_RAS#<11>
DDR_A_WE#<11>
DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
C10
D10
H10
G10
AH5 AF5 AK6 AK7 AF6 AG5
AJ10 AL10
AK12
AK8
AK11
AN8 AM10 AR11
AL11
AM9
AN9
AT11
AP12 AM12 AN12 AM13
AT14
AT12
AL13 AR14
AP14
AC3 AB2
AE1 AB3 AE9
A10
B10 E10
F10
AJ7 AJ6
AJ9
AL7 AL8
C7 A7
A8 D8
E6 F7 E9 B7 E7 C6
G8
K7
G7
J10 M6
M8
K8 N8 P9
U7
J8
J7 L7
L9 L6
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
SA_BS[0] SA_BS[1] SA_BS[2]
SA_CAS# SA_RAS# SA_WE#
SA_CKE[0]
Y6
SA_CK[1]
Y5
SA_CK#[1]
P6
SA_CKE[1]
AE2
SA_CS#[0]
AE8
SA_CS#[1]
AD8
SA_ODT[0]
AF9
SA_ODT[1]
DDR_A_DM0
B9
SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]
SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
D7 H7 M7 AG6 AM7 AN10 AN13
DDR_A_DQS#0
C9
DDR_A_DQS#1
F8
DDR_A_DQS#2
J9
DDR_A_DQS#3
N9
DDR_A_DQS#4
AH7
DDR_A_DQS#5
AK9
DDR_A_DQS#6
AP11
DDR_A_DQS#7
AT13
C8 F9 H9 M9 AH8 AK10 AN11 AR13
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8
DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDRA_CLK0 <11> DDRB_CLK0 <12> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRB_CKE0 <12>
DDRA_CLK1 <11> DDRA_CLK1# <11> DDRA_CKE1 <11>
DDRA_SCS0# <11> DDRA_SCS1# <11> DDRB_SCS1# <12>
DDRA_ODT0 <11> DDRB_ODT0 <12> DDRA_ODT1 <11> DDRB_ODT1 <12>
DDR_A_DM[0..7] <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_A_MA[0..15] <11>
DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>
DDR_B_CAS#<12> DDR_B_RAS#<12>
DDR_B_WE#<12>
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AF3 AG1
AK1 AG4 AG3
AH4 AK3 AK4
AM6
AN2 AK5
AK2 AM4 AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10 AT10
AB1
AC5
AC6
AJ3
AJ4
W5
B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2
J6
J3 G1 G5
J2
J1
J5 K2
L3 M1 K5 K4 M4 N5
R7
Y7
SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
SB_BS[0] SB_BS[1] SB_BS[2]
SB_CAS# SB_RAS# SB_WE#
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_CK[0] SB_CK#[0] SB_CKE[0]
SB_CK[1] SB_CK#[1] SB_CKE[1]
SB_CS#[0] SB_CS#[1]
SB_ODT[0] SB_ODT[1]
SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]
SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
W8 W9 M3
V7 V6 M2
AB8 AD6
AC7 AD1
D4 E1 H3 K1 AH1 AL2 AR4 AT8
D5 F4 J4 L4 AH2 AL4 AR5 AR8
C5 E3 H4 M5 AG2 AL5 AP5 AR7
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8
DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDRB_CLK0# <12>
DDRB_CLK1 <12> DDRB_CLK1# <12> DDRB_CKE1 <12>
DDRB_SCS0# <12>
DDR_B_DM[0..7] <12>
DDR_B_DQS#[0..7] <12>
DDR_B_DQS[0..7] <12>
DDR_B_MA[0..15] <12>
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
A A
Security Classification
Security Classification
Security Classification
2009/10/05 2010/01/23
2009/10/05 2010/01/23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
3
Deciphered Date
Deciphered Date
Deciphered Date
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
CPU DDRIII
CPU DDRIII
CPU DDRIII
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
745Wednesday, March 24, 2010
745Wednesday, March 24, 2010
745Wednesday, March 24, 2010
1
2.0
2.0
2.0
of
of
of
5
4
3
2
1
Material Note (+VTT):
JCPUF
JCPUF
+CPU_CORE
D D
C C
B B
A A
Clarksfield: 65A Clarksfield: 21A Auburndale:48A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26
U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26
VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
SENSE LINES
SENSE LINES
Auburndale:18A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8
VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31
1.1V RAIL POWER
1.1V RAIL POWER
VTT0_32
VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44
PSI#
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
VTT_SELECT
ISENSE
VCC_SENSE VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15
AN33
AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34
G15
AN35
AJ34 AJ35
B15 A15
390uF/ 10mohm, number are 3, power x1, HW x2
(Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+
+
C144 390U_2.5V_M_R10
C144 390U_2.5V_M_R10
1 2
+
+
C267 390U_2.5V_M_R10
C267 390U_2.5V_M_R10
1 2
C89 22U_0805_6.3V6MC89 22U_0805_6.3V6M
1 2
C91 22U_0805_6.3V6MC91 22U_0805_6.3V6M
1 2
H_PSI# <42>
CPU_VID0 <42> CPU_VID1 <42> CPU_VID2 <42> CPU_VID3 <42> CPU_VID4 <42> CPU_VID5 <42>
T3 PADT3 PAD
CPU_VID6 <42> H_DPRSLPVR <42>
IMVP_IMON <42>
H_DPRSLPVR_R
H_VTTSELECT
VCCSENSE_R
1 2
R62 0_0402_5%R62 0_0402_5%
R65 0_0402_5%R65 0_0402_5%
1 2
R66 0_0402_5%R66 0_0402_5%
1 2
VTT_SENSE <39> VSS_SENSE_VTT <39>
+VTT
C81 10U_0805_10V4KC81 10U_0805_10V4K
1 2
C83 10U_0805_10V4KC83 10U_0805_10V4K
1 2
C85 10U_0805_10V4KC85 10U_0805_10V4K
1 2
C87 10U_0805_10V4KC87 10U_0805_10V4K
1 2
C88 10U_0805_10V4KC88 10U_0805_10V4K
1 2
C90 10U_0805_10V4KC90 10U_0805_10V4K
1 2
C92 10U_0805_10V4KC92 10U_0805_10V4K
1 2
C94 10U_0805_10V4K@C94 10U_0805_10V4K@
1 2
Add on 5/25 for power team request
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C179
C179
C114
C114
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C131
C131
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
CRB default setting: VID[6:0]=[0100111]
VTT Rail
Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V
H_VTTSELECT = low, 1.1V
H_VTTSELECT = high, 1.05V
1 2
R64 100_0402_1%R64 100_0402_1%
VCCSENSE VSSSENSEVSSSENSE_R
1 2
R67 100_0402_1%R67 100_0402_1%
near CPU
VCCSENSE <42> VSSSENSE <42>
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C116
C116
C132
C132
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C129
C129
2
1
1
C149
C149
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
10U_0805_10V4K
10U_0805_10V4K
1
C71
C71
2
10U_0805_10V4K
10U_0805_10V4K
1
C72
C72
2
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
1
C73
C73
2
1
2
1
C75
C75
C74
C74
2
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
1
C76
C76
2
10U_0805_10V4K
10U_0805_10V4K
(Place these capacitors under CPU socket, top layer)
+CPU_CORE
10U_0805_10V4K
10U_0805_10V4K
1
C98
C98
2
10U_0805_10V4K
10U_0805_10V4K
1
C99
C99
2
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
1
C100
C100
2
1
C101
C101
2
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
1
C102
C102
2
(Place these capacitors on CPU cavity, Bottom Layer)
+CPU_CORE
22U_0805_6.3V6M
1
C107
C107
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C113
C113
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C108
C108
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C130
C130
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C109
C109
C110
C110
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C148
C148
C115
C115
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C106
C106
C105
C105
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C112
C112
C111
C111
2
22U_0805_6.3V6M
22U_0805_6.3V6M
TOP side (under inductor)
+CPU_CORE
330U_D2_2.5VM_R9M
1
+
+
C121
C121
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
2
330U_D2_2.5VM_R9M
1
+
+
C122
C122
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
2
C123
C123
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
1
+
+
C124
C124
2
1
+
+
2
Check list:
+CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
+VTT: 4x 330uF, 7x 22uF, 8x 10uF
10U_0805_10V4K
10U_0805_10V4K
1
1
C77
C77
2
2
1
1
C103
C103
C104
C104
2
2
10U_0805_10V4K
10U_0805_10V4K
1
C78
C78
C79
C79
2
10U_0805_10V4K
10U_0805_10V4K
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R W RI TTEN CO NSENT OF COMPAL ELECTRONICS, INC.
3
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, I n c.
Compal Electronics, I n c.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, I n c.
CPU POWER-1
CPU POWER-1
CPU POWER-1
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
1
845Wednesday, March 24, 2010
845Wednesday, March 24, 2010
845Wednesday, March 24, 2010
2.0
2.0
2.0
of
of
of
5
4
3
2
1
For S3 CPU Power Saving
For EMI request
+GFX_CORE
R424
R424
470_0805_5%
47P_0402_50V8J
C118
C118
@
@
47P_0402_50V8J
12
C119
C119
@
@
12
C93
C93
@
@
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
47P_0402_50V8J
47P_0402_50V8J
12
12
C97
C97
@
@
D D
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J
470_0805_5%
PS@
PS@
1 2 3
Q46B
Q46B
SUSP SUSP
5
PS@
PS@
4
1
C273
C273 10U_0805_10V4K
10U_0805_10V4K
2
PS@
PS@
3A
Change C271 to 4.5mm height OS-CON at PVT
+GFX_CORE
22U_0805_6.3V6M
C271
330U_2.5V_M_R17
330U_2.5V_M_R17
C271
1
+
+
2
1
C95
C95
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C127
C127
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C117
C117
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C96
C96
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
2
C120
C120
1
C86
C86 10U_0805_6.3V6M
10U_0805_6.3V6M
2
Add C496 Co-Layout with C271
C496
C496
@
@
+GFX_CORE
1
+
+
2
C141
C141
22U_0805_6.3V6M
22U_0805_6.3V6M
C146
C146
22U_0805_6.3V6M
22U_0805_6.3V6M
+VTT
+VTT
1
2
1
2
1
C142
C142 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C147
C147 22U_0805_6.3V6M
22U_0805_6.3V6M
2
C C
330U_D2_2VM_R6M
330U_D2_2VM_R6M
B B
(Place these capacitors under CPU socket, top layer)
A A
JCPUG
JCPUG
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
Auburndale:22A
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
GRAPHICS
GRAPHICS
Clarksfield: 5A Auburndale:3A
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
Clarksfield: 21A Auburndale:18A
Clarksfield: 0.6A Auburndale:1.35A
GFX_IMON
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
VTT0_59 VTT0_60 VTT0_61 VTT0_62
VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68
VCCPLL1 VCCPLL2 VCCPLL3
AR22 AT22
AM22 AP22 AN22 AP23 AM23 AP24 AN24
AR25 AT25 AM24
AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
P10 N10 L10 K10
J22 J20 J18 H21 H20 H19
L26 L27 M26
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GRAPHICS VIDs
GRAPHICS VIDs
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
1.1V1.8V
1.1V1.8V
R365 0_0402_5%R365 0_0402_5%
1 2
R384 0_0402_5%R384 0_0402_5%
1 2
For Power request
GFXVR_EN
GFXVR_DPRSLPVR GFXVR_IMON
R687 1K_0402_5%
R687 1K_0402_5%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C133
C133
C134
C134
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+VTT
1
C143
C143 10U_0805_10V4K
10U_0805_10V4K
2
1
C145
C145 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1U_0402_6.3V4Z
C151
C151
1U_0402_6.3V4Z
1
2
+1.8VS_H_PLL
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2
R69 100_0402_1%R69 100_0402_1%
1 2
R82 100_0402_1%R82 100_0402_1%
near CPU
GFXVR_VID_0 <43> GFXVR_VID_1 <43> GFXVR_VID_2 <43>
12
@
@
1
1
C135
C135
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
GFXVR_VID_3 <43> GFXVR_VID_4 <43> GFXVR_VID_5 <43> GFXVR_VID_6 <43>
GFXVR_EN <43>
T8 PADT8 PAD
GFXVR_IMON <43>
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C136
C136
2
Change R136 to 470 ohm for GFX issue
1 2
R50 470_0402_5%R50 470_0402_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
1
C137
C137
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C138
C138
2
2
(Place these capacitors under CPU socket Edge, top layer)
+VTT
(Place these capacitors under CPU socket, top layer)
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
C152
C152
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
C153
C153
2
C154
C154
1
C155
C155
2
22U_0805_6.3V6M
22U_0805_6.3V6M
Q33
1 2 3 4
FDS6676AS_SO8
FDS6676AS_SO8
1
C472
C472
2
PS@
PS@
0.1U_0402_25V6
0.1U_0402_25V6
+GFX_CORE
+1.5V_CPU
1
C139
C139
2
22U_0805_6.3V6M
22U_0805_6.3V6M
R71 0_0805_5%R71 0_0805_5%
S S S G
12
1
+
+
C216
C216 390U_2.5V_M_R10
390U_2.5V_M_R10
2
12
+1.5V+1.5V_CPU
PS@Q33
PS@
8
D
7
D
6
D
5
D
R417
R417 820K_0402_5%
820K_0402_5%
PS@
PS@
VCC_AXG_SENSE <43> VSS_AXG_SENSE <43>
+1.8VS
61
PJ30,PJ31 need to open for S3 CPU Power Saving
R418
R418
1 2
220K_0402_5%
220K_0402_5%
PS@
PS@
Q46A
PS@Q46A
PS@
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
C230 0.1U_0402_16V4ZC230 0.1U_0402_16V4Z
1 2
C314 0.1U_0402_16V4ZC314 0.1U_0402_16V4Z
1 2
C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z
1 2
C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z
1 2
2
JUMP_43X79
JUMP_43X79
2
JUMP_43X79
JUMP_43X79
PJ30
PJ31
@PJ30
@
112
@PJ31
@
112
+VSB
SUSP <34,41>
+1.5V
Security Classification
Security Classification
Security Classification
2009/10/05 2010/01/23
2009/10/05 2010/01/23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
3
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
CPU POWER-2
CPU POWER-2
CPU POWER-2
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
945Wednesday, March 24, 2010
945Wednesday, March 24, 2010
945Wednesday, March 24, 2010
1
2.0
2.0
2.0
of
of
of
5
JCPUI
JCPUI
K27
VSS161
K9
VSS162
K6
VSS163
D D
C C
B B
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
VSS
VSS
NCTF
NCTF
VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7
AT35 AT1 AR34 B34 B2 B1 A35
H_NCTF1 H_NCTF2
H_NCTF6 H_NCTF7
PADT4PAD PADT5PAD
PADT6PAD PADT7PAD
4
JCPUH
JCPUH
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
VSS8
AR17
VSS9
AR15
VSS10
AR12
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
AP20
VSS15
AP17
VSS16
AP13
VSS17
AP10
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
AN34
VSS22
AN31
VSS23
AN23
VSS24
AN20
VSS25
AN17
VSS26
AM29
VSS27
AM27
VSS28
AM25
VSS29
AM20
VSS30
AM17
VSS31
AM14
VSS32
AM11
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
AL34
VSS37
AL31
VSS38
AL23
VSS39
AL20
VSS40
AL17
VSS41
AL12
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
AK29
T4 T5
T6 T7
VSS46
AK27
VSS47
AK25
VSS48
AK20
VSS49
AK17
VSS50
AJ31
VSS51
AJ23
VSS52
AJ20
VSS53
AJ17
VSS54
AJ14
VSS55
AJ11
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
AH35
VSS60
AH34
VSS61
AH33
VSS62
AH32
VSS63
AH31
VSS64
AH30
VSS65
AH29
VSS66
AH28
VSS67
AH27
VSS68
AH26
VSS69
AH20
VSS70
AH17
VSS71
AH13
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
AG10
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
AE35
VSS80
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
VSS
VSS
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
3
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
2
WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1
R743.01K_0402_1% @ R743.01K_0402_1% @
1 2
R753.01K_0402_1% @ R753.01K_0402_1% @
1 2
R763.01K_0402_1% @ R763.01K_0402_1% @
1 2
CFG0 - PCI-Express Configuration Select
*1:Single PEG 0:Bifurcation enabled
CFG3 - PCI-Express Static Lane Reversal
*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG4 - Display Port Presence
*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port
JCPUE
JCPUE
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
RSVD9
H17
RSVD10
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
@
@
(SA_DIMM_VREF) (SB_DIMM_VREF)
RSVD32 RSVD33
RSVD34 RSVD35
RSVD36
RSVD_NCTF_37
RSVD38 RSVD39
RSVD_NCTF_40 RSVD_NCTF_41
RSVD_NCTF_42 RSVD_NCTF_43
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52
RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57
RSVD58
RSVD_TP_59 RSVD_TP_60
RESERVED
RESERVED
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75
RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85
KEY
VSS
1
AJ13 AJ12
AH25 AK26
AL26 AR2
AJ26 AJ27
AP1 AT2
AT3 AR1
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32
E15 F15 A2 D15 C15 AJ15 AH15
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3
V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9
AP34
*:Default
A A
Security Classification
Security Classification
Security Classification
2009/10/05 2010/01/23
2009/10/05 2010/01/23
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/10/05 2010/01/23
3
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
CPU GND/RESERVED/XDP
CPU GND/RESERVED/XDP
CPU GND/RESERVED/XDP
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
10 45Tuesday, March 23, 2010
10 45Tuesday, March 23, 2010
10 45Tuesday, March 23, 2010
1
2.0
2.0
2.0
of
of
of
5
+VREF_DQA
1
C157
C157
C156
C156
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D D
close to JDDRL.1
C C
B B
A A
+3VS
C181
C181
DDRA_CLK0<7> DDRA_CLK0#<7>
DDR_A_BS0<7>
DDR_A_CAS#<7>
DDRA_SCS1#<7>
DDR_A_BS2<7>
DDR_A_WE#<7>
1
C182
C182
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
DDR_A_D0 DDR_A_D1
1
DDR_A_DM0
2
DDR_A_D2 DDR_A_D3
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3 DDR_A_D26
DDR_A_D27
DDR_A_MA12 DDR_A_MA9
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDR_A_MA10
DDR_A_MA13
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49 DDR_A_DQS#6
DDR_A_DQS6 DDR_A_D50
DDR_A_D51 DDR_A_D56
DDR_A_D57 DDR_A_DM7 DDR_A_D58
DDR_A_D59
R90
R90
1 2
10K_0402_5%
10K_0402_5%
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
R91
R91
+0.75VS
12
10K_0402_5%
10K_0402_5%
+1.5V
JDDRL
JDDRL
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
FOX_AS0A626-U2SN-7F_204P
FOX_AS0A626-U2SN-7F_204P
@
@
VREF_CA
VSS DQ4 DQ5 VSS
DQS0#
DQS0
VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
RESET#
VSS DQ14 DQ15
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1 RAS#
VDD ODT0
VDD ODT1
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
EVENT#
SDA
SCL
VTT
BOSS1 BOSS2
A15 A14
A11
A7 A6
A4 A2
A0
S0#
NC
4
+1.5V
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26
DDR_A_DM1
28 30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44
DDR_A_DM2
46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
74 76
DDR_A_MA15
78
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86 88
DDR_A_MA6
90
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
+DDR_VREF_CA_DIMMA
DDR_A_D36 DDR_A_D37
DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D47 DDR_A_D52
DDR_A_D53 DDR_A_DM6 DDR_A_D54
DDR_A_D55 DDR_A_D60
DDR_A_D61 DDR_A_DQS#7
DDR_A_DQS7 DDR_A_D62
DDR_A_D63
+0.75VS
4
DDR3 SO-DIMM A Standard Type
+1.5V
12
R83
R83
1K_0402_1%
1K_0402_1%
PS@
PS@
DDRA_CKE1 <7>DDRA_CKE0<7>
DDRA_CLK1 <7> DDRA_CLK1# <7>
DDR_A_BS1 <7> DDR_A_RAS# <7>
DDRA_SCS0# <7> DDRA_ODT0 <7>
DDRA_ODT1 <7>
C161
C161
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
close to JDDRL.126
PM_EXTTS# <5,12>
PM_SMBDATA <12,13,17,27> PM_SMBCLK <12,13,17,27>
+V_DDR3_DIMM_REF
R89
R89
1 2
0_0402_5%
0_0402_5%
1
1
C162
C162
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SM_DRAMRST# <5,12>
3
DDR_A_DQS[0..7]<7>
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_MA[0..15]<7>
Layout Note: Place near JDDRL
+1.5V
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
3
+
+
C218 390U_2.5V_M_R10
C218 390U_2.5V_M_R10
1 2
C166 10U_0805_6.3V6MC166 10U_0805_6.3V6M
1 2
C168 10U_0805_6.3V6MC168 10U_0805_6.3V6M
1 2
C171 10U_0805_6.3V6MC171 10U_0805_6.3V6M
1 2
C174 10U_0805_6.3V6MC174 10U_0805_6.3V6M
1 2
C176 10U_0805_6.3V6MC176 10U_0805_6.3V6M
1 2
C178 10U_0805_6.3V6MC178 10U_0805_6.3V6M
1 2
Deciphered Date
Deciphered Date
Deciphered Date
M1 Circuit
+1.5V
12
R79
R79
1K_0402_1%
1K_0402_1%
12
R81
R81
1K_0402_1%
1K_0402_1%
Layout Note: Place these 4 Caps near Command and Control signals of DIMMA
+1.5V +0.75VS
C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z
2
+V_DDR3_DIMM_REF
1 2 1 2 1 2 1 2
2
1
12
R78 0_0402_5%R78 0_0402_5%
12
R80 0_0402_5%R80 0_0402_5%
Layout Note: Place near JDDRL1.203 and 204
C165 10U_0805_6.3V6MC165 10U_0805_6.3V6M
C169 1U_0402_6.3V4ZC169 1U_0402_6.3V4Z C172 1U_0402_6.3V4ZC172 1U_0402_6.3V4Z C175 1U_0402_6.3V4ZC175 1U_0402_6.3V4Z C177 1U_0402_6.3V4ZC177 1U_0402_6.3V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM0
DDRIII-SODIMM0
DDRIII-SODIMM0
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
1 2
+VREF_DQB
+VREF_DQA
12 12 12 12
1
of
of
of
11 45Wednesday, March 24, 2010
11 45Wednesday, March 24, 2010
11 45Wednesday, March 24, 2010
2.0
2.0
2.0
A
+VREF_DQB
1
2
C183
C183
2.2U_0603_6.3V4Z
1 1
2.2U_0603_6.3V4Z
close to JDDRH.1
2 2
3 3
4 4
DDRB_CKE0<7>
DDR_B_BS2<7>
DDRB_CLK0<7> DDRB_CLK0#<7>
DDR_B_WE#<7> DDR_B_CAS#<7>
DDRB_SCS1#<7>
+3VS
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
C207
C207
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C208
C208
2
1
2
C184
C184
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R98
R98 10K_0402_5%
10K_0402_5%
R99
R99
1 2
10K_0402_5%
10K_0402_5%
A
DDR_B_D0 DDR_B_D1
DDR_B_DM0 DDR_B_D2
DDR_B_D3 DDR_B_D8
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11 DDR_B_D16
DDR_B_D17 DDR_B_DQS#2
DDR_B_DQS2 DDR_B_D18
DDR_B_D19 DDR_B_D24
DDR_B_D25 DDR_B_DM3 DDR_B_D26
DDR_B_D27
DDR_B_MA12 DDR_B_MA9
DDR_B_MA8 DDR_B_MA5
DDR_B_MA3 DDR_B_MA1
DDR_B_MA10
DDR_B_MA13
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D48
DDR_B_D49 DDR_B_DQS#6
DDR_B_DQS6 DDR_B_D50
DDR_B_D51 DDR_B_D56
DDR_B_D57 DDR_B_DM7 DDR_B_D58
DDR_B_D59
1 2
+0.75VS
+1.5V
JDDRH
JDDRH
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
GND2
FOX_AS0A626-UASN-7F_204P
FOX_AS0A626-UASN-7F_204P
@
@
VREF_CA
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS DQ12 DQ13
VSS
DM1
RESET#
VSS DQ14 DQ15
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
BA1 RAS#
VDD ODT0
VDD ODT1
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
EVENT#
SDA
SCL
VTT
BOSS1 BOSS2
A15 A14
A11
A7 A6
A4 A2
A0
S0#
NC
+1.5V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
206 208
B
DDR_B_D4 DDR_B_D5
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D6 DDR_B_D7
DDR_B_D12 DDR_B_D13
DDR_B_DM1
DDR_B_D14 DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2 DDR_B_D22
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31
DDR_B_MA15 DDR_B_MA14
DDR_B_MA11 DDR_B_MA7
DDR_B_MA6 DDR_B_MA4
DDR_B_MA2 DDR_B_MA0
+DDR_VREF_CA_DIMMB DDR_B_D36
DDR_B_D37 DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D47 DDR_B_D52
DDR_B_D53 DDR_B_DM6 DDR_B_D54
DDR_B_D55 DDR_B_D60
DDR_B_D61 DDR_B_DQS#7
DDR_B_DQS7 DDR_B_D62
DDR_B_D63
+0.75VS
B
Standard Type DDR3 SO-DIMM B
SM_DRAMRST# <5,11>
DDRB_CKE1 <7>
DDRB_CLK1 <7> DDRB_CLK1# <7>
DDR_B_BS1 <7> DDR_B_RAS# <7>DDR_B_BS0<7>
DDRB_SCS0# <7> DDRB_ODT0 <7>
DDRB_ODT1 <7>
R97
R97
1 2
1
1
2
2
C188
C188
C187
C187
close to JDDRH.126
PM_EXTTS# <5,11>
PM_SMBDATA <11,13,17,27> PM_SMBCLK <11,13,17,27>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+V_DDR3_DIMM_REF
0_0402_5%
0_0402_5%
C
DDR_B_DQS#[0..7]<7>
DDR_B_DQS[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DM[0..7]<7>
DDR_B_MA[0..15]<7>
Layout Note: Place near JDDRH
+1.5V
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
C
@
@
+
+
C189 330U_B2_2.5VM_R15M
C189 330U_B2_2.5VM_R15M
1 2
C192 10U_0805_6.3V6MC192 10U_0805_6.3V6M
1 2
C194 10U_0805_6.3V6MC194 10U_0805_6.3V6M
1 2
C197 10U_0805_6.3V6MC197 10U_0805_6.3V6M
1 2
C200 10U_0805_6.3V6MC200 10U_0805_6.3V6M
1 2
C202 10U_0805_6.3V6MC202 10U_0805_6.3V6M
1 2
C204 10U_0805_6.3V6MC204 10U_0805_6.3V6M
1 2
Deciphered Date
Deciphered Date
Deciphered Date
Layout Note: Place these 4 Caps near Command and Control signals of DIMMB
D
C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z
1 2
C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z
1 2
C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z
1 2
C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z
1 2
D
E
Layout Note: Place near JDDRH.203 and 204
+0.75VS+1.5V
C191 10U_0805_6.3V6MC191 10U_0805_6.3V6M
1 2
C195 1U_0402_6.3V4ZC195 1U_0402_6.3V4Z
12
C198 1U_0402_6.3V4ZC198 1U_0402_6.3V4Z
12
C201 1U_0402_6.3V4ZC201 1U_0402_6.3V4Z
12
C203 1U_0402_6.3V4ZC203 1U_0402_6.3V4Z
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
DDRIII-SODIMM1
DDRIII-SODIMM1
DDRIII-SODIMM1
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
12 45Wednesday, March 24, 2010
12 45Wednesday, March 24, 2010
12 45Wednesday, March 24, 2010
E
of
of
of
2.0
2.0
2.0
A
Clock Generator
1 1
+1.5VS +1.5VS_CK505
Change C213 to 1U for NALAA ESATA issue at pre-MP
CLK_DOT<17> CLK_DOT#<17>
2 2
CLK_SATA<17> CLK_SATA#<17>
PCH_CLK_DMI<17>
PCH_CLK_DMI#<17>
B
C
D
E
F
For SED For SED
FBMH1608HM601-T_0603
FBMH1608HM601-T_0603
+3VS +3VS_CK505 +1.05VS +1.05VS_CK505
1 2
R100
R100
R401
@ R401
@
0_0603_5%
0_0603_5%
FBMH1608HM601-T_0603
FBMH1608HM601-T_0603
1 2
R126
R126
For SED
+1.05VS_CK505 +3VS_CK505
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C209
C209
2
10U_0805_10V4Z
10U_0805_10V4Z
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C213
C213
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+1.5VS_CK505
U5
U5
1
VDD_USB_48
2
VSS_48M
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
USB_48
9
VSS_27M
10
SATA
11
SATA#
12
VSS_SRC
13
SRC_1
14
SRC_1#
15
VDD_SRC_IO
16
CPU_STOP#
33
TGND
RTM890N-631-GRT QFN 32P
RTM890N-631-GRT QFN 32P
C210
C210
C214
C214
0.1U_0402_16V4Z
1
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C211
C211
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C215
C215
2
C212
C212
For SED For SED
1
12
C251
C251 47P_0402_50V8J
2
47P_0402_50V8J
SCL SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
+1.05VS_CK505
+3VS_CK505
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
FBMH1608HM601-T_0603
FBMH1608HM601-T_0603
CPU_SEL
1 2
CLK_XTAL_IN CLK_XTAL_OUT
CK_PWRGD
+1.5VS_CK505
1 2
R101
R101
R10233_0402_5% R10233_0402_5%
10U_0805_10V4Z
10U_0805_10V4Z
C219
C219
CPU_SEL
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C220
C220
C221
C221
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
For RF
C484
C484
1 2
100P_0402_50V8J
100P_0402_50V8J
PM_SMBCLK <11,12,17,27>
PM_SMBDATA <11,12,17,27>
CLK_14M_PCH <17>
CLK_BCLK <17> CLK_BCLK# <17>
CLK_XTAL_IN
C223
C223
22P_0402_50V8J
22P_0402_50V8J
1
1
C222
C222
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLK_XTAL_OUTH_STP_CPU#
Y1
Y1
1 2
2
14.318MHZ_16PF_7A14300083
14.318MHZ_16PF_7A14300083
1
12
C252
C252 47P_0402_50V8J
47P_0402_50V8J
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
C224
C224 22P_0402_50V8J
22P_0402_50V8J
1
G
+3VS_CK505
12
R110
R110 10K_0402_5%
10K_0402_5%
CK_PWRGD
3
Q35B
Q35B
5
4
Silego Have Internal Pull-Up
H_STP_CPU#
CPU_SEL
IDT Have Internal Pull-Down
(Default)
0 133MHz
1
100MHz 100MHz
H
CLK_ENABLE# <42>
+3VS_CK505
R10510K_0402_5% R10510K_0402_5%
12
R11910K_0402_5% @ R11910K_0402_5% @
12
+1.05VS
R10610K_0402_5% R10610K_0402_5%
12
CPU_1/1#CPU_SEL CPU_0/0#
133MHz
@
Reserve for EMI request
R93 0_0402_5%
LCD/PANEL BD. Conn.
USB20_N11<20>
3 3
+LCD_VDD
Q1A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4 4
UMA_ENVDD<19>
A
Q1A
R112
R112
100K_0402_5%
100K_0402_5%
12
R107
R107 150_0603_5%
150_0603_5%
61
2
1 2
USB20_P11<20>
+3VS
12
R108
R108 100K_0402_5%
100K_0402_5%
3
5
Q1B
Q1B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
1 2
R109 47K_0402_5%R109 47K_0402_5%
B
R93 0_0402_5%
1 2
L55
1
1
4
4
WCM-2012-900T_0805
WCM-2012-900T_0805 R92 0_0402_5%
R92 0_0402_5%
1 2
CAM@
CAM@
C228
0.1U_0402_16V7K
0.1U_0402_16V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
C228
C229
C229
CAM@
CAM@
@L55
@
USB20_N11_R
2
2
USB20_P11_R
3
3
1
C871
C871 10P_0402_50V8J
10P_0402_50V8J
2
@
@
1
C872
C872 10P_0402_50V8J
10P_0402_50V8J
2
@
@
+3VS
For RF request
LCD_TXOUT0+<19> LCD_TXOUT0-<19> LCD_TXOUT1+<19>
+3VS
W=60mils
2
S
S
G
G
1 1
2
Q17
Q17
2
AO3413_SOT23
AO3413_SOT23
D
D
1 3
+LCD_VDD
W=60mils
1
C233
C233
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C
LCD_TXOUT1-<19> LCD_TXOUT2+<19> LCD_TXOUT2-<19> LCD_TXCLK+<19>
LCD_TXCLK-<19>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
+LCD_INV
1
C234
C234
68P_0402_50V8J
68P_0402_50V8J
2
0_0603_5%
0_0603_5%
R388
R388
1 2
CAM@
CAM@
USB20_P11_R USB20_N11_R
LCD_TXOUT0+ LCD_TXOUT0­LCD_TXOUT1+ LCD_TXOUT1­LCD_TXOUT2+ LCD_TXOUT2­LCD_TXCLK+ LCD_TXCLK-
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
L2
L2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1
C235
C235
0.1U_0402_25V6
0.1U_0402_25V6
2
680P_0402_50V7K
680P_0402_50V7K
W=20mils
+3VS_LVDS_CAM
3 5 7
13 15 17 19 21 23 25 27 29
31 32
ACES_87242-3001-09
ACES_87242-3001-09
Deciphered Date
Deciphered Date
Deciphered Date
E
12
JLVDS
112 3 5 7 9910 111112 13 15 17 19 21 23 25 27 29
GND1 GND2
@C236
@
B+
1
C236
2
EMI
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
C225
CAM@C225
CAM@
@JLVDS
@
2 4
4
6
6
8
8
10 12 14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
INT_MIC_CLK INT_MIC_DATA LED_PWM_R BKOFF#_R
F
B+
Top layer near H12, For EMI request
1
C268
C268
@
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LCD_EDID_CLK <19> LCD_EDID_DATA <19>
R387 FBMA-10-100505-301TR387 FBMA-10-100505-301T
+LCD_INV
12 12
R10333_0402_5% R10333_0402_5%
1 2
R113 10K_0402_5%R113 10K_0402_5%
1
C226
C226
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1.5A
+LCD_VDD
1
C227
C227
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Title
Title
Title
Clock Generator (CK505)/ LVDS CONN
Clock Generator (CK505)/ LVDS CONN
Clock Generator (CK505)/ LVDS CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
G
BKOFF#
BKOFF#_R
D84
D84
2
1
3
PACDN042Y3R_SOT23-3
PACDN042Y3R_SOT23-3
INT_MIC_CLK <30>
INT_MIC_DATA <30> PCH_PWM <19> BKOFF# <31>
680P_0402_50V7K
680P_0402_50V7K
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
@
1 2
C485 330P_0402_50V7K
C485 330P_0402_50V7K
@
@
1 2
C489 330P_0402_50V7K
C489 330P_0402_50V7K
@
@
1 2
C486 0.1U_0402_16V4Z
C486 0.1U_0402_16V4Z
For ESD request at PVT
+3VS
1
1
C232
2
C232
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
of
of
of
13 45Wednesday, March 24, 2010
13 45Wednesday, March 24, 2010
13 45Wednesday, March 24, 2010
H
C231
@C231
@
EMI
2.0
2.0
2.0
A
CRT CONNECTOR
B
C
D
E
1
D3
D3
DAN217_SC59
1 1
UMA_CRT_R<19>
UMA_CRT_G<19>
UMA_CRT_B<19>
1
12
12
R139
R139
R138
R138
150_0402_1%
150_0402_1%
2 2
1 2
C244 0.1U_0402_16V4ZC244 0.1U_0402_16V4Z
UMA_CRT_HSYNC<19>
UMA_CRT_VSYNC<19>
3 3
12
R140
R140
150_0402_1%
150_0402_1%
SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
1
C239
C239
C238
C238
2
2.2P_0402_50V8C
150_0402_1%
150_0402_1%
+CRT_VCC
2.2P_0402_50V8C
1
5
P
4
OE#
A2Y
G
U6
U6
3
+CRT_VCC
5
P
A2Y
SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
G
3
2
1
OE#
U7
U7
DAN217_SC59
2
3
@
@
L3
L3
1 2
NBQ100505T-800Y_0402
NBQ100505T-800Y_0402
L4
L4
1 2
NBQ100505T-800Y_0402
NBQ100505T-800Y_0402
L5
L5
1 2
NBQ100505T-800Y_0402
NBQ100505T-800Y_0402
1
C240
C240
2
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
12
R141 10K_0402_5%R141 10K_0402_5%
D_CRT_HSYNC
4
C241
C241
1
D4
D4
DAN217_SC59
DAN217_SC59
2
3
@
@
1
C242
C242
2
2.2P_0402_50V8C
2.2P_0402_50V8C
1 2
L6 10_0402_5%L6 10_0402_5%
1 2
L7 10_0402_5%L7 10_0402_5%
D5
D5
DAN217_SC59
DAN217_SC59
2
@
@
1
2
2.2P_0402_50V8C
2.2P_0402_50V8C
1
C243
C243
3
C245
C245
@
@
1
2
2.2P_0402_50V8C
2.2P_0402_50V8C
1
C246
C246
@
@
2
10P_0402_50V8J
10P_0402_50V8J
+3VS
CRT_R_L
CRT_G_L
CRT_B_L
HSYNC
VSYNCD_CRT_VSYNC
1
2
10P_0402_50V8J
10P_0402_50V8J
+CRT_VCC
+5VS
2 3
CRT_R_L CRT_DDC_DAT
CRT_G_L HSYNC
CRT_B_L VSYNC
CRT_DDC_CLK
+CRT_VCC_R +CRT_VCC
D6
D6
RB491D_SOT23-3
RB491D_SOT23-3
If=1A
F1
F1
1
1.1A_6V_MINISMDC110F-2
1.1A_6V_MINISMDC110F-2
21
6
11
1 7
12
2 8
13
3 9
14
4 10 15
5
ALLTO_C10532-11505-L_15P-T
ALLTO_C10532-11505-L_15P-T
@
@
30mil
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
JCRT
JCRT
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
G G
C237
C237
1
2
16 17
+3VS
+CRT_VCC
R146
R146
R147
@
@
R147
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
CRT_DDC_DAT
CRT_DDC_CLK
1
1
C250
C250 470P_0402_50V8J
470P_0402_50V8J
2
2
@
@
2009/10/05 2010/01/23
2009/10/05 2010/01/23
2009/10/05 2010/01/23
C
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
CRT\TV\LVDS
CRT\TV\LVDS
CRT\TV\LVDS
NWQAA LA6061P M/B
NWQAA LA6061P M/B
NWQAA LA6061P M/B
14 45Wednesday, March 24, 2010
14 45Wednesday, March 24, 2010
14 45Wednesday, March 24, 2010
E
2.0
2.0
2.0
of
of
of
4.7K_0402_5%
4.7K_0402_5%
2
Q2A
Q2A
UMA_CRT_DATA<19>
UMA_CRT_CLK<19>
33P_0402_50V8K
33P_0402_50V8K
4 4
A
1
C247
C247
2
@
@
B
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q2B
Q2B
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
C248
C248 33P_0402_50V8K
33P_0402_50V8K
2
@
@
61
3
C249
C249
470P_0402_50V8J
470P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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