Compal LA-5971P NAWA1, 3000 G455 Schematic
A
ZZZ1
ZZZ1
LA5971P LS5971P
LA5971P LS5971P
1 1
ZZZ3
ZZZ3
LA5971P
LA5971P
DAZ@
DAZ@
ZZZ4
ZZZ4
LS5971P
LS5971P
DAZ@
DAZ@
B
C
D
E
Compal Confidential
2 2
NAWA1 Schematics Document
AMD Tigris: Caspian Processor with RS880M/SB710/Park-S3 & M93-S3
3 3
4 4
A
B
2009-11-26
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-5971P
LA-5971P
LA-5971P
E
1 49Thursday, December 10, 2009
1 49Thursday, December 10, 2009
1 49Thursday, December 10, 2009
1.0
1.0
1.0
A
B
C
D
E
Tigris
Compal Confidential
Model Name : NAWA1
1 1
LCD (LED BL)
page 21
VRAM 512MB
64M16 x 4
page 19
DDR3 800MHz
ATI PARK-S3 & M93-S3
uFCBGA-631
Page 14,15,16,17,18
Fan Control
page 37
PCI-Express 16x
Gen2
CRT
page 22
PCI-Express 1x
AMD S1G3 Processor
uPGA-638 Package
Caspian
Hyper Transport Link
16 x 16
page 4,5,6,7
ATI RS880M
uFCBGA-528
page 10,11,12,13
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 667 (800)
Thermal Sensor
ADM1032
WINBOND
page 32 page 32 page 31 page 32 page 31
200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3
page 8,9
Clock Generator
page 6 page 20
SLG8SP626VTR
5 in 1 socket
page 29
Card Reader
RTS5138
page 29
MINI Card x1
WLAN
page 31
2 2
LAN(10/100)/1000
AR8131/AR8132
port 3port 2
page 30
A link Express2
ATI SB710
RJ45
page 30
uFCBGA-528
page 23,24,25,26,27
LPC BUS
conn
X 2
USB port 0,1
3.3V 48MHz
3.3V 24.576MHz/48Mhz
S-ATA
SATA HDD
Conn.
page 28
port 0
USB
CMOS
Camera
USB port 7 USB port 8 USB port 3 USB port 5
USB
CDROM
Conn.
page 28
port 1
Bluetooth
Conn
HD Audio
USB
conn
X 1
Mini
card
(WL)X1
HDA Codec
CX20671
page 36
Phone Jack x2
page 36
USB port 2
MIC
page 36
ENE KB926
3 3
Touch Pad
page 34
Power Board
page 35
DC/DC Interface.
page 38
page 33
Int.KBD
page 34
BIOS
page 34
Power Circuit
4 4
page 39,40,41,42,43,
44,45,46,47,48
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-5971P
LA-5971P
LA-5971P
E
1.0
1.0
2 49Thursday, December 10, 2009
2 49Thursday, December 10, 2009
2 49Thursday, December 10, 2009
1.0
A
Voltage Rails
Power Plane Description
VIN
B+
+CPU_CORE_0
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V)
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF
1 1
+0.9V 0.9V switched power rail for DDR terminator
+1.1VS
+1.2V_HT 1.2V switched power rail ON OFF OFF
+VGA_CORE OFFOFFON
+1.5VS
+1.8V
+1.8VS 1.8V switched power rail
+2.5VS
+3VALW
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS
+5VALW
+5VS
+VSB VSB always on power rail ON ON*
+RTCVCC RTC power
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
1.1V switched power rail for NB VDDC & VGA
0.95-1.2V switched power rail
1.5V power rail for PCIE Card
1.8V power rail for CPU VDDIO and DDR
2.5V for CPU_VDDA
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
B
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF OFF
ON
ON OFF OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF OFF
OFF
ON
OFF
OFF
OFF
OFF
ON ON*
OFF
OFF
ON
ON*
OFF
OFFON
ONON
C
BTO Option Table
BTO Item BOM Structure
Discrete
PARK PARK@
M93 M93@
HDT debug HDT@
UMA UMA@
Wireless LAN WLAN@
Blue Tooth BT@
Camera CMOS@
New Card New Card@
VRAM X76@
UNPON @
VGA@
D
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
LOW LOW LOW LOW
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
NAWA1_UMA : UMA@/WLAN@/BT@/CMOS@/NEW CARD@
NAWA1_DIS : VGA@/M93@/WLAN@/BT@/NEW CARD@/CMOS@/X76@
PARK-S3 power on sequence
+3VS_VGA
+VGA_CPRE
+1.1VS_VGA
+1.8VS_VGA
E
ON ON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
External PCI Devices
Device IDSEL#
REQ#/GNT#
Interrupts
+3VS
(AVDD, VDD33)
RS880M power on sequence
+1.8VS
+1.1VS PLL Rails
(PLLVDD, IOPLLVDD)
+NB_CORE
3 3
EC SM Bus1 address
Device
Smart Battery
Address Address
HEX
16H
SB710
SM Bus 0 address
Device
Clock Generator
(SILEGO SLG8SP626)
DDR DIMM1
DDR DIMM2
Mini card
4 4
A
Address
1101 001Xb
1001 000Xb
1001 010Xb
HEX
D2
90
94
EC SM Bus2 address
Device
ADI ADM1032 (CPU)
GMT G781-1 (GPU)
SB-Temp Sensor
1001 100X b0001 011X b
1001 101X b
SB710
SM Bus 1 address
Device Address
New card
B
HEX
98H
9AH
9CH
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-5971P
LA-5971P
LA-5971P
E
3 49Thursday, December 10, 2009
3 49Thursday, December 10, 2009
3 49Thursday, December 10, 2009
1.0
1.0
1.0
A
1 1
B
C
D
E
+1.2V_HT
250 mil
1
C755
H_CADIP[0..15](10)
H_CADIP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADOP[0..15] (10)
H_CADON[0..15] (10)H_CADIN[0..15](10)
C755
10U_0805_6.3V4Z
10U_0805_6.3V4Z
2
1
C727
C727
10U_0805_6.3V4Z
10U_0805_6.3V4Z
2
1
C666
C666
10U_0805_6.3V4Z
10U_0805_6.3V4Z
2
VLDT CAP.
1
C725
C725
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
2
C726
C726
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C722
C722
180P_0402_50V8J
180P_0402_50V8J
2
1
C668
C668
180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket
+1.2V_HT
2 2
VLDT=1.5A
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
3 3
H_CLKIP0(10)
H_CLKIN0(10)
H_CLKIP1(10)
H_CLKIN1(10)
H_CTLIP0(10)
H_CTLIP1(10) H_CTLOP1 (10)
H_CTLIN1(10)
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
6090022100G_B
6090022100G_B
JCPU1A
JCPU1A
HT LINK
HT LINK
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
ME@
ME@
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
+1.2V_HT
1 2
C664 10U_0805_6.3V4ZC664 10U_0805_6.3V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CLKOP0 (10)
H_CLKON0 (10)
H_CLKOP1 (10)
H_CLKON1 (10)
H_CTLOP0 (10)
H_CTLON0 (10)H_CTLIN0(10)
H_CTLON1 (10)
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G3 HT I/F
AMD CPU S1G3 HT I/F
AMD CPU S1G3 HT I/F
LA-5971P
LA-5971P
LA-5971P
4 49Thursday, December 10, 2009
4 49Thursday, December 10, 2009
4 49Thursday, December 10, 2009
E
1.0
1.0
1.0
A
B
C
D
E
PLACE CLOSE TO PROCESSOR
WITHIN 1.2 INCH
AD10
AF10
AE10
AA16
D10
C10
B10
H16
T19
V22
U21
V19
T20
U19
U20
V20
N19
N20
E16
F16
Y16
P19
P20
N21
M20
N22
M19
M22
M24
K22
R21
K20
V24
K24
K19
R20
R23
R19
T22
T24
J22
J20
L20
L21
L19
L22
J21
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
VTT1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT2
VTT3
VTT4
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
6090022100G_B
6090022100G_B
ME@
ME@
JCPU1B
JCPU1B
1
2
1
2
1
2
1
2
VTT5
VTT6
VTT7
VTT8
VTT9
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
C888
C888
1.5P_0402_50V9C
1.5P_0402_50V9C
C891
C891
1.5P_0402_50V9C
1.5P_0402_50V9C
C890
C890
1.5P_0402_50V9C
1.5P_0402_50V9C
C889
C889
1.5P_0402_50V9C
1.5P_0402_50V9C
W10
AC10
AB10
AA10
A10
Y10
W17
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
+0.9V+0.9V
VTT_SENSE
+MCH_REF
DDRB_ODT0
DDRB_ODT1
DDRB_SCS1#
DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#DDRA_CLK1#
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
T4PAD T4PAD
DDRB_ODT0 (9)
DDRB_ODT1 (9)
DDRB_SCS1# (9)
DDRB_CKE0 (9)
DDRB_CKE1 (9)
DDRB_CLK0 (9)
DDRB_CLK0# (9)
DDRB_CLK1 (9)
DDRB_CLK1# (9)
DDRB_SBS0# (9)
DDRB_SBS1# (9)
DDRB_SBS2# (9)
DDRB_SRAS# (9)
DDRB_SCAS# (9)
DDRB_SWE# (9)
1 1
2 2
3 3
4 4
+1.8V
R78
R78
1K_0402_1%
1K_0402_1%
1 2
+MCH_REF
1
R79
R79
1K_0402_1%
1K_0402_1%
1 2
Place them clos e to CPU withi n 1"
DDRA_SMA[15..0](8) DDRB_SMA[15..0] (9)
1
C178
C178
C177
2
C177
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
1000P_0402_25V8J
VTT=0.75A
R77 39.2_0402_1%R77 39.2_0402_1%
1 2
+1.8V
DDRA_ODT0(8)
DDRA_ODT1(8)
DDRA_SCS0#(8)
DDRA_SCS1#(8) DDRB_SCS0# (9)
DDRA_CKE0(8)
DDRA_CKE1(8)
DDRA_CLK0(8)
DDRA_CLK0#(8)
DDRA_CLK1(8)
DDRA_CLK1#(8)
DDRA_SBS0#(8)
DDRA_SBS1#(8)
DDRA_SBS2#(8)
DDRA_SRAS#(8)
DDRA_SCAS#(8)
DDRA_SWE#(8)
1 2
R76 39.2_0402_1%R76 39.2_0402_1%
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1# DDRB_SCS0#
DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
DDRB_SDQ[63..0](9)
DDRB_SDM[7..0](9) DDRA_SDM[7..0] (8)
DDRB_SDQS0(9)
DDRB_SDQS0#(9)
DDRB_SDQS1(9)
DDRB_SDQS1#(9)
DDRB_SDQS2(9)
DDRB_SDQS2#(9)
DDRB_SDQS3(9)
DDRB_SDQS3#(9)
DDRB_SDQS4(9)
DDRB_SDQS4#(9)
DDRB_SDQS5(9)
DDRB_SDQS5#(9)
DDRB_SDQS6(9)
DDRB_SDQS6#(9)
DDRB_SDQS7(9)
DDRB_SDQS7#(9)
Processor DDR2 Memory Interface
JCPU1C
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
AE14
AF14
AF11
AD11
AB26
AE22
AC16
AD12
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
Y11
A12
B16
A22
E25
C12
B12
D16
C16
A24
A23
F26
E26
JCPU1C
6090022100G_B
6090022100G_B
ME@
ME@
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MEM:DATA
MEM:DATA
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_SDQ[63..0] (8)
DDRA_SDQS0 (8)
DDRA_SDQS0# (8)
DDRA_SDQS1 (8)
DDRA_SDQS1# (8)
DDRA_SDQS2 (8)
DDRA_SDQS2# (8)
DDRA_SDQS3 (8)
DDRA_SDQS3# (8)
DDRA_SDQS4 (8)
DDRA_SDQS4# (8)
DDRA_SDQS5 (8)
DDRA_SDQS5# (8)
DDRA_SDQS6 (8)
DDRA_SDQS6# (8)
DDRA_SDQS7 (8)
DDRA_SDQS7# (8)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G3 DDRII I/F
AMD CPU S1G3 DDRII I/F
AMD CPU S1G3 DDRII I/F
LA-5971P
LA-5971P
LA-5971P
5 49Thursday, December 10, 2009
5 49Thursday, December 10, 2009
5 49Thursday, December 10, 2009
E
1.0
1.0
1.0
A
+2.5VS
1
+
+
C918
C918
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
1 1
CLK_CPU_BCLK(20)
CLK_CPU_BCLK#(20)
+1.8VS
R557
R557
300_0402_5%
300_0402_5%
1 2
LDT_RST#(23)
2 2
H_PWRGD(23)
LDT_STOP#(11,23)
3 3
+3VS
1
C206
C206
4 4
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C194
C194
1 2
3300P_0402_50V7K
3300P_0402_50V7K
LDT_RST#
1
C721
C721
0.01U_0402_16V7K
0.01U_0402_16V7K
@
@
2
+1.8VS
R558
R558
300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C720
C720
0.01U_0402_16V7K
0.01U_0402_16V7K
@
@
2
+1.8VS
R556
R556
300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C719
C719
0.01U_0402_16V7K
0.01U_0402_16V7K
@
@
2
THERMDA_CPU
THERMDC_CPU
1
2
3
Address
A
2
C723
C723
C724 3900P_0402_50V7KC724 3900P_0402_50V7K
U10
U10
VDD
SCLK
D+
SDATA
ALERT#
D-
THERM#4GND
ADM1032ARMZ_MSOP8
ADM1032ARMZ_MSOP8
1001 100X b
1 2
1 2
8
7
6
5
1 2
MBK1608221YZF_0603
MBK1608221YZF_0603
1
C296
C296
2
180P_0402_50V8J
180P_0402_50V8J
close to L35
3900P_0402_50V7K
3900P_0402_50V7K
12
R455
R455
169_0402_1%
169_0402_1%
EC_SMB_CK2
EC_SMB_DA2
L63
L63
B
+2.5VDDA
3300P_0402_50V7K
3300P_0402_50V7K
1
1
C9414.7U_0805_10V4Z C9414.7U_0805_10V4Z
2
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
+1.8V
R70 390_0402_5%R70 390_0402_5%
+1.8V
R71 390_0402_5%@R71 390_0402_5 %@
R82 44.2_0402_1%R82 44.2_0402_1%
R89 44.2_0402_1%R89 44.2_0402_1%
+1.2V_HT
EC_SMB_CK2 (33)
EC_SMB_DA2 (33)
B
C938
C938
12
12
1 2
1 2
CPU_VDD0_FB_H(47)
CPU_VDD0_FB_L(47)
CPU_VDD1_FB_H(47)
CPU_VDD1_FB_L(47)
T25 PADT25 PAD
T26 PADT26 PAD
T37 PADT37 PAD
T33 PADT33 PAD
T43 PADT43 PAD
T42 PADT42 PAD
T3 PADT3 PAD
T41 PADT41 PAD
T2 PADT2 PAD
VDDA=0.25A
1
C880
C880
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
LDT_RST#
H_PWRGD
LDT_STOP#
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
T44 PADT44 PAD
R227 0_0402_5%R 227 0_0402_5%
1 2
C
JCPU1D
JCPU1D
CPU_SIC
CPU_SID
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_VDD1_FB_L
CPU_TEST23
CPU_TEST18
CPU_TEST19
CPU_TEST25H
CPU_TEST25L
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
CPU_TEST6
AF4
AF5
AE6
AB6
G10
AA9
AC9
AD9
AF9
AD7
H10
AB8
AF7
AE7
AE8
AC8
AF8
AA6
F8
F9
A9
A8
B7
A7
F10
C6
R6
P6
F6
E6
Y6
G9
E9
E8
C2
A3
A5
B3
B5
C1
VDDA1
VDDA2
CLKIN_H
CLKIN_L
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
SIC
SID
ALERT_L
HT_REF0
HT_REF1
VDD0_FB_H
VDD0_FB_L
VDD1_FB_H
VDD1_FB_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST23
TEST18
TEST19
TEST25_H
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
6090022100G_B
6090022100G_B
ME@
ME@
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
KEY1
KEY2
SVC
SVD
MEMHOT_L
THERMDC
THERMDA
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
M11
W18
CPU_SVC
A6
CPU_SVD
A4
CPU_THERMTRIP#_R
AF6
H_PROCHOT#
AC7
AA8
THERMDC_CPU
W7
THERMDA_CPU
W8
W9
Y9
H6
G6
E10
AE9
J7
H8
D7
E7
F7
C7
C3
K8
C4
C9
C8
H18
H19
AA7
D5
C5
T5PAD T5PAD
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_DBREQ#
CPU_TDO
CPU_TEST28_H_PLLCHRZ _P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
CPU_TEST7
CPU_TEST10
CPU_TEST8
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
+1.8V
R117220_0402_5%@R117220_0402_5%
12
CPU_DBREQ#
CPU_DBRDY
@
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
CPU_SVC (47)
CPU_SVD (47)
VDDIO (43)
R118220_0402_5%@R118220_0402_5%
R119220_0402_5%@R119220_0402_5%
12
12
@
@
CPU_VDDNB_FB_H (47)
CPU_VDDNB_FB_L (47)
R120300_0402_5%@R120300_0402_5%
R555300_0402_5%R555300_0402_5%
12
1 2
@
+1.8V
MP(Remove)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+1.8V
T24PAD T24PAD
T21PAD T21PAD
T34PAD T34PAD
T36PAD T36PAD
T32PAD T32PAD
T38PAD T38PAD
T31PAD T31PAD
T18PAD T18PAD
T67PAD T67PAD
T39PAD T39PAD
T35PAD T35PAD
@ SAMTEC_ASP-68200-07
@
D
1 2
R66 10K_0402_ 5%R66 10K_0402_ 5%
1 2
R67 300_0402_5%R67 300_0402_5%
CPU_THERMTRIP#_R
1 2
+1.8V
R69 300_0402_5%R69 300_0402_5%
H_PROCHOT#
CPU_SVC
CPU_SVD
CPU_TEST25H
CPU_TEST25L
CPU_TEST10
CPU_TEST18
CPU_TEST19
CPU_TEST22
CPU_TEST21
CPU_TEST24
CPU_TEST20
CPU_TEST23
CPU_TEST25H
CPU_TEST25L
JP1
JP1
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
MP(mask)
E
B
B
2
Q9
Q9
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R456 1K_0402_5%R456 1K_0402_5%
1 2
1 2
R549 1K_0402_5%R549 1K_0402_5%
@
@
1 2
R144 510_0402_5%
R144 510_0402_5%
1 2
R143 510_0402_5%R14 3 510_0402_5%
1 2
R101 0_0603_5%@R101 0_0603_5%@
1 2
R950 0_0603_5%@R950 0_0603_5%@
1 2
R951 0_0603_5%@R951 0_0603_5%@
1 2
R952 0_0603_5%@R952 0_0603_5%@
1 2
R75 300_0402_5%R75 300_0402_5%
1 2
R74 300_0402_5%R74 300_0402_5%
1 2
R73 300_0402_5%R73 300_0402_5%
1 2
R72 300_0402_5%R72 300_0402_5%
1 2
R136 510_0402_5%R13 6 510_0402_5%
1 2
R135 510_0402_5%
R135 510_0402_5%
@
@
HDT_RST#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R65
R65
1 2
0_0402_5%
0_0402_5%
R68
R68
1 2
0_0402_5%
0_0402_5%
+1.8V
R140
R140
1 2
0_0402_5%@
0_0402_5%@
+3VS
MP(Remove)
5
U15
U15
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G3 CTRL
AMD CPU S1G3 CTRL
AMD CPU S1G3 CTRL
2
P
B
Y
1
A
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
@
@
LA-5971P
LA-5971P
LA-5971P
H_PROCHOT_R# (23,33)
+1.8V
E
H_THERMTRIP# (24)
LDT_RST#
SB_PWRGD (11,24,33)
6 49Thursday, December 10, 2009
6 49Thursday, December 10, 2009
6 49Thursday, December 10, 2009
1.0
1.0
1.0
A
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
1
+
+
C939
1 1
C939
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
+
+
C661
C661
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
+CPU_CORE_0
1
C914
C914
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE_0
1
C887
C887
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2 2
1
C911
C911
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C276
C276
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C273
C273
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C921
C921
180P_0402_50V8J
180P_0402_50V8J
2
1
C915
C915
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
VDDIO decoupling.
+1.8V
1
C195
C195
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C228
C228
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C222
C222
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
1
C886
C886
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
+CPU_CORE_1
+CPU_CORE_1
1
C214
C214
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C919
C919
180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C96
C96
330U_X_2VM_R6M
330U_X_2VM_R6M
2
+CPU_CORE_1
1
C274
C274
180P_0402_50V8J
180P_0402_50V8J
2
1
C238
C238
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C882
C882
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C
VDD0 = 18A VDD1 =18A
JCPU1E
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
K16
M16
P16
T16
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
6090022100G_B
6090022100G_B
Athlon 64 S1
Processor Socket
ME@
ME@
JCPU1E
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
1
+
+
C643
C643
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C227
C227
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C9
C9
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C215
C215
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C230
C230
180P_0402_50V8J
180P_0402_50V8J
2
+CPU_CORE_0
VDDNB=4A
(For Tigris)
VDDNB=3A
+CPU_CORE_NB
+1.8V
VDDIO=3A
+CPU_CORE_NB decoupling.
+CPU_CORE_NB
1
C207
C207
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C910
C910
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C913
C913
22U_0805_6.3V6M
22U_0805_6.3V6M
2
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
D
JCPU1F
JCPU1F
AA4
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+CPU_CORE_1
+1.8V
AA11
AA13
AA15
AA17
AA19
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AB2
AB7
AB9
AD6
AD8
B11
B13
B15
B17
B19
B21
B23
B25
D11
D13
D15
D17
D19
D21
D23
D25
H21
H23
B4
B6
B8
B9
D6
D8
D9
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
J4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
6090022100G_B
6090022100G_B
Athlon 64 S1
Processor Socket
ME@
ME@
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
E
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
3 3
4 4
+1.8V
1
C301
C301
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C309
C309
0.01U_0402_16V7K
0.01U_0402_16V7K
2
+1.8V
1
2
Between CPU Socket and DIMM
C211
C211
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C302
C302
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C307
C307
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C209
C209
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C303
C303
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
180PF Qt'y foll ow the distanc e between
CPU socket and DIMM0. <2.5inc h>
1
C218
C218
180P_0402_50V8J
180P_0402_50V8J
2
1
C208
C208
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C300
C300
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C308
C308
180P_0402_50V8J
180P_0402_50V8J
2
1
C210
C210
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C310
C310
180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C226
C226
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C219
C219
180P_0402_50V8J
180P_0402_50V8J
2
VTT decoupling.
220U_D2_4VM_R15
220U_D2_4VM_R15
+0.9V
1
C943
C943
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+0.9V
1
C942
C942
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C945
C945
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side.
1
C944
C944
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C883
C883
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C884
C884
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+0.9V
Near Power Supply
1
C937
C937
C: Change to NP O CAP
+
+
2
1
C885
C885
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C881
C881
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C912
C912
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C893
C893
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C718
C718
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C892
C892
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C717
C717
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C920
C920
180P_0402_50V8J
180P_0402_50V8J
2
1
C716
C716
180P_0402_50V8J
180P_0402_50V8J
2
1
C922
C922
180P_0402_50V8J
180P_0402_50V8J
2
1
C715
C715
180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket Left side.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G3 PWR & GND
AMD CPU S1G3 PWR & GND
AMD CPU S1G3 PWR & GND
LA-5971P
LA-5971P
LA-5971P
7 49Thursday, December 10, 2009
7 49Thursday, December 10, 2009
7 49Thursday, December 10, 2009
E
1.0
1.0
1.0
A
+1.8V +1.8V
JDIMM1
JDIMM1
+V_DDR_MCH_REF
DDRA_SDQS0#(5)
1 1
2 2
3 3
4 4
DDRA_SDQS0(5)
DDRA_SDQS1#(5)
DDRA_SDQS1(5)
DDRA_SDQS2#(5)
DDRA_SDQS2(5)
DDRA_CKE0(5)
DDRA_SBS2#(5)
DDRA_SBS0#(5)
DDRA_SWE#(5)
DDRA_SCAS#(5)
DDRA_SCS1#(5)
DDRA_ODT1(5)
DDRA_SDQS4#(5)
DDRA_SDQS4(5)
DDRA_SDQS6#(5)
DDRA_SDQS6(5)
SB_SMBDATA(9,20,24,31)
SB_SMBCLK(9,20,24,31)
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25 DDRA_SDQ29
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
SB_SMBDATA
SB_SMBCLK
+3VS
+3VS
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_292527-4
TYCO_292527-4
ME@
ME@
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
GND
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDM0
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1DDRA_CKE0
DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ63
R39 10K_0402_5%R39 10K_0402_5%
1 2
R36 10K_0402_5%R36 10K_0402_5%
1 2
DDRA_CLK0 (5)
DDRA_CLK0# (5)
DDRA_SDQS3# (5)
DDRA_SDQS3 (5)
DDRA_CKE1 (5)
DDRA_SBS1# (5)
DDRA_SRAS# (5)
DDRA_SCS0# (5)
DDRA_ODT0 (5)
DDRA_SDQS5# (5)
DDRA_SDQS5 (5)
DDRA_CLK1 (5)
DDRA_CLK1# (5)
DDRA_SDQS7# (5)
DDRA_SDQS7 (5)
C
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+1.8V
+V_DDR_MCH_REF
1
1
C923
C923
C894
C894
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1000P_0402_25V8J
1000P_0402_25V8J
Check layout place
DDRA_SDQ[0..63] (5)
DDRA_SDM[0..7] (5)
DDRA_SMA[0..15] (5)
R147
R147
1K_0402_1%
1K_0402_1%
1 2
R148
R148
1K_0402_1%
1K_0402_1%
1 2
+V_DDR_MCH_REF
D
DDRA_SMA6
DDRA_SMA7
DDRA_SMA15
DDRA_SMA11
DDRA_SBS2#
DDRA_CKE0
DDRA_SMA14
DDRA_CKE1
DDRA_SBS1#
DDRA_SMA0
DDRA_SMA2
DDRA_SMA4
DDRA_SMA5
DDRA_SMA8
DDRA_SMA9
DDRA_SMA12
DDRA_SBS0#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3
DDRA_SCS1#
DDRA_ODT1
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_ODT0
DDRA_SCS0#
DDRA_SRAS#
RP10
RP10
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP13
RP13
47_0804_8P4R_5%
47_0804_8P4R_5%
RP8
RP8
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP9
RP9
47_0804_8P4R_5%
47_0804_8P4R_5%
RP7
RP7
47_0804_8P4R_5%
47_0804_8P4R_5%
RP4
RP4
47_0804_8P4R_5%
47_0804_8P4R_5%
RP3
RP3
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
EMI
+1.8V
C13 0.1U_0402_16V4Z
C13 0.1U_0402_16V4Z
C175 0.1U_0402_16V4Z
C175 0.1U_0402_16V4Z
C176 0.1U_0402_16V4Z
C176 0.1U_0402_16V4Z
+0.9V
C16 0.1U_0402_16V4ZC16 0.1U_0402_16V4Z
C198 0.1U_0402_16V4ZC198 0.1U_0402_16V4Z
18
C225 0.1U_0402_16V4ZC225 0.1U_0402_16V4Z
27
36
C223 0.1U_0402_16V4ZC223 0.1U_0402_16V4Z
45
C159 0.1U_0402_16V4ZC159 0.1U_0402_16V4Z
C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z
18
C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z
27
36
C17 0.1U_0402_16V4ZC17 0.1U_0402_16V4Z
45
18
C169 0.1U_0402_16V4ZC169 0.1U_0402_16V4Z
27
36
C15 0.1U_0402_16V4ZC15 0.1U_0402_16V4Z
45
18
C157 0.1U_0402_16V4ZC157 0.1U_0402_16V4Z
27
36
C142 0.1U_0402_16V4ZC142 0.1U_0402_16V4Z
45
C145 0.1U_0402_16V4ZC145 0.1U_0402_16V4Z
C18 0.1U_0402_16V4ZC18 0.1U_0402_16V4Z
1 2
@
@
1 2
@
@
1 2
@
@
E
+1.8V
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C936
C936
C14
C14
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2.2U_0805_10V6K
2.2U_0805_10V6K
A
1
2
DIMM1 REV H:5.2mm (BOT)
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
LA-5971P
LA-5971P
LA-5971P
E
8 49Thursday, December 10, 2009
8 49Thursday, December 10, 2009
8 49Thursday, December 10, 2009
1.0
1.0
1.0
A
B
C
D
E
+V_DDR_MCH_REF
1
C933
C933
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1 1
2 2
3 3
4 4
DDRB_SDQS0#(5)
DDRB_SDQS0(5)
DDRB_SDQS1#(5)
DDRB_SDQS1(5)
DDRB_SDQS2#(5)
DDRB_SDQS2(5)
DDRB_CKE0(5)
DDRB_SBS2#(5)
DDRB_SBS0#(5)
DDRB_SWE#(5)
DDRB_SCAS#(5)
DDRB_SCS1#(5)
DDRB_ODT1(5)
DDRB_SDQS4#(5)
DDRB_SDQS4(5)
DDRB_SDQS6#(5)
DDRB_SDQS6(5)
SB_SMBDATA(8,20,24,31)
SB_SMBCLK(8,20,24,31)
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26 DDRB_SDQ30
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
SB_SMBDATA
SB_SMBCLK
+3VS
+1.8V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
JDIMM2
JDIMM2
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
NC/CKE1
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
FOX_AS0A426-NARN-7F~N
FOX_AS0A426-NARN-7F~N
ME@
ME@
DIMM2 REV H:9.2mm (BOT)
A
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
CK0
BA1
CK1
SA1
+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
B
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
DDRB_SDQ31
DDRB_CKE1
DDRB_SMA15
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
R37 10K_0402_5%R37 10K_0402_5%
1 2
R35 10K_0402_5%R35 10K_0402_5%
1 2
DDRB_CLK0 (5)
DDRB_CLK0# (5)
DDRB_SDQS3# (5)
DDRB_SDQS3 (5)
DDRB_CKE1 (5)
DDRB_SBS1# (5)
DDRB_SRAS# (5)
DDRB_SCS0# (5)
DDRB_ODT0 (5)
DDRB_SDQS5# (5)
DDRB_SDQS5 (5)
DDRB_CLK1 (5)
DDRB_CLK1# (5)
DDRB_SDQS7# (5)
DDRB_SDQS7 (5)
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
DDRB_SDQ[0..63] (5)
DDRB_SDM[0..7] (5)
DDRB_SMA[0..15] (5)
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
DDRB_SRAS#
DDRB_SMA0
DDRB_SMA2
DDRB_SMA4
DDRB_SMA6
DDRB_SMA7
DDRB_SMA11
DDRB_SMA14
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA15
DDRB_CKE1
DDRB_SMA8
DDRB_SMA5
DDRB_SMA9
DDRB_SMA12
DDRB_SBS0#
DDRB_SMA10
DDRB_SMA3
DDRB_SMA1
DDRB_ODT1
DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_ODT0
DDRB_SCS0#
DDRB_SBS1#
D
RP6
RP6
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP12
RP12
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP14
RP14
47_0804_8P4R_5%
47_0804_8P4R_5%
RP11
RP11
47_0804_8P4R_5%
47_0804_8P4R_5%
RP5
RP5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP1
RP1
47_0804_8P4R_5%
47_0804_8P4R_5%
RP2
RP2
1 8
2 7
3 6
4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
+0.9V
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
12
C171 0.1U_0402_16V4ZC171 0.1U_0402_16V4Z
1 2
C201 0.1U_0402_16V4ZC201 0.1U_0402_16V4Z
12
C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z
1 2
C20 0.1U_0402_16V4ZC20 0.1U_0402_16V4Z
12
C200 0.1U_0402_16V4ZC200 0.1U_0402_16V4Z
1 2
C231 0.1U_0402_16V4ZC231 0.1U_0402_16V4Z
12
C21 0.1U_0402_16V4ZC21 0.1U_0402_16V4Z
1 2
C197 0.1U_0402_16V4ZC197 0.1U_0402_16V4Z
12
C146 0.1U_0402_16V4ZC146 0.1U_0402_16V4Z
1 2
C19 0.1U_0402_16V4ZC19 0.1U_0402_16V4Z
12
C122 0.1U_0402_16V4ZC122 0.1U_0402_16V4Z
1 2
C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z
12
C147 0.1U_0402_16V4ZC147 0.1U_0402_16V4Z
1 2
C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRII SO-DIMM 2
DDRII SO-DIMM 2
DDRII SO-DIMM 2
+1.8V
LA-5971P
LA-5971P
LA-5971P
9 49Thursday, December 10, 2009
9 49Thursday, December 10, 2009
9 49Thursday, December 10, 2009
E
1.0
1.0
1.0
A
B
C
D
E
PCIE_GTX_C_MRX_P[0..15](14)
PCIE_GTX_C_MRX_N[0..15](14)
1 1
2 2
PCIE_PTX_C_IRX_P1(31)
PCIE_PTX_C_IRX_N1(31)
PCIE_PTX_C_IRX_P2(30)
PCIE_PTX_C_IRX_N2(30)
PCIE_PTX_C_IRX_P4(31)
PCIE_PTX_C_IRX_N4(31)
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
SB_RX0P(23)
SB_RX0N(23)
SB_RX1P(23)
SB_RX1N(23)
SB_RX2P(23)
SB_RX2N(23)
SB_RX3P(23)
SB_RX3N(23)
U20B
U20B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS880M_FCBGA528
RS880M_FCBGA528
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALR P)
PCE_CALRN(PCE_BCALR N)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0
A5
B5
PCIE_MTX_GRX_P1
A4
PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1
B4
PCIE_MTX_GRX_P2
C3
PCIE_MTX_GRX_N2
B2
PCIE_MTX_GRX_P3
D1
PCIE_MTX_GRX_N3
D2
PCIE_MTX_GRX_P4
E2
PCIE_MTX_GRX_N4
E1
PCIE_MTX_GRX_P5
F4
PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5
F3
PCIE_MTX_GRX_P6
F1
PCIE_MTX_GRX_N6
F2
PCIE_MTX_GRX_P7
H4
PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7
H3
PCIE_MTX_GRX_P8
H1
PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8
H2
PCIE_MTX_GRX_P9
J2
PCIE_MTX_GRX_N9
J1
PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10
K4
PCIE_MTX_GRX_N10
K3
PCIE_MTX_GRX_P11
K1
PCIE_MTX_GRX_N11
K2
PCIE_MTX_GRX_P12
M4
PCIE_MTX_GRX_N12
M3
PCIE_MTX_GRX_P13
M1
PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13
M2
PCIE_MTX_GRX_P14
N2
PCIE_MTX_GRX_N14
N1
PCIE_MTX_GRX_P15
P1
PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15
P2
AC1
AC2
PCIE_ITX_PRX_P1
AB4
PCIE_ITX_PRX_N1
AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
Y1
Y2
PCIE_ITX_PRX_P4
Y4
PCIE_ITX_PRX_N4
Y3
V1
V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
AC8
AB8
R32 1.27K_0402_1%R32 1.27K_0402_1%
R267 2K_0402_1%R267 2K_0402_1%
RS780M Display Port Support (muxed on GFX)
DP0
3 3
4 4
DP1
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
C646 0.1U_0402_10V7KVGA@C646 0.1U_0402_10V7KVGA@
1 2
C648 0.1U_0402_10V7KVGA@C648 0.1U_0402_10V7KVGA@
1 2
C650 0.1U_0402_10V7KVGA@C650 0.1U_0402_10V7KVGA@
1 2
C652 0.1U_0402_10V7KVGA@C652 0.1U_0402_10V7KVGA@
1 2
C356 0.1U_0402_10V7KVGA@C356 0.1U_0402_10V7KVGA@
1 2
C657 0.1U_0402_10V7KVGA@C657 0.1U_0402_10V7KVGA@
1 2
C365 0.1U_0402_10V7KVGA@C365 0.1U_0402_10V7KVGA@
1 2
C641 0.1U_0402_10V7KVGA@C641 0.1U_0402_10V7KVGA@
1 2
C636 0.1U_0402_10V7KVGA@C636 0.1U_0402_10V7KVGA@
1 2
C635 0.1U_0402_10V7KVGA@C635 0.1U_0402_10V7KVGA@
1 2
C632 0.1U_0402_10V7KVGA@C632 0.1U_0402_10V7KVGA@
1 2
C360 0.1U_0402_10V7KVGA@C360 0.1U_0402_10V7KVGA@
1 2
C627 0.1U_0402_10V7KVGA@C627 0.1U_0402_10V7KVGA@
1 2
C623 0.1U_0402_10V7KVGA@C623 0.1U_0402_10V7KVGA@
1 2
C624 0.1U_0402_10V7KVGA@C624 0.1U_0402_10V7KVGA@
1 2
C361 0.1U_0402_10V7KVGA@C361 0.1U_0402_10V7KVGA@
1 2
WLAN@
WLAN@
WLAN@
WLAN@
C614 0.1U_0402_10V7K
C614 0.1U_0402_10V7K
1 2
C362 0.1U_0402_10V7K
C362 0.1U_0402_10V7K
1 2
C357 0.1U_0402_10V7KC357 0.1U_0402_10V7K
1 2
C618 0.1U_0402_10V7KC618 0.1U_0402_10V7K
1 2
C964 0.1U_0402_10V7K
C964 0.1U_0402_10V7K
1 2
C965 0.1U_0402_10V7K
C965 0.1U_0402_10V7K
1 2
NEWCARD@
NEWCARD@
NEWCARD@
NEWCARD@
C352 0.1U_0402_10V7KC352 0.1U_0402_10V7K
1 2
C609 0.1U_0402_10V7KC609 0.1U_0402_10V7K
1 2
C38 0.1U_0402_10V7KC38 0.1U_0402_10V7K
1 2
C33 0.1U_0402_10V7KC33 0.1U_0402_10V7K
1 2
C37 0.1U_0402_10V7KC37 0.1U_0402_10V7K
1 2
C32 0.1U_0402_10V7KC32 0.1U_0402_10V7K
1 2
C610 0.1U_0402_10V7KC610 0.1U_0402_10V7K
1 2
C616 0.1U_0402_10V7KC616 0.1U_0402_10V7K
1 2
1 2
1 2
C358 0.1U_0402_10V7KVGA@C358 0.1U_0402_10V7KVGA@
C649 0.1U_0402_10V7KVGA@C649 0.1U_0402_10V7KVGA@
C651 0.1U_0402_10V7KVGA@C651 0.1U_0402_10V7KVGA@
C653 0.1U_0402_10V7KVGA@C653 0.1U_0402_10V7KVGA@
C366 0.1U_0402_10V7KVGA@C366 0.1U_0402_10V7KVGA@
C876 0.1U_0402_10V7KVGA@C876 0.1U_0402_10V7KVGA@
C658 0.1U_0402_10V7KVGA@C658 0.1U_0402_10V7KVGA@
C364 0.1U_0402_10V7KVGA@C364 0.1U_0402_10V7KVGA@
C638 0.1U_0402_10V7KVGA@C638 0.1U_0402_10V7KVGA@
C637 0.1U_0402_10V7KVGA@C637 0.1U_0402_10V7KVGA@
C634 0.1U_0402_10V7KVGA@C634 0.1U_0402_10V7KVGA@
C631 0.1U_0402_10V7KVGA@C631 0.1U_0402_10V7KVGA@
C629 0.1U_0402_10V7KVGA@C629 0.1U_0402_10V7KVGA@
C363 0.1U_0402_10V7KVGA@C363 0.1U_0402_10V7KVGA@
C359 0.1U_0402_10V7KVGA@C359 0.1U_0402_10V7KVGA@
C621 0.1U_0402_10V7KVGA@C621 0.1U_0402_10V7KVGA@
+1.1VS
PCIE_MTX_C_GRX_P[0..15] (14)
PCIE_MTX_C_GRX_N[0..15] (14)
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCIE_ITX_C_PRX_P1 (31)
PCIE_ITX_C_PRX_N1 (31)
PCIE_ITX_C_PRX_P2 (30)
PCIE_ITX_C_PRX_N2 (30)
PCIE_ITX_C_PRX_P4 (31)
PCIE_ITX_C_PRX_N4 (31)
SB_TX0P (23)
SB_TX0N (23)
SB_TX1P (23)
SB_TX1N (23)
SB_TX2P (23)
SB_TX2N (23)
SB_TX3P (23)
SB_TX3N (23)
PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
WLAN
LAN
New Card
H_CLKOP0(4)
H_CLKON0(4)
H_CLKOP1(4)
H_CLKON1(4)
H_CTLOP0(4)
H_CTLON0(4)
H_CTLON1(4)
R56
R56
1 2
301_0402_1%
0718 Place within 1"
layout 1:2
301_0402_1%
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
H_CADOP[0..15](4)
H_CADON[0..15](4) H_CADIN[0..15] (4)
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
H_CADON[0..15]
U20A
U20A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS880M_FCBGA528
RS880M_FCBGA528
H_CADIP[0..15] (4)
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H24
H25
L21
L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
B24
B25
0718 Place within 1"
layout 1:2
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA
H_CLKIP0 (4)
H_CLKIN0 (4)
H_CLKIP1 (4)
H_CLKIN1 (4)
H_CTLIP0 (4)
H_CTLIN0 (4)
H_CTLIP1 (4)H_CTLOP1(4)
H_CTLIN1 (4)
R51
R51
1 2
301_0402_1%
301_0402_1%
SA000032710 S IC 216-0752001 A11 RS880M FCBGA528 0FA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS880-HT/PCIE
RS880-HT/PCIE
RS880-HT/PCIE
LA-5971P
LA-5971P
LA-5971P
E
1.0
1.0
10 49Thursday, December 10, 2009
10 49Thursday, December 10, 2009
10 49Thursday, December 10, 2009
1.0
A
For RS780M A13
RED: Connected to GND through two separate 140ohm 1% resistor
UMA@
UMA@
1 2
R45 140_0402_1%
R45 140_0402_1%
UMA@
UMA@
1 2
R49 150_0402_1%
R49 150_0402_1%
UMA@
UMA@
1 2
R50 150_0402_1%
1 1
+1.1VS
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
FBMA-L11-160808-221LMT_0603
2 2
3 3
4 4
FBMA-L11-160808-221LMT_0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
CLK_NB_14.318M
12
R477
R477
100_0402_5%
100_0402_5%
@
@
1
C854
C854
100P_0402_50V8J
100P_0402_50V8J
2
@
@
+3VS
+3VS
12
R451
R451
10K_0402_5%
10K_0402_5%
@
@
POWER_SEL
12
R1004
R1004
2K_0402_5%
2K_0402_5%
R563 4.7K_0402_5%
R563 4.7K_0402_5%
R565 4.7K_0402_5%
R565 4.7K_0402_5%
PLLVDD=65mA
L59
L59
L13
L13
L9
L9
L14
L14
ALLOW_LDTSTOP(23)
+NB_PLLVDD
12
1
C645
C645
2
PLLVDD18=20mA
+NB_HTPVDD+1.8VS
12
1
C93
C93
2
VDDA18HTPLL=20mA
+VDDA18HTPLL
12
1
C934
C934
2
VDDA18PCIEPLL=0.12A
+VDDA18PCIEPLL
12
1
C87
C87
2
+1.1VS
UMA@
UMA@
1 2
1 2
UMA@
UMA@
A
1
C663
C663
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
2
1
C84
C84
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
2
1
C924
C924
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
2
1
C86
C86
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
2
4.7K_0402_5%
4.7K_0402_5%
1 2
R564
R564
GMCH_LCD_CLK
GMCH_LCD_DATA
R50 150_0402_1%
NB_PWRGD
SB_PWRGD(6,24,33)
1 2
R566
R566
4.7K_0402_5%
4.7K_0402_5%
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
+1.8VS
+1.8VS
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.8VS
2
1
PLT_RST#(13,14,23,30,31,33)
NB_PWRGD(24)
+1.8VS
R283 300_0402_5%R28 3 300_0402_5%
+1.8VS
R60
R60
1K_0402_5%
1K_0402_5%
1 2
R59 0_0402_5%R5 9 0_0402_5%
1 2
B
+3VS
AVDDDI=20mA
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AVDDQ=4mA
L8
L8
12
1
C935
C935
2
U42
U42
5
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
P
B
4
Y
A
G
3
12
CLK_NBGFX(20)
CLK_NBGFX#(20)
CLK_SBLINK_BCLK(20)
CLK_SBLINK_BCLK#(20)
GMCH_LCD_CLK(21)
GMCH_LCD_DATA(21)
POWER_SEL
HIGH 1.0V
B
AVDD=0.11A
L15
L15
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
1U_0402_6.3V4Z@
L10
L10
+AVDDQ
GMCH_CRT_HSYNC(13,22)
GMCH_CRT_VSYNC(13,22)
R107 0_0402_5%R107 0_0402_ 5%
1 2
1 2
R511 0_0402_5%@R511 0_0402_5%@
POWER_SEL(45)
1U_0402_6.3V4Z@
12
1
C22
C22
2
1
C875
C875
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
@
@
GMCH_CRT_R(22)
GMCH_CRT_G(22)
GMCH_CRT_B(22)
GMCH_CRT_CLK(22)
GMCH_CRT_DATA(22)
R42 715_0402_1%R42 715_0402_1%
+NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
CLK_NBHT(20)
CLK_NBHT#(20)
CLK_NB_14.318M(20)
1.1VLOW
NB_ALLOW_LDTSTOP
12
C874
C874
+AVDD2
1 2
NB_ALLOW_LDTSTOP
CLK_NB_14.318M
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK_R2
GMCH_HDMI_CLK
GMCH_HDMI_DATA
AUX_CAL(13)
Strap pin
+AVDD1
1
1
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
2
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
+NB_PLLVDD
+NB_HTPVDD
NB_RESET#
NB_PWRGD_R
NB_LDTSTOP#
POWER_SEL
C
C94
C94
U20C
U20C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLK P)
V3
GPPSB_REFCLKN(SB_REFCLK N)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS880M_FCBGA528
RS880M_FCBGA528
LDT_STOP#(6,23)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
0_0402_5%
0_0402_5%
1 2
R280
R280
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
C
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM _GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
NB_LDTSTOP#
Compal Secret Data
Compal Secret Data
Compal Secret Data
HPD(NC)
TESTMODE
Deciphered Date
Deciphered Date
Deciphered Date
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
4.7K_0402_5%
4.7K_0402_5%
D9
D10
D12
AE8
AD8
D13
+VDDLTP18
+VDDLT18
12
R469
R469
1 2
R106 0_0402_5%R106 0_0402_5%
1 2
R279
R279
1.8K_0402_5%
1.8K_0402_5%
D
GMCH_TXOUT0+ (21)
GMCH_TXOUT0- (21)
GMCH_TXOUT1+ (21)
GMCH_TXOUT1- (21)
GMCH_TXOUT2+ (21)
GMCH_TXOUT2- (21)
GMCH_TXCLK+ (21)
GMCH_TXCLK- (21)
@
@
R441
R441
1 2
D
R744 0_0402_5%R744 0_0402_5%
1 2
R29
R29
@
@
1 2
1.27K_0402_1%
1.27K_0402_1%
1.27K_0402_1%
1.27K_0402_1%
SUS_STAT# (24)
SUS_STAT_R# (13)
E
VDDLTP18=15mA
+VDDLTP18
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
VDDLT18=0.3A
+VDDLT18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
UMA_ENVDD_R (21)
UMA_VARIBL (21,33)
ENBKL (33)
C665
C665
C90
C90
1
2
1
2
L56
L56
FBMA-L11-160808-221LMT_0603
FBMA-L11-160808-221LMT_0603
1
C644
C644
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
L12
L12
1 2
MBK1608221YZF_0603
MBK1608221YZF_0603
1
C95
C95
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
12
+1.8VS
+1.8VS
Strap pin
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RS880 VEDIO/CLK GEN
RS880 VEDIO/CLK GEN
RS880 VEDIO/CLK GEN
LA-5971P
LA-5971P
LA-5971P
11 49Thursday, December 10, 2009
11 49Thursday, December 10, 2009
11 49Thursday, December 10, 2009
E
1.0
1.0
1.0
A
1 1
2 2
FOR Version A11 pop 1.35VS A12
use 1.2V_HT
3 3
4 4
+1.1VS
MBK2012221YZF_0805
MBK2012221YZF_0805
+1.2V_HT
MBK2012221YZF_0805
MBK2012221YZF_0805
+1.8VS
MBK2012221YZF_0805
MBK2012221YZF_0805
MBK2012221YZF_0805
MBK2012221YZF_0805
L4
L4
12
L5
L5
4.7U_0805_10V4Z
4.7U_0805_10V4Z
L71
L71
4.7U_0805_10V4Z
4.7U_0805_10V4Z
L11
L11
12
C940
C940
4.7U_0805_10V4Z
4.7U_0805_10V4Z
VDDHTTX=0.68A
VDDA18PCIE=0.7A
12
C45
C45
VDDHTRX+VDDHT=1.3A
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
1
1
C341
C344
C344
2
1
C336
C336
C85
C85
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C49
C49
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C40
C40
2
+1.8VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C341
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C931
C931
2
1
C50
C50
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C51
C51
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C89
C89
C612
C612
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C31
C31
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C47
C47
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C928
C928
2
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C342
C342
C925
C925
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C345
C345
C48
C48
2
2
VDD18=10mA
1
2
VDDHTRX=0.7A
+VDDHTRX
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHT
+VDDHTTX
1
2
+VDDA18PCIE
1
2
B
VDDHT=0.6A
U20E
U20E
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS880M_FCBGA528
RS880M_FCBGA528
PART 5/6
PART 5/6
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
POWER
POWER
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
C
VDDPCIE=2.5A
+VDDA11PCIE
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C30 10U_0805_10V4ZC30 10U_0805_10V4Z
C28 10U_0805_10V4ZC28 10U_0805_10V4Z
C29 4.7U_0805_10V4ZC29 4.7U_08 05_10V4Z
C930 1U_0402_6.3V4ZC930 1U_0402_6.3V4Z
C929 1U_0402_6.3V4ZC929 1U_0402_6.3V4Z
C88 0.1U_0402_16V4ZC88 0.1U_04 02_16V4Z
C339 0.1U_0402_16V4ZC339 0.1U_04 02_16V4Z
NB_CORE=10A
C340.1U_0402_16V4Z C340.1U_0402_16V4Z
C430.1U_0402_16V4Z C430.1U_0402_16V4Z
C230.1U_0402_16V4Z C230.1U_0402_16V4Z
C350.1U_0402_16V4Z C350.1U_0402_16V4Z
1
1
1
1
1
C3430.1U_0402_16V4Z C3430.1U_0402_16V4Z
2
2
2
2
2
1
C338
C338
C24
C24
2
L3
L3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C260.1U_0402_16V4Z C260.1U_0402_16V4Z
1
1
1
C3400.1U_0402_16V4Z C3400.1U_0402_16V4Z
C3370.1U_0402_16V4Z C3370.1U_0402_16V4Z
2
2
2
VDD33=60mA
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+3VS
D
U20F
U20F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
+1.1VS
+NB_CORE
C27 330U_D2E_2.5VM+C27 330U_D2E_2.5VM
1
C3610U_0805_10V4Z C3610U_0805_10V4Z
C250.1U_0402_16V4Z C250.1U_0402_16V4Z
C4410U_0805_10V4Z C4410U_0805_10V4Z
1
1
1
+
2
2
2
2
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS780M_FCBGA528
RS780M_FCBGA528
U20D
U20D
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
MEM_A9(NC)
AC16
MEM_A10(NC)
AE13
MEM_A11(NC)
AC14
MEM_A12(NC)
Y14
MEM_A13(NC)
AD16
MEM_BA0(NC)
AE17
MEM_BA1(NC)
AD17
MEM_BA2(NC)
W12
MEM_RASb(NC)
Y12
MEM_CASb(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
AB18
MEM_CKE(NC)
V14
MEM_ODT(NC)
V15
MEM_CKP(NC)
W14
MEM_CKN(NC)
AE12
MEM_COMPP(NC)
AD12
MEM_COMPN(NC)
RS780M_FCBGA528
RS780M_FCBGA528
VSSAPCIE1
PART 6/6
PART 6/6
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
GROUND
GROUND
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
+1.8VS=W/S=20/1 0mil For Memor y PLL power
+1.1VS=W/S=20/1 0mil For Memor y PLL power
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
E
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
15mA
+1.8VS
+1.1VS
26mA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS880 PWR/GND
RS880 PWR/GND
RS880 PWR/GND
LA-5971P
LA-5971P
LA-5971P
E
1.0
1.0
12 49Thursday, December 10, 2009
12 49Thursday, December 10, 2009
12 49Thursday, December 10, 2009
1.0
A
B
C
D
E
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
GMCH_CRT_VSYNC(11,22)
1 1
12
R560 3K_0402_5%R560 3K_0402 _5%
12
R559 3K_0402_5%@R559 3K_0402_5%@
+3VS
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS880m)
0 : Enable (RS880M)
DFT_GPIO1: LOAD_EEPROM_STRAPS
AUX_CAL(11)
RS780 DFT_GPIO1
2 2
SUS_STAT_R#(11) PLT_RST# (11,14,23,30,31,33)
1 2
R284 150_0402_1%@R284 150_0402_1%@
D29
D29
CH751H-40_SC76@
CH751H-40_SC76@
2 1
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RS780 use HSYNC to enable SIDE PORT
RS780 use HSYNC to enable SIDE PORT
GMCH_CRT_HSYNC(11,22)
12
R281 3K_0402_5%R281 3K_0402 _5%
@
@
12
R282 3K_0402_5%
R282 3K_0402_5%
+3VS
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS880M)
1 : Disable(RS880M)
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS880 STRAPS
RS880 STRAPS
RS880 STRAPS
LA-5971P
LA-5971P
LA-5971P
E
1.0
1.0
13 49Thursday, December 10, 2009
13 49Thursday, December 10, 2009
13 49Thursday, December 10, 2009
1.0
5
U40A
U40A
4
3
2
PCIE_GTX_C_MRX_P[0..15](10)
PCIE_GTX_C_MRX_N[0..15](10)
PCIE_MTX_C_GRX_P[0..15](10)
PCIE_MTX_C_GRX_N[0..15](10)
1
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P0
D D
C C
B B
CLK_PCIE_VGA(20)
CLK_PCIE_VGA#(20 )
A A
VGA_PWROK(44)
PLT_RST#
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
CLK_PCIE_VGA
CLK_PCIE_VGA#
PARK@
PARK@
R293 10K_0402_5%
R293 10K_0402_5%
5
R127
R127
1 2
0_0402_5%@
0_0402_5%@
PLT_RST#
12
AF30
PCIE_RX0P
AE31
PCIE_RX0N
AE29
PCIE_RX1P
AD28
PCIE_RX1N
AD30
PCIE_RX2P
AC31
PCIE_RX2N
AC29
PCIE_RX3P
AB28
PCIE_RX3N
AB30
PCIE_RX4P
AA31
PCIE_RX4N
AA29
PCIE_RX5P
Y28
PCIE_RX5N
Y30
PCIE_RX6P
W31
PCIE_RX6N
W29
PCIE_RX7P
V28
PCIE_RX7N
V30
PCIE_RX8P
U31
PCIE_RX8N
U29
PCIE_RX9P
T28
PCIE_RX9N
T30
PCIE_RX10P
R31
PCIE_RX10N
R29
PCIE_RX11P
P28
PCIE_RX11N
P30
PCIE_RX12P
N31
PCIE_RX12N
N29
PCIE_RX13P
M28
PCIE_RX13N
M30
PCIE_RX14P
L31
PCIE_RX14N
L29
PCIE_RX15P
K30
PCIE_RX15N
AK30
PCIE_REFCLKP
AK32
PCIE_REFCLKN
N10
PWRGOOD
AL27
PERSTB
M9X-S2/S3 + Park-S3
M9X-S2/S3 + Park-S3
PARK@
PARK@
CLOCK
CLOCK
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALRP
PCIE_CALRN
4
PCIE_GTX_MRX_P0
AH30
PCIE_GTX_MRX_N0
AG31
PCIE_GTX_MRX_P1
AG29
PCIE_GTX_MRX_N1
AF28
PCIE_GTX_MRX_P2
AF27
PCIE_GTX_MRX_N2
AF26
PCIE_GTX_MRX_P3
AD27
PCIE_GTX_MRX_N3
AD26
PCIE_GTX_MRX_P4
AC25
PCIE_GTX_MRX_N4
AB25
PCIE_GTX_MRX_P5
Y23
PCIE_GTX_MRX_N5
Y24
PCIE_GTX_MRX_P6
AB27
PCIE_GTX_MRX_N6
AB26
PCIE_GTX_MRX_P7
Y27
PCIE_GTX_MRX_N7
Y26
PCIE_GTX_MRX_P8
W24
PCIE_GTX_MRX_N8
W23
PCIE_GTX_MRX_P9
V27
PCIE_GTX_MRX_N9
U26
PCIE_GTX_MRX_P10
U24
PCIE_GTX_MRX_N10
U23
PCIE_GTX_MRX_P11
T26
PCIE_GTX_MRX_N11
T27
PCIE_GTX_MRX_P12
T24
PCIE_GTX_MRX_N12
T23
PCIE_GTX_MRX_P13
P27
PCIE_GTX_MRX_N13
P26
PCIE_GTX_MRX_P14
P24
PCIE_GTX_MRX_N14
P23
PCIE_GTX_MRX_P15
M27
PCIE_GTX_MRX_N15
N26
Y22
AA22
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
1 2
1 2
C131 0.1U_04 02_10V7K VGA@C131 0.1U _0402_10V7K VGA@
1 2
1 2
C102 0.1U_04 02_10V7K
C102 0.1U_04 02_10V7K
C126 0.1U_04 02_10V7K VGA@C126 0.1U _0402_10V7K VGA@
1 2
1 2
C130 0.1U_04 02_10V7K
C130 0.1U_04 02_10V7K
C101 0.1U_04 02_10V7K VGA@C101 0.1U _0402_10V7K VGA@
1 2
1 2
C107 0.1U_04 02_10V7K
C107 0.1U_04 02_10V7K
C112 0.1U_04 02_10V7K VGA@C112 0.1U _0402_10V7K VGA@
1 2
1 2
C129 0.1U_04 02_10V7K
C129 0.1U_04 02_10V7K
C124 0.1U_04 02_10V7K VGA@C124 0.1U _0402_10V7K VGA@
1 2
1 2
C83 0.1U_ 0402_10V7K
C83 0.1U_ 0402_10V7K
C123 0.1U_04 02_10V7K VGA@C123 0.1U _0402_10V7K VGA@
1 2
1 2
C98 0.1U_ 0402_10V7K
C98 0.1U_ 0402_10V7K
C103 0.1U_04 02_10V7K VGA@C103 0.1U _0402_10V7K VGA@
1 2
1 2
C105 0.1U_04 02_10V7K
C105 0.1U_04 02_10V7K
C110 0.1U_04 02_10V7K VGA@C110 0.1U _0402_10V7K VGA@
1 2
1 2
C125 0.1U_04 02_10V7K
C125 0.1U_04 02_10V7K
C133 0.1U_04 02_10V7K VGA@C133 0.1U _0402_10V7K VGA@
1 2
1 2
C135 0.1U_04 02_10V7K
C135 0.1U_04 02_10V7K
C128 0.1U_04 02_10V7K VGA@C128 0.1U _0402_10V7K VGA@
1 2
1 2
C132 0.1U_04 02_10V7K
C132 0.1U_04 02_10V7K
C108 0.1U_04 02_10V7K VGA@C108 0.1U _0402_10V7K VGA@
1 2
1 2
C113 0.1U_04 02_10V7K
C113 0.1U_04 02_10V7K
C127 0.1U_04 02_10V7K VGA@C127 0.1U _0402_10V7K VGA@
1 2
1 2
C99 0.1U_ 0402_10V7K
C99 0.1U_ 0402_10V7K
C134 0.1U_04 02_10V7K VGA@C134 0.1U _0402_10V7K VGA@
1 2
1 2
C104 0.1U_04 02_10V7K
C104 0.1U_04 02_10V7K
C109 0.1U_04 02_10V7K VGA@C109 0.1U _0402_10V7K VGA@
1 2
1 2
C136 0.1U_04 02_10V7K
C136 0.1U_04 02_10V7K
C106 0.1U_04 02_10V7K VGA@C106 0.1U _0402_10V7K VGA@
1 2
1 2
C111 0.1U_04 02_10V7K
C111 0.1U_04 02_10V7K
C97 0.1U_ 0402_10V7K VGA@C97 0.1U_0402_10V7K VGA@
1 2
1 2
C100 0.1U_04 02_10V7K
C100 0.1U_04 02_10V7K
R1591.27K_040 2_1% VGA@ R1591.27K_0402_1% VGA@
R3332K_0402_5% VGA@ R3332K_040 2_5% VGA@
+VGA_PCIE
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
3
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
VGA@
VGA@
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
VGA@
VGA@
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
VGA@
VGA@
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
VGA@
VGA@
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
VGA@
VGA@
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
VGA@
VGA@
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
VGA@
VGA@
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
VGA@
VGA@
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
VGA@
VGA@
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
VGA@
VGA@
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
VGA@
VGA@
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
VGA@
VGA@
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
VGA@
VGA@
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
VGA@
VGA@
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
VGA@
VGA@
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
VGA@
VGA@
Compal Secret Data
Compal Secret Data
Compal Secret Data
U40
U40
M93-S3
M93-S3
M93@
M93@
Deciphered Date
Deciphered Date
Deciphered Date
U40F
U40F
LVDS CONTROL
LVDS CONTROL
LVTMDP
LVTMDP
M9X-S2/S3 + Park-S3
M9X-S2/S3 + Park-S3
PARK@
PARK@
VARY_BL
DIGON
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2 N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1 N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0 N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
TXOUT_L3P
TXOUT_L3N
2
R292
VGA@ R292
VGA@
1 2
10K_0402_5%
10K_0402_5%
R128
VGA@ R128
VGA@
1 2
AB11
AB12
VGA@ R907
VGA@
AH20
AJ19
AL21
AK20
AH22
AJ21
AL23
AK22
AK24
AJ23
0_0402_5%
0_0402_5%
R907
1 2
10K_0402_5%
10K_0402_5%
add at 8/11
VGA_VARIBL (21 ,33)
VGA_ENVDD (21)
change at 8/11
AL15
AK14
AH16
AJ15
AL17
AK16
AH18
AJ17
AL19
AK18
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PARK-S3 PCIE/LVDS
PARK-S3 PCIE/LVDS
PARK-S3 PCIE/LVDS
LA-5971P
LA-5971P
LA-5971P
VGA_TXCLK+ (21)
VGA_TXCLK- (21)
VGA_TXOUT0+ (21)
VGA_TXOUT0- (21)
VGA_TXOUT1+ (21)
VGA_TXOUT1- (21)
VGA_TXOUT2+ (21)
VGA_TXOUT2- (21)
1
14 49Thursday, December 10 , 2009
14 49Thursday, December 10 , 2009
14 49Thursday, December 10 , 2009
1.0
1.0
1.0
5
L40
L40
+1.8VS_VGA
D D
+VGA_PCIE
+1.8VS_VGA
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
C C
B B
add at 8/11
+1.8VS_VGA +DPLL_PVDD
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
CLK_XTALIN 27MCLK_SSIC
A A
27MCLK_SSIC
XTALOUT_XTL
08/11
Spread Spectrum For EMI
12
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
PARK@
PARK@
L23
L23
12
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
VGA@
VGA@
L24
L24
12
VGA@
VGA@
L83
L83
12
VGA@
VGA@
C951
C951
R843
R843
1 2
0_0402_5%@
0_0402_5%@
U46
U46
1
REFOUT
2
MODOUT
XOUT
3
XIN/CLKIN
ASM3P2872AF-06OR_TSOT-23-6@
ASM3P2872AF-06OR_TSOT-23-6@
R_27M_SSC
PARK@
PARK@
1
C322
C322
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
1
C324
C324
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
1
C323
C323
2
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
VGA@
VGA@
1
1
C952
C952
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
6
VSS
5
4
VDD
R841
R841
1 2
33_0402_1% @
33_0402_1% @
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+1.8VS_VGA
5
PARK@
PARK@
1
C695
C695
2
VGA@
VGA@
1
C694
C694
2
VGA@
VGA@
1
C696
C696
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+3VS_VGA
ACIN(25,33,39)
VGA@
VGA@
1
C953
C953
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
27M_CLK(20)
C949
C949
C950
C950
+DPC_VDD18
PARK@
PARK@
1
130mA
C56
C56
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
+DPC_VDD10
VGA@
VGA@
1
200mA
C57
C57
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
+DPC_PVDD
VGA@
VGA@
1
20mA
C55
C55
2
0.1U_0402_10V6K
0.1U_0402_10V6K
VGA_LCD_CLK(21)
VGA_LCD_DATA(21)
R300
1 2
10K_0402_5%
10K_0402_5%
VGA_ENBKL(33)
VGA_PWRSEL(44)
27M_SSC(20)
GPIO21_BBEN(17)
TEST_EN(16)
R481
R481
1 2
499_0402_1%
499_0402_1%
VGA@
VGA@
249_0402_1%
249_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
R582 82.5_0402_1%
R582 82.5_0402_1%
+3VS_VGA
1
1
2
2
@
@
@
@
@R300
@
D4
VGA@
VGA@
R332
R332
@
@
R842
R842
1 2
+1.8VS_VGA
AE9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
VRAM_ID2
VRAM_ID2(16)
VRAM_ID1(16)
VRAM_ID0(16)
+DPC_PVDD
+DPC_VDD18
+DPC_VDD10
VGA_LCD_CLK
VGA_LCD_DATA
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
21
RB751V_SOD323@D4RB751V_SOD323@
VGA_ENBKL
GPU_GPIO8
GPU_GPIO9
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
VGA_PWRSEL
R840
R840
1 2
THM_ALERT#
R301
1 2
10K_0402_5%
10K_0402_5%
GPIO21_BBEN TEST_EN
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
TEST_EN
+VREFG_GPU
VGA@
VGA@
1
12
C58
C58
2
+DPLL_PVDD
0.1U_0402_10V6K
0.1U_0402_10V6K
+DPLL_VDDC
12
12
R160
R160
100_0402_1%
100_0402_1%
@
@
GPU_THERMAL_D+
GPU_THERMAL_D-
T69 PADT69 PAD
@
@
1
C1040
C1040
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CLK_XTALOUTXTALOUT_XTL
@
@
1
C1041
C1041
2
0_0402_5%@
0_0402_5%@
VRAM_ID1
VRAM_ID0
R_27M_SSC
0_0402_5%@
0_0402_5%@
@R301
@
120mA
300mA
CLK_XTALIN
VGA@
VGA@
1
C1042
C1042
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AB2
Y8
Y7
W6
V6
AC6
AC5
AA5
AA6
U1
W1
U3
Y6
AA1
R1
R3
U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
K4
AF24
AB13
W8
W9
W7
AD10
AC14
AC16
AF14
AE14
AD14
AM28
AK28
AC22
AB22
T4
T2
R5
AD17
AC17
0.1U_0402_10V6K
0.1U_0402_10V6K
4
U40B
U40B
M93-S3/M92-S2
M93-S3/M92-S2
DVCNTL_0/ DVPDATA_18
L9
DVCNTL_1 / NC
DVCNTL_2 / TESTEN#2
DVDATA_12 / DVPDATA_16
DVDATA_11 / DVPDATA_20
DVDATA_10 / DVPDATA_22
DVDATA_9 / DVPDATA_12
DVDATA_8 / DVPDATA_14
DVDATA_7 / DVPCNTL_0
DVDATA_6 / DVPDATA_8
DVDATA_5 / DVPDATA_6
DVDATA_4 DVPDATA_4
DVDATA_3 / DVPDATA_19
DVDATA_2 / DVPDATA_21
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0
DVO
DVO
M93-S3/M92-S2
M93-S3/M92-S2
DPC_PVDD / DVPDATA_11
DPC_PVSS / GND
DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23
DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17
DPC_VSSR#1 / DVPCLK
DPC_VSSR#2 / DVPDAT5
DPC_VSSR#3 / GND
DPC_VSSR#4 / GND
DPC_VSSR#5/ DVPCNTL_MV0
SCL
I2C
I2C
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
L6
JTAG_TRSTB
L5
JTAG_TDI
L3
JTAG_TCK
L1
JTAG_TMS
JTAG_TDO
TESTEN
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
HPD1
VREFG
PLL/CLOCK
PLL/CLOCK
DPLL_PVDD
DPLL_PVSS
DPLL_VDDC
XTALIN
XTALOUT
NC#2/XO_IN
NC#1/XO_IN2
THERMAL
THERMAL
DPLUS
DMINUS
TS_FDO
TSVDD
TSVSS
M9X-S2/S3 + Park-S3
M9X-S2/S3 + Park-S3
PARK@
PARK@
4
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
DPA
DPA
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
M92-S2/M93-S3
M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N
DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N
DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N
DVPDATA_13 / TX2P_DPC0P
DVPCNTL_1 / TX2M_DPC0N
VDDR4 / DPCD_CALR
DPC
DPC
DAC1
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
M92-S2/M93-S3
M92-S2/M93-S3
R2 / NC
R2B / NC
G2 / NC
G2B / NC
B2 / NC
B2B / NC
C / NC
DAC2
DAC2
Y / NC
COMP / NC
H2SYNC
V2SYNC
VDD2DI / NC
VSS2DI / NC
A2VDD / NC
A2VDDQ / NC
A2VSSQ
R2SET / NC
M92-S2/M93-S3M92-S2/M93-S3
M92-S2/M93-S3M92-S2/M93-S3
DDC1CLK
DDC1DATA
AUX1P
DDC/AUX
DDC/AUX
AUX1N
DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDC6CLK
DDC6DATA
NC/DDCCLK_AUX3P
NC/DDCDATA_AUX3N
3
CLK_XTALIN
12
R972
R972
1M_0402_5%
1M_0402_5%
VGA@
VGA@
1
C1022
C1022
2
22P_0402_50V8J VGA@
22P_0402_50V8J VGA@
12
VGA@
VGA@
1
C1000
C1000
2
12
VGA@
VGA@
1
C1001
C1001
2
12
PARK@
PARK@
1
C1007
C1007
2
+DPLL_VDDC+VGA_PCIE
VGA@
VGA@
1
C1013
C1013
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
CLK_XTALOUT
EMI request
add at 8/17
12
12
12
12
12
12
12
12
12
12
12
12
12
12
VGA@
VGA@
1
C998
C998
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
VGA@
1
C1002
C1002
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
PARK@
PARK@
1
C1008
C1008
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0603_6.3V6M
10U_0603_6.3V6M
2008/10/06 2009/10/06
2008/10/06 2009/10/06
2008/10/06 2009/10/06
AF2
AF4
AG3
AG5
AH3
AH1
AK3
AK1
AK5
AM3
AK6
AM5
AJ7
AH6
AK8
AL7
V4
U5
W3
V2
Y4
W5
AA3
Y2
AA12
AM26
R
AK26
RB
AL25
G
AJ25
GB
AH24
B
AG25
BB
AH26
AJ27
AD22
AG24
AE22
AE23
AD23
AM12
AK12
AL11
AJ11
AK10
AL9
AH12
AM10
AJ9
AL13
AJ13
AD19
AC19
AE20
AE17
AE19
AG13
AE6
AE5
AD2
AD4
AC11
AC13
AD13
AD11
AE16
AD16
AC1
AC3
AD20
AC20
70mA
45mA
50mA
130mA
1.5mA
12
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
R482
1 2
499_0402_1%
499_0402_1%
+AVDD
+VDD1DI
VGA_CRT_HSYNC2
VGA_CRT_VSYNC2
+VDD2DI
+A2VDD
+A2VDDQ
R908
1 2
715_0402_1%
715_0402_1%
VGA_CRT_CLK
VGA_CRT_DATA
R310
R310
150_0402_1%
150_0402_1%
VGA@
VGA@
VGA@R482
VGA@
VGA@R908
VGA@
add at 8/11
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
Y6
Y6
1 2
27MHZ_20P_7A27000010
27MHZ_20P_7A27000010
1
VGA@
VGA@
C1021
C1021
2
22P_0402_50V8J VGA@
22P_0402_50V8J VGA@
STRAPS
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO8
GPU_GPIO9
GPIO21_BBEN
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_VSYNC2
VGA_CRT_HSYNC2
GPU_GPIO8
VGA_CRT_R (22)
VGA_CRT_G (22)
VGA_CRT_B (22)
VGA_CRT_HSYNC (22)
VGA_CRT_VSYNC (22)
+1.8VS_VGA
+1.8VS_VGA
+1.8VS_VGA
VGA_CRT_CLK (22)
VGA_CRT_DATA (22)
L101
L101
VGA@
VGA@
3
R232 10K_0402_5%VGA@R232 10K_0402_5%VGA@
R228 10K_0402_5%@R228 10K_0402_5%@
R215 10K_0402_5%@R215 10K_0402_5%@
R233 10K_0402_5%@R233 10K_0402_5%@
R231 10K_0402_5%@R231 10K_0402_5%@
R216 10K_0402_5%@R216 10K_0402_5%@
R217 10K_0402_5%VGA@R217 10K_0402_5%VGA@
R236 10K_0402_5%@R236 10K_0402_5%@
R234 10K_0402_5%@R234 10K_0402_5%@
R229 10K_0402_5%@R229 10K_0402_5%@
R230 10K_0402_5%@R230 10K_0402_5%@
R235 10K_0402_5%@R235 10K_0402_5%@
R108 10K_0402_5%@R108 10K_0402_5%@
R1014 10K_0402_5%@R1014 10K_0402_5%@
L96
L96
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
VGA@
VGA@
L97
L97
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
VGA@
VGA@
L99
L99
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
PARK@
PARK@
add at 8/11
12
VGA@
VGA@
VGA@
VGA@
1
1
C1014
C1014
C1015
C1015
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
+3VS_VGA
VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE ST RAPS
+3VS_VGA
+AVDD
VGA@
VGA@
1
C999
C999
2
0.1U_0402_10V6K
0.1U_0402_10V6K
+1.8VS_VGA
+VDD1DI
VGA@
VGA@
1
C1003
C1003
2
0.1U_0402_10V6K
0.1U_0402_10V6K
+VDD2DI
PARK@
PARK@
1
C1009
C1009
2
0.1U_0402_10V6K
0.1U_0402_10V6K
VGA_SMB_CK2_R
VGA_SMB_DA2_R
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
1
CONFIGURATION STRAPS
STRAPS
BIF_GEN2_EN_A
BIOS_ROM_EN
GPIO0 PCIE FU LL TX OUTPUT SWINGTX_PWRS_ENB
GPIO1TX_DEEMPH_EN PCIE TRANSMITTER DE-EMPHASIS ENABLED
GPIO2
GPIO8
GPIO9 VGA ENABLEDBIF_VGA DIS
GPIO21
GPIO_22_ROMCSB
GPIO[13:11]ROMIDCFG(2:0)
H2SYNC
GENERICC
HSYNCAUD[1]
VSYNCAUD[0]
DESCRIPTION OF DEFAULT SETT INGSPIN
PCIE GNE2 ENABLED
ENABLE EXTERNAL BIOS ROM
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
H2SYNC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
L98
L98
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
10K_0402_5%
10K_0402_5%
Deciphered Date
Deciphered Date
Deciphered Date
12
PARK@
L100
L100
12
+3VS_VGA
12
12
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
PARK@
1
C1004
C1004
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PARK@
PARK@
1
C1010
C1010
2
10U_0603_6.3V6M
10U_0603_6.3V6M
R713
R713
10K_0402_5%
10K_0402_5%
VGA@
VGA@
VGA@
VGA@
VGA Thermal Sensor G781-1P8F
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C708
1 2
2200P_0402_50V7K
2200P_0402_50V7K
PARK@
PARK@
PARK@
PARK@
R714
R714
VGA@
VGA@
Closed to GPU
GPU_THERMAL_D+ VGA_SMB_DA2_R
GPU_THERMAL_D-
+A2VDD
PARK@
PARK@
PARK@
PARK@
1
1
C1006
C1006
C1005
C1005
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
+A2VDDQ
PARK@
PARK@
PARK@
PARK@
1
1
C1012
C1012
C1011
C1011
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
0.1U_0402_10V6K
+3VS_VGA
2
61
5
Q54A
Q54A
4
Q54B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+3VS_VGA
C137
C137
VGA@
VGA@
VGA@C708
VGA@
2
1
GENERICC
GPIO21_BB_EN
+3VS_VGA
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
8
7
6
5
LA-5971P
LA-5971P
LA-5971P
GPU_GPIO3
GPU_GPIO4
VGA_PWRSEL
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
VGA_LCD_DATA
VGA_LCD_CLK
VGA_SMB_CK2_R
1
R303 10K_0402_5%@R303 10K_0402_5%@
1 2
R297 10K_0402_5%@R297 10K_0402_5%@
1 2
R287 10K_0402_5%@R287 10K_0402_5%@
1 2
R302 10K_0402_5%@R302 10K_0402_5%@
1 2
R305 10K_0402_5%@R305 10K_0402_5%@
1 2
R294 10K_0402_5%@R294 10K_0402_5%@
1 2
R299 10K_0402_5%@R299 10K_0402_5%@
1 2
R298 10K_0402_5%@R298 10K_0402_5%@
1 2
R483 5.11K_0402_1%@R483 5.11K_0402_1%@
1 2
R341 4.7K_0402_5%VGA@R341 4.7K_0402_5%VGA@
12
R342 4.7K_0402_5%VGA@R342 4.7K_0402_5%VGA@
12
VGA_SMB_CK2 (33)
3
VGA@Q54B
VGA@
VGA_SMB_DA2 (33)
U26
U26
1
VDD1
SCLK
2
D+
SDATA
3
ALERT#
D-
THERM#4GND
G780P81U_MSOP8
G780P81U_MSOP8
VGA@
VGA@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PARK-S3 Main Generic/MSIC
PARK-S3 Main Generic/MSIC
PARK-S3 Main Generic/MSIC
RECOMMEN DED SETTINGS
0= DO N OT INSTALL RESISTOR
1 = I NSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
RECOMMENDED SETTINGS
0
0
0
0
0
0
0
001
0
0
0
11
R315
R315
10K_0402_5%
10K_0402_5%
VGA@
VGA@
1 2
12
12
R311
R311
R309
R309
150_0402_1%
150_0402_1%
150_0402_1%
150_0402_1%
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
THM_ALERT#
12
+3VS_VGA
R3404.7K_0402_5% VGA@ R3404.7K_0402_5% VGA@
15 49Thursday, December 10, 2009
15 49Thursday, December 10, 2009
15 49Thursday, December 10, 2009
12
R308
R308
150_0402_1%
150_0402_1%
1.0
1.0
1.0
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