Compal LA-5931P NAUR2 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

NAUR2 Schematics Document

AMD Processor with RS780MN/SB710/M92-S2/S3 LP

3 3

2009-11-25

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

143Friday, January 08, 2010

A

Compal Confidential

Model Name :

B

C

D

E

VRAM 512MB

1 1

LVDS Conn.

64M16 x 4

page 19

DDR3

ATI M93-S3 LP

PCI-Express 8x

CRT Conn.

Page 14,15,16,17,18

Gen1

AMD ASB1 Processor

page 4,5,6,7

Hyper Transport Link 16 x 16

ATI RS780MN

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 667/800

Thermal Sensor

ADM1032

page 6 page 20

Clock Generator

SLG8SP626VTR

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

uFCBGA-528

HDMI Conn.

PCI-Express 1x

page 10,11,12,13

page 32

4 in 1 socket

page 30

USB conn

page 31

2 2

A link Express2

ATI SB710

uFCBGA-528

X 1

USB

3.3V 48MHz

HD Audio

3.3V 24.576MHz/48Mhz

Card Reader

RTS5138

page 30

S-ATA

page 24,25,26,27,28

LPC BUS

HDA Codec CX20671

page 32

Phone Jack x2

page 33

3 3

Golden finger

CPU/board to I/O board

LED

page 23

DC/DC Interface .

page 35

Power Circuit

page 35~40

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

page 29

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

243Friday, January 08, 2010

C

A

Voltage Rails

Power Plane Description

VIN B+ +CPU_CORE

1 1

+NB_CORE 1.0V switched power rail ON OFF +0.9V 0.9V switched power rail for DDR terminator +1.1VS

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU (0.7-1.2V)

1.1V switched power rail for NB VDDC & VGA

B

S1 S3 S5

N/A N/A N/A

N/AN/AN/A

ON OFF

OFF

ON

OFF

ON OFF OFF

C

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S1# SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW

LOWLOWLOW

LOW LOW LOW LOW

HIGHHIGHHIGH

HIGH

D

ON

OFF

ON ON

ON

OFF

LOW

OFF

ON

E

+1.2V_HT 1.2V switched power rail ON OFF OFF +VGA_CORE +1.5VS +1.8V +1.8VS 1.8V switched power rail +2.5VS +3VALW

0.90-0.95V switched power rail

1.5V power rail for PCIE Card

1.8V power rail for CPU VDDIO and DDR

2.5V for CPU_VDDA

3.3V always on power rail

ON ON ON ON ON

OFFOFFON OFF OFF ON

OFF

OFF OFF

OFF ON ON*

+3V_LAN 3.3V power rail for LAN ON ON ON

OFF ON OFF

OFF

ON*

OFFON

ONON

+3VS +5VALW +5VS

3.3V switched power rail 5V always on power rail 5V switched power rail

+VSB VSB always on power rail ON ON*

2 2

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

ON ON

EC SM Bus1 address

Device

Smart Battery

Address Address

HEX 16H

EC SM Bus2 address

Device

ADI ADM1032 (CPU)

SB-Temp Sensor

1001 100X b0001 011X b

HEX

98H

9CH

SB710 SM Bus 0 address

Device

Clock Generator

3 3

4 4

(SILEGO SLG8SP626) DDR DIMM1 DDR DIMM2

Address

1101 001Xb

1001 000Xb 1001 010Xb

HEX

D2 90

94

Device Address

IGP only mode

PowerXpress mode

IGP only mode

PowerXpress mode

PX_GPIO0 dGPU_ResetFunction Description dGPU_PWR_Enable PX Mode Switch

PX_GPIO1

Enable +1.1VS_PXFunction Description PX MODE SWITCH Enable +3VS_DELAY

H : Enable Reserved

Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)Function Description

PX_GPIO1

XX

H : EnableH : Enable L : iGPU(DC) / H : dGPU(AC)

XX

KB926

PX_GPIO1_SB

X

H : Enable

RS780MNSB700 SB700 PX_GPIO2

X

KB926

PX_+3VSPX_GPIO2

X

H : Enable

DISPLAY OUTPUT

PX_+1.8VS

Enable +1.8VS_PX

X

H : Enable

LVDS / CRTPowerXpress mode

PX_+VGA_CORE Enable +VGA_CORE

X

H : Enable

PX_GPIO2_NB

Trigger from SB

X

Reserved

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

343Friday, January 08, 2010

C

ZZZ

PCB

5

U1

CPU

L325@

U1

CPU

MV40@

U1

CPU

L335@

4

3

2

1

D D

VLDT=500mA

C C

H_CLKIP1<10> H_CLKIN1<10>

H_CLKIP0<10>

11/24 update 11/24 update

B B

H_CLKIN0<10> H_CTLIP1<10> H_CTLOP1 <10>

H_CTLIN1<10> H_CTLIP0<10> H_CTLOP0 <10>

H_CTLIN0<10>

H_CADIP[0..15] H_CADIN[0..15]

+1.2V_HT

H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0

H_CTLIP0

U1A

AL4

VLDT_B4

AL3

VLDT_B3

AL2

VLDT_B2

AL1

VLDT_B1

Y6

L0_CADIN_H15

Y5

L0_CADIN_L15

W7

L0_CADIN_H14

W6

L0_CADIN_L14

U6

L0_CADIN_H13

U5

L0_CADIN_L13

R7

L0_CADIN_H12

R6

L0_CADIN_L12

M8

L0_CADIN_H11

M7

L0_CADIN_L11

L6

L0_CADIN_H10

L5

L0_CADIN_L10

J6

L0_CADIN_H9

J5

L0_CADIN_L9

H4

L0_CADIN_H8

H3

L0_CADIN_L8

T3

L0_CADIN_H7

T4

L0_CADIN_L7

T2

L0_CADIN_H6

T1

L0_CADIN_L6

P3

L0_CADIN_H5

P4

L0_CADIN_L5

P2

L0_CADIN_H4

P1

L0_CADIN_L4

M2

L0_CADIN_H3

M1

L0_CADIN_L3

K3

L0_CADIN_H2

K4

L0_CADIN_L2

K2

L0_CADIN_H1

K1

L0_CADIN_L1

H2

L0_CADIN_H0

H1

L0_CADIN_L0

P6

L0_CLKIN_H1

P5

L0_CLKIN_L1

M3

L0_CLKIN_H0

M4

L0_CLKIN_L0

P8

L0_CTLIN_H1

P9

L0_CTLIN_L1

V2

L0_CTLIN_H0

V1

L0_CTLIN_L0

TMZL625OAX5DY_BGA812

TMZL625OAX5DY_BGA812 L625@

L625@

L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10

L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6

HT LINK

L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0 L0_CTLOUT_H1

L0_CTLOUT_L1 L0_CTLOUT_H0

L0_CTLOUT_L0

VLDT_A4 VLDT_A3 VLDT_A2 VLDT_A1

F4 F3 F2 F1

Y9 Y8 AB6 AB5 AC7 AC6 AE6 AE5 AE9 AE8 AH3 AH4 AK3 AK4 AK1 AK2 Y1 Y2 Y4 Y3 AB1 AB2 AB4 AB3 AD4 AD3 AF1 AF2 AF4 AF3 AH1 AH2

AF6 AF5

AD1 AD2

AB8 AB9

V4 V3

H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0

H_CTLOP0 H_CTLON0H_CTLIN0

H_CADOP[0..15] H_CADON[0..15]

1 2

C668 4.7U_0805_10V4ZC668 4.7U_0805_10V4Z

H_CLKOP1 <10> H_CLKON1 <10>

H_CLKOP0 <10> H_CLKON0 <10>

H_CTLON1 <10>

H_CTLON0 <10>

H_CADOP[0..15] <10>H_CADIP[0..15]<10> H_CADON[0..15] <10>H_CADIN[0..15]<10>

+1.2V_HT

250 mil

VLDT CAP.

12

C669

4.7U_0805_10V6K

12

C670

4.7U_0805_10V6K

1

C671

0.22U_0603_16V4Z

2

1

C672

0.22U_0603_16V4Z

2

1

C673

C673 180P_0402_50V8J

180P_0402_50V8J

2

1

C674

C674 180P_0402_50V8J

180P_0402_50V8J

2

Near CPU Socket

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

443Friday, January 08, 2010

A

B

C

D

E

DDR_B_D[63..0]<9>

R523

1K_0402_1%

R521

1K_0402_1%

+1.8V

1 2

1

C675

2

1 2

+1.8V

DDR_A_MA[15..0]<8>

2

0.1U_0402_16V4Z

R524

1 2

R522

DDR_CS1_DIMMA#<8> DDR_CS0_DIMMA#<8> DDR_CS1_DIMMB#<9> DDR_CS0_DIMMB#<9>

DDR_CKE1_DIMMB<9> DDR_CKE0_DIMMB<9> DDR_CKE1_DIMMA<8> DDR_CKE0_DIMMA<8>

DDR_A_BS#2<8> DDR_A_BS#1<8> DDR_A_BS#0<8>

DDR_A_RAS#<8> DDR_A_CAS#<8> DDR_A_WE#<8>

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

DDR_A_CLK2

DDR_A_CLK#2 DDR_A_CLK1

DDR_A_CLK#1

C676

1000P_0402_50V7K

+CPU_M_VREF

39.2_0402_1%

12

39.2_0402_1%

+CPU_M_VREF

+0.9V

VTT_SENSE

TP1TP1

DDR_CS1_DIMMA# DDR_CS0_DIMMA# DDR_CS1_DIMMB# DDR_CS0_DIMMB#

DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA

DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0

DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

1

C677

1.5P_0402_50V8C

2

1

C679

1.5P_0402_50V8C

2

M_ZN M_ZP

U1B

A12

VTT1

B12

VTT2

C12

VTT3

D12

VTT4

AK10

VTT5

AN10

VTT6

AL10

VTT7

AM10

VTT8

B11

VTT9

A11

MEMVREF

B10

VTT_SENSE

AG9

MEMZN

AH9

MEMZP

AH29

RSVD#AH29

AE29

RSVD#AE29

AK33

RSVD#AK33

AF33

RSVD#AF33

AH30

MA0_CS_L1

AF29

MA0_CS_L0

AJ32

MB0_CS_L1

AF31

MB0_CS_L0

N33

MB_CKE1

P32

MB_CKE0

M30

MA_CKE1

M28

MA_CKE0

P30

MA_ADD15

M29

MA_ADD14

AG28

MA_ADD13

P28

MA_ADD12

T30

MA_ADD11

AC28

MA_ADD10

P27

MA_ADD9

R26

MA_ADD8

R27

MA_ADD7

U28

MA_ADD6

V30

MA_ADD5

U27

MA_ADD4

Y30

MA_ADD3

AB29

MA_ADD2

W29

MA_ADD1

AC26

MA_ADD0

R29

MA_BANK2

AC29

MA_BANK1

AE28

MA_BANK0

TMZL625OAX5DY_BGA812

AC27

MA_RAS_L

AF30

MA_CAS_L

AE27

MA_WE_L

L625@

RSVD#AH17 RSVD#AG17

RSVD#E20

RSVD#E19 RSVD#AB27 RSVD#AB26 RSVD#AN21 RSVD#AM21 RSVD#AN22

RSVD#A23 RSVD#AB33 RSVD#AB32

MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 MA0_CLK_H0 MA0_CLK_L0

MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 MB0_CLK_H0 MB0_CLK_L0

MB0_ODT1

MB0_ODT0

MA0_ODT1

MA0_ODT0

DDR II: CMD/CTRL/CLK

MB_ADD15

MB_ADD14

MB_ADD13

MB_ADD12

MB_ADD11

MB_ADD10

MB_BANK2

MB_BANK1

MB_BANK0

MB_RAS_L

MB_CAS_L

TMZL625OAX5DY_BGA812

DDR_B_CLK2

DDR_B_CLK#2 DDR_B_CLK1

DDR_B_CLK#1

MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0

MB_WE_L

1

C678

1.5P_0402_50V8C

2

1

C680

1.5P_0402_50V8C

2

AH17 AG17 E20 E19 AB27 AB26 AN21 AM21 A22 A23 AB33 AB32

AK18 AJ17 D18 F19 Y28 Y27

AN22 AM22 C22 B22 AA32 AA33

AK32 AH33 AJ30 AG29

P33 P31 AJ33 T32 T31 AD32 T33 V32 U33 V33 V31 W33 Y31 Y33 Y32 AC33

R33 AD33 AE33

AF32 AH32 AG33

DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1

DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1

DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0

DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0

DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_A_CLK2 <8> DDR_A_CLK#2 <8> DDR_A_CLK1 <8> DDR_A_CLK#1 <8>

DDR_B_CLK2 <9> DDR_B_CLK#2 <9> DDR_B_CLK1 <9> DDR_B_CLK#1 <9>

DDR_B_ODT1 <9> DDR_B_ODT0 <9> DDR_A_ODT1 <8> DDR_A_ODT0 <8>

DDR_B_MA[15..0] <9>

DDR_B_BS#2 <9> DDR_B_BS#1 <9> DDR_B_BS#0 <9>

DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_B_DQS7<9> DDR_B_DQS#7<9> DDR_B_DQS6<9> DDR_B_DQS#6<9> DDR_B_DQS5<9> DDR_B_DQS#5<9> DDR_B_DQS4<9> DDR_B_DQS#4<9> DDR_B_DQS3<9> DDR_B_DQS#3<9> DDR_B_DQS2<9> DDR_B_DQS#2<9> DDR_B_DQS1<9> DDR_B_DQS#1<9> DDR_B_DQS0<9> DDR_B_DQS#0<9>

4 4

3 3

2 2

1 1

DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0

DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0

DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0

Processor DDR2 Memory Interface

U1C

AN13

MB_DATA63

AL14

MB_DATA62

AL16

MB_DATA61

AN17

MB_DATA60

AN12

MB_DATA59

AM12

MB_DATA58

AM16

MB_DATA57

AN16

MB_DATA56

AL18

MB_DATA55

AN19

MB_DATA54

AM24

MB_DATA53

AN24

MB_DATA52

AM18

MB_DATA51

AN18

MB_DATA50

AL22

MB_DATA49

AN23

MB_DATA48

AM25

MB_DATA47

AL26

MB_DATA46

AN28

MB_DATA45

AL28

MB_DATA44

AL24

MB_DATA43

AN25

MB_DATA42

AN27

MB_DATA41

AM28

MB_DATA40

AM29

MB_DATA39

AL30

MB_DATA38

AL32

MB_DATA37

AL33

MB_DATA36

AK28

MB_DATA35

AN29

MB_DATA34

AM31

MB_DATA33

AM32

MB_DATA32

E33

MB_DATA31

D31

MB_DATA30

B31

MB_DATA29

A31

MB_DATA28

F33

MB_DATA27

F31

MB_DATA26

C32

MB_DATA25

B32

MB_DATA24

C30

MB_DATA23

A29

MB_DATA22

B26

MB_DATA21

A26

MB_DATA20

B30

MB_DATA19

A30

MB_DATA18

A27

MB_DATA17

C26

MB_DATA16

A24

MB_DATA15

B24

MB_DATA14

C18

MB_DATA13

A18

MB_DATA12

A25

MB_DATA11

TMZL625OAX5DY_BGA812

C24

MB_DATA10

C20

MB_DATA9

A19

MB_DATA8

C16

MB_DATA7

A16

MB_DATA6

B14

MB_DATA5

A13

MB_DATA4

B18

MB_DATA3

A17

MB_DATA2

C14

MB_DATA1

A14

MB_DATA0

K33

MB_CHECK7

K31

MB_CHECK6

G32

MB_CHECK5

F32

MB_CHECK4

L33

MB_CHECK3

K32

MB_CHECK2

H31

MB_CHECK1

G33

MB_CHECK0

H33

MB_DM8

AN15

MB_DM7

AN20

MB_DM6

AK26

MB_DM5

AN31

MB_DM4

C33

MB_DM3

C28

MB_DM2

A20

MB_DM1

D14

MB_DM0

J33

MB_DQS_H8

H32

MB_DQS_L8

AM14

MB_DQS_H7

AN14

MB_DQS_L7

AL20

MB_DQS_H6

AM20

MB_DQS_L6

AN26

MB_DQS_H5

AM26

MB_DQS_L5

AN30

MB_DQS_H4

AM30

MB_DQS_L4

D33

MB_DQS_H3

D32

MB_DQS_L3

B28

MB_DQS_H2

A28

MB_DQS_L2

A21

MB_DQS_H1

B20

MB_DQS_L1

B16

MB_DQS_H0

A15

MB_DQS_L0

TMZL625OAX5DY_BGA812

L625@

DDRII: DATA

MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10

MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0

MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0

MA_DM8 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0

MA_DQS_H8

MA_DQS_L8

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AG11 AH11 AJ12 AJ14 AF11 AF12 AG12 AH12 AK14 AF15 AH19 AK20 AF14 AG14 AF17 AG19 AG20 AJ20 AF22 AK24 AF19 AF20 AJ23 AG23 AF23 AF25 AH27 AK30 AJ25 AG25 AJ26 AJ28 D28 G28 D26 E26 F30 E29 F27 H26 H25 D24 H22 E22 F26 G26 D22 G23 G22 G20 G15 F15 D20 F22 D16 E17 H15 H14 G12 H12 E15 E14 E11 F11

K30 J29 G29 F29 L28 L29 H29 H27

H30 AL12 AK16 AK22 AJ27 E27 E23 H19 G14

J27 J26 AJ11 AK12 AG15 AH15 AH22 AG22 AG26 AH26 E28 F28 E25 F25 G17 H17 E12 F12

DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0

DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0

DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0

DDR_A_D[63..0] <8>

DDR_A_DQS7 <8> DDR_A_DQS#7 <8> DDR_A_DQS6 <8> DDR_A_DQS#6 <8> DDR_A_DQS5 <8> DDR_A_DQS#5 <8> DDR_A_DQS4 <8> DDR_A_DQS#4 <8> DDR_A_DQS3 <8> DDR_A_DQS#3 <8> DDR_A_DQS2 <8> DDR_A_DQS#2 <8> DDR_A_DQS1 <8> DDR_A_DQS#1 <8> DDR_A_DQS0 <8> DDR_A_DQS#0 <8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SCHEMATIC A5931.

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

401814

543Friday, January 08, 2010

E

C

of

5

+1.8VS

4

3

2

1

R525

R525 300_0402_5%

300_0402_5%

1 2

LDT_RST#<24>

D D

H_PWRGD<24>

C C

B B

LDT_STOP#<11,24>

C691

2200P_0402_50V7K

1

2

LDT_RST#

1

C685

0.01U_0402_25V4Z

2

+1.8VS

1 2

H_PWRGD

1

C686

0.01U_0402_25V4Z

2

+1.8VS

1 2

1

2

+3VS

CPU_THERMDA CPU_THERMDC

@

R529

R529 300_0402_5%

300_0402_5%

@

R540

R540 300_0402_5%

300_0402_5%

LDT_STOP#

C689

0.01U_0402_25V4Z

0.01U_0402_25V4Z @

@

C690

0.1U_0402_16V4Z

1 2

U2

1

VDD D+

SDATA

ALERT#

DTHERM#4GND

F75383M_MSOP8

SCLK

2 3

ADM1032ARMZ-2REEL_MSOP8

SMBus Address: 1001110X (b)

CLK_CPU_BCLK<20>

CLK_CPU_BCLK#<20>

8 7 6 5

+2.5VS

+1.8V

R542 510_0402_5%

R543 510_0402_5%

R543 510_0402_5% R544 300_0402_5%

R544 300_0402_5% R545 300_0402_5%

R545 300_0402_5%

L124

1 2

FCM2012CF-800T06_2P

1

+

C681

C681 150U_B2_6.3VM

150U_B2_6.3VM

2

1 2

C687

1 2

C688 3900P_0402_50V7KC688 3900P_0402_50V7K

12

12 12 12

EC_SMB_CK2 <15,29> EC_SMB_DA2 <15,29>

+2.5VDDA

3300P_0402_50V7K

1

C682

2

4.7U_0805_10V4Z

+1.8V

R531 44.2_0402_1%R531 44.2_0402_1%

+1.2V_HT

R527 44.2_0402_1%R527 44.2_0402_1%

CPU_VCC_SENSE<39>

3900P_0402_50V7K

3900P_0402_50V7K 12

R537

R537 169_0402_1%

169_0402_1%

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

+1.8V

R551220_0402_5%@ R551220_0402_5%@

R552220_0402_5%@ R552220_0402_5%@

R550220_0402_5%@ R550220_0402_5%@

12

1

C684

C683

0.22U_0603_16V4Z

2

LDT_RST# H_PWRGD LDT_STOP#

R528

1 2 1 2

Close to CPU within 1"

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

CPU_TMS CPU_TCK CPU_TRST#

CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

R553220_0402_5%@ R553220_0402_5%@

12

CPU_TDI

CPU_SIC

12

1K_0402_5%

CPU_HTREF1 CPU_HTREF0

TP2TP2 TP3TP3

TP4TP4

CPU_THERMDC CPU_THERMDA

U1D

A8

VDDA2

B8

VDDA1

AK6

RESET_L

AM2

PWROK

AM6

LDTSTOP_L

AN4

SIC

AN5

SID

V10

HT_REF1

V9

HT_REF0

E2

VDD_FB_H

E1

VDD_FB_L

AM9

VDDIO_FB_H

AK9

VDDIO_FB_L

A6

CLKIN_H

A7

CLKIN_L

AH8

DBRDY

AN8

TMS

AK8

TCK

AL8

TRST_L

AM8

TDI

A9

TEST25_H

B9

TEST25_L

A5

TEST19

B6

TEST18

AJ9

TEST13

H8

TEST9

J8

TEST17

C8

TEST16

D9

TEST15

H7

TEST14

AN3

TEST12

C6

TEST7

AH7

TEST6

AL6

THERMDC

AM5

THERMDA

AJ5

TEST3

AJ7

TEST2

M31

RSVD#M31

L32

RSVD#L32

M33

RSVD#M33

M32

RSVD#M32

TMZL625OAX5DY_BGA812

W27

RSVD#W27

W26

RSVD#W26

AJ29

RSVD#AJ29

P26

RSVD#P26

M26

RSVD#M26

AH31

RSVD#AH31

AF27

RSVD#AF27

L625@

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

MISC

TMZL625OAX5DY_BGA812

RSVD#AB31 RSVD#AB30 RSVD#AK31 RSVD#AD31 RSVD#AD30

VID5 VID4 VID3 VID2 VID1 VID0

PSI_L

DBREQ_L

TDO

TEST29_H TEST29_L

TEST24 TEST23 TEST22 TEST21 TEST20

TEST28_H

TEST28_L

TEST27 TEST26 TEST10

TEST8

RSVD#L27 RSVD#B25

RSVD1 RSVD2 RSVD3

RSVD#E8 RSVD#G5

CPU_THERMTRIP#_R

AJ6

H_PROCHOT_R#

AN6

B2 C2 C1 D2 D1 D3

CPU_PRESENT#

AM3 E4

CPU_DBREQ#

AN9

AN7

CPU_TEST29_H_FBCLKOUT_P

E9

CPU_TEST29_L_FBCLKOUT_N

D10

ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1"

AH6 AG8 AN11 F9 AM7

G11 H11 AJ8

CPU_TEST26_BURNIN#

AM4 D7 B5

L27 B25

G6 A10 B7

E8 G5

AB31 AB30 AK31 AD31

CPU_THERMTRIP#_R H_THERMTRIP#

AD30

+1.8V

CPU_VID5 <39> CPU_VID4 <39> CPU_VID3 <39> CPU_VID2 <39> CPU_VID1 <39> CPU_VID0 <39>

PSI_L <39>CPU_VSS_SENSE<39>

R539

220_0402_5%

TP5TP5

CPU_TEST21_SCANEN

+1.8V

12

R548

300_0402_5%

12

R526

R526 300_0402_5%

300_0402_5%

12

R541

80.6_0402_1%

1 2

TEST24 TEST22 TEST20

E

3 1

MMBT3904_NL_SOT23-3

+1.8V

B

+1.8V

12

2

R546

R546 1K_0402_5%

1K_0402_5%

Q19

C

H_PROCHOT_R# <24,29>

CPU_VID1 CPU_PRESENT# CPU_TEST26_BURNIN#

CPU_TEST21_SCANEN

TEST24

TEST22

TEST20

+3VALW

12

R549

R549 10K_0402_5%

10K_0402_5%

1 2

R530 300_0402_5%

1 2

R532 1K_0402_5%

1 2

R533 300_0402_5%

1 2

R534 300_0402_5%

1 2

R535 300_0402_5%

1 2

R536 300_0402_5%

1 2

R538 300_0402_5%R538 300_0402_5%

+3VALW

12

R547

1K_0402_5%@

B

2

Q20

Q20 MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

E

3 1

C

@

H_THERMTRIP# <25>

+1.8V

MAINPWON <29,39>

CPU_TCK CPU_TMS CPU_TDI CPU_TRST#

+3VS

5

LDT_RST#

2

P

A A

5

4

HDT_RST#

B

4

Y

A

G

@ U3

@

3

NC7SZ08P5X_NL_SC70-5

1

U3

SB_PWRGD <11,25,29>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

643Friday, January 08, 2010

5

VDD(+CPU_CORE) decoupling.

+CPU_CORE

D D

1

+

C695

C695 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

+

C692

C692 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

+

C693

C693 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

1

2

Near CPU Socket

+CPU_CORE

1

C696

C696 22U_0805_6.3V6M

22U_0805_6.3V6M

2

+CPU_CORE

1

C705

0.22U_0603_16V4Z

C C

0.22U_0603_16V4Z

2

1

C697

C697 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C706

0.22U_0603_16V4Z

2

1

C698

C698 22U_0805_6.3V6M

22U_0805_6.3V6M

2

+CPU_CORE +CPU_CORE

1

C699

C699 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C707

0.01U_0402_25V7K

2

1

C700

C700 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C708

C708 180P_0402_50V8J

180P_0402_50V8J

2

VDDIO decoupling.

+1.8V

1

C709

C709 22U_0805_6.3V6M

22U_0805_6.3V6M

2

B B

+1.8V

1

C713

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C725

0.01U_0402_25V7K

2

+1.8V

1

C731

A A

C731

4.7U_0805_10V4Z

2

1

C710

C710 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C714

0.22U_0603_16V4Z

2

1

C726

0.01U_0402_25V7K

2

1

C732

4.7U_0805_10V4Z

2

+1.8V

1

C711

0.22U_0603_16V4Z

2

1

C715

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>

1

C727

C727 180P_0402_50V8J

180P_0402_50V8J

2

1

C733

4.7U_0805_10V4Z

2

1

C712

0.22U_0603_16V4Z

2

1

C716

0.22U_0603_16V4Z

2

1

C728

C728 180P_0402_50V8J

180P_0402_50V8J

2

1

C743

4.7U_0805_10V4Z

2

+

C694

C694 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

1

C729

C729 180P_0402_50V8J

180P_0402_50V8J

2

1

+

C734

C734 220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

2

4

1

C701

C701 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

2

1

C730

C730 180P_0402_50V8J

180P_0402_50V8J

2

C702

C702 22U_0805_6.3V6M

22U_0805_6.3V6M

+1.8V

+0.9V

1

2

+0.9V

1

2

1

C703

C703 22U_0805_6.3V6M

22U_0805_6.3V6M

2

U1F

Y29

VDDIO#Y29

U29

VDDIO#U29

R28

VDDIO#R28

P29

VDDIO#P29

W32

VDDIO#W32

W30

VDDIO#W30

W28

VDDIO#W28

U30

VDDIO#U30

N30

VDDIO#N30

U32

VDDIO#U32

R32

VDDIO#R32

R30

VDDIO#R30

N32

VDDIO#N32

U26

VDDIO#U26

Y26

VDDIO#Y26

M27

VDDIO#M27

AG32

VDDIO#AG32

AG30

VDDIO#AG30

AF28

VDDIO#AF28

AE30

VDDIO#AE30

AE26

VDDIO#AE26

AC32

VDDIO#AC32

AC30

VDDIO#AC30

AE32

VDDIO#AE32

AB28

VDDIO#AB28

AA30

VDDIO#AA30

TMZL625OAX5DY_BGA812

TMZL625OAX5DY_BGA812 L625@

L625@ TMZL625OAX5DY_BGA812

TMZL625OAX5DY_BGA812

C717

4.7U_0805_10V4Z

Near CPU Right side.

C735

4.7U_0805_10V4Z

Near CPU Left side.

1

2

1

2

1

C704

C704 22U_0805_6.3V6M

22U_0805_6.3V6M

2

POWER2

C718

4.7U_0805_10V4Z

C736

4.7U_0805_10V4Z

3

+CPU_CORE +CPU_CORE

U1E

A3

VDDC#A3

A4

VDDC#A4

B3

VDDC#B3

B4

VDDC#B4

C3

VDDC#C3

C4

VDDC#C4

D4

VDDC#D4

D5

VDDC#D5

D6

VDDC#D6

E5

VDDC#E5

E6

VDDC#E6

E7

VDDC#E7

F5

VDDC#F5

F6

VDDC#F6

F7

VDDC#F7

F8

VDDC#F8

G8

VDDC#G8

G9

VDDC#G9

H9

VDDC#H9

J9

VDDC#J9

J10

VDDC#J10

J12

VDDC#J12

J14

VDDC#J14

J18

VDDC#J18

J20

VDDC#J20

J21

VDDC#J21

J23

VDDC#J23

K10

VDDC#K10

K12

VDDC#K12

K14

VDDC#K14

K18

VDDC#K18

K20

VDDC#K20

K21

VDDC#K21

K23

VDDC#K23

K25

VDDC#K25

L7

VDDC#L7

L9

VDDC#L9

L11

VDDC#L11

L13

VDDC#L13

M5

VDDC#M5

M10

VDDC#M10

M12

VDDC#M12

M25

VDDC#M25

N9

VDDC#N9

N11

VDDC#N11

N24

VDDC#N24

N25

VDDC#N25

P15

VDDC#P15

P18

VDDC#P18

P20

VDDC#P20

P24

VDDC#P24

P25

VDDC#P25

TMZL625OAX5DY_BGA812

TMZL625OAX5DY_BGA812 L625@

L625@

TMZL625OAX5DY_BGA812

VTT decoupling.

1

C719

0.22U_0603_16V4Z

2

1

C737

0.22U_0603_16V4Z

2

1

C720

0.22U_0603_16V4Z

2

1

C744

0.22U_0603_16V4Z

2

1

C721

C721 1000P_0402_50V7K

1000P_0402_50V7K

2

1

C738

C738 1000P_0402_50V7K

1000P_0402_50V7K

2

VDDC#AA10 VDDC#AA12 VDDC#AA24 VDDC#AA25 VDDC#AB11 VDDC#AB13

VDDC#AC5 VDDC#AC10 VDDC#AC12 VDDC#AC24 VDDC#AC25

VDDC#AD9 VDDC#AD11 VDDC#AD12 VDDC#AD14 VDDC#AD18 VDDC#AD21 VDDC#AD25 VDDC#AE12 VDDC#AE14 VDDC#AE18 VDDC#AE21 VDDC#AE23

VDDC#V25

VDDC#V24

POWER1

VDDC#Y19

VDDC#Y16

VDDC#Y14

VDDC#W20 VDDC#W18 VDDC#W15

VDDC#W5 VDDC#V19 VDDC#V16 VDDC#V14 VDDC#T20 VDDC#T18 VDDC#T15 VDDC#T10 VDDC#R19 VDDC#R16 VDDC#R14

VDDC#R5

AA10 AA12 AA24 AA25 AB11 AB13 AC5 AC10 AC12 AC24 AC25 AD9 AD11 AD12 AD14 AD18 AD21 AD25 AE12 AE14 AE18 AE21 AE23 V25 V24 Y19 Y16 Y14 W20 W18 W15 W5 V19 V16 V14 T20 T18 T15 T10 R19 R16 R14 R5

1

C722

C722 1000P_0402_50V7K

1000P_0402_50V7K

2

1

C739

C739 1000P_0402_50V7K

1000P_0402_50V7K

2

U1G

A32 AA1 AA2 AA4 AA9

AA11 AA22 AA23 AB10 AB12 AB21 AB22 AB23 AB24 AB25 AC11

AC1 AC2 AC4 AC8 AC9

AC13 AC21 AC22 AC23 AD10 AD13 AD16 AD20 AD22 AD23 AD24

AE1 AE2 AE4 AE7

AE10 AE11 AE13 AE16 AE20 AE22 AE24 AE25

AF7 AF8 AF9

AF26

AG1 AG2 AG4 AG6 AG7

AG27

AH5

AH14 AH20 AH23 AH25 AH28

1

C723

C723 180P_0402_50V8J

180P_0402_50V8J

2

1

C740

C740 180P_0402_50V8J

180P_0402_50V8J

2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53

TMZL625OAX5DY_BGA812

VSS54 VSS55 VSS56 VSS57 VSS58

TMZL625OAX5DY_BGA812

VSS59 VSS60

L625@

1

C724

C724 180P_0402_50V8J

180P_0402_50V8J

2

1

C741

C741 180P_0402_50V8J

180P_0402_50V8J

2

VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100

VSS99 VSS98 VSS97

GND1

VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61

G4 G2 G1 F23 F20 F14 E32 E30 D30 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D8 C31 B33 B29 B27 B21 B19 B17 B15 B13 C10 AN32 AN2 AM33 AM27 AM23 AM19 AM17 AM15 AM13 AM11 AM1 AL31 AK29 AK27 AK25 AK23 AK21 AK19 AK17 AK15 AK13 AK11 AK7 AK5 AJ22 AJ19 AJ15 AJ4 AJ2 AJ1

+0.9V

1

U1H

G19

VSS121

G25

VSS123

G27

VSS124

G30

VSS125

H5

VSS126

H6

VSS127

H20

VSS128

H23

VSS129

H28

VSS130

J1

VSS131

J2

VSS132

J4

VSS133

J7

VSS134

J11

VSS135

J13

VSS136

J16

VSS137

J22

VSS138

J24

VSS139

J25

VSS140

J28

VSS141

J30

VSS142

J32

VSS143

K11

VSS144

K13

VSS145

K16

VSS146

A2

VSS147

K22

VSS148

K24

VSS149

K9

VSS150

L1

VSS151

L2

VSS152

L4

VSS153

L8

VSS154

L10

VSS155

L12

VSS156

L21

VSS157

L22

VSS158

L23

VSS159

L24

VSS160

L25

VSS161

L26

VSS162

L30

VSS163

M6

VSS164

M9

VSS165

M11

VSS166

M13

VSS167

M21

VSS168

M22

VSS169

M23

VSS170

M24

VSS171

N1

VSS172

N2

VSS173

N4

VSS174

TMZL625OAX5DY_BGA812

N10

VSS175

N12

VSS176

N22

VSS177

N23

VSS178

P7

VSS179

TMZL625OAX5DY_BGA812

P10

VSS180

P14

VSS181

P16

VSS182

P19

VSS183

L625@

Near Power Supply

1

C: Change to NBO CAP

+

C742

C742 150U_B2_6.3VM

150U_B2_6.3VM

2

VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207

GND2

VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224

R1 R2 R4 R8 R15 R18 R20 T9 T14 T16 T19 T24 T25 V15 V18 V20 U1 U2 U4 U7 U8 W1 W2 W4 W8 W14 W16 W19 Y7 Y10 Y15 Y18 Y20 Y24 Y25 F17 AB7 AG5 B23 B1 G7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/18 2009/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

743Friday, January 08, 2010

5

4

3

2

1

C747

2

Issued Date

3

+1.8V+DIMM_VREF

12

R554

1K_0402_1%

12

R555

1K_0402_1%

DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]

DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4

DDR_A_MA12 DDR_A_BS#2

DDR_CKE0_DIMMA

DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_CS0_DIMMA#

DDR_A_MA5 DDR_A_MA8 DDR_A_MA9

DDR_A_BS#0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3

DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#

DDR_A_RAS# DDR_A_ODT0 DDR_A_MA13

DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14

Compal Secret Data

2005/10/11 2009/06/11

Compal Secret Data

Deciphered Date

2

47_0804_8P4R_5%

+0.9V

RP1

18

1 2

C745 0.1U_0402_16V4ZC745 0.1U_0402_16V4Z

27

1 2

36

C748 0.1U_0402_16V4ZC748 0.1U_0402_16V4Z

45

RP2

RP3

RP4

RP5

RP6

RP7

RP8

1 2

18

C750 0.1U_0402_16V4ZC750 0.1U_0402_16V4Z

27

1 2

36

C749 0.1U_0402_16V4ZC749 0.1U_0402_16V4Z

45

1 2

18

C751 0.1U_0402_16V4ZC751 0.1U_0402_16V4Z

27 36

1 2

C752 0.1U_0402_16V4ZC752 0.1U_0402_16V4Z

45

18

1 2

C754 0.1U_0402_16V4ZC754 0.1U_0402_16V4Z

27

1 2

36

C753 0.1U_0402_16V4ZC753 0.1U_0402_16V4Z

45

1 2

18

C755 0.1U_0402_16V4ZC755 0.1U_0402_16V4Z

27 36

1 2

C756 0.1U_0402_16V4ZC756 0.1U_0402_16V4Z

45

18

1 2

C758 0.1U_0402_16V4ZC758 0.1U_0402_16V4Z

27 36

1 2

C757 0.1U_0402_16V4ZC757 0.1U_0402_16V4Z

45

1 2

18

C759 0.1U_0402_16V4ZC759 0.1U_0402_16V4Z

27

1 2

36

C760 0.1U_0402_16V4ZC760 0.1U_0402_16V4Z

45

1 2

18

C761 0.1U_0402_16V4ZC761 0.1U_0402_16V4Z

27

1 2

36

C762 0.1U_0402_16V4ZC762 0.1U_0402_16V4Z

45

+1.8V

COMPAL Electronics，Inc

Title

Size Document Number Rev

Custom

Date: Sheet

SCHEMATIC A5931.

401814

1

C

of

843Friday, January 08, 2010

+1.8V

0.1U_0402_16V4Z

JDIMM1

1

VREF

3

DDR_A_D0

D D

C C

DDR_CKE0_DIMMA<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5> DDR_A_WE#<5>

DDR_A_CAS#<5> DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

B B

A A

SB_CK_SDAT<9,20,25>

SB_CK_SCLK<9,20,25>

DDR_A_D1 DDR_A_DQS#0

DDR_A_DQS0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D22 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

DDR_A_ODT1 DDR_A_D32

DDR_A_D33 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D34

DDR_A_D35 DDR_A_D40

DDR_A_D41 DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D47 DDR_A_D48

DDR_A_D49 DDR_A_D53

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51 DDR_A_D55

DDR_A_D56 DDR_A_D57

DDR_A_DM7 DDR_A_D58

DDR_A_D59 SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C763

0.1U_0402_16V4Z

2

5

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

P-TWO_A5652C-A0G16

P-TWO_A5652C-A0G16 ME@

ME@

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS

DQ12 DQ13

VSS DM1 VSS CK0

CK0#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS

NC DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

A11

A7

A6 VDD

A4

A2

A0 VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS CK1

CK1#

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS SAO

SA1

GND

JAWD0 used

+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204

4

DDR_A_D4 DDR_A_D5

DDR_A_DM0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13 DDR_A_DM1 DDR_A_CLK1

DDR_A_CLK#1 DDR_A_D14

DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6DDR_A_MA8

DDR_A_MA4 DDR_A_MA2 DDR_A_MA0

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_ODT0 DDR_A_MA13

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D52

DDR_A_CLK2 DDR_A_CLK#2

DDR_A_DM6 DDR_A_D54

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

R556 10K_0402_5%R556 10K_0402_5%

1 2

R557 10K_0402_5%R557 10K_0402_5%

1 2

DDR_A_CLK1 <5> DDR_A_CLK#1 <5>

DDR_CKE1_DIMMA <5>

DDR_A_BS#1 <5> DDR_A_RAS# <5> DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_A_CLK2 <5> DDR_A_CLK#2 <5>

0.1U_0402_16V4Z

C746

1

2

4.7U_0805_10V4Z

DDR_A_D[0..63]<5> DDR_A_DM[0..7]<5>

DDR_A_DQS[0..7]<5> DDR_A_MA[0..15]<5>

DDR_A_DQS#[0..7]<5>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

4.7U_0805_10V4Z

+3VS

1

2

DDR_B_D[0..63]<5> DDR_B_DM[0..7]<5>

DDR_B_DQS[0..7]<5> DDR_B_MA[0..15]<5>

DDR_B_DQS#[0..7]<5>

+DIMM_VREF

C766

3

0.1U_0402_16V4Z

0.1U_0402_16V4Z C767

C767

1

2

DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7]

Compal Secret Data

2005/10/11 2009/06/11

Compal Secret Data

Deciphered Date

DDR_B_MA4 DDR_B_MA2 DDR_B_BS#1 DDR_B_MA0

DDR_B_MA11 DDR_B_MA7 DDR_B_MA6

DDR_B_BS#2 DDR_CKE0_DIMMB

DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12

DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA3

DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE#

DDR_CS0_DIMMB# DDR_B_RAS# DDR_B_MA13 DDR_B_ODT0

DDR_B_MA14 DDR_B_MA15

DDR_CKE1_DIMMB

RP9

47_0804_8P4R_5%

RP10

47_0804_8P4R_5%

RP11

47_0804_8P4R_5%

RP12

47_0804_8P4R_5%

RP13

47_0804_8P4R_5%

RP14

47_0804_8P4R_5%

RP15

47_0804_8P4R_5%

RP16

47_0804_8P4R_5%

+0.9V

18

C764 0.1U_0402_16V4ZC764 0.1U_0402_16V4Z

27 36

1 2

C765 0.1U_0402_16V4ZC765 0.1U_0402_16V4Z

45

18

C769 0.1U_0402_16V4ZC769 0.1U_0402_16V4Z

27

1 2

36

C768 0.1U_0402_16V4ZC768 0.1U_0402_16V4Z

45

18

C770 0.1U_0402_16V4ZC770 0.1U_0402_16V4Z

27

1 2

36

C771 0.1U_0402_16V4ZC771 0.1U_0402_16V4Z

45

18

C772 0.1U_0402_16V4ZC772 0.1U_0402_16V4Z

27

1 2

36

C773 0.1U_0402_16V4ZC773 0.1U_0402_16V4Z

45

18

C774 0.1U_0402_16V4ZC774 0.1U_0402_16V4Z

27 36

1 2

C775 0.1U_0402_16V4ZC775 0.1U_0402_16V4Z

45

18

C776 0.1U_0402_16V4ZC776 0.1U_0402_16V4Z

27 36

1 2

C777 0.1U_0402_16V4ZC777 0.1U_0402_16V4Z

45

18

C778 0.1U_0402_16V4ZC778 0.1U_0402_16V4Z

27

1 2

36

C779 0.1U_0402_16V4ZC779 0.1U_0402_16V4Z

45

18

C780 0.1U_0402_16V4ZC780 0.1U_0402_16V4Z

27 36

1 2

C781 0.1U_0402_16V4ZC781 0.1U_0402_16V4Z

45

12

+1.8V

COMPAL Electronics，Inc

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SCHEMATIC A5931.

401814

1

C

of

943Friday, January 08, 2010

+1.8V

JDIMM2

1

VREF

3 DDR_B_D0 DDR_B_D1

D D

C C

DDR_CKE0_DIMMB<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5> DDR_B_WE#<5>

DDR_B_CAS#<5> DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

B B

SB_CK_SDAT<8,20,25>

A A

SB_CK_SCLK<8,20,25>

5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D22 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS1_DIMMB#

DDR_B_ODT1 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D47 DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_DM7 DDR_B_D58

DDR_B_D59 SB_CK_SDAT

SB_CK_SCLK

+3VS

1

C782

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

203

GND

FOX_AS0A426-M2RN-7F

FOX_AS0A426-M2RN-7F ME@

ME@

VSS DQ4 DQ5

VSS DM0

VSS DQ6 DQ7

VSS

DQ12 DQ13

VSS DM1

VSS

CK0

CK0#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS

NC

DM2

VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

NC/CKE1

VDD

NC/A15 NC/A14

VDD

A11

A7 A6

VDD

A4 A2 A0

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC

VSS

DQ36 DQ37

VSS DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS

CK1

CK1#

VSS DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS SAO

SA1 GND

KAV10 used

4

+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196

R558 10K_0402_5%R558 10K_0402_5%

198

R559 10K_0402_5%R559 10K_0402_5%

200 204

DDR_B_D4 DDR_B_D5

DDR_B_DM0 DDR_B_D6

DDR_B_D7 DDR_B_D12

DDR_B_D13 DDR_B_DM1 DDR_B_CLK1

DDR_B_CLK#1 DDR_B_D14

DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6DDR_B_MA8

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#

DDR_B_ODT0 DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D52

DDR_B_CLK2 DDR_B_CLK#2

DDR_B_DM6 DDR_B_D54

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

1 2 1 2

DDR_B_CLK1 <5> DDR_B_CLK#1 <5>

DDR_CKE1_DIMMB <5>

DDR_B_BS#1 <5> DDR_B_RAS# <5> DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_B_CLK2 <5> DDR_B_CLK#2 <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

E

PCIE_GTX_C_MRX_P[0..15]<14> PCIE_GTX_C_MRX_N[0..15]<14>

1 1

2 2

PCIE_PTX_C_IRX_P1<29> PCIE_PTX_C_IRX_N1<29> PCIE_PTX_C_IRX_P2<29> PCIE_PTX_C_IRX_N2<29>

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15

SB_RX0P<24> SB_RX0N<24> SB_RX1P<24> SB_RX1N<24> SB_RX2P<24> SB_RX2N<24> SB_RX3P<24> SB_RX3N<24>

U4B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

PART 2 OF 6

GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

PCIE_MTX_GRX_P0

A5

PCIE_MTX_GRX_N0

B5

PCIE_MTX_GRX_P1

A4

PCIE_MTX_GRX_N1

B4

PCIE_MTX_GRX_P2

C3

PCIE_MTX_GRX_N2

B2

PCIE_MTX_GRX_P3

D1

PCIE_MTX_GRX_N3

D2 E2 E1 F4 F3 F1 F2 H4 H3

PCIE_MTX_GRX_P8

H1

PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8

H2

PCIE_MTX_GRX_P9

J2

PCIE_MTX_GRX_N9

J1

PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10

K4

PCIE_MTX_GRX_N10

K3

PCIE_MTX_GRX_P11

K1

PCIE_MTX_GRX_N11

K2

PCIE_MTX_GRX_P12

M4

PCIE_MTX_GRX_N12

M3

PCIE_MTX_GRX_P13

M1

PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13

M2

PCIE_MTX_GRX_P14

N2

PCIE_MTX_GRX_N14

N1

PCIE_MTX_GRX_P15

P1

PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15

P2 AC1

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1 Y1 Y2 Y4 Y3 V1 V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5 AC8

AB8

R560 1.27K_0402_1%R560 1.27K_0402_1% R561 2K_0402_1%R561 2K_0402_1%

RS780M Display Port Support (muxed on GFX)

DP0

3 3

4 4

DP1

GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

C800 0.1U_0402_16V7KVGA@C800 0.1U_0402_16V7KVGA@

1 2

C802 0.1U_0402_16V7KVGA@C802 0.1U_0402_16V7KVGA@

1 2

C804 0.1U_0402_16V7KVGA@C804 0.1U_0402_16V7KVGA@

1 2

C806 0.1U_0402_16V7KVGA@C806 0.1U_0402_16V7KVGA@

1 2

C808 0.1U_0402_16V7KVGA@C808 0.1U_0402_16V7KVGA@

1 2

C810 0.1U_0402_16V7KVGA@C810 0.1U_0402_16V7KVGA@

1 2

C812 0.1U_0402_16V7KVGA@C812 0.1U_0402_16V7KVGA@

1 2

C814 0.1U_0402_16V7KVGA@C814 0.1U_0402_16V7KVGA@

1 2

C815 0.1U_0402_16V7KC815 0.1U_0402_16V7K

1 2

C816 0.1U_0402_16V7KC816 0.1U_0402_16V7K

1 2

C817 0.1U_0402_16V7KC817 0.1U_0402_16V7K

1 2

C818 0.1U_0402_16V7KC818 0.1U_0402_16V7K

1 2

C819 0.1U_0402_16V7KC819 0.1U_0402_16V7K

1 2

C820 0.1U_0402_16V7KC820 0.1U_0402_16V7K

1 2

C821 0.1U_0402_16V7KC821 0.1U_0402_16V7K

1 2

C822 0.1U_0402_16V7KC822 0.1U_0402_16V7K

1 2

C823 0.1U_0402_16V7KC823 0.1U_0402_16V7K

1 2

C824 0.1U_0402_16V7KC824 0.1U_0402_16V7K

1 2

C825 0.1U_0402_16V7KC825 0.1U_0402_16V7K

1 2

C826 0.1U_0402_16V7KC826 0.1U_0402_16V7K

1 2

1 2 1 2

C799 0.1U_0402_16V7KVGA@C799 0.1U_0402_16V7KVGA@ C801 0.1U_0402_16V7KVGA@C801 0.1U_0402_16V7KVGA@ C803 0.1U_0402_16V7KVGA@C803 0.1U_0402_16V7KVGA@ C805 0.1U_0402_16V7KVGA@C805 0.1U_0402_16V7KVGA@ C807 0.1U_0402_16V7KVGA@C807 0.1U_0402_16V7KVGA@ C809 0.1U_0402_16V7KVGA@C809 0.1U_0402_16V7KVGA@ C811 0.1U_0402_16V7KVGA@C811 0.1U_0402_16V7KVGA@ C813 0.1U_0402_16V7KVGA@C813 0.1U_0402_16V7KVGA@

+1.1VS

PCIE_MTX_C_GRX_P[0..15] <14>

PCIE_MTX_C_GRX_N[0..15] <14>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PCIE_ITX_C_PRX_P1 <29> PCIE_ITX_C_PRX_N1 <29> PCIE_ITX_C_PRX_P2 <29> PCIE_ITX_C_PRX_N2 <29>

SB_TX0P <24> SB_TX0N <24> SB_TX1P <24> SB_TX1N <24> SB_TX2P <24> SB_TX2N <24> SB_TX3P <24> SB_TX3N <24>

PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15

WLAN GLAN

H_CLKOP0<4> H_CLKON0<4> H_CLKOP1<4> H_CLKON1<4>

H_CTLOP0<4> H_CTLON0<4> H_CTLOP1<4> H_CTLON1<4>

R562

1 2

301_0402_1%

0718 Place within 1" layout 1:2

301_0402_1%

PCIE_MTX_GRX_N[0..3]

PCIE_MTX_GRX_P[0..3]

H_CADOP[0..15]<4> H_CADON[0..15]<4> H_CADIN[0..15] <4>

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7

H_CADOP8 H_CADON8 H_CADOP9 H_CADON9

H_CADOP10

H_CADON10

H_CADOP11

H_CADON11

H_CADOP12

H_CADON12

H_CADOP13

H_CADON13

H_CADOP14

H_CADON14

H_CADOP15

H_CADON15

H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLIP1 H_CTLON1

H_CADON[0..15]

Y25 Y24 V22 V23 V25

V24 U24 U25

T25

T24

P22

P23

P25

P24 N24 N25

AC24 AC25 AB25 AB24 AA24 AA25

Y22

Y23 W21 W20

V21

V20 U20 U21 U19 U18

T22

T23

AB23 AA22

M22 M23 R21 R20

C23

A24

PCIE_MTX_GRX_N[0..3] <22> PCIE_MTX_GRX_P[0..3] <22>

U4A

HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N

HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N

HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N

HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N

HT_RXCALP HT_RXCALN

RS780M_FCBGA528

H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]

PART 1 OF 6

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP HT_TXCALN

H_CADIP[0..15] <4>

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18 H24

H25 L21 L20

H_CTLIP0

M24

H_CTLIN0

M25 P19

H_CTLIN1

R18 B24

B25

0718 Place within 1" layout 1:2

301_0402_1%

SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA

H_CLKIP0 <4> H_CLKIN0 <4> H_CLKIP1 <4> H_CLKIN1 <4>

H_CTLIP0 <4> H_CTLIN0 <4> H_CTLIP1 <4> H_CTLIN1 <4>

R563

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

10 43Friday, January 08, 2010

A

+1.1VS

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

1 1

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+1.8VS

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+1.8VS

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

2 2

CLK_NB_14.318M

12

R571

R571 100_0402_5%

100_0402_5% @

@

3 3

1

C842

C842 100P_0402_25V8K

100P_0402_25V8K

2

@

Mode

PX mode High

4 4

DIS Only High High

PLLVDD=65mA

L126

L128

L130

L132

+NB_PLLVDD

1

C828

C831

1

2

PLLVDD18=20mA

+NB_HTPVDD+1.8VS

1

2

VDDA18HTPLL=20mA

+VDDA18HTPLL

1

C834

2

VDDA18PCIEPLL=0.12A

+VDDA18PCIEPLL

1

C838

2

11/16 update

R665

4.7K_0402_5%

4.7K_0402_5% VGA@

GMCH_HDMI_DATA_R2

VGA@

PX_EN<24>

NC7SZ08P5X_NL_SC70-5

PX_EN

GMCH_HDMI_DATA_R2

X(Don't Care)

LOWIGP Only

ALLOW_LDTSTOP<24>

A

C829

C829 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C832

C832 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C835

C835 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C839

C839 1U_0402_6.3V4Z

1U_0402_6.3V4Z

PLT_RST#<13,14,24,29>

NB_PWRGD<25>

+1.8VS

R568 300_0402_5%R568 300_0402_5%

1 2

+1.1VS

R569

4.7K_0402_5%

+3VS

R575 4.7K_0402_5%@R575 4.7K_0402_5%@

1 2

R576 4.7K_0402_5%

1 2

@

+3VS

12

5

U27

2

P

B

4

Y

1

A

G

3

VGA@

High/LOW

+1.8VS

FBM-L11-201209-300LMA30T_0805

1 2

2.2U_0603_6.3V4Z

11/26 update

+1.8VS

U47

5

NC7SZ08P5X_NL_SC70-5

NB_PWRGD

SB_PWRGD<6,25,29>

1 2

R570

4.7K_0402_5%

12

NC7SZ08P5X_NL_SC70-5

2

P

B

1

A

G

3

11/26 update

DDC2_DATA DDC2_DATA

+3VS

12

R590

4.7K_0402_5%

VGA@

DP_SELECT <21,23>

+1.8VS

12

R586

1K_0402_5%

R589 0_0402_5%R589 0_0402_5%

1 2

B

For RS780M A13 RED: Connected to GND through two separate 140ohm 1% resistor

AVDD=0.11A

L125

1 2

+AVDD2

1

2

GMCH_CRT_R<23> GMCH_CRT_G<23> GMCH_CRT_B<23>

R567

R567 715_0402_1%

715_0402_1%

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

NB_RESET# NB_PWRGD_R

CLK_NBHT<20> CLK_NBHT#<20>

POWER_SEL

GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B

+AVDD1

GMCH_CRT_R GMCH_CRT_G GMCH_CRT_B

GMCH_CRT_HSYNC GMCH_CRT_VSYNC

CRT_DDC_CLK CRT_DDC_DATA

1 2

+NB_PLLVDD +NB_HTPVDD

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

CLK_NB_14.318M

DDC2_CLKDDC2_CLK

GMCH_HDMI_DATA_R2 GMCH_HDMI_CLK_R1

GMCH_HDMI_DATA_R1

AUX_CAL<13>

Strap pin

1

2

DAC_RSET

C827

2.2U_0603_6.3V4Z

U4C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

1 2

R564 140_0402_1%R564 140_0402_1%

1 2

R565 150_0402_1%R565 150_0402_1%

1 2

R566 150_0402_1%R566 150_0402_1%

+3VS

FBM-L11-201209-300LMA30T_0805

AVDDDI=20mA

L127

1 2

FBM-L11-201209-300LMA30T_0805

AVDDQ=4mA

L129

C833

4

Y

R974 0_0402_5%R974 0_0402_5% 1 2 1 2

R975 0_0402_5%@R975 0_0402_5%@

POWER_SEL<36>

C830

0.1U_0402_16V4Z

+AVDDQ

1

2

GMCH_CRT_HSYNC<13,23> GMCH_CRT_VSYNC<13,23>

CRT_DDC_CLK<23,29> CRT_DDC_DATA<23,29>

CLK_NB_14.318M<20>

CLK_NBGFX<20> CLK_NBGFX#<20>

CLK_SBLINK_BCLK<20> CLK_SBLINK_BCLK#<20>

DDC2_CLK<21,29>

DDC2_DATA<21,29>

POWER_SEL

HIGH 1.0V

1.1VLOW

NB_ALLOW_LDTSTOP

B

GMCH_HDMI_CLK<22> GMCH_HDMI_DATA<22>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GMCH_HDMI_CLK GMCH_HDMI_DATA GMCH_HDMI_DATA_R1

LDT_STOP#<6,24>

Issued Date

C

HPD(NC)

TESTMODE

Deciphered Date

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

4.7K_0402_5%

D9 D10

D12 AE8

AD8 D13

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

CLOCKs PLL PWR

MIS.

R582 0_0402_5%UMA@R582 0_0402_5%UMA@

1 2 1 2

R583 0_0402_5%UMA@R583 0_0402_5%UMA@

0_0402_5%

1 2

R588

2008/10/06 2009/10/06

C

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)

TXOUT_U0N(NC)

TXOUT_U2P(NC) TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC) VSSLTP18(NC)

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

THERMALDIODE_P THERMALDIODE_N

GMCH_HDMI_CLK_R1

NB_LDTSTOP#

Compal Secret Data

+VDDLTP18

+VDDLT18

12

R572

1 2

R577 0_0402_5%R577 0_0402_5%

1 2

R579

1.8K_0402_5%

D

GMCH_TXOUT0+ <21> GMCH_TXOUT0- <21> GMCH_TXOUT1+ <21> GMCH_TXOUT1- <21> GMCH_TXOUT2+ <21> GMCH_TXOUT2- <21>

GMCH_TXCLK+ <21> GMCH_TXCLK- <21>

R573

1 2

1.27K_0402_1%

R639

1 2

UMA@

0_0402_5%

D

UMA_ENVDD UMA_DPST UMA_ENBKL

R574

1 2

1.27K_0402_1%

HDMI_DET <15,29>

SUS_STAT# <25> SUS_STAT_R# <13>

UMA_ENVDD

UMA_DPST

UMA_ENBKL

E

VDDLTP18=15mA

+VDDLTP18

1U_0402_6.3V4Z

VDDLT18=0.3A

+VDDLT18

C840

0.1U_0402_16V4Z

UMA_ENVDD <21> UMA_ENBKL <21>

C836

1

2

1

2

L131

1 2

MBC1608121YZF_0603

MBC1608121YZF_0603 C837

C837

2.2U_0603_6.3V4Z

L133

1 2

MBC1608121YZF_0603

C841

4.7U_0805_10V4Z

+1.8VS

Strap pin

R581 0_0402_5%

1 2

UMA@

1 2

R584 0_0402_5%@R584 0_0402_5%@

R587 0_0402_5%

1 2

UMA@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

ENVDD <21,29>

DPST_PWM <29>

ENBKL <21,29>

E

of

11 43Friday, January 08, 2010

C

A

VDDHTRX+VDDHT=0.68A

0.1U_0402_16V4Z

L134

+1.1VS

FBMA-L11-201209-221LMA30T_0805

1 1

FBMA-L11-201209-221LMA30T_0805

L137

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

FOR Version A11 pop 1.35VS A12 use 1.2V_HT

2 2

L137

+1.8VS

FBMA-L11-201209-221LMA30T_0805

L134

L136

12

VDDA18PCIE=0.7A

L140

12

C877

10U_0805_10V4Z

0.1U_0402_16V4Z

12

1

C845

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

12

1

C853

C843

2

4.7U_0805_10V4Z

VDDHTTX=0.68A

0.1U_0402_16V4Z

1

C858

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1

C868

2

4.7U_0805_10V4Z

+1.8VS

1U_0402_6.3V4Z

C846

C859

C869

1

2

C881

1

C847

2

0.1U_0402_16V4Z

1U_0402_6.3V4Z

1

C854

C844

2

0.1U_0402_16V4Z

1

C860

2

0.1U_0402_16V4Z

1

C878

2

0.1U_0402_16V4Z

1

2

1U_0402_6.3V4Z

1

C848

2

1

2

1

C861

C862

2

1U_0402_6.3V4Z

1

C870

C872

2

0.1U_0402_16V4Z

VDD18=10mA

+VDDHTRX

+VDDHTTX

1

2

+VDDA18PCIE

1

2

+VDDHT

B

U4E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

AE25

VDDHTTX_1

AD24

VDDHTTX_2

AC23

VDDHTTX_3

AB22

VDDHTTX_4

AA21

VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2

AE11

VDD18_MEM1(NC)

AD11

VDD18_MEM2(NC)

RS780M_FCBGA528

PART 5/6

VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

POWER

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)

VDD33_1(NC) VDD33_2(NC)

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

C

VDDPCIE=1.1A

+1.1VS

1

C8630.1U_0402_16V4Z C8630.1U_0402_16V4Z

2

VDD33=60mA

C882

0.1U_0402_16V4Z

C849 10U_0603_6.3V6MC849 10U_0603_6.3V6M C850 10U_0603_6.3V6MC850 10U_0603_6.3V6M

C851 4.7U_0805_10V4ZC851 4.7U_0805_10V4Z C852 1U_0402_6.3V4ZC852 1U_0402_6.3V4Z

C855 1U_0402_6.3V4ZC855 1U_0402_6.3V4Z

C856 0.1U_0402_16V4ZC856 0.1U_0402_16V4Z C857 0.1U_0402_16V4ZC857 0.1U_0402_16V4Z

VDDC=7.6A

1

C8640.1U_0402_16V4Z C8640.1U_0402_16V4Z

2

1

2

1

C8740.1U_0402_16V4Z C8740.1U_0402_16V4Z

C8790.1U_0402_16V4Z C8790.1U_0402_16V4Z

C8650.1U_0402_16V4Z C8650.1U_0402_16V4Z

C8730.1U_0402_16V4Z C8730.1U_0402_16V4Z

2

1

C883

0.1U_0402_16V4Z

2

1 2 1 2

1 2

1

C8660.1U_0402_16V4Z C8660.1U_0402_16V4Z

2

D

U4F

A25

VSSAHT1

D23

VSSAHT2

+1.1VS

+NB_CORE

C871 330U_D2E_2.5VM_R9M+C871 330U_D2E_2.5VM_R9M

1

C8750.1U_0402_16V4Z C8750.1U_0402_16V4Z

C8800.1U_0402_16V4Z C8800.1U_0402_16V4Z

2

+3VS

1

C87610U_0603_6.3V6M C87610U_0603_6.3V6M

C86710U_0603_6.3V6M C86710U_0603_6.3V6M

+

2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

PART 6/6

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

12 43Friday, January 08, 2010

A

B

C

D

E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO. (VSYNC) 1 : Disable (RS780) 0 : Enable (Rs780)

1 1

GMCH_CRT_VSYNC<11,23>

12

R592 3K_0402_5%R592 3K_0402_5%

12

R593 3K_0402_5%@R593 3K_0402_5%@

+3VS

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

AUX_CAL<11>

RS780 DFT_GPIO1

SUS_STAT_R#<11> PLT_RST# <11,14,24,29>

2 2

1 2

R594 150_0402_1%@ R594 150_0402_1%@

D1 CH751H-40_SC76@D1CH751H-40_SC76@

2 1

R595 3K_0402_5%@R595 3K_0402_5%@

12

RS780 use HSYNC to enable SIDE PORT

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

For E-Machine disable side port

0. Enable (RS780) 1 : Disable(RS780)

RS780 use HSYNC to enable SIDE PORT

R985

12

15mA

12

GMCH_CRT_HSYNC<11,23>

U4D

PAR 4 OF 6

MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)

MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)

MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)

MEM_CKP(NC) MEM_CKN(NC)

MEM_COMPP(NC) MEM_COMPN(NC)

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)

MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC) MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC) IOPLLVSS(NC)

MEM_VREF(NC)

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

AB12 AE16

3 3

4 4

V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14

Y14 AD16

AE17 AD17

W12

Y12 AD18 AB13 AB18

V14

V15

W14

AE12 AD12

RS780M_FCBGA528

+1.8VS=W/S=20/10mil For Memory PLL power +1.1VS=W/S=20/10mil For Memory PLL power

26mA

R596 3K_0402_5%R596 3K_0402_5%

0_0603_5%

+1.1VS

+3VS

12/2 update

R984

0_0603_5%

+1.8VS

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

13 43Friday, January 08, 2010

5

U5A

4

3

2

PCIE_GTX_C_MRX_P[0..15]<10> PCIE_GTX_C_MRX_N[0..15]<10> PCIE_MTX_C_GRX_P[0..15]<10> PCIE_MTX_C_GRX_N[0..15]<10>

1

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_N15

D D

C C

B B

CLK_PCIE_VGA<20> CLK_PCIE_VGA#<20>

A A

PCIE_MTX_C_GRX_P15

PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12

PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P11

PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P8

CLK_PCIE_VGA CLK_PCIE_VGA#

PARK@

R601 10K_0402_5%

5

12

MXM_RST#

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

PWRGOOD

AL27

PERSTB

M9X-S2/S3 + Park-S3

VGA@

CLOCK

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP PCIE_CALRN

4

PEG_NRX_C_GTX_N15 PCIE_GTX_C_MRX_N15

AH30

PEG_NRX_C_GTX_P15 PCIE_GTX_C_MRX_P15

AG31

AG29

PEG_NRX_C_GTX_P14 PCIE_GTX_C_MRX_P14

AF28

PEG_NRX_C_GTX_N13 PCIE_GTX_C_MRX_N13

AF27 AF26

AD27 AD26

PEG_NRX_C_GTX_N11

AC25 AB25

PEG_NRX_C_GTX_N10

Y23 Y24

PEG_NRX_C_GTX_N9

AB27

PEG_NRX_C_GTX_P9

AB26

PEG_NRX_C_GTX_N8

Y27

PEG_NRX_C_GTX_P8

Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22 AA22

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2 1 2

Issued Date

C884 0.1U_0402_16V7K

C884 0.1U_0402_16V7K C885 0.1U_0402_16V7K

C885 0.1U_0402_16V7K

C886 0.1U_0402_16V7K

C886 0.1U_0402_16V7K C887 0.1U_0402_16V7K

C887 0.1U_0402_16V7K

C888 0.1U_0402_16V7K

C888 0.1U_0402_16V7K C889 0.1U_0402_16V7K

C889 0.1U_0402_16V7K

C890 0.1U_0402_16V7K

C890 0.1U_0402_16V7K C891 0.1U_0402_16V7K

C891 0.1U_0402_16V7K

C893 0.1U_0402_16V7K

C893 0.1U_0402_16V7K C894 0.1U_0402_16V7K

C894 0.1U_0402_16V7K

C892 0.1U_0402_16V7K

C892 0.1U_0402_16V7K C895 0.1U_0402_16V7K

C895 0.1U_0402_16V7K

C896 0.1U_0402_16V7K

C896 0.1U_0402_16V7K C897 0.1U_0402_16V7K

C897 0.1U_0402_16V7K

C898 0.1U_0402_16V7K

C898 0.1U_0402_16V7K C899 0.1U_0402_16V7K

C899 0.1U_0402_16V7K

R6001.27K_0402_1% VGA@ R6001.27K_0402_1% VGA@ R6022K_0402_5% VGA@ R6022K_0402_5% VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

PLT_RST#<11,13,24,29>

DGPU_HOLD_RST#<24>

+1.1/1.0VS_VGA

2008/10/06 2009/10/06

NC7SZ08P5X_NL_SC70-5

3

Compal Secret Data

PCIE_GTX_C_MRX_N14PEG_NRX_C_GTX_N14

PCIE_GTX_C_MRX_P13PEG_NRX_C_GTX_P13

PCIE_GTX_C_MRX_N12PEG_NRX_C_GTX_N12 PCIE_GTX_C_MRX_P12PEG_NRX_C_GTX_P12

PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11PEG_NRX_C_GTX_P11

PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10PEG_NRX_C_GTX_P10

PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9

PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8

+3VS_VGA

5

U26

2

P

B

1

A

G

3

VGA@

MXM_PWRGD<40>

Deciphered Date

Y

PEG_RST#

4

R976

R976 0_0402_5%

0_0402_5%

@

1 2

U5F

LVDS CONTROL

LVTMDP

M9X-S2/S3 + Park-S3

+3VS_VGA

5

U29

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

VGA@

@ R977

@

1 2 0_0402_5%

0_0402_5%

2

@

R598

1 2

10K_0402_5%

R599

@ R599

@

1 2

AB11

VARY_BL

DIGON

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

VGA@

AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

0_0402_5%

R671

R671 10K_0402_5%

10K_0402_5%

VGA@

1 2

11/24 update

MXM_RST#

4

R977

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

MXM_RST# <21>

1

VGA_PWM <29> ENVDD_R <21>

VGA_TXCLK+ <21> VGA_TXCLK- <21>

VGA_TXOUT0+ <21> VGA_TXOUT0- <21>

VGA_TXOUT1+ <21> VGA_TXOUT1- <21>

VGA_TXOUT2+ <21> VGA_TXOUT2- <21>

of

14 43Friday, January 08, 2010

C

5

L143

VGA@

L84

VGA@

L83

PARK@

L144

VGA@

L145

ENBKL_R<21>

R620 82.5_0402_1%@R620 82.5_0402_1%@

1 2

12

R866

1 2

82.5_0402_1%@

12

VGA@

VGA@ 1

C1288

2

27M_NSSC<20>

VGA@

1

C1285

2

PARK@

PARK@ 1

C919

2

10U_0603_6.3V6M

VGA@

VGA@ 1

C918

2

10U_0603_6.3V6M

VGA@

1

C922

2

10U_0603_6.3V6M

12

VGA@

VGA@ 1

C1284

C1284 2

10U_0603_6.3V6M

VGA@

VGA@ 1

C1287

C1287 2

10U_0603_6.3V6M

27MCLK_SSICCLK_XTALIN

+1.8VS_VGA

BLM15BD121SN1D_0402

D D

+1.1/1.0VS_VGA

BLM15BD121SN1D_0402

+1.8VS_VGA

BLM15BD121SN1D_0402

C C

27M_SSC<20>

+3VS_VGA

R627 5.11K_0402_1%@R627 5.11K_0402_1%@

B B

BLM15BD121SN1D_0402

VGA@

11/24 update

A A

+1.8VS_VGA

R978

0_0402_5%

VGA@

12

@

@ 1

2

C1294

10U_0603_6.3V6M

5

PARK@

PARK@ 1 C916

C916

2

1U_0402_6.3V4Z

VGA@

VGA@ 1 C920

C920

2

1U_0402_6.3V4Z

VGA@

VGA@ 1

C924

C923

2

1U_0402_6.3V4Z

+3VS_VGA

ACIN<26,29>

1 2

12

R621

R621 100_0402_1%

100_0402_1% @

@

TEST_EN

VGA@

VGA@ 1

C1283

C1283 2

1U_0402_6.3V4Z

+DPLL_PVDD+1.8VS_VGA

VGA@

VGA@ 1

C1286

C1286 2

1U_0402_6.3V4Z

0.1U_0402_10V6K

XTALOUT_XTL

@

@ 1

2 C1295

C1295

1U_0402_6.3V4Z

+DPC_VDD18

PARK@

PARK@ 1 C917

C917

2

0.1U_0402_10V6K

+DPC_VDD10

VGA@

VGA@ 1 C921

C921

2

0.1U_0402_10V6K

+DPC_PVDD

VGA@

VGA@ 1

2

0.1U_0402_10V6K

VGA_LCD_CLK<21> VGA_LCD_DATA<21>

R617

1 2

10K_0402_5%

D2

1 2

R669 10K_0402_5%

R669 10K_0402_5% VGA@

VGA@

VGA_PWRSEL0<40>

+DPLL_VDDC+1.1/1.0VS_VGA

TEST_EN<16>

+1.8VS_VGA

0.1U_0402_10V6K

R630

499_0402_1%

VGA@

R633

249_0402_1%

VGA@

R635 82.5_0402_1%VGA@R635 82.5_0402_1%VGA@

1 2

@

@ 1

2 C1296

C1296

0.1U_0402_10V6K

AE9

N9 AE8 AD9

AC10

AD7 AC8 AC7 AB9 AB8 AB7 AB4

VRAM_ID2

VRAM_ID2<16> VRAM_ID1<16> VRAM_ID0<16>

+DPC_PVDD

+DPC_VDD18

+DPC_VDD10

VGA_LCD_CLK VGA_LCD_DATA

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

@R617

@

21

RB751V_SOD323@D2RB751V_SOD323@

R618

VGA@R618

VGA@

GPU_GPIO8

0_0402_5%

GPU_GPIO9 GPU_GPIO11

GPU_GPIO12 GPU_GPIO13

VGA_PWRSEL0

27M_SSC_R

THM_ALERT#

R622

1 2

10K_0402_5%

TEST_EN

1 2

R628 10K_0402_5%

R628 10K_0402_5% VGA@

VGA@

12

R865

+VREFG_GPU

VGA@

VGA@ 1 C931

C931

2

0.1U_0402_10V6K

+DPLL_VDDC

12

0_0402_5%@

HDMI_DET<11,29>

+DPLL_PVDD

12

R636

R636 100_0402_1%

100_0402_1% VGA@

VGA@

GPU_THERMAL_D+ GPU_THERMAL_D-

VRAM_ID1 VRAM_ID0

@R622

@

TP9TP9 TP10TP10 TP11TP11 TP12TP12 TP13TP13

CLK_XTALIN

CLK_XTALOUT

W10

AF24 AB13

AD10 AC14

AC16

AF14 AE14

AD14

AM28 AK28

AC22 AB22

AD17 AC17

AB2

Y8

Y7

W6

V6 AC6

AC5 AA5

AA6

U1

W1

U3

Y6 AA1

R1

R3

U6 U10

T10

U8

U7

T9

T8

T7

P10

P4

P2

N6

N5

N3

Y9

N1

M4

R6

M2

P8

P7

N8

N7

K4

W8

W9

W7

T4

T2

R5

4

U5B

M93-S3/M92-S2

DVCNTL_0/ DVPDATA_18

L9

DVCNTL_1 / NC DVCNTL_2 / TESTEN#2 DVDATA_12 / DVPDATA_16 DVDATA_11 / DVPDATA_20 DVDATA_10 / DVPDATA_22 DVDATA_9 / DVPDATA_12 DVDATA_8 / DVPDATA_14 DVDATA_7 / DVPCNTL_0 DVDATA_6 / DVPDATA_8 DVDATA_5 / DVPDATA_6 DVDATA_4 DVPDATA_4 DVDATA_3 / DVPDATA_19 DVDATA_2 / DVPDATA_21 DVDATA_1 / DVPDATA_2 DVDATA_0 / DVPDATA_0

DVO

M93-S3/M92-S2

DPC_PVDD / DVPDATA_11 DPC_PVSS / GND

DPC_VDD18#1/DVPDAT10 DPC_VDD18#2/DVPDAT23

DPC_VDD10#1/DVPDAT15 DPC_VDD10#2/DVPDAT17

DPC_VSSR#1 / DVPCLK DPC_VSSR#2 / DVPDAT5 DPC_VSSR#3 / GND DPC_VSSR#4 / GND DPC_VSSR#5/ DVPCNTL_MV0

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS JTAG_TDO TESTEN

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4

HPD1

VREFG

PLL/CLOCK

DPLL_PVDD DPLL_PVSS

DPLL_VDDC

XTALIN XTALOUT

NC#2/XO_IN NC#1/XO_IN2

THERMAL

DPLUS DMINUS

TS_FDO TSVDD TSVSS

M9X-S2/S3 + Park-S3

VGA@

4

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

DPA

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

DPB

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

M92-S2/M93-S3

DVPDATA_3/TXCCP_DPC3P DVPCNTL_2/TXCCM_DPC3N

DVPDATA_7 / TX0P_DPC2P DVPDATA_1 / TX0M_DPC2N

DVPCNTL_MV1 / TX1P_DPC1P

DVPDATA_9 / TX1M_DPC1N

DVPDATA_13 / TX2P_DPC0P

DVPCNTL_1 / TX2M_DPC0N

VDDR4 / DPCD_CALR

DPC

DAC1

HSYNC VSYNC

RSET AVDD

AVSSQ

VDD1DI VSS1DI

M92-S2/M93-S3

R2 / NC

R2B / NC

G2 / NC

G2B / NC

B2 / NC

B2B / NC

C / NC

DAC2

Y / NC

COMP / NC

H2SYNC V2SYNC

VDD2DI / NC

VSS2DI / NC

A2VDD / NC

A2VDDQ / NC

A2VSSQ

R2SET / NC

M92-S2/M93-S3M92-S2/M93-S3

DDC1CLK

DDC1DATA

AUX1P

DDC/AUX

AUX1N

DDC2CLK

DDC2DATA

AUX2P

AUX2N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

NC/DDCCLK_AUX3P

NC/DDCDATA_AUX3N

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

AA12

AM26

R

AK26

RB

AL25

G

AJ25

GB

AH24

B

AG25

BB

AH26 AJ27

AD22

+AVDD

AG24 AE22

+VDD2DI

AE23 AD23

AM12 AK12

AL11 AJ11

AK10 AL9

AH12 AM10 AJ9

AL13 AJ13

+VDD2DI

AD19 AC19

+A2VDD

AE20

+A2VDDQ

AE17 AE19

R634 715_0402_1%

AG13

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AE16 AD16

AC1 AC3

AD20 AC20

3

HDMI_CLK+_VGA <22> HDMI_CLK-_VGA <22>

HDMI_TX0+_VGA <22> HDMI_TX0-_VGA <22>

HDMI_TX1+_VGA <22> HDMI_TX1-_VGA <22>

HDMI_TX2+_VGA <22> HDMI_TX2-_VGA <22>

CLK_XTALOUT_R CLK_XTALOUT

12

R616

R616 150_0402_1%

150_0402_1% VGA@

VGA@

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

VGA_CRT_HSYNC VGA_CRT_VSYNC

VGA_CRT_HSYNC2 VGA_CRT_VSYNC2

1 2

VGA@

VGA_CRT_CLK VGA_CRT_DATA

R867

1 2

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

VGA_CRT_HSYNC VGA_CRT_VSYNC VGA_CRT_VSYNC2 VGA_CRT_HSYNC2

VGA_CRT_R <23>

VGA_CRT_G <23>

VGA_CRT_B <23>

VGA_CRT_HSYNC <23> VGA_CRT_VSYNC <23>

R619

1 2 499_0402_1%

499_0402_1%

VGA_CRT_CLK <23> VGA_CRT_DATA <23>

VGA_HDMI_SCLK <22,29> VGA_HDMI_SDATA <22,29>

3

2

CLK_XTALIN

12

R972

R972 1M_0402_5%

1M_0402_5% @

@

Y6

123

4

G2

G1

27MHZ_10PF_X3S027000BA1H-U~D

1

@

@ C1118

C1118

2

22P_0402_50V8J

0_0402_5%@

R603 10K_0402_5%@ R603 10K_0402_5%@ R604 10K_0402_5%@ R604 10K_0402_5%@ R605 10K_0402_5%@ R605 10K_0402_5%@

R606 10K_0402_5%@ R606 10K_0402_5%@ R607 10K_0402_5%@ R607 10K_0402_5%@

R609 10K_0402_5%VGA@R609 10K_0402_5%VGA@ R610 10K_0402_5%@ R610 10K_0402_5%@ R611 10K_0402_5%@ R611 10K_0402_5%@

R612 10K_0402_5%VGA@R612 10K_0402_5%VGA@ R613 10K_0402_5%VGA@R613 10K_0402_5%VGA@ R614 10K_0402_5%@ R614 10K_0402_5%@ R615 10K_0402_5%@ R615 10K_0402_5%@

VGA@R619

VGA@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CLK_XTALOUT_R

1

@

@ C1117

C1117

2

22P_0402_50V8J

+3VS_VGA

12 12 12

12 12

12 12 12

12 12 12 12

VGA_CRT_R VGA_CRT_G VGA_CRT_B

+3VS_VGA

12

R626

R626 10K_0402_5%

10K_0402_5% VGA@

VGA@

EC_SMB_CK2_PX

EC_SMB_DA2_PX

L148

+3VS_VGA

27MCLK_SSIC

XTALOUT_XTL

L148

BLM15BD121SN1D_0402

PARK@

U46

1

REFOUT

2

XOUT

3

XIN/CLKIN

ASM3P2872AF-06OR_TSOT-23-6@

27M_SSC_R

2008/10/06 2009/10/06

12

R623

150_0402_1%

VGA@

12

+3VS_VGA

R629

R629 10K_0402_5%

10K_0402_5% VGA@

VGA@

2

Q21A

2N7002DW-T/R7_SOT363-6

VGA@

12

PARK@

1

C934

C933

2

10U_0603_6.3V6M

6

VSS

5

MODOUT

4

VDD

R864

1 2

33_0402_1% @

0.1U_0402_10V6K

0.1U_0402_10V6K 1U_0402_6.3V4Z

1U_0402_6.3V4Z

Compal Secret Data

Deciphered Date

12

R624

150_0402_1%

2N7002DW-T/R7_SOT363-6

1U_0402_6.3V4Z

C1204

C1204 C1205

C1205

61

4

R625

VGA@

C935

12

PARK@

PARK@ 1

2

@

2

150_0402_1%

5

Q21B

+A2VDD

0.1U_0402_10V6K

+3VS_VGA

1

2

@

3

VGA@

C936 2200P_0402_50V7KVGA@C936 2200P_0402_50V7KVGA@

GPU_THERMAL_D-

EC_SMB_CK2 <6,29>

EC_SMB_DA2 <6,29>

0.1U_0402_16V4Z

GPU_THERMAL_D+

1 2

1

L185

+1.8VS_VGA

+3VS_VGA

2

C932

C932 VGA@

VGA@

1

Title

Size Document Number Rev

C

Date: Sheet

12

BLM15BD121SN1D_0402

VGA@

L146

12

BLM15BD121SN1D_0402

VGA@

L147

12

BLM15BD121SN1D_0402

PARK@

VGA_LCD_DATA VGA_LCD_CLK

U6

1

VDD

SCLK

2

D+

SDATA

3

ALERT#

DTHERM#4GND

ADM1032ARMZ REEL_MSOP8

ADM1032ARMZ REEL_MSOP8 VGA@

VGA@

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

VGA@

1

C939

2

10U_0603_6.3V6M

VGA@

1

C927

2

10U_0603_6.3V6M

PARK@

1

C928

2

10U_0603_6.3V6M

1 2 1 2

8 7 6 5

VGA@

VGA@ 1

C938

2

1U_0402_6.3V4Z

VGA@

VGA@ 1

C925

2

1U_0402_6.3V4Z

PARK@

PARK@ 1

C929

2

1U_0402_6.3V4Z

VGA@

R631

6.8K_0402_5%

6.8K_0402_5% R632

R632

6.8K_0402_5%

6.8K_0402_5% VGA@

VGA@

1

VGA@

VGA@ 1

C940

2

VGA@

VGA@ 1

C926

2

PARK@

PARK@ 1

C930

2

THM_ALERT#

+AVDD

0.1U_0402_10V6K

+VDD2DI

0.1U_0402_10V6K

+A2VDDQ

0.1U_0402_10V6K

+3VS_VGA

EC_SMB_CK2_PX EC_SMB_DA2_PX

1 2

R637 4.7K_0402_5%VGA@R637 4.7K_0402_5%VGA@

15 43Friday, January 08, 2010

+3VS_VGA

of

C

5

240

150 240

51.1

0.1uF

MDA[0..63] M_MA[13..0] M_DQM[7..0] M_DQS[7..0] M_DQS#[7..0]

R657

240_0402_1%

M93@

C943

0_0402_5%

M93@

C944

0_0402_5%

M93@

R660

4.7K_0402_5%

M93@

R661

4.7K_0402_5%

M93@

+1.8VS_VGA

TEST_EN<15>

PARK@

R4

R660 51.1_0402_1%

1 2 1 2

R661 51.1_0402_1%

PARK@

R5

MDA[0..63]<19> M_MA[13..0]<19> M_DQM[7..0]<19> M_DQS[7..0]<19>

+1.8VS_VGA

12

+1.8VS_VGA

12

M_DQS#[7..0]<19>

1

2

1

2

MVREFDA

C937

0.1U_0402_16V4Z

0.1U_0402_16V4Z VGA@

VGA@

MVREFSA

C941

0.1U_0402_16V4Z

0.1U_0402_16V4Z VGA@

VGA@

D D

R645

100_0402_5%

VGA@

R647

100_0402_5%

VGA@

C C

R649

100_0402_5%

VGA@

R650

100_0402_5%

VGA@

B B

M93-S3 PARK-S3 J25 K7 J8 K25

NC NC 0/short 240 NC

M93-S3 PARK-S3

A A

R4 R5 C2 C3

4.7K

4.7K 51.1 0/short 0/short

5

4

MVREFDA MVREFSA

PARK@

1 2

R654 240_0402_1%

1 2

R655 0_0402_5%PARK@ R655 0_0402_5%PARK@

PARK@

1 2

R657 150_0402_1%

1 2

R658 240_0402_1%PARK@R658 240_0402_1%PARK@

DRAM_RST

PARK@

C2

C943 0.1U_0402_16V4Z

1 2 1 2

C944 0.1U_0402_16V4Z

PARK@

C3

4

3

U5C

MDA0

K27

MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8

MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DQA_0

J29

DQA_1

H30

DQA_2

H32

DQA_3

G29

DQA_4

F28

DQA_5

F32

DQA_6

F30

DQA_7

C30

DQA_8

F27

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

J25

MEM_CALRN0

K7

NC/TESTEN#2

J8

MEM_CALRP1/DPC_CALR

K25

MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

M9X-S2/S3 + Park-S3

Issued Date

MAA_13/BA2 MAA_14/BA0 MAA_15/BA1

MEMORY INTERFACE

WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7

VGA@

2008/10/06 2009/10/06

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12

DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6 DQMA_7

RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7

ODTA0

ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B RASA0B

RASA1B CASA0B

CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0

CKEA1

WEA0B WEA1B

PX_EN

RSVD#2 RSVD#3

3

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

AB16

G14 G20

Compal Secret Data

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1

M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7

M_ODT0 M_ODT1

M_CLK0 M_CLK#0

M_CLK1 M_CLK#1

M_RAS#0 M_RAS#1

M_CAS#0 M_CAS#1

M_CS#0

M_CS#1

M_CKE0 M_CKE1

M_WE#0 M_WE#1

Deciphered Date

M_BA2 <19> M_BA0 <19> M_BA1 <19>

M_ODT0 <19> M_ODT1 <19>

M_CLK0 <19> M_CLK#0 <19>

M_CLK1 <19> M_CLK#1 <19>

M_RAS#0 <19> M_RAS#1 <19>

M_CAS#0 <19> M_CAS#1 <19>

M_CS#0 <19>

M_CS#1 <19>

M_CKE0 <19> M_CKE1 <19>

M_WE#0 <19> M_WE#1 <19>

2

+1.8VS_VGA

R638 10K_0402_5%H@R638 10K_0402_5%H@

1 2

R640 10K_0402_5%S@R640 10K_0402_5%S@

1 2

R641 10K_0402_5%S@R641 10K_0402_5%S@

1 2

R642 10K_0402_5%H@R642 10K_0402_5%H@

1 2

R643 10K_0402_5%@R643 10K_0402_5%@

1 2

R644 10K_0402_5%VGA@R644 10K_0402_5%VGA@

1 2

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

Hynix H5TQ1G63BFR-12C

SA000032410

Samsung K4W1G1646E-HC12

SA000035710

R1 R2 R3 C1

C942

R656

0_0402_5%

M93@

DRAM_RST

C942

2200P 50V K X7R 0402

M93@

R656

R656 PARK@

PARK@

1 2

R2

12

680_0402_5%

R659

R659 10K_0402_5%

10K_0402_5%

R1

PARK@

Title

Size Document Number Rev

B

Date: Sheet

SCHEMATIC A5931.

1

VRAM_ID0 VRAM_ID1 VRAM_ID2

1

00

1

VRAM_ID0 <15> VRAM_ID1 <15> VRAM_ID2 <15>

00

M93-S3 PARK-S3

NA

10K

0/short 680

NA2.2K

2.2nF 68pF

+VGA_CORE

12

R653

2.2K_0402_5%

R3

M93@

DRAM_RST# <19>

1

C942

C942 68P_0402_50V8J

68P_0402_50V8J PARK@

PARK@

C1

2

Compal Electronics, Inc.

C

401814

of

16 43Friday, January 08, 2010

1

C

5

+1.8VS_VGA

L150

VGA@

12

VGA@

1

C957

2

BLM15BD121SN1D_0402

D D

+1.1/1.0VS_VGA

C C

BLM15BD121SN1D_0402

L153

BLM15BD121SN1D_0402

VGA@

1U_0402_6.3V4Z

VGA@

VGA@ 1

C946

2

C958

VGA@

1

2

0.2A

VGA@

1

C950

2

10U_0603_6.3V6M

+DPF_VDD10

0.1U_0402_10V6K

1U_0402_6.3V4Z

VGA@

1

C959

2

VGA@

0.1U_0402_10V6K

1

C947

2

10U_0603_6.3V6M

4

0.11A

0.17A

+DPE_VDD18

+DPF_VDD10

AG15 AG16

AG20 AG21

AG14 AH14 AM14 AM16 AM18

AF16

AG17

AF22

AG22

AF23 AG23 AM20 AM22 AM24

U5G

DPE_VDD18#1 DPE_VDD18#2

DPE_VDD10#1 DPE_VDD10#2

DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5

DPF_VDD18#1 DPF_VDD18#2

DPF_VDD10#1 DPF_VDD10#2

DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5

3

DP A/B POWERDP E/F POWER

DPA_VDD18#1 DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPB_VDD18#1 DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

130mA

AE11 AF11

AF6 AF7

AE1 AE3 AG1 AG6 AH5

130mA

AE13 AF13

AF8 AF9

AF10 AG9 AH8 AM6 AM8

+DPA_VDD18

+DPA_VDD10+DPA_VDD10

+DPB_VDD18

+VPB_VDD10

0.2A

VGA@

1

C960

2

1

C951

2

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

1

C961

2

0.2A

VGA@

1

C952

2

0.2A

VGA@

1U_0402_6.3V4Z

1

C953

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

1

C962

2

0.1U_0402_10V6K

+1.8VS_VGA

L151

BLM15BD121SN1D_0402

VGA@

+1.8VS_VGA

L154

VGA@

12

BLM15BD121SN1D_0402

L149

BLM15BD121SN1D_0402

PARK@

+1.1/1.0VS_VGA

12

L152

BLM15BD121SN1D_0402

PARK@

+1.1/1.0VS_VGA

1

1U_0402_6.3V4Z

PARK@

0.1U_0402_10V6K

0.1U_0402_10V6K 1 C945

C945

2

PARK@

0.1U_0402_10V6K

0.1U_0402_10V6K 1 C956

C956

2

+DPA_VDD18

+DPB_VDD18

12

PARK@

1

C948

C949

2

10U_0603_6.3V6M

12

PARK@

1

C954

C955

2

10U_0603_6.3V6M

+1.8VS_VGA

L155

BLM15BD121SN1D_0402

B B

A A

5

12

@

+DPE_PVDD

@

1

C963

2

1U_0402_6.3V4Z

@

@ 1

C964

2

0.1U_0402_10V6K

@

@ 1

C965

2

1 2

4

10U_0603_6.3V6M

R664

R664 VGA@

VGA@ 0_0402_5%

0_0402_5%

R662

12

AF17

150_0402_1%

VGA@

+DPE_PVDD+DPE_VDD18

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DPEF_CALR

AG18

DPE_PVDD

AF19

DPE_PVSS

AG19

DPF_PVDD

AF20

DPF_PVSS

M9X-S2/S3 + Park-S3

M9X-S2/S3 + Park-S3 VGA@

VGA@

DP PLL POWER

2008/10/06 2009/10/06

3

DPAB_CALR

DPA_PVDD

DPA_PVSS

DPB_PVDD

DPB_PVSS

AE10

AG8 AG7

AG10 AG11

Compal Secret Data

Deciphered Date

R663

VGA@ R663

VGA@

1 2

150_0402_1%

+DPA_PVDD

VGA@

1

C966

2

10U_0603_6.3V6M

+DPB_PVDD

VGA@

C967

1

2

0.02A

VGA@

1U_0402_6.3V4Z

VGA@

1

C969

2

BLM15BD121SN1D_0402

0.1U_0402_10V6K

1

C968

2

0.02A

VGA@

1 C971

C971

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

2

+1.8VS_VGA

L156

12

VGA@

L157

BLM15BD121SN1D_0402

0.1U_0402_10V6K

0.1U_0402_10V6K 1 C970

C970

2

12

VGA@

+VPB_VDD10 +DPA_VDD10

+DPB_VDD18 +DPA_VDD18

+DPA_PVDD

+DPB_PVDD

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

+1.8VS_VGA

0_0402_5%

401814

R666

R667

R668

R670

@R666

@

12

@R667

@

12

@R668

@

12

@R670

@

12

C

of

17 43Friday, January 08, 2010

1

5

+1.5VS_VGA

VGA@

C975

1

2

1U_0402_6.3V4Z

L159

C976

VGA@

1

2

2.2A

12

VGA@

C977

1

2

1U_0402_6.3V4Z

VGA@

C1000

1

2

10U_0603_6.3V6M

+3VS_VGA

VGA@

C978

1

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

0.136A

C995

1

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

C979

1

2

C996

1

2

C980

1

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

VGA@

+VDDC_CT

C1001

1

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

VGA@

C981

1

2

VGA@

C982

1

2

0.1U_0402_10V6K

10U_0603_6.3V6M

10U_0603_6.3V6M +1.5VS_VGA

C991

1

2

10U_0603_6.3V6M

VGA@

C983

C992

VGA@

1

2

0.1U_0402_10V6K

1

2

10U_0603_6.3V6M

VGA@

C984

C993

VGA@

1

2

0.1U_0402_10V6K

1

2

10U_0603_6.3V6M

VGA@

C973

C974

C972

1

2

1U_0402_6.3V4Z

D D

+1.8VS_VGA

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603 VGA@

VGA@

0.06A

C1004

VGA@

C C

+1.1/1.0VS_VGA

+VGA_CORE

B B

+1.8VS_VGA

A A

C1005

1

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

VGA@

L162

1 2

BLM15BD121SN1D_0402

L163

1 2

BLM15BD121SN1D_0402

M93@

L164

1 2

BLM15BD121SN1D_0402

L166

1 2

BLM15BD121SN1D_0402

C1006

VGA@

1

2

1U_0402_6.3V4Z

PARK@

5

C1007

1

2

VGA@

+1.8VS_VGA

1U_0402_6.3V4Z

+1.8VS_VGA

1 2

BLM15BD121SN1D_0402

VGA@

0.035A

C1040

C1041

1

2

10U_0603_6.3V6M

VGA@

PARK@

C1045

C1047

1

2

1U_0402_6.3V4Z

PARK@

C1050

C1051

1

2

1U_0402_6.3V4Z

L161

C1042

1

2

1U_0402_6.3V4Z

VGA@

+MPV18

0.1U_0402_10V6K

+SPV18

0.1U_0402_10V6K

+1.5VS_VGA

VGA@

C1033

0.1U_0402_10V6K

VGA@

C1019

1

2

10U_0603_6.3V6M

L160

VGA@

L160

VGA@

1 2

BLM15BD121SN1D_0402

1U_0402_6.3V4Z

VGA@

C1034

1

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

+VGA_CORE

VGA@

C1020

C1035

1

2

1

2

VGA@

C1021

1

2

1U_0402_6.3V4Z

0.04A

12

C1032

VGA@

0.1U_0402_10V6K

C1043

1

VGA@

2

+1.8VS_VGA

+PCIE_PVDD

+MPV18

+SPV18 +SPV10

4

C985

1

2

0.1U_0402_10V6K

C994

1

2

10U_0603_6.3V6M

+VDDC_CT

+VDDR

0.1U_0402_10V6K

+VDDRHA

75mA 50mA

C1044

1

VGA@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

L165

VGA@ L165

VGA@

1 2

BLM15BD121SN1D_0402

4

U5D

H13

VDDR1#1

H16

VDDR1#2

H19

VDDR1#3

J10

VDDR1#4

J23

VDDR1#5

J24

VDDR1#6

J9

VDDR1#7

K10

VDDR1#8

K23

VDDR1#9

K24

VDDR1#10

K9

VDDR1#11

L11

VDDR1#12

L12

VDDR1#13

L13

VDDR1#14

L20

VDDR1#15

L21

VDDR1#16

L22

VDDR1#17

AA20

VDD_CT#1

AA21

VDD_CT#2

AB20

VDD_CT#3

AB21

VDD_CT#4

M93-S3/M92-S2

AA17

VDDR3#1

AA18

VDDR3#2

AB17

VDDR3#3

AB18

VDDR3#4

V12

VDDR4#1 / VDDR5

Y12

VDDR4#2

U12

VDDR4#3 / VDDR5

AA11

NC#1 / VDDR4

Y11

DVCLK / VDDR4

V11

NC#3 / VDDR5

U11

TESTEN#2 / VDDR5

L17

VDDRHA

L16

VSSRHA

AM30

PCIE_PVDD

L8

MPV18

H7

SPV18

H8

SPV10

J7

SPVSS

M11

BBP#1

M12

BBP#2

M9X-S2/S3 + Park-S3

M9X-S2/S3 + Park-S3 VGA@

VGA@

C1048

MEM I/O

LEVEL

LEVEL TRANSLATION

TRANSLATION

MEM CLK

PLL

BACK BIAS

VGA@

C1049

1

2

1U_0402_6.3V4Z

I/O

VGA@

VGA@ 1

2

+VDDR

0.1U_0402_10V6K

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3

POWER

VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#20 VDDC#21 VDDC#22

VDDC#23 /BIF_VDDC

VDDC#19/BIF_VDDC

ISOLATED

ISOLATED CORE I/O

CORE I/O

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

+PCIE_GDDR

C986

1

2

1U_0402_6.3V4Z

VGA@

C1002

1

2

1U_0402_6.3V4Z

VGA@

C1008

1

2

1U_0402_6.3V4Z

C1022

1

2

10U_0603_6.3V6M

VGA@

3

0.5A

MCK2012221YZF 0805

C987

VGA@

1

2

C988

1

2

1U_0402_6.3V4Z

VGA@

C989

1

2

1U_0402_6.3V4Z

VGA@

1U_0402_6.3V4Z

C990

VGA@

1

2

10U_0603_6.3V6M

MCK2012221YZF 0805

2A

C1003

VGA@

C1009

C1023

VGA@

1

2

1U_0402_6.3V4Z

VGA@

VGA@ 1

2

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

C997

VGA@

C1010

C1024

VGA@

1

2

VGA@

VGA@ 1

2

1

2

C998

1

2

1U_0402_6.3V4Z

VGA@

C1011

1

2

1U_0402_6.3V4Z

C1025

1

2

10U_0603_6.3V6M

VGA@

C999

VGA@

C1012

C1026

VGA@

1

2

10U_0603_6.3V6M

VGA@

VGA@ 1

2

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

C1013

C1027

VGA@

VGA@ 1

2

VGA@

VGA@ 1

2

1U_0402_6.3V4Z

2A

C1036

1

2

1U_0402_6.3V4Z

VGA@

1

2

1U_0402_6.3V4Z

VGA@

1

2

1

2

1U_0402_6.3V4Z

VGA@

10U_0603_6.3V6M

C1039

C1037

C1038

C1036

11/24 update

VGA_PWR_EN<24,35,36,40>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8VS_VGA

L158

VGA@

L158

VGA@

1 2

+1.1/1.0VS_VGA

+VGA_CORE

VGA@

C1014

C1028

VGA@ 1

2

VGA@

VGA@ 1

2

VGA@

C1016

1

2

1U_0402_6.3V4Z

VGA@

C1030

1

2

1U_0402_6.3V4Z

+VGA_CORE

VGA@

1 3

D

Q23

0.1U_0402_10V6K

VGA@

C1017

1

2

1U_0402_6.3V4Z

+VGA_CORE

VGA@

C1031

1

2

1U_0402_6.3V4Z

S

G

2

1 2

C1046 0.1U_0402_10V6K

Compal Secret Data

VGA@

C1015

1

2

1U_0402_6.3V4Z

VGA@

C1029

1

2

1U_0402_6.3V4Z

SI2301BDS_SOT23

C1297

@

C1297

@

1 2

R674 100K_0402_5%

2008/10/06 2009/10/06

1

+

2

1U_0402_6.3V4Z

R673

1 2 0_0402_5%

0_0402_5% VGA@

VGA@

Deciphered Date

2

C1018

C1018 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M VGA@

VGA@

+3VS+3VS_VGA

1 2

13

D

2

G

S

2

R672

R672 100K_0402_5%

100K_0402_5% VGA@

VGA@

2N7002_SOT23

2N7002_SOT23 Q24

Q24

VGA@

VGA_PWR_EN#<35>

1

U5E

AA27

PCIE_VSS#1

AB24

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

M6

GND#56

N11

GND#57

N12

GND#58

N13

GND#59

N16

GND#60

N18

GND#61

N21

GND#62

P6

GND#63

P9

GND#64

R12

GND#65

R15

GND#66

R17

GND#67

R20

GND#68

T13

GND#69

T16

GND#70

T18

GND#71

T21

GND#72

T6

GND#73

U15

GND#74

U17

GND#75

U20

GND#76

U9

GND#77

V13

GND#78

V16

GND#79

V18

GND#80

Y10

GND#81

Y15

GND#82

Y17

GND#83

Y20

GND#84

M9X-S2/S3 + Park-S3

VGA@

GND#3 / EVDDQ#2

GND#6 / EVDDQ#3

GND

+3VS_VGA

1 2

13

D

2

G

S

Title

SCHEMATIC A5931.

Size Document Number Rev

C

Date: Sheet

A3

GND#1

A30

GND#2

AA13 AA16

GND#4

AB10

GND#5

AB15 AB6

GND#7

AC9

GND#8

AD6

GND#9

AD8

GND#10

AE7

GND#11

AG12

GND#12

AH10

GND#13

AH28

GND#14

B10

GND#15

B12

GND#16

B14

GND#17

B16

GND#18

B18

GND#19

B20

GND#20

B22

GND#21

B24

GND#22

B26

GND#23

B6

GND#24

B8

GND#25

C1

GND#26

C32

GND#27

E28

GND#28

F10

GND#29

F12

GND#30

F14

GND#31

F16

GND#32

F18

GND#33

F2

GND#34

F20

GND#35

F22

GND#36

F24

GND#37

F26

GND#38

F6

GND#39

F8

GND#40

G10

GND#41

G27

GND#42

G31

GND#43

G8

GND#44

H14

GND#45

H17

GND#46

H2

GND#47

H20

GND#48

H6

GND#49

J27

GND#50

J31

GND#51

K11

GND#52

K2

GND#53

K22

GND#54

K6

GND#55

T11

GND#85

R11

GND#86

A32

VSS_MECH#1

AM1

VSS_MECH#2

AM32

VSS_MECH#3

R860

R860 470_0603_5%

470_0603_5% VGA@

VGA@

2N7002_SOT23

2N7002_SOT23 Q34

Q34

VGA@

Compal Electronics, Inc.

401814

1

C

18 43Friday, January 08, 2010

C

of

5

MDA[0..63]<16>

M_MA[13..0]<16>

M_DQM[7..0]<16> M_DQS[7..0]<16> M_DQS#[7..0]<16>

D D

ZZZ1

Hynix

X76H@

U32

SAMSUNG VRAM

S@

U30

SAMSUNG VRAM

S@

C C

MDA[0..63] M_MA[13..0] M_DQM[7..0] M_DQS[7..0] M_DQS#[7..0]

ZZZ2

Samsung

X76S@

U22

SAMSUNG VRAM

S@

U31

SAMSUNG VRAM

S@

M_BA0<16> M_BA1<16> M_BA2<16>

M_CLK0<16> M_CLK#0<16> M_CKE0<16>

M_ODT0<16> M_CS#0<16> M_RAS#0<16> M_CAS#0<16> M_WE#0<16>

R675

R675 240_0402_1%

240_0402_1%

VGA@

U8

VREFC_A1

M9

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

M_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

H2 N4

P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8 M8

M3 N9 M4

J8 K8

K10

K2

L3

J4 K4

L4

F4 C8

E8 D4

G4 B8

T3

L9

J2

L2

J10 L10

A1

A11

T1

T11

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

NC NC NC NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

64MX16 H5TQ1G63BFR-12C FBGA

64MX16 H5TQ1G63BFR-12C FBGA H@

H@

VREFD_Q1

M_DQS2 M_DQS0

M_DQM2 M_DQM0

M_DQS#2 M_DQS#0

DRAM_RST#<16>

12

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

4

U9

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

M_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

M_DQS3 M_DQS1

M_DQM3 M_DQM1

M_DQS#3 M_DQS#1

DRAM_RST#

U9

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

64MX16 H5TQ1G63BFR-12C FBGA

64MX16 H5TQ1G63BFR-12C FBGA H@

H@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

+1.5VS_VGA

R676

R676 240_0402_1%

240_0402_1%

VGA@

VREFC_A2 VREFD_Q2

12

MDA16

E4

MDA19

F8

MDA22

F3

MDA18

F9 H4

MDA17

H9

MDA23

G3

MDA20

H8

MDA3

D8

MDA2

C4

MDA4

C9

MDA5

C3

MDA7

A8

MDA0

A3

MDA6

B9

MDA1

A4

+1.5VS_VGA

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2 B10 D2 D9 E3 E9 F10 G2 G10

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

MDA26 MDA28 MDA27 MDA31 MDA24 MDA30 MDA25 MDA29

MDA15 MDA10 MDA14 MDA11 MDA12

MDA8

MDA13

MDA9

+1.5VS_VGA

3

+1.5VS_VGA

M_CLK1<16> M_CLK#1<16> M_CKE1<16>

M_ODT1<16> M_CS#1<16> M_RAS#1<16> M_CAS#1<16> M_WE#1<16>

R677

R677 240_0402_1%

240_0402_1%

VGA@

2

U10

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

M_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8 M8

M3 N9 M4

J8

K8

K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

J2

L2

J10 L10

A1

A11

T1

T11

U10

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

NC NC NC NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

64MX16 H5TQ1G63BFR-12C FBGA

64MX16 H5TQ1G63BFR-12C FBGA H@

H@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2 B10 D2 D9 E3 E9 F10 G2 G10

MDA44 MDA45 MDA41 MDA43 MDA40 MDA47 MDA42 MDA46

MDA35 MDA37 MDA38 MDA32 MDA36 MDA33 MDA39 MDA34

+1.5VS_VGA

R678

R678 240_0402_1%

240_0402_1%

VGA@

VREFC_A4 VREFD_Q4

M_CLK1 M_CLK#1 M_CKE1

M_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M_DQS6 M_DQS7

M_DQM6 M_DQM7

M_DQS#6 M_DQS#7

12

VREFC_A3 VREFD_Q3

M_DQS5 M_DQS4

M_DQM5 M_DQM4

M_DQS#5 M_DQS#4

DRAM_RST# DRAM_RST#

12

M_MA0 M_MA1MDA21 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12

M_BA0 M_BA1 M_BA2

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8 M8

M3 N9 M4

J8

K8

K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

J2

L2

J10 L10

A1

A11

T1

T11

U11

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

NC NC NC NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

64MX16 H5TQ1G63BFR-12C FBGA

64MX16 H5TQ1G63BFR-12C FBGA H@

H@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2 B10 D2 D9 E3 E9 F10 G2 G10

MDA52 MDA50 MDA54 MDA49 MDA53 MDA51 MDA55 MDA48

MDA56 MDA58 MDA60 MDA61 MDA63 MDA62 MDA57 MDA59

1

+1.5VS_VGA

B B

12

R679

4.99K_0402_1%

4.99K_0402_1% VGA@

VGA@

VREFD_Q1

12

0.1U_0402_10V6K

R687

4.99K_0402_1%

4.99K_0402_1% VGA@

VGA@

M_CLK0

1 2

R695 56_0402_1%

VGA@

M_CLK#0

1 2

R697 56_0402_1%

VGA@

A A

VGA@

5

1

C1086

0.01U_0402_16V7K

0.01U_0402_16V7K VGA@

VGA@

2

1

C1052

VGA@

2

M_CLK1

R696 56_0402_1%

M_CLK#1

R698 56_0402_1%

4.99K_0402_1%

1 2

VGA@

1 2

VGA@

R680

R688

+1.5VS_VGA+1.5VS_VGA

12

+1.5VS_VGA

1

2

4

VREFC_A1

0.1U_0402_10V6K

1 C1053

C1053

VGA@

2

C1087

0.01U_0402_16V7K

0.01U_0402_16V7K VGA@

VGA@

4.99K_0402_1%

10U_0603_6.3V6M

1

C1060

2

10U_0603_6.3V6M

VGA@

C1061

R681

R689

VGA@

+1.5VS_VGA+1.5VS_VGA +1.5VS_VGA+1.5VS_VGA +1.5VS_VGA+1.5VS_VGA

12

VREFC_A2 VREFD_Q2 VREFD_Q3VREFC_A3 VREFC_A4 VREFD_Q4

12

VGA@

0.1U_0402_10V6K

1

C1054

2

10U_0603_6.3V6M

1

C1070

C1069

2

10U_0603_6.3V6M

VGA@

R682

4.99K_0402_1%

4.99K_0402_1% VGA@

VGA@

R690

4.99K_0402_1%

VGA@

10U_0603_6.3V6M

1

C1062

2

10U_0603_6.3V6M

VGA@

12

0.1U_0402_10V6K

1 C1055

C1055

VGA@

2

+1.5VS_VGA

1

C1071

2

VGA@

1U_0402_6.3V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

4.99K_0402_1%

4.99K_0402_1% VGA@

VGA@

4.99K_0402_1%

4.99K_0402_1% VGA@

VGA@

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

C1072

1

2

Issued Date

12

R683

12

R691

1U_0402_6.3V4Z

VGA@

C1063

1

2

1U_0402_6.3V4Z

12

R684

R684 VGA@

VGA@

4.99K_0402_1%

0.1U_0402_10V6K

R692

VGA@

4.99K_0402_1%

1U_0402_6.3V4Z

VGA@

C1075

C1076

1

2

1U_0402_6.3V4Z

12

1U_0402_6.3V4Z

VGA@

C1077

C1065

1

2

1U_0402_6.3V4Z

Compal Secret Data

1

C1057

VGA@

2

+1.5VS_VGA

VGA@

C1078

1

VGA@

2

1U_0402_6.3V4Z

Deciphered Date

2

0.1U_0402_10V6K

1

C1056

2

VGA@

1U_0402_6.3V4Z

VGA@

C1073

C1074

C1064

1

2

1U_0402_6.3V4Z

2008/10/06 2009/10/06

VGA@

4.99K_0402_1%

1U_0402_6.3V4Z

C1079

C1080

1

2

1U_0402_6.3V4Z

VGA@

12

R685

R685 VGA@

VGA@

4.99K_0402_1%

12

R693

1U_0402_6.3V4Z

VGA@

C1081

C1066

1

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

1

VGA@

C1058

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

C1083

C1082

1

2

1U_0402_6.3V4Z

4.99K_0402_1%

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

C1067

1

2

12

R686

VGA@

4.99K_0402_1%

0.1U_0402_10V6K

12

R694

VGA@

VGA@ 1

2

1U_0402_6.3V4Z

1

C1059

VGA@

2

1U_0402_6.3V4Z

VGA@

C1085

C1084

C1068

1

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

19 43Friday, January 08, 2010

C

of

5

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

D D

C1108

33P_0402_50V8J

C C

+VDDCLK_IO

L168

1 2

1

2

1

2

22U_0805_10V4Z

CLK_XTAL_OUT CLK_XTAL_IN

Y1

12

14.318MHZ_20PF_7A14300003

14.318MHZ_20PF_7A14300003 1

C1110

C1110 33P_0402_50V8J

33P_0402_50V8J

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

C1099

C1100

2

0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z

1

C1101

2

+3VS

22U_0805_10V4Z

+3VS_CLK

1 2

+3VS_CLK

1

C1102

2

0.1U_0402_16V4Z

L169

C1109 0.1U_0402_16V4ZC1109 0.1U_0402_16V4Z

+3VS_CLK

0.1U_0402_16V4Z

1

C1103

2

+3VS_CLKVDDA

1

C1106

2

+VDDCLK_IO

Routing the trace at least 10mil

FBMA-L11-160808-601LMT 0603

1 2

R705 8.2K_0402_5%R705 8.2K_0402_5%

WLAN

CLK_NB_14.318M<11>

B B

8.2K_0402_5%

A A

MINI1_CLKREQ#<29>

CLK_NB_14.318M

1.1V 158R/90.0RRS780

+3VS_CLK

R712

@

1 2

R716

1 2

R708 90.9_0402_1%R708 90.9_0402_1%

R713

8.2K_0402_5%

1 2

SEL_SATA 27M_SEL

SB710_CLK_14M<24>

1 2

R707 158_0402_1%R707 158_0402_1%

CLK_48M_SD<30>

CLK_48M_USB<25>

C1113 22P_0402_50V8J@C1113 22P_0402_50V8J@

R706 33_0402_5%R706 33_0402_5%

CLK_14.318M

12

R709 33_0402_5%R709 33_0402_5% R710 33_0402_5%R710 33_0402_5%

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

1

C1105

C1104

2

1

C1107

0.1U_0402_16V4Z

2

12

L170

1 2

12

C1112 0.1U_0402_16V4ZC1112 0.1U_0402_16V4Z

27M_SEL SEL_SATA

12

For EMI

CLK_48MHZ

12

CLK_48M

12

CLK_XTAL_IN CLK_XTAL_OUT

1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN 2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN

+3VS

FBMA-L11-201209-221LMA30T_0805

U12

ICS 9LPRS488

49 48

62 66

12 18 28 37 53

17 29 38 44 54 61 69

24 51 50 43 42

63 64 65

71 70

67 68

11 19 27 36 47 52 58 72 73

ICS 9LPRS488

VDDA GNDA

VDDREF GNDREF

VDDSRC_IO VDDSRC_IO VDDATIG_IO VDDSB_SRC_IO VDDCPU_IO

3

VDDDOT VDDSRC VDDATIG VDDSB_SRC VDDSATA VDDCPU VDDHTT VDD48

CLKREQ0 # CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

REF2/SEL_27 REF1/SEL_SATA REF0/SEL_HTT66

48MHz_0 48MHz_1

X1 X2

6

GNDDOT GNDSRC GNDSRC GNDATIG GNDSB_SRC GNDSATA GNDCPU GNDHTT GND48 GNDPAD

SLG8SP626VTR_QFN72_10x10

+3VS_CLK

L167

1 2

SMBCLK SMBDAT

SB_SRC_SLOW#

CPUKG0T_LPRS

CPUKG0C_LPRS

HTT0T_LPRS / 66 M HTT0C_LPRS / 66 M

SB_SRC0T_LPRS SB_SRC0C_LPRS

SB_SRC1T_LPRS SB_SRC1C_LPRS

ATIG0T_LPRS ATIG0C_LPRS

ATIG1T_LPRS ATIG1C_LPRS

ATIG2T_LPRS ATIG2C_LPRS

SRC0T_LPRS SRC0C_LPRS

SRC1T_LPRS SRC1C_LPRS

SRC2T_LPRS SRC2C_LPRS

SRC3T_LPRS SRC3C_LPRS

SRC4T_LPRS SRC4C_LPRS

SRC5T_LPRS SRC5C_LPRS

SRC6T/SATAT_LPRS

SRC6C/SATAC_LPRS

SRC7T_LPRS/27MHz_SS

SRC7C_LPRS/27MHz_NS

1

C1088

C1088 22U_0805_10V4Z

22U_0805_10V4Z

2

1 2

41

56 55

60 59

40 39

35 34

33 32

31 30

26 25

23 22

21 20

16 15

14 13

10 9

8 7

46 45

5 4

57

PD#

3

0.1U_0402_16V4Z

1

C1089

2

0.1U_0402_16V4Z

SRC_SLOW

CPUCLK_EXT_R CPUCLK#_EXT_R

CLK_SRC7T CLK_SRC7C

R715 8.2K_0402_5%R715 8.2K_0402_5%

1

2

0_0402_5%

R701

1 2

R703

1 2

0_0402_5%

R711 0_0402_5%@R711 0_0402_5%@

1 2

R714 0_0402_5%

1 2

12

1

C1090

2

0.1U_0402_16V4Z

SB_CK_SCLK <8,9,25>

SB_CK_SDAT <8,9,25>

VGA@

+3VS_CLK

C1091

261_0402_1%

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z 1

C1092

2

R700

@R700

@

2

0.1U_0402_16V4Z

1

C1093

2

0.1U_0402_16V4Z

CLK_NBHT <11> CLK_NBHT# <11>

CLK_NBGFX <11> CLK_NBGFX# <11>

CLK_PCIE_VGA <14> CLK_PCIE_VGA# <14>

CLK_PCIE_LAN <29> CLK_PCIE_LAN# <29>

CLK_PCIE_MINI1 <29> CLK_PCIE_MINI1# <29>

CLK_SBLINK_BCLK <11> CLK_SBLINK_BCLK# <11>

CLK_SBSRC_BCLK <24> CLK_SBSRC_BCLK# <24>

27M_SSC <15> 27M_NSSC <15>

NB GFX

0.1U_0402_16V4Z

1

C1094

2

0.1U_0402_16V4Z

CLK_CPU_BCLK <6> CLK_CPU_BCLK# <6>

1

C1095

2

0.1U_0402_16V4Z

CPU

VGA

GLAN

WLAN

NB A LINK

SB RCLK

NB CLOCK INPUT TABLE

NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF 100M DIFF

VGA (Spread spectrum) VGA (Non spread spectrum)

1

2

C1096

1

C1097

2

0.1U_0402_16V4Z

1

C1098

C1098 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1U CLOSE PIN 69

+3VS_CLK

12

R699

8.2K_0402_5%

SRC_SLOW

12

R702

@

8.2K_0402_5%

RS740 RX780 RS780

66M SE(SINGLE END)

NC

14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V) NC NC vref

100M DIFF NC 100M DIFF

100M DIFF 100M DIFF

100M DIFF(IN/OUT)*

NC

SEL_HTT66

SEL_SATA

* default

1

single-ended 66MHz HTT output

*0

differential 100MHz HTT output

1*

NON SPREAD 100M SATA SRC6 output SPREAD 100M SATA SRC6 output

0

5

27M_SEL

NON SPREAD 27M and SPREAD 27M output1*

differential spread SRC_7 output

0

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

of

20 43Friday, January 08, 2010

C

5

4

3

2

1

+3VS

R652

R651

4.7K_0402_5%

4.7K_0402_5% VGA@

D D

UMA_ENBKL<11>

UMA_ENBKL

ENBKL_R<15>

VGA@

1 2

61

Q37A

VGA@

2N7002DW-T/R7_SOT363-6

2

3

VGA@

Q37B

2N7002DW-T/R7_SOT363-6

5

4

R652

4.7K_0402_5%

VGA@

1 2 3

VGA@

Q36B

2N7002DW-T/R7_SOT363-6

5

4

ENBKL <11,29>

UMA_ENVDD<11>

UMA_ENVDD

ENVDD_R<14>

2

4.7K_0402_5%

4.7K_0402_5% VGA@

VGA@

61

Q35A

VGA@

2N7002DW-T/R7_SOT363-6

R597

5

+3VS

R591

4.7K_0402_5%

VGA@

1 2

3

VGA@

Q35B

2N7002DW-T/R7_SOT363-6

4

VGA@

1 2 61

Q36A

VGA@

2N7002DW-T/R7_SOT363-6

2

ENVDD <11,29>

LID Switch

C C

+3VALW

C1114

0.1U_0402_16V4Z

B B

C1116

C1116 1U_0603_10V4Z

1U_0603_10V4Z VGA@

VGA@

TXOUT_L0-<29> TXOUT_L0+<29> TXOUT_L1-<29> TXOUT_L1+<29> TXOUT_L2-<29> TXOUT_L2+<29> TXCLK_L-<29> TXCLK_L+<29>

A A

5

TXOUT_L0TXOUT_L0+ TXOUT_L1TXOUT_L1+ TXOUT_L2TXOUT_L2+ TXCLK_LTXCLK_L+

DP_SELECT<11,23>

DP_SELECT

2

VDD

1

OUTPUT

GND

2

U13

1

APX9132ATI-TRL SOT-23 3P

+3VS

1

2

R717

47K_0402_5%

1 2

3

1

C1115

2

10P_0402_50V8J

U14

4

VCC

10

VCC

18

VCC

27

VCC

38

VCC

50

VCC

56

VCC

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

A8

20

A9

17

SEL

1

GND

6

GND

9

GND

13

GND

16

GND

21

GND

24

GND

28

GND

33

GND

39

GND

44

GND

49

GND

53

GND

55

GND

Thermal_GND

TS3DV520ERHUR_WQFN56_11X5

TS3DV520ERHUR_WQFN56_11X5 VGA@

VGA@

LID_SW# <29>

11/26 update

DDC2_CLK<11,29> DDC2_DATA<11,29>

TXOUT_L0+<29> TXOUT_L0-<29>

TXOUT_L1+<29> TXOUT_L1-<29> GMCH_TXOUT1- <11>

TXOUT_L2+<29> TXOUT_L2-<29>

TXCLK_L+<29> TXCLK_L-<29>

GM LVDS

VGA LVDS

VGA_TXOUT0VGA_TXOUT0+

GMCH_TXOUT0GMCH_TXOUT0+ GMCH_TXOUT1GMCH_TXOUT1+ GMCH_TXOUT2GMCH_TXOUT2+ GMCH_TXCLKGMCH_TXCLK+

VGA_TXOUT1VGA_TXOUT1+ VGA_TXOUT2VGA_TXOUT2+ VGA_TXCLKVGA_TXCLK+

GMCH_TXOUT0- <11> GMCH_TXOUT0+ <11> GMCH_TXOUT1- <11> GMCH_TXOUT1+ <11> GMCH_TXOUT2- <11> GMCH_TXOUT2+ <11> GMCH_TXCLK- <11> GMCH_TXCLK+ <11>

VGA_TXOUT0- <14> VGA_TXOUT0+ <14> VGA_TXOUT1- <14> VGA_TXOUT1+ <14> VGA_TXOUT2- <14> VGA_TXOUT2+ <14> VGA_TXCLK- <14> VGA_TXCLK+ <14>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDC2_DATA<11,29>

DDC2_CLK<11,29>

2008/10/06 2009/10/06

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

4

TXOUT_L0+ GMCH_TXOUT0+ TXOUT_L0-

TXOUT_L1+ TXOUT_L1-

TXOUT_L2+ TXOUT_L2-

TXCLK_L+ GMCH_TXCLK+ TXCLK_L-

MXM_RST#<14>

DDC2_DATA

MXM_RST#

DDC2_CLK

Compal Secret Data

Deciphered Date

1 4 2 3

RP18 0_0404_4P2R_5%UMA@RP18 0_0404_4P2R_5%UMA@

1 4 2 3

RP19 0_0404_4P2R_5%UMA@RP19 0_0404_4P2R_5%UMA@

1 4 2 3

RP20 0_0404_4P2R_5%UMA@RP20 0_0404_4P2R_5%UMA@

1 4 2 3

RP21 0_0404_4P2R_5%UMA@RP21 0_0404_4P2R_5%UMA@

MXM_RST#

2

6 1

Q38A

Q38A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 VGA@

VGA@

5

3

4

Q38B

Q38B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 VGA@

VGA@

2

VGA_LCD_CLK <15>

DDC2_CLKDDC2_CLK DDC2_DATADDC2_DATA

GMCH_TXOUT0GMCH_TXOUT1+

GMCH_TXOUT1GMCH_TXOUT2+

GMCH_TXOUT2-

GMCH_TXCLK-

VGA_LCD_DATA <15>

Title

Size Document Number Rev

B

Date: Sheet

DDC2_CLK <11,29> DDC2_DATA <11,29>

GMCH_TXOUT0+ <11> GMCH_TXOUT0- <11>

GMCH_TXOUT1+ <11>

GMCH_TXOUT2+ <11> GMCH_TXOUT2- <11>

GMCH_TXCLK+ <11> GMCH_TXCLK- <11>

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

21 43Friday, January 08, 2010

5

4

3

2

1

DDC to HDMI CONN

R720

D D

C C

PCIE_MTX_GRX_N3<10> PCIE_MTX_GRX_P3<10>

PCIE_MTX_GRX_N2<10>

PCIE_MTX_GRX_P2<10>

PCIE_MTX_GRX_N1<10> PCIE_MTX_GRX_P1<10>

B B

PCIE_MTX_GRX_N0<10> PCIE_MTX_GRX_P0<10>

GMCH_HDMI_CLK<11>

VGA_HDMI_SCLK<15,29>

GMCH_HDMI_DATA<11>

VGA_HDMI_SDATA<15,29>

C1119 0.1U_0402_16V7K

C1119 0.1U_0402_16V7K C1120 0.1U_0402_16V7K

C1120 0.1U_0402_16V7K

C1123 0.1U_0402_16V7K

C1123 0.1U_0402_16V7K C1124 0.1U_0402_16V7K

C1124 0.1U_0402_16V7K

C1127 0.1U_0402_16V7K

C1127 0.1U_0402_16V7K C1128 0.1U_0402_16V7K

C1128 0.1U_0402_16V7K

C1131 0.1U_0402_16V7K

C1131 0.1U_0402_16V7K C1132 0.1U_0402_16V7K

C1132 0.1U_0402_16V7K

1 2

R722 0_0402_5%

1 2

UMA@

1 2 1 2

UMA@

1 2 1 2

UMA@

1 2 1 2

UMA@

1 2 1 2

UMA@

UMA@ R725 0_0402_5%

R725 0_0402_5%

12

4.7K_0402_5%

VGA@

HDMI_CLK-_VGA<15> HDMI_CLK+_VGA<15>

HDMI_TX0-_VGA<15>

HDMI_TX0+_VGA<15>

HDMI_TX1-_VGA<15> HDMI_TX1+_VGA<15>

HDMI_TX2-_VGA<15> HDMI_TX2+_VGA<15>

R723

R723 12

VGA@

R724

R724 12

4.7K_0402_5%

4.7K_0402_5% UMA@

UMA@

+3VS+3VS_VGA

R721

12

4.7K_0402_5%

VGA_HDMI_SCLK

UMA@

VGA_HDMI_SDATA

VGA_HDMI_SCLK <15,29>

VGA_HDMI_SDATA <15,29>

VGA@

1 2

R726 0_0402_5%

1 2

R727 0_0402_5%

VGA@

1 2

R728 0_0402_5%

1 2

R729 0_0402_5%

VGA@

1 2

R730 0_0402_5%

1 2

R731 0_0402_5%

VGA@

1 2

R732 0_0402_5%

1 2

R733 0_0402_5%

VGA@

TXCDTXCD+

TX0DTX0D+

TX1DTX1D+

TX2DTX2D+

TXCD- <29> TXCD+ <29>

TX0D- <29> TX0D+ <29>

TX1D- <29> TX1D+ <29>

TX2D- <29> TX2D+ <29>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

22 43Friday, January 08, 2010

A

B

C

D

E

CRT CONNECTOR

+3VS

U15

1 1

UMA@

GMCH_CRT_R<11>

GMCH_CRT_G<11>

GMCH_CRT_B<11>

GMCH_CRT_HSYNC<11,13>

GMCH_CRT_VSYNC<11,13>

2 2

12

R734 0_0402_5%

UMA@

12

R735 0_0402_5%

UMA@

12

R736 0_0402_5%

UMA@

12

R737 0_0402_5%

UMA@

12

R738 0_0402_5%

D_RED

D_GREEN

D_BLUE

D_RED <29>

D_GREEN <29>

D_BLUE <29>

CRT_HSYNC <29>

CRT_VSYNC <29>

CRT_DDC_DATA<11,29>

CRT_DDC_CLK<11,29>

CRT_DDC_DATA

CRT_DDC_CLK

D_RED<29>

D_GREEN<29>

D_BLUE<29> CRT_HSYNC<29> CRT_VSYNC<29>

DP_SELECT<11,21>

+3VS_VGA

6 1

Q13A

Q13A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 VGA@

VGA@

+3VS_VGA

3

Q13B

Q13B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 VGA@

VGA@

D_RED

D_GREEN

D_BLUE

2

5

4

U15

1

A0

2

A1

5

A2

6

A3

7

A4

8

SEL1

9

A5

10

A6

30

SEL2

3

GND

11

GND

28

GND

31

GND

33

GPAD

PI3V712-AZLEX_TQFN32_6X3

VGA@

VGA_CRT_DATA <15>

VGA_CRT_CLK <15>

VDD VDD VDD VDD VDD

4 16 23 29 32

27

0B1

25

1B1

22

2B1

20

3B1

18

4B1

12

5B1

14

6B1

26

0B2

24

1B2

21

2B2

19

3B2

17

4B2

13

5B2

15

6B2

+3VS_VGA

R739

10K_0402_5%

VGA@

12

1

C1133

0.1U_0402_16V4Z

0.1U_0402_16V4Z VGA@

VGA@

2

GMCH_CRT_R <11> GMCH_CRT_G <11>

GMCH_CRT_B <11> GMCH_CRT_HSYNC <11,13> GMCH_CRT_VSYNC <11,13>

VGA_CRT_R <15> VGA_CRT_G <15>

VGA_CRT_B <15>

VGA_CRT_HSYNC <15>

VGA_CRT_VSYNC <15>

12

R740

R740 10K_0402_5%

10K_0402_5% VGA@

VGA@

VGA_CRT_DATA <15>

VGA_CRT_CLK <15>

3 3

4 4

+5VS

+5VALW

+3VALW

1 2

R747 330_0402_5%R747 330_0402_5%

A

1 2

R741 1K_0402_5%R741 1K_0402_5%

1 2

R744 1K_0402_5%R744 1K_0402_5%

1 2

R745 1K_0402_5%R745 1K_0402_5%

1 2

R746 1K_0402_5%R746 1K_0402_5%

LED1

2 1

S LED HT-F196BP5 0603 WHITE

LED2

2 1

S LED HT-F196BP5 0603 WHITE

LED3

2 1

S LED HT-F196BP5 0603 WHITE

LED4

2 1

S LED HT-F196BP5 0603 WHITE

LED5

2 1

S LED HT-191UD5 0603 AMBER

S LED HT-191UD5 0603 AMBER SC500007700

SC500007700

TP_LOCK_LED#

WLAN_LED#

PWR_LED#

CHARGE_LED0#

CHARGE_LED1#

B

TP_LOCK_LED# <29>

WLAN_LED# <29>

PWR_LED# <29>

CHARGE_LED0# <29>

CHARGE_LED1# <29>

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

CRT_DDC_DATA<11,29>

CRT_DDC_CLK<11,29>

Compal Secret Data

2008/10/06 2009/10/06

C

Compal Secret Data

11/26 update

Deciphered Date

CRT_DDC_DATA

CRT_DDC_CLK

D

CRT_DDC_DATA <11,29>

CRT_DDC_CLK <11,29>

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

23 43Friday, January 08, 2010

C

A

1 1

PCIE_CALRP=W/S=4/8(55ohm impedance), <1" PCIE_CALRN=W/S=4/8(55ohm impedance), <1"

+3VALW

C1144

12

0.1U_0402_16V4Z

R750

8.2K_0402_5%

8.2K_0402_5% @

@

1 2

0.1U_0402_16V4Z

A_RST#

2 2

3 3

2

B

1

A

5

U17

NC7SZ08P5X_NL_SC70-5

P

PLT_RST#

4

Y

G

3

12

R751

R751 100K_0402_5%

100K_0402_5%

SB_RX0P<10> SB_RX0N<10> SB_RX1P<10> SB_RX1N<10> SB_RX2P<10> SB_RX2N<10> SB_RX3P<10> SB_RX3N<10>

SB_TX0P<10> SB_TX0N<10> SB_TX1P<10> SB_TX1N<10> SB_TX2P<10> SB_TX2N<10> SB_TX3P<10> SB_TX3N<10>

+PCIE_VDDR

+1.2V_HT

1 2

MBC1608121YZF_0603

PLT_RST# <11,13,14,29>

C1145 100P_0402_25V8K@C1145 100P_0402_25V8K@

SB710_CLK_14M<20>

2.2U_0603_6.3V4Z

Close to SB

R754 20M_0402_5%@R754 20M_0402_5%@

1 2

C1146

1 2

12

12P_0402_50V8J

12P_0402_50V8J R756

R756

20M_0603_5%

C1147

1 2

12P_0402_50V8J

4 4

A

Y2

4

OUT

NC

1

IN

NC

32.768KHZ_12.5P_MC-306

SB_32KHI

3 2

SB_32KHO

B

C1134 0.1U_0402_16V7KC1134 0.1U_0402_16V7K

1 2

C1135 0.1U_0402_16V7KC1135 0.1U_0402_16V7K

1 2

C1136 0.1U_0402_16V7KC1136 0.1U_0402_16V7K

1 2

C1137 0.1U_0402_16V7KC1137 0.1U_0402_16V7K

1 2

C1138 0.1U_0402_16V7KC1138 0.1U_0402_16V7K

1 2

C1139 0.1U_0402_16V7KC1139 0.1U_0402_16V7K

1 2

C1140 0.1U_0402_16V7KC1140 0.1U_0402_16V7K

1 2

C1141 0.1U_0402_16V7KC1141 0.1U_0402_16V7K

1 2

R749 562_0402_1%R749 562_0402_1% R748 2.05K_0402_1%R748 2.05K_0402_1%

L171

PCIE_PVDD=43mA

C1142

CLK_SBSRC_BCLK<20> CLK_SBSRC_BCLK#<20>

12

R753 100_0402_5%

ALLOW_LDTSTOP<11>

H_PROCHOT_R#<6,29>

H_PWRGD<6>

LDT_STOP#<6,11>

LDT_RST#<6>

B

A_RST#

1

C1143

1U_0402_6.3V4Z

2

@

12

C

U16A

SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C

12 12

+SB_PCIEVDD

SB_32KHI

SB_32KHO

H_PROCHOT_R#

U16A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

218S7EALA11FG_BGA528_SB700

SB700

Part 1 of 5

PCI EXPRESS INTERFACE

LPC

RTC XTAL

CPU

RTC

PCICLK5/GPIO41

PCI CLKS

PCI INTERFACE

CLOCK GENERATOR

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

SA00001S570 S IC 218S7EBLA12FG SB700 BGA 528P SB 0FA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

P4

PCICLK0

P3

PCICLK1

P1

PCICLK2

P2

PCICLK3

T4

PCICLK4

T3

TP14TP14

N1

PCIRST#

U2

AD0

P7

AD1

V4

AD2

T1

AD3

V3

AD4

U1

AD5

V1

AD6

V2

AD7

T2

AD8

W1

AD9

T9

AD10

R6

AD11

R7

AD12

R5

AD13

U8

AD14

U5

AD15

Y7

AD16

W8

AD17

V9

AD18

Y8

AD19

AA8

AD20

Y4

AD21

Y3

AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30

AD31 CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR STOP# PERR# SERR# REQ0# REQ1# REQ2#

REQ3#/GPIO70 REQ4#/GPIO71

GNT0# GNT1#

GNT2# GNT3#/GPIO72 GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33 INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

VBAT

2008/10/06 2009/10/06

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5

VGA_PWR_EN_A

AC6 AE5 AD6 V5

AD3 AC4

PX_EN

AE2 AE3

G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15

C3 C2

R757 1M_0402_5%

B2

C1148

1

2

0.1U_0402_16V4Z

Compal Secret Data

MXM_PWR_EN<25>

R755 22_0402_5%R755 22_0402_5%

@

1 2

C1149

1

2

1U_0402_6.3V4Z

Deciphered Date

PCI_AD23 <28> PCI_AD24 <28> PCI_AD25 <28> PCI_AD26 <28> PCI_AD27 <28> PCI_AD28 <28>

VGA_PWR_EN_A

NC7SZ08P5X_NL_SC70-5

PX_EN <11> DGPU_HOLD_RST# <14>

1 2

LPC_AD0 <29> LPC_AD1 <29> LPC_AD2 <29> LPC_AD3 <29> LPC_FRAME# <29>

SERIRQ <29>

RTC_CLK <28>

+RTCBATT

1 2

R758 510_0402_5%R758 510_0402_5%

W=20mils

D

U28

2 1

VGA@

CLK_PCI_EC

+RTCBATT

+3VS

5

P

B

VGA_PWR_EN

4

Y

A

G

3

STRAP PIN

E

PCI_CLK2 <28> PCI_CLK3 <28> PCI_CLK4 <28> PCI_CLK5 <28>

+3VS

R752

8.2K_0402_5%

8.2K_0402_5% @

@

VGA_PWR_EN

VGA_PWR_EN <18,35,36,40>

CLK_PCI_EC <28,29>

LPCCLK1 <28>

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

STRAP PIN

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

24 43Friday, January 08, 2010

C

A

1 1

EC_RSMRST#

SB_CK_SCLK SB_CK_SDAT

PCIE_WAKE#

EC_LID_OUT# USB_OC#0 USB_OC#1

USB_OC#3

R770 33_0402_5%R770 33_0402_5% R771 33_0402_5%R771 33_0402_5%

HDA_SYNC_AUDIO<32>

HDA_RST_AUDIO#<32>

HDA_RST#<28>

SUS_STAT#

1 2 1 2

R772 33_0402_5%R772 33_0402_5%

R773 33_0402_5%R773 33_0402_5%

PCIE_WAKE#<29>

H_THERMTRIP#<6>

NB_PWRGD<11>

SB_SPKR=W/S=4/4(55ohm impedance)

HDA_BITCLK HDA_SDOUT

1 2

+3VS

2 2

3 3

1 2

R762 4.7K_0402_5%R762 4.7K_0402_5%

1 2

R763 2.2K_0402_5%R763 2.2K_0402_5%

+3VS

R764 2.2K_0402_5%R764 2.2K_0402_5%

1 2

R765 2.2K_0402_5%R765 2.2K_0402_5%

1 2

+3VALW

1 2

R766 10K_0402_5%R766 10K_0402_5%

@

1 2

R767 100K_0402_5%

1 2

R768 100K_0402_5%R768 100K_0402_5%

1 2

R769 100K_0402_5%R769 100K_0402_5%

HDA_BITCLK_AUDIO<32> HDA_SDOUT_AUDIO<32>

HDA_SDIN0<32>

STRAP PIN

B

demo circuit LID use RI#

PM_SLP_S3#<29> PM_SLP_S5#<29> PBTN_OUT#<29> SB_PWRGD<6,11,29> SUS_STAT#<11>

GATEA20<29> KB_RST#<29> EC_SCI#<29> EC_SMI#<29>

EC_RSMRST#<29>

SB700 has internal PD

MXM_PWR_EN<24>

SB_SPKR<32> SB_CK_SCLK<8,9,20> SB_CK_SDAT<8,9,20>

EC_LID_OUT#<29>

USB_OC#3<29> USB_OC#1<29>

USB_OC#0<31>

HDA_SDIN0

SUS_STAT#

TP7TP7 TP8TP8 TP6TP6

H_THERMTRIP# NB_PWRGD

EC_RSMRST#

SB_CK_SCLK SB_CK_SDAT

EC_LID_OUT# USB_OC#3

USB_OC#1 USB_OC#0

HDA_SYNC

HDA_RST#

U16D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700

C

SB700

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

INTEGRATED uC

Part 4 of 5

USB_RCOMP

USB_FSD13P

USB MISC

USB_FSD13N USB_FSD12P

USB_FSD12N

USB 1.1

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N

USB_HSD3P

USB_HSD3N

GPIO

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

IMC_GPIO8 IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11 SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17

IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25

IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41

D

@

1 2

R760 100_0402_5%

C8

USB_RCOMP

G8

E6 E7

F7 E8

H11 J10

E11 F11

A11 B11

USB20_P8

C10

USB20_N8

D10

USB20_P7

G11

USB20_N7

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5

D12

USB20_P4

B12

USB20_N4

A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14 A18

B18 F21 D21 F19 E20 E21 E19 D19 E18

G20 G21 D25 D24 C25 C24 B25 C23

B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

R760 100_0402_5%

1 2

R76111.8K_0402_1% R76111.8K_0402_1%

USB20_P8 <29> USB20_N8 <29>

USB20_P7 <29> USB20_N7 <29>

USB20_P6 <29> USB20_N6 <29>

USB20_P5 <29> USB20_N5 <29>

USB20_P4 <29> USB20_N4 <29>

USB20_P3 <29> USB20_N3 <29>

USB20_P2 <30> USB20_N2 <30>

USB20_P1 <29> USB20_N1 <29>

USB20_P0 <31> USB20_N0 <31>

GPIO16 <28> GPIO17 <28>

STRAP PIN STRAP PIN

@

C1150 100P_0402_25V8K

1 2

CLK_48M_USB <20>

USB-8 Bluetooth USB-7 USB Camera USB-6 Finger Print USB-5 MiniCard(WLAN) USB-4 MiniCard(WWAN) USB-3 Ext USB USB-2 USB Card reader USB-1 Ext USB USB-0 Ext USB

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

25 43Friday, January 08, 2010

A

1 1

SATA_STX_C_DRX_P0<29> SATA_STX_C_DRX_N0<29>

HDD

SATA_DTX_C_SRX_N0<29> SATA_DTX_C_SRX_P0<29>

SATA_STX_C_DRX_P1<29> SATA_STX_C_DRX_N1<29>

SSD

SATA_DTX_C_SRX_N1<29> SATA_DTX_C_SRX_P1<29>

25MHZ_20PF_7A25000012

2 2

27P_0402_50V8J

3 3

25MHZ_20PF_7A25000012

C1151

12

Y3

C1152

12

+1.2V_HT

FBMA-L11-160808-221LMT_0603

+3VS

FBMA-L11-160808-221LMT_0603

12

R774

R774 10M_0402_5%

10M_0402_5%

L172

L173

SATA_X1

SATA_X2

12

PLLVDD_SATA=93mA

XTLVDD_SATA=6mA

12

SATA_CAL=W/S=9/20(35ohm impedance), <1"

R775 1K_0402_1%R775 1K_0402_1%

R776 10K_0402_5%R776 10K_0402_5%

1 2

+3VS

SATA_LED#<29>

+PLLVDD_SATA

1

C1153

2.2U_0603_6.3V4Z

1U_0402_6.3V4Z

C1155

2

+XTLVDD_SATA

2

1

B

12

1

C1154

0.1U_0402_16V4Z

2

1

C1156

0.1U_0402_16V4Z

2

C

U16B

SB700

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_CALSATA_CAL SB_SPI_CS1#

SATA_X1 SATA_X2

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48 FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

IDE_IORDY

IDE_IRQ

IDE_A0 IDE_A1 IDE_A2

IDE_DACK#

IDE_DRQ IDE_IOR#

IDE_IOW#

IDE_CS1# IDE_CS3#

VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

AVDD AVSS

AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24

AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

G6 D2 D1 F4 F3

U15 J1

M8 M5 M7

P5 P8 R8

C6 B6 A6 A5 B5

A4 B4 C4 D4 D5 D6 A7 B7

F6 G7

+3VALW

SB_SPI_DI

SB_SPI_DO SB_SPI_CLK SB_SPI_HOLD#

AVDD=5mA

11/27 Update for reserve Non Share ROM

1

C1298

@ C1298

@

0.1U_0402_16V4Z

2

SB_SPI_CS1# SB_SPI_CLK

EC_THERM# <29>

2 1

D3 RB751V_SOD323D3 RB751V_SOD323

R777 100K_0402_5%R777 100K_0402_5% R778 100K_0402_5%

R778 100K_0402_5%

12 12

@

D

FOR EC 256KB SPI ROM (150mil PACKAGE)

+3VALW +3VALW

SPI_CS# SPI_SO SB_SPI_HOLD#

+3VALW

20mils

R980

@ R980

@

SB_SPI_HOLD#

1 2

10K_0402_5%

10K_0402_5% R981 0_0402_5%@ R981 0_0402_5%@ L186 FBMA-10-100505-101T 0402@ L186 FBMA-10-100505-101T 0402@ R982 0_0402_5%@ R982 0_0402_5%@

1 2

+3VALW +3VS

SPI_CS#

SPI_CLK_R

12

SPI_SISB_SPI_DO SB_SPI_DISPI_SO

ACIN <15,29>

U48

1 2 3 4

8 3 7 1 6 5

VCC

CS#

HOLD#

DO

CLK

WP#

DIO

GND

MX25L2005CMI-12G SOP

MX25L2005CMI-12G SOP @

@

U49

VCC W HOLD S C D

MX25L1605AM2C-12G_SO8-200mil

MX25L1605AM2C-12G_SO8-200mil @

@

VSS

4

2

Q

8 7

SPI_CLK_R

6

SPI_SI

5

1 2

R983 0_0402_5%

E

SPI_CLK_R

@

R979

@

33_0402_5%

1

1 2

C1299

@ C1299

@

22P_0402_50V8J

2

Port Number

Port 0

Port 1

Port 2

Port 3

4 4

Port 4

Port 5

Pri/SEC,Mas/Slave assignment SATA drive controlled by

Primary master

Secondary master

Primary slave

Secondary slave

Primary (Secondary) master

Primary (Secondary) slave

A

SATA controler

PATA controler

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

26 43Friday, January 08, 2010

C

A

+3VS

1 1

2 2

3 3

C1158 22U_0805_6.3V6MC1158 22U_0805_6.3V6M

C1161 0.1U_0402_16V4ZC1161 0.1U_0402_16V4Z C1163 0.1U_0402_16V4ZC1163 0.1U_0402_16V4Z C1164 0.1U_0402_16V4ZC1164 0.1U_0402_16V4Z

+3VS

+1.2V_HT

FBMA-L11-201209-221LMA30T_0805

+3VALW

VDDQ=131mA

1 2

1 2 1 2 1 2

VDD33=71mA

PCIE_VDDR=0.6A

L174

1 2 1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2

L175

L177

12

FBMA-L11-201209-221LMA30T_0805

C1166 10U_0805_10V4ZC1166 10U_0805_10V4Z C1167 1U_0402_6.3V4ZC1167 1U_0402_6.3V4Z

C1168 0.1U_0402_16V4ZC1168 0.1U_0402_16V4Z C1169 0.1U_0402_16V4ZC1169 0.1U_0402_16V4Z

AVDD_SATA=567mA

C1172 22U_0805_6.3V6MC1172 22U_0805_6.3V6M C1173 1U_0402_6.3V4ZC1173 1U_0402_6.3V4Z C1175 1U_0402_6.3V4ZC1175 1U_0402_6.3V4Z C1177 0.1U_0402_16V4ZC1177 0.1U_0402_16V4Z C1178 0.1U_0402_16V4ZC1178 0.1U_0402_16V4Z

AVDDTX/RX=658mA

FBMA-L11-201209-221LMA30T_0805

C1182 10U_0805_10V4ZC1182 10U_0805_10V4Z C1184 10U_0805_10V4ZC1184 10U_0805_10V4Z C1185 1U_0402_6.3V4ZC1185 1U_0402_6.3V4Z C1186 1U_0402_6.3V4ZC1186 1U_0402_6.3V4Z

C1187 0.1U_0402_16V4ZC1187 0.1U_0402_16V4Z

+PCIE_VDDR

+1.2V_SATA

+AVDD_USB

B

U16C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1 USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4

S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7

S5_1.2V_1 S5_1.2V_2

V5_VREF AVDDCK_3.3V AVDDCK_1.2V

AVDDC

VDD=0.51A

+1.2V_SB_CORE

L15 M12 M14 N13 P12 P14 R11 R15 T16

VDD=138mA

+1.2V_HT

L21 L22 L24 L25

+S5_3V

A17 A24 B17 J4 J5 L1 L2

+S5_1.2V

G2 G4

USB_PHY_1.2V=197mA

+1.2_USB A10 B10

+V5_VREF

AE7

+AVDDCK_3.3V

J16

+AVDDCK_1.2V

K17

+AVDDC

E9

AVDDC=17mA

C

1 2

R779 0_0805_5%R779 0_0805_5%

1 2

12 12 12 12

S5_3.3V=32mA

C11702.2U_0603_6.3V4Z C11702.2U_0603_6.3V4Z

1 2

C11712.2U_0603_6.3V4Z C11712.2U_0603_6.3V4Z

1 2

S5_1.2V=113mA

+1.2VALW

1 2

12

12 12

L176FBMA-L11-160808-221LMT 0603L176FBMA-L11-160808-221LMT 0603

C1179 10U_0805_10V4ZC1179 10U_0805_10V4Z C1180 0.1U_0402_16V4ZC1180 0.1U_0402_16V4Z

C1181 0.1U_0402_16V4ZC1181 0.1U_0402_16V4Z

V5_VREF=1mA

2

C1183

C1183 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

L178

12

FBMA-L11-160808-221LMT_0603

C115910U_0805_10V4Z C115910U_0805_10V4Z

C11601U_0402_6.3V4Z C11601U_0402_6.3V4Z C11651U_0402_6.3V4Z C11651U_0402_6.3V4Z C11570.1U_0402_16V4Z C11570.1U_0402_16V4Z C11620.1U_0402_16V4Z C11620.1U_0402_16V4Z

+3VALW

12 12

+1.2V_HT

C1174 1U_0402_6.3V4ZC1174 1U_0402_6.3V4Z C1176 1U_0402_6.3V4ZC1176 1U_0402_6.3V4Z

12

D4

21

CH751H-40PT_SOD323-2

+3VALW

C11882.2U_0603_6.3V4Z C11882.2U_0603_6.3V4Z C11890.1U_0402_16V4Z C11890.1U_0402_16V4Z

D

U16E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

+1.2VALW

12 12

R7801K_0402_5% R7801K_0402_5%

+5VS +3VS

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42

GROUND

VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50

PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21

AVSSCK

A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24

P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25

L17

E

AVDDCK_1.2V=62mA

+AVDDCK_1.2V

AVDDCK_3.3V=47mA

+AVDDCK_3.3V

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L179

L180

12

FBMA-L11-160808-221LMT_0603

2008/10/06 2009/10/06

+1.2V_HT

C11902.2U_0603_6.3V4Z C11902.2U_0603_6.3V4Z

12

C11910.1U_0402_16V4Z C11910.1U_0402_16V4Z

12

+3VS

C11922.2U_0603_6.3V4Z C11922.2U_0603_6.3V4Z

12

C11930.1U_0402_16V4Z C11930.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

of

27 43Friday, January 08, 2010

C

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK2

PULL

1 1

2 2

HIGH

PULL LOW

PCI_CLK2<24> PCI_CLK3<24> PCI_CLK4<24> PCI_CLK5<24>

CLK_PCI_EC<24,29>

LPCCLK1<24> RTC_CLK<24> HDA_RST#<25>

GPIO17<25> GPIO16<25>

BOOTFAIL TIMER ENABLED

BOOTFAIL TIMER DISABLED

DEFAULT

R781

@

R791

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

12

R782

10K_0402_5%

R782

@

12

R792

12

10K_0402_5%

12

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R783

@

R793

@

12

10K_0402_5%

12

10K_0402_5%

RESERVED

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0

R784

10K_0402_5%

@

R794

10K_0402_5%

@

12

CLK_PCI_EC

ENABLE PCI MEM BOOT

DISABLE PCI MEM BOOT

DEFAULT

12

R785

10K_0402_5%

@

12

R795

10K_0402_5%

CLKGEN ENABLED

CLKGEN DISABLED

DEFAULT

R786

10K_0402_5%

@

R796

10K_0402_5%

RTC_CLKLPC_CLK1

INTERNAL RTC

DEFAULT

EXT. RTC

(PD on X1, apply 32KHz to RTC_CLK)

12

R787

10K_0402_5%

@

R797

2.2K_0402_5%

@

12

AZ_RST_CD#

EC ENABLED

EC DISABLED

DEFAULT

12

R788

10K_0402_5%

@

12

R798

10K_0402_5%

GP17

Internal pull up H,H = Reserved

H,L = SPI ROM L,L = FWH ROM

L,H = LPC ROM (SB700) L,NC = LPC ROM (SB710)

12

R789

2.2K_0402_5%

@

12

R799

2.2K_0402_5%

GP16

R790

2.2K_0402_5%

@

R800

2.2K_0402_5%

11/27 Update for change to LPC

12

@

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

USE PCI PLL

DEFAULT

BYPASS PCI PLL

R802

@

USE ACPI BCLK

DEFAULT

BYPASS ACPI BCLK

12

R803

2.2K_0402_5%

2.2K_0402_5% @

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_AD28

PULL

3 3

PCI_AD28<24> PCI_AD27<24> PCI_AD26<24> PCI_AD25<24> PCI_AD24<24> PCI_AD23<24>

4 4

A

HIGH

PULL LOW

B

USE LONG RESET

DEFAULT

USE SHORT RESET

R801

@

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

USE IDE PLL

DEFAULT

BYPASS IDE PLL

R804

@

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

12

R805

2.2K_0402_5%

2.2K_0402_5% @

@

2008/10/06 2009/10/06

12

2.2K_0402_5%

PCI_AD23

RESERVED

12

R806

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

28 43Friday, January 08, 2010

A

+RTCBATT

GPIO

LAN

12/1 update

VGA_PWM<14>

EC_SMB_DA2<6,15>

EC_SMB_CK2<6,15>

LID_SW#<21>

TP_LOCK_LED#<23>

EC_SMI#<25> DPST_PWM<11> WLAN_LED#<23>

PWR_LED#<23>

CHARGE_LED0#<23> CHARGE_LED1#<23>

PCIE_ITX_C_PRX_P1<10> PCIE_ITX_C_PRX_N1<10>

PCIE_PTX_C_IRX_P1<10> PCIE_PTX_C_IRX_N1<10>

PCIE_PTX_C_IRX_N2<10> PCIE_PTX_C_IRX_P2<10>

PCIE_ITX_C_PRX_N2<10> PCIE_ITX_C_PRX_P2<10>

VLDT_EN<35,36>

VGATE<39>

EC_RSMRST#<25> EC_LID_OUT#<25>

SB_PWRGD<6,11,25>

SUSP<35>

SUSP#<37>

ACIN<15,26>

USB_OC#1<25>

PBTN_OUT#<25>

PM_SLP_S5#<25> PM_SLP_S3#<25>

EC_SCI#<25> PLT_RST#<11,13,14,24>

SYSON<35,38> LPC_AD0<24> LPC_AD1<24> LPC_AD2<24> LPC_AD3<24>

LPC_FRAME#<24>

SERIRQ<24> KB_RST#<25> GATEA20<25>

HDMI_DET<11,15> CLK_PCI_EC<24,28>

VGA_HDMI_SDATA<15,22> VGA_HDMI_SCLK<15,22>

TX2D+<22>

TX2D-<22>

TX1D+<22>

TX1D-<22>

TX0D+<22>

TX0D-<22>

TXCD+<22>

TXCD-<22>

MINI1_CLKREQ#<20>

PCIE_WAKE#<25>

CLK_PCIE_MINI1#<20> CLK_PCIE_MINI1<20>

CLK_PCIE_LAN#<20> CLK_PCIE_LAN<20>

SPKL+<32> SPKL-<32>

SPKR+<32> SPKR-<32>

1

2

C1195

2.2U_0603_6.3V4Z

1 1

WLAN

2 2

3 3

HDMI

WLAN_CLK

LAN_CLK

C1300

1 2

+RTCBATT

WLAN_LED#

CHARGE_LED0#

CHARGE_LED1#

B

1000P_0402_50V7K

TP_LOCK_LED#

PWR_LED#

SPKL+ SPKL-

SPKR+ SPKR-

+5VALW

MAINPWON<6,39> +3VALW

0.1U_0603_50V4Z~D

C

B+

JP1

1

B+

C1194

1

2

3

B+

5

B+

7

B+

9

B+

11

B+

13

B+

15

RESERVED

17

GND

19

GND

21

GND

23

MAINPWON

25

+RTCVCC

27

ICH_RTCRST#

29

GPIO1

31

EC_SMB_DA2

33

EC_SMB_CK2

35

GPIO6

37

GPIO48

39

EC_SMI#

41

L_BKLT_CTRL

43

PETP4

45

PETN4

47

GND

49

PERP4

51

PERN4

53

GND

55

PETP2

57

PETN2

59

GND

61

PERP2

63

PERN2

65

GND

67

PETN1

69

PETP1

71

GND

73

PERN1

75

PERP1

77

GND

79

SLP_S4#

81

VGATE

83

PM_RSMRST#

85

LID_SW#

87

GPIO24

89

PM_PWROK

91

EC_SWI#

93

SUSP#

95

AC_IN

97

USB_OC2#

99

USB_OC1#

101

USB_OC0#

103

ON/OFFBTN#

105

SLP_S5#

107

SLP_S3#

109

EC_SCI#

111

PLT_RST#

113

SYSON

115

LPC_AD0

117

LPC_AD1

119

LPC_AD2

121

LPC_AD3

123

LPC_FRAME#

125

SIRQ

127

KB_RST#

129

GATEA20

131

CLKREQG_WWAN#

133

RESERVED

135

HDMI_HPD#

137

CLK_PCI_EC

139

GND

141

HDMIDAT

143

HDMICLK

145

GND

147

TX2D+

149

TX2D-

151

GND

153

TX1D+

155

TX1D-

157

GND

159

TX0D+

161

TX0D-

163

GND

165

TXCD+

167

TXCD-

169

GND

171

CLKREQ_WLAN#

173

ICH_SMBDATA

175

ICH_SMBCLK

177

PCIE_WAKE#

179

PCI_PME#

181

CLK_48M_CR

183

CLKREQA#

185

CLK_PCIE_WAN#

187

CLK_PCIE_WAN

189

GND

191

CLK_PCIE_MCARD#

193

CLK_PCIE_MCARD

195

HDI_B_DET/GND

197

CLK_PCIE_LAN#

199

CLK_PCIE_LAN

D

+5VS

+5VALW +3VALW

+3VS +3VS +3VS

VR_ON

HDI_B_DET/GND

SB_SPKR

HDA_RST#

HDA_SDOUT

HDA_SYNC

HDA_BITCLK

HDA_SDIN0 HDA_SDIN1

DE_LED#

SATA0TXP

SATA0TXN

THERM_SCI#

GPIO42

SATA1TXP

SATA1TXN

1.5VS

SATA2TXP

SATA2TXN SATA2RXP

SATA2RXN SATA0RXP

SATA0RXN

USB20_P7 USB20_N7

SATA1RXP SATA1RXN

USB20_P5 USB20_N5

USB20_P4 USB20_N4

USB20_P3 USB20_N3

GPIO44

USB20_P8 USB20_N8

USB20_P6 USB20_N6

USB20_P1 USB20_N1

USB20_P2 USB20_N2

USB20_P0 USB20_N0

ENABLT

ENAVDD

L_DDC_DATA

L_DDC_CLK CRT_VSYNC CRT_HSYNC

CRT_DDC_DATA

CRT_DDC_CLK

CRT_RED

CRT_GREEN

CRT_BLUE

LCDSA_DATA_1

LCDSA_DATA#_1

LCDSA_DATA_0

LCDSA_DATA#_0

LCDSA_DATA_2

LCDSA_DATA#_2

LCDSA_CLK

LCDSA_CLK#

+VL

GND GND GND

GND

GND GND

GND

GND GND GND GND

GND

E

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

TP15TP15 TP16TP16

+1.5VS

+5VS +5VALW VL +3VALW +3VS

VR_ON <39>

EAPD <32> BEEP# <32> EC_MUTE# <32> INT_MIC_L <32> USB_ON# <31>

SATA_LED# <26>

SATA_STX_C_DRX_P0 <26> SATA_STX_C_DRX_N0 <26>

EC_THERM# <26>

USB_OC#3 <25>

11/26 update

SATA_STX_C_DRX_P1 <26> SATA_STX_C_DRX_N1 <26>

SATA_DTX_C_SRX_P1 <26> SATA_DTX_C_SRX_N1 <26>

SATA_DTX_C_SRX_P0 <26> SATA_DTX_C_SRX_N0 <26>

USB20_P7 <25> USB20_N7 <25>

USB20_P5 <25> USB20_N5 <25>

USB20_P4 <25> USB20_N4 <25>

USB20_P3 <25> USB20_N3 <25>

H_PROCHOT_R# <6,24> USB20_P1 <25>

USB20_N1 <25> USB20_P6 <25>

USB20_N6 <25> USB20_P8 <25>

USB20_N8 <25>

ENBKL <11,21> ENVDD <11,21>

DDC2_CLK <11,21> CRT_VSYNC <23> CRT_HSYNC <23>

CRT_DDC_CLK <11,23> D_RED <23>

TXOUT_L1+ <21> TXOUT_L1- <21>

TXOUT_L0+ <21> TXOUT_L0- <21>

TXOUT_L2+ <21> TXOUT_L2- <21>

TXCLK_L+ <21> TXCLK_L- <21>

F

USB

DDC2_DATA <11,21>

CRT_DDC_DATA <11,23>

D_GREEN <23>

D_BLUE <23>

LVDS

SATA

11/16 update

G

H

4 4

FPC_O0P45X2P35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2008/10/06 2009/10/06

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

F

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931

401814

G

CB

of

29 43Friday, January 08, 2010

H

5

C1196 100P_0402_50V8C1196 100P_0402_50V8

1 2

R807

6.19K_0402_1%

+VCC_3IN1

12

USB20_N2<25>

USB20_P2<25>

0.1U_0402_16V4Z

1

2

D D

+3VALW

Trace width:20mil

0.1U_0402_16V4Z

1

C1197

C1198

C1198 10U_0805_10V6K

2

10U_0805_10V6K

2

4

U18

1

10 11 12

2 3

4 5 6

7 8

9

REFE DM

DP 3V3_IN

CARD_3V3 V18

XD_CD# SP1

SP2 SP3 SP4 SP5

EPAD

25

USB20_N2 USB20_P2 CLK_48M_SD_R

1U_0402_6.3V6K

2

C1200

C1199

1

XD_RDY_SD_WP_MS_CLK

R809

12

XD_RE#_MS_INS#

0_0402_5%

XD_CE#_SD_D1 XD_CLE_SD_D0_MS_D7 XD_ALE_SD_D7_MS_D3 XD_WE#_SD_CD#

3

17

GPIO0

24

CLK_IN

23

XD_D7

22

SP14

XD_D5_SD_D2_MS_D5

21

SP13

XD_D4_SD_D3_MS_D1

20

SP12

19

SP11

18

SP10

XD_D1_SD_D5_MD_D0

16

SP9

XD_D0_SD_CLK_MS_D2

15

SP8

14

SP7

13

SP6

RTS5138-GR_QFN24_4X4

XD_DATA5_MS_BS

XD_D2_SD_CMD

R808

0_0402_5%

R810

0_0402_5%

12

CLK_48M_SD

CLK_48M_SD <20>

XD_D0_SD_CLK_MS_D2_R

2

CLK_48M_SD_R

12

@

@ R863

R863 10_0402_5%

10_0402_5%

1

@

@ C1203

C1203 10P_0402_50V8J

10P_0402_50V8J

2

1

XD_RDY_SD_WP_MS_CLK_R

XD_D0_SD_CLK_MS_D2_R

XD_RDY_SD_WP_MS_CLK_R

C C

+VCC_3IN1

Trace width:20mil

B B

0.1U_0402_16V4Z

1

C1289

2

EMI reserved Close to JP2

12

@

@ R811

R811 10_0402_5%

10_0402_5%

1

@

C1201

C1201 10P_0402_50V8J

10P_0402_50V8J

2

JP2

33

XD-VCC

8

XD-D0

9

XD-D1

26

XD-D2

27

XD-D3

28

XD-D4

30

XD-D5

31

XD-D6

32

XD-D7

6

XD-WE

7

XD-WP

5

XD-ALE

34

XD-CD-SW

1

XD-R/B

2

XD-RE

3

XD-CE

4

XD-CLE

13

4IN1-GND

22

4IN1-GND

T-SOL_144-3000000900_NR

ME@

12

1

2

4 IN 1 CONN

@

@ R812

R812 10_0402_5%

10_0402_5%

@

@ C1202

C1202 10P_0402_50V8J

10P_0402_50V8J

SD-VCC

SD-CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3

SD-CMD

SD-CD-SW

SD-WP-SW

MS-VCC

MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3

MS-INS

MS-BS

GROUND GROUND

23 24

25 29 10 11

12 36 35

14

XD_RDY_SD_WP_MS_CLK_R

15 19 20 18 16 17 21

37 38

R813

@

1 2

100K_0402_1%

XD_D0_SD_CLK_MS_D2_R XD_CLE_SD_D0_MS_D7

XD_CE#_SD_D1 XD_D5_SD_D2_MS_D5 XD_D4_SD_D3_MS_D1

XD_D2_SD_CMD

XD_WE#_SD_CD#

XD_RDY_SD_WP_MS_CLK_R

XD_D1_SD_D5_MD_D0 XD_D4_SD_D3_MS_D1

XD_D0_SD_CLK_MS_D2_R XD_ALE_SD_D7_MS_D3

XD_RE#_MS_INS#

XD_DATA5_MS_BS

1

0.1U_0402_16V4Z

1

2

C1291

2

0.1U_0402_16V4Z

C1290

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2007/8/18

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

of

30 43Friday, January 08, 2010

C

A

B

C

D

E

USB PORT x 1

+USB_VCCA

1

+

C1206

1 1

R608 0_0402_5%R608 0_0402_5%

USB20_N0<25> USB20_P0<25>

1 2 1 2

R646 0_0402_5%R646 0_0402_5%

WCM-2012-900T_4P

4

3

1

2

L11

@

C1206 150U_B2_6.3VM

150U_B2_6.3VM

2

USB20_N0_R USB20_P0_R

USB20_P0_R

3

2

W=40mils

1

C1207

C1207 470P_0402_50V7K

470P_0402_50V7K

2

3

1

PSOT24C_SOT23-3

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

@

@ D5

D5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004S50DZL

SUYIN_020173MR004S50DZL ME@

ME@

C1208

0.1U_0402_16V4Z

USB_ON#<29>

+5VALW

1

2

U19

1

GND

VOUT

2

VOUT

VIN VIN3VOUT

4

EN

APL3510BKI-TRGSO8

2 2

3 3

+USB_VCCA

40mil

8 7 6 5

FLG

1

C1209

1000P_0402_50V7K@

2

USB_OC#0 <25>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

E

C

of

31 43Friday, January 08, 2010

5

CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

D D

+3VS

To suuport Wake-on-Jack or Wake-on-Ring, the CODEC VAUX_3.3 & VDD_IO pins must be powerd by a rail that is not removed unless AC power is removed. *DSH page42 has more detail.

+3VS

C C

HDA_RST_AUDIO#<25> HDA_BITCLK_AUDIO<25>

HDA_SYNC_AUDIO<25>

HDA_SDIN0<25>

HDA_SDOUT_AUDIO<25>

EAPD active low 0=power down ex AMP 1=power up ex AMP

EAPD<29>

C1236

@C1236

@

1 2

0.1U_0402_16V4Z

C1237

@C1237

@

1 2

0.1U_0402_16V4Z

C1238

@C1238

@

1 2

0.1U_0402_16V4Z

C1240

@C1240

@

1 2

0.1U_0402_16V4Z

B B

0.1U_0402_16V4Z

R826

@R826

@

1 2

R828

@R828

@

1 2

R830

@R830

@

1 2

0_0402_5%

Internal SPEAKER

EC_MUTE#<29>

GND GNDA

4

+3VS

1

C1214

2

1

C1217

C1218

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C1224

C1223

2

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z R816

R816

HDA_BITCLK_AUDIO

R819 33_0402_5%R819 33_0402_5%

1 2

HDA_SDOUT_AUDIO

PC_BEEP

EC_MUTE#

SPKL+<29> SPKL-<29>

SPKR+<29> SPKR-<29>

wide 20MIL

1

C1215

C1216

2

10U_0805_10V4Z

0.1U_0402_16V4Z

10K only needed if supply to VAUX_3.3 is removed during system re-start.

12

1

C1231

C1232

2

10K_0402_5%

10U_0805_10V4Z

0.1U_0402_16V4Z

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

R8240_0402_5% R8240_0402_5%

1 2

12

R8250_0402_5% R8250_0402_5%

SPKL+ SPKL-

SPKR+ SPKR-

C1219

U20

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

10

PC_BEEP

38

GPIO0/EAPD#

37

GPIO1/SPK_MUTE#

40

DMIC_CLK

1

DMIC_1/2

11

LEFT+

13

LEFT-

16

RIGHT+

14

RIGHT-

1

2

1U_0603_10V4Z

3

GND

41

1

C1220

2

0.1U_0402_16V4Z

18

2

29

7

VDD_IO

FILT_1.8

VAUX_3.3

DVDD_3.3

CX20671-11Z_QFN40_6X6

FILT_1.65

27

28

AVDD_5V

AVDD_3.3

1

C1221

2

10U_0805_10V4Z

26

LPWR_5.0 RPWR_5.0

AVDD_HP CLASS-D_REF

SENSE_A

PORTB_R

PORTB_L

B_BIAS

C_BIAS

PORTC_R

PORTC_L

PORTA_R

PORTA_L

3

AVDD_3.3 pinis output of

1

internal LDO. NOT connect to external supply.

C1222

2

0.1U_0402_16V4Z

1

C1225

2

12 15 17

36

35 34 33

32 31 30

23 22

24

NC

25

NC

39

NC

21

AVEE

19

FLY_P

20

FLY_N

+LDO_OUT_3.3V

1

C1226

2

10U_0805_10V4Z

0.1U_0402_16V4Z

+MICBIASB

+MICBIASC

1 2

C1239 1U_0603_10V4ZC1239 1U_0603_10V4Z

Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)

+5VS

1

C1228

C1227

2

0.1U_0402_16V4Z

1

C1233

2

C1234 2.2U_0603_10V7KC1234 2.2U_0603_10V7K C1235 2.2U_0603_10V7KC1235 2.2U_0603_10V7K

0.1U_0402_16V4Z

Please bypass caps very close to device.

0.1U_0402_16V4Z

MIC_INR

MIC_INL

1 2 1 2

HP_OUTR <33> HP_OUTL <33>

1

C1241

C1242

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C1229

C1230

2

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

R817 5.11K_0402_1%R817 5.11K_0402_1% R818 10K_0402_1%R818 10K_0402_1%

R820 39.2K_0402_1%R820 39.2K_0402_1%

Internal MIC

Headphone

INT_MIC_L<29>

2

R815

1 2

0.1_1206_1%

1 2 1 2

1 2

R822 100_0402_1%R822 100_0402_1% R823 100_0402_1%R823 100_0402_1%

+MICBIASB

R829

4.7K_0402_5%

R648 4.7K_0402_5%

1 2

+3VS

@

C1210

@

22P_0402_50V8J

+5VS

+3VS

MIC_JD <33>

PLUG_IN <33>

R821 2.2K_0402_5%R821 2.2K_0402_5%

EXT_MIC_R <33> EXT_MIC_L <33>

1 2 1 2

MIC_INL

@

12

C1243 2.2U_0603_10V7KC1243 2.2U_0603_10V7K C1244 2.2U_0603_10V7K

C1244 2.2U_0603_10V7K

1

2

C1211

@

22P_0402_50V8J

Port C Port A

HDA_RST_AUDIO# HDA_SYNC_AUDIO HDA_SDOUT_AUDIO

1

2

C1212

@

22P_0402_50V8J

Sense resistors must be connected same power that is used for VAUX_3.3

External MIC

R827

1 2

0_0402_5%

MIC_INR MIC_INL

1

2

C1213

+MICBIASC

MIC_INR

1 2

1

R8140_0402_5% @ R8140_0402_5% @

EMI

HDA_BITCLK_AUDIO

PC Beep

EC Beep

BEEP#<29>

A A

SB_SPKR<25>

SB Beep

5

0.1U_0402_16V4Z

11/16 update for PC Beep

C1292

1 2

C1293

1 2

12

1

R833

10K_0402_5%

R833

@

2

@

C1246

0.1U_0402_16V4Z

R973

1 2

0_0402_5%

PC_BEEPPC_BEEP1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/25 2008/04/

Compal Secret Data

Deciphered Date

2

Compal Electronics,Ltd.

Title

SCHEMATIC A5931

Size Document Number Rev

C

Date: Sheet

401814

32 43Friday, January 08, 2010

of

1

of

C

5

D D

C C

4

W=20mils

EXT_MIC_L<32>

W=20mils

EXT_MIC_R<32>

MIC_JD<32>

3

L181

EXT_MIC_L

47P_0402_50V8J

EXT_MIC_R

47P_0402_50V8J

MIC_JD

C1251

C1253

1

2

1

2

L181

1 2

FBMA-L10-160808-121LMT_2P

L182

1 2

FBMA-L10-160808-121LMT_2P

2

EXT_MIC_L-2

1

C1252

@C1252

@

10P_0402_50V8J

2

EXT_MIC_R-2

1

C1254

@C1254

@

10P_0402_50V8J

2

1

C125510P_0402_50V8J@C125510P_0402_50V8J @

2

PSOT24C_SOT23-3

1

Audio Jack

MIC IN

JMIC1

7 3 1 4 2

5

2

3

@

D8

1

GNDAGNDA

6 8

SINGA_2SJ2285-001191

SINGA_2SJ2285-001191 ME@

ME@

220P_0402_50V7K

B B

W=20mils

HP_OUTL<32> HP_OUTR<32> PLUG_IN<32>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

HP_OUTL HP_OUTR PLUG_IN

2008/03/25 2008/04/

R861

1 2

15_0402_5%

R862

1 2

15_0402_5%

Compal Secret Data

Deciphered Date

L183

1 2

FBMA-L10-160808-121LMT_2P

FBMA-L10-160808-121LMT_2P L184

L184

1 2

FBMA-L10-160808-121LMT_2P

220P_0402_50V7K

C1258

10P_0402_50V8J

@

2

C1256

1 2

PL-OUT

PR-OUT

1

@

D9

2

PSOT24C_SOT23-3

C1257

1 2

Headphone

JHP1

7 3 1 4 2

5

2

3

1

GNDA

Title

Size Document Number Rev

Custom

Date: Sheet

6 8

SINGA_2SJ2285-001191

SINGA_2SJ2285-001191 ME@

ME@

Compal Electronics,Ltd.

SCHEMATIC A5931

401814

1

33 43Friday, January 08, 2010

GNDA

of

C

5

H4

H3

H3 H_2P8

H_2P8

1

@

1

H4

H5

H7

H_2P8

1

H24

H24 H_4P2

H_4P2

1

@

1

H7 H_2P8

H_2P8

@

1

H11

H12

H_1P8N

@

1

@

FD4

FD4 FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

1

H_2P8

@

1

H6

H6 H_6P0

H_6P0

@

1

H23

H23 H_4P2

H_4P2

@

1

FD3

FD3 FIDUCIAL_C40M80

FIDUCIAL_C40M80

H2

H1

D D

C C

H1

H_2P8

@

1

H8

H9

H_3P2

@

1

H10

H10 H

H

H_3P8X5P8N

@

1

H21

H21 H_4P2

H_4P2

@

1

FD1

FD1 FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

1

@

H22

H22 H_4P2

H_4P2

@

1

FD2

FD2 FIDUCIAL_C40M80

FIDUCIAL_C40M80

4

@

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

C

of

34 43Friday, January 08, 2010

1

A

+1.2VALW TO +1.2V_HT

+1.2VALW

DVT

12

1

C1262

R839

1K_0402_5%

1 1

B+

VLDT_EN#

2N7002DW-T/R7_SOT363-6

2 2

10U_0805_10V4Z

R843

R843 200K_0402_5%

200K_0402_5%

12

2

Q14B

5

U21

8

D

7

D

6

D

5

D

SI4800BDY_SO8

1.2VS_GATE

3

4

S S S

G

3.265A

1 2 3 4

1

2

C1266

0.1U_0603_25V7K

+1.2V_HT

1

C1259

C1259 10U_0805_10V4Z

10U_0805_10V4Z

2

1U_0402_6.3V4Z

2N7002DW-T/R7_SOT363-6

1

C1260

2

Q14A

R840

1 2 61

+1.8V to +1.8VS

+1.8V

1

C1274

2

10U_0805_10V4Z

68K_0402_1%

R852

SUSP

1

2

12

Q18B

5

C1273

3 3

C1273

10U_0805_10V4Z

B+

2N7002DW-T/R7_SOT363-6

6.988A

U24

8

S

D

7

S

D

6

S

D

5

G

D

SI4800BDY_SO8

1.8VS_GATE SUSP

3

4

11/30 Update change R852 to 68K, C1277 to 0.1u

+1.5VS +2.5VS +1.8V+0.9V

4 4

R855

R855 470_0603_5%

470_0603_5%

1 2 13

D

SUSP SUSP SYSON# SYSON#

2

G

Q29

S

2N7002_SOT23

D

S

A

R856

R856 470_0603_5%

470_0603_5%

1 2 13

2

G

Q30

Q30 2N7002_SOT23

2N7002_SOT23

1 2 3 4

1

2

C1277

0.1U_0603_25V7K

+1.8VS

1

C1275

C1275 10U_0805_10V4Z

10U_0805_10V4Z

2

1U_0402_6.3V4Z

2N7002DW-T/R7_SOT363-6

R857

R857 470_0603_5%

470_0603_5%

1 2 13

D

2

G

Q31

S

2N7002_SOT23

1

C1276

2

Q18A

470_0603_5%

VLDT_EN#

2

1 2 61

B

R851

470_0603_5%

2

R858

R858 470_0603_5%

470_0603_5%

1 2 13

D

S

B

2

G

Q32

Q32 2N7002_SOT23

2N7002_SOT23

SUSP <29>

10U_0805_10V4Z

B+

+1.1VS

R859

R859 470_0603_5%

470_0603_5%

1 2 13

D

S

C1269

VGA@

R849

R849 200K_0402_5%

200K_0402_5%

VGA_PWR_EN#

2N7002DW-T/R7_SOT363-6

VLDT_EN#

2

G

Q33

Q33 2N7002_SOT23

2N7002_SOT23

C

D

+1.5VS to +1.5VS_VGA

+1.5VS

1

C1270

C1270 VGA@

VGA@

2

10U_0805_10V4Z

12

VGA@

VGA@ Q16B

Q16B

U23

8

S

D

7

S

D

6

S

D

5

G

D

SI4800BDY_SO8

VGA@

1.5VS_VGA_GATE VGA_PWR_EN#

3

5

4

6.988A

1 2 3 4

+1.5VS_VGA

1

C1268

VGA@C1268

VGA@

10U_0805_10V4Z

2

2N7002DW-T/R7_SOT363-6

1

C1272

C1272 VGA@

VGA@

0.1U_0603_25V7K

2

1

VGA@

VGA@ C1271

C1271

2

1U_0402_6.3V4Z

Q16A

Q16A VGA@

VGA@

1 2 61

R848

VGA@

2

470_0603_5%

+1.8V to +1.8VS_VGA

+1.8V

1

12

VGA@

VGA@ Q17B

Q17B

2

5

1

C1281

C1281 VGA@

VGA@

2

10U_0805_10V4Z

68K_0402_1%

3

4

Deciphered Date

R986

C1279

VGA@

10U_0805_10V4Z

R854

B+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2009/10/06

R854

100K_0402_5%

VGA@

VGA_PWR_EN#

2N7002DW-T/R7_SOT363-6

Compal Secret Data

U25

8

D

7

D

6

D

5

D

SI4800BDY_SO8

VGA@

1.8VS_VGA_GATE

12

S S S G

6.988A

1 2 3 4

D

1

2

VGA_PWR_EN#<18>

VGA_PWR_EN<18,24,36,40>

+1.8VS_VGA

1

C1280

VGA@C1280

VGA@

10U_0805_10V4Z

2

2N7002DW-T/R7_SOT363-6

C1282

C1282 VGA@

VGA@

0.1U_0603_25V7K

E

100K_0402_5%

R845

R845 100K_0402_5%

100K_0402_5% VGA@

VGA@

1 2

13

D

Q27

Q27 2N7002_SOT23

2N7002_SOT23 VGA@

VGA@

S

10K_0402_5%

401814

SYSON#

SYSON

R842

VLDT_EN#

R850

E

2

G

12

2

G

12

SYSON#<37>

SYSON<29,38>

+3VALW

VGA_PWR_EN#

2

G

12

R846

10K_0402_5%

VGA@

VLDT_EN<29,36>

1

VGA@

VGA@ C1278

C1278

2

1U_0402_6.3V4Z

R853

470_0603_5%

VGA@

1 2 61

VGA_PWR_EN#

Q17A

Q17A VGA@

VGA@

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

+5VALW

1 2

13

+5VALW

1 2

13

35 43Friday, January 08, 2010

R838

R838 100K_0402_5%

100K_0402_5%

D

Q26

Q26 2N7002_SOT23

2N7002_SOT23

S

R847

R847 100K_0402_5%

100K_0402_5%

D

Q28

Q28 2N7002_SOT23

2N7002_SOT23

S

of

C

5

D D

PR102

22K_0402_1%

1 2

VLDT_EN<29,35>

C C

+5VALW

PR104

220K_0402_1%

PR106

100_0603_1%

100_0603_1% 1 2

4.7U_0603_6.3V6K

12

PC108

12

PC102

0.22U_0402_10V6K

12

PC107

@PC107

@

47P_0402_50V8J

1 2

PR108

3.57K_0402_1%

3.57K_0402_1% 1 2

4

PR101

267K_0402_1%

1 2

3

578

PD101

21

+5VALW

@

1SS355_SOD323-2

BST_NBCOREP

14

15

1

PU101

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

TP

VBST

EN_PSV

V5DRV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

DRVH

LL

TRIP

DRVL

13 12 11 10 9

PR103

1 2

DH_NBCOREP

2.2_0603_5%

LX_NBCOREP

DL_NBCOREP

BST_NBCOREP_1

PR107

0.1U_0603_25V7K

+5VALW

6.65K_0402_1%

PC103

1 2

12

PC106

4.7U_0805_10V6K

3 6

241

786

5

4

123

12

PQ101

PQ101 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

1.5UH_PCMC063T-1R5MN_9A_20%

1.5UH_PCMC063T-1R5MN_9A_20% 1 2

12

PR105

4.7_1206_5%

12

PC105

PC105 680P_0603_50V8J

680P_0603_50V8J

PQ102

SI4634DY-T1-E3_SO8

12

PC122

PC123

0.1U_0603_25V7K

PL101

2

PL102

FBMA-L11-322513-151LMA50T_1210

NB_51117_B+

1 2

12

PC101

10U_1206_25VAK

2200P_0402_50V7K

1

+

2

PC104

220U_B2_2.5VM_R25M

1

2

1

B+

+

PC115

68U_25V_M_R0.44

+NB_COREP

12

PC116

PC116 10U_0603_6.3V6M

10U_0603_6.3V6M <BOM Structure>

+NB_COREP +NB_CORE

PJ102

2

112

JUMP_43X118@

PJ103

2

112

JUMP_43X79@

+1.1VS+1.1VSP

PJ105

12

PR109

PR109 10K_0402_1%

10K_0402_1%

SSM3K7002FU 1N SC70-3

PC119

7

8

PR124

10K_0402_5%

SSM3K7002FU 1N SC70-3

+5VALW

12

6

PU103

VIN

POK

VOUT

VCNTL

VOUT

EN

FB

VIN

GND

APL5912-KAC-TRL_SO8

1

B B

M93

Park

A A

VGA_PWR_EN

,24,35,40>

1.1V

1.0V

1U_0603_10V6K

5

PR122

12_0402_5%

1 2

PC118

1U_0402_6.3V6K

12

PQ103

5 4 3 2 9

PR110

PR110 30K_0402_1%

30K_0402_1%

1 2

13

D

S

BOM control (R*C>1ms)

PR112

10K_0402_1%

1

PJ104

1

JUMP_43X79

JUMP_43X79 @

@

2

12

PC121

4.7U_0805_6.3V6K

PR123

1.82K_0402_1%

1 2

12

PC109

0.1U_0402_16V7K

SSM3K7002FU 1N SC70-3

12

2

G

+1.2VALW

4

1 2

PC117

0.01U_0402_25V7K

PR121

4.53K_0402_1%

PR113

@ PR113

@ 10K_0402_1%

10K_0402_1%

PQ104

12

+3VALW

PR111

PR111 10K_0402_5%

10K_0402_5%

1 2

@PR114

@ 10K_0402_5%

10K_0402_5%

1 2

PR115

13

D

10K_0402_1%

1 2

2

G

S

2.2K_0402_1%

1 2

+VGA_PCIEP

12

PC120

1.0V

1.1V

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HL1.017V

+3VALW

PR114

POWER_SEL

PR116

PR123

1.24k

1.82k

3

1.1V

POWER_SEL <11>

VLDT_EN<29,35>

PR120

12_0402_5%

VLDT_EN

1 2

PC112

1U_0603_10V6K

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K

12

PR117

10K_0402_5%

PC111

PU102

7

POK

8

EN

2

+5VALW

12

6

VOUT

VCNTL

VOUT

GND

APL5912-KAC-TRL_SO8

1

2010/03/122008/11/03

+1.5VS

1

PJ101

1

JUMP_43X79

JUMP_43X79 @

@

2

12

PC114

4.7U_0805_6.3V6K

5

VIN

4 3 2

FB

9

VIN

Title

Size Document Number Rev

Date: Sheet

PR119

1.3K_0402_1%

PR118

3.24K_0402_1%

PJ105

2

112

JUMP_43X79@

12

PC110

0.01U_0402_25V7K

12

Compal Electronics, Inc.

SCHEMATIC A5931.

PC113

12

22U_0805_6.3V6M

401814

36 43Friday, January 08, 2010

1

+1.1/1.0VS_VGA+VGA_PCIEP

+1.1VSP

C

of

5

4

3

2

1

+1.8V

1

PJ201

1

JUMP_43X79

PC201

@

12

PQ201

12

2

1 2

13

D

2

G

S

PC209

@PC209

@

47P_0402_50V8J

1 2

PR211

1 2

10K_0402_1%

PR205

10K_0402_1%

PR201

1K_0402_1%

PR203

1K_0402_1%

267K_0402_1%

1 2

PR207

PU201

1

VIN

2

12

PC203

0.1U_0402_16V7K

1

PU203

2

TON

EN_PSV

3

VOUT

4

VFB=0.75V

V5FILT

5

VFB

6

PGOOD

GND7PGND

GND

3

REFEN

4

VOUT

RT9173DPSP_SO8

+0.9VP

12

PC204

PC204 10U_0805_6.3V6M

10U_0805_6.3V6M

15

14

TP

VBST

DRVH

LL

TRIP

V5DRV

DRVL

TPS51117RGYR_QFN14_3.5x3.5

8

6

VCNTL

5

NC

7

NC

8

NC

9

GND

PR208

BST_1.5V BST_1.5V-1

DH_1.5V

13

LX_1.5V

12 11 10

DL_1.5V

9

PR208

1 2

2.2_0603_5%

12

PR206

8.66K_0402_1%

+3VALW

12

PC202

PC202 1U_0402_6.3V6K

1U_0402_6.3V6K

@

0.1U_0603_25V7K

+5VALW

12

PD201

21

+5VALW

1SS355_SOD323-2

PC213

1 2

PC214

4.7U_0805_10V6K

PU202

APL5508-25DC-TRL_SOT89-3

PC206

2

IN

12

PC218

PC219

2200P_0402_50V7K

0.1U_0603_25V7K

+3VS

12

1U_0402_6.3V6K

1.5_51117_B+

5

4

5

4

123

PQ202

SIS412DN-T1-GE3_POWERPAK8-5

123

PL202

2.2UH_PCMC063T-2R2MN_8A_20%

2.2UH_PCMC063T-2R2MN_8A_20% 1 2

12

PR212

4.7_1206_5%

12

PC215

PQ203

680P_0402_50V7K

SI7716ADN-T1-GE3_POWERPAK8-5

+1.5VSP +1.5VS

3

OUT

GND

1

PC207

4.7U_0805_6.3V6K

PL201

FBMA-L11-322513-151LMA50T_1210

1 2

12

PC210

PC210 10U_1206_25VAK

10U_1206_25VAK

+1.5VSP

1

12

+

2

PC208

220U_B2_2.5VM_R25M

PC217

PC217 10U_0603_6.3V6M

10U_0603_6.3V6M

PJ202

2

JUMP_43X79@

PJ203

2

JUMP_43X79@

JUMP_43X79@ PJ204

PJ204

2

JUMP_43X118@

12

B+

12

PC216

@PC216

@ 680P_0402_50V7K

680P_0402_50V7K

112

12

PR204

@PR204

@ 150_1206_5%

150_1206_5%

+2.5VSP

+0.9V+0.9VP

+2.5VS+2.5VSP

D D

4.7U_0805_6.3V6K

PR202

@PR202

@ 0_0402_5%

0_0402_5%

+5VALW

1 2

0_0402_5%

1 2

SYSON#<35>

C C

SUSP#<29>

B B

0.1U_0402_16V7K

PR210

PR209

100_0603_1%

1 2

PC212

4.7U_0603_6.3V6K

SSM3K7002FU 1N SC70-3

PC205

@PC205

@

12

PC211

@PC211

@

0.1U_0402_16V7K

12

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/06/11 2010/03/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

SCHEMATIC A5931

401814

1

C

of

37 43Friday, January 08, 2010

5

PR302

0_0402_5%

D D

SYSON<29,35>

+5VALW

C C

1 2

PR304

100_0603_1%

1 2

4.7U_0603_6.3V6K

PC307

12

PC302

@PC302

@

0.1U_0402_16V7K

12

4

PC306

@PC306

@

47P_0402_50V8J

1 2

PR306

14K_0402_1%

1 2

PR307

PR307 10K_0402_1%

10K_0402_1%

PR301

267K_0402_1%

1 2

3

PD301

21

@

PR303

15

1

PU301

2

TON

3

VOUT

4

VFB=0.75V

V5FILT

5

VFB

6

PGOOD

14

TP

EN_PSV

VBST

V5DRV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

DRVH

TRIP

DRVL

BST_1.8V

DH_1.8V

13

LX_1.8V

12

LL

11 10

DL_1.8V

9

PR303

1 2

2.2_0603_5%

12

PR305

BST_1.8V-1

8.45K_0402_1%

+1.8VP +1.8V

+1.2VALWP +1.2VALW

+5VALW

1SS355_SOD323-2

PC303

0.1U_0603_25V7K

1 2

+5VALW

12

PC305

4.7U_0805_10V6K

PJ301

2

112

JUMP_43X118@

PJ302

2

112

JUMP_43X118@

578

5

4

3 6

241

786

123

2

1.8_51117_B+

PQ301

PQ301 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

12

4.7_1206_5%

12

680P_0402_50V7K

PQ302

SI4634DY-T1-E3_SO8

680P_0402_50V7K

12

PC321

PC322

2200P_0402_50V7K

0.1U_0603_25V7K

PL301

1.5UH_PCMC063T-1R5MN_9A_20%

1 2

PR315

PC315

1

PL303

FBMA-L11-322513-151LMA50T_1210

1 2

12

PC301

PC301 10U_1206_25VAK

10U_1206_25VAK

1

+

2

PC304

220U_B2_2.5VM_R25M

12

PC317

@PC317

@ 680P_0402_50V7K

680P_0402_50V7K

12

B+

+1.8VP

PC319

PC319 10U_0603_6.3V6M

10U_0603_6.3V6M

PL304

FBMA-L11-322513-151LMA50T_1210

PD302

21

@

PR308

B B

+3VALW

+5VALW

A A

5

PR309

0_0402_5%

1 2

PR311

100_0603_1%

1 2

4.7U_0603_6.3V6K

PC314

12

PC309

@PC309

@

0.1U_0402_16V7K

12

PC313

@PC313

@

47P_0402_50V8J

1 2

PR313

6.34K_0402_1%

1 2

12

PR314

10K_0402_1%

4

PR308

267K_0402_1%

1 2

PR310

15

14

1

PU302

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

TP

VBST

EN_PSV

DRVH

VFB=0.75V

V5DRV

DRVL

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

TRIP

BST_1.2V

DH_1.2V

13

LX_1.2V

12

LL

11 10

DL_1.2V

9

PR310

1 2

2.2_0603_5%

12

PR312

2008/06/11 2010/03/12

3

@

0.1U_0603_25V7K

BST_1.2V-1

+5VALW

12

PC312

4.7U_0805_10V6K

14.7K_0402_1%

Compal Secret Data

+5VALW

1SS355_SOD323-2

PC310

1 2

Deciphered Date

5

4

2

1.2_51117_B+

5

4

123

PQ303

123

1.5UH_PCMC063T-1R5MN_9A_20%

1.5UH_PCMC063T-1R5MN_9A_20% SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5

12

PR316

4.7_1206_5%

12

PC316

PQ304

680P_0402_50V7K

SI7716ADN-T1-GE3_POWERPAK8-5

Custom

12

PC324

PC323

0.1U_0603_25V7K

PL302

1 2

COMPAL Electronics

Title

Size Document Number Rev

Date: Sheet

SCHEMATIC A5931.

FBMA-L11-322513-151LMA50T_1210

1 2

12

PC308

PC308 10U_1206_25VAK

10U_1206_25VAK

2200P_0402_50V7K

1

+

PC311

2

220U_B2_2.5VM_R25M

401814

1

12

@PC318

@ 680P_0402_50V7K

680P_0402_50V7K

+1.2VALWP

12

PC320

PC320 10U_0603_6.3V6M

10U_0603_6.3V6M

，

Inc

38 43Friday, January 08, 2010

B+

PC318

of

C

5

PC417

@

PR415

1 2

6.81K_0402_1%

PC423

@

1000P_0402_50V7K

12

VGATE<29>

VCC_PRM

1 2

PR416

PC418

1 2

1000P_0402_50V7K

7.32K_0402_1%

1 2

0.047U_0402_16V7K

1000P_0402_50V7K

1 2

@

PC428

0.22U_0402_6.3V6K

D D

1 2

PC416

1000P_0402_50V7K

PC419

PR423

97.6K_0402_1%

1 2

220P_0402_50V8J

PR426

255_0402_1%

1 2

220P_0402_50V8J

1K_0402_1%

C C

CPU_VCC_SENSE<6>

PR428

10_0402_5%

+CPU_CORE

平行線

10_0402_5%

from output Bulk Cap

PR431

10_0402_5%

1 2

CPU_VSS_SENSE<6>

B B

One phase :Ipeak=10A ; Imax=6A ; 1.2Ipeak=12A L(0.47U, DCR= 4.6m ohm) Rdson=4.5m ~ 5.6m ohm

Rocset=13K ohm // Iocp=12.873A MLCC*9(22U,6.3V,X5R) ; Poscap*4(330U,ESR=9m ohm)

470P_0402_50V7K

PC421

1 2

PR424

12

PC422

1000P_0402_50V7K

1 2

12

PC419

1 2

PR427

0_0402_5%

12

PR433

0_0402_5%

Update:OCP=PR416*10UA/(2.3m ohm) -->PR416=7.32K ohm ;Iocp=~31.8A

PR448

0_0402_5%

PR413

1 2

36.5K_0402_1%

PC424

@PC424

@

PC427

1000P_0402_50V7K

1 2

PC429

.1U_0402_16V7K

4

+3VS

PR401

10K_0402_5%

1 2

12

+3VS

PR403 0_0402_5%PR403 0_0402_5%

PR412

PR407

@

1 2

10K_0402_5%

PR414

1 2

150K_0402_1%

1K_0402_1%

1

SET

2

RBIAS

3

OFS

4

SOFT

5

OCSET

6

VW

7

COMP

8

FB

9

VDIFF

10

VSEN

41

GND PAD

PC426

180P_0402_50V8J

1 2

PR429

VCC_PRM

PC430

PR430

300_0402_1%

12

1 2

Close to Phase1 Choke PL11

PR435

1 2

11K_0402_1%

1 2

.1U_0402_16V7K

Rn

CPU thermal protection at 92 degree C

PSI_L

1 2

38

39

40

PSI_L

VR_ON

PGOOD

ISL6264CRZ-T_QFN40_6X6

DROOP

RTN

DFB

12

11

13

VR_ON

PR402 0_0402_5%PR402 0_0402_5%

<6>

PR408 0_0402_5%PR408 0_0402_5%

1 2

37

PU402

VO

15

14

PR409 0_0402_5%PR409 0_0402_5%

PR404 0_0402_5%PR404 0_0402_5%

1 2

VSUM

VIN

16

<29>

CPU_VID5 <6>

CPU_VID4 <6>

CPU_VID3 <6>

12

PR405 0_0402_5%PR405 0_0402_5%

PR406 0_0402_5%PR406 0_0402_5%

PR410 0_0402_5%PR410 0_0402_5%

1 2

VID032VID133VID234VID335VID436VID5

ISEN2

GND

VDD

19

17

18

CPU_VID2 <6>

31

BOOT1

ISEN1

20

+5VS

B+

PR432

10_0402_5%

1 2

PR434

10_0402_5%

1 2

PR441

1 2

2.61K_0402_1%

PH402

10K_0603_5%_TSM1A103J4302RE

VSUM

1 2

PC432

1 2

0.01U_0402_50V7K

PC431

1U_0402_6.3V6K

12

PH1 under CPU botten side :

3

CPU_VID1 <6>

CPU_VID0 <6>

UGATE1 PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2 PHASE2 UGATE2

BOOT2

CPU_ISEN1

CPU_ISEN2

PC415

0.22U_0603_25V7K

PR422 0_0402_5%PR422 0_0402_5%

UG_CPU2

PR425

0.22U_0603_25V7K

1 2

4.7U_0603_6.3V6K

12

PC425

PR411

1 2

2.2_0603_5%

30 29 28 27 26 25 24 23 22 21

2.2_0603_5%

0.22U_0603_25V7K

100K_0603_1%_TSM1A104F4361RZ

2

1

(ME interference /change to 6mm)

PL401

FBMA-L18-453215-900LMA90T_1812

CPU_B+

12

1 2

PC409

1 2

12

PC403

2200P_0402_50V7K

PR437

1 2

4.7_1206_5%

12

PC407

VL

1 2

1

PC409

2200P_0402_50V7K

PR417

4.7_1206_5%

PC402

680P_0603_50V8J

1 2

0.47UH_FDVE0630-R47M=P3_17.7A_20%

PR438

1 2

VSUM

680P_0603_50V8J

PR442

PR442 47K_0402_1%

47K_0402_1%

SSM3K7002FU 1N SC70-3

578

03/03_EVT

PQ402

UG_CPU1

PHASE_CPU1

AO4456_SO8

LG_CPU1

12

+5VS

12

PC420

PQ403

578

3 6

241

578

3 6

AO4466_SO8

241

CPU_B+

03/03_EVT

1 2

PQ404 AO4466_SO8PQ404 AO4466_SO8

3 6

241

PHASE_CPU2

AO4456_SO8

LG_CPU2

VL VL

PH401

PQ405

12

0.1U_0603_25V7K

578

3 6

241

PC408

PR444

11.3K_0402_1%

11.3K_0402_1% 1 2

TM_REF1

12

3 2

8

P

+

-

G

4

PR443

47K_0402_1%

1 2

O

PU401A

LM393DG_SO8

PC411

0.47UH_FDVE0630-R47M=P3_17.7A_20%

0.47UH_FDVE0630-R47M=P3_17.7A_20% 1 2

PR420

10K_0402_1%

0.22U_0603_16V7K

PR419

1 2

3.65K_0805_1%

Rs

VSUM

1 2

PC405

PC404

10U_1206_25V6M

PL403

1 2

10K_0402_1%

PR439

PC406

0.22U_0603_16V7K

0.22U_0603_16V7K 1 2

1 2

3.65K_0805_1%

FBMA-L18-453215-900LMA90T_1812

1 2

1

+

1 2

PC413

2

10U_1206_25V6M

PL402

PR421

1_0402_5%

PR421

PC401

10U_1206_25V6M

PQ401

1_0402_5%

1 2

VCC_PRMCPU_ISEN1

PR440

1_0402_5%

PR440

1_0402_5%

1 2

VCC_PRMCPU_ISEN2

MAINPWON<6,29>

13

D

2

G

S

PC414

PC414 68U_25V_M_R0.44

68U_25V_M_R0.44

+CPU_CORE

PR418

PR418 10K_0402_1%

10K_0402_1%

1 2

CPU_ISEN2

+CPU_CORE

PR436

PR436 10K_0402_1%

10K_0402_1%

1 2

CPU_ISEN1

B+

12

PC410

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/06/11 2010/03/12

3

0.22U_0603_16V7K

Compal Secret Data

Deciphered Date

PR445

12.1K_0402_1%

12

PC412

PR446

100K_0402_1%

12

PR447

PR447 100K_0402_1%

100K_0402_1%

1000P_0402_50V7K

2

12

VL

COMPAL Electronics，Inc

Title

Size Document Number Rev

Custom

Date: Sheet

SCHEMATIC A5931

401814

1

C

of

39 43Friday, January 08, 2010

5

VGA_TON

D D

PR502

0_0402_5%

VGA_PWR_EN<18,24,35,36>

+5VALW

MXM_PWRGD<14>

C C

1 2

+3VS

12

PR518

PR518 10K_0402_1%

10K_0402_1%

PR506

100_0402_1%

12

PC501

0.1U_0402_16V7K

@

12

PC509

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K <BOM Structure>

PR510

12

36.5K_0402_1%

PR504

PR504 0_0402_5%

0_0402_5%

47P_0402_50V8J@

VGA_EN BST_VGA

VGA_VOUT+VGA_COREP

12

VGA_V5FILT

VGA_FB

12

PR509

0_0402_5%

@

PC512

1 2

PR511

7.68K_0402_1%

7.68K_0402_1% 1 2

2 3 4 5 6

VGA_FB1

4

TON VOUT V5FILT VFB PGOOD

PR501

267K_0402_1%

1 2

15

1

TP

EN_PSV

GND7PGND

8

PR503

BST_VGA-1

1 2

14

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

PU501

PU501 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

2.2_0603_5%

UG_VGA SW_VGA VGA_TRIP

1 2

PR507

6.65K_0402_1%

LG_VGA

0.1U_0603_25V7K

PD501

PD501 1SS355_SOD323-2@

1SS355_SOD323-2@

1 2

PC504

1 2

+5VALW

12

PC510

4.7U_0805_6.3V6K

3

VGA_IN

578

PQ501

PQ501 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

3 6

241

786

5

4

PQ502

123

SI4634DY-T1-E3_SO8

12

PC516

2200P_0402_50V7K

0.1U_0603_25V7K

1 2

PR505

4.7_1206_5%

PC511

680P_0603_50V7K

PL502

12

PC515

1UH_PCMC063T-1R0MN_11A_20%

12

VGA_SNB

12

PC502

10U_1206_25V6M

2

PL501

HCB1608KF-121T30_0603

1 2

PC503

10U_1206_25V6M

12

PR508

0_0402_5%

1

+

PC505

2

PR512

PR512 0_0402_5%

0_0402_5%

B+

+VGA_COREP

12

PC507

PC506

330U_D2_2.5VY_R15M

@

12

10U_0805_6.3V6M

+VGASENSE

10U_0805_6.3V6M

+VGA_COREP +VGA_CORE

PC508

10U_0805_6.3V6M

12

PC514

PC514 10U_0603_6.3V6M

10U_0603_6.3V6M

PJ501

2

JUMP_43X118@

112

1

+3VALW

PR513

115K_0402_1%

1 2

PR515

13

D

GVID-2

2

G

PQ504

S

SSM3K7002FU_SC70-3

B B

SSM3K7002FU_SC70-3

S

0.1U_0402_16V7K

PC513

10K_0402_1%

1 2

12

PR515

12

PR516

10K_0402_1%@

VGA_PWRSEL0

A A

5

4

12

PR514

PR514 10K_0402_1%

10K_0402_1%

PQ505

SSM3K7002FU_SC70-3

13

D

GVID-1

2

G

S

Park

VGA_CORE

0

1

1V

0.95V

PR517

10K_0402_1%

1 2

VGA_PWRSEL0 <15>

M93-LP

VGA_PWRSEL0

0

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VGA_CORE

0.95V

0.9V

Compal Secret Data

Deciphered Date

2008/11/122007/11/12

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931

401814

40 43Friday, January 08, 2010

1

of

C

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

D D

1

modify OCP point change PR416 from 3.65K to 7.32K

P.39

2009.9.29

EVTChange design

2

3 4

5

6

C C

7

8

9

Change design

add resistance for HW request

modify thermal protection function point

modify power sequence

modify resistance for AMD suggestion

P.36

P.40

P.36

P.39

P.36

change PC102 from 0.1u to 0.22umodify capacity for AMD suggestion

change PR123 from 1.24K to 1.82Kmodify VGA_PCIEP output voltage

change PR511 from 10K to 7.68Kmodify VGA output voltage

add PR116 to 10K

change PR445 from 13.3K to 12.1K

change PR102 from 1.3K to 22K change PR104 from 47K to 220K

change PR116 from 10k to 2.2K

add PC115(68uf)reduce noise issue

2009.9.29

2009.10.08

2009.10.16

2009.10.22

2009.11.16

2009.11.17

EVT

EVTChange design

EVT

PVT

10

11

B B

12

13

14

15

16

17

18

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/06/11 2010/03/12

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

COMPAL Electronics，Inc

SCHEMATIC A5931

401814

41 43Friday, January 08, 2010

1

C

of

5

4

3

2

1

Item

1

D D

2

3

4

5

6

7

8

C C

9

10

11

12

13

14

15

B B

16

17

18

19

20

21

22

A A

23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/09/20 2008/09/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

42 43Friday, January 08, 2010

C

of

5

4

3

2

1

Modification list PURPOSEPHASE PAGE

P20 Delete R7040.2 For Lan function

0.2 P11 Add R665 For PX DIS only AMD recommend

0.2 P12 Pop C871 on UMA and DIS

0.2 P31,33 Change JUSB1,JMIC1,JHP1 connect type for DFX issue

0.2 P11 Add R574 For PX Enable

D D

0.2 Change R674 to 100k ohm, C1046 to 0.1uF, R860 to 470 ohm, C1277 to 33nF For M97LP power sequence

0.2 Y1 and Y3 change footprint and P/N by sourcer request and change C1108,1110 to 33p and C1151,1152 to 27p

0.2 P15 Add R669 for AMD recommend

0.2 P15 Change C925,926,927,L146 to VGA@ Add L185,C939,938,940 for CRT function

0.2 Add R574, R749,740 change to 10k

1.0

C C

1.0

1.0 P4 Change CPU to R3 P/N

P6 Add H_PROCHOT_R# to golden finger pin 114 P11 Add U47 R974 R975 circuit P15 Add R978,C1294,C1295,C1296 to U5 pin AD17 and pin AC 17 connect to GND

For Thermal For AMD suggestion

For Thermal P32 Change R815 P/N, Del R831 832 C1245, Add C1292 C1293 R973 For PC Beep P4 Del R515, R516, R517, R518 For CPU trace P6 @ U43 For MP not need reserve P14 Add R976, R977 For reserve pass AND gate function P18 Add C1297 For reserve +3VS_VGA soft-start P26 Reserve U48, U49, L186, C1298, C1299, R980,R981, R982, R983 For reserve Non share ROM function P21 Del RP17 P23 Del R742, R743

For MP not need reserve

For MP not need reserve P35 Change R852 to 68K, C1277 to 0.1u For +1.8VS power sequence P29 Add C1300 P32 Change R861, R862 to 15 ohm P13 Add R984 , R985 P35 Add R986

For EMI request

For Audio Vendoe suggestion

For AMD request

For +1.8VS_VGA power down sequence

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/06 2009/10/06

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC A5931.

401814

1

C

of

43 43Friday, January 08, 2010

Compal LA-5931P NAUR2 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual