Compal LA-5892P NEW50, Aspire 5740, Aspire 5741, Aspire 5742, LA-5892P NEW70 Schematic

...

1 1

Compal Confidential

2 2

NEW70 / 80 / 90 / 50 <LA-5892P> M/B Schematics Document

Intel Arrandale Processor with DDRIII + Ibex Peak-M

3 3

2010-01-21

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/5/12 2010/04/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Page

NEW70 M/B LA-5892P Schematic

1 49Thursday, January 21, 2010

1.0

ompal Confidential

odel Name NEW70 / 80 / 90 / 50

ile Name : LA-5892P

1 1

AZ0C900200

CB NEW70 LA-5892P

ZZ1

O0000003HM46@

DMI+HDCP LOGO

Fan Control

page 26

Intel

Arrandale (UMA)

Processor

rPGA988A

emory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 10,11

page 4,5,6,7,8,9

DMI x4FDI x8

(UMA)

100MHz

2.7GT/s

2 2

LVDS Conn.

page 22

CRT Conn.

HDMI Conn.

page 24

Level Shift

page 24

page 23

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)

LVDS(UMA)

CRT(UMA)

HDMI(UMA)

100MHz

Intel

Ibex Peak-M

PCH

page 13,14,15,16,17 18,19,20,21

port 2,4 port 1

MINI Card x2

WLAN, 3G

page 26

3 3

RTC CKT. LS-5891P

Power ON/Off CKT.

DC/DC Interface CKT.

LS-5892P

LS-5893P

LAN(GbE)

BCM57780

page 27

RJ45

page 28

Touch Pad

page 31

LPC BUS

ENE KB926

100MHz

1GB/s x4

33MHz

page 30

Int.KBD

BIOS ROM

Power Circuit DC/DC CKT.

LS-5894P

USB conn x3

USB port 0 (sub board) USB Port 1 Left side

Bluetooth Conn

USB port 2 (sub board)

USBx14

HD Audio

3.3V 48MHz

3.3V 24MHz

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

SPI

port 0

SPI ROM x2

page 13

SATA HDD Conn.

page 25

Clock Generator

page 31

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH

48MHZ to CardReader

CMOS Camera

page 29page 39 page 22

100MHz

SATA ODD Conn.

page 25

page 12

USB port 8USB port 11

port 1

Mini card

USB port 12 USB port 13

page 39

HDA Codec

ALC888

page 33

Audio AMP

APA2051

page 34

Int. Speaker

page 34

Card Reader

USB port 9

page 39

4 4

LS-5895P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/5/12 2010/04/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

NEW70 M/B LA-5892P Schematic

2 49Thursday, January 21, 2010

1.0

oltage Rails

Power Plane Description

1 1

2 2

B+

+CPU_CORE

0.75VS 0.75V switched power rail for DDR terminator

+1.05VS

+1.05VS_VTT 1.05V switched power rail (1.05 for AUB CPU) ON OFF OFF

+1.5V 1.5V power rail for DDRIII ON ON OFF

+1.5VS

+1.8VS 1.8V switched power rail

+3VALW 3.3V always on power rail

+3V_LAN 3.3V power rail for LAN ON ON

+3VS

+5VALW

+5VS

+5V 5V power rail for PCH

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

1.05V switched power rail for PCH

1.5V switched power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

S3 S5

N/A N/A N/A

ON OFF OFF

ON ON ON

N/AN/AN/A

OFF

ON ON*

ON*

OFF

ON ON*

OFF

OFFON

ONON

TATE

Full ON

S1(Power On Suspend)

3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

LP_S4#SLP_S5#+VALW+V

LOW

HIGH

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

lock

+VSC

OFF

ON ON

OFF

LOW

OFF

HIGHHIGHHIGH

HIGH

LOWLOWLOW

HIGH

Project ID / Board ID Table for EC-AD channel

Vcc 3.3V +/- 5%

100K +/- 5%Ra/Rc

Rb / Rd V min

0 1 2 3 4 5 6

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

7 NC

BTO Option Table

AD_BID

0 V

V typ

AD_BID

max

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Config

0.1

0.2

0.3

1.0

Not Used

Project IDBoard ID NEW70 NEW80 NEW90

BTO Item BOM Structure

External PCI Devices

Device IDSEL#

REQ#/GNT#

Interrupts

HDMI 3G 9050@ 7080@

HDMI@ 3G@ NEW90 / NEW50 NEW70 / NEW80

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

Ibex SM Bus address

3 3

Device Address

Clock Generator (9LRS3199AKLFT, SLG8SP 587)

DDR DIMM0

DDR DIMM2

1101 0010b

1001 000Xb

1001 010Xb

EC SM Bus2 address

Device

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

0 1 2

4 External USB Port

Ext1 USB

Ext2 USB

3 External USB Port

Ext1 USB Ext3 HS USBExt3 HS USB Ext2 USB

UHCI1

EHCI1

UHCI2

3 4 5 6

UHCI3

UHCI4

EHCI2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UHCI5

UHCI6

2009/08/01 2010/08/01

Camera

Card Reader

SIM CARD SIM CARD

Blue Tooth Blue Tooth

1st Min-Card

2st Min-Card

Compal Secret Data

Deciphered Date

Camera Card Reader

1st Min-Card 2st Min-Card

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

NEW70 M/B LA-5892P Schematic

3 49Thursday, January 21, 2010

1.0

CPU1A

MI_PTX_HR X_N0

D D

MI_PTX_HR X_N1

MI_PTX_HR X_N2

MI_PTX_HR X_N3

MI_PTX_HR X_P0

MI_PTX_HR X_P1

MI_PTX_HR X_P2

H_FDI_INT<15>

MI_PTX_HR X_P3

MI_HTX_PR X_N0 MI_HTX_PR X_N1

D D

MI_HTX_PR X_N2

DMI_HTX_P RX_N3

DMI_HTX_P RX_P0 DMI_HTX_P RX_P1 DMI_HTX_P RX_P2 DMI_HTX_P RX_P3

H_FDI_TXN 0 H_FDI_TXN 1 H_FDI_TXN 2 H_FDI_TXN 3 H_FDI_TXN 4 H_FDI_TXN 5 H_FDI_TXN 6 H_FDI_TXN 7

H_FDI_TXP 0 H_FDI_TXP 1 H_FDI_TXP 2 H_FDI_TXP 3 H_FDI_TXP 4 H_FDI_TXP 5 H_FDI_TXP 6 H_FDI_TXP 7

D D

C C

H_FDI_FSYNC0<15> H_FDI_FSYNC1<15>

H_FDI_LSYNC0<15> H_FDI_LSYNC1<15>

B B

A24

MI_RX#[0]

C23

MI_RX#[1]

B22

MI_RX#[2]

A21

MI_RX#[3]

B24

MI_RX[0]

D23

MI_RX[1]

B23

MI_RX[2]

A22

MI_RX[3]

D24

MI_TX#[0]

G24

MI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD _rPGA,R1P0

CONN@

DMI Intel(R) FDI

EG_ICOMPI

EG_ICOMPO

EG_RCOMPO

EG_RBIAS

EG_RX#[0]

EG_RX#[1]

EG_RX#[2]

EG_RX#[3]

EG_RX#[4]

EG_RX#[5] EG_RX#[6]

P P

EG_RX#[7] EG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

EG_IRCOMP

XP_RBIAS

1 2

1 49.9_0402_ 1%

1 2

3 750_0402_ 1%

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

3.01K_04 02_1% @

3.01K_04 02_1% @ R7

3.01K_04 02_1%

1 2

1 2 1 2

1 2

R11

R11 0_0402_ 5%

0_0402_ 5%

1 2 1 2

R12

R12 0_0402_ 5%

0_0402_ 5%

DMI_PTX_H RX_N[0..3] <15>

DMI_PTX_H RX_P[0..3] <15>

DMI_HTX_P RX_N[0..3] <15> DMI_HTX_P RX_P[0..3] <15>

H_FDI_TXN [0..7] <15>

H_FDI_TXP [0..7] <15>

CPU1E

AP25

SVD1

AL25

SVD2

AL24

SVD3

AL22

SVD4

AJ33

SVD5

AG9

SVD6

M27

SVD7

L28

SVD8

J17

A_DIMM_VREF

H17

B_DIMM_VREF

G25

SVD11

G17

SVD12

E31

RSVD13

E30

RSVD14

CFG0

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG3

@R7

@R8

CFG4

CFG7

H_RSVD1 7_R

H_RSVD1 8_R

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

U9 T9

C1 A3

J29 J28

CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

(CFD Only)

CFD Only)

(

RESERVED

R R

SVD_NCTF_37

R R

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52

RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD58

RSVD_TP_59 RSVD_TP_60

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

SVD32 SVD33

SVD34 SVD35

SVD36

SVD38 SVD39

KEY

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

RSVD64_ R RSVD65_ R

R9 0_0402_ 5%

0_0402_ 5%

R10

R10 0_0402_ 5%

0_0402_ 5%

IC,AUB_CFD _rPGA,R1P0

CONN@

eDP Signals Mapping eDP Singal

eDP_TX0

PEG Singals

PEG_HTX_C_GRX_P15 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1

A A

eDP_TX2 eDP_TX#2 eDP_TX3 eDP_TX#3 eDP_AUX eDP_AUX# eDP_HPD#

PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N12

PEG_GTX_C_HRX_P13

PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12

Lane Reversal

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

CFG0 - PCI-Express Configuration Select

*1:Single PEG 0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

Deciphered Date

Title

Size Document N umber Rev

Date: Sheet of

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port attached to Embedd ed Display Port 0:Enabled; An externa l Display Port device is connected to the Embe dded Display Port

*:Default

Compal Electronics, Inc.

PROCESSOR (1/6) DMI,FDI,PEG

NEW70 M/B LA-5892P Schematic

4 49Thursday, January 21, 20 10

1.0

18 20_0402_ 1%

19 20_0402_ 1%

20 49.9_0402 _1%

21 49.9_0402 _1%

D D

H_PECI<18>

H_PROCH OT#<45>

H_THERM TRIP#<18>

H_PM_SYNC<15>

C C

B B

A A

H_CPUPW RGD<18>

PM_DRAM _PWRGD<15>

H_PW RGD_XDP H_PWRGD_ XDP_R

PLT_RST #<17,21,27,30>

2009/2/4 #414044 DG

Update Rev1.11

+1.05VS_ VTT

R58 49.9_040 2_1% R58 49.9_0402_ 1%

R59 68_0402 _5% R59 68_0402_ 5%

R60 68_0402 _5%@R60 68_0 402_5%@

H_VTTPW RGD<4 3>

U1 / U2 change to SA00000OH00

#425302 CP_S3PowerReduction WhitePaper_Rev0.7

PM_DRAM _PWRGD_R

H_VTTPW RGD

NC7SZ08 P5X_NL_SC70-5

1.1K_040 2_1%

3.01K_04 02_1%

R68

R71

+1.5V_1

R26

1 2

0_0402_ 5%

R36

1 2

0_0402_ 5%

R42 0_0402_ 5%

0_0402_ 5%

R44 0_0402_ 5%

0_0402_ 5%

R47 0_0402_ 5%

0_0402_ 5%

R50

1 2

0_0402_ 5%

H_VTTPW RGD

R55 0_0402_ 5%

0_0402_ 5%

R56

1 2

1.5K_040 2_1%

12 12 12

PAD

R42

1 2

R44

1 2

R47

1 2

R50

1 2

R52 0_0402_ 5%

R55

1 2

R56

+3VALW

R69

1.5K_040 2_1%

R72

750_040 2_1%

_COMP3

_COMP2

_COMP1

_COMP0

KTOCC#_ R

_CATERR #

H_PECI_R

H_PROCH OT#

H_THERM TRIP#_R

H_CPURS T#

H_PM_SYNC_ R

H_CPUPW RGD_1

H_CPUPW RGD_0

PM_DRAM _PWRGD_R

H_VTTPW RGD_R

PLT_RST #_R

R57

R57 750_040 2_1%

750_040 2_1%

H_CATER R# H_PROCH OT# H_CPURS T#

R61

2K_0402 _1%

1 2

+3VALW

Need to check Voltage Level

NC7SZ08 P5X_NL_SC70-5

2009/04/23 Intel CRB 1.55 Update Change R292 to 1.1K_1%, R302 to 3.01K_1%

AT23

AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

IC,AUB_CFD _rPGA,R1P0

CONN@

2009/8/14 change back to 2K

H_VTTPW RGD_R

R62

1K_0402 _1%

H_VTTPW RGD

CPU1B

OMP3

OMP2

OMP1

OMP0

KTOCC#

ATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

MISC THERMAL

CLOCKS

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CLK#

CLK_ITP

CLK_ITP#

EG_CLK

EG_CLK#

PLL_REF_SSCLK

PLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY#

PREQ#

TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+1.05VS_ VTT

Issued Date

CLK

TCK

TDI

A16 B16

AR30 AT30

E16 D16

A18 A17

SM_RCOM P_0

AL1

SM_RCOM P_1

AM1

SM_RCOM P_2

AN1

PM_EXTT S#0

AN15

PM_EXTT S#1_R

AP15

XDP_PRD Y#

AT28

XDP_PRE Q#

AP27

XDP_TCL K

AN28

XDP_TMS

AP28

XDP_TRS T#

AT27

XDP_TDI_R

AT29

XDP_TDO _R

AR27

XDP_TDI_M

AR29

XDP_TDO _M

AP29

XDP_DBR #_R

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

PBTN_OU T#<15,21,30 >

C65

0.1U_040 2_16V4Z

LK_CPU_ BCLK <18>

C C

LK_CPU_ XDP

LK_CPU_ XDP#

1 2

R28 100K_04 02_5%

R46 0_0402_ 5% R46 0_0402_ 5%

1 2

XDP_OBS 0 XDP_OBS 1 XDP_OBS 2 XDP_OBS 3 XDP_OBS 4 XDP_OBS 5 XDP_OBS 6 XDP_OBS 7

2009/2/4 Delete dampling resistor for

power noise and Layout sp ace issue

R65

R65 1K_0402 _5%

1K_0402 _5%

H_CPUPW RGD

2009/08/ 01 2010/08/ 01

1 2 1 2

R66 0 _0402_5%R 66 0_0402 _5%

SMB_DAT A_S3<21> SMB_CLK _S3<21>

Compal Secret Data

LK_CPU_ BCLK# <18>

LK_CPU_ DMI <14>

LK_CPU_ DMI# <14>

LK_CPU_ DP < 14>

C C

LK_CPU_ DP# <14>

SM_DRAM RST# <10>

R32 10K_040 2_5% R32 10K_040 2_5%

1 2

R34 10K_040 2_5% R34 10K_040 2_5%

1 2

R35 0_0402_ 5% R35 0_0 402_5%

1 2

SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2

XDP_PRE Q# XDP_PRD Y#

XDP_OBS 0 XDP_OBS 1

XDP_OBS 2 XDP_OBS 3

XDP_OBS 4 XDP_OBS 5

XDP_OBS 6 XDP_OBS 7

H_PW RGOOD_R PBTN_OU T#_XDP

H_PW RGD_XDP

XDP_TCL K

Deciphered Date

R38 100_040 2_1% R3 8 100 _0402_1%

1 2

R39 24.9_040 2_1% R39 24.9_0402 _1%

1 2

R40 130_040 2_1%<BOM S tructure>R40 130_04 02_1%<BOM Structure>

1 2

XDP_DBR ESET#

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

+1.05VS_ VTT

XDP Connector

JP5

GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

009/08/14 #42530 2 CP_S3PowerReduction WhitePaper_Rev0 .9

PM_EXTT S#0_1 <10,11>

XDP_DBR ESET# <15,21>

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

SAMTE_B SH-030-01-L-D-ACONN@

1.05VS_V TT

XDP_PRD Y# XDP_TMS XDP_TDI_R XDP_PRE Q# XDP_TCL K

XDP_TRS T#

XDP_TDI_R XDP_TDI

XDP_TDI_M XDP_TDO _R

R27 51_0402 _5%@R27 51_0402_5 %@

1 2

R29 51_0402 _5%@R29 51_0402_5 %@

1 2

R30 51_0402 _5%@R30 51_0402_5 %@

1 2

R31 51_0402 _5%@R31 51_0402_5 %@

1 2

R33 51_0402 _5%@R33 51_0402_5 %@

1 2

R37 51_0402 _5% R37 51_0402 _5%

1 2

R41 0_0402_ 5% R41 0_0 402_5%

1 2

R43 0_0402_ 5%@R43 0_0 402_5%@

1 2

R45

R45 0_0402_ 5%

0_0402_ 5%

1 2

R48 0_0402_ 5%

1 2

R49 0_0402_ 5%

JTAG MAPPING

Scan Chain (Default)

CPU Only

GMCH Only

GND1

4 6 8

GND3

10 12 14

GND5

16 18 20

GND7

22 24 26

GND9

28 30 32

GND11

34 36 38

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

Title

Size Document N umber Rev

Date: Sheet of

CLK_CPU _XDP

CLK_CPU _XDP#

42 44

H_RESET #_R

XDP_DBR ESET#

48 50

XDP_TDO

XDP_TRS T#

XDP_TDI

XDP_TMS

58 60

PROCESSOR (2/6) CLK,JTAG

NEW70 M/B LA-5892P Schematic

STUFF -> R653, R657, R662 NO STUFF -> R655, R660

STUFF -> R653, R655 NO STUFF -> R657, R660, R662

STUFF -> R660, R662 NO STUFF -> R653, R655, R657

R63

R63 1K_0402 _5%

1K_0402 _5%

1 2 1 2

R64 0 _0402_5%@R64 0 _0402_5%@

1 2

R67 1K_ 0402_5%R67 1K_ 0402_5%

1 2

R70 51_ 0402_5%R7 0 51_0402_5%

Compal Electronics, Inc.

H_CPURS T# PLT_RST #H_RESET #_R

5 49Thursday, January 21, 20 10

XDP_TDOXDP_TDO _M

+1.05VS_ VTT

+3VS

+1.05VS_ VTT

1.0

CPU1C

A10

C10

B10

D10

E10

F10

H10

G10

AH5 AF5 AK6 AK7 AF6

AG5

AJ7 AJ6

AJ10

AJ9

AL10

AK12

AK8

AL7

AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

J10

M6 M8

K8 N8 P9

L9 L6

A_DQ[0]

A_DQ[1]

A_DQ[2] A_DQ[3]

S S

A_DQ[4] A_DQ[5]

S SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DR_A_D[0 ..63]<10>

DR_A_DM [0..7]<10>

DR_A_DQ S#[0..7]<10>

DR_A_DQ S[0..7]<10>

DR_A_MA [0..15]< 10>

DR_A_D0

DR_A_D1

D D

C C

B B

DDR_A_B S0<10> DDR_A_B S1<10> DDR_A_B S2<10>

DDR_A_C AS#<10> DDR_A_R AS#<10>

DDR_A_W E#< 10>

DR_A_D2 DR_A_D3

D D

DR_A_D4 DR_A_D5

D D

DR_A_D6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63

DDR_A_B S0 DDR_A_B S1 DDR_A_B S2

DDR_A_C AS# DDR_A_R AS# DDR_A_W E#

A_CK[0]

A_CK#[0]

A_CKE[0]

A_CK[1]

A_CK#[1] A_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_D M0 DDR_A_D M1 DDR_A_D M2 DDR_A_D M3 DDR_A_D M4 DDR_A_D M5 DDR_A_D M6 DDR_A_D M7

DDR_A_D QS#0 DDR_A_D QS#1 DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7

DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7

DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_M A10 DDR_A_M A11 DDR_A_M A12 DDR_A_M A13 DDR_A_M A14 DDR_A_M A15

DR_A_CL K0 <10> DR_A_CL K0# <10>

DR_A_CK E0 <10>

DR_A_CL K1 <10>

DR_A_CL K1# <10>

DR_A_CK E1 <10>

DDR_A_C S0# <10> DDR_A_C S1# <10>

DDR_A_O DT0 <1 0> DDR_A_O DT1 <1 0>

DR_B_D[0 ..63]<11>

DR_B_DM [0..7]<11>

DR_B_DQ S#[0..7]<11>

DR_B_DQ S[0..7]<11>

DR_B_MA [0..15]<11>

DR_B_D0

DR_B_D1

DR_B_D2

DR_B_D3

DR_B_D4

DR_B_D5 DR_B_D6

D D

DR_B_D7 DR_B_D8

D D

DR_B_D9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39 DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63

DDR_B_B S0<11> DDR_B_B S1<11> DDR_B_B S2<11>

DDR_B_C AS#<11> DDR_B_R AS#<11>

DDR_B_W E#< 11>

DDR_B_BS0 DDR_B_B S1 DDR_B_B S2

DDR_B_C AS# DDR_B_R AS# DDR_B_W E#

AF3

AG1

AK1 AG4 AG3

AH4

AK3

AK4 AM6

AN2

AK5

AK2 AM4 AM3

AP3

AN5

AT4

AN6

AN4

AN3

AT5

AT6

AN7

AP6

AP8

AT9

AT7

AP9

AR10

AT10

AB1

AC5

AC6

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3

J3 G1 G5

L3 M1

K5 K4

AJ3

AJ4

CPU1D

B_DQ[0]

B_DQ[1]

B_DQ[2]

B_DQ[3]

B_DQ[4]

B_DQ[5] B_DQ[6]

S S

B_DQ[7] B_DQ[8]

S SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

B_CK[0]

B_CK#[0]

B_CKE[0]

B_CK[1]

B_CK#[1]

B_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_D M0 DDR_B_D M1 DDR_B_D M2 DDR_B_D M3 DDR_B_D M4 DDR_B_D M5 DDR_B_D M6 DDR_B_D M7

DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7

DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7

DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_M A14 DDR_B_M A15

DR_B_CL K0 <11>

DR_B_CL K0# <11>

DR_B_CK E0 <11>

DR_B_CL K1 <11> DR_B_CL K1# <11>

D D

DR_B_CK E1 <11>

DDR_B_C S0# <11> DDR_B_C S1# <11>

DDR_B_O DT0 <1 1> DDR_B_O DT1 <1 1>

IC,AUB_CFD _rPGA,R1P0

CONN@

A A

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

Deciphered Date

IC,AUB_CFD _rPGA,R1P0

CONN@

Compal Electronics, Inc.

Title

PROCESSOR (3/6) DDRIII

Size Document N umber Rev

Date: Sheet of

Compal Electronics, Inc.

NEW70 M/B LA-5892P Schematic

6 49Thursday, January 21, 20 10

1.0

CPU1F

CPU_CORE

8A Continuous 18A

AG35

CC1

AG34

CC2

AG33

CC3

AG32

CC4

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27

AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26

AA35

AA34

AA33

AA32

AA31

AA30

AA29

AA28

AA27

AA26

V V

CC5 CC6

V V

CC7

CC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

WW15 MOW

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

TT0_1

TT0_2 TT0_3

TT0_4

V V

TT0_5 TT0_6

V V

TT0_7

TT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VTTVID1

G15

H_VTTVID1 = low, 1.1V

H_VTTVID1 = high, 1.05V

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

10U_0805_6.3V6M

C82

330U_D2E_2.5VM_R6M

22U_0805_6.3V6M

C91

C92

22U_0805_6.3V6M

PAD

IMVP_IMON <45>

R92 0_0402_5% R92 0_0402_5%

1 2

R93 0_0402_5% R93 0_0402_5%

1 2

R95 0_0402_5% R95 0_0402_5%

10U_0805_6.3V6M

+1.05VS_VTT

20090915 Modify

T14

1 2

10U_0805_6.3V6M

C83

330U_D2E_2.5VM_R6M

+1.05VS_VTT

10U_0805_6.3V6M

H_PSI# <45>

CPU_VID0 <45> CPU_VID1 <45> CPU_VID2 <45> CPU_VID3 <45> CPU_VID4 <45> CPU_VID5 <45> CPU_VID6 <45> H_DPRSLPVR <45>

VTT Rail

Auburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V

1 2

R91 100_0402_1%

VCCSENSE VSSSENSE

1 2

R94 100_0402_1%

VTT_SENSE <43>

R94 100_0402_1%

1.05VS_VTT

10U_0805_6.3V6M

CSC (Current Sense Configuration) 8/25

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

H_DPRSLPVR

H_PSI#

R73 1K_0402_1% R73 1K_0402_1% R74 1K_0402_1%@R74 1K_0402_1%@

R75 1K_0402_1% R75 1K_0402_1% R76 1K_0402_1%@R76 1K_0402_1%@

R77 1K_0402_1% R77 1K_0402_1% R78 1K_0402_1%@R78 1K_0402_1%@

R79 1K_0402_1%@R79 1K_0402_1%@ R80 1K_0402_1% R80 1K_0402_1%

R81 1K_0402_1%@R81 1K_0402_1%@ R82 1K_0402_1% R82 1K_0402_1%

R83 1K_0402_1% R83 1K_0402_1% R84 1K_0402_1%@R84 1K_0402_1%@

R85 1K_0402_1%@R85 1K_0402_1%@ R86 1K_0402_1% R86 1K_0402_1%

R87 1K_0402_1% R87 1K_0402_1% R88 1K_0402_1%@R88 1K_0402_1%@

R89 1K_0402_1%@R89 1K_0402_1%@ R90 1K_0402_1% R90 1K_0402_1%

+CPU_CORE

VCCSENSE <45> VSSSENSE <45>

1 2 1 2

CPU_CORE

10U_0805_6.3V6M

+1.05VS_VTT

+CPU_CORE

C105

330U_D2E_2.5VM_R6M

10U_0805_6.3V6M

C74

(Place these capacitors between inductor and socket on Bottom)

+CPU_CORE

C84

10U_0805_6.3V6M

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

C106

330U_D2E_2.5VM_R6M

TOP side (under inductor)

10U_0805_6.3V6M

22U_0805_6.3V6M

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

C76

10U_0805_6.3V6M

C85

C84

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M

C94

C98

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M

C99

22U_0805_6.3V6M

330U_D2E_2.5VM_R6M

C77

C85

C86

10U_0805_6.3V6M

C94

22U_0805_6.3V6M

C100

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

C272

C,uF

4X470uF 4m ohm/4

16X22uF

16X10uF 3m ohm/16

C78

10U_0805_6.3V6M

C87

C86

C95

C96

C101

C273

330U_D2E_2.5VM_R6M

ESR, mohm

3m ohm/12

C87

22U_0805_6.3V6M

C96

22U_0805_6.3V6M

C102

10U_0805_6.3V6M

C79

C88

10U_0805_6.3V6M

C97

22U_0805_6.3V6M

C103

22U_0805_6.3V6M

C275

330U_D2E_2.5VM_R6M

Stuffing Option

C80

10U_0805_6.3V6M

C89

22U_0805_6.3V6M

C104

2X470uF

10U_0805_6.3V6M

C81

Security Classification

IC,AUB_CFD_rPGA,R1P0

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR (4/6) PWR,Bypass

NEW70 M/B LA-5892P Schematic

7 49Thursday, January 21, 2010

1.0

VGFX_CO RE

110

107

D D

330U_D2 E_2.5VM_R6M

C C

B B

107

22U_080 5_6.3V6M

111

112

10U_080 5_6.3V6M

+1.05VS_ VTT

C122

+1.05VS_ VTT

C125

10U_080 5_6.3V6M

113

C123

22U_080 5_6.3V6M

C126

22U_080 5_6.3V6M

CPU1G

AT21

AXG1

AT19

AXG2

AT18

AXG3

AT16

AXG4

AR21

AXG5

AR19

AXG6

AR18

AXG7

AR16

AXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD _rPGA,R1P0

CONN@

15A

GRAPHICS

FDI PEG & DMI

FX_VID[0]

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFXVR_E N

AR25

GFXVR_D PRSLPVR_R

AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

1U_0402 _6.3V4Z

C114

1U_0402 _6.3V4Z

+1.05VS_ VTT

C127

+1.8VS_V CCSFR

C128

AXG_SENSE

SSAXG_SENSE

SENSE

LINES

G GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GRAPHICS VIDs

POWER

DDR3 - 1.5V RAILS

1.1V1.8V

0.6A

CC_AXG_ SENSE <44>

V V

SS_AXG_ SENSE < 44>

FXVR_VID_ 0 <44> GFXVR_V ID_1 <44 > GFXVR_V ID_2 <44 > GFXVR_V ID_3 <44 > GFXVR_V ID_4 <44 > GFXVR_V ID_5 <44 > GFXVR_V ID_6 <44 >

R97 0_0402_ 5% R97 0_0 402_5%

1 2

1U_0402 _6.3V4Z

C115

C116

1U_0402 _6.3V4Z

+1.05VS_ VTT

C124

10U_080 5_6.3V6M

C127

22U_080 5_6.3V6M

2.2U_060 3_6.3V4Z

C130

C129

1U_0402 _6.3V4Z

C118

C117

1U_0402 _6.3V4Z

C131

4.7U_080 5_10V4Z

22U_080 5_6.3V6M

C119

GFXVR_E N

PD 470ohm 20091105

GFXVR_E N < 44> GFXVR_D PRSLPVR <4 4> GFXVR_IMON < 44>

C120

22U_080 5_6.3V6M

R99

R99 0_0805_ 5%

0_0805_ 5%

1 2

C132

22U_080 5_6.3V6M

1 2

R167 470_0402_5 %

Reserved for +1.5V to +1.5V_1

C121

C121 330U_D2 E_2.5VM_R6M

330U_D2 E_2.5VM_R6M

112

JUMP_43 X118@J1JUMP_43 X118@

112

JUMP_43 X118@J3JUMP_43 X118@

Reserved for +1.5VS to +1.5V_1

11/03 add four 0.1u 0402 Intel suggest

+1.5V+1.5V_1

1 2

C670 0.1U_0402_1 6V4ZC670 0.1U_0402_1 6V4Z

1 2

C671 0.1U_0402_1 6V4ZC671 0.1U_0402_1 6V4Z

1 2

C672 0.1U_0402_1 6V4ZC672 0.1U_0402_1 6V4Z

1 2

C673 0.1U_0402_1 6V4ZC673 0.1U_0402_1 6V4Z

+1.8VS

+1.5V+1.5V_1

+1.5VS

A A

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR (5/6) PWR

Size Document N umber Rev

Custom

NEW70 M/B LA-5892P Schematic

Date: Sheet of

Compal Electronics, Inc.

8 49Thursday, January 21, 20 10

1.0

CPU1H

AT20

SS1

AT17

SS2

AR31

SS3

AR28

SS4

AR26

SS5

AR24

SS6

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

SS7 SS8

V V

SS9 SS10

V VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

SS81

SS82

SS83

SS84

SS85

SS86

SS87 SS88

V V

SS89 SS90

V VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

CPU1I

K27

SS161

SS162

SS163

SS164

J32

SS165

J30

SS166

J21

SS167

J19

SS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

VSS179

VSS180

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

VSS185

VSS186

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

VSS202

VSS203

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

VSS208

VSS209

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

VSS227

VSS228

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

H_NCTF1 H_NCTF2

H_NCTF6 H_NCTF7

PAD

IC,AUB_CFD _rPGA,R1P0

CONN@

A A

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

IC,AUB_CFD _rPGA,R1P0

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR (6/6) VSS

NEW70 M/B LA-5892P Schematic

9 49Thursday, January 21, 20 10

1.0

IMMA VREFDQ M1 Circuit

1.5V

101

1K_0402_1%

R104

D D

1K_0402_1%

C C

Layout Note: Place near JDIMM1

B B

C137

10U_0805_6.3V6M

Layout Note: Place near JDIMM1.203 & JDIMM1.204

A A

1U_0402_6.3V4Z

1K_0402_1%

DIMMA & DIMMB VREFCA circuit

+1.5V

R106

R107

1K_0402_1%

+1.5V

10U_0805_6.3V6M

C138

+0.75VS

1U_0402_6.3V4Z

C150

C151

DIMM_VREFDQA

104

+DIMM_VREFCA

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0805_6.3V6M

C140

C141

10U_0805_6.3V6M

1U_0402_6.3V4Z

C153

C141

C139

10U_0805_6.3V6M

C152

1U_0402_6.3V4Z

10U_0805_6.3V6M

C154

10U_0805_6.3V6M

DR_A_DQS#[0..7]<6>

DR_A_D[0..63]<6>

DR_A_DM[0..7]<6>

DR_A_DQS[0..7]<6>

DR_A_MA[0..15]<6>

#425302 CP_S3PowerReduction WhitePaper_Rev1.0

SM_DRAMRST#<5>

C142

0.1U_0402_16V4Z

RST_GATE<18>

C143

0.1U_0402_16V4Z

C144

0.1U_0402_16V4Z

RST_GATE

R102

R102 0_0402_5%

0_0402_5%

1 2

0.1U_0402_16V4Z

C145

C146

DIMM_VREFDQA

+1.5V

R103

1K_0402_1%

DIMM_DRAMRST#

Q2 BSS138LT1G_SOT23-3

BSS138LT1G_SOT23-3

C617

1 2

0.047U_0402_16V7K

C147

@+C147

330U_2.5V_M_R15

M1 Circuit

0.1U_0402_16V4Z

DIMM_DRAMRST# <11>

DIMM_VREFDQA

134

2.2U_0603_6.3V4Z

Issued Date

133

2.2U_0805_16V4Z

DDR_A_CKE0<6>

DDR_A_BS2<6>

DDR_A_CLK0<6> DDR_A_CLK0#<6>

DDR_A_BS0<6>

DDR_A_WE#<6>

DDR_A_CAS#<6> DDR_A_ODT0 <6>

DDR_A_CS1#<6>

+3VS

C148

2009/08/01 2010/08/01

Security Classification

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DR_A_D0

D D

DR_A_D1

DR_A_DM0

DR_A_D2

DR_A_D3

DR_A_D8

D D

DR_A_D9

DR_A_DQS#1

DR_A_DQS1

DR_A_D10 DR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# DDR_A_ODT0

DDR_A_MA13 DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R109 10K_0402_5% R109 10K_0402_5%

1 2

C149

R110

0.1U_0402_16V4Z

1.5V

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

R110

10K_0402_5%

Compal Secret Data

203

205

Deciphered Date

11 13 15 17 19 21 23 25 27 29 31 33 35

39 41

45 47 49 51 53 55 57 59

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

DIMM1

REF_DQ

SS2

SS4

V D

SS5

SS7

Q8 Q9

SS9

V D

QS#1 QS1

D V

SS11

Q10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

FOX_AS0A626-U8RN-7F

SS1

D D

SS3

QS#0

QS0

SS6 D D

SS8

Q12

Q13

D SS10

ESET#

SS12 D

Q14

DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15

A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2 4

8 10 12 14 16

20 22 24 26 28

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

88 90

94 96

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

C135

1.5V

DR_A_D4

DR_A_D5

DR_A_DQS#0

DR_A_DQS0

DR_A_D6

DR_A_D7

DR_A_D12

D D

DR_A_D13

DR_A_DM1

IMM_DRAMRST#

DR_A_D14 DR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_A_CKE1

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_CS0#

DDR_A_ODT1

DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

+0.75VS

DDR_A_CKE1 <6>

DDR_A_CLK1 <6> DDR_A_CLK1# <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_A_CS0# <6>

DDR_A_ODT1 <6>

R108 0_0402_5% R108 0_0402_5%

1 2

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,11>

D_CK_SDATA <11,12> D_CK_SCLK <11,12>

DDR3 SO-DIMM A

Change to Reverse Type

8mm High

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

NEW70 M/B LA-5892P Schematic

+DIMM_VREFCA

C136

0.1U_0402_16V4Z

10 49Thursday, January 21, 2010

1.0

008/9/8 #400755

DR_B_DQS#[0..7]<6>

DR_B_D[0..63]<6>

DR_B_DM[0..7]<6>

DR_B_DQS[0..7]<6>

DR_B_MA[0..15]<6>

D D

IMMB VREFDQ M1 Circuit

+1.5V

R113

1K_0402_1%

R114

1K_0402_1%

C C

Layout Note: Place near JDIMM2

+1.5V

B B

A A

C159

10U_0805_6.3V6M

1U_0402_6.3V4Z

C160

10U_0805_6.3V6M

Layout Note: Place near JDIMM2.203 & JDIMM2.204

+0.75VS

C170

C171

1U_0402_6.3V4Z

10U_0805_6.3V6M

C162

161

161 C

10U_0805_6.3V6M

1U_0402_6.3V4Z

C172

C173

1U_0402_6.3V4Z

+DIMM_VREFDQB

10U_0805_6.3V6M

C163

C164

10U_0805_6.3V6M

C174

10U_0805_6.3V6M

2 Calpella Clark sfield DDR3 SO-DIMM VREFDQ Platform D

esign Guide Change Details

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

0.1U_0402_16V4Z

C165

C166

0.1U_0402_16V4Z

C167

C168

0.1U_0402_16V4Z

C169

C169 330U_2.5V_M_R15

330U_2.5V_M_R15

DIMM_VREFDQB

1 Circuit

C155

2.2U_0805_16V4Z

+3VS

C175

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

DDR_B_CKE0<6>

DDR_B_BS2<6>

DDR_B_CLK0<6> DDR_B_CLK0#<6>

DDR_B_BS0<6>

DDR_B_WE#<6>

DDR_B_CAS#<6>

DDR_B_CS1#<6>

DIMM_VREFDQB

C156

R116 10K_0402_5%R116 10K_0402_5%

1 2

R117 10K_0402_5%R117 10K_0402_5%

C176

0.1U_0402_16V4Z

DR_B_D0

DR_B_D1

DR_B_DM0

DR_B_D2 DR_B_D3

DR_B_D8

DR_B_D9

DR_B_DQS#1

DR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_CKE0

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

1.5V

DIMM2

REF_DQ

SS2

SS4

SS5

SS7

SS9

QS#1

QS1

VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F CONN@

CONN@

D D

QS#0

D D

V D D

SS10

ESET#

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

SS1

SS3

QS0 SS6

SS8 Q12 Q13

A15 A14

A11

CK1

BA1

S0#

SCL

1.5V

DR_B_D4

Q4 Q5

Q6 Q7

A6 A4

A2 A0

6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DR_B_D5

DR_B_DQS#0

DR_B_DQS0

DR_B_D6 DR_B_D7

DR_B_D12

DR_B_D13

DR_B_DM1

IMM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23DDR_B_D18

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_B_CKE1

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLK

+0.75VS

IMM_DRAMRST# <10>

DDR_B_CKE1 <6>

DDR_B_CLK1 <6> DDR_B_CLK1# <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_B_CS0# <6> DDR_B_ODT0 <6>

DDR_B_ODT1 <6>

R115 0_0402_5%R115 0_0402_5%

1 2

C157

2.2U_0603_6.3V4Z

PM_EXTTS#0_1 <5,10>

D_CK_SDATA <10,12> D_CK_SCLK <10,12>

DDR3 SO-DIMM B

+DIMM_VREFCA

C158

0.1U_0402_16V4Z

Reverse Type 4mm High

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/01 2010/08/01

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

NEW70 M/B LA-5892P Schematic

11 49Thursday, January 21, 2010

1.0

1.05VS_V TT

1 1

FBMA-L11 -201209-221LMA 30T_0805

177

10U_080 5_10V4Z

CLK_1.05 VS

178

0.1U_040 2_16V4Z

179

0.1U_040 2_16V4Z

47P_040 2_50V8J

180

47P_040 2_50V8J

0090915 Add for 3G team 20090915 Add for 3G team

3VS

10U_080 5_10V4Z

181

+1.5VS

FBMA-L11 -201209-221LMA 30T_0805

C185

C185 10U_080 5_10V4Z

10U_080 5_10V4Z

CLK_3VS

0.1U_040 2_16V4Z

182

10U_080 5_10V4Z

+CLK_1.5 VS

C186

0.1U_040 2_16V4Z

183

0.1U_040 2_16V4Z

C187

47P_040 2_50V8J

184

C188

0.1U_040 2_16V4Z

47P_040 2_50V8J

C189

C32

47P_040 2_50V8J

20090915 Add for 3G team

47P_040 2_50V8J

C33

C34

2 2

CLK_BUF _DREF_96M

CLK_BUF _DREF_96M#<14>

CLK_BUF _PCIE_SATA<14> CLK_BUF _PCIE_SATA#<14>

CLK_BUF _CPU_DMI<14> CLK_BUF _CPU_DMI#<14>

3 3

+3VS

Silego Have Internal Pull-Up

R121 10K_0402_ 5% R1 21 10K_040 2_5%

1 2

CLK_BUF _DREF_96M#

CLK_BUF _PCIE_SATA CLK_BUF _PCIE_SATA#

CLK_BUF _CPU_DMI CLK_BUF _CPU_DMI#

+CLK_1.0 5VS

H_STP_C PU#

IDT Have Internal Pull-Down

R124 10K_0402_ 5% R1 24 10K_040 2_5%

1 2

REF_0/CP U_SEL

CPU_1PIN 30 CPU_0

(Default)

4 4

0 133MHz

100MHz 100MHz

133MHz

+CLK_3V S

+CLK_1.5 VS

H_STP_C PU#

Clock Generator

VDD_USB_48

VSS_48M

DOT_96

DOT_96#

VDD_27

27MHZ

27MHZ_SS

USB_48

VSS_27M

SATA

SATA#

VSS_SRC

SRC_1

SRC_1#

VDD_SRC_IO

CPU_STOP#

TGND

SLG8SP5 87VTR_QFN32_ 5X5

IDT SA00003HR00

REF_0/CPU_SEL

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

CKPWRGD/PD#

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

SCL SDA

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

+CLK_3V S

D_CK_SC LK D_CK_SD ATA REF_0/CP U_SEL

CLK_XTA L_IN CLK_XTA L_OUT

CK505_P WRGD

CLK_BUF _CPU_BCLK CLK_BUF _CPU_BCLK#

R118 33_0402_5 % R118 33_0402_5%

+CLK_1.0 5VS +CLK_1.5 VS

1 2

D_CK_SC LK <10 ,11>

D_CK_SD ATA <10,1 1> CLK_BUF _ICH_14M <14>CLK_BUF _DREF_96M<14>

CLK_BUF _CPU_BCLK <14> CLK_BUF _CPU_BCLK# <14>

IDT: 9LRS3199AKLFT, SA000030P00

SILEGO: SLG8SP587V(WF), SA00002XY10

Low Power:

+3VS

IDT: 9LVS3199AKLFT, SA00003HR00

R120

Realtek: RTM890N-631-GRT, SA00003HQ00

+3VS

R123

4.7K_040 2_5%

1 2

PCH_SMB DATA<14,21,26>

PCH_SMB CLK<14,2 1,26>

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 3

D_CK_SD ATA

Q4 2N7002_ SOT23

2N7002_ SOT23

+3VS

R125

4.7K_040 2_5%

1 2

Q6 2N7002_ SOT23

2N7002_ SOT23

2009/08/ 01 2010/08/ 01

+3VS

D_CK_SC LK

Compal Secret Data

Deciphered Date

Change to 5x3.2

R120 10K_040 2_5%

10K_040 2_5%

1 2

CK505_P WRGD

2N7002_ SOT23

CLK_XTA L_IN

14.31818 MHZ 20PF 7A143 00003

CLK_XTA L_OUT

R122

R122 0_0402_ 5%

0_0402_ 5%

1 2

CLK_ENA BLE# <45 >

27P_040 2_50V8J

Title

Size Document N umber Rev

Custom

NEW70 M/B LA-5892P Schematic

Date: Sheet of

VGATE <15,45>

C190

Y1 Change to SJ100009R00 20091117

C191

Compal Electronics, Inc.

Clock Generator (CK505)

12 49Thursday, January 21, 2010

1.0

CH_RTCR ST#

RTCVCC

lose to RAM door

D D

RTCVCC

close to RAM door

1 2

126

R 20K_040 2_1%

20K_040 2_1%

1 2

127

10K_060 3_5%

1U_0603 _10V6K

1 2

132

20K_040 2_1%

1 2

R130 10K_060 3_5%

10K_060 3_5%

C194

1U_0603 _10V6K

1 2

193

HDA for AUDIO

+3VS

R137

R137 1K_0402 _5%

1K_0402 _5%

1 2

R138

C C

B B

A A

R138 10K_040 2_5%

10K_040 2_5%

If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.

ME_OVER RIDE<30>

100K_04 02_5%

GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on th e rising edge of PW ROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted af ter manfacturing/ debug.

PCH_JTA G_TMS

PCH_JTA G_TDO

PCH_JTA G_TDI

PCH_JTA G_RST#

RC Delay 18~25mS

32.768KH Z_12.5PF_Q13M C14610002

CH_SRTC RST#

RC Delay 18~25mS

@R130

INTVRMEN - Integrated SUS

1.1V VRM Enable High - Enable Internal VRs

PCH_SPK R

Have internal PD

SERIRQ

PCH_GPIO3 3#

2N7002_ SOT23

R140

2N7002_ SOT23

R151 51_0402_5 %@R1 51 51_040 2_5%@

1 2

R478 200_0402_ 1%R478 200_0402_ 1%

1 2

R479 100_0402_ 5% R479 100_04 02_5%

1 2

R152 51_0402_5 %@R1 52 51_040 2_5%@

1 2

R480 200_0402_ 1%R480 200_0402_ 1%

1 2

R481 100_0402_ 5% R481 100_04 02_5%

1 2

R153 51_0402_5 %@R1 53 51_040 2_5%@

1 2

R482 200_0402_ 1%R482 200_0402_ 1%

1 2

R483 100_0402_ 5% R483 100_04 02_5%

1 2

R154 51_0402_5 %@R1 54 51_040 2_5%@

1 2

R484 20K_0402_ 5% R4 84 20K_040 2_5%

1 2

R485 10K_0402_ 5% R4 85 10K_040 2_5%

1 2

modify to 330K

HDA_BITCL K_AUDIO<33>

HDA_SYNC_ AUDIO<33>

HDA_RST _AUDIO#<33>

HDA_SDO UT_AUDIO<33>

18P_040 2_50V8J

+RTCVCC

R133 1M_0402_5 % R133 1M_04 02_5%

R134 330K_0402 _1% R1 34 330K_04 02_1%

PCH_SPI_C LK_1

PCH_SPI_C S0#

PCH_SPI_M ISO_1 PCH_SPI_M ISO

+1.05VS

+3VALW

192

10M_040 2_5%

CH_RTCX 1

CH_RTCX 2

195

1 2

R135 33_0402_5%

1 2

R131 33_0402_5%

PCH_SPK R<33>

1 2

R136 33_0402_5%

HDA_SDIN0<33>

1 2

R139 33_0402_5%

GPIO33 can not pull down (manufacturing environments)

PCH_JTA G_TCK<21>

PCH_JTA G_TMS< 21>

PCH_JTA G_TDI<2 1>

PCH_JTA G_TDO<2 1>

PCH_JTA G_RST#<21>

R142 0_0402_5% R1 42 0_0402 _5%

1 2

R143 15_0402_5 % R143 15 _0402_5%

1 2

PAD

R145 15_0402_5 % R145 15 _0402_5%

1 2

R147 33_0402_5 % R147 33_040 2_5%

1 2

20090923 Update

2008 Intel MOW36/MOW50

TDO: Reserved on ES1 Sample Mount R516, R517 on ES2 Sample

MP mount R689, R690, R691, R692 and remove others

128

CH_RTCR ST#

PCH_SRT CRST#

SM_INTRUD ER#

PCH_INTVR MEN

HDA_BITCL K_PCH

HDA_SYNC_ PCH

PCH_SPK R

HDA_RST _PCH#

HDA_SDO UT_PCH

PCH_GPIO33 #

PCH_JTA G_TCK

PCH_SPI_C LKP CH_SPI_CLK

PCH_SPI_C S0#_R

PCH_SPI_C S1#

PCH_SPI_M OSIPCH_SPI_M OSI_1

+3VS

1 Change to mini type

20091102

EV1.0

B13 D13

C14

D17

A16

A14

A30

D29

C30

G30

F30

E32

F32

B29

H32

J30

BA2

AV3

AY3

AY1

AV1

PCH_SPI_M OSI

enable iTPM: SPI_MOSI High

PCH_JTA G_TCK

CRB 1.0 Change to 4.7K

R155 3.3K_0402_ 5% R155 3.3K_0402_ 5%

1 2

R156 3.3K_0402_ 5% R156 3.3K_0402_ 5%

1 2

TCX1

TCX2

TCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

TRST#

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

IBEXPEAK-M _FCBGA107

R157 1K_040 2_5%@R157 1K_ 0402_5%@

1 2

R158 4.7K_04 02_5% R158 4.7 K_0402_5%

1 2

LPC

RTCIHDA

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

SPI JTAG

PCH_SPI_C S0# SPI_WP 1# SPI_HOLD1 #

WH0 / LAD0

WH1 / LAD1 WH2 / LAD2

F F

WH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

+3VS

1 3 7 4

SPI ROM Footprint 200mil

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

PC_AD0

D33

PC_AD1

B33

PC_AD2

C32

PC_AD3

A32

PC_FRAM E#

C34

A34 F34

SERIRQ

AB9

SATA_DT X_C_PRX_N0

AK7

SATA_DT X_C_PRX_P0

AK6

SATA_PT X_DRX_N0

AK11

SATA_PT X_DRX_P0

AK9

SATA_DT X_C_PRX_N1

AH6

SATA_DT X_C_PRX_P1

AH5

SATA_PT X_DRX_N1

AH9

SATA_PT X_DRX_P1

AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

U18

CS# WP# HOLD# GND

MX25L16 05DM2I-12G SOP 8P

SA00002 1A00

Deciphered Date

2/10 SATA2, SATA3 not support on HM55

SATA_CO MP

SATA_LE D#

VCC

SCLK

PC_AD0 <30 >

L L

PC_AD1 <30 >

PC_AD2 <30 >

PC_AD3 <30 >

LPC_FRA ME# <30 >

SERIRQ <30>

R141 37.4_0402_ 1% R141 37 .4_0402_1%

1 2

R144 10K_0402_ 5% R144 10K_0402_ 5%

1 2

SATA_LE D# <32 >

PCH_GPIO21 <21 > PCH_GPIO19 <21 >

+3VS

PCH_SPI_C LK_1 PCH_SPI_MO SI_1 PCH_SPI_MISO _1

SATA_DT X_C_PRX_N0 <25>

SATA_DT X_C_PRX_P0 < 25> SATA_PT X_DRX_N0 <25 > SATA_PT X_DRX_P0 <25>

SATA_DT X_C_PRX_N1 <25>

SATA_DT X_C_PRX_P1 < 25> SATA_PT X_DRX_N1 <25 > SATA_PT X_DRX_P1 <25>

+1.05VS

+3VS

R149

10K_040 2_5%

PCH_SPI_C LK_1

For 3G team Close to U5 20090915

RTCBATT

129

1K_0402 _5%

1 2 1

D BAS40-04 _SOT23-3

RTCVCC

C196

0.1U_040 2_16V4Z

BAS40-04 _SOT23-3

+CHGRTC

SATA for HDD1

SATA for ODD

+3VS

1 2

R146 10K_0402_ 5%@R146 10K_0402_ 5%@

1 2

R148 10K_0402_5%@R148 10K_0402_5%@

R150

10K_040 2_5%

1 2

R340 10_040 2_5%

Title

PCH (1/9) SATA,HDA,SPI, LPC

Size Document N umber Rev

Custom

NEW70 M/B LA-5892P Schematic

Date: Sheet of

GPIO21 Project

0 1

Compal Electronics, Inc.

1 2

C557 10P_04 02_50V8J

NEW70/90 NEW71/91

13 49Thursday, January 21, 2010

1.0

CIE_DTX_C _PRX_N1<27>

For PCIE LAN

or Wireless LAN

D D

CIE_DTX_C _PRX_P1<27>

CIE_PTX_C _DRX_N1<27>

CIE_PTX_C _DRX_P1<27>

CIE_DTX_C _PRX_N2<26>

CIE_DTX_C _PRX_P2<26>

P P

CIE_PTX_C _DRX_N2<26>

CIE_PTX_C _DRX_P2<26>

197 0.1U_0402_1 6V7K

198 0.1U_0402_1 6V7K

12 12

199 0.1U_0402_16V7 K

200 0.1U_0402_16V7 K

2/10 PCIE7, PCIE8 not support on HM55

C C

For PCIE LAN

R164 0_0402_5% R1 64 0_0402 _5%

LAN_CLK REQ#<27>

1 2

For Wireless LAN

R165 0_0402_5% R1 65 0_0402 _5%

MINI1_CLKREQ #< 26>

PCH_GPIO1 8<21>

PCH_GPIO2 0<21>

B B

+3VS

MINI1_CLKREQ # PCH_GPIO2 0

A A

PCH_GPIO2 6

PCH_GPIO2 5

R177 10K_0402_ 5% R1 77 10K_040 2_5%

1 2

R178 10K_0402_ 5% R1 78 10K_040 2_5%

1 2

2009/09/23:Change to +3VALW

R166 10K_0402_ 5%R166 10K_ 0402_5%

1 2

R186 10K_0402_ 5% R1 86 10K_040 2_5%

2009/08/13: Change back to +3VALW

1 2

+3VALW

1 2

EC_LID_OU T# PCH_SMB CLK PCH_SMB DATA

PCH_GPIO6 0

PCH_SML 1CLK PCH_SML 1DAT

PCH_GPIO7 4

PCH_GPIO4 4 PCH_GPIO5 6 PCH_GPIO7 3

CIE_DTX_C _PRX_N1 CIE_DTX_C _PRX_P1

CIE_PTX_D RX_N1

CIE_PTX_D RX_P1

CIE_DTX_C _PRX_N2

CIE_DTX_C _PRX_P2

CIE_PTX_D RX_N2

CIE_PTX_D RX_P2

CLK_PCIE_ LAN#< 27> CLK_PCIE_ LAN<27>

CLK_PCIE_ MINI1#<26> CLK_PCIE_ MINI1<26>

R179 10K_0402_ 5%

R179 10K_0402_ 5% R180 2.2K_0402_ 5%

R180 2.2K_0402_ 5% R181 2.2K_0402_ 5% R181 2.2K_0402_5 %

R182 10K_0402_ 5% R18 2 10K_040 2_5%

R183 2.2K_0402_ 5%

R183 2.2K_0402_ 5% R184 2.2K_0402_ 5% R184 2.2K_0402_5 %

R185 10K_0402_ 5% R18 5 10K_040 2_5%

R187 10K_0402_ 5% R18 7 10K_040 2_5% R188 10K_0402_ 5% R18 8 10K_040 2_5% R189 10K_0402_ 5% R18 9 10K_040 2_5%

PCH_GPIO7 3

PCH_GPIO2 6

PCH_GPIO4 4

PCH_GPIO5 6

1 2 1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2 1 2

PCH_GPIO1 8

PCH_GPIO2 0

PCH_GPIO2 5

EV1.0

BG30

ERN1

BJ30

ERP1

BF29

ETN1

BH29

ETP1

AW30

ERN2

BA30

ERP2

BC30

ETN2

BD30

ETP2

AU30

ERN3

AT30

ERP3

AU32

ETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M _FCBGA107

+3VALW

PCI-E*

Controller

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

Clock Flex

MBALERT# / GPIO11

ML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKIN_DOT_96N

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

MBCLK

MBDATA

ML0CLK

ML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

Board ID

HIGHLOW

ID1 GPIO65

A & B test

C test

H14

J14

M14

E10

G12

T13

T11

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

AF38

T45

P43

T42

N50

PROJECT _ID1

PROJECT _ID0

C_LID_OUT #

CH_SMBC LK

CH_SMBD ATA

CH_GPIO60

PCH_GPIO74

PCH_SML 1CLK

PCH_SML 1DAT

PEG_CLK REQ#

1 2

R338 10_040 2_5%R338 10_040 2_5%

XTAL25_ IN XTAL25_ OUT

XCLK_RC OMP

Project Port ID

PROJECT ID

ID2 GPIO21

0 0 0 0

R169 90.9_0402_ 1% R16 9 90.9_0402 _1%

ID1 GPIO65

1 0 0

Security Class ification

2009/08/ 01 2010/08/ 01

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/08/ 01 2010/08/ 01

Compal Secret Data

Deciphered Date

C_LID_OUT # <30 >

CH_SMBC LK <12,2 1,26>

CH_SMBD ATA <12,21,2 6>

+3VALW

R159

R159 10K_040 2_5%

10K_040 2_5%

1 2

20090915 Add

CLK_CPU _DMI# <5> CLK_CPU _DMI <5>

CLK_CPU _DP# <5> CLK_CPU _DP <5>

CLK_BUF _CPU_DMI# < 12> CLK_BUF _CPU_DMI <1 2>

CLK_BUF _CPU_BCLK# <12> CLK_BUF _CPU_BCLK < 12>

CLK_BUF _DREF_96M# <1 2> CLK_BUF _DREF_96M <12 >

CLK_BUF _PCIE_SATA# <12> CLK_BUF _PCIE_SATA <12>

1 2

C555 10P_04 02_50V8JC55 5 10P_0 402_50V8J

CLK_BUF _ICH_14M <12>

CLK_PCI_F B < 17>

1 2

R171 10K_0402_ 5%R171 10K_ 0402_5%

1 2 1 2

R174 10K_0402_ 5%@ R174 1 0K_0402_5%@

1 2 1 2

R175 10K_0402_ 5%R175 10K_ 0402_5%

ID0 GPIO66

10 0

10K_040 2_5%R172@ 10K_040 2_5%R172@

PROJECT

NEW70

NEW80

NEW90

10 1

1. Connect Directly EXPRESS CARD, MINI1, MINI2 2

. Level Shift1, Pull-Up to +3VS

CLOCK GEN, DIMM1, DIMM2

3. Level Shift2, Pull-Up to +3VS LAN

4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP

6/9 MOW23 Request add 25MHz crystal supporting Integrated Graphics

C203

C203 27P_040 2_50V8J

27P_040 2_50V8J

1 2

R170

+1.05VS

+3VS

PCH_SML 1CLK EC _SMB_CK2

PCH_SML 1DAT EC_S MB_DA2

Title

Size Document N umber Rev

Custom

Date: Sheet of

R170

1M_0402 _5%

6 1

2N7002D W-T/R7_SOT3 63-6

2N7002D W-T/R7_SOT3 63-6 Q9A

Q9A

2N7002D W-T/R7_SOT3 63-6

PCH (2/9) PCIE, SMBUS, CLK

NEW70 M/B LA-5892P Schematic

Y2 25MHZ_2 0PF_7A250000 12

25MHZ_2 0PF_7A250000 12

1 2

C204

C204 27P_040 2_50V8J

27P_040 2_50V8J

+3VS

Pull high +3VS at KB926 side

Q9B

Compal Electronics, Inc.

Change to 5x3.2

EC_SMB_ CK2 <30>

EC_SMB_ DA2 <30>

14 49Thursday, January 21, 2010

1.0

MI_HTX_PR X_N[0..3]

MI_HTX_PR X_N[0..3]< 4>

MI_HTX_PR X_P[0..3]<4>

MI_PTX_HR X_N[0..3]< 4>

MI_PTX_HR X_P[0..3]<4>

_FDI_TXN[0 ..7]<4>

1 2

_FDI_TXP[0 ..7]<4>

PM_CLKR UN#

SUS_PW R_ACK

PCH_GPIO7 2

EC_SW I#

PCH_PCIE_ WAKE#

PM_SLP_ LAN#

D D

+3VS

R190 8.2K_04 02_5%R190 8.2K_ 0402_5%

+3VALW

R191 10K_04 02_5%R191 10K_0402 _5%

R193 8.2K_04 02_5%R193 8.2K_ 0402_5%

C C

R194 10K_04 02_5%R194 10K_0402 _5%

R195 10K_04 02_5%R195 10K_0402 _5%

R196 10K_04 02_5%

MI_HTX_PR X_P[0..3]

MI_PTX_HR X_N[0..3]

MI_PTX_HR X_P[0..3]

_FDI_TXN[0 ..7]

_FDI_TXP[0 ..7]

+1.05VS

R192

49.9_040 2_1%

1 2

R195 Change to 10K for WW37 20090916

MI_HTX_PR X_N0 MI_HTX_PR X_N1

D D

MI_HTX_PR X_N2

DMI_HTX_P RX_N3

DMI_HTX_P RX_P0 DMI_HTX_P RX_P1 DMI_HTX_P RX_P2 DMI_HTX_P RX_P3

DMI_PTX_H RX_N0 DMI_PTX_H RX_N1 DMI_PTX_H RX_N2 DMI_PTX_H RX_N3

DMI_PTX_H RX_P0 DMI_PTX_H RX_P1 DMI_PTX_H RX_P2 DMI_PTX_H RX_P3

DMI_COMP

BC24

BJ22

AW20

BJ20

BD24 BG22 BA20 BG20

BE22

BF21 BD20 BE18

BD22 BH21 BC20 BD18

BH25

BF25

MI0RXN MI1RXN

D DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

EV1.0

DMI

FDI

DI_RXN0

F F

DI_RXN1 DI_RXN2

F FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14

BF13

BH13

BJ12

BG14

_FDI_TXN0

H H

_FDI_TXN1 _FDI_TXN2

H H

_FDI_TXN3 H_FDI_TXN 4 H_FDI_TXN 5 H_FDI_TXN 6 H_FDI_TXN 7

H_FDI_TXP 0 H_FDI_TXP 1 H_FDI_TXP 2 H_FDI_TXP 3 H_FDI_TXP 4 H_FDI_TXP 5 H_FDI_TXP 6 H_FDI_TXP 7

H_FDI_INT <4>

H_FDI_FSYNC0 <4>

H_FDI_FSYNC1 <4>

H_FDI_LSYNC0 <4>

H_FDI_LSYNC1 <4>

XDP_DBR ESET#<5,21 >

SYS_PW ROK VGATE

B B

10/2 Intel sugge stion change to 10K

+3VALW

EC_ACIN<30>

SYS_PW ROK<2 1>

SYS_PW ROK

U6 change to SA00000 OH00

A A

SYS_PW ROK

EC_PW ROK

LAN_RST #

R197 0_0402_5% R197 0_0402 _5% R198 0_0402_5%@R1 98 0_0402 _5%@

1 2

R199 10K_04 02_5%

CH751H-4 0PT_SOD323-2

R203 0_0402_5%@R2 03 0_0402 _5%@

+3VS

R205 1 0K_0402_5%

R206 1 0K_0402_5%

R207 1 0K_0402_5%

No used Integrated LAN, connecting LAN_RST# to GND

12 12

PM_DRAM _PWRGD<5>

SUS_PW R_ACK<3 0>

PBTN_OU T#<5,21 ,30>

EC_SW I#<30>

EC_PW ROK

NC7SZ08 P5X_NL_SC70-5

1 2

VGATE

XDP_DBR ESET#

SYS_PW ROK_R

SYS_PW ROK

LAN_RST #

PCH_RSM RST#

SUS_PW R_ACK

PBTN_OU T#

PCH_ACIN

PCH_GPIO7 2

EC_SW I#

B17

A10

C16

F14

EC_PW ROK <30 >

VGATE <12,45 >

SYS_RESET#

SYS_PWROK

PWROK

MEPWROK

LAN_RST#

DRAMPWROK

RSMRST#

SUS_PWR_DN_ACK / GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

IBEXPEAK-M _FCBGA107

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_M#

System Power Management

SLP_LAN# / GPIO29

Issued Date

TP23

PMSYNCH

PCH_PCIE_ WAKE#

J12

PM_CLKR UN#

PCH_GPIO61

P12

PM_SLP_ M#

PM_SLP_ DSW#

BJ10

PM_SLP_ LAN#

2009/08/ 01 2010/08/ 01

PCH_PCIE_ WAKE# <26,27 >

PM_CLKR UN# <3 0>

PAD

PCH_SUS CLK <30>

PM_SLP_ S5# <30>

PM_SLP_ S4# <30>

PM_SLP_ S3# <30>

PAD

T10

H_PM_SYNC <5 >

Compal Secret Data

Deciphered Date

32.768KHZ ouput for remove EC c rystal 20091103

R200 0_0402_5%

Q11

Q11 MMBT390 6_SOT23-3

PCH_RSM RST#

R201

R201 10K_040 2_5%

10K_040 2_5%

Title

Size Document N umber Rev

Custom

Date: Sheet of

MMBT390 6_SOT23-3

Compal Electronics, Inc.

PCH (3/9) DMI, FDI, PM

NEW70 M/B LA-5892P Schematic

123

1 2

R202 4.7K_04 02_5%R202 4.7K_ 0402_5%

D3A

BAV99DW -7_SOT363

D3B

BAV99DW -7_SOT363

EC_RSMR ST# <30>

+3VALW

R204

2.2K_040 2_5%

15 49Thursday, January 21, 2010

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