COMPAL LA-5841P Schematics

A

B

C

D

E

1 1

Compal Confidential

2 2

Tampa Bay NPVAA

LA-5841P Schematics Document

Intel PineView Processor/ Tiger point

3 3

4 4

A

B

2009-10-21

REV: 1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

139Tuesday, December 15, 2009

139Tuesday, December 15, 2009

139Tuesday, December 15, 2009

E

of

of

of

D

D

D

A

Compal Confidential

B

C

D

E

Model Name : NPVAA
File Name : LA-5841P

1 1

CRT Conn.

page 10

Fan Control

page 24

Intel Pineview-M

(22x22mm)

LED Conn.

page 9

2 2

PCIeMini Card
WWAN

USB port 6

page 15

PCIeMini Card
WLAN

PCIe port 2

page 15

RJ45

page 20

3 3

RTC CKT.

page 13

PCIeMini Card
WLAN

USB port 5

page 15

PCIeMini Card
GPS

PCIe port 4

page 15

RTL8103EL 10/100M

PCIe port 3

Card Reader

RTS5159 2IN1
USB port 3

LVDS

ONE CHANNEL

PCIe 1x [2,4]

1.5V 2.5GHz(250MB/s)

1.5V 2.5GHz(250MB/s)

page 20

page 21

USB

5V 480MHz

PCIe 1x

USB

5V 480MHz

page 4,5,6

DMI x 2

Tiger Pointer

(17x17mm)

page 11,12,13,14

HD Audio

Thermal Sensor

EMC1402

page 5

Memory BUS(DDRII)

1.8V DDRII 667

USB Conn X3

USB port 0,1,4

USB

5V 480MHz

SATA port 0

5V 1.5GHz(150MB/s)

BT conn

USB port 2

page 17

SATA HDD

3.3V 24.576MHz/48Mhz

page 16

Clock Generator

SLG8SP556VTR

page 8

200pin DDRII-SO-DIMM

Int. Camera

USB port 7

page 17

page 17

page 7

DC/DC Interface CKT.

3.3V 33 MHz

page 26

Power Circuit DC/DC

page 28~34

Debug Port

page 24

Touch Pad

4 4

IO/B

page 16

A

B

page 25

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ENE KB926 D3

Int.KBD

page 24

LPC BUS

page 22

SPI ROM

page 24

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

C

GSENSOR

page 23

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Int.

MIC CONN

page 19 page 19 page 19

D

HDA Codec

ALC272-GR

page 18

AMP.

E

TPA6017

page 19

SPK CONN

page 19

of

239Tuesday, December 15, 2009

of

239Tuesday, December 15, 2009

of

239Tuesday, December 15, 2009

MIC CONN

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

HP CONN

Compal Electronics,Inc

Compal Electronics,Inc

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

D

D

D

A

B

C

D

E

Voltage Rails

1 1

Power Plane Description

VIN
B+
+CPU_CORE
+0.89VS 0.89VS GFX support voltage
+0.9VS 0.9V switched power rail for DDR terminator
+1.05VS
+1.5VS
+1.8V
+1.8VS 1.8VS switched power rail
+3VALW
+3V_SB 3.3V power rail for LAN

2 2

+3V_LAN 3.3V power rail for LAN
+3V_WLAN
+3VS
+5VALW
+5V_SB 5V power rail for SB
+5VS
+VSB VSB always on power rail ONON
+RTCVCC RTC power

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

VCCP switched power rail

1.8V power rail for DDR

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail
5V always on power rail

5V switched power rail

S1 S3 S5

ON ON ON OFF
ON ON ON ON
ON OFF
ON

OFF
ON OFF OFF
ON OFF OFF

OFF

ON OFF1.5V switched power rail
ON

ON
ON

OFF OFF

ON

ON
ON

ON
ON ON
ON

ON
ON OFF

ON

ON
ON

ON OFF
ON

OFF OFF

ON
ON ONON

OFF
OFF

OFF

ON
OFF
OFF
OFF
OFF
ON
OFF

OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

OFF
OFF
ON

G3

BTO Option Table

Function

description

explain

BTO

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Mini PCI-E SLOT

WLAN@ 3GGPS@

WIMAX@

SIGNAL

3GGPSWi-Fi WiMax

SLP_S3#

SLP_S4#

SLP_S5#

HIGH HIGH HIGH

HIGH

LOW

LOW LOW

LOWLOW

STAR

3G

3G@

POWER SAVING

STAR@

HIGHHIGHHIGH

HIGH

HIGH

LOW

+VALW

ON

ON

ON

ON

ON

+V +VS Clock

ON

ON

ON

OFF

OFF

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

description

explain

BTO

Function

3 3

EC SM Bus1 address

Device

Smart Battery

Address

EC SM Bus2 address

Device

EMC1402

Address

1001 010X b0001 011X b

Tiger point SM Bus address

Device

Clock Generator
(SLG8SP556VTR)

DDR DIMMA

4 4

A

Address

1101 001Xb

1010 000Xb

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841
401799

401799

401799

339Tuesday, December 15, 2009

339Tuesday, December 15, 2009

339Tuesday, December 15, 2009

E

D

D

D

of

of

of

5

PINEVIEW_M

C1

C1

1 2

C2

C2

1 2

C3

C3

1 2

C4

C4

1 2

PINEVIEW_M

REV = 1.1

REV = 1.1

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

+1.05VS

ACES_87151-24051

ACES_87151-24051

U1A

D D

CLK_CPU_EXP#<8>
CLK_CPU_EXP<8>

C C

DMI_RXP0_C
DMI_RXN0_C
DMI_RXP1_C
DMI_RXN1_C

DMI_RXP0<12>

DMI_RXN0<12>

DMI_RXP1<12>

DMI_RXN1<12>

U1A

F3

DMI_RXP_0

F2

DMI_RXN_0

H4

DMI_RXP_1

G3

DMI_RXN_1

N7

EXP_CLKINN

N6

EXP_CLKINP

R10

EXP_TCLKINN

R9

EXP_TCLKINP

N10

RSVD

N9

RSVD

K2

RSVD

J1

RSVD

M4

RSVD

L3

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

XDP Reserve

XDP_TDI
XDP_TMS
XDP_TDO

B B

+1.05VS

A A

XDP_PREQ#

XDP_TRST#
XDP_TCK

H_PWRGD<5,13>

SLPIOVR<13>

PLTRST#<5,13,15,20,24>

5

R3

R3

1 2

51_0402_5%

51_0402_5%

R4

R4

1 2

51_0402_5%

51_0402_5%

R5

R5

1 2

51_0402_5%

51_0402_5%

R7

R7

1 2

51_0402_5%

51_0402_5%

R10

R10

1 2

51_0402_5%

51_0402_5%

R12

R12

1 2

51_0402_5%

51_0402_5%

XDP_PREQ#<5>
XDP_PRDY#<5>

XDP_BPM#3<5>
XDP_BPM#2<5>

XDP_BPM#1<5>
XDP_BPM#0<5>

R13 1K_0402_5%R13 1K_0402_5%
R14 1K_0402_5%R14 1K_0402_5%

PLTRST#

XDP_TDO<5>
XDP_TRST#<5>

XDP_TDI<5>
XDP_TMS<5>

XDP_TCK<5>

XDP_PREQ#
XDP_PRDY#

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

1 2

1 2

R15 1K_0402_5%R15 1K_0402_5%

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

XDP_TCK

T5T5
T6T6

12

T7T7

4

G2

DMI_TXP_0

G1

DMI_TXN_0

H3

DMI_TXP_1

J2

DMI_RXP0_C

DMI_RXN0_C

DMI_RXP1_C

DMI_RXN1_C

DMI_TXN_1

EXP_RCOMPO

EXP_ICOMPI

EXP_RBIAS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD
RSVD

1 OF 6

1 OF 6

L10

DMI_IRCOMP

L9
L8

N11

T1T1

P11

K3
L2
M2
N2

Pull-down must be placed

T2T2

within 500 mils from Pineview-M

DMI

DMI

Close to CPU

7/21 Add C302 to GND for Intel request

7/27 Change C302 to GND for +1.8V pull up

JXDP

JXDP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

@

@

4

XDP_TDI XDP_TDO

XDP_TMS XDP_TCKXDP_TRST#

Place diff CPU side

10/19 Change footprint T5, T6 and T7 from TPC24 to TPC12

3

DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..14]<7>

DMI_TXP0 <12>
DMI_TXN0 <12>
DMI_TXP1 <12>
DMI_TXN1 <12>

R1

R1

49.9_0402_1%

49.9_0402_1%

R2

R2

750_0402_1%

750_0402_1%

7/20 Add R238 and R239 for Ref board design

+1.8V

DDR_RPU

R6

R6

1

80.6_0402_1%

80.6_0402_1%

C302

C302

0.01U_0402_16V7K

0.01U_0402_16V7K
2

80.6_0402_1%

80.6_0402_1%

1K_0402_1%

1K_0402_1%

DDR_RPD

R9

R9

1K_0402_1%

1K_0402_1%

DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_A_RAS#<7>

DDR_A_BS0<7>
DDR_A_BS1<7>
DDR_A_BS2<7>

DDR_CS0#<7>
DDR_CS1#<7>

DDR_CKE0<7>
DDR_CKE1<7>

M_ODT0<7>
M_ODT1<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>
M_CLK_DDR1<7>
M_CLK_DDR#1<7>

10K_0402_5%

10K_0402_5%

+1.8V

10K_0402_5%

10K_0402_5%

12

R8

R8

12

R11

R11

R238

R238

R239

DDR_VREF

1

2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_CS0#
DDR_CS1#

DDR_CKE0
DDR_CKE1

M_ODT0
M_ODT1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

+1.8V

12

12

@R239

@

DDR_RPD
DDR_RPU

C5

C5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

T3T3
T4T4

8/14 Add +DDR_VREF net name

8/24 Change net to DDR_VREF

D34

D33

D33

1
2

CM1293A-04SO_SOT23-6

CM1293A-04SO_SOT23-6

6

I/O1

I/O4

5

REF1

REF2

I/O23I/O3

@

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS +3VS

XDP_PREQ#

4

2009/10/21 2012/10/21

2009/10/21 2012/10/21

Issued Date

Issued Date

Issued Date

3

2009/10/21 2012/10/21

D34

1
2

CM1293A-04SO_SOT23-6

CM1293A-04SO_SOT23-6

6

I/O1

I/O4

5

REF1

REF2

4

I/O23I/O3

@

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

PINEVIEW_M

U1B

U1B

AH19

DDR_A_MA_0

AJ18

DDR_A_MA_1

AK18

DDR_A_MA_2

AK16

DDR_A_MA_3

AJ14

DDR_A_MA_4

AH14

DDR_A_MA_5

AK14

DDR_A_MA_6

AJ12

DDR_A_MA_7

AH13

DDR_A_MA_8

AK12

DDR_A_MA_9

AK20

DDR_A_MA_10

AH12

DDR_A_MA_11

AJ11

DDR_A_MA_12

AJ24

DDR_A_MA_13

AJ10

DDR_A_MA_14

AK22

DDR_A_WE#

AJ22

DDR_A_CAS#

AK21

DDR_A_RAS#

AJ20

DDR_A_BS_0

AH20

DDR_A_BS_1

AK11

DDR_A_BS_2

AH22

DDR_A_CS#_0

AK25

DDR_A_CS#_1

AJ21

DDR_A_CS#_2

AJ25

DDR_A_CS#_3

AH10

DDR_A_CKE_0

AH9

DDR_A_CKE_1

AK10

DDR_A_CKE_2

AJ8

DDR_A_CKE_3

AK24

DDR_A_ODT_0

AH26

DDR_A_ODT_1

AH24

DDR_A_ODT_2

AK27

DDR_A_ODT_3

AG15

DDR_A_CK_0

AF15

DDR_A_CK_0#

AD13

DDR_A_CK_1

AC13

DDR_A_CK_1#

AC15

DDR_A_CK_3

AD15

DDR_A_CK_3#

AF13

DDR_A_CK_4

AG13

DDR_A_CK_4#

AD17

RSVD

AC17

RSVD

AB15

RSVD

AB17

RSVD

AB4

RSVD

AK8

RSVD

AB11

RSVD_TP

AB13

RSVD_TP

AL28

DDR_VREF

AK28

DDR_RPD

AJ26

DDR_RPU

AK29

RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

2

PINEVIEW_M

REV = 1.1

REV = 1.1

DDR_A_DQS_0

DDR_A_DQS#_0

DDR_A_DM_0
DDR_A_DQ_0

DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_1

DDR_A_DQS#_1

DDR_A_DM_1
DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQS#_2

DDR_A_DM_2
DDR_A_DQ_16

DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQS#_3

DDR_A_DM_3
DDR_A_DQ_24

DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQS#_4

DDR_A_DM_4
DDR_A_DQ_32

DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQS#_5

DDR_A_DM_5
DDR_A_DQ_40

DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQS#_6

DDR_A

DDR_A

2 OF 6

2 OF 6

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

DDR_A_DM_6
DDR_A_DQ_48

DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQS#_7

DDR_A_DM_7
DDR_A_DQ_56

DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

Compal Electronics,Inc

Compal Electronics,Inc

Compal Electronics,Inc

1

DDR_A_DQS0

AD3

DDR_A_DQS#0

AD2

DDR_A_DM0

AD4

DDR_A_D0

AC4

DDR_A_D1

AC1

DDR_A_D2

AF4

DDR_A_D3

AG2

DDR_A_D4

AB2

DDR_A_D5

AB3

DDR_A_D6

AE2

DDR_A_D7

AE3

DDR_A_DQS1

AB8

DDR_A_DQS#1

AD7

DDR_A_DM1

AA9

DDR_A_D8

AB6

DDR_A_D9

AB7

DDR_A_D10

AE5

DDR_A_D11

AG5

DDR_A_D12

AA5

DDR_A_D13

AB5

DDR_A_D14

AB9

DDR_A_D15

AD6

DDR_A_DQS2

AD8

DDR_A_DQS#2

AD10

DDR_A_DM2

AE8

DDR_A_D16

AG8

DDR_A_D17

AG7

DDR_A_D18

AF10

DDR_A_D19

AG11

DDR_A_D20

AF7

DDR_A_D21

AF8

DDR_A_D22

AD11

DDR_A_D23

AE10

DDR_A_DQS3

AK5

DDR_A_DQS#3

AK3

DDR_A_DM3

AJ3

DDR_A_D24

AH1

DDR_A_D25

AJ2

DDR_A_D26

AK6

DDR_A_D27

AJ7

DDR_A_D28

AF3

DDR_A_D29

AH2

DDR_A_D30

AL5

DDR_A_D31

AJ6

DDR_A_DQS4

AG22

DDR_A_DQS#4

AG21

DDR_A_DM4

AD19

DDR_A_D32

AE19

DDR_A_D33

AG19

DDR_A_D34

AF22

DDR_A_D35

AD22

DDR_A_D36

AG17

DDR_A_D37

AF19

DDR_A_D38

AE21

DDR_A_D39

AD21

DDR_A_DQS5

AE26

DDR_A_DQS#5

AG27

DDR_A_DM5

AJ27

DDR_A_D40

AE24

DDR_A_D41

AG25

DDR_A_D42

AD25

DDR_A_D43

AD24

DDR_A_D44

AC22

DDR_A_D45

AG24

DDR_A_D46

AD27

DDR_A_D47

AE27

DDR_A_DQS6

AE30

DDR_A_DQS#6

AF29

DDR_A_DM6

AF30

DDR_A_D48

AG31

DDR_A_D49

AG30

DDR_A_D50

AD30

DDR_A_D51

AD29

DDR_A_D52

AJ30

DDR_A_D53

AJ29

DDR_A_D54

AE29

DDR_A_D55

AD28

DDR_A_DQS7

AB27

DDR_A_DQS#7

AA27

DDR_A_DM7

AB26

DDR_A_D56

AA24

DDR_A_D57

AB25

DDR_A_D58

W24

DDR_A_D59

W22

DDR_A_D60

AB24

DDR_A_D61

AB23

DDR_A_D62

AA23

DDR_A_D63

W27

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

1

of

of

of

439Tuesday, December 15, 2009

439Tuesday, December 15, 2009

439Tuesday, December 15, 2009

D

D

D

5

PINEVIEW_M

U1C

U1C

D12

T8T8
T9T9
T10T10
T11T11
T12T12

D D

T13T13
T14T14
T15T15
T16T16

XDP_RSVD_9

T17T17
T18T18
T19T19
T20T20
T21T21
T22T22
T23T23
T24T24

T25T25

C C

T26T26
T27T27
T28T28
T29T29

T31T31
T33T33
T35T35
T37T37

C10
D10
B11
B10
B12
C11

AA7
AA6

AA21

W21

V21

A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8

L11

R5
R6

T21

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

RSVD

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

PINEVIEW_M

REV = 1.1

REV = 1.1

VGA

VGA

PM_EXTTS#_1/DPRSLPVR

MISC

MISC

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

REFCLKINP

REFCLKINN
REFSSCLKINP
REFSSCLKINN

PM_EXTTS#_0

PWROK

RSTIN#

HPL_CLKINN

HPL_CLKINP

8/14 Add CRT_IRTN net name

8/24 Det CRT_IRTN net name

M30
M29

GMCH_CRT_R

N31

GMCH_CRT_G

P30

GMCH_CRT_B

P29
N30

L31
L30

P28
Y30

Y29
AA30
AA31

R17 be placed <500 mils to U1.P28

DAC_IREF
CPU_DREFCLK

CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#

8/14 Add DAC_IREF net name

PM_EXTTS#1

K29

PM_EXTTS#0

J30

PCH_POK

L5

PLTRST#

AA3

CLK_CPU_HPLCLK#

W8

CLK_CPU_HPLCLK

W9

XDP_RSVD_9

4

GMCH_CRT_HSYNC <10>
GMCH_CRT_VSYNC <10>

GMCH_CRT_R <10>
GMCH_CRT_G <10>
GMCH_CRT_B <10>

GMCH_CRT_DATA <10>
GMCH_CRT_CLK <10>

R17 665_0402_1%R17 665_0402_1%

0_0402_5%

0_0402_5%

R19

R19

PM_EXTTS#0 <7>
PCH_POK <13>
PLTRST# <4,13,15,20,24>

CPU_DREFCLK <8>
CPU_DREFCLK# <8>
CPU_SSCDREFCLK <8>
CPU_SSCDREFCLK# <8>

PM_DPRSLPVR <13>

CLK_CPU_HPLCLK# <8>
CLK_CPU_HPLCLK <8>

R16 be placed U1.R22

Close to Processor pin

To be placed <250 mils to U1 ball

R21

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
ENBKL

R21

1 2

150_0402_1%

150_0402_1%
R22

R22

1 2

150_0402_1%

150_0402_1%
R23

R23

1 2

150_0402_1%

150_0402_1%
R24

R24

100K_0402_5%

100K_0402_5%

To be placed <500 mils to U1 ball

LVDS_ACLK#<9>

LVDS_ACLK<9>
LVDS_A0#<9>
LVDS_A0<9>
LVDS_A1#<9>
LVDS_A1<9>
LVDS_A2#<9>
LVDS_A2<9>

GMCH_INVT_PWM<9>

GMCH_ENVDD<9>

PM_EXTTS#0

LVDS_SCL<9>
LVDS_SDA<9>

ENBKL<22>

+3VS

12

R20

R20
10K_0402_5%

10K_0402_5%

XDP_BPM#0<4>
XDP_BPM#1<4>
XDP_BPM#2<4>
XDP_BPM#3<4>

XDP_TDI<4>
XDP_TDO<4>
XDP_TCK<4>
XDP_TMS<4>
XDP_TRST#<4>

3

R16

R16

2.37K_0402_1%

2.37K_0402_1%

ENBKL

H_THERMDA
H_THERMDC

L_IBG

U25
U26
R23
R24
N26
N27
R26
R27

R22
N22

N23

K25
K23
K24
H26

J28

L27
L26
L23

U1D

U1D

LA_CLKN
LA_CLKP
LA_DATAN_0
LA_DATAP_0
LA_DATAN_1
LA_DATAP_1
LA_DATAN_2
LA_DATAP_2

LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN

PINEVIEW_M

PINEVIEW_M

LVDS

LVDS

REV = 1.1

REV = 1.1

ICH

ICH

2

THERMTRIP#

CPUPWRGOOD

SMI#
A20M#
FERR#

LINT0
LINT1

IGNNE#

STPCLK#

DPRSTP#

DPSLP#

INIT#
PRDY#
PREQ#

PROCHOT#

GTLREF

VSS

E7
H7
H6
F10
F11
E5
F8

G6
G10
G8
E11
F15

E13

C18
W1

A13
H27

H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#

H_DPRSTP#
H_DPSLP#

H_INIT#
XDP_PRDY#
XDP_PREQ#

H_THERMTRIP#

H_PROCHOT#

H_PWRGD

H_GTLREF

H_SMI# <11>
H_A20M# <11>
H_FERR# <11>
H_INTR <11>
H_NMI <11>
H_IGNNE# <11>
H_STPCLK# <11>

H_DPRSTP# <13>
H_DPSLP# <13>
H_INIT# <11>

XDP_PRDY# <4>

XDP_PREQ# <4>

H_THERMTRIP# <11>

H_PWRGD <4,13>

1

+1.05VS

R18

R18
68_0402_5%

68_0402_5%

Close to CPU

8/14 Change net name to +H_GTLREF

L6

RSVD

G11

BPM_1_0#

E15

BPM_1_1#

G13

BPM_1_2#

F13

BPM_1_3#

B18

T30T30
T32T32
T34T34
T36T36

T38T38

B20
C20
B21

D14
D13
B14
C14
C16

D30
E30

G5

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

RSVD
TDI
TDO
TCK
TMS
TRST#

THRMDA_1
THRMDC_1

CPU

CPU

RSVD

BCLKN
BCLKP

BSEL_0
BSEL_1
BSEL_2

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

RSVD
RSVD
RSVD
RSVD

RSVD_TP
RSVD_TP

EXTBGREF

8/24 Change net name to H_GTLREF

E17

CLK_CPU_BCLK#

H10
J10

K5
H5
K6

H30
H29
H28
G30
G29
F29
E29

L7
D20
H13
D18

K9
D19
K7

CLK_CPU_BCLK

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

T39T39
T40T40

H_EXTBGREF

CLK_CPU_BCLK# <8>
CLK_CPU_BCLK <8>

CPU_BSEL0 <8>
CPU_BSEL1 <8>
CPU_BSEL2 <8>

CPU_VID0 <34>
CPU_VID1 <34>
CPU_VID2 <34>
CPU_VID3 <34>
CPU_VID4 <34>
CPU_VID5 <34>
CPU_VID6 <34>

8/14 Change net name to +H_EXTBGREF

R137

B B

3 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

3 OF 6

7/21 Pull down 1K to GND for Intel request

+3VS

1

C6

C6

2

0.1U_0402_16V4Z

A A

+3VS

0.1U_0402_16V4Z

C7

C7

1 2

2200P_0402_50V7K

2200P_0402_50V7K

1 2

R30 10K_0402_5%R30 10K_0402_5%

5

H_THERMDA

H_THERMDC
CPU_THERM#

CPU THERMAL SENSOR

U2

U2

GND

8
7
6
5

EC_SMB_CK2
EC_SMB_DA2

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

EMC1402-1-ACZL-TR_MSOP8

Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2

SMCLK

SMDATA

ALERT#

R137
1K_0402_5%

1K_0402_5%

1 2

H_DPRSTP#
H_DPSLP#
H_PWRGD
H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_FERR#
H_NMI

EC_SMB_CK2 <22,23>
EC_SMB_DA2 <22,23>

12

R29 10K_0402_5%@R29 10K_0402_5%@

4

+3VS

H_SMI#
H_STPCLK#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C151 220P_0402_50V7K@C151 220P_0402_50V7K@

1 2

C152 220P_0402_50V7K@C152 220P_0402_50V7K@

1 2

C154 220P_0402_50V7K@C154 220P_0402_50V7K@

1 2

C134 220P_0402_50V7K@C134 220P_0402_50V7K@

1 2

C135 220P_0402_50V7K@C135 220P_0402_50V7K@

1 2

C136 220P_0402_50V7K@C136 220P_0402_50V7K@

1 2

C137 220P_0402_50V7K@C137 220P_0402_50V7K@

1 2

C138 220P_0402_50V7K@C138 220P_0402_50V7K@

1 2

C139 220P_0402_50V7K@C139 220P_0402_50V7K@

1 2

C140 220P_0402_50V7K@C140 220P_0402_50V7K@

1 2

C141 220P_0402_50V7K@C141 220P_0402_50V7K@

1 2

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

3

C30

THRMDA_2/RSVD

D31

THRMDC_2/RSVD

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

ESD request

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4 OF 6

4 OF 6

220P_0402_50V7K

220P_0402_50V7K

placed within 0.5"
of processor pin.

2

C336

C336

@

@

1

2

8/24 Change net name to H_EXTBGREF

placed within 0.5" of processor
pin and 5 mils spacing

+1.05VS+1.05VS

R25

R25
1K_0402_1%

1K_0402_1%

R27

R27
2K_0402_1%

2K_0402_1%

H_EXTBGREFH_GTLREF

C335

C335

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

R26

R26
976_0402_1%

976_0402_1%

R28

R28

3.3K_0402_1%

3.3K_0402_1%

7/20 Add C335 for Ref board design7/20 Reserve C336 for Ref board design

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

539Tuesday, December 15, 2009

539Tuesday, December 15, 2009

539Tuesday, December 15, 2009

1

of

of

of

D

D

D

5

+0.89VS

D D

1380mA

+1.8V

R33

R33

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1 2

0_0603_5%

0_0603_5%

2

@

@

C12

C12

C13

C13

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

Please closed U1 ball

+1.8V

R36

R36

C C

1 2

0_0603_5%

0_0603_5%

Please closed U1 ball

B B

2

C14

C14

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C31

C31

0.1U_0402_10V6K

0.1U_0402_10V6K

2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

2

C22

C22

C21

C21

1

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

@

@

1

C32

C32

2

+VCCA_VCCD

1320mA

+VCCSFR_AB_DPL

+VCC_SM

2

1

+VCC_SM

+VCCCK_DDR

2270mA

+VCCCK_DDR

W14
W16
W18
W19

AK13
AK19

AL11
AL16
AL21
AL25

W10
W11

AA10
AA11

AA19

AC31

T13
T14
T16
T18

T19
V13
V19

AK9

AK7
AL7

U10

U5
U6
U7
U8
U9
V2
V3
V4

V11

U1E

U1E

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

VCCCK_DDR
VCCCK_DDR

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VCCACK_DDR
VCCACK_DDR

VCCD_AB_DPL

VCCD_HMPLL

VCCSFR_AB_DPL

GFX/MCH

GFX/MCH

DDR

DDR

PINEVIEW_M

PINEVIEW_M

REV = 1.1

REV = 1.1

154mA

+3VS

+RING_EAST
+RING_WEST

+LGI_VID +DMI_HMPLL

+0.89VS

A A

2

C44

C44

C43

C43

1

2.2U_0603_10V6K

2.2U_0603_10V6K

+VCC_CRT_DAC

5mA

305mA

1

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C45

C45

C46

C46

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

T30

VCCACRTDAC

T31

VCC_GIO

J31

VCCRING_EAST

C3

VCCRING_WEST

B2

VCCRING_WEST

C2

VCCRING_WEST

A21

VCC_LGI

5 OF 6

5 OF 6

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

1

1

C47

C47

2

1

C48

C48

C49

C49

C50

C50

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

EXP\CRT\PLL

EXP\CRT\PLL

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C51

C51

C52

C52

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

Close Chipset pin

5

POWER

POWER

DMI

DMI

10U_0805_10V4Z

10U_0805_10V4Z

1

+

+

C53

C53

2

4

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

CPU

CPU

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCSENSE

VSSSENSE

VCCA

VCCP
VCCP

VCCP

VCCALVDS
VCCDLVDS

LVDS

LVDS

VCCA_DMI
VCCA_DMI
VCCA_DMI

RSVD

VCCSFR_DMIHMPLL

VCCP

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

4

3500mA

1U_0402_6.3V6K

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

C29
B29
Y2

80mA

D4
B4

B3

1U_0402_6.3V6K

VCCSENSE
VSSSENSE

@

@

Please closed U1.D4

+VCC_ALVD

V30

+VCC_DLVD

W31

60mA

+VCC_DMI

T1

480mA

T2
T3

P2
AA1

104mA

E2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C18

C18

C19

C19

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

Please closed U1 ball

+CPU_CORE

2 x 330uF(9mohm/2)

1

+

+

C23

C23

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

+CPU_CORE

1

1

C28

C28

C29

C29

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS

1

C38

C38

0.1U_0402_10V6K

0.1U_0402_10V6K

2

T41T41

+1.05VS

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+CPU_CORE

1

1

C10

C10

C11

C11

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

1

+

+

C24

C24

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

1

C30

C30

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.5VS

1

C35

C35

0.01U_0402_16V7K

0.01U_0402_16V7K

2

Please closed U1.Y2

Issued Date

Issued Date

Issued Date

3

+1.05VS

R31

R31

1 2

0_0603_5%

0_0603_5%

1

2

C15

C15

C16

C16

2

1

@

@

@

@

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

+1.05VS

R32

R32

1 2

0_0603_5%

0_0603_5%

R34

R34

1 2

0_0603_5%

0_0603_5%

C25

C25

R35

R35

1 2

0_0603_5%

0_0603_5%

R37

R37

1 2

0_0603_5%

0_0603_5%

+CPU_CORE

12

R38

R38

100_0402_5%

100_0402_5%

VCCSENSE <34>
VSSSENSE <34>

12

R39

R39

100_0402_5%

100_0402_5%

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

+1.8VS

R40

R40

1 2

0_0603_5%

0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

R41

R41

1 2

0_0603_5%

0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

R42

R42

1 2

0_0603_5%

0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

R43

R43

1 2

0_0603_5%

0_0603_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

R44

R44

1 2

0_0603_5%

0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C33

C33

1

2

C8

22U_0805_6.3V6MC822U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1

2

C20

C20

+RING_WEST

C26

C26

@

@

C27

C27

C34

C34

1U_0402_6.3V6K

1U_0402_6.3V6K

C36

C36

C39

C39

C40

C40

C41

C41

C42

C42

+VCCA_VCCD

1

C9

2

4.7U_0603_6.3V6KC94.7U_0603_6.3V6K

+RING_EAST

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+LGI_VID

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_DMI

+VCC_DMI

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCSFR_AB_DPL

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCC_CRT_DAC+VCC_CRT_DAC

1

2

+DMI_HMPLL

1

2

+VCC_ALVD

1

2

+VCC_DLVD

1

2

2

PINEVIEW_M

PINEVIEW_M

U1F

U1F

REV = 1.1

REV = 1.1

A11

VSS

1

C17

C17

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C37

C37

2

2

A16

VSS

A19

VSS

A29

RSVD_NCTF

A3

RSVD_NCTF

A30

RSVD_NCTF

A4

RSVD_NCTF

AA13

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA2

VSS

AA22

VSS

AA25

VSS

AA26

VSS

AA29

VSS

AA8

VSS

AB19

VSS

AB21

VSS

AB28

VSS

AB29

VSS

AB30

VSS

AC10

VSS

AC11

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC28

VSS

AC30

VSS

AD26

VSS

AD5

VSS

AE1

VSS

AE11

VSS

AE13

VSS

AE15

VSS

AE17

VSS

AE22

VSS

AE31

VSS

AF11

VSS

AF17

VSS

AF21

VSS

AF24

VSS

AF28

VSS

AG10

VSS

AG3

VSS

AH18

VSS

AH23

VSS

AH28

VSS

AH4

VSS

AH6

VSS

AH8

VSS

AJ1

RSVD_NCTF

AJ16

VSS

AJ31

RSVD_NCTF

AK1

RSVD_NCTF

AK2

RSVD_NCTF

AK23

VSS

AK30

RSVD_NCTF

AK31

RSVD_NCTF

AL13

VSS

AL19

VSS

AL2

RSVD_NCTF

AL23

VSS

AL29

RSVD_NCTF

AL3

RSVD_NCTF

AL30

RSVD_NCTF

AL9

VSS

B13

VSS

B16

VSS

B19

VSS

B22

VSS

B30

RSVD_NCTF

B31

RSVD_NCTF

B5

VSS

B9

VSS

C1

RSVD_NCTF

C12

VSS

C21

VSS

C22

VSS

C25

VSS

C31

RSVD_NCTF

D22

VSS

E1

RSVD_NCTF

E10

VSS

E19

VSS

E21

VSS

E25

VSS

E8

VSS

F17

VSS

F19

VSS

PINEVIEW-M_FCBGA8559

PINEVIEW-M_FCBGA8559

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

6 OF 6

6 OF 6

GND

GND

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

401799

401799

401799

1

F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4

T29

D

D

D

of

of

of

639Tuesday, December 15, 2009

639Tuesday, December 15, 2009

639Tuesday, December 15, 2009

5

DDR_A_DQS#[0..7]<4>

DDR_A_D[0..63]<4>

DDR_A_DM[0..7]<4>

DDR_A_DQS[0..7]<4>

DDR_A_MA[0..14]<4>

D D

+1.8V

@

@

C C

+0.9VS

1

@

@

C66

C66

C67

C67

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

A A

C54

C54

1

+

+

C61

C61

2

220U_B2_2.5VM_R35

220U_B2_2.5VM_R35

1

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1

DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5

DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA6

DDR_CKE1
DDR_A_BS2
DDR_CKE0

2

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

@

@

C68

C68

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place near JDDR1

2

2

2

C57

C57

C56

C56

C55

C55

1

C62

C62

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C69

C69

2

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

1

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

1

C63

C63

C64

C64

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RP1

RP1
1 8
2 7
3 6
4 5

RP3

RP3
1 8
2 7
3 6
4 5

RP5

RP5
1 8
2 7
3 6
4 5

R50

R50

1 2

47_0402_5%

47_0402_5%
R51

R51

1 2

47_0402_5%

47_0402_5%
R52

R52

1 2

47_0402_5%

47_0402_5%

5

1

1

C71

C71

C70

C70

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+0.9VS

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

2

C58

C58

1

1

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

1

C65

C65

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

@

@

C72

C72

C73

C73

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

9/4 Reserve C66, C67, C68, C69, C72, C75, C77, C78, C79, C81, C83, C84, C85

RP2

RP2

DDR_A_MA3

18

DDR_A_MA1

27

DDR_A_MA10

36

DDR_A_BS0

45

RP4

RP4

M_ODT0

18

DDR_A_MA13

27

DDR_CS0#

36

DDR_A_RAS#

45

RP6

RP6

DDR_A_MA4

18

DDR_A_MA11

27

DDR_A_MA7

36

DDR_A_MA14

45

47_0804_8P4R_5%

47_0804_8P4R_5%

+1.8V

7/8 Add 4PCS CAP on 1.8V for EMI request

1

1

@

@

C75

C75

C74

C74

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C76

C76

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4

1

C217

C217

C216

C216

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

@

@

C77

C77

C78

C78

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Note:
Place these resistor
closely DIMMA,all
trace length<1000 mil

Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1000 mil

4

Please closed SO-DIMM

1

C238

C238

1

C291

C291

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

@

@

C79

C79

C80

C80

C81

C81

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

1

@

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

@

@

C82

C82

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R45

R45

1K_0402_1%

1K_0402_1%

R46

R46

1K_0402_1%

1K_0402_1%

+DIMM_VREF

C59

C59

1

C83

C83

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.8V

12

12

Share +DIMM_VREF for

1.DDRII VREF

2.PineView DDR_VREF

20mils

1

2

1

1

@

@

@

@

C84

C84

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+DIMM_VREF

1

C60

C60
@

@

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2

7/21 Reserve C60

1

1

@

@

C85

C85

C86

C86

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3

+1.8V +1.8V

+DIMM_VREF

DDR_CKE0<4>

DDR_A_BS2<4>

DDR_A_WE#<4> DDR_CS0# <4>
DDR_A_CAS#<4> M_ODT0 <4>

DDR_CS1#<4>

M_ODT1<4>

CLK_SMBDATA<8,15>

CLK_SMBCLK<8,15>

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0 DDR_A_D6

DDR_A_D2
DDR_A_D3

DDR_A_D9
DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D16
DDR_A_D17

DDR_A_DM2

DDR_A_D18
DDR_A_D19

DDR_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1#

M_ODT1
DDR_A_D33

DDR_A_D32
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D34
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D62

DDR_A_D59
CLK_SMBDATA

CLK_SMBCLK

1

C87

C87

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Secret Data

Compal Secret Data

Compal Secret Data

1

C88

C88

2

Deciphered Date

Deciphered Date

Deciphered Date

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

201

2

JDDR

JDDR

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

G1

FOX_AS0A426-N4SN-7F_200P

FOX_AS0A426-N4SN-7F_200P
@

@

DIMMA

2

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA0
SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

G2

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

202

DDR_A_D5
DDR_A_D4

DDR_A_DM0

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D14

DDR_A_D15

DDR_A_D24
DDR_A_D25

DDR_A_DM3
DDR_A_D26

DDR_A_D27
DDR_A_D20

DDR_A_D21
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D22

DDR_A_D23
DDR_CKE1

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D35
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D58

DDR_A_D63

R48 10K_0402_5%R48 10K_0402_5%

1 2

R49 10K_0402_5%R49 10K_0402_5%

1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

M_CLK_DDR0 <4>
M_CLK_DDR#0 <4>

R47

R47

1 2

0_0402_5%

0_0402_5%

DDR_CKE1 <4>

DDR_A_BS1 <4>
DDR_A_RAS# <4>DDR_A_BS0<4>

M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>

Compal Electronics,Inc

Compal Electronics,Inc

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

1

PM_EXTTS#0 <5>

739Tuesday, December 15, 2009

739Tuesday, December 15, 2009

739Tuesday, December 15, 2009

of

of

of

D

D

D

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

USB
MHz

FSC FSB REF

CLKSEL2

0 1000 133 33.31 14.318 96.0 48.0

0 1001 200 33.30 14.318 96.0 48.0

0 1001 166 33.31 14.318 96.0 48.0

D D

1 1000 333 33.30 14.318 96.0 48.0

1 1000 100 33.31 14.318 96.0 48.0

1 1001 400 33.30 14.318 96.0 48.0

111

R251

R251

2.2K_0402_5%

2.2K_0402_5%

1 2

R252

R252
0_0402_5%

0_0402_5%

R244

R244
1K_0402_5%

1K_0402_5%

1 2

R242

R242
0_0402_5%

0_0402_5%

R246

R246

10K_0402_5%

10K_0402_5%

1 2

R247

R247
0_0402_5%

0_0402_5%

+1.05VS

12

R248

R248
470_0402_5%

470_0402_5%

12

12

R253

@R253

@
1K_0402_5%

1K_0402_5%

+1.05VS

12

R249

R249
470_0402_5%

470_0402_5%

12

12

R243

@R243

@
0_0402_5%

0_0402_5%

+1.05VS

12

R250

R250
470_0402_5%

470_0402_5%

12

12

R245

@R245

@
0_0402_5%

0_0402_5%

C C

FSA

CPU_BSEL0<5>

FSB

CPU_BSEL1<5>

B B

FSC

CPU_BSEL2<5>

Reserved

+1.5VM_CK505

+1.05VM_CK505

+1.5VM_CK505

8/24 Change net name to FSB for U3.2
7/13 Add 33pF to GND for RF request
7/21 Reserve 33pF to GND for RF request
8/27 C303, C324, C325, C326, C327 to GND for RF request

R241

R241

+3VS

1 2

7/22 Add R241 pull up to +3VS for RF Intel request

R70

R70

+3VS

8/14 Add R250 pull up for Intel request

H_STP_CPU#

10K_0402_5%

10K_0402_5%

H_STP_PCI#_R

1 2

10K_0402_5%

10K_0402_5%

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#

For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed

7/22 Add R242 to R253 for Intel request

A A

C108 22P_0402_50V8JC108 22P_0402_50V8J

14.31818MHZ_16PF_DSX840GA

14.31818MHZ_16PF_DSX840GA

C109 22P_0402_50V8JC109 22P_0402_50V8J

Y1

Y1

CLK_XTAL_IN

12

CLK_XTAL_OUT

Routing the trace at least 10mil

5

4

+3VM_CK505

R53

R53

1 2

+3VS

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

+1.05VM_CK505

+1.05VS

R54

R54

1 2

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

7/13 For RF request

@

@

+3VM_1.5VM_R

+1.5VM_CK505

1

@

@

C103

C103

2

1

C104

C104

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VM_1.5VM_R

1

C107

C107

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R71 0_0402_5%@R71 0_0402_5%@

1 2

R57

R57

1 2

+1.5VS

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

7/13 For RF request

+3VM_CK505

R58

R58

1 2

0_0603_5%

0_0603_5%

R60

@R60

@

1 2

0_0603_5%

0_0603_5%

R59

R59

1 2

0_0603_5%

0_0603_5%

R61

@R61

@

1 2

0_0603_5%

0_0603_5%

7/13 For RF request

CLK_48M_CR<21>
CLK_PCH_48M<12>

CLK_PCH_14M<13>

VGATE<13,22,34>

H_STP_CPU#<13>

H_STP_PCI#<13>

CLK_PCI_DDR<24>

CLK_PCI_LPC<22>
CLK_PCI_PCH<11>

7/13 Add 33pF to GND for RF request

1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS

ITP_EN PCI2_TME

R76

R76
10K_0402_5%

10K_0402_5%

1 2

PCI4_SEL

R77

R77
10K_0402_5%

10K_0402_5%

1 2

4

3

250 mA

1

C89

C89
10U_0805_10V4Z

10U_0805_10V4Z

2

1

C90

C90

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C91

C91

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C92

C92

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

80 mA

1

C96

C96
10U_0805_10V4Z

10U_0805_10V4Z

2

1

C97

C97

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C98

C98

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C99

C99

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

SA000020K00 (Silego : SLG8SP556VTR )

10U_0805_10V4Z

10U_0805_10V4Z

1

C105

C105

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@
C330

C330

1 2
1 2

1 2

C303 22P_0402_50V8JC303 22P_0402_50V8J

1 2

1 2

C324 22P_0402_50V8JC324 22P_0402_50V8J

1 2

C325 22P_0402_50V8JC325 22P_0402_50V8J

1 2

1 2

C326 22P_0402_50V8JC326 22P_0402_50V8J

1 2
1 2

1 2

C327 22P_0402_50V8JC327 22P_0402_50V8J

+3VS

R75

R75
10K_0402_5%

10K_0402_5%

1 2

@

@
R78

R78
10K_0402_5%

10K_0402_5%

1 2

1

C106

C106

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VM_CK505

47P_0402_50V8J

47P_0402_50V8J

R6222_0402_5% R6222_0402_5%
R6322_0402_5% R6322_0402_5%

R6533_0402_5% R6533_0402_5%

R7233_0402_5% R7233_0402_5%

R7333_0402_5% R7333_0402_5%
R7433_0402_5% R7433_0402_5%

+3VM_CK505

FSA
FSB
FSC

VGATE

H_STP_CPU#
H_STP_PCI#_R

CLK_XTAL_IN
CLK_XTAL_OUT

CLK_PCI_DDR_R

CLK_PCI_DDR_R
PCI2_TME

PCI4_SEL

PCI4_SEL
ITP_EN

ITP_EN

U3

U3

55

VDD_SRC

6

VDD_REF

12

VDD_PCI

72

VDD_CPU

19

VDD_48

27

VDD_PLL3

66

VDD_CPU_IO

31

VDD_PLL3_IO

62

VDD_SRC_IO

52

VDD_SRC_IO

23

VDD_IO

38

VDD_SRC_IO

20

USB_0/FS_A

2

FS_B/TEST_MODE

7

REF_0/FS_C/TEST_

8

REF_1

1

CKPWRGD/PD#

11

NC

53

CPU_STOP#

54

PCI_STOP#

5

XTAL_IN

4

XTAL_OUT

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

3

VSS_REF

22

VSS_48

26

VSS_IO

69

VSS_CPU

30

VSS_PLL3

34

VSS_SRC

59

VSS_SRC

42

VSS_SRC

73

VSS

SLG8SP556VTR_QFN72_10X10

SLG8SP556VTR_QFN72_10X10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

C328

C328
47P_0402_50V8J

47P_0402_50V8J

1

C100

C100

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

7/13 For RF request

1

C101

C101

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C329

C329
47P_0402_50V8J

47P_0402_50V8J

8/27 Delete C93, C94, C95, C102 for low power CLK GEN

7/21 Delete C296, C297 for RF request
7/13 Add 22pF to gnd and close to U3 for RF request
7/21 Reserve 22pF to gnd and close to U3 for RF request

CPU_0#

CPU_1#

SRC_0/DOT_96

SRC_0#/DOT_96#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_2#

SRC_3#

SRC_4#

SRC_6#

SRC_7#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

SRC_9#

SRC_10

SRC_10#

SRC_11

SRC_11#

CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#

CLKREQ_9#
SLKREQ_10#
CLKREQ_11#

USB_1/CLKREQ_A#

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

9

SDA

10

SCL

71

CPU_0

70
68

CPU_1

67

24
25

28
29

32

SRC_2

33

35

SRC_3

36

39

SRC_4

40

57

SRC_6

56

61

SRC_7

60

64
63

44

SRC_9

45

50
51

48
47

37
41
58
65
43
49
46
21

Compal Secret Data

Compal Secret Data

Compal Secret Data

CLK_SMBDATA
CLK_SMBCLK

CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_HPLCLK
CLK_CPU_HPLCLK#

CPU_DREFCLK
CPU_DREFCLK#

CPU_SSCDREFCLK
CPU_SSCDREFCLK#

CLK_CPU_EXP
CLK_CPU_EXP#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_PCH
CLK_PCIE_PCH#

CLK_PCIE_WWAN
CLK_PCIE_WWAN#

WLAN_CLKREQ#

LAN_CLKREQ#

WWAN_CLKREQ#

CLK_SMBDATA <7,15>
CLK_SMBCLK <7,15>

CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>
CLK_CPU_HPLCLK <5>
CLK_CPU_HPLCLK# <5>

CPU_DREFCLK <5>
CPU_DREFCLK# <5>

CPU_SSCDREFCLK <5>
CPU_SSCDREFCLK# <5>

CLK_CPU_EXP <4>
CLK_CPU_EXP# <4>

CLK_PCIE_SATA <11>
CLK_PCIE_SATA# <11>

CLK_PCIE_WLAN <15>
CLK_PCIE_WLAN# <15>

CLK_PCIE_LAN <20>
CLK_PCIE_LAN# <20>

CLK_PCIE_PCH <12>
CLK_PCIE_PCH# <12>

CLK_PCIE_WWAN <15>
CLK_PCIE_WWAN# <15>

WLAN_CLKREQ# <15>

LAN_CLKREQ# <20>

WWAN_CLKREQ# <15>

7/21 Change WWAN_CLKREQ# from REQ4 to REQ11

Deciphered Date

Deciphered Date

Deciphered Date

2

1

CPU_SSCDREFCLK CPU_SSCDREFCLK#

1

C300

@C300

@
33P_0402_50V8K

33P_0402_50V8K

2

C301

1

@C301

@
33P_0402_50V8K

33P_0402_50V8K

2

7/13 Add 33pFfor RF request
7/21 Reserve 33pFfor RF request

+3VS

R55

PCH_SMBDATA<13>

PCH_SMBCLK<13>

2.2K_0402_5%

2.2K_0402_5%

Q1A

Q1A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

6 1

+3VS

3

Q1B 2N7002DW-T/R7_SOT363-6Q1B 2N7002DW-T/R7_SOT363-6

R55

2
5

4

R56

R56

2.2K_0402_5%

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

SRC PORT LIST

PORT

SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11

WLAN_CLKREQ#
WWAN_CLKREQ#
LAN_CLKREQ#

DEVICE

CPU_DREFCLK
CPU_EXP

PCIE_SATA
PCIE_WLAN

PCIE_LAN
PCIE_PCH
PCIE_WWAN

R67 10K_0402_5%R67 10K_0402_5%
R68 10K_0402_5%R68 10K_0402_5%
R69 10K_0402_5%R69 10K_0402_5%

12
12
12

REQ PORT LIST

DEVICEPORT

REQ_3#

REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

PEIC_WLAN

PCIE_LAN

PEIC_WWAN

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841
401799

401799

401799

1

839Tuesday, December 15, 2009

839Tuesday, December 15, 2009

839Tuesday, December 15, 2009

of

of

of

+3VS

D

D

D

5

4

3

2

1

LCD POWER CIRCUIT

D D

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

GMCH_ENVDD<5>

C C

LED/PANEL BD. Conn.

R85 0_0805_5%R85 0_0805_5%

250mA

C117

C117
@

@

B+

+3VS

1

680P_0402_50V7K

680P_0402_50V7K

2

450mA

B B

+LCDVDD

680P_0402_50V7K

680P_0402_50V7K

For EMI request

1 2

R86 0_0805_5%R86 0_0805_5%

1 2

1

C118

C118
@

@

2

+LCDVDD

12

3

Q2B

Q2B

4

100K_0402_5%

100K_0402_5%

BKOFF#<22>

LVDS_A0<5>
LVDS_A0#<5>

LVDS_A1<5>
LVDS_A1#<5>

LVDS_A2<5>
LVDS_A2#<5>

LVDS_ACLK<5>
LVDS_ACLK#<5>

R79

R79
150_0603_5%

150_0603_5%

5

12

R82

R82

C115680P_0402_50V7K C115680P_0402_50V7K

12

C11668P_0402_50V8J C11668P_0402_50V8J

12

+3VS

12

R80

R80
100K_0402_5%

100K_0402_5%

R81 47K_0402_5%R81 47K_0402_5%

61

Q2A

Q2A

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+LEDVDD
+LCDVDD_L

(20 MIL)

LCD_PWM
BKOFF#
LVDS_SDA
LVDS_SCL

LVDS_A0

LVDS_A0#

LVDS_A1

LVDS_A1#

LVDS_A2

LVDS_A2#

LVDS_ACLK
LVDS_ACLK#

12

JLVDS

JLVDS

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_87213-2000G

ACES_87213-2000G

@

@

1

C111

C111

0.1U_0402_10V6K

0.1U_0402_10V6K

2

1

C112

C112

0.01U_0402_25V7K

0.01U_0402_25V7K

2

21

GND

22

GND

G

G

2

W=40mils

+3VS

S

S

2A

D

D

Q10

Q10

1 3

AO3413_SOT23

AO3413_SOT23

1

C113

C113
@

@

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+LCDVDD

1

2

GMCH_INVT_PWM<5>

1

C110

C110

@

@

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

W=40mils

C114

C114

0.1U_0402_16V4Z

0.1U_0402_16V4Z

INVT_PWM<22>

LVDS_SCL
LVDS_SDA

R87 0_0402_5%R87 0_0402_5%

1 2

R88 0_0402_5%

R88 0_0402_5%

1 2

@

@

+3VS

1 2

R83

R83

1 2

2.2K_0402_5%

2.2K_0402_5%

LCD_PWM

7/2 EVT:Add support DPST function from CPU

8/14 DVT:Add R87 and Det R88 for no support DPST

LVDS_ACLK LVDS_ACLK#

C331

@C331

@

1 2

10P_0402_50V8J

10P_0402_50V8J

7/21 Reserve Shunt Capacitor for EMI request

R84

R84

2.2K_0402_5%

2.2K_0402_5%
LVDS_SCL <5>

LVDS_SDA <5>

A A

5

4

Security Classification

Security Classification

Security Classification

2009/10/21 2012/10/21

2009/10/21 2012/10/21

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/21 2012/10/21

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

939Tuesday, December 15, 2009

939Tuesday, December 15, 2009

939Tuesday, December 15, 2009

1

of

of

of

D

D

D

A

B

C

D

E

CRT CONNECTOR

8/24 Det D1, D2, D3 for ESD request

1 1

GMCH_CRT_R<5>

GMCH_CRT_G<5>

GMCH_CRT_B<5>

12

R90

R90

R89

R89

150_0402_1%

150_0402_1%

2 2

1 2

C125 0.1U_0402_16V4ZC125 0.1U_0402_16V4Z

GMCH_CRT_HSYNC<5>

SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

GMCH_CRT_VSYNC<5>

3 3

+3VS

12

R95

R95

4.7K_0402_5%

4.7K_0402_5%

GMCH_CRT_DATA<5>

GMCH_CRT_CLK<5>

4 4

GMCH_CRT_G

GMCH_CRT_B

12

12

R91

R91

150_0402_1%

150_0402_1%

150_0402_1%

150_0402_1%

+CRT_VCC

1

5

P

OE#

A2Y

G

3

1 2

C126 0.1U_0402_16V4ZC126 0.1U_0402_16V4Z

12

R96

R96

4.7K_0402_5%

4.7K_0402_5%

Q4B

Q4B

2

Q4A

Q4A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

C120

C120

C119

C119

2

2.2P_0402_50V8C

2.2P_0402_50V8C

U4

U4

4

+CRT_VCC

1

5

U5

U5

P

4

OE#

A2Y

G

SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

+3VS

R97

R97

4.7K_0402_5%

4.7K_0402_5%

5

3

4

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

470P_0402_50V8J

470P_0402_50V8J

Place closed to conn.

L1

L1

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

L2

L2

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

L3

L3

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

1

1

C121

C121

2

2

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

1 2

R92 10K_0402_5%R92 10K_0402_5%

CRT_HSYNC_1

CRT_VSYNC_1

+CRT_VCC

12

12

R98

R98

4.7K_0402_5%

4.7K_0402_5%

CRT_DDC_DAT

CRT_DDC_CLK

1

C130

C130

@

@

1

C131

C131
470P_0402_50V8J

2

470P_0402_50V8J

2

@

@

1

C123

C122

C122

C123

2

2.2P_0402_50V8C

2.2P_0402_50V8C

R93 10_0402_5%R93 10_0402_5%

1 2

R94 10_0402_5%R94 10_0402_5%

1 2

1

C124

C124

2

2.2P_0402_50V8C

2.2P_0402_50V8C

+5VS

C127

C127

2
3

1

2

If=1A

D4

D4

2.2P_0402_50V8C

2.2P_0402_50V8C

1

C128

C128

2

33P_0402_50V8K

33P_0402_50V8K

+CRT_VCC_R

1

RB491D_SOT23-3

RB491D_SOT23-3

CRT_R_L
CRT_DDC_DAT

CRT_G_L
HSYNC

CRT_B_L
VSYNC

CRT_DDC_CLK

HSYNC

VSYNC

1

2

33P_0402_50V8K

33P_0402_50V8K

+CRT_VCC

J2

J2

@

@

2

112

JUMP_43X39

JUMP_43X39

F1

F1

1.1A_6V_MINISMDC110F-2

1.1A_6V_MINISMDC110F-2

@

@

JCRT

JCRT

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5
16

17

CRT_R_LGMCH_CRT_R

CRT_G_L

CRT_B_L

7/10 Add J2 for cost down PolySwitch

9/28 Reserve F1 for cost down PolySwitch

+CRT_VCC

30mil

21

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

GND
GND

SUYIN_070546FR015S263ZR

SUYIN_070546FR015S263ZR

@

@

C129

C129

1

2

A

B

Security Classification

Security Classification

Security Classification

2009/10/21 2012/10/21

2009/10/21 2012/10/21

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/21 2012/10/21

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet of

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

10 39Tuesday, December 15, 2009

10 39Tuesday, December 15, 2009

10 39Tuesday, December 15, 2009

E

of

of

D

D

D

5

PCI_PIRQB#
PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQA#

PCI_PIRQE#
PCI_PLOCK#
PCI_PIRQG#
PCI_IRDY#

PCI_SERR#
PCI_PERR#
PCI_TRDY#
GPIO1

GPIO22
PCI_DEVSEL#
PCI_PIRQD#
PCI_PIRQH#

REQ2#
REQ1#
PCI_STOP#
PCI_FRAME#

RSVD01
RSVD02

CLK_PCI_PCH<8>
PCI_RST#<22>

+3VS

R99 8.2K_0402_5%R99 8.2K_0402_5%

1 2

R100 8.2K_0402_5%R100 8.2K_0402_5%

1 2

+3VS

D D

+3VS

+3VS

+3VS

C C

+3VS

B B

RP7

RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP8

RP8

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP9

RP9

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%
RP10

RP10

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP11

RP11

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

4

100K_0402_5%

100K_0402_5%

For EC request.

R103

R103

10K_0402_5%

10K_0402_5%

@

@

@

@

1 2

CLK_PCI_PCH
PCI_RST#

12

R101

R101

R104

R104
10K_0402_5%

10K_0402_5%
@

@

R105

R105
1K_0402_5%

1K_0402_5%

+3VS

PCI_DEVSEL#

PCI_IRDY#
PCI_SERR#

PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

REQ1#
REQ2#

GPIO22
GPIO1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

RSVD01
RSVD02

R236

R236

1 2

8.2K_0402_5%

8.2K_0402_5%

R12
AE20
AD17
AC15
AD18

Y12
AA10
AA12

Y10
AD15

W10

V12
AE21
AE18
AD19

U12
AC17

AB13
AC13
AB15

Y14
AB16

AE24
AE23

AA14

V14

AD16
AB11
AB10

AD23

B15

J12

A23
C22

B11

F14

A10
D10
A16

A18
E16

G16
A20

G14
C15

H10

D11
M13

A5

B7

A8

A2
C9

B2
D7
B3

E8
D6
H8
F8

K9

U6A

U6A

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

GNT1#
GNT2#

REQ1#
REQ2#

GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

STRAP0#
RSVD01
RSVD02

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

U6C

U6C

RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD24
RSVD25
RSVD26

RSVD27
RSVD28

RSVD29
RSVD30
RSVD31

GPIO36

TGP

TGP

PCI

PCI

TGP

TGP

3

SATA

SATA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1

1

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

SATALED#

A20GATE

A20M#

CPUSLP#

IGNNE#

INIT3_3V#

FERR#

RCIN#

HOST

HOST

SERIRQ

STPCLK#

THRMTRIP#

INIT#
INTR

NMI

SMI#

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

H16
M15
C13
L16

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

AD4
AC4

AD11
AC11
AD25

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

SATARBIAS

GATEA20
H_A20M#

H_IGNNE#
H_INIT#

H_INTR
H_FERR#
H_NMI
EC_KBRST#
SERIRQ
H_SMI#
H_STPCLK#

CLK_PCIE_SATA# <8>
CLK_PCIE_SATA <8>

R106 24.9_0402_1%R106 24.9_0402_1%

SATALED# <25>

GATEA20 <22>
H_A20M# <5>

H_IGNNE# <5>
H_INIT# <5>

H_INTR <5>
H_FERR# <5>
H_NMI <5>
EC_KBRST# <22>
SERIRQ <22>
H_SMI# <5>
H_STPCLK# <5>

2

PCI_RST#

CLK_PCI_PCH

@

@

10_0402_5%

10_0402_5%

8.2P_0402_50V8D

8.2P_0402_50V8D

For EMI, close to TigerPoint

SATA_IRX_C_DTX_N0 <17>
SATA_IRX_C_DTX_P0 <17>
SATA_ITX_DRX_N0 <17>
SATA_ITX_DRX_P0 <17>

Please closed Tiger point
PIN within 500 mils

+1.05VS

12

R110

R110
56_0402_5%

56_0402_5%

R110 to be within 1" from the Tiger
Point chipset.

H_THERMTRIP# <5>

1

12

1

@

C132

C132

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

H_FERR#

@

+1.05VS

R111

R111
56_0402_5%

56_0402_5%

R102

R102

C133

C133

1

@

@

2

R111 closed TigerPoint within 1"

+3VS

R107

SATALED#

GATEA20

SERIRQ

R107

10K_0402_5%

10K_0402_5%

R108

R108
10K_0402_5%

10K_0402_5%
R109

R109

1 2

8.2K_0402_5%

8.2K_0402_5%

3

A A

5

4

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

11 39Tuesday, December 15, 2009

11 39Tuesday, December 15, 2009

11 39Tuesday, December 15, 2009

1

D

D

D

of

of

of

5

4

3

2

1

D D

TGP

U6B

U6B

DMI_TXN0<4>
DMI_TXP0<4>
DMI_RXN0<4>
DMI_RXP0<4>
DMI_TXN1<4>
DMI_TXP1<4>
DMI_RXN1<4>
DMI_RXP1<4>

C C

WLAN

LAN

WWLAN

B B

PCIE_PTX_C_IRX_N2<15>
PCIE_PTX_C_IRX_P2<15>
PCIE_ITX_C_PRX_N2<15>
PCIE_ITX_C_PRX_P2<15>
PCIE_PTX_C_IRX_N3<20>
PCIE_PTX_C_IRX_P3<20>
PCIE_ITX_C_PRX_N3<20>
PCIE_ITX_C_PRX_P3<20>
PCIE_PTX_C_IRX_N4<15>
PCIE_PTX_C_IRX_P4<15>
PCIE_ITX_C_PRX_N4<15>
PCIE_ITX_C_PRX_P4<15>

C142 0.1U_0402_10V6KC142 0.1U_0402_10V6K
C143 0.1U_0402_10V6KC143 0.1U_0402_10V6K

C144 0.1U_0402_10V6KC144 0.1U_0402_10V6K
C145 0.1U_0402_10V6KC145 0.1U_0402_10V6K

C146 0.1U_0402_10V6K@C146 0.1U_0402_10V6K@
C147 0.1U_0402_10V6K@C147 0.1U_0402_10V6K@

Please closed Tiger point
PIN within 500 mils

CLK_PCIE_PCH#<8>
CLK_PCIE_PCH<8>

12
12

12
12

12
12

+1.5VS

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2

PCIE_ITX_PRX_N2

PCIE_ITX_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3

PCIE_ITX_PRX_N3

PCIE_ITX_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4

PCIE_ITX_PRX_N4

PCIE_ITX_PRX_P4

R114 24.9_0402_1%R114 24.9_0402_1%

1 2

R23

DMI0RXN

R24

DMI0RXP

P21

DMI0TXN

P20

DMI0TXP

T21

DMI1RXN

T20

DMI1RXP

T24

DMI1TXN

T25

DMI1TXP

T19

DMI2RXN

T18

DMI2RXP

U23

DMI2TXN

U24

DMI2TXP

V21

DMI3RXN

V20

DMI3RXP

V24

DMI3TXN

V23

DMI3TXP

K21

PERN1

K22

PERP1

J23

PETN1

J24

PETP1

M18

PERN2

M19

PERP2

K24

PETN2

K25

PETP2

L23

PERN3

L24

PERP3

L22

PETN3

M21

PETP3

P17

PERN4

P18

PERP4

N25

PETN4

N24

PETP4

H24

DMI_ZCOMP

J22

DMI_IRCOMP

W23

DMI_CLKN

W24

DMI_CLKP

TIGERPOINT_ES1_BGA360

TIGERPOINT_ES1_BGA360

TGP

USB20_N0

H7

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P

DMI PCI-E

DMI PCI-E

USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

OC0#
OC1#
OC2#
OC3#

USB

USB

OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

USBRBIAS

USBRBIAS#

CLK48

2

2

USB20_P0

H6

USB20_N1

H3

USB20_P1

H2

USB20_N2

J2

USB20_P2

J3

USB20_N3

K6

USB20_P3

K5

USB20_N4

K1

USB20_P4

K2

USB20_N5

L2

USB20_P5

L3

USB20_N6

M6

USB20_P6

M5

USB20_N7

N1

USB20_P7

N2

USB_OC#0_1_D

D4

USB_OC#0_1_D

C5

USB_OC#2

D3

USB_OC#3

D2

USB_OC#4_D

E5

SLP_CHG_M3

E6

SLP_CHG_M4

C2

USB_OC#7

C3

G2
G3

F4

22.6_0402_1%

22.6_0402_1%

CLK_PCH_48M

12

R113

R113
33_0402_5%

33_0402_5%
@

@

1

C148

C148

@

@

22P_0402_50V8J

22P_0402_50V8J

2

For EMI, Close to TigerPoint

R112

R112

R117 0_0402_5%R117 0_0402_5%

USB20_N0 <16>
USB20_P0 <16>
USB20_N1 <16>
USB20_P1 <16>
USB20_N2 <17>
USB20_P2 <17>
USB20_N3 <21>
USB20_P3 <21>
USB20_N4 <16>
USB20_P4 <16>
USB20_N5 <15>
USB20_P5 <15>
USB20_N6 <15>
USB20_P6 <15>
USB20_N7 <17>
USB20_P7 <17>

SLP_CHG_M3 <16>
SLP_CHG_M4 <16>

CLK_PCH_48M <8>

@

@
D5

D5

2 1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

1 2

USB2(Right)
USB1(Right)
BT
Card Reader
USB3(Left)
WWLAN
WLAN
CMOS

Please closed Tiger point
PIN within 200 mils

R115

R115
330K_0402_5%

330K_0402_5%
@

@

1 2

7/17 Reassign Tiger point USB port for TOSHIBA concern

USB PORT LIST

PORT
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7

USB_OC#4_DUSB_OC#0_1_D

DEVICE

USB3(Left)
BT
Card Reader
USB2(Right)
USB1(Right)
WWLAN WWLAN
WLAN
CMOS

USB_OC#3
SLP_CHG_M4
USB_OC#0_1_D

10K_0804_8P4R_5%

10K_0804_8P4R_5%

USB_OC#7
USB_OC#2
USB_OC#4_D
SLP_CHG_M3

10K_0804_8P4R_5%

10K_0804_8P4R_5%

@

@
D6

D6

2 1

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

1 2

R118 0_0402_5%R118 0_0402_5%

+3VALW+3VALW

1 2

Modify

USB2(Right)
USB1(Right)
BT
Card Reader
USB3(Left)

WLAN
CMOS

RP12

RP12
4 5
3 6
2 7
1 8

RP13

RP13
4 5
3 6
2 7
1 8

R116

R116
330K_0402_5%

330K_0402_5%
@

@

+3V_SB

USB_OC#4 <16,22>USB_OC#0_1 <16,22>

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/21 2012/10/21

2009/10/21 2012/10/21

2009/10/21 2012/10/21

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics,Inc

Compal Electronics,Inc

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics,Inc

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

SCHEMATICS,MB A5841

401799

401799

401799

1

of

of

of

12 39Tuesday, December 15, 2009

12 39Tuesday, December 15, 2009

12 39Tuesday, December 15, 2009

D

D

D