COMPAL LA-5752P Schematics
A
1 1
B
C
D
E
Compal Confidential
NIWE2
2 2
Schematics Document
Arrandale
with Intel IBEX PEAK-M core logic
3 3
REV:0.3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/03/25 2008/04/
C
Compal Secret Data
Deciphered Date
Compal Electronics,Ltd.
Title
Cover Sheet
Size Docu ment Numb er R ev
Cus tom
LA-5752P
D
Dat e: Sheet o f
1 51Thur sday, Octobe r 29, 2009
E
0.3
A
Compal confidential
File Name :
ZZ Z
15.6W_PCB_LA5752P
1 1
HDMI
CO NN
page24
VR AM 6 4*16
DD R3*4
page20
NVidia N11M-GE1
page19~ 23
level shift IC
ASM 1 4 42
page25
PCI-E X16
B
intel
Arrandale
(UMA/DIS)
C
POWER BD: LS-5754P
POWER BT
NOVO BT
POWER MANAGE BT
D
CAP SENSOR BD:LS-5752P
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE
E
CARD READER BD:
LS-5753P
RTS5138
HP JACK
MIC JACK
BUTTON & LED
Clock Generator
ICS9LRS3199AKLFT
page12
Socket-rPGA989
37.5mm*37.5mm
page5~9
DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
page 10,11
Dual Channel
100MHz
2.7GT/s
FDI *8
DMI *4
DDR3-800(1.5V)
DDR3-1067(1.5V)
UP TO 8G
2Channel Speaker
page33
CRT Connector
page26
2 2
LVDS
Co nnector
page27
PCI Express
Mini card Slot 1
page28
6*PCI-E B US
PCI Express
Mini card Slot 2
SIM Card
3 3
page28
page28
USB(WWAN)
SPI ROM
BIOS
page13
RTL8111DL-VB-GR
10/100/1G LAN
RJ45 CONN
page29
page30
Intel Ibex Peak M
FCBGA 951
25mm*25mm
LPC BUS
EC
ENE KB926D
Touch Pad
page35
page 13 ~18
page34
Int.KBD
SPI ROM
AZALIA
14*USB2.0
6*SATA serial
page35
page36
Audio Codec
Conexant
CX20671
page33
CMOS Camera
BlueTooth CONN
USB CONN X1(Right)
USB PORT X1(Left)
New Card X1
WWAN
SATA HDD CONN
page32
page27
page37
page28
page28
Analog MIC_Int
page37
page37
Card Reader/Audio Jack SB
CONN
Realtek 5138
MS/MS
pro/SD/SD
pro/mmc/XD
page33
HP X 1+
MIC_Ext X1
ESATA HDD AND USB CONN
page38
page37
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/03/24 2008/04/
SATA ODD CONN
Compal Secret Data
Deciphered Date
page32
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet of
Compal Electronics, Inc.
MB Block Diagram
LA-5752P
2 51Thurs day, October 29, 2009
E
0.3
A
B
C
D
E
DDR3 Voltage Rails
SMBUS Control Table
N10x
Thermal
Sensor
X
X
X
X X
X
X X
X
X
V
+3VS
X
X
+3VS
X
WLAN
WWAN
+5VS
power
plane
1 1
+B
State
+5VALW
+3VALW
+1.5V
+3VS
+1.5VS
+VCCP
+CPU_CO RE
+VGA_CO RE
+1.8VS
+0.75VS
+1.05VS
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
SOURCE
KB926
+3VALW
KB926
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
RAM
M2
X V
X
V
+3VALW
X
BATT KE926 SODIMM CLK CHIP
+3VALW
X
X
X
X
X
X
V
+3VALW
X
X
V V
+3VS
X
N10x
X
X
X
Cap sensor
bo ard
+3VS
NEW
PCH
CARD
X
XX
X
X
V
X X
X
V
+3VS
XXX X X X X X
V
+3VALW
X
X
S0
S3
2 2
S5 S4/AC
S5 S 4/ Batter y only
S5 S 4/AC & Ba ttery
don't e xist
O
O
O
O
X
O
O
O
X
O
X X
X
X X X
OO
I2C / SMBUS ADDRESSING
X
DEVICE
DDR SO-DIMM 0
X
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
@ FUNCTION
EVT NON-USE
45@
100@ 10/100 LAN
GIGA@
UMA_HDMI@
HDMI@
3 3
3G@
X76@
ESATA@
CMOS@
BT@ Blue Tooth
10M@
11M@
UMA@
DIS@
VGA@ FOR NVIDIA PART
HYBRID@ FOR SWITCHABLE
HU@
HD@
SKU
Arrandale(dGPU)
4 4
DIS only
Arrandale(iGPU)
UMA only
Arrandale(iGPU+dGPU)
SWITCHABLE
A
(45 BOM)
GIGA LAN
FOR UMA HDMI components
FOR HDMI components
3G(WWAN) function
(X76 BOM)
ESATA function
Camera function
FOR 10M CHIP
FOR 11M CHIP
UMA only (Arranddale)
DIS only (Arranddale)
SWITCHABLE or UMA only
SWITCHABLE or DIS only
DIS@ / 100@ for EVT
UMA@ / 100@ for EVT
VGA@+HD@+HU@+HYBRID@
PCIE PORT LIST
DEVICEPORT
1
2
LAN
3
3G
4
NEW CARD
5
6
7
8
USB PORT LIST
DEVICEPORT
RIGHT SIDE0
1WLAN
LEFT SIDE
CMOS
2
3
LEFT SIDE
4
RIGHT SIDE
5
CARD READER
6
7
WIRELESS8
9
NEW CARD
10
BT
11
12
3G
13
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/03/24 2008/04/
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
D
Date: Sheet of
Compal Electronics, Inc.
MB Notes List
LA-5752P
3 51Thurs day, October 29, 2009
E
0.3
A
B
C
D
E
Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
GPIO1
GPIO2
1 1
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
2 2
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
3 3
N/A
N/A
IN
-
OUT
H
OUT
H
OUT
H
OUT
-
OUT
-
OUT
-
I/O
L
OUT
L
OUT
I/O
L
IN
-
OUT
-
OUT
- Powe r supply control
IN
-
OUT
-
IN
-
IN
-
IN
-
IN
-
IN
-
IN
-
I/O
Hot pl ug detect for IFP link C
Panel Back-Li ght b rightness(PWM capable)
Pan el Powe r Enab le
Panel Back-Li ght On/Off (PWM)
GPU VID0
GPU VID1
GPU VID2
Thermal Catast rophic Overtemp
Therma l Alert
Memory VREF switch
SLI raster sync
AC pow er det ect pin
MEM_VID orPower supply control
Hot pl ug detect for IFP Link E
Progra mmable Fan Co ntrol
Hot pl ug detect for IFP Link D
Hot pl ug detect for IFP link F
SLI sw ap ready signal
Products
N10P-GS
128bit
1024MB
DDR3
N10P-GE
128bit
1024MB
DDR3
N10P-LP
128bit
1024MB
DDR3
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
Products
N10M-GE
64bit
512MB
DDR3
N10M-GS
64bit
512MB
DDR3
N10M-LP
64bit
512MB
DDR3
Power Sequence
(+3VS)
(1. 05VS)
(+V GA_CORE)
GPIO6
GPU_VID 1 G PU_VID0 VGA _CORE
GPIO5 N10M-GS N10P-GS
0.8V
00
0 1
1 0
1 1
0.85V 12
0.9V
1.0V (N10M-G S)
0.92 5V (N10P- GS)
P-State
12
0,10
(1.8VS)IFPAB_IOVDD
(1.5VS)
GPU Mem NVCLK
(4) (1,5) (6)
(W) (W)
21.07
20.97
15.48
GPU Mem NVCLK
(4) (1,5) (6)
(W) (W)
13.36
14.29
8.28
/MCLK NVVDD
(MHz)
6.67
TBD
6.73
TBD
6.44
TBD
/MCLK NVVDD
(MHz)
2.93
TBD
3.10
TBD
2.91
TBD
(V) (A) (W ) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
TBD
18.25
TBD
19.17
TBD
13.95
(V) (A) (W ) (A) (W)
TBD
11.89
TBD
11.53
TBD
6.60
The ramp ti me for a ny rail mu st be more than 40us
VDD33
PEX_VDD
NVVDD
FBVDDQ
17.34
17.25
11.86
10.70
11.53
5.61
tNVVDD
FBVDD
2.06
2.03
1.90
FBVDD
0.66
0.70
0.62
FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)
3.09
4.09
3.05
4.09 6. 14
2.85
3.99
FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
0.99
2.16
1.05
2.28 3. 42
0.93
2.20
(1.05V)
6.14
850 75 0.14
5.99
810
(1.05V)
3.24
792 75 0.14
3.3
782
0.89
0.88840
0.85
0.83
0.86817
0.82
PLLVDD
75 0.14
75 0.14
PLLVDD
75 0.14
75 0.14
PEX_ VDD can ramp u p any time
tNV- IFPAB_IOV DD
tNV-F BVDDQ
I/O and
PLLVDD
63 0.07
63 0.07
63 0.07
I/O and
PLLVDD
63 0.07
63 0.07
63 0.07
Other
(3.3V)(1.05V)(1.8V)
55 0.18
55 0.18
55 0.18
Other
(3.3V)(1.05V)(1.8V)
100 0.33
100 0.33
100 0.33
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/03/16 2010/03/15
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
D
Date: Sheet of
Compal Electronics, Inc.
VGA Notes List
LA-5752P
4 51Thurs day, October 29, 2009
E
0.3
5
D D
C C
VCC P_POK<46>
FROM P OWER VTT
POWER GOOD S IGNAL
B B
R1 84
1K_ 0402_1%
12
Layout rule 10m il wid th ：trace
length < 0.5 ", spa cing 20mil
+V CCP
H_ PROCH OT#<34, 48>
H_T HERM TRIP#<16>
+V CCP
H_ PM_S YNC<15>
H_ CPU PW RGD< 16>
PM_ DRAM _PWR GD<15>
R1 83
560_ 0402_5%
1 2
BUF _PLT_RS T#<16, 19,28, 29>
R5 64 0_04 02_5%
H_ PECI<16>
+V CCP
1.5K _0402_5 %
4
R5 6020_040 2_1%
1 2
R5 5820_040 2_1%
1 2
R5 4849.9_ 0402_1%
1 2
R5 5749.9_ 0402_1%
1 2
TP_ SKTOCC#
12
R1 6349. 9_04 02_1%
H_P ECI_I SO
1 2
R5 69 68_0 402_5%
12
H_ PROC HOT#
H_T HERM TRIP#
H_ CPUR ST#_ R
12
R1 3568_0 402_5%
H_ PM_ SYNC _R
R1 87
1 2
0_04 02_5%
VC CPW RGOO D_1
R1 90
1 2
0_04 02_5%
VC CPW RGOO D_0
R1 39
1 2
0_04 02_5%
VD DPW RGO OD_R
R1 91
1 2
0_04 02_5%
R1 85
PLT _RST#_R
1 2
12
COM P3
COM P2
COM P1
COM P0
H_ CATE RR#
VTT_POK
R1 86
750_ 0402_1%
JC PU1B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
3
CL K_CP U_BC LK
MISC THERMAL
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
DDR3
MISC
PWR MANAGEMENT
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
AT28
AP27
AN28
TCK
AP28
TMS
AT27
AT29
TDI
AR27
TDO
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
CLK _CPU_ BCLK #
CLK _CPU_ ITP
CLK _CPU_ ITP#
CLK_EX P
CLK_ EXP#
SM_ DRAMR ST#
SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2
PM_EXTTS#0
PM_EXTTS#1
XDP _PRD Y#
XDP _PREQ#
XDP _TCK
XDP_TMS
XDP_TR ST#
XDP _TDI
XDP _TDO
R5 55 0_04 02_5%
XDP _DBRES ET#
XDP_B PM#0
XDP_B PM#1
XDP_B PM#2
XDP_B PM#3
XDP_B PM#4
XDP_B PM#5
XDP_B PM#6
XDP_B PM#7
T17 PA D
T18 PA D
3
1 2
R5 63 0_04 02_5%
T19 PA D
12
CL K_CPU _BCL K <16>
CLK _CPU_ BCLK # <16>
CLK_EX P <14>
pins u nused by
Clarks field on the
rPGA98 9 Pack age
CLK_E XP# <14>
PM_EX TTS#1_R <1 0,11>
2
DDR3 C ompensation Signals
SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2
PM_EXTTS#0
PM_EXTTS#1
XDP _PREQ#
XDP_TMS
XDP _TDI
XDP _TDO
XDP _TCK
XDP_TR ST#
XDP _DBRES ET#
1 2
R5 67 100_ 0402_1%
1 2
R5 66 24.9 _0402_1 %
1 2
R5 65 130_ 0402_1%
Layout Note:Please these
resist ors near Processor
1 2
R5 61 10K _0402_5%
1 2
R5 62 10K _0402_5%
R1 36 51_0 402_1%@
1 2
R1 38 51_0 402_1%@
1 2
R5 56 51_0 402_1%@
1 2
R1 34 51_0 402_5%
1 2
R5 7 51_0 402_1%@
1 2
R1 33 51_0 402_5%
1 2
R1 37
1K_ 0402_5%@
1 2
1
+V CCP
+3VS
CHECK INTEL DOCUMENT #385422
Debug Port Design Guide Rev1.3
+1.5V
For In tel S3 Power Reduc tion.
5
+3V ALW
5
U8
2
P
B
DR AM_ PWRG D
VCC P_POK<46>
A A
VCC P_PO K
2N70 02_SOT2 3
5
4
Y
1
A
G
MC7 4VHC1 G08D FT2G SC70 5P
3
+5V ALW
12
R6 10
10K _0402_5%
S3_ 0.75V _EN
13
D
2
G
Q42
S
4
R1 95
1 2
1.5K _0402 _1%
750_ 0402_1%
S3_ 0.75V _EN <44>
R1 94
12
+1.5 V
12
R1 93
1.1K _0402_1 %
@
VD DPW RGO OD_R
12
R1 92
3K_ 0402_1%
@
R3 01
DDR3 CONN ECT ER
DRA MRST#<10, 11>
PCH GPIO CON TROL
DRA MRST _CNTR L_PC H<16>
DRA MRST _CNTR L_EC<34>
EC GPIO C ONT ROL
1K_ 0402_1%
1 2
1 2
R2 81 0_04 02_5%
1 2
R2 82 0_04 02_5%@
1 2
DRA MRST# SM_ DRAMR ST#
2N70 02_SOT 23
DRA MRST _CNTR L_R
C3 38
6
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
For In tel S3 Power Reduc tion.
@
R3 000 _0402_ 5%
D
S
1 3
Q27
G
2
1
0.01 U_040 2_16V7K
2
2
12
R2 83 100K _0402_5 %
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
3
Title
Compal Electronics, Inc.
Arrandale(1/5)-Thermal/XDP
LA-5752P
1
5 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
JC PU1A
DMI _CRX_PTX _N0<15>
DMI _CRX_PTX _N1<15>
DMI _CRX_PTX _N2<15>
DMI _CRX_PTX _N3<15>
DMI_C RX_PTX_P 0<15>
DMI_C RX_PTX_P 1<15>
D D
DMI_C RX_PTX_P 2<15>
DMI_C RX_PTX_P 3<15>
DMI _CTX_PRX _N0<15>
DMI _CTX_PRX _N1<15>
DMI _CTX_PRX _N2<15>
DMI _CTX_PRX _N3<15>
DMI_C TX_PRX_P 0<15>
DMI_C TX_PRX_P 1<15>
DMI_C TX_PRX_P 2<15>
DMI_C TX_PRX_P 3<15>
FDI _CTX_ PRX_N0<15>
FDI _CTX_ PRX_N1<15>
FDI _CTX_ PRX_N2<15>
FDI _CTX_ PRX_N3<15>
FDI _CTX_ PRX_N4<15>
FDI _CTX_ PRX_N5<15>
FDI _CTX_ PRX_N6<15>
FDI _CTX_ PRX_N7<15>
FDI _CTX_PRX _P0<15 >
FDI _CTX_PRX _P1<15 >
FDI _CTX_PRX _P2<15 >
FDI _CTX_PRX _P3<15 >
FDI _CTX_PRX _P4<15 >
FDI _CTX_PRX _P5<15 >
C C
FDI _CTX_PRX _P6<15 >
FDI _CTX_PRX _P7<15 >
FD I_F SYN C0<15>
FD I_F SYN C1<15>
FD I_I NT< 15>
FD I_L SYN C0<15>
FD I_L SYN C1<15>
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_F SYN C0
FD I_F SYN C1
FD I_I NT
FD I_L SY NC0
FD I_L SY NC1
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RCOMPO
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
B B
FD I_F SYN C0
FD I_F SYN C1
FD I_I NT
FD I_L SY NC0
FD I_L SY NC1
A A
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
R5 32 1K_ 0402_5%DI S@
1 2
R5 36 1K_ 0402_5%DI S@
1 2
R5 34 1K_ 0402_5%DI S@
1 2
R5 33 1K_ 0402_5%DI S@
1 2
R5 35 1K_ 0402_5%DI S@
1 2
PEG_ICOMPI
PEG_ICOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
4
EXP _ICOMPI
1 2
EXP _RBIAS
1 2
PCI E_CRX _GTX_N15
PCI E_CRX _GTX_N14
PCI E_CRX _GTX_N13
PCI E_CRX _GTX_N12
PCI E_CRX _GTX_N11
PCI E_CRX _GTX_N10
PCI E_CRX _GTX_N9
PCI E_CRX _GTX_N8
PCI E_CRX _GTX_N7
PCI E_CRX _GTX_N6
PCI E_CRX _GTX_N5
PCI E_CRX _GTX_N4
PCI E_CRX _GTX_N3
PCI E_CRX _GTX_N2
PCI E_CRX _GTX_N1
PCI E_CRX _GTX_N0
PCI E_CRX_GT X_P15
PCI E_CRX_GT X_P14
PCI E_CRX_GT X_P13
PCI E_CRX_GT X_P12
PCI E_CRX_GT X_P11
PCI E_CRX_GT X_P10
PCI E_CRX_GTX _P9
PCI E_CRX_GTX _P8
PCI E_CRX_GTX _P7
PCI E_CRX_GTX _P6
PCI E_CRX_GTX _P5
PCI E_CRX_GTX _P4
PCI E_CRX_GTX _P3
PCI E_CRX_GTX _P2
PCI E_CRX_GTX _P1
PCI E_CRX_GTX _P0
PCI E_CT X_GRX_C _N15
PCI E_CT X_GRX_C _N14
PCI E_CT X_GRX_C _N13
PCI E_CT X_GRX_C _N12
PCI E_CT X_GRX_C _N11
PCI E_CT X_GRX_C _N10
PCI E_CT X_GRX_C _N9
PCI E_CT X_GRX_C _N8
PCI E_CT X_GRX_C _N7
PCI E_CT X_GRX_C _N6
PCI E_CT X_GRX_C _N5
PCI E_CT X_GRX_C _N4
PCI E_CT X_GRX_C _N3
PCI E_CT X_GRX_C _N2
PCI E_CT X_GRX_C _N1
PCI E_CT X_GRX_C _N0
PCI E_CTX _GRX_C_P1 5
PCI E_CTX _GRX_C_P1 4
PCI E_CTX _GRX_C_P1 3
PCI E_CTX _GRX_C_P1 2
PCI E_CTX _GRX_C_P1 1
PCI E_CTX _GRX_C_P1 0
PCI E_CTX _GRX_C_P9
PCI E_CTX _GRX_C_P8
PCI E_CTX _GRX_C_P7
PCI E_CTX _GRX_C_P6
PCI E_CTX _GRX_C_P5
PCI E_CTX _GRX_C_P4
PCI E_CTX _GRX_C_P3
PCI E_CTX _GRX_C_P2
PCI E_CTX _GRX_C_P1
PCI E_CTX _GRX_C_P0
Layout rule tr：ace
length < 0.5"
R5 44 49.9 _0402_1 %
R5 45 750_ 0402_1%
PCI E_CRX _GTX _N[0..15] <19>
PCI E_CRX _GTX_P [0..15] <19>
PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal
VGA@
C5 27 0.1U _0402 _10V6K
1 2
C5 40 0.1U _0402 _10V6K
1 2
C5 29 0.1U _0402 _10V6K
1 2
C5 42 0.1U _0402 _10V6K
1 2
C5 31 0.1U _0402 _10V6K
1 2
C5 44 0.1U _0402 _10V6K
1 2
C5 33 0.1U _0402 _10V6K
1 2
C5 46 0.1U _0402 _10V6K
1 2
C5 35 0.1U _0402 _10V6K
1 2
C5 62 0.1U _0402 _10V6K
1 2
C5 64 0.1U _0402 _10V6K
1 2
C5 55 0.1U _0402 _10V6K
1 2
C5 57 0.1U _0402 _10V6K
1 2
C5 61 0.1U _0402 _10V6K
1 2
C5 48 0.1U _0402 _10V6K
1 2
C5 59 0.1U _0402 _10V6K
1 2
C5 28 0.1U _0402 _10V6K
1 2
C5 41 0.1U _0402 _10V6K
1 2
C5 30 0.1U _0402 _10V6K
1 2
C5 43 0.1U _0402 _10V6K
1 2
C5 32 0.1U _0402 _10V6K
1 2
C5 45 0.1U _0402 _10V6K
1 2
C5 34 0.1U _0402 _10V6K
1 2
C5 47 0.1U _0402 _10V6K
1 2
C5 36 0.1U _0402 _10V6K
1 2
C5 63 0.1U _0402 _10V6K
1 2
C5 65 0.1U _0402 _10V6K
1 2
C5 56 0.1U _0402 _10V6K
1 2
C5 58 0.1U _0402 _10V6K
1 2
C5 60 0.1U _0402 _10V6K
1 2
C5 49 0.1U _0402 _10V6K
1 2
C5 50 0.1U _0402 _10V6K
1 2
PCI E_CTX _GRX_N15
PCI E_CTX _GRX_N14
PCI E_CTX _GRX_N13
PCI E_CTX _GRX_N12
PCI E_CTX _GRX_N11
PCI E_CTX _GRX_N10
PCI E_CTX _GRX_N9
PCI E_CTX _GRX_N8
PCI E_CTX _GRX_N7
PCI E_CTX _GRX_N6
PCI E_CTX _GRX_N5
PCI E_CTX _GRX_N4
PCI E_CTX _GRX_N3
PCI E_CTX _GRX_N2
PCI E_CTX _GRX_N1
PCI E_CTX _GRX_N0
PCI E_CTX_G RX_P15
PCI E_CTX_G RX_P14
PCI E_CTX_G RX_P13
PCI E_CTX_G RX_P12
PCI E_CTX_G RX_P11
PCI E_CTX_G RX_P10
PCI E_CTX_GRX _P9
PCI E_CTX_GRX _P8
PCI E_CTX_GRX _P7
PCI E_CTX_GRX _P6
PCI E_CTX_GRX _P5
PCI E_CTX_GRX _P4
PCI E_CTX_GRX _P3
PCI E_CTX_GRX _P2
PCI E_CTX_GRX _P1
PCI E_CTX_GRX _P0
PCI E_CT X_GRX _N[0..15] <19>
PCI E_CT X_GRX_P [0..15] <19>
3
R5 9
@
1 2
3.01 K_040 2_1%
FOR ES1 S AMP LE ONLY
R5 47
0_04 02_5%
@
1 2
@
1 2
R5 46
0_04 02_5%
CFG Straps for PROCESSOR
CF G0
PCI-Ex press Configuration Select
CFG0
Not ap plica ble f or Clarksfield Processor
CFG[1:0] 11 =1*16 PEG
CF G3
CFG3-P CI Ex press Static Lane Reversal
CF G4
CFG4-D isplay Port Presence
CFG4
@
1 2
R5 8 3. 01K_0 402_1%
1: Single PEG
0: Bif urcation enabled
10=2*8 PEG
1 2
R6 1 3. 01K_0 402_1%
1: Nor mal Operation
0: Lan e Numbers Reversed
CFG3
15 -> 0, 14 ->1, .....
@
1 2
R6 0 3. 01K_0 402_1%
1: Dis abled ; No Physical Display Port
attach ed to Embedded Display Port
0: Ena bled; An external Display Port
device is c onnected to the Embedded
Display Port
CF G0
CF G3
CF G4
CF G7
H_ RSV D17_R
H_ RSV D18_R
2
JC PU1E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
RESERVED
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
1
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AP1
AT2
AT3
AR1
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
KEY
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
VSS
RS VD6 4_R
RS VD6 5_R
R1 89
0_04 02_5%
R1 88
0_04 02_5%
@
12
@
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Arrandale(2/5)-DMI/PEG/FDI
LA-5752P
1
6 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
4
3
2
1
AR10
AT10
JC PU1 D
W8
SB_CK[0]
W9
SB_CK#[0]
B5
SB_DQ[0]
A5
SB_DQ[1]
C3
SB_DQ[2]
B3
SB_DQ[3]
E4
SB_DQ[4]
A6
SB_DQ[5]
A4
SB_DQ[6]
C4
SB_DQ[7]
D1
SB_DQ[8]
D2
SB_DQ[9]
F2
SB_DQ[10]
F1
SB_DQ[11]
C2
SB_DQ[12]
F5
SB_DQ[13]
F3
SB_DQ[14]
G4
SB_DQ[15]
H6
SB_DQ[16]
G2
SB_DQ[17]
J6
SB_DQ[18]
J3
SB_DQ[19]
G1
SB_DQ[20]
G5
SB_DQ[21]
J2
SB_DQ[22]
J1
SB_DQ[23]
J5
SB_DQ[24]
K2
SB_DQ[25]
L3
SB_DQ[26]
M1
SB_DQ[27]
K5
SB_DQ[28]
K4
SB_DQ[29]
M4
SB_DQ[30]
N5
SB_DQ[31]
AF3
SB_DQ[32]
AG1
SB_DQ[33]
AJ3
SB_DQ[34]
AK1
SB_DQ[35]
AG4
SB_DQ[36]
AG3
SB_DQ[37]
AJ4
SB_DQ[38]
AH4
SB_DQ[39]
AK3
SB_DQ[40]
AK4
SB_DQ[41]
AM6
SB_DQ[42]
AN2
SB_DQ[43]
AK5
SB_DQ[44]
AK2
SB_DQ[45]
AM4
SB_DQ[46]
AM3
SB_DQ[47]
AP3
SB_DQ[48]
AN5
SB_DQ[49]
AT4
SB_DQ[50]
AN6
SB_DQ[51]
AN4
SB_DQ[52]
AN3
SB_DQ[53]
AT5
SB_DQ[54]
AT6
SB_DQ[55]
AN7
SB_DQ[56]
AP6
SB_DQ[57]
AP8
SB_DQ[58]
AT9
SB_DQ[59]
AT7
SB_DQ[60]
AP9
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AB1
SB_BS[0]
W5
SB_BS[1]
R7
SB_BS[2]
AC5
SB_CAS#
Y7
SB_RAS#
AC6
SB_WE#
DDR SYSTEM MEMORY - B
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M3
V7
V6
M2
AB8
AD6
AC7
AD1
D4
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DD R_B_ DM0
DD R_B_ DM1
DD R_B_ DM2
DD R_B_ DM3
DD R_B_ DM4
DD R_B_ DM5
DD R_B_ DM6
DD R_B_ DM7
DD R_B_ DQS# 0
DD R_B_ DQS# 1
DD R_B_ DQS# 2
DD R_B_ DQS# 3
DD R_B_ DQS# 4
DD R_B_ DQS# 5
DD R_B_ DQS# 6
DD R_B_ DQS# 7
DD R_B _DQS 0
DD R_B _DQS 1
DD R_B _DQS 2
DD R_B _DQS 3
DD R_B _DQS 4
DD R_B _DQS 5
DD R_B _DQS 6
DD R_B _DQS 7
DDR_ B_M A0
DDR_ B_M A1
DDR_ B_M A2
DDR_ B_M A3
DDR_ B_M A4
DDR_ B_M A5
DDR_ B_M A6
DDR_ B_M A7
DDR_ B_M A8
DDR_ B_M A9
DDR_ B_MA 10
DDR_ B_MA 11
DDR_ B_MA 12
DDR_ B_MA 13
DDR_ B_MA 14
DDR_ B_MA 15
M_ CLK_D DR2 < 11>
M_ CLK_D DR#2 <11>
DDR_ CKE2 _DIM MB <11>
M_ CLK_D DR3 < 11>
M_ CLK_D DR#3 <11>
DDR_ CKE3 _DIM MB <11>
DDR_ CS2_ DIMM B# <11>
DDR_ CS3_ DIMM B# <11>
M_ODT 2 <11>
M_ODT 3 <11>
DD R_B_ DM[0 ..7] < 11>
DD R_B_ DQS# [0..7 ] <11>
DD R_B _DQS [0..7 ] <11>
DDR_ B_MA [0.. 15] <1 1>
JC PU1 C
D D
DD R_A _D[0 ..63]<10>
C C
B B
DD R_A_B S0<10>
DD R_A_B S1<10>
DD R_A_B S2<10>
DD R_A_ CAS#<10>
DD R_A_ RAS#<10>
DD R_A _WE#<10>
DD R_A _D0
DD R_A _D1
DD R_A _D2
DD R_A _D3
DD R_A _D4
DD R_A _D5
DD R_A _D6
DD R_A _D7
DD R_A _D8
DD R_A _D9
DD R_A _D10
DD R_A _D11
DD R_A _D12
DD R_A _D13
DD R_A _D14
DD R_A _D15
DD R_A _D16
DD R_A _D17
DD R_A _D18
DD R_A _D19
DD R_A _D20
DD R_A _D21
DD R_A _D22
DD R_A _D23
DD R_A _D24
DD R_A _D25
DD R_A _D26
DD R_A _D27
DD R_A _D28
DD R_A _D29
DD R_A _D30
DD R_A _D31
DD R_A _D32
DD R_A _D33
DD R_A _D34
DD R_A _D35
DD R_A _D36
DD R_A _D37
DD R_A _D38
DD R_A _D39
DD R_A _D40
DD R_A _D41
DD R_A _D42
DD R_A _D43
DD R_A _D44
DD R_A _D45
DD R_A _D46
DD R_A _D47
DD R_A _D48
DD R_A _D49
DD R_A _D50
DD R_A _D51
DD R_A _D52
DD R_A _D53
DD R_A _D54
DD R_A _D55
DD R_A _D56
DD R_A _D57
DD R_A _D58
DD R_A _D59
DD R_A _D60
DD R_A _D61
DD R_A _D62
DD R_A _D63
AJ10
AL10
AK12
AK11
AM10
AR11
AL11
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
A10
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
AG5
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39]
SA_DQ[40]
AJ9
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
AK8
SA_DQ[44]
AL7
SA_DQ[45]
SA_DQ[46]
AL8
SA_DQ[47]
AN8
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
AM9
SA_DQ[52]
AN9
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
DDR SYSTEM MEMORY A
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7
DD R_A_ DQS# 0
DD R_A_ DQS# 1
DD R_A_ DQS# 2
DD R_A_ DQS# 3
DD R_A_ DQS# 4
DD R_A_ DQS# 5
DD R_A_ DQS# 6
DD R_A_ DQS# 7
DD R_A _DQS 0
DD R_A _DQS 1
DD R_A _DQS 2
DD R_A _DQS 3
DD R_A _DQS 4
DD R_A _DQS 5
DD R_A _DQS 6
DD R_A _DQS 7
DDR_ A_M A0
DDR_ A_M A1
DDR_ A_M A2
DDR_ A_M A3
DDR_ A_M A4
DDR_ A_M A5
DDR_ A_M A6
DDR_ A_M A7
DDR_ A_M A8
DDR_ A_M A9
DDR_ A_MA 10
DDR_ A_MA 11
DDR_ A_MA 12
DDR_ A_MA 13
DDR_ A_MA 14
DDR_ A_MA 15
M_ CLK_D DR0 <1 0>
M_C LK_DD R#0 < 10>
DDR_ CKE0 _DIMM A <10>
M_ CLK_D DR1 <1 0>
M_C LK_DD R#1 < 10>
DDR_ CKE1 _DIMM A <10>
DDR_ CS0_ DIMM A# <10>
DDR_ CS1_ DIMM A# <10>
M_ODT 0 <10>
M_ODT 1 <10>
DD R_A_ DM[0 ..7] < 10>
DD R_A_ DQS# [0..7 ] <10>
DD R_A_ DQS[ 0..7] <10>
DDR_ A_MA [0.. 15] <10 >
DD R_B _D[0 ..63]<11>
DD R_B_B S0<11>
DD R_B_B S1<11>
DD R_B_B S2<11>
DD R_B_ CAS#<11>
DD R_B_ RAS#<11>
DD R_B_ WE#<11>
DD R_B _D0
DD R_B _D1
DD R_B _D2
DD R_B _D3
DD R_B _D4
DD R_B _D5
DD R_B _D6
DD R_B _D7
DD R_B _D8
DD R_B _D9
DD R_B _D10
DD R_B _D11
DD R_B _D12
DD R_B _D13
DD R_B _D14
DD R_B _D15
DD R_B _D16
DD R_B _D17
DD R_B _D18
DD R_B _D19
DD R_B _D20
DD R_B _D21
DD R_B _D22
DD R_B _D23
DD R_B _D24
DD R_B _D25
DD R_B _D26
DD R_B _D27
DD R_B _D28
DD R_B _D29
DD R_B _D30
DD R_B _D31
DD R_B _D32
DD R_B _D33
DD R_B _D34
DD R_B _D35
DD R_B _D36
DD R_B _D37
DD R_B _D38
DD R_B _D39
DD R_B _D40
DD R_B _D41
DD R_B _D42
DD R_B _D43
DD R_B _D44
DD R_B _D45
DD R_B _D46
DD R_B _D47
DD R_B _D48
DD R_B _D49
DD R_B _D50
DD R_B _D51
DD R_B _D52
DD R_B _D53
DD R_B _D54
DD R_B _D55
DD R_B _D56
DD R_B _D57
DD R_B _D58
DD R_B _D59
DD R_B _D60
DD R_B _D61
DD R_B _D62
DD R_B _D63
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
Arrandale(3/5)-DDR III
LA-5752P
1
7 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
+C PU_C ORE
JC PU1 F
D D
C C
B B
A A
48A 15A18A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
CPU CO RE SUP PLY
5
POWER
1.1V R AIL PO WER
CPU VI DS
SENSE LINES
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AH14
10U_ 0805_10 V4K
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
G15
VTT_S ELECT
H_ VID 0
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
H_ VID 5
H_ VID 6
PM_ DPRS LPVR _R
10U_ 0805_10 V4K
C2 01
1
1
2
2
10U_ 0805_10 V4K
10U_ 0805_10 V4K
C2 71
1
1
@
2
2
10U_ 0805_10 V4K
C2 08
1
1
2
2
R6 08 1K_ 0402_5%
1 2
R5 6 0_ 0402_5%
C1 99
1
2
C2 70
1
@
2
+V CCP
10U_ 0805_10 V4K
C2 09
1 2
PSI # <48>
H_ VID [0..6 ] <48>
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
H_VTTVID1 = High, 1.05V FOR Auburndale
AN35
AJ34
AJ35
B15
A15
VCC _SEN SE
VSS _SENS E
IMV P_IMON <48>
0_04 02_5%
R5 54
1 2
1 2
R5 53 0_04 02_5%
VTT_S ENSE <4 6>
@
T15PA D
Clo se to CP U
VCC SENS E
VSS SENSE
1 2
R5 52 10 0_0402_ 1%
1 2
R5 51 10 0_0402_ 1%
10U_ 0805_10 V4K
C1 98
10U_ 0805_10 V4K
C2 16
10U_ 0805_10 V4K
1
2
10U_ 0805_10 V4K
1
2
1
2
VCC SENS E
VSS SENSE
4
C1 81
1
+
2
C1 82
1
2
10U_ 0805_ 10V4K
C2 19
+C PU_C ORE
4
+V CCP
330U _D2_2 .5VY _R9M
C5 54
10U_ 0805_10 V4K
C2 00
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 74
C2 17
1
1
2
2
PR OC_DP RSLP VR <48 >
VTT_S ELECT <46 >
VC CSEN SE <48>
VSS SENSE <48>
+V CCP
3
+GF X_CORE
22U_ 0805_ 6.3V6M
1
C1 60
C1 61
@
2
22U_ 0805_6. 3V6M
12
R5 59
0_04 02_5%
DI S@
10U_ 0805_ 10V4K
C2 07
1
2
CPU
1
C1 91
@
2
22U_ 0805_6. 3V6M
1
SUS P<39, 44,45>
22U_ 0805_6. 3V6M
1
C1 90
@
2
22U_ 0805_ 6.3V6M
1
1
C1 89
@
UMA @
2
2
22U_ 0805_6. 3V6M
+V CCP
1
2
+1.5 V + 1.5V_ DDR3
+5V ALW
R2 68
20K _0402_5%
1.5V _DDR 3_GAT E
13
D
2
G
S
3
1
1
C5 91
C1 59
UMA @
UMA @
2
2
10U_ 0805_ 6.3V6M
10U_ 0805_10 V4K
10U_ 0805_10 V4K
C2 15
C2 14
1
2
J3
2
JUM P_43X118
@
J2
2
JUM P_43X118
@
U1 1
8
D
7
D
6
D
5
D
SI4 800BD Y-T1-E 3_SO8
Q23
2N70 02_SOT2 3
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10U_ 0805_ 6.3V6M
1
C5 92
UMA @
2
+V CCP
10U_ 0805_ 10V4K
C2 10
1
2
10U_ 0805_10 V4K
C2 72
1
2
112
112
1
S
2
S
3
S
4
G
R2 67
0_04 02_5%
@
1 2
1
2
1
2
JC PU1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
10U_ 0805_ 10V4K
C2 11
10U_ 0805_10 V4K
C2 40
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC, AUB_C FD_r PGA, R1P0
ME@
GRAPHI CS
FDI PEG & DMI
For In tel S3 Power Reduc tion.
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C2 89
1
1
2
+1 .5V_D DR3
1
C3 25
0.1U _0603 _25V7K
2
2008/10/31 2009/10/31
2
Compal Secret Data
POWER
+1.5 V
0.1U _0402 _10V6K
C2 88
C2 87
1
2
Deciphered Date
2
SENSE
3A
0.6A
1
2
2
LINES
GRA PHI CS VIDs
0.1U _0402 _10V6K
VAXG_SENSE
VSSAXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
DDR3 - 1.5V RAILS
1.1V1.8V
VCCPLL1
VCCPLL2
VCCPLL3
C2 86
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
AN24
GFX _VR_E N
AR25
AT25
GFX _IMON
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
2
SUS P
UMA @
1 2
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C2 54
1
1
2
2
22U_ 0805_6. 3V6M
220U _B2_ 2.5VM_R3 5
C2 68
1
1
+
@
2
2
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C1 67
C1 49
1
2
1
1
2
2
+1 .5V_ DDR3
0.1U _0402 _10V6K
C2 69
1
@
2
2
G
For In tel S3 Power Reduc tion.
1
GFX _IMON
R1 32
DI S@
1K_ 0402_5%
12
AS NO CONNECT
BUT A SMALL AMOUNT OF POWER
VCC _AXG_S ENSE < 47>
VSS_A XG_SENS E <47>
GFX VR_V ID_0 <47>
GFX VR_V ID_1 <47>
GFX VR_V ID_2 <47>
GFX VR_V ID_3 <47>
GFX VR_V ID_4 <47>
GFX VR_V ID_5 <47>
GFX VR_V ID_6 <47>
R1 41 0_04 02_5%
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C2 53
C2 56
1
1
2
2
22U_ 0805_6. 3V6M
Modify for cost revew.
C2 58
C2 52
1
09/16/2009
2
+V CCP
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 73
1
1
2
2
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 18
1
1
2
2
2.2U _0603 _6.3V 4Z
10U_ 0805_ 10V4K
C1 68
C1 69
1
2
12
R2 33
220_ 0402_5%
13
D
Q19
BSS 138_NL_ SOT23-3
S
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
(~15MW ) MAYB E WASTED
DESIGN GU IDE RE V1.1
R1 40
1 2
UMA @
1
+1 .5V_D DR3
1U_0 603_1 0V4Z
C2 55
1
2
C2 12
+VC CP
C2 13
+1.8V S
4.7U _0603 _6.3V6K
C1 70
1
2
GFX _VR_E N
GFX VR_EN <47>
GFX VR_D PRSLPV R <47>
GFX VR_IMO N <47>
C2 57
Compal Electronics, Inc.
Arrandale(4/5)-PWR
LA-5752P
1
8 5 1Thur sday , Oc tobe r 29, 2009
4.7K _0402 _5%
0. 3
5
JC PU1 H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
D D
C C
B B
AR17
AR15
AR12
AP20
AP17
AP13
AP10
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AL34
AL31
AL23
AL20
AL17
AL12
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AG10
AE35
VSS8
VSS9
VSS10
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
VSS15
VSS16
VSS17
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
4
JC PU1 I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
VSS
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
NCTF
AT1
AR34
B34
B2
B1
A35
VSS _NCT F2_R
VSS _NCT F3_R
VSS _NCT F4_R
VSS _NCT F5_R
VSS _NCT F6_R
VSS _NCT F7_R
VSS _NCT F1_R
AT35
3
+C PU_C ORE
2
1
CPU CORE
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 85
C5 68
1
1
2
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 63
C1 47
1
1
2
2
10U_ 0805_6. 3V6M
10U_ 0805_6. 3V6M
C1 92
C1 95
1
1
2
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 80
1
2
10U_ 0805_ 6.3V6M
C1 62
1
2
10U_ 0805_6. 3V6M
C8 8
1
2
22U_ 0805_6. 3V6M
C5 79
1
2
1
2
1
2
C5 74
1
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 93
C1 79
1
2
10U_ 0805_6. 3V6M
10U_ 0805_6. 3V6M
C1 96
C1 80
1
2
Under cavity
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 84
C5 73
1
1
2
2
10U_ 0805_ 6.3V6M
C1 66
1
1
2
2
10U_ 0805_6. 3V6M
C8 9
1
1
2
2
C5 78
1
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 48
C1 65
1
2
10U_ 0805_6. 3V6M
C1 97
22U_ 0805_6. 3V6M
C5 83
1
2
1
2
1
2 3
C5 77
1
2
10U_ 0805_ 6.3V6M
C1 94
between Inductor and socket
470U _D2T_2VM
470U _D2T_2VM
C7 6
C7 5
1
+
+
2 3
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 71
C5 72
1
1
2
470U _D2T_2VM
1
+
2 3
2
C9 2
1
+
2 3
Inside cavity
470U _D2T_2VM
C1 64
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C9 1
1
1
2
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C9 0
C1 29
C8 7
1
1
2
2
470uF 4.5mohm
IC, AUB_C FD_r PGA, R1P0
ME@
A A
5
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Arrandale(5/5)-GND/Bypass
LA-5752P
1
9 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
+VR EF_D Q_DIMM A
+VR EF_D Q_DIMM A
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C3 03
1
1
2
D D
C C
B B
A A
2
DDR_ CKE0 _DIMM A<7>
DDR_ A_BS 2<7>
M_ CLK_D DR0<7>
M_C LK_DD R#0< 7>
DDR_ A_BS 0<7>
DD R_A_ WE#<7>
DD R_A_ CAS#< 7>
DDR_ CS1_ DIMM A#<7>
+3VS
1
2
5
DD R_A _D0
C3 47
DD R_A _D1
DD R_A_ DM0
DD R_A _D2
DD R_A _D3
DD R_A _D8
DD R_A _D9
DD R_A_ DQS# 1
DD R_A _DQS 1
DD R_A _D10
DD R_A _D11
DD R_A _D16
DD R_A _D17
DD R_A_ DQS# 2
DD R_A _DQS 2
DD R_A _D18
DD R_A _D19
DD R_A _D24
DD R_A _D25
DD R_A_ DM3
DD R_A _D26
DD R_A _D27
DDR_ CKE0 _DIM MA
DD R_A_ BS2
DDR_ A_MA 12
DDR_ A_M A9
DDR_A_MA8
DDR_ A_M A5
DDR_ A_M A3
DDR_ A_M A1
M _CLK_ DDR0
M _CLK_ DDR#0
DDR_ A_MA 10
DD R_A_ BS0
DD R_A _WE#
DD R_A_ CAS# M_OD T0
DDR_ A_MA 13
DDR_ CS1_ DIMM A#
DD R_A _D32
DD R_A _D33
DD R_A_ DQS# 4
DD R_A _DQS 4
DD R_A _D34
DD R_A _D35
DD R_A _D40
DD R_A _D41
DD R_A_ DM5
DD R_A _D42
DD R_A _D43
DD R_A _D48
DD R_A _D49
DD R_A_ DQS# 6
DD R_A _DQS 6
DD R_A _D50
DD R_A _D51
DD R_A _D56
DD R_A _D57
DD R_A_ DM7
DD R_A _D58
DD R_A _D59
1 2
10K _0402_5%
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C6 08
C6 17
1
2
+1.5 V + 1.5V
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
DDR3 SO-DIMM A
JDI MM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
R5 70
10K _0402_5%
12
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
R5 71
VTT1
205
G1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
FOX _AS0 A626-U4S N-7F
ME@
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
4
DD R_A _D4
DD R_A _D5
DD R_A_ DQS# 0
DD R_A _DQS 0
DD R_A _D6
DD R_A _D7
DD R_A _D12
DD R_A _D13
DD R_A_ DM1
DRA MRST#
DD R_A _D14
DD R_A _D15
DD R_A _D20
DD R_A _D21
DD R_A_ DM2
DD R_A _D22
DD R_A _D23
DD R_A _D28
DD R_A _D29
DD R_A_ DQS# 3
DD R_A _DQS 3
DD R_A _D30
DD R_A _D31
DDR_ CKE1 _DIM MA
DDR_ A_MA 15
DDR_ A_MA 14
DDR_A_MA 11
DDR_ A_M A7
DDR_A_MA6
DDR_ A_M A4
DDR_ A_M A2
DDR_ A_M A0
M _CLK_ DDR1
M _CLK_ DDR#1
DD R_A_ BS1
DD R_A_ RAS#
DDR_ CS0_ DIMM A#
M_OD T1
DD R_A _D36
DD R_A _D37
DD R_A_ DM4
DD R_A _D38
DD R_A _D39
DD R_A _D44
DD R_A _D45
DD R_A_ DQS# 5
DD R_A _DQS 5
DD R_A _D46
DD R_A _D47
DD R_A _D52
DD R_A _D53
DD R_A_ DM6
DD R_A _D54
DD R_A _D55
DD R_A _D60
DD R_A _D61
DD R_A_ DQS# 7
DD R_A _DQS 7
DD R_A _D62
DD R_A _D63
PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3
+0.7 5VS
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V6 5A @ 0. 7 5V
4
DRA MRST# <5,11>
DDR_ CKE1 _DIMM A <7>
M_ CLK_D DR1 <7>
M_C LK_DD R#1 <7>
DDR_ A_BS 1 <7>
DD R_A_ RAS# <7>
DDR_ CS0_ DIMM A# <7>
M_ODT 0 <7>
M_ODT 1 <7>
0.1U _0402 _10V6K
C3 46
1
1
2
2
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
VREF =
1*0402 0.1uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
PM_EX TTS#1_R <5 ,11>
SMB_D ATA_S3 <11,1 2,14,28 >
SMB _CLK_S3 <11, 12,14, 28>
DD R_A _D[0 ..63]<7>
DD R_A_ DM[0 ..7]<7>
DD R_A _DQS [0..7 ]<7>
DD R_A_ DQS# [0..7 ]<7>
DDR_ A_MA [0.. 15]<7>
+VR EF_D Q_DIMM A
2.2U _0603 _6.3V 4Z
C3 55
4*0402 1uf
1*0402 2.2uf
3
Lay ou t N ote:
Pl ace near DIM M
+1.5 V
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
C5 88
C5 89
1
1
@
@
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
C5 81
C5 86
1
2
+0.7 5VS
C6 07
C6 05
1U_0 603_1 0V4Z
1
1
2
2
Compal Secret Data
1
2
1U_0 603_1 0V4Z
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
C3 10
1
2
C6 06
C3 00
1U_0 603_1 0V4Z
1
2
Deciphered Date
2
10U_ 0603_ 6.3V6M
C5 70
C3 09
1
1
2
2
C3 01
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
1
1
2
2
2
1
+1.5V
12
R2 97
1K_ 0402_1%
1K_ 0402_1%
For Arr anale only +V REF_DQ_DIMMA
supply f rom a exte rnal 1 .5V v oltage divide
circuit.
07/ 17/2009
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
0.1U _0402 _10V6K
C3 08
1
2
C3 14
1
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 17
C3 15
1
1
2
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
1
2
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
R3 05
0.1U _0402 _10V6K
C3 16
+VR EF_D Q_DIMM A
12
1
+
C5 69
220U _B2_ 2.5VM_R 35
2
LA-5752P
1
10 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
+VR EF_D Q_DIMM B
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
1
C3 82
+3VS
2
DDR_ CKE2 _DIM MB<7>
DD R_B_B S2<7>
M_ CLK_D DR2<7>
M_ CLK_D DR#2<7>
DD R_B_B S0<7>
DD R_B _WE#<7>
DD R_B_ CAS#<7>
DDR_ CS3_ DIMM B#<7>
2.2U _0603 _6.3V 4Z
1
2
D D
C C
B B
A A
+VR EF_D Q_DIMM B
DD R_B _D0
DD R_B _D1
1
C3 84
DD R_B_ DM0
2
DD R_B _D2
DD R_B _D3
DD R_B _D8
DD R_B _D9
DD R_B_ DQS# 1
DD R_B _DQS 1
DD R_B _D10
DD R_B _D11
DD R_B _D16
DD R_B _D17
DD R_B_ DQS# 2
DD R_B _DQS 2
DD R_B _D19
DD R_B _D24
DD R_B _D25
DD R_B_ DM3
DD R_B _D26
DD R_B _D27
DDR_ CKE2 _DIM MB
DD R_B_ BS2
DDR_ B_MA 12
DDR_ B_M A9
DDR_B_MA8
DDR_ B_M A5
DDR_ B_M A3
DDR_ B_M A1
M _CLK_ DDR2
M _CLK_ DDR#2
DDR_ B_MA 10
DD R_B_ BS0
DD R_B _WE#
DD R_B_ CAS#
DDR_ B_MA 13
DDR_ CS3_ DIMM B#
DD R_B _D32
DD R_B _D33
DD R_B_ DQS# 4
DD R_B _DQS 4
DD R_B _D34
DD R_B _D35
DD R_B _D40
DD R_B _D41
DD R_B_ DM5
DD R_B _D42
DD R_B _D43
DD R_B _D48
DD R_B _D49
DD R_B_ DQS# 6
DD R_B _DQS 6
DD R_B _D50
DD R_B _D51
DD R_B _D56
DD R_B _D57
DD R_B_ DM7
DD R_B _D58
DD R_B _D59
1 2
10K _0402_5%
0.1U _0402 _10V6K
C6 18
C6 16
1
2
5
+1.5V +1.5V
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
JDI MM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
R5 72
1 2
R5 73 10K _0402_5%
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYC O_2- 2013297- 2~D
ME@
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND1
2
VSS
4
DQ4
6
DQ5
8
VSS
10
12
14
VSS
16
DQ6
18
DQ7
20
VSS
22
24
26
VSS
28
DM1
30
32
VSS
34
36
38
VSS
40
42
44
VSS
46
DM2
48
VSS
50
52
54
VSS
56
58
60
VSS
62
64
66
VSS
68
70
72
VSS
74
76
VDD
78
A15
80
A14
82
VDD
84
A11
86
A7
88
VDD
90
A6
92
A4
94
VDD
96
A2
98
A0
100
VDD
102
CK1
104
106
VDD
108
BA1
110
112
VDD
114
S0#
116
118
VDD
120
122
NC
124
VDD
126
128
VSS
130
132
134
VSS
136
DM4
138
VSS
140
142
144
VSS
146
148
150
VSS
152
154
156
VSS
158
160
162
VSS
164
166
168
VSS
170
DM6
172
VSS
174
176
178
VSS
180
182
184
VSS
186
188
190
VSS
192
194
196
VSS
198
200
SDA
202
SCL
204
VTT
206
4
DD R_B _D4
DD R_B _D5
DD R_B_ DQS# 0
DD R_B _DQS 0
DD R_B _D6
DD R_B _D7
DD R_B _D12
DD R_B _D13
DD R_B_ DM1
DRA MRST#
DD R_B _D14
DD R_B _D15
DD R_B _D20
DD R_B _D21
DD R_B_ DM2
DD R_B _D22
DD R_B _D23DDR _B_ D18
DD R_B _D28
DD R_B _D29
DD R_B_ DQS# 3
DD R_B _DQS 3
DD R_B _D30
DD R_B _D31
DDR_ CKE3 _DIM MB
DDR_ B_MA 15
DDR_ B_MA 14
DDR_B_MA 11
DDR_ B_M A7
DDR_B_MA6
DDR_ B_M A4
DDR_ B_M A2
DDR_ B_M A0
M _CLK_ DDR3
M _CLK_ DDR#3
DD R_B_ BS1
DD R_B_ RAS#
DDR_ CS2_ DIMM B#
M_OD T2
M_OD T3
DD R_B _D36
DD R_B _D37
DD R_B_ DM4
DD R_B _D38
DD R_B _D39
DD R_B _D44
DD R_B _D45
DD R_B_ DQS# 5
DD R_B _DQS 5
DD R_B _D46
DD R_B _D47
DD R_B _D52
DD R_B _D53
DD R_B_ DM6
DD R_B _D54
DD R_B _D55
DD R_B _D60
DD R_B _D61
DD R_B_ DQS# 7
DD R_B _DQS 7
DD R_B _D62
DD R_B _D63
PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V6 5A @ 0. 7 5V
4
DD R_B_ DQS# [0..7 ]<7>
DD R_B _D[0 ..63]<7>
DD R_B_ DM[0 ..7]<7>
DD R_B_ DQS[ 0..7]<7>
DDR_ B_MA [0.. 15]<7>
DRA MRST# <5,1 0>
DDR_ CKE3 _DIM MB <7>
M_ CLK_ DDR3 <7>
M_ CLK_D DR#3 <7>
DD R_B_B S1 <7>
DD R_B_ RAS# <7>
DDR_ CS2_ DIMM B# <7>
M_OD T2 <7>
M_OD T3 <7>
1
2
0.1U _0402 _10V6K
C3 85
+VR EF_D Q_DIMMB
2.2U _0603 _6.3V 4Z
C3 83
1
2
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
1*0402 0.1uf
4*0402 1uf
1*0402 2.2uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
PM_EX TTS#1_R <5 ,10>
SMB_ DATA_S3 <10, 12,14,2 8>
SMB _CLK_S3 <10, 12,14, 28>
+0.7 5VS
3
Lay ou t N ote:
Pl ace near DIM M
+1.5V
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C5 82
1
@
@
2
Lay ou t N ote:
Pl ace near DIM M
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
10U_ 0603_6. 3V6M
C5 87
C5 76
1
1
2
2
+0.7 5VS
1U_0 603_1 0V4Z
10U_ 0603_ 6.3V6M
C5 95
C5 96
1
1
2
2
2008/10/31 2009/10/31
10U_ 0603_6. 3V6M
C3 11
1
2
1U_0 603_1 0V4Z
C2 99
1
2
10U_ 0603_6. 3V6M
C3 13
1
2
1U_0 603_1 0V4Z
C5 98
1
2
Compal Secret Data
10U_ 0603_6. 3V6M
C5 75
C5 90
1
2
Deciphered Date
2
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C3 12
1
1
2
2
2
1
+1.5V
12
R3 41
1K_ 0402_1%
1K_ 0402_1%
For Arr anale only +VREF_DQ_DIMMB
supply f rom a exte rnal 1 .5V v oltage divide
circuit.
07/ 17/2009
0.1U _0402 _10V6K
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 04
C3 07
1
1
2
2
0.1U _0402 _10V6K
C3 05
1
2
C3 06
1
2
Title
Size D ocum ent N umber Re v
Da te: She et
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
R3 40
+VR EF_D Q_DIMM B
12
LA-5752P
1
0. 3
o f
11 5 1Th ursda y, O ctob er 29 , 2009
5
4
3
2
1
Reserve for Low Power CLK GEN.
RTM890N-632
SLG8LV597VTR
VDD _3V3_ 1V5+3V S_CK505
1 2
R2 780_0 603_5%
@
D D
+1.5V S
1 2
R2 690_0 603_5%
1 PCS CAP(0.1u) BY 1 INPUT PIN
VDD _3V3_ 1V5
0.1U _0402 _10V6K
10U_ 0805_ 10V4K
C3 36
1
1
2
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 66
C3 30
C3 34
1
1
2
2
CLK GEN TO PCH
1. CLK _DMI
2. CLK _BUF_B CLK
3. CLK _BUF_C KSSCD
4. CLK _BUF_D OT96
5. CLK _14M_PCH
C C
CLK GEN TO VGA
1. 27M _CLK
1. 27M _CLK_SS
+1.0 5VS_ CK505+1.0 5VS
1 2
R2 770_06 03_5%
CLK _BUF_ DOT96<14 >
CLK _BUF_ DOT96 #<14>
CL K_B UF_CK SSCD<14>
CL K_BU F_CK SSCD #<14>
CLK _DMI<14>
CLK _DMI#<14>
CLK _BUF_ DOT96
CLK _BUF_ DOT 96#
CL K_B UF_CK SSCD
CL K_B UF_CK SSCD #
CLK _DMI
CLK _DMI#
+3V S_CK505
R3 24 0_040 2_5%
R3 08
R3 07 0_040 2_5%
R3 06
R2 99
1 PCS CAP(0.1u) BY 1 INPUT PIN
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C3 33
1
1
2
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 31
C3 43
C3 32
1
1
2
2
0.1U _0402 _10V6K
C3 35
1
2
R3 18 0_0 402_5%
1 2
1 2
R3 19 0_0 402_5%
CLOSE U27
1 2
1 2
1 2
1 2
1 2
CLK _48M_ CR
0_04 02_5%
0_04 02_5%
10K _0402_5%
L_CL K_BU F_DO T96
L_CL K_BU F_DO T96#
L_CL K_DM I
L_CL K_DM I#
CPU _STOP #
unstuff 09.09.08
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_SRC
+3V S_CK505 +1 .05VS _CK505+3V S_CK505 +1 .05VS _CK505
32
SCL
31
SDA
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD _3V3_ 1V5
CLK _48M_ CR_R
CL K_B UF_C KSSC D_R
CL K_B UF_CK SSCD #_R
U1 4
1
VDD_USB_48
2
VSS_48M
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
USB_48
9
VSS_27M
10
SATA
11
SATA#
12
VSS_SRC
13
SRC_1
14
SRC_1#
15
VDD_SRC_IO
16
CPU_STOP#
33
TGND
SLG 8SP5 87VTR_QFN 32_5X5
REF_0/CPU_SEL
CKPWRGD/PD#
VDD_CPU_IO
RTM890N-631-GRT QFN 32P CLK GEN (SA00003HQ00)
ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)
1 2
@
CLK _48M_ CR_R
R3 2233_ 0402_1%
12
R3 230_0 402_5%
@
PIN8 IS GND FOR ICS3197
SMB _CLK_S 3
SMB _DATA_S3
RE F_0/ CPU_S EL
CLK _XTAL_IN
CLK_ XTAL_OUT
CK _P WRGD
VDD _3V3_ 1V5
R_ CLK_ BUF_B CLK CLK _BUF_ BCLK
R_CL K_BU F_BC LK# CLK _BUF _BCL K#
VDD _3V3_ 1V5
R2 75 0_04 02_5%
1 2
1 2
R2 76 0_04 02_5%
R3 15
12
33_0 402_1%
CK _P WRGD
CLK _14M_ PCH
2N70 02_SOT2 3-3
SMB _CLK_S3 <10, 11,14, 28>
SMB_D ATA_S3 <10,1 1,14,2 8>
CLK _14M_ PCH <1 4>
CLK _BUF_ BCLK <14>
CLK _BUF_ BCLK # <14>
R2 98
1 2
10K _0402_5%
13
D
2
G
Q25
S
+3V S_CK505
CLK _EN# < 48>
PIN8 IS 48MHz FOR ICS3199
B B
A A
+3VS
1 2
R2 790_06 03_5%
+3V S_CK505
1 PCS CAP(0.1u) BY 1 INPUT PIN
0.1U _0402 _10V6K
C3 42
C3 50
1
1
2
2
100MHz 100MHz
0.1U _0402 _10V6K
C3 67
CPU_1PIN 30 CP U_0
133MHz
0.1U _0402 _10V6K
10U_ 0805_10 V4K
C3 44
1
1
2
2
(De faul t)
0 133M Hz
1
+1.0 5VS
1 2
R3 17 10K _0402 _5%@
1 2
R3 16 10K _0402 _5%
C3 65
CLK _14M_ PCH
12
22P _0402_50 V8J
C3 64
EMI Ca pacitor
RE F_0/ CPU_S EL
RE F_0/ CPU_S EL
12
10P _0402_5 0V8J@
C3 48
22P _0402_5 0V8J
CLK_ XTAL_OUT
CLK _XTAL_IN
Y1
12
2
2
14.3 1818M HZ_16P F_DSX840G A
1
C3 49
22P _0402_5 0V8J
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber R ev
Da te: She et
Compal Electronics, Inc.
CLOCK GENERATOR
LA-5752P
1
o f
12 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
PCH _RTCX 1
1 2
R1 54 10M _0402_5%
1
D D
+R TCVC C
R1 44
1 2
100_ 0603_1%
2
C4 41
0.1U _0402 _16V4Z
1
C C
+RTCBA TT
12
SHO RT P ADS
+R TCVC C
R4 21
R4 20
CL RP1
H In te gr：ated VRM e nable
*
L In te gra：ted V RM di sable
+3VS
1 2
1 2
R4 52 1K _0402_ 5%@
1
2
15P _0402_5 0V8J
1M_ 0402_5%
330K _0402_5 %
1 2
C1 71
2
S M_INT RUDE R#
PCH _INTV RME N
P CH_SP KR
OSC4OSC
NC3NC
PCH _RTCX 2
X1
32.7 68KH Z_12. 5PF_ 9H032004 13
1
C1 83
15P _0402_5 0V8J
2
@
HD A_BI TCLK_ CODE C<33>
HD A_S YNC _CO DEC< 33>
@
GPI O33 = GP O , i nte rna l pu ll-up ,shou ld no t be pulle d low
fla sh ME co re of st rap pin p ull d own
(2009, 07,07)
+3V ALW+3V ALW +3V ALW + 3VALW +3VS
12
@
R7 4
200_ 0402_5%
12
B B
@
R1 17
100_ 0402_1%
A A
PCH _JT AG_TD I
PCH _JT AG_TC K
PCH _JT AG_RS T#
Ref DesPCH Pin
R59 1
R59 0
R58 4
R58 3
R58 6
R58 0
R59 5
R59 4
12
@
R7 2
200_ 0402_5%
PCH _JTAG_T MS PCH _JTA G_RST#PCH _JTA G_TDO PCH _JTA G_TDI
12
@
R1 15
100_ 0402_1%
PCH JTAG
Pre -Pr oduc tion
ES1 MPES 2
No Inst all
No Inst all
200 ohm
100 ohm 100 ohm
200 ohm
100 ohm 100 ohm
51o hm
20K ohm 20K ohm
10K ohm 10K ohm
5
12
@
R7 3
200_ 0402_5%
12
@
R1 16
100_ 0402_1%
PCH JTAG
Pro duct ion
*
200 ohm
No Inst all
100 ohm
No Inst allPCH _JT AG_TD O
200 ohm
No Inst all
No Inst allPCH _JT AG_TM S
200 ohm
No Inst allR58 7
No Inst all
51o hm 51 ohm
No Inst all
No Inst all
@
R7 5
20K _0402_5%
1 2
12
@
R1 18
10K _0402_5%
PCH _JTA G_TCK
FOR INTEL DP DG REV 1.6 (M AY 2009)
4
+R TCVC C
1U_0 603_1 0V4Z
1 2
R4 19 20K _0402_1%
1 2
R4 22 20K _0402_1%
C6 471 2P_04 02_50V8J
1 2
1 2
C6 481 2P_04 02_50V8J
R1 14 51_0 402_5%
1U_0 603_1 0V4Z
PC H_SP KR< 33>
HD A_RS T_CO DEC#<33>
HD A_S DIN1<33>
HD A_S DOUT_ CODE C<33>
ME_ FLASH<34>
1 2
4
C1 84
C2 02
+3V ALW
SPI _CLK _PCH
1
12
CL RP3
SHO RT P ADS
2
1
12
CL RP2
SHO RT P ADS
2
R1 68 33_0 402_5%
1 2
R1 67 33_0 402_5%
1 2
R1 69 33_0 402_5%
1 2
R1 66 33_0 402_5%
1 2
R4 09 1K_0 402_5%@
1 2
R4 25 0_040 2_5%
1 2
R4 24 10K _0402_5%
1 2
@
GPI O13 = GPI, 3.3V, SUS
R9 9
1 2
0_04 02_5%
(2009, 05,04)
PCH _RTCX 1
PCH _RTCX 2
PCH _RTCR ST#
PCH _SRT CRST#
S M_INT RUDE R#
PCH _INTV RME N
BIT CLK
HD A_S YNC
P CH_SP KR
HDA _RST #
HD A_S DIN0
HD A_S DIN1
HD A_SD OUT
GPI O13
PCH _JTA G_TCK
PCH _JTAG_T MS
PCH _JTA G_TDI
PCH _JTA G_TDO
S PI_CL K_PC H_R
SPI _SB _CS0#
SPI _SI
SPI _SO _R
3
U7 A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IBE XPEAK- M_FCBGA1 071
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RT CIH DA
SPI JTAG
FWH4 / LFRAME#
LDRQ1# / GPIO23
LP C
SA TA
SATA0GP / GPIO21
SATA1GP / GPIO19
D33
FWH0 / LAD0
B33
FWH1 / LAD1
C32
FWH2 / LAD2
A32
FWH3 / LAD3
C34
A34
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
2008/10/31 2009/10/31
GPI O23
F34
SE RIR Q
AB9
AK7
AK6
SAT A_ITX_ C_DRX_N0
AK11
SAT A_ITX_C_D RX_P0
AK9
AH6
AH5
SAT A_ITX_ C_DRX_N1
AH9
SAT A_ITX_C_D RX_P1
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
SAT A_DTX_C _IRX_N4
AD9
SAT A_DTX_C_I RX_P4
AD8
SAT A_ITX_ C_DRX_N4
AD6
SAT A_ITX_C_D RX_P4
AD5
AD3
AD1
AB3
AB1
AF16
SAT AICOMPPCH _JTA G_RST#
AF15
T3
Y9
V1
R4 53 10K _0402_5%
GPI O21
GPI O19
SPI _SB _CS0#
SPI _SO _R SPI _SO_L
Compal Secret Data
2
LPC _AD0 < 28,34>
LPC _AD1 < 28,34>
LPC _AD2 < 28,34>
LPC _AD3 < 28,34>
LPC _FRAM E# <28 ,34>
T7 PA D
GPI O23 = NA TIVE, 3.3V, CORE
1 2
37.4 _0402_1 %
1 2
SE RIRQ <34>
R5 00
HD D_L ED# <3 6>
GPI O21 = GPI ,3.3V ,CORE
GPI O19 = GPI ,3.3V ,CORE
+3VS
R6 2
1 2
R1 02
1 2
R1 03
15_0 402_5%
1 2
15_0 402_5%
Deciphered Date
2
+1.0 5VS
+3VS
R1 01
12
R4 7910K_ 0402_5%
12
12
12
12
12
12
SPI _WP#
3.3K _0402 _5%
SPI _HOL D#
3.3K _0402 _5%
12
SPI _WP#
+3VS
C1 400.01 U_040 2_16V7K
C1 410.01 U_040 2_16V7K
C4 270.01 U_040 2_16V7K
C4 280.01 U_040 2_16V7K
SAT A_DTX_C _IRX_N0
SAT A_DTX_C_I RX_P0
SATA_ ITX_DRX_N 0
SATA_ ITX_DRX_P0
SAT A_DTX_C _IRX_N1
SAT A_DTX_C_I RX_P1
SATA_ ITX_DRX_N 1
SATA_ ITX_DRX_P1
SAT A_IT X_DRX_ N4_CONN
C1 420.01 U_040 2_16V7K ESATA @
SAT A_I TX_DRX_P4 _CONN
C1 430.01 U_040 2_16V7K ESATA @
R4 47
10K _0402_5%
GPI O21
GPI O19
1 2
1 2
SAT A_DTX_C_ IRX_N0 <3 2>
SATA _DTX_C_IRX _P0 <32>
SATA_ ITX_DRX_N 0 <32>
SATA_ ITX_DRX_P0 <32>
SAT A_DTX_C_ IRX_N1 <3 2>
SATA _DTX_C_IRX _P1 <32>
SATA_ ITX_DRX_N 1 <32>
SATA_ ITX_DRX_P1 <32>
R4 82
10K _0402_5%
4M SPI ROM FOR HM55
(ME code & BIOS code)
SA00003K800
+3VS
U3
1
CS#
VCC
2
SO
HOLD#
3
WP#
SCLK
4
GND
SI
S I C FL 16M EN25 F16-1 00HIP SOP 8P
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
1 2
8
SPI _HOL D#
7
SPI _CLK _PCH
6
SPI _SI
5
Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA
1
SAT A_DTX_C_ IRX_N4 < 37>
SATA _DTX_C_IRX _P4 <3 7>
SAT A_IT X_DRX_ N4_CONN < 37>
SAT A_IT X_DRX_P4_C ONN <37>
C4 60
0.1U _0402 _16V4Z
LA-5752P
1
HDD
ODD
E-SATA
SPI _CLK _PCH
R1 00
33_0 402_5%
@
22P _0402_5 0V8J
@
13 5 1Thu rsda y, O ctobe r 29, 2009
12
C1 38
0. 3
5
PCIE PORT LIST
DEVICEPORT
1
X
WLAN
2
LAN
3
4
CL K_P CIE_C ARD_ PCH#<28 >
CL K_P CIE_ CARD_ PCH<2 8>
5
6
7
8
PCI E_PRX_D TX_N2< 28>
PCIE _PRX_DTX _P2<28>
PCI E_PT X_C_DRX_N 2<28>
PCI E_PTX _C_DRX_P2< 28>
PCI E_PRX_D TX_N3< 29>
PCIE _PRX_DTX _P3<29>
PCI E_PT X_C_DRX_N 3<29>
PCI E_PTX _C_DRX_P3< 29>
PCI E_PRX_D TX_N4< 28>
PCIE _PRX_DTX _P4<28>
PCI E_PT X_C_DRX_N 4<28>
PCI E_PTX _C_DRX_P4< 28>
PCI E_PRX_D TX_N5< 28>
PCIE _PRX_DTX _P5<28>
PCI E_PT X_C_DRX_N 5<28>
PCI E_PTX _C_DRX_P5< 28>
CLK _PCIE _WLA N1#<28>
CL K_PCI E_WL AN1<28>
CLK _PCIE _EXP _PCH#<28>
CLK _PCIE _EXP _PCH<28>
WLA N_CLK REQ1 #< 28>
CLK _PCIE _LAN #<29>
CLK _PCIE _LAN<29>
CLK REQ_ LAN#< 29>
PCI ECLK REQ3 #<28>
CLK REQ_EXP #< 28>
3G
NEW CARD
X
X
X
C2 30 0.1U _0402 _10V6K
C2 29 0.1U _0402 _10V6K
C2 23 0.1U _0402 _10V6K
C2 22 0.1U _0402 _10V6K
C2 31 0.1U _0402 _10V6K3G@
C2 32 0.1U _0402 _10V6K3G@
C2 20 0.1U _0402 _10V6K
C2 21 0.1U _0402 _10V6K
R4 31 10K _0402_5%
+3V ALW
R1 96 0_04 02_5%
R1 97 0_04 02_5%
R4 54 10K _0402_5%
+3VS
R2 20 0_04 02_5%
R2 21 0_04 02_5%
R1 13 10K _0402_5%
+3VS
R2 23 0_04 02_5%3G @
R2 22 0_04 02_5%3G @
R1 20 10K _0402_5%
+3V ALW
R2 24 0_04 02_5%
R2 25 0_04 02_5%
R4 35 10K _0402_5%
+3V ALW
R4 34 10K _0402_5%
+3V ALW
R4 57 10K _0402_5%
+3V ALW
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI E_PRX_ DTX_N2
PCI E_PRX_DT X_P2
PCI E_PTX _DRX_N2
PCI E_PTX_DR X_P2
PCI E_PRX_ DTX_N3
PCI E_PRX_DT X_P3
PCI E_PTX _DRX_N3
PCI E_PTX_DR X_P3
PCI E_PRX_ DTX_N4
PCI E_PRX_DT X_P4
PCI E_PTX _DRX_N4
PCI E_PTX_DR X_P4
PCI E_PRX_ DTX_N5
PCI E_PRX_DT X_P5
PCI E_PTX _DRX_N5
PCI E_PTX_DR X_P5
GPI O73 = NAT IVE,3 .3V,S US
CL K_PC IE_W LAN1# _R
CL K_PC IE_W LAN1_ R
GPI O18 = NA TIVE, 3.3V, CORE
CLK _PCIE _LAN #_R
CLK _PCIE _LAN _R
GPI O20 = NA TIVE, 3.3V, CORE
CL K_P CIE_ CARD _PCH #_R
CL K_P CIE _CAR D_PCH _R
GPI O25 = NAT IVE,3 .3V,S US
CLK _PCIE _EX P_PCH#_ R
CLK REQ_EXP #
GPI O26 = NAT IVE,3 .3V,S US
GPI O44 = NAT IVE,3 .3V,S US
GPI O56 = NAT IVE,3 .3V,S US
D D
WLAN
LAN
3G
C C
EXP
WLAN
B B
LAN
3G
EXP
A A
4
U7 B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IBE XPEAK- M_FCBGA1 071
WLAN
LAN
MINI1
NEW CARD
SMBus
PCI-E*
Link
Con trol ler
PEG_A_CLKRQ# / GPIO47
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
From C LK BUF FER
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
3
R4 07
0_0402_5%
LID_ OUT#
B9
H14
C8
J14
C6
G8
M14
E10
G12
T13
T11
T9
H1
AD43
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
J42
AH51
AH53
AF38
T45
P43
T42
N50
GPI O11 = NAT IVE,3 .3V,S US
SM BCLK
SMBDA TA
GPI O60 = NAT IVE,3 .3V,S US
GPI O60
SML 0CLK
SML 0DATA
GPI O74 = NAT IVE,3 .3V,S US
GPI O74
SML 1CLK
R7 9
SML 1DATA
R8 0
PEG _CLK REQ#
PEG _CLK REQ#
GPI O47 = 10 Kohm PULL DOWN
CLK OUT_D P_N
CLK OUT_D P_P
CLK _14M_ PCH
CL K_PC I_FB
XTA L25_IN
XTAL25 _OUTCLK _PCIE _EX P_PCH_R
CL K_P CI_DB _R
1 2
CLK _PCIE _VG A#_R
CLK _PCIE _VG A_R
CLK _EXP#_R
CLK _EXP_R
R4 91 90.9_ 0402_1%
R5 24 0_04 02_5%
R5 25 0_04 02_5%
R1 05 0_04 02_5%
R1 06 0_04 02_5%
1 2
R1 98
1 2
EC_ LID_O UT# <34 >
0_0402_5%
0_0402_5%
DTS , read f rom EC
PEG _CLK REQ# <19 >
R4 1210 K_0402_ 5%
1 2
1 2
1 2
1 2
CLK _DMI# <12>
CL K_DM I < 12>
CLK _BUF_ BCLK # <12>
CLK _BUF_ BCLK <12>
CLK _BUF_ DOT96 # <12>
CLK _BUF_ DOT96 <12>
CL K_BU F_CK SSCD # < 12>
CL K_B UF_CK SSCD <12>
CLK _14M_ PCH <1 2>
CL K_PCI _FB < 16>
+1.0 5VS
22_0 402_5%
@
EC_ SMB_ CK2
EC_ SMB_ DA2
CL K_PCI _DB < 28>
SMB CLK
SMBDA TA
CLK _PCIE _VGA #
CLK _PCIE _VGA
SMB _CLK_S 3
SMB _DATA_S3
EC_ SMB_CK 2 <34>
EC_ SMB_DA 2 <34>
CLK_E XP# <5>
CLK_E XP <5>
2
1 2
R1 21 10K _0402_5%
1 2
R4 06 10K _0402_5%
Q8A
2N70 02DW -T/R7 _SOT363-6
6 1
2N70 02DW -T/R7 _SOT363-6
3
SMB _CLK_S 3
2
+3VS
Q8B
SMB _DATA_S3
4
5
EC_THERMAL
CLK _PCIE _VGA# <19>
CLK _PCIE _VGA <19>
+3VS
Q7A
6 1
5
2N70 02DW -T/R7 _SOT363-6
Q7B
3
2N70 02DW -T/R7 _SOT363-6
4
EC_ SMB_ DA2
EC_ SMB_ CK2
EMI REQUEST 0303
CLK _14M_ PCHCL K_PC I_FB
R2 09
33_0 402_5%
@
1 2
C2 63
22P _0402_5 0V8J
@
1 2
SM BCLK
+3VS +3V ALW
SMBDA TA
SML 0CLK
SML 0DATA
SML 1CLK
SML 1DATA
GPI O74
LID_ OUT#
GPI O60
SMB _CLK_S3 <10, 11,12, 28>
1 2
R1 23 2.2K _0402 _5%
1 2
R7 8 2 .2K_ 0402_5%
1 2
R1 48 2.2K _0402 _5%
1 2
R1 47 2.2K _0402 _5%
1 2
R4 04 2.2K _0402 _5%
1 2
R4 03 2.2K _0402 _5%
1 2
R3 99 10K _0402_5%
1 2
R1 45 10K _0402_5%
1 2
R4 00 10K _0402_5%
DDR3*2 AND CLK GEN
SMB_ DATA_S3 <10, 11,12,2 8>
+3VS
2
R8 1 0_04 02_5%
1 2
R8 3 0_04 02_5%
1 2
R4 13
33_0 402_5%
@
C4 39
22P _0402_50 V8J
@
+3VS
R1 24
2.2K _0402 _5%
SMB _EC_ DA2_R
@
SMB _EC_ CK2_R
@
25MHz crysta l not used, XTAL25_IN
need t o GND.
(check list R ev1.6)
XTA L25_IN
XTAL25 _OUT
1
R1 22
SM BCLK
SMBDA TA SMB _DATA_S3
R8 2
2.2K _0402 _5%
SMB _EC_ DA2_REC_ SMB_ DA2
SMB _EC_ CK2_REC_ SMB_ CK2
0_04 02_5%
@
1 2
@
1 2
0_04 02_5%
R1 19
Nvidia
thermal
sensor
1 2
R5 98 1M_ 0402_5%@
Y4
@
1 2
25M HZ_20 P_1BG 25000CK1A
18P _0402_50 V8J
C6 30
1
@
2
SMB _EC_ DA2_R <19,31>
SMB _EC_ CK2_R <19,31>
SMB _CLK_S 3
0_04 02_5%
1
2
C6 31
C631 Resi sto r P ull down
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK
LA-5752P
1
14 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
4
3
2
1
D D
DMI _CTX_PRX _N0<6>
DMI _CTX_PRX _N1<6>
DMI _CTX_PRX _N2<6>
DMI _CTX_PRX _N3<6>
DMI_CT X_PRX_P0<6>
DMI_CT X_PRX_P1<6>
DMI_CT X_PRX_P2<6>
DMI_CT X_PRX_P3<6>
DMI _CRX_PTX _N0<6>
DMI _CRX_PTX _N1<6>
DMI _CRX_PTX _N2<6>
DMI _CRX_PTX _N3<6>
DMI_CRX _PTX_P0<6>
DMI_CRX _PTX_P1<6>
DMI_CRX _PTX_P2<6>
DMI_CRX _PTX_P3<6>
+1.0 5VS
1 2
R5 20 49.9 _0402 _1%
4mil w idth a nd place
within 500mi l of t he PCH
C C
Che ckl is t0.8 M EPWRO K
can be co nnect to
PWR OK if iAMT disa ble
(2009, 05,04)
SU S_PW R_DN _ACK<34>
+3V ALW
R4 50 10K _0402_5%
VGATE
IC H_PO K
+3V ALW
1
A
2
B
+3VS
Reserv ed
(2009, 09,08)
B B
A A
：
R3 96 100K _0402_1%
VGATE<48>
IC H_PO K< 34>
+3V ALW
1 2
AC_ PRES ENT<34 >
MC7 4VHC1 G08D FT2G SC70 5P
3
@
G
Y
P
U2 8
5
12
R3 98 0_04 02_5%@
R3 97 0_04 02_5%
PM_ DRAM _PWR GD<5>
R4 01
R4 37 10K _0402_5%
1 2
1 2
R5 99 0_ 0402_5%@
PBT N_OUT#<34>
GPI O31 = GPI, 3.3V, SUS
R7 7 8.2K_0 402_1%
1 2
GPI O30 = GPI, 3.3V, SUS
R1 65 10K _0402_5%
1 2
S YS_P WROK
4
1 2
1 2
10K _0402_5%
R4 51 0_ 0402_5%
DMI _CTX_PR X_N0
DMI _CTX_PR X_N1
DMI _CTX_PR X_N2
DMI _CTX_PR X_N3
DMI_CT X_PRX_P0
DMI_CT X_PRX_P1
DMI_CT X_PRX_P2
DMI_CT X_PRX_P3
DMI _CRX_PT X_N0
DMI _CRX_PT X_N1
DMI _CRX_PT X_N2
DMI _CRX_PT X_N3
DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3
DMI _IRCO MP
+3VS
R4 48
10K _0402_5%
SYS _RS T#
1 2
S YS_P WROK
R4 55
0_04 02_5%
1 2
R1 46 10K_ 0402_5%
1 2
PM_ DRAM _PW RGD
PM_ RSMRST#
12
SU S_P WR_D N_AC K_R
PBT N_OUT#
AC_ PRES ENT_R
1 2
GPI O72
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IBE XPEAK- M_FCBGA1 071
EC_ RSMRS T#<34>
U7C
System Power Manag ement
RSMRST circuit
BAV 99DW- 7_SOT363
5
D8 B
R1 75
1 2
2.2K _0402 _5%
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_LAN# / GPIO29
@
0_04 02_5%
1 2
E
B
4
2
3
6
BA18
FDI_RXN0
BH17
FDI_RXN1
BD16
FDI_RXN2
BJ16
FDI_RXN3
BA16
FDI_RXN4
BE14
FDI_RXN5
BA14
FDI_RXN6
BC12
FDI_RXN7
BB18
FDI_RXP0
BF17
FDI_RXP1
BC16
FDI_RXP2
BG16
FDI_RXP3
AW16
FDI_RXP4
BD14
FDI_RXP5
BB14
FDI_RXP6
BD12
FDI_RXP7
BJ14
FDI_INT
BF13
FDI_FSYNC0
BH13
FDI_FSYNC1
BJ12
FDI_LSYNC0
BG14
FDI_LSYNC1
J12
WAKE#
Y1
P8
F3
E4
H7
SLP_S4#
P12
SLP_S3#
K8
SLP_M#
N2
TP23
BJ10
PMSYNCH
GPI O29 = GPO, 3.3V, SUS
F6
R4 02
C
PM_ RSMRST#
123
Q14
MMBT 3906_SOT23-3
1 2
R1 76 4. 7K_0 402_5%
1
D8 A
BAV 99DW- 7_SOT363
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_I NT
FD I_F SYN C0
FD I_F SYN C1
FD I_L SY NC0
FD I_L SY NC1
10K _0402_5%
1 2
PCI E_WA KE#
GPI O32 = GPO, 3.3V, CORE
GPI O61
GPI O62
R4 36
PCI E_WA KE# <2 8>
1 2
R1 08 10K _0402_5%
GPI O61 = NAT IVE,3 .3V,S US
GPI O62 = NAT IVE,3 .3V,S US
SLP _S5# <34 >
SLP _S4# <34 >
SLP _S3# <34 >
Can be l eft NC w hen I AMT i s
not su pp ort on t he pl atfro m
H_ PM_ SYNC < 5>
If not u sing inte grate d
LAN ,si gn al may be le ft as NC.
+3V ALW
FDI _CTX_ PRX_N0 <6>
FDI _CTX_ PRX_N1 <6>
FDI _CTX_ PRX_N2 <6>
FDI _CTX_ PRX_N3 <6>
FDI _CTX_ PRX_N4 <6>
FDI _CTX_ PRX_N5 <6>
FDI _CTX_ PRX_N6 <6>
FDI _CTX_ PRX_N7 <6>
FDI _CTX_PRX _P0 <6>
FDI _CTX_PRX _P1 <6>
FDI _CTX_PRX _P2 <6>
FDI _CTX_PRX _P3 <6>
FDI _CTX_PRX _P4 <6>
FDI _CTX_PRX _P5 <6>
FDI _CTX_PRX _P6 <6>
FDI _CTX_PRX _P7 <6>
FD I_I NT <6>
FD I_F SYN C0 <6>
FD I_F SYN C1 <6>
FD I_L SYN C0 <6>
FD I_L SYN C1 <6>
+3V ALW
+3VS
SLP _S3#
SLP _S4#
SLP _S5#
+3VS
1 2
R4 18 10K _0402_5%@
1 2
R4 17 10K _0402_5%@
1 2
R4 16 10K _0402_5%@
PC H_EN BKL<27>
PC H_E NVDD<27>
ED ID_C LK<2 7>
EDI D_DAT A< 27>
PCH _PWM< 27>
12
R5 02
2.37 K_040 2_1%
CR T_D DC_C LK<2 6>
CR T_DDC _DAT A<26 >
CR T_H SYN C<26>
CR T_V SYN C<26 >
LVD S_AC LK#<27>
LVD S_AC LK<27>
LVD S_A0#<27>
LVD S_A1#<27>
LVD S_A2#<27>
LVD S_A0<27>
LVD S_A1<27>
LVD S_A2<27>
DA C_B LU<26>
DA C_G RN<2 6>
DA C_R ED<26>
PCH _ENB KL
PC H_E NVD D
ED ID_ CLK
EDI D_DAT A
R4 97
1 2
10K _0402_5%
1 2
R4 96 10K _0402_5%
T10 PA D
DA C_B LU
DA C_G RN
DA C_R ED
CR T_I REF
1K_ 0402_5%
R4 92
12
U7D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBE XPEAK- M_FCBGA 1071
update R492 tolera nce for
DAC_CR T from 0.5% to 5%
(check list 2 .0)
DA C_B LU
DA C_G RN
DA C_R ED
ED ID_ CLK
EDI D_DAT A
CRT OUT
R4 93 150_0 402_1%UM A@
1 2
R4 95 150_0 402_1%UM A@
1 2
R4 94 150_0 402_1%UM A@
1 2
R4 58 2.2K _0402 _5%U MA@
R4 98 2.2K _0402 _5%U MA@
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
2.2K _0402_5 %
AW38
BA38
HD MIC LK_NB
Y49
HDM IDAT _NB
AB49
BE44
BD44
AV40
TMD S_B_ DATA2#_P CH
BE40
TMD S_B_ DATA2_P CH
BD40
TMD S_B_ DATA1#_P CH
BF41
TMD S_B_ DATA1_P CH
BH41
TMD S_B_ DATA0#_P CH
BD38
TMD S_B_ DATA0_P CH
BC38
TMD S_B_ CLK#_P CH
BB36
TMD S_B_ CLK_PCH
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R5 10 10K _0402_5%
12
+3VS
12
12
UMA @
UMA @
R5 04
R5 03
2.2K _0402_5 %
C6 38 0.1U _0402 _10V6KUMA _HDM I@
C6 39 0.1U _0402 _10V6KUMA _HDM I@
C6 40 0.1U _0402 _10V6KUMA _HDM I@
C6 41 0.1U _0402 _10V6KUMA _HDM I@
C6 42 0.1U _0402 _10V6KUMA _HDM I@
C6 43 0.1U _0402 _10V6KUMA _HDM I@
C6 44 0.1U _0402 _10V6KUMA _HDM I@
C6 45 0.1U _0402 _10V6KUMA _HDM I@
HD MICL K_NB <25>
HDM IDAT _NB <25 >
TMD S_B_HP D# <25>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
TMDS _B_DATA 2# <25>
TMDS _B_DATA 2 <25>
TMDS _B_DATA 1# <25>
TMDS _B_DATA 1 <25>
TMDS _B_DATA 0# <25>
TMDS _B_DATA 0 <25>
TMD S_B_CLK # <25>
TMD S_B_CLK <25>
HDMI
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Disp lay In terface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS
LA-5752P
1
15 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
D D
PCI _PIRQ A#
PCI _PIRQ B#
GPI O18 = NAT IVE,5 V,COR E
GPI O52 = NAT IVE,5 V,COR E
GPI O54 = NAT IVE,5 V,COR E
C C
GPI O2 = G PI,5V ,CORE
GPI O3 = G PI,5V ,CORE
GPI O4 = G PI,5V ,CORE
GPI O5 = G PI,5V ,CORE
PCI _RST#<2 8,34>
R4 08 100 K_0402_1 %
12
GNT 2
Def aul t- Inte rnal pull up
Low =Co nf igu res D MI fo r ESI
com pat ib le o perat ion(f or
ser ver s only. Not f or
mob ile /des ktops )
PCI _PME#<34>
B B
CL K_PCI _LPC<34 >
CL K_PCI _FB<1 4>
PCI _REQ 0#
PC I_P IRQF#
PCI _REQ 3#
PCI _REQ 1#
PCI _FRA ME#
PC I_ TRDY#
PC I_P IRQH #
PCI _STOP#
PC I_I RD Y#
PC I_P IRQD #
PCI _REQ 2#
A A
PCI _GNT 3#
A16 sw ap ove ride S trap/T op-Block
Swap O verrid e jumper
PCI_GN T3#
R1 99 22_0 402_5%
1 2
1 2
R2 11 22_0 402_5%
RP 5
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
RP 7
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
RP 4
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
R2 00 1K_ 0402_5%@
1 2
Low=A1 6 swap
overri de/Top -Block
Swap O verrid e enabled
High=D efault
PC I_P IRQC #
PC I_P IRQD #
PCI _REQ 0#
PCI _REQ 1#
PCI _REQ 2#
PCI _REQ 3#
PCI _GNT 0#
PCI _GNT 1#
PCI _GNT 2#
PCI _GNT 3#
PCI _PIRQ E#
PC I_P IRQF#
P CI_PI RQG#
PC I_P IRQH #
PC I_S ERR#
PC I_P ERR#
PC I_I RD Y#
*
PCI _DEV SEL#
PCI _FRA ME#
PCI _LOCK #
PCI _STOP#
PC I_ TRDY#
PLT_ RST#
CL K_P CI_LP C_R
CL K_P CI_FB _R
+3VS +3V S
*
5
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
J50
G42
H47
G34
G38
H51
B37
A44
F51
A46
B45
M53
F48
K45
F36
H53
B41
K53
A36
A48
K6
E44
E50
A42
H44
F46
C46
D49
D41
C48
M7
D5
N52
P53
P46
P51
P48
P CI_PI RQG#
PC I_P IRQC #PCI _PIRQ B#
PCI _PIRQ A#
PCI _PIRQ E#
PCI _DEV SEL#
PCI _LOCK #
PC I_S ERR#
PC I_P ERR#
U7 E
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
STOP#
TRDY#
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
IBE XPEAK- M_FCBGA1 071
RP 3
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_5 %
RP 6
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_5 %
BUF _PLT_RS T#<5, 19,28 ,29>
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV RAM
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
PC I
USB
0.1U _0402 _16V4Z
C6 46
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
4
AY9
NV_CE#0
BD1
NV_CE#1
AP15
NV_CE#2
BD8
NV_CE#3
AV9
NV_DQS0
BG8
NV_DQS1
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
NV_ ALE
BD3
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
PCI _GNT 0#
PCI _GNT 1#
NV _CLE
NV_ RCOM P
USB 20_N0
USB 20_P0
USB 20_N1
USB 20_P1
USB 20_N2
USB 20_P2
USB 20_N3
USB 20_P3
USB 20_N5
USB 20_P5
USB 20_N8
USB 20_P8
USB 20_N 10
USB 20_P10
USB 20_N 11
USB 20_P11
USB 20_N 13
USB 20_P13
USB RBIA S
USB _OC# 0
USB _OC# 1
USB _OC# 2
USB _OC# 3
USB _OC# 4
USB _OC# 5
USB _OC# 6
USB _OC# 7
R2 12 1K_ 0402_5%@
R2 10 1K_ 0402_5%@
Boot B IOS St rap
0
0
1
R1 49 0_04 02_5%
MC7 4VHC1 G08D FT2G SC70 5P
12
1
R1 55
100K _0402_5%
2
4
GPI O8
Wea k i nt ern al PU , don 't PD
Check list R ev0.8 sectio n1.23.2
If not imple mented , the
Braidw ood
interf ace si gnals can be
left a s No C onnect (NC).
GPI O15
*
L In te l M E： Cryp to Tr anspo rt
Lay er Se cur ity( TLS) chip er su ite
wit h n o conf ident ialit y
H In te l M E： Cryp to Tr anspo rt
Lay er Se cur ity( TLS) chip er su ite
wit h c on fiden tiali ty
it hav e wea k in terna l PU 20K
within 500mil
R1 04
1 2
32.4 _0402_1 %
@
USB 20_N0 <37>
USB 20_P0 < 37>
USB 20_N1 <37>
USB 20_P1 < 37>
USB 20_N2 <27>
USB 20_P2 < 27>
USB 20_N3 <37>
USB 20_P3 < 37>
USB 20_N5 <38>
USB 20_P5 < 38>
USB 20_N8 <28>
USB 20_P8 < 28>
USB 20_N1 0 <28>
USB 20_P10 <28>
USB 20_N1 1 <37>
USB 20_P11 <37>
USB 20_N1 3 <28>
USB 20_P13 <28>
1 2
R1 64 22.6 _0402 _1%
Within 500 mi ls mini mum spa cing to other
signal i s 15mil
1 2
1 2
PCI_GN T1#PCI_GNT0#
1 2
@
4
U5
0
1
0
11
Y
+3VS
Boot B IOS
Locati on
LPC
Reserv ed(NAND)
PCI
SPI
3
1
G
A
2
B
P
5
GPI O27
Def aul t D o ：not c onnec t(flo ating )
Hig h E nab le：s the inte rnal VccVR M
to hav e a c lean sup ply f or an alog
rai ls. n o n eed to us e on board
fil ter cir cuit.
GPI O1 = GPI,3 .3V,C ORE
GPI O6 = GPI,3 .3V,C ORE
GPI O7 = GPI,3 .3V,C ORE
GPI O8 = GPO,3 .3V,S US
GPI O12 = GPI, 3.3V, SUS
LEFT USB
LEFT USB (COMBO)
USB Cam era
RIGHT USB
che ckl is t 2 .0 u pdate 2009 .0916
CARD READER
WLAN
EXPRESS
Bluetooth
3G CARD
USB _OC# 0 < 37>
USB _OC# 1 < 37>
*
PLT_ RST#
3
+3VS
+3V ALW
+3V ALW
6
DRA MRST _CNTR L_PC H<5>
PCH _TEMP_A LERT#<34 >
SUS P#<28, 34,3 9,42,4 4,46> VGA _EN <45>
+3V ALW
+3V ALW
DI S@
R5 06 0_04 02_5%
1 2
GPI O0 = GPI,3 .3V,C ORE
EC _SCI #<34>
EC_ SMI#< 34>
CP USB#<28 >
GPIO27 if p ull down to turn off 1.8V VR
DRA MRST _CNTR L_PC H GPI O46
Int el An ti- Theft Tech onlog y
High=Enabled
NV_ALE
Low=Disable(floating)
NV_ ALE
R5 15 1K_ 0402_5%@
1 2
*
+1.8V S
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
Wea k i ntern al
PU, Do not pull low
NV _CLE
R9 8 1K_ 0402_5%@
1 2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3VS
Issued Date
2
GPIO
NCTF
+3V ALW
Deciphered Date
2
RSVD
+3VS
+3VS
+3V ALW
：
AB12
AB13
BE53
BF53
BH52
BH53
BJ49
BJ50
BJ52
BJ53
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
Y3
C38
D37
J32
F10
K9
T7
AA2
F38
Y7
H10
V13
M11
V6
AB7
V3
P3
H3
F1
AB6
AA4
F8
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BF1
BH1
BH2
BJ1
BJ2
BJ4
BJ5
D1
D2
D53
E1
E53
RP 1
8.2K _080 4_8P4R_5 %
RP 2
8.2K _080 4_8P4R_5 %
U7 F
BMBUSY# / GPIO0
TACH1 / GPIO1
TACH2 / GPIO6
TACH3 / GPIO7
GPIO8
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
STP_PCI# / GPIO34
SATACLKREQ# / GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
PCIECLKRQ6# / GPIO45
PCIECLKRQ7# / GPIO46
SDATAOUT1 / GPIO48
SATA5GP / GPIO49
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
IBE XPEAK- M_FCBGA1 071
Compal Secret Data
GPI O0
1 2
R4 8310K _0402_ 5%
GPI O1
1 2
R4 2810K _0402_ 5%
GPI O6
1 2
R4 2710K _0402_ 5%
EC _SC I#
EC_ SMI#
CP USB #
GPI O15
1 2
R4 331K _0402_5%
GPI O16
GPI O17
GPI O22
1 2
R4 4910K _0402_ 5%
@
12
R5 0710K _0402_ 5%
GPI O28
1 2
R4 4610K _0402_ 5%
GPI O34
12
R4 3210K _0402_ 5%
GPI O35
12
R4 5610K _0402_ 5%
GPI O36
GPI O37
1 2
R4 8110K _0402_ 5%
GPI O38
1 2
R1 0910K _0402_ 5%
GPI O39
1 2
R1 1210K _0402_ 5%
GPI O45
1 2
R7 610K_ 0402_5%
GPI O48
1 2
R4 8010K _0402_ 5%
PCH _TEMP _ALERT#
GPI O57
1 2
R4 15 10K _0402_5%
1 2
R6 09 10K _0402_5%
@
USB _OC# 0
USB _OC# 1
USB _OC# 2
USB _OC# 3
USB _OC# 4
USB _OC# 5
USB _OC# 6
USB _OC# 7
NV_ ALE
Ena ble I ntel Anti -Thef t
Tec hno lo gy 8 .2K P U to +3VS
Dis abl e Inte l Ant i-The ft
Tec hno lo gy：float ing(i ntern al PD )
NV_ CLE
DMI te rm inat ion v oltag e.
wea k i nt ern al PU , don 't PD
2008/08/12 2009/08/12
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
MISC
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
CPU
CLKOUT_PCIE7P
PROCPWRGD
THRMTRIP#
1 2
R4 29 10K _0402_5%
1 2
R4 85 10K _0402_5%
1 2
R4 84 10K _0402_5%
12
R1 07 10K _0402_5%
@
1 2
R4 26 10K _0402_5%
@
1 2
R4 14 10K _0402_5%
1
AH45
AH46
+3VS
A20GATE
PECI
RCIN#
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
AF48
AF47
U2
AM3
AM1
BG10
T1
BE10
BD10
BA22
TP1
AW22
TP2
BB22
TP3
AY45
TP4
AY46
TP5
AV43
TP6
AV45
TP7
AF13
TP8
M18
TP9
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
C10
R1 10
10K _0402_5%
1 2
H_ PEC I
KB _RST#
H_T HERM TRIP#_L
56_0 402_5%
56 5%- ->checklist 1.6
54.9 1 %-->CRB 1.0
+3V ALW
INT 3_3V#
TP24
GATE A20 <34>
CLK _CPU_ BCLK # <5>
CL K_CPU _BCL K <5>
H_ PEC I <5>
KB_ RST# <34 >
H_ CPU PW RGD <5>
R5 18
1 2
12
R5 19
56_0 402_5%
DRA MRST _CNTR L_PC H
12
R4 05 10K_ 0402_5%
USB PORT LIST
RIGHT SIDE0
1
LEFT SIDE
CMOS
GPI O17
GPI O36
PCH _TEMP _ALERT#
GPI O16
EC _SC I#
EC_ SMI#
2
3
LEFT SIDE
4
5
CARD READER
6
7
WIRELESS8
9
NEW CARD
10
BT
11
12
3G
13
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/RSVD
LA-5752P
1
+3VS
KB _RST#
H_T HERM TRIP# <5>
+V CCP
DEVICEPORT
16 5 1Thu rsda y, O ctobe r 29, 2009
12
R1 11
10K _0402_5%
0. 3
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