A
1 1
B
C
D
E
Compal Confidential
NIWE2
2 2
Schematics Document
Arrandale
with Intel IBEX PEAK-M core logic
3 3
REV:0.3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/03/25 2008/04/
C
Compal Secret Data
Deciphered Date
Compal Electronics,Ltd.
Title
Cover Sheet
Size Docu ment Numb er R ev
Cus tom
LA-5752P
D
Dat e: Sheet o f
1 51Thur sday, Octobe r 29, 2009
E
0.3
A
Compal confidential
File Name :
ZZ Z
15.6W_PCB_LA5752P
1 1
HDMI
CO NN
page24
VR AM 6 4*16
DD R3*4
page20
NVidia N11M-GE1
page19~ 23
level shift IC
ASM 1 4 42
page25
PCI-E X16
B
intel
Arrandale
(UMA/DIS)
C
POWER BD: LS-5754P
POWER BT
NOVO BT
POWER MANAGE BT
D
CAP SENSOR BD:LS-5752P
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE
E
CARD READER BD:
LS-5753P
RTS5138
HP JACK
MIC JACK
BUTTON & LED
Clock Generator
ICS9LRS3199AKLFT
page12
Socket-rPGA989
37.5mm*37.5mm
page5~9
DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
page 10,11
Dual Channel
100MHz
2.7GT/s
FDI *8
DMI *4
DDR3-800(1.5V)
DDR3-1067(1.5V)
UP TO 8G
2Channel Speaker
page33
CRT Connector
page26
2 2
LVDS
Co nnector
page27
PCI Express
Mini card Slot 1
page28
6*PCI-E B US
PCI Express
Mini card Slot 2
SIM Card
3 3
page28
page28
USB(WWAN)
SPI ROM
BIOS
page13
RTL8111DL-VB-GR
10/100/1G LAN
RJ45 CONN
page29
page30
Intel Ibex Peak M
FCBGA 951
25mm*25mm
LPC BUS
EC
ENE KB926D
Touch Pad
page35
page 13 ~18
page34
Int.KBD
SPI ROM
AZALIA
14*USB2.0
6*SATA serial
page35
page36
Audio Codec
Conexant
CX20671
page33
CMOS Camera
BlueTooth CONN
USB CONN X1(Right)
USB PORT X1(Left)
New Card X1
WWAN
SATA HDD CONN
page32
page27
page37
page28
page28
Analog MIC_Int
page37
page37
Card Reader/Audio Jack SB
CONN
Realtek 5138
MS/MS
pro/SD/SD
pro/mmc/XD
page33
HP X 1+
MIC_Ext X1
ESATA HDD AND USB CONN
page38
page37
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/03/24 2008/04/
SATA ODD CONN
Compal Secret Data
Deciphered Date
page32
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet of
Compal Electronics, Inc.
MB Block Diagram
LA-5752P
2 51Thurs day, October 29, 2009
E
0.3
A
B
C
D
E
DDR3 Voltage Rails
SMBUS Control Table
N10x
Thermal
Sensor
X
X
X
X X
X
X X
X
X
V
+3VS
X
X
+3VS
X
WLAN
WWAN
+5VS
power
plane
1 1
+B
State
+5VALW
+3VALW
+1.5V
+3VS
+1.5VS
+VCCP
+CPU_CO RE
+VGA_CO RE
+1.8VS
+0.75VS
+1.05VS
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
SOURCE
KB926
+3VALW
KB926
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
RAM
M2
X V
X
V
+3VALW
X
BATT KE926 SODIMM CLK CHIP
+3VALW
X
X
X
X
X
X
V
+3VALW
X
X
V V
+3VS
X
N10x
X
X
X
Cap sensor
bo ard
+3VS
NEW
PCH
CARD
X
XX
X
X
V
X X
X
V
+3VS
XXX X X X X X
V
+3VALW
X
X
S0
S3
2 2
S5 S4/AC
S5 S 4/ Batter y only
S5 S 4/AC & Ba ttery
don't e xist
O
O
O
O
X
O
O
O
X
O
X X
X
X X X
OO
I2C / SMBUS ADDRESSING
X
DEVICE
DDR SO-DIMM 0
X
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
@ FUNCTION
EVT NON-USE
45@
100@ 10/100 LAN
GIGA@
UMA_HDMI@
HDMI@
3 3
3G@
X76@
ESATA@
CMOS@
BT@ Blue Tooth
10M@
11M@
UMA@
DIS@
VGA@ FOR NVIDIA PART
HYBRID@ FOR SWITCHABLE
HU@
HD@
SKU
Arrandale(dGPU)
4 4
DIS only
Arrandale(iGPU)
UMA only
Arrandale(iGPU+dGPU)
SWITCHABLE
A
(45 BOM)
GIGA LAN
FOR UMA HDMI components
FOR HDMI components
3G(WWAN) function
(X76 BOM)
ESATA function
Camera function
FOR 10M CHIP
FOR 11M CHIP
UMA only (Arranddale)
DIS only (Arranddale)
SWITCHABLE or UMA only
SWITCHABLE or DIS only
DIS@ / 100@ for EVT
UMA@ / 100@ for EVT
VGA@+HD@+HU@+HYBRID@
PCIE PORT LIST
DEVICEPORT
1
2
LAN
3
3G
4
NEW CARD
5
6
7
8
USB PORT LIST
DEVICEPORT
RIGHT SIDE0
1WLAN
LEFT SIDE
CMOS
2
3
LEFT SIDE
4
RIGHT SIDE
5
CARD READER
6
7
WIRELESS8
9
NEW CARD
10
BT
11
12
3G
13
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/03/24 2008/04/
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
D
Date: Sheet of
Compal Electronics, Inc.
MB Notes List
LA-5752P
3 51Thurs day, October 29, 2009
E
0.3
A
B
C
D
E
Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
GPIO1
GPIO2
1 1
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
2 2
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
3 3
N/A
N/A
IN
-
OUT
H
OUT
H
OUT
H
OUT
-
OUT
-
OUT
-
I/O
L
OUT
L
OUT
I/O
L
IN
-
OUT
-
OUT
- Powe r supply control
IN
-
OUT
-
IN
-
IN
-
IN
-
IN
-
IN
-
IN
-
I/O
Hot pl ug detect for IFP link C
Panel Back-Li ght b rightness(PWM capable)
Pan el Powe r Enab le
Panel Back-Li ght On/Off (PWM)
GPU VID0
GPU VID1
GPU VID2
Thermal Catast rophic Overtemp
Therma l Alert
Memory VREF switch
SLI raster sync
AC pow er det ect pin
MEM_VID orPower supply control
Hot pl ug detect for IFP Link E
Progra mmable Fan Co ntrol
Hot pl ug detect for IFP Link D
Hot pl ug detect for IFP link F
SLI sw ap ready signal
Products
N10P-GS
128bit
1024MB
DDR3
N10P-GE
128bit
1024MB
DDR3
N10P-LP
128bit
1024MB
DDR3
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
Products
N10M-GE
64bit
512MB
DDR3
N10M-GS
64bit
512MB
DDR3
N10M-LP
64bit
512MB
DDR3
Power Sequence
(+3VS)
(1. 05VS)
(+V GA_CORE)
GPIO6
GPU_VID 1 G PU_VID0 VGA _CORE
GPIO5 N10M-GS N10P-GS
0.8V
00
0 1
1 0
1 1
0.85V 12
0.9V
1.0V (N10M-G S)
0.92 5V (N10P- GS)
P-State
12
0,10
(1.8VS)IFPAB_IOVDD
(1.5VS)
GPU Mem NVCLK
(4) (1,5) (6)
(W) (W)
21.07
20.97
15.48
GPU Mem NVCLK
(4) (1,5) (6)
(W) (W)
13.36
14.29
8.28
/MCLK NVVDD
(MHz)
6.67
TBD
6.73
TBD
6.44
TBD
/MCLK NVVDD
(MHz)
2.93
TBD
3.10
TBD
2.91
TBD
(V) (A) (W ) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
TBD
18.25
TBD
19.17
TBD
13.95
(V) (A) (W ) (A) (W)
TBD
11.89
TBD
11.53
TBD
6.60
The ramp ti me for a ny rail mu st be more than 40us
VDD33
PEX_VDD
NVVDD
FBVDDQ
17.34
17.25
11.86
10.70
11.53
5.61
tNVVDD
FBVDD
2.06
2.03
1.90
FBVDD
0.66
0.70
0.62
FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)
3.09
4.09
3.05
4.09 6. 14
2.85
3.99
FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.5V)(1.5V)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
0.99
2.16
1.05
2.28 3. 42
0.93
2.20
(1.05V)
6.14
850 75 0.14
5.99
810
(1.05V)
3.24
792 75 0.14
3.3
782
0.89
0.88840
0.85
0.83
0.86817
0.82
PLLVDD
75 0.14
75 0.14
PLLVDD
75 0.14
75 0.14
PEX_ VDD can ramp u p any time
tNV- IFPAB_IOV DD
tNV-F BVDDQ
I/O and
PLLVDD
63 0.07
63 0.07
63 0.07
I/O and
PLLVDD
63 0.07
63 0.07
63 0.07
Other
(3.3V)(1.05V)(1.8V)
55 0.18
55 0.18
55 0.18
Other
(3.3V)(1.05V)(1.8V)
100 0.33
100 0.33
100 0.33
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/03/16 2010/03/15
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
D
Date: Sheet of
Compal Electronics, Inc.
VGA Notes List
LA-5752P
4 51Thurs day, October 29, 2009
E
0.3
5
D D
C C
VCC P_POK<46>
FROM P OWER VTT
POWER GOOD S IGNAL
B B
R1 84
1K_ 0402_1%
12
Layout rule 10m il wid th ：trace
length < 0.5 ", spa cing 20mil
+V CCP
H_ PROCH OT#<34, 48>
H_T HERM TRIP#<16>
+V CCP
H_ PM_S YNC<15>
H_ CPU PW RGD< 16>
PM_ DRAM _PWR GD<15>
R1 83
560_ 0402_5%
1 2
BUF _PLT_RS T#<16, 19,28, 29>
R5 64 0_04 02_5%
H_ PECI<16>
+V CCP
1.5K _0402_5 %
4
R5 6020_040 2_1%
1 2
R5 5820_040 2_1%
1 2
R5 4849.9_ 0402_1%
1 2
R5 5749.9_ 0402_1%
1 2
TP_ SKTOCC#
12
R1 6349. 9_04 02_1%
H_P ECI_I SO
1 2
R5 69 68_0 402_5%
12
H_ PROC HOT#
H_T HERM TRIP#
H_ CPUR ST#_ R
12
R1 3568_0 402_5%
H_ PM_ SYNC _R
R1 87
1 2
0_04 02_5%
VC CPW RGOO D_1
R1 90
1 2
0_04 02_5%
VC CPW RGOO D_0
R1 39
1 2
0_04 02_5%
VD DPW RGO OD_R
R1 91
1 2
0_04 02_5%
R1 85
PLT _RST#_R
1 2
12
COM P3
COM P2
COM P1
COM P0
H_ CATE RR#
VTT_POK
R1 86
750_ 0402_1%
JC PU1B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT#
AK15
THERMTRIP#
AP26
RESET_OBS#
AL15
PM_SYNC
AN14
VCCPWRGOOD_1
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
AM15
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
3
CL K_CP U_BC LK
MISC THERMAL
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
DDR3
MISC
PWR MANAGEMENT
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
AT28
AP27
AN28
TCK
AP28
TMS
AT27
AT29
TDI
AR27
TDO
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
CLK _CPU_ BCLK #
CLK _CPU_ ITP
CLK _CPU_ ITP#
CLK_EX P
CLK_ EXP#
SM_ DRAMR ST#
SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2
PM_EXTTS#0
PM_EXTTS#1
XDP _PRD Y#
XDP _PREQ#
XDP _TCK
XDP_TMS
XDP_TR ST#
XDP _TDI
XDP _TDO
R5 55 0_04 02_5%
XDP _DBRES ET#
XDP_B PM#0
XDP_B PM#1
XDP_B PM#2
XDP_B PM#3
XDP_B PM#4
XDP_B PM#5
XDP_B PM#6
XDP_B PM#7
T17 PA D
T18 PA D
3
1 2
R5 63 0_04 02_5%
T19 PA D
12
CL K_CPU _BCL K <16>
CLK _CPU_ BCLK # <16>
CLK_EX P <14>
pins u nused by
Clarks field on the
rPGA98 9 Pack age
CLK_E XP# <14>
PM_EX TTS#1_R <1 0,11>
2
DDR3 C ompensation Signals
SM_ RCOMP0
SM_ RCOMP1
SM_ RCOMP2
PM_EXTTS#0
PM_EXTTS#1
XDP _PREQ#
XDP_TMS
XDP _TDI
XDP _TDO
XDP _TCK
XDP_TR ST#
XDP _DBRES ET#
1 2
R5 67 100_ 0402_1%
1 2
R5 66 24.9 _0402_1 %
1 2
R5 65 130_ 0402_1%
Layout Note:Please these
resist ors near Processor
1 2
R5 61 10K _0402_5%
1 2
R5 62 10K _0402_5%
R1 36 51_0 402_1%@
1 2
R1 38 51_0 402_1%@
1 2
R5 56 51_0 402_1%@
1 2
R1 34 51_0 402_5%
1 2
R5 7 51_0 402_1%@
1 2
R1 33 51_0 402_5%
1 2
R1 37
1K_ 0402_5%@
1 2
1
+V CCP
+3VS
CHECK INTEL DOCUMENT #385422
Debug Port Design Guide Rev1.3
+1.5V
For In tel S3 Power Reduc tion.
5
+3V ALW
5
U8
2
P
B
DR AM_ PWRG D
VCC P_POK<46>
A A
VCC P_PO K
2N70 02_SOT2 3
5
4
Y
1
A
G
MC7 4VHC1 G08D FT2G SC70 5P
3
+5V ALW
12
R6 10
10K _0402_5%
S3_ 0.75V _EN
13
D
2
G
Q42
S
4
R1 95
1 2
1.5K _0402 _1%
750_ 0402_1%
S3_ 0.75V _EN <44>
R1 94
12
+1.5 V
12
R1 93
1.1K _0402_1 %
@
VD DPW RGO OD_R
12
R1 92
3K_ 0402_1%
@
R3 01
DDR3 CONN ECT ER
DRA MRST#<10, 11>
PCH GPIO CON TROL
DRA MRST _CNTR L_PC H<16>
DRA MRST _CNTR L_EC<34>
EC GPIO C ONT ROL
1K_ 0402_1%
1 2
1 2
R2 81 0_04 02_5%
1 2
R2 82 0_04 02_5%@
1 2
DRA MRST# SM_ DRAMR ST#
2N70 02_SOT 23
DRA MRST _CNTR L_R
C3 38
6
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
For In tel S3 Power Reduc tion.
@
R3 000 _0402_ 5%
D
S
1 3
Q27
G
2
1
0.01 U_040 2_16V7K
2
2
12
R2 83 100K _0402_5 %
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
3
Title
Compal Electronics, Inc.
Arrandale(1/5)-Thermal/XDP
LA-5752P
1
5 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
JC PU1A
DMI _CRX_PTX _N0<15>
DMI _CRX_PTX _N1<15>
DMI _CRX_PTX _N2<15>
DMI _CRX_PTX _N3<15>
DMI_C RX_PTX_P 0<15>
DMI_C RX_PTX_P 1<15>
D D
DMI_C RX_PTX_P 2<15>
DMI_C RX_PTX_P 3<15>
DMI _CTX_PRX _N0<15>
DMI _CTX_PRX _N1<15>
DMI _CTX_PRX _N2<15>
DMI _CTX_PRX _N3<15>
DMI_C TX_PRX_P 0<15>
DMI_C TX_PRX_P 1<15>
DMI_C TX_PRX_P 2<15>
DMI_C TX_PRX_P 3<15>
FDI _CTX_ PRX_N0<15>
FDI _CTX_ PRX_N1<15>
FDI _CTX_ PRX_N2<15>
FDI _CTX_ PRX_N3<15>
FDI _CTX_ PRX_N4<15>
FDI _CTX_ PRX_N5<15>
FDI _CTX_ PRX_N6<15>
FDI _CTX_ PRX_N7<15>
FDI _CTX_PRX _P0<15 >
FDI _CTX_PRX _P1<15 >
FDI _CTX_PRX _P2<15 >
FDI _CTX_PRX _P3<15 >
FDI _CTX_PRX _P4<15 >
FDI _CTX_PRX _P5<15 >
C C
FDI _CTX_PRX _P6<15 >
FDI _CTX_PRX _P7<15 >
FD I_F SYN C0<15>
FD I_F SYN C1<15>
FD I_I NT< 15>
FD I_L SYN C0<15>
FD I_L SYN C1<15>
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_F SYN C0
FD I_F SYN C1
FD I_I NT
FD I_L SY NC0
FD I_L SY NC1
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RCOMPO
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
B B
FD I_F SYN C0
FD I_F SYN C1
FD I_I NT
FD I_L SY NC0
FD I_L SY NC1
A A
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
R5 32 1K_ 0402_5%DI S@
1 2
R5 36 1K_ 0402_5%DI S@
1 2
R5 34 1K_ 0402_5%DI S@
1 2
R5 33 1K_ 0402_5%DI S@
1 2
R5 35 1K_ 0402_5%DI S@
1 2
PEG_ICOMPI
PEG_ICOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
4
EXP _ICOMPI
1 2
EXP _RBIAS
1 2
PCI E_CRX _GTX_N15
PCI E_CRX _GTX_N14
PCI E_CRX _GTX_N13
PCI E_CRX _GTX_N12
PCI E_CRX _GTX_N11
PCI E_CRX _GTX_N10
PCI E_CRX _GTX_N9
PCI E_CRX _GTX_N8
PCI E_CRX _GTX_N7
PCI E_CRX _GTX_N6
PCI E_CRX _GTX_N5
PCI E_CRX _GTX_N4
PCI E_CRX _GTX_N3
PCI E_CRX _GTX_N2
PCI E_CRX _GTX_N1
PCI E_CRX _GTX_N0
PCI E_CRX_GT X_P15
PCI E_CRX_GT X_P14
PCI E_CRX_GT X_P13
PCI E_CRX_GT X_P12
PCI E_CRX_GT X_P11
PCI E_CRX_GT X_P10
PCI E_CRX_GTX _P9
PCI E_CRX_GTX _P8
PCI E_CRX_GTX _P7
PCI E_CRX_GTX _P6
PCI E_CRX_GTX _P5
PCI E_CRX_GTX _P4
PCI E_CRX_GTX _P3
PCI E_CRX_GTX _P2
PCI E_CRX_GTX _P1
PCI E_CRX_GTX _P0
PCI E_CT X_GRX_C _N15
PCI E_CT X_GRX_C _N14
PCI E_CT X_GRX_C _N13
PCI E_CT X_GRX_C _N12
PCI E_CT X_GRX_C _N11
PCI E_CT X_GRX_C _N10
PCI E_CT X_GRX_C _N9
PCI E_CT X_GRX_C _N8
PCI E_CT X_GRX_C _N7
PCI E_CT X_GRX_C _N6
PCI E_CT X_GRX_C _N5
PCI E_CT X_GRX_C _N4
PCI E_CT X_GRX_C _N3
PCI E_CT X_GRX_C _N2
PCI E_CT X_GRX_C _N1
PCI E_CT X_GRX_C _N0
PCI E_CTX _GRX_C_P1 5
PCI E_CTX _GRX_C_P1 4
PCI E_CTX _GRX_C_P1 3
PCI E_CTX _GRX_C_P1 2
PCI E_CTX _GRX_C_P1 1
PCI E_CTX _GRX_C_P1 0
PCI E_CTX _GRX_C_P9
PCI E_CTX _GRX_C_P8
PCI E_CTX _GRX_C_P7
PCI E_CTX _GRX_C_P6
PCI E_CTX _GRX_C_P5
PCI E_CTX _GRX_C_P4
PCI E_CTX _GRX_C_P3
PCI E_CTX _GRX_C_P2
PCI E_CTX _GRX_C_P1
PCI E_CTX _GRX_C_P0
Layout rule tr：ace
length < 0.5"
R5 44 49.9 _0402_1 %
R5 45 750_ 0402_1%
PCI E_CRX _GTX _N[0..15] <19>
PCI E_CRX _GTX_P [0..15] <19>
PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal
VGA@
C5 27 0.1U _0402 _10V6K
1 2
C5 40 0.1U _0402 _10V6K
1 2
C5 29 0.1U _0402 _10V6K
1 2
C5 42 0.1U _0402 _10V6K
1 2
C5 31 0.1U _0402 _10V6K
1 2
C5 44 0.1U _0402 _10V6K
1 2
C5 33 0.1U _0402 _10V6K
1 2
C5 46 0.1U _0402 _10V6K
1 2
C5 35 0.1U _0402 _10V6K
1 2
C5 62 0.1U _0402 _10V6K
1 2
C5 64 0.1U _0402 _10V6K
1 2
C5 55 0.1U _0402 _10V6K
1 2
C5 57 0.1U _0402 _10V6K
1 2
C5 61 0.1U _0402 _10V6K
1 2
C5 48 0.1U _0402 _10V6K
1 2
C5 59 0.1U _0402 _10V6K
1 2
C5 28 0.1U _0402 _10V6K
1 2
C5 41 0.1U _0402 _10V6K
1 2
C5 30 0.1U _0402 _10V6K
1 2
C5 43 0.1U _0402 _10V6K
1 2
C5 32 0.1U _0402 _10V6K
1 2
C5 45 0.1U _0402 _10V6K
1 2
C5 34 0.1U _0402 _10V6K
1 2
C5 47 0.1U _0402 _10V6K
1 2
C5 36 0.1U _0402 _10V6K
1 2
C5 63 0.1U _0402 _10V6K
1 2
C5 65 0.1U _0402 _10V6K
1 2
C5 56 0.1U _0402 _10V6K
1 2
C5 58 0.1U _0402 _10V6K
1 2
C5 60 0.1U _0402 _10V6K
1 2
C5 49 0.1U _0402 _10V6K
1 2
C5 50 0.1U _0402 _10V6K
1 2
PCI E_CTX _GRX_N15
PCI E_CTX _GRX_N14
PCI E_CTX _GRX_N13
PCI E_CTX _GRX_N12
PCI E_CTX _GRX_N11
PCI E_CTX _GRX_N10
PCI E_CTX _GRX_N9
PCI E_CTX _GRX_N8
PCI E_CTX _GRX_N7
PCI E_CTX _GRX_N6
PCI E_CTX _GRX_N5
PCI E_CTX _GRX_N4
PCI E_CTX _GRX_N3
PCI E_CTX _GRX_N2
PCI E_CTX _GRX_N1
PCI E_CTX _GRX_N0
PCI E_CTX_G RX_P15
PCI E_CTX_G RX_P14
PCI E_CTX_G RX_P13
PCI E_CTX_G RX_P12
PCI E_CTX_G RX_P11
PCI E_CTX_G RX_P10
PCI E_CTX_GRX _P9
PCI E_CTX_GRX _P8
PCI E_CTX_GRX _P7
PCI E_CTX_GRX _P6
PCI E_CTX_GRX _P5
PCI E_CTX_GRX _P4
PCI E_CTX_GRX _P3
PCI E_CTX_GRX _P2
PCI E_CTX_GRX _P1
PCI E_CTX_GRX _P0
PCI E_CT X_GRX _N[0..15] <19>
PCI E_CT X_GRX_P [0..15] <19>
3
R5 9
@
1 2
3.01 K_040 2_1%
FOR ES1 S AMP LE ONLY
R5 47
0_04 02_5%
@
1 2
@
1 2
R5 46
0_04 02_5%
CFG Straps for PROCESSOR
CF G0
PCI-Ex press Configuration Select
CFG0
Not ap plica ble f or Clarksfield Processor
CFG[1:0] 11 =1*16 PEG
CF G3
CFG3-P CI Ex press Static Lane Reversal
CF G4
CFG4-D isplay Port Presence
CFG4
@
1 2
R5 8 3. 01K_0 402_1%
1: Single PEG
0: Bif urcation enabled
10=2*8 PEG
1 2
R6 1 3. 01K_0 402_1%
1: Nor mal Operation
0: Lan e Numbers Reversed
CFG3
15 -> 0, 14 ->1, .....
@
1 2
R6 0 3. 01K_0 402_1%
1: Dis abled ; No Physical Display Port
attach ed to Embedded Display Port
0: Ena bled; An external Display Port
device is c onnected to the Embedded
Display Port
CF G0
CF G3
CF G4
CF G7
H_ RSV D17_R
H_ RSV D18_R
2
JC PU1E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
RESERVED
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
1
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AP1
AT2
AT3
AR1
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
KEY
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
VSS
RS VD6 4_R
RS VD6 5_R
R1 89
0_04 02_5%
R1 88
0_04 02_5%
@
12
@
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Arrandale(2/5)-DMI/PEG/FDI
LA-5752P
1
6 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
4
3
2
1
AR10
AT10
JC PU1 D
W8
SB_CK[0]
W9
SB_CK#[0]
B5
SB_DQ[0]
A5
SB_DQ[1]
C3
SB_DQ[2]
B3
SB_DQ[3]
E4
SB_DQ[4]
A6
SB_DQ[5]
A4
SB_DQ[6]
C4
SB_DQ[7]
D1
SB_DQ[8]
D2
SB_DQ[9]
F2
SB_DQ[10]
F1
SB_DQ[11]
C2
SB_DQ[12]
F5
SB_DQ[13]
F3
SB_DQ[14]
G4
SB_DQ[15]
H6
SB_DQ[16]
G2
SB_DQ[17]
J6
SB_DQ[18]
J3
SB_DQ[19]
G1
SB_DQ[20]
G5
SB_DQ[21]
J2
SB_DQ[22]
J1
SB_DQ[23]
J5
SB_DQ[24]
K2
SB_DQ[25]
L3
SB_DQ[26]
M1
SB_DQ[27]
K5
SB_DQ[28]
K4
SB_DQ[29]
M4
SB_DQ[30]
N5
SB_DQ[31]
AF3
SB_DQ[32]
AG1
SB_DQ[33]
AJ3
SB_DQ[34]
AK1
SB_DQ[35]
AG4
SB_DQ[36]
AG3
SB_DQ[37]
AJ4
SB_DQ[38]
AH4
SB_DQ[39]
AK3
SB_DQ[40]
AK4
SB_DQ[41]
AM6
SB_DQ[42]
AN2
SB_DQ[43]
AK5
SB_DQ[44]
AK2
SB_DQ[45]
AM4
SB_DQ[46]
AM3
SB_DQ[47]
AP3
SB_DQ[48]
AN5
SB_DQ[49]
AT4
SB_DQ[50]
AN6
SB_DQ[51]
AN4
SB_DQ[52]
AN3
SB_DQ[53]
AT5
SB_DQ[54]
AT6
SB_DQ[55]
AN7
SB_DQ[56]
AP6
SB_DQ[57]
AP8
SB_DQ[58]
AT9
SB_DQ[59]
AT7
SB_DQ[60]
AP9
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AB1
SB_BS[0]
W5
SB_BS[1]
R7
SB_BS[2]
AC5
SB_CAS#
Y7
SB_RAS#
AC6
SB_WE#
DDR SYSTEM MEMORY - B
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
M3
V7
V6
M2
AB8
AD6
AC7
AD1
D4
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DD R_B_ DM0
DD R_B_ DM1
DD R_B_ DM2
DD R_B_ DM3
DD R_B_ DM4
DD R_B_ DM5
DD R_B_ DM6
DD R_B_ DM7
DD R_B_ DQS# 0
DD R_B_ DQS# 1
DD R_B_ DQS# 2
DD R_B_ DQS# 3
DD R_B_ DQS# 4
DD R_B_ DQS# 5
DD R_B_ DQS# 6
DD R_B_ DQS# 7
DD R_B _DQS 0
DD R_B _DQS 1
DD R_B _DQS 2
DD R_B _DQS 3
DD R_B _DQS 4
DD R_B _DQS 5
DD R_B _DQS 6
DD R_B _DQS 7
DDR_ B_M A0
DDR_ B_M A1
DDR_ B_M A2
DDR_ B_M A3
DDR_ B_M A4
DDR_ B_M A5
DDR_ B_M A6
DDR_ B_M A7
DDR_ B_M A8
DDR_ B_M A9
DDR_ B_MA 10
DDR_ B_MA 11
DDR_ B_MA 12
DDR_ B_MA 13
DDR_ B_MA 14
DDR_ B_MA 15
M_ CLK_D DR2 < 11>
M_ CLK_D DR#2 <11>
DDR_ CKE2 _DIM MB <11>
M_ CLK_D DR3 < 11>
M_ CLK_D DR#3 <11>
DDR_ CKE3 _DIM MB <11>
DDR_ CS2_ DIMM B# <11>
DDR_ CS3_ DIMM B# <11>
M_ODT 2 <11>
M_ODT 3 <11>
DD R_B_ DM[0 ..7] < 11>
DD R_B_ DQS# [0..7 ] <11>
DD R_B _DQS [0..7 ] <11>
DDR_ B_MA [0.. 15] <1 1>
JC PU1 C
D D
DD R_A _D[0 ..63]<10>
C C
B B
DD R_A_B S0<10>
DD R_A_B S1<10>
DD R_A_B S2<10>
DD R_A_ CAS#<10>
DD R_A_ RAS#<10>
DD R_A _WE#<10>
DD R_A _D0
DD R_A _D1
DD R_A _D2
DD R_A _D3
DD R_A _D4
DD R_A _D5
DD R_A _D6
DD R_A _D7
DD R_A _D8
DD R_A _D9
DD R_A _D10
DD R_A _D11
DD R_A _D12
DD R_A _D13
DD R_A _D14
DD R_A _D15
DD R_A _D16
DD R_A _D17
DD R_A _D18
DD R_A _D19
DD R_A _D20
DD R_A _D21
DD R_A _D22
DD R_A _D23
DD R_A _D24
DD R_A _D25
DD R_A _D26
DD R_A _D27
DD R_A _D28
DD R_A _D29
DD R_A _D30
DD R_A _D31
DD R_A _D32
DD R_A _D33
DD R_A _D34
DD R_A _D35
DD R_A _D36
DD R_A _D37
DD R_A _D38
DD R_A _D39
DD R_A _D40
DD R_A _D41
DD R_A _D42
DD R_A _D43
DD R_A _D44
DD R_A _D45
DD R_A _D46
DD R_A _D47
DD R_A _D48
DD R_A _D49
DD R_A _D50
DD R_A _D51
DD R_A _D52
DD R_A _D53
DD R_A _D54
DD R_A _D55
DD R_A _D56
DD R_A _D57
DD R_A _D58
DD R_A _D59
DD R_A _D60
DD R_A _D61
DD R_A _D62
DD R_A _D63
AJ10
AL10
AK12
AK11
AM10
AR11
AL11
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
A10
SA_DQ[0]
C10
SA_DQ[1]
C7
SA_DQ[2]
A7
SA_DQ[3]
B10
SA_DQ[4]
D10
SA_DQ[5]
E10
SA_DQ[6]
A8
SA_DQ[7]
D8
SA_DQ[8]
F10
SA_DQ[9]
E6
SA_DQ[10]
F7
SA_DQ[11]
E9
SA_DQ[12]
B7
SA_DQ[13]
E7
SA_DQ[14]
C6
SA_DQ[15]
H10
SA_DQ[16]
G8
SA_DQ[17]
K7
SA_DQ[18]
J8
SA_DQ[19]
G7
SA_DQ[20]
G10
SA_DQ[21]
J7
SA_DQ[22]
J10
SA_DQ[23]
L7
SA_DQ[24]
M6
SA_DQ[25]
M8
SA_DQ[26]
L9
SA_DQ[27]
L6
SA_DQ[28]
K8
SA_DQ[29]
N8
SA_DQ[30]
P9
SA_DQ[31]
AH5
SA_DQ[32]
AF5
SA_DQ[33]
AK6
SA_DQ[34]
AK7
SA_DQ[35]
AF6
SA_DQ[36]
AG5
SA_DQ[37]
AJ7
SA_DQ[38]
AJ6
SA_DQ[39]
SA_DQ[40]
AJ9
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
AK8
SA_DQ[44]
AL7
SA_DQ[45]
SA_DQ[46]
AL8
SA_DQ[47]
AN8
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
AM9
SA_DQ[52]
AN9
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AC3
SA_BS[0]
AB2
SA_BS[1]
U7
SA_BS[2]
AE1
SA_CAS#
AB3
SA_RAS#
AE9
SA_WE#
DDR SYSTEM MEMORY A
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7
DD R_A_ DQS# 0
DD R_A_ DQS# 1
DD R_A_ DQS# 2
DD R_A_ DQS# 3
DD R_A_ DQS# 4
DD R_A_ DQS# 5
DD R_A_ DQS# 6
DD R_A_ DQS# 7
DD R_A _DQS 0
DD R_A _DQS 1
DD R_A _DQS 2
DD R_A _DQS 3
DD R_A _DQS 4
DD R_A _DQS 5
DD R_A _DQS 6
DD R_A _DQS 7
DDR_ A_M A0
DDR_ A_M A1
DDR_ A_M A2
DDR_ A_M A3
DDR_ A_M A4
DDR_ A_M A5
DDR_ A_M A6
DDR_ A_M A7
DDR_ A_M A8
DDR_ A_M A9
DDR_ A_MA 10
DDR_ A_MA 11
DDR_ A_MA 12
DDR_ A_MA 13
DDR_ A_MA 14
DDR_ A_MA 15
M_ CLK_D DR0 <1 0>
M_C LK_DD R#0 < 10>
DDR_ CKE0 _DIMM A <10>
M_ CLK_D DR1 <1 0>
M_C LK_DD R#1 < 10>
DDR_ CKE1 _DIMM A <10>
DDR_ CS0_ DIMM A# <10>
DDR_ CS1_ DIMM A# <10>
M_ODT 0 <10>
M_ODT 1 <10>
DD R_A_ DM[0 ..7] < 10>
DD R_A_ DQS# [0..7 ] <10>
DD R_A_ DQS[ 0..7] <10>
DDR_ A_MA [0.. 15] <10 >
DD R_B _D[0 ..63]<11>
DD R_B_B S0<11>
DD R_B_B S1<11>
DD R_B_B S2<11>
DD R_B_ CAS#<11>
DD R_B_ RAS#<11>
DD R_B_ WE#<11>
DD R_B _D0
DD R_B _D1
DD R_B _D2
DD R_B _D3
DD R_B _D4
DD R_B _D5
DD R_B _D6
DD R_B _D7
DD R_B _D8
DD R_B _D9
DD R_B _D10
DD R_B _D11
DD R_B _D12
DD R_B _D13
DD R_B _D14
DD R_B _D15
DD R_B _D16
DD R_B _D17
DD R_B _D18
DD R_B _D19
DD R_B _D20
DD R_B _D21
DD R_B _D22
DD R_B _D23
DD R_B _D24
DD R_B _D25
DD R_B _D26
DD R_B _D27
DD R_B _D28
DD R_B _D29
DD R_B _D30
DD R_B _D31
DD R_B _D32
DD R_B _D33
DD R_B _D34
DD R_B _D35
DD R_B _D36
DD R_B _D37
DD R_B _D38
DD R_B _D39
DD R_B _D40
DD R_B _D41
DD R_B _D42
DD R_B _D43
DD R_B _D44
DD R_B _D45
DD R_B _D46
DD R_B _D47
DD R_B _D48
DD R_B _D49
DD R_B _D50
DD R_B _D51
DD R_B _D52
DD R_B _D53
DD R_B _D54
DD R_B _D55
DD R_B _D56
DD R_B _D57
DD R_B _D58
DD R_B _D59
DD R_B _D60
DD R_B _D61
DD R_B _D62
DD R_B _D63
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
Arrandale(3/5)-DDR III
LA-5752P
1
7 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
+C PU_C ORE
JC PU1 F
D D
C C
B B
A A
48A 15A18A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
CPU CO RE SUP PLY
5
POWER
1.1V R AIL PO WER
CPU VI DS
SENSE LINES
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
AH14
10U_ 0805_10 V4K
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
G15
VTT_S ELECT
H_ VID 0
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
H_ VID 5
H_ VID 6
PM_ DPRS LPVR _R
10U_ 0805_10 V4K
C2 01
1
1
2
2
10U_ 0805_10 V4K
10U_ 0805_10 V4K
C2 71
1
1
@
2
2
10U_ 0805_10 V4K
C2 08
1
1
2
2
R6 08 1K_ 0402_5%
1 2
R5 6 0_ 0402_5%
C1 99
1
2
C2 70
1
@
2
+V CCP
10U_ 0805_10 V4K
C2 09
1 2
PSI # <48>
H_ VID [0..6 ] <48>
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
H_VTTVID1 = High, 1.05V FOR Auburndale
AN35
AJ34
AJ35
B15
A15
VCC _SEN SE
VSS _SENS E
IMV P_IMON <48>
0_04 02_5%
R5 54
1 2
1 2
R5 53 0_04 02_5%
VTT_S ENSE <4 6>
@
T15PA D
Clo se to CP U
VCC SENS E
VSS SENSE
1 2
R5 52 10 0_0402_ 1%
1 2
R5 51 10 0_0402_ 1%
10U_ 0805_10 V4K
C1 98
10U_ 0805_10 V4K
C2 16
10U_ 0805_10 V4K
1
2
10U_ 0805_10 V4K
1
2
1
2
VCC SENS E
VSS SENSE
4
C1 81
1
+
2
C1 82
1
2
10U_ 0805_ 10V4K
C2 19
+C PU_C ORE
4
+V CCP
330U _D2_2 .5VY _R9M
C5 54
10U_ 0805_10 V4K
C2 00
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 74
C2 17
1
1
2
2
PR OC_DP RSLP VR <48 >
VTT_S ELECT <46 >
VC CSEN SE <48>
VSS SENSE <48>
+V CCP
3
+GF X_CORE
22U_ 0805_ 6.3V6M
1
C1 60
C1 61
@
2
22U_ 0805_6. 3V6M
12
R5 59
0_04 02_5%
DI S@
10U_ 0805_ 10V4K
C2 07
1
2
CPU
1
C1 91
@
2
22U_ 0805_6. 3V6M
1
SUS P<39, 44,45>
22U_ 0805_6. 3V6M
1
C1 90
@
2
22U_ 0805_ 6.3V6M
1
1
C1 89
@
UMA @
2
2
22U_ 0805_6. 3V6M
+V CCP
1
2
+1.5 V + 1.5V_ DDR3
+5V ALW
R2 68
20K _0402_5%
1.5V _DDR 3_GAT E
13
D
2
G
S
3
1
1
C5 91
C1 59
UMA @
UMA @
2
2
10U_ 0805_ 6.3V6M
10U_ 0805_10 V4K
10U_ 0805_10 V4K
C2 15
C2 14
1
2
J3
2
JUM P_43X118
@
J2
2
JUM P_43X118
@
U1 1
8
D
7
D
6
D
5
D
SI4 800BD Y-T1-E 3_SO8
Q23
2N70 02_SOT2 3
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10U_ 0805_ 6.3V6M
1
C5 92
UMA @
2
+V CCP
10U_ 0805_ 10V4K
C2 10
1
2
10U_ 0805_10 V4K
C2 72
1
2
112
112
1
S
2
S
3
S
4
G
R2 67
0_04 02_5%
@
1 2
1
2
1
2
JC PU1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
10U_ 0805_ 10V4K
C2 11
10U_ 0805_10 V4K
C2 40
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC, AUB_C FD_r PGA, R1P0
ME@
GRAPHI CS
FDI PEG & DMI
For In tel S3 Power Reduc tion.
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C2 89
1
1
2
+1 .5V_D DR3
1
C3 25
0.1U _0603 _25V7K
2
2008/10/31 2009/10/31
2
Compal Secret Data
POWER
+1.5 V
0.1U _0402 _10V6K
C2 88
C2 87
1
2
Deciphered Date
2
SENSE
3A
0.6A
1
2
2
LINES
GRA PHI CS VIDs
0.1U _0402 _10V6K
VAXG_SENSE
VSSAXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
DDR3 - 1.5V RAILS
1.1V1.8V
VCCPLL1
VCCPLL2
VCCPLL3
C2 86
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
AN24
GFX _VR_E N
AR25
AT25
GFX _IMON
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
2
SUS P
UMA @
1 2
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C2 54
1
1
2
2
22U_ 0805_6. 3V6M
220U _B2_ 2.5VM_R3 5
C2 68
1
1
+
@
2
2
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C1 67
C1 49
1
2
1
1
2
2
+1 .5V_ DDR3
0.1U _0402 _10V6K
C2 69
1
@
2
2
G
For In tel S3 Power Reduc tion.
1
GFX _IMON
R1 32
DI S@
1K_ 0402_5%
12
AS NO CONNECT
BUT A SMALL AMOUNT OF POWER
VCC _AXG_S ENSE < 47>
VSS_A XG_SENS E <47>
GFX VR_V ID_0 <47>
GFX VR_V ID_1 <47>
GFX VR_V ID_2 <47>
GFX VR_V ID_3 <47>
GFX VR_V ID_4 <47>
GFX VR_V ID_5 <47>
GFX VR_V ID_6 <47>
R1 41 0_04 02_5%
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
C2 53
C2 56
1
1
2
2
22U_ 0805_6. 3V6M
Modify for cost revew.
C2 58
C2 52
1
09/16/2009
2
+V CCP
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 73
1
1
2
2
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C2 18
1
1
2
2
2.2U _0603 _6.3V 4Z
10U_ 0805_ 10V4K
C1 68
C1 69
1
2
12
R2 33
220_ 0402_5%
13
D
Q19
BSS 138_NL_ SOT23-3
S
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
(~15MW ) MAYB E WASTED
DESIGN GU IDE RE V1.1
R1 40
1 2
UMA @
1
+1 .5V_D DR3
1U_0 603_1 0V4Z
C2 55
1
2
C2 12
+VC CP
C2 13
+1.8V S
4.7U _0603 _6.3V6K
C1 70
1
2
GFX _VR_E N
GFX VR_EN <47>
GFX VR_D PRSLPV R <47>
GFX VR_IMO N <47>
C2 57
Compal Electronics, Inc.
Arrandale(4/5)-PWR
LA-5752P
1
8 5 1Thur sday , Oc tobe r 29, 2009
4.7K _0402 _5%
0. 3
5
JC PU1 H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
D D
C C
B B
AR17
AR15
AR12
AP20
AP17
AP13
AP10
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AL34
AL31
AL23
AL20
AL17
AL12
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AG10
AE35
VSS8
VSS9
VSS10
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
VSS15
VSS16
VSS17
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
4
JC PU1 I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
VSS
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
NCTF
AT1
AR34
B34
B2
B1
A35
VSS _NCT F2_R
VSS _NCT F3_R
VSS _NCT F4_R
VSS _NCT F5_R
VSS _NCT F6_R
VSS _NCT F7_R
VSS _NCT F1_R
AT35
3
+C PU_C ORE
2
1
CPU CORE
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 85
C5 68
1
1
2
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 63
C1 47
1
1
2
2
10U_ 0805_6. 3V6M
10U_ 0805_6. 3V6M
C1 92
C1 95
1
1
2
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 80
1
2
10U_ 0805_ 6.3V6M
C1 62
1
2
10U_ 0805_6. 3V6M
C8 8
1
2
22U_ 0805_6. 3V6M
C5 79
1
2
1
2
1
2
C5 74
1
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 93
C1 79
1
2
10U_ 0805_6. 3V6M
10U_ 0805_6. 3V6M
C1 96
C1 80
1
2
Under cavity
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 84
C5 73
1
1
2
2
10U_ 0805_ 6.3V6M
C1 66
1
1
2
2
10U_ 0805_6. 3V6M
C8 9
1
1
2
2
C5 78
1
2
10U_ 0805_ 6.3V6M
10U_ 0805_ 6.3V6M
C1 48
C1 65
1
2
10U_ 0805_6. 3V6M
C1 97
22U_ 0805_6. 3V6M
C5 83
1
2
1
2
1
2 3
C5 77
1
2
10U_ 0805_ 6.3V6M
C1 94
between Inductor and socket
470U _D2T_2VM
470U _D2T_2VM
C7 6
C7 5
1
+
+
2 3
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C5 71
C5 72
1
1
2
470U _D2T_2VM
1
+
2 3
2
C9 2
1
+
2 3
Inside cavity
470U _D2T_2VM
C1 64
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C9 1
1
1
2
2
22U_ 0805_6. 3V6M
22U_ 0805_6. 3V6M
C9 0
C1 29
C8 7
1
1
2
2
470uF 4.5mohm
IC, AUB_C FD_r PGA, R1P0
ME@
A A
5
IC ,AUB _CFD_ rPGA ,R1P 0
ME@
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber Re v
Cu stom
Da te: She et o f
Compal Electronics, Inc.
Arrandale(5/5)-GND/Bypass
LA-5752P
1
9 5 1Thur sday , Oc tobe r 29, 2009
0. 3
5
+VR EF_D Q_DIMM A
+VR EF_D Q_DIMM A
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C3 03
1
1
2
D D
C C
B B
A A
2
DDR_ CKE0 _DIMM A<7>
DDR_ A_BS 2<7>
M_ CLK_D DR0<7>
M_C LK_DD R#0< 7>
DDR_ A_BS 0<7>
DD R_A_ WE#<7>
DD R_A_ CAS#< 7>
DDR_ CS1_ DIMM A#<7>
+3VS
1
2
5
DD R_A _D0
C3 47
DD R_A _D1
DD R_A_ DM0
DD R_A _D2
DD R_A _D3
DD R_A _D8
DD R_A _D9
DD R_A_ DQS# 1
DD R_A _DQS 1
DD R_A _D10
DD R_A _D11
DD R_A _D16
DD R_A _D17
DD R_A_ DQS# 2
DD R_A _DQS 2
DD R_A _D18
DD R_A _D19
DD R_A _D24
DD R_A _D25
DD R_A_ DM3
DD R_A _D26
DD R_A _D27
DDR_ CKE0 _DIM MA
DD R_A_ BS2
DDR_ A_MA 12
DDR_ A_M A9
DDR_A_MA8
DDR_ A_M A5
DDR_ A_M A3
DDR_ A_M A1
M _CLK_ DDR0
M _CLK_ DDR#0
DDR_ A_MA 10
DD R_A_ BS0
DD R_A _WE#
DD R_A_ CAS# M_OD T0
DDR_ A_MA 13
DDR_ CS1_ DIMM A#
DD R_A _D32
DD R_A _D33
DD R_A_ DQS# 4
DD R_A _DQS 4
DD R_A _D34
DD R_A _D35
DD R_A _D40
DD R_A _D41
DD R_A_ DM5
DD R_A _D42
DD R_A _D43
DD R_A _D48
DD R_A _D49
DD R_A_ DQS# 6
DD R_A _DQS 6
DD R_A _D50
DD R_A _D51
DD R_A _D56
DD R_A _D57
DD R_A_ DM7
DD R_A _D58
DD R_A _D59
1 2
10K _0402_5%
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C6 08
C6 17
1
2
+1.5 V + 1.5V
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
DDR3 SO-DIMM A
JDI MM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
R5 70
10K _0402_5%
12
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
R5 71
VTT1
205
G1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
FOX _AS0 A626-U4S N-7F
ME@
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
4
DD R_A _D4
DD R_A _D5
DD R_A_ DQS# 0
DD R_A _DQS 0
DD R_A _D6
DD R_A _D7
DD R_A _D12
DD R_A _D13
DD R_A_ DM1
DRA MRST#
DD R_A _D14
DD R_A _D15
DD R_A _D20
DD R_A _D21
DD R_A_ DM2
DD R_A _D22
DD R_A _D23
DD R_A _D28
DD R_A _D29
DD R_A_ DQS# 3
DD R_A _DQS 3
DD R_A _D30
DD R_A _D31
DDR_ CKE1 _DIM MA
DDR_ A_MA 15
DDR_ A_MA 14
DDR_A_MA 11
DDR_ A_M A7
DDR_A_MA6
DDR_ A_M A4
DDR_ A_M A2
DDR_ A_M A0
M _CLK_ DDR1
M _CLK_ DDR#1
DD R_A_ BS1
DD R_A_ RAS#
DDR_ CS0_ DIMM A#
M_OD T1
DD R_A _D36
DD R_A _D37
DD R_A_ DM4
DD R_A _D38
DD R_A _D39
DD R_A _D44
DD R_A _D45
DD R_A_ DQS# 5
DD R_A _DQS 5
DD R_A _D46
DD R_A _D47
DD R_A _D52
DD R_A _D53
DD R_A_ DM6
DD R_A _D54
DD R_A _D55
DD R_A _D60
DD R_A _D61
DD R_A_ DQS# 7
DD R_A _DQS 7
DD R_A _D62
DD R_A _D63
PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3
+0.7 5VS
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V6 5A @ 0. 7 5V
4
DRA MRST# <5,11>
DDR_ CKE1 _DIMM A <7>
M_ CLK_D DR1 <7>
M_C LK_DD R#1 <7>
DDR_ A_BS 1 <7>
DD R_A_ RAS# <7>
DDR_ CS0_ DIMM A# <7>
M_ODT 0 <7>
M_ODT 1 <7>
0.1U _0402 _10V6K
C3 46
1
1
2
2
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
VREF =
1*0402 0.1uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
PM_EX TTS#1_R <5 ,11>
SMB_D ATA_S3 <11,1 2,14,28 >
SMB _CLK_S3 <11, 12,14, 28>
DD R_A _D[0 ..63]<7>
DD R_A_ DM[0 ..7]<7>
DD R_A _DQS [0..7 ]<7>
DD R_A_ DQS# [0..7 ]<7>
DDR_ A_MA [0.. 15]<7>
+VR EF_D Q_DIMM A
2.2U _0603 _6.3V 4Z
C3 55
4*0402 1uf
1*0402 2.2uf
3
Lay ou t N ote:
Pl ace near DIM M
+1.5 V
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
C5 88
C5 89
1
1
@
@
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
C5 81
C5 86
1
2
+0.7 5VS
C6 07
C6 05
1U_0 603_1 0V4Z
1
1
2
2
Compal Secret Data
1
2
1U_0 603_1 0V4Z
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
C3 10
1
2
C6 06
C3 00
1U_0 603_1 0V4Z
1
2
Deciphered Date
2
10U_ 0603_ 6.3V6M
C5 70
C3 09
1
1
2
2
C3 01
1U_0 603_1 0V4Z
1U_0 603_1 0V4Z
1
1
2
2
2
1
+1.5V
12
R2 97
1K_ 0402_1%
1K_ 0402_1%
For Arr anale only +V REF_DQ_DIMMA
supply f rom a exte rnal 1 .5V v oltage divide
circuit.
07/ 17/2009
10U_ 0603_ 6.3V6M
10U_ 0603_ 6.3V6M
0.1U _0402 _10V6K
C3 08
1
2
C3 14
1
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 17
C3 15
1
1
2
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
1
2
2
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
R3 05
0.1U _0402 _10V6K
C3 16
+VR EF_D Q_DIMM A
12
1
+
C5 69
220U _B2_ 2.5VM_R 35
2
LA-5752P
1
10 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
+VR EF_D Q_DIMM B
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
1
C3 82
+3VS
2
DDR_ CKE2 _DIM MB<7>
DD R_B_B S2<7>
M_ CLK_D DR2<7>
M_ CLK_D DR#2<7>
DD R_B_B S0<7>
DD R_B _WE#<7>
DD R_B_ CAS#<7>
DDR_ CS3_ DIMM B#<7>
2.2U _0603 _6.3V 4Z
1
2
D D
C C
B B
A A
+VR EF_D Q_DIMM B
DD R_B _D0
DD R_B _D1
1
C3 84
DD R_B_ DM0
2
DD R_B _D2
DD R_B _D3
DD R_B _D8
DD R_B _D9
DD R_B_ DQS# 1
DD R_B _DQS 1
DD R_B _D10
DD R_B _D11
DD R_B _D16
DD R_B _D17
DD R_B_ DQS# 2
DD R_B _DQS 2
DD R_B _D19
DD R_B _D24
DD R_B _D25
DD R_B_ DM3
DD R_B _D26
DD R_B _D27
DDR_ CKE2 _DIM MB
DD R_B_ BS2
DDR_ B_MA 12
DDR_ B_M A9
DDR_B_MA8
DDR_ B_M A5
DDR_ B_M A3
DDR_ B_M A1
M _CLK_ DDR2
M _CLK_ DDR#2
DDR_ B_MA 10
DD R_B_ BS0
DD R_B _WE#
DD R_B_ CAS#
DDR_ B_MA 13
DDR_ CS3_ DIMM B#
DD R_B _D32
DD R_B _D33
DD R_B_ DQS# 4
DD R_B _DQS 4
DD R_B _D34
DD R_B _D35
DD R_B _D40
DD R_B _D41
DD R_B_ DM5
DD R_B _D42
DD R_B _D43
DD R_B _D48
DD R_B _D49
DD R_B_ DQS# 6
DD R_B _DQS 6
DD R_B _D50
DD R_B _D51
DD R_B _D56
DD R_B _D57
DD R_B_ DM7
DD R_B _D58
DD R_B _D59
1 2
10K _0402_5%
0.1U _0402 _10V6K
C6 18
C6 16
1
2
5
+1.5V +1.5V
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
JDI MM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
R5 72
1 2
R5 73 10K _0402_5%
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYC O_2- 2013297- 2~D
ME@
DQS0#
DQS0
DQ12
DQ13
RESET#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
VREF_CA
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
EVENT#
GND1
2
VSS
4
DQ4
6
DQ5
8
VSS
10
12
14
VSS
16
DQ6
18
DQ7
20
VSS
22
24
26
VSS
28
DM1
30
32
VSS
34
36
38
VSS
40
42
44
VSS
46
DM2
48
VSS
50
52
54
VSS
56
58
60
VSS
62
64
66
VSS
68
70
72
VSS
74
76
VDD
78
A15
80
A14
82
VDD
84
A11
86
A7
88
VDD
90
A6
92
A4
94
VDD
96
A2
98
A0
100
VDD
102
CK1
104
106
VDD
108
BA1
110
112
VDD
114
S0#
116
118
VDD
120
122
NC
124
VDD
126
128
VSS
130
132
134
VSS
136
DM4
138
VSS
140
142
144
VSS
146
148
150
VSS
152
154
156
VSS
158
160
162
VSS
164
166
168
VSS
170
DM6
172
VSS
174
176
178
VSS
180
182
184
VSS
186
188
190
VSS
192
194
196
VSS
198
200
SDA
202
SCL
204
VTT
206
4
DD R_B _D4
DD R_B _D5
DD R_B_ DQS# 0
DD R_B _DQS 0
DD R_B _D6
DD R_B _D7
DD R_B _D12
DD R_B _D13
DD R_B_ DM1
DRA MRST#
DD R_B _D14
DD R_B _D15
DD R_B _D20
DD R_B _D21
DD R_B_ DM2
DD R_B _D22
DD R_B _D23DDR _B_ D18
DD R_B _D28
DD R_B _D29
DD R_B_ DQS# 3
DD R_B _DQS 3
DD R_B _D30
DD R_B _D31
DDR_ CKE3 _DIM MB
DDR_ B_MA 15
DDR_ B_MA 14
DDR_B_MA 11
DDR_ B_M A7
DDR_B_MA6
DDR_ B_M A4
DDR_ B_M A2
DDR_ B_M A0
M _CLK_ DDR3
M _CLK_ DDR#3
DD R_B_ BS1
DD R_B_ RAS#
DDR_ CS2_ DIMM B#
M_OD T2
M_OD T3
DD R_B _D36
DD R_B _D37
DD R_B_ DM4
DD R_B _D38
DD R_B _D39
DD R_B _D44
DD R_B _D45
DD R_B_ DQS# 5
DD R_B _DQS 5
DD R_B _D46
DD R_B _D47
DD R_B _D52
DD R_B _D53
DD R_B_ DM6
DD R_B _D54
DD R_B _D55
DD R_B _D60
DD R_B _D61
DD R_B_ DQS# 7
DD R_B _DQS 7
DD R_B _D62
DD R_B _D63
PM_EX TTS#1_R
SMB _DATA_S3
SMB _CLK_S 3
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V6 5A @ 0. 7 5V
4
DD R_B_ DQS# [0..7 ]<7>
DD R_B _D[0 ..63]<7>
DD R_B_ DM[0 ..7]<7>
DD R_B_ DQS[ 0..7]<7>
DDR_ B_MA [0.. 15]<7>
DRA MRST# <5,1 0>
DDR_ CKE3 _DIM MB <7>
M_ CLK_ DDR3 <7>
M_ CLK_D DR#3 <7>
DD R_B_B S1 <7>
DD R_B_ RAS# <7>
DDR_ CS2_ DIMM B# <7>
M_OD T2 <7>
M_OD T3 <7>
1
2
0.1U _0402 _10V6K
C3 85
+VR EF_D Q_DIMMB
2.2U _0603 _6.3V 4Z
C3 83
1
2
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
1*0402 0.1uf
4*0402 1uf
1*0402 2.2uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
PM_EX TTS#1_R <5 ,10>
SMB_ DATA_S3 <10, 12,14,2 8>
SMB _CLK_S3 <10, 12,14, 28>
+0.7 5VS
3
Lay ou t N ote:
Pl ace near DIM M
+1.5V
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C5 82
1
@
@
2
Lay ou t N ote:
Pl ace near DIM M
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
10U_ 0603_6. 3V6M
C5 87
C5 76
1
1
2
2
+0.7 5VS
1U_0 603_1 0V4Z
10U_ 0603_ 6.3V6M
C5 95
C5 96
1
1
2
2
2008/10/31 2009/10/31
10U_ 0603_6. 3V6M
C3 11
1
2
1U_0 603_1 0V4Z
C2 99
1
2
10U_ 0603_6. 3V6M
C3 13
1
2
1U_0 603_1 0V4Z
C5 98
1
2
Compal Secret Data
10U_ 0603_6. 3V6M
C5 75
C5 90
1
2
Deciphered Date
2
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C3 12
1
1
2
2
2
1
+1.5V
12
R3 41
1K_ 0402_1%
1K_ 0402_1%
For Arr anale only +VREF_DQ_DIMMB
supply f rom a exte rnal 1 .5V v oltage divide
circuit.
07/ 17/2009
0.1U _0402 _10V6K
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 04
C3 07
1
1
2
2
0.1U _0402 _10V6K
C3 05
1
2
C3 06
1
2
Title
Size D ocum ent N umber Re v
Da te: She et
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
R3 40
+VR EF_D Q_DIMM B
12
LA-5752P
1
0. 3
o f
11 5 1Th ursda y, O ctob er 29 , 2009
5
4
3
2
1
Reserve for Low Power CLK GEN.
RTM890N-632
SLG8LV597VTR
VDD _3V3_ 1V5+3V S_CK505
1 2
R2 780_0 603_5%
@
D D
+1.5V S
1 2
R2 690_0 603_5%
1 PCS CAP(0.1u) BY 1 INPUT PIN
VDD _3V3_ 1V5
0.1U _0402 _10V6K
10U_ 0805_ 10V4K
C3 36
1
1
2
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 66
C3 30
C3 34
1
1
2
2
CLK GEN TO PCH
1. CLK _DMI
2. CLK _BUF_B CLK
3. CLK _BUF_C KSSCD
4. CLK _BUF_D OT96
5. CLK _14M_PCH
C C
CLK GEN TO VGA
1. 27M _CLK
1. 27M _CLK_SS
+1.0 5VS_ CK505+1.0 5VS
1 2
R2 770_06 03_5%
CLK _BUF_ DOT96<14 >
CLK _BUF_ DOT96 #<14>
CL K_B UF_CK SSCD<14>
CL K_BU F_CK SSCD #<14>
CLK _DMI<14>
CLK _DMI#<14>
CLK _BUF_ DOT96
CLK _BUF_ DOT 96#
CL K_B UF_CK SSCD
CL K_B UF_CK SSCD #
CLK _DMI
CLK _DMI#
+3V S_CK505
R3 24 0_040 2_5%
R3 08
R3 07 0_040 2_5%
R3 06
R2 99
1 PCS CAP(0.1u) BY 1 INPUT PIN
10U_ 0805_ 10V4K
10U_ 0805_ 10V4K
C3 33
1
1
2
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C3 31
C3 43
C3 32
1
1
2
2
0.1U _0402 _10V6K
C3 35
1
2
R3 18 0_0 402_5%
1 2
1 2
R3 19 0_0 402_5%
CLOSE U27
1 2
1 2
1 2
1 2
1 2
CLK _48M_ CR
0_04 02_5%
0_04 02_5%
10K _0402_5%
L_CL K_BU F_DO T96
L_CL K_BU F_DO T96#
L_CL K_DM I
L_CL K_DM I#
CPU _STOP #
unstuff 09.09.08
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_SRC
+3V S_CK505 +1 .05VS _CK505+3V S_CK505 +1 .05VS _CK505
32
SCL
31
SDA
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD _3V3_ 1V5
CLK _48M_ CR_R
CL K_B UF_C KSSC D_R
CL K_B UF_CK SSCD #_R
U1 4
1
VDD_USB_48
2
VSS_48M
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
USB_48
9
VSS_27M
10
SATA
11
SATA#
12
VSS_SRC
13
SRC_1
14
SRC_1#
15
VDD_SRC_IO
16
CPU_STOP#
33
TGND
SLG 8SP5 87VTR_QFN 32_5X5
REF_0/CPU_SEL
CKPWRGD/PD#
VDD_CPU_IO
RTM890N-631-GRT QFN 32P CLK GEN (SA00003HQ00)
ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)
1 2
@
CLK _48M_ CR_R
R3 2233_ 0402_1%
12
R3 230_0 402_5%
@
PIN8 IS GND FOR ICS3197
SMB _CLK_S 3
SMB _DATA_S3
RE F_0/ CPU_S EL
CLK _XTAL_IN
CLK_ XTAL_OUT
CK _P WRGD
VDD _3V3_ 1V5
R_ CLK_ BUF_B CLK CLK _BUF_ BCLK
R_CL K_BU F_BC LK# CLK _BUF _BCL K#
VDD _3V3_ 1V5
R2 75 0_04 02_5%
1 2
1 2
R2 76 0_04 02_5%
R3 15
12
33_0 402_1%
CK _P WRGD
CLK _14M_ PCH
2N70 02_SOT2 3-3
SMB _CLK_S3 <10, 11,14, 28>
SMB_D ATA_S3 <10,1 1,14,2 8>
CLK _14M_ PCH <1 4>
CLK _BUF_ BCLK <14>
CLK _BUF_ BCLK # <14>
R2 98
1 2
10K _0402_5%
13
D
2
G
Q25
S
+3V S_CK505
CLK _EN# < 48>
PIN8 IS 48MHz FOR ICS3199
B B
A A
+3VS
1 2
R2 790_06 03_5%
+3V S_CK505
1 PCS CAP(0.1u) BY 1 INPUT PIN
0.1U _0402 _10V6K
C3 42
C3 50
1
1
2
2
100MHz 100MHz
0.1U _0402 _10V6K
C3 67
CPU_1PIN 30 CP U_0
133MHz
0.1U _0402 _10V6K
10U_ 0805_10 V4K
C3 44
1
1
2
2
(De faul t)
0 133M Hz
1
+1.0 5VS
1 2
R3 17 10K _0402 _5%@
1 2
R3 16 10K _0402 _5%
C3 65
CLK _14M_ PCH
12
22P _0402_50 V8J
C3 64
EMI Ca pacitor
RE F_0/ CPU_S EL
RE F_0/ CPU_S EL
12
10P _0402_5 0V8J@
C3 48
22P _0402_5 0V8J
CLK_ XTAL_OUT
CLK _XTAL_IN
Y1
12
2
2
14.3 1818M HZ_16P F_DSX840G A
1
C3 49
22P _0402_5 0V8J
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
2
Title
Size D ocum ent N umber R ev
Da te: She et
Compal Electronics, Inc.
CLOCK GENERATOR
LA-5752P
1
o f
12 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
PCH _RTCX 1
1 2
R1 54 10M _0402_5%
1
D D
+R TCVC C
R1 44
1 2
100_ 0603_1%
2
C4 41
0.1U _0402 _16V4Z
1
C C
+RTCBA TT
12
SHO RT P ADS
+R TCVC C
R4 21
R4 20
CL RP1
H In te gr：ated VRM e nable
*
L In te gra：ted V RM di sable
+3VS
1 2
1 2
R4 52 1K _0402_ 5%@
1
2
15P _0402_5 0V8J
1M_ 0402_5%
330K _0402_5 %
1 2
C1 71
2
S M_INT RUDE R#
PCH _INTV RME N
P CH_SP KR
OSC4OSC
NC3NC
PCH _RTCX 2
X1
32.7 68KH Z_12. 5PF_ 9H032004 13
1
C1 83
15P _0402_5 0V8J
2
@
HD A_BI TCLK_ CODE C<33>
HD A_S YNC _CO DEC< 33>
@
GPI O33 = GP O , i nte rna l pu ll-up ,shou ld no t be pulle d low
fla sh ME co re of st rap pin p ull d own
(2009, 07,07)
+3V ALW+3V ALW +3V ALW + 3VALW +3VS
12
@
R7 4
200_ 0402_5%
12
B B
@
R1 17
100_ 0402_1%
A A
PCH _JT AG_TD I
PCH _JT AG_TC K
PCH _JT AG_RS T#
Ref DesPCH Pin
R59 1
R59 0
R58 4
R58 3
R58 6
R58 0
R59 5
R59 4
12
@
R7 2
200_ 0402_5%
PCH _JTAG_T MS PCH _JTA G_RST#PCH _JTA G_TDO PCH _JTA G_TDI
12
@
R1 15
100_ 0402_1%
PCH JTAG
Pre -Pr oduc tion
ES1 MPES 2
No Inst all
No Inst all
200 ohm
100 ohm 100 ohm
200 ohm
100 ohm 100 ohm
51o hm
20K ohm 20K ohm
10K ohm 10K ohm
5
12
@
R7 3
200_ 0402_5%
12
@
R1 16
100_ 0402_1%
PCH JTAG
Pro duct ion
*
200 ohm
No Inst all
100 ohm
No Inst allPCH _JT AG_TD O
200 ohm
No Inst all
No Inst allPCH _JT AG_TM S
200 ohm
No Inst allR58 7
No Inst all
51o hm 51 ohm
No Inst all
No Inst all
@
R7 5
20K _0402_5%
1 2
12
@
R1 18
10K _0402_5%
PCH _JTA G_TCK
FOR INTEL DP DG REV 1.6 (M AY 2009)
4
+R TCVC C
1U_0 603_1 0V4Z
1 2
R4 19 20K _0402_1%
1 2
R4 22 20K _0402_1%
C6 471 2P_04 02_50V8J
1 2
1 2
C6 481 2P_04 02_50V8J
R1 14 51_0 402_5%
1U_0 603_1 0V4Z
PC H_SP KR< 33>
HD A_RS T_CO DEC#<33>
HD A_S DIN1<33>
HD A_S DOUT_ CODE C<33>
ME_ FLASH<34>
1 2
4
C1 84
C2 02
+3V ALW
SPI _CLK _PCH
1
12
CL RP3
SHO RT P ADS
2
1
12
CL RP2
SHO RT P ADS
2
R1 68 33_0 402_5%
1 2
R1 67 33_0 402_5%
1 2
R1 69 33_0 402_5%
1 2
R1 66 33_0 402_5%
1 2
R4 09 1K_0 402_5%@
1 2
R4 25 0_040 2_5%
1 2
R4 24 10K _0402_5%
1 2
@
GPI O13 = GPI, 3.3V, SUS
R9 9
1 2
0_04 02_5%
(2009, 05,04)
PCH _RTCX 1
PCH _RTCX 2
PCH _RTCR ST#
PCH _SRT CRST#
S M_INT RUDE R#
PCH _INTV RME N
BIT CLK
HD A_S YNC
P CH_SP KR
HDA _RST #
HD A_S DIN0
HD A_S DIN1
HD A_SD OUT
GPI O13
PCH _JTA G_TCK
PCH _JTAG_T MS
PCH _JTA G_TDI
PCH _JTA G_TDO
S PI_CL K_PC H_R
SPI _SB _CS0#
SPI _SI
SPI _SO _R
3
U7 A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IBE XPEAK- M_FCBGA1 071
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
RT CIH DA
SPI JTAG
FWH4 / LFRAME#
LDRQ1# / GPIO23
LP C
SA TA
SATA0GP / GPIO21
SATA1GP / GPIO19
D33
FWH0 / LAD0
B33
FWH1 / LAD1
C32
FWH2 / LAD2
A32
FWH3 / LAD3
C34
A34
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
2008/10/31 2009/10/31
GPI O23
F34
SE RIR Q
AB9
AK7
AK6
SAT A_ITX_ C_DRX_N0
AK11
SAT A_ITX_C_D RX_P0
AK9
AH6
AH5
SAT A_ITX_ C_DRX_N1
AH9
SAT A_ITX_C_D RX_P1
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
SAT A_DTX_C _IRX_N4
AD9
SAT A_DTX_C_I RX_P4
AD8
SAT A_ITX_ C_DRX_N4
AD6
SAT A_ITX_C_D RX_P4
AD5
AD3
AD1
AB3
AB1
AF16
SAT AICOMPPCH _JTA G_RST#
AF15
T3
Y9
V1
R4 53 10K _0402_5%
GPI O21
GPI O19
SPI _SB _CS0#
SPI _SO _R SPI _SO_L
Compal Secret Data
2
LPC _AD0 < 28,34>
LPC _AD1 < 28,34>
LPC _AD2 < 28,34>
LPC _AD3 < 28,34>
LPC _FRAM E# <28 ,34>
T7 PA D
GPI O23 = NA TIVE, 3.3V, CORE
1 2
37.4 _0402_1 %
1 2
SE RIRQ <34>
R5 00
HD D_L ED# <3 6>
GPI O21 = GPI ,3.3V ,CORE
GPI O19 = GPI ,3.3V ,CORE
+3VS
R6 2
1 2
R1 02
1 2
R1 03
15_0 402_5%
1 2
15_0 402_5%
Deciphered Date
2
+1.0 5VS
+3VS
R1 01
12
R4 7910K_ 0402_5%
12
12
12
12
12
12
SPI _WP#
3.3K _0402 _5%
SPI _HOL D#
3.3K _0402 _5%
12
SPI _WP#
+3VS
C1 400.01 U_040 2_16V7K
C1 410.01 U_040 2_16V7K
C4 270.01 U_040 2_16V7K
C4 280.01 U_040 2_16V7K
SAT A_DTX_C _IRX_N0
SAT A_DTX_C_I RX_P0
SATA_ ITX_DRX_N 0
SATA_ ITX_DRX_P0
SAT A_DTX_C _IRX_N1
SAT A_DTX_C_I RX_P1
SATA_ ITX_DRX_N 1
SATA_ ITX_DRX_P1
SAT A_IT X_DRX_ N4_CONN
C1 420.01 U_040 2_16V7K ESATA @
SAT A_I TX_DRX_P4 _CONN
C1 430.01 U_040 2_16V7K ESATA @
R4 47
10K _0402_5%
GPI O21
GPI O19
1 2
1 2
SAT A_DTX_C_ IRX_N0 <3 2>
SATA _DTX_C_IRX _P0 <32>
SATA_ ITX_DRX_N 0 <32>
SATA_ ITX_DRX_P0 <32>
SAT A_DTX_C_ IRX_N1 <3 2>
SATA _DTX_C_IRX _P1 <32>
SATA_ ITX_DRX_N 1 <32>
SATA_ ITX_DRX_P1 <32>
R4 82
10K _0402_5%
4M SPI ROM FOR HM55
(ME code & BIOS code)
SA00003K800
+3VS
U3
1
CS#
VCC
2
SO
HOLD#
3
WP#
SCLK
4
GND
SI
S I C FL 16M EN25 F16-1 00HIP SOP 8P
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
1 2
8
SPI _HOL D#
7
SPI _CLK _PCH
6
SPI _SI
5
Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA
1
SAT A_DTX_C_ IRX_N4 < 37>
SATA _DTX_C_IRX _P4 <3 7>
SAT A_IT X_DRX_ N4_CONN < 37>
SAT A_IT X_DRX_P4_C ONN <37>
C4 60
0.1U _0402 _16V4Z
LA-5752P
1
HDD
ODD
E-SATA
SPI _CLK _PCH
R1 00
33_0 402_5%
@
22P _0402_5 0V8J
@
13 5 1Thu rsda y, O ctobe r 29, 2009
12
C1 38
0. 3
5
PCIE PORT LIST
DEVICEPORT
1
X
WLAN
2
LAN
3
4
CL K_P CIE_C ARD_ PCH#<28 >
CL K_P CIE_ CARD_ PCH<2 8>
5
6
7
8
PCI E_PRX_D TX_N2< 28>
PCIE _PRX_DTX _P2<28>
PCI E_PT X_C_DRX_N 2<28>
PCI E_PTX _C_DRX_P2< 28>
PCI E_PRX_D TX_N3< 29>
PCIE _PRX_DTX _P3<29>
PCI E_PT X_C_DRX_N 3<29>
PCI E_PTX _C_DRX_P3< 29>
PCI E_PRX_D TX_N4< 28>
PCIE _PRX_DTX _P4<28>
PCI E_PT X_C_DRX_N 4<28>
PCI E_PTX _C_DRX_P4< 28>
PCI E_PRX_D TX_N5< 28>
PCIE _PRX_DTX _P5<28>
PCI E_PT X_C_DRX_N 5<28>
PCI E_PTX _C_DRX_P5< 28>
CLK _PCIE _WLA N1#<28>
CL K_PCI E_WL AN1<28>
CLK _PCIE _EXP _PCH#<28>
CLK _PCIE _EXP _PCH<28>
WLA N_CLK REQ1 #< 28>
CLK _PCIE _LAN #<29>
CLK _PCIE _LAN<29>
CLK REQ_ LAN#< 29>
PCI ECLK REQ3 #<28>
CLK REQ_EXP #< 28>
3G
NEW CARD
X
X
X
C2 30 0.1U _0402 _10V6K
C2 29 0.1U _0402 _10V6K
C2 23 0.1U _0402 _10V6K
C2 22 0.1U _0402 _10V6K
C2 31 0.1U _0402 _10V6K3G@
C2 32 0.1U _0402 _10V6K3G@
C2 20 0.1U _0402 _10V6K
C2 21 0.1U _0402 _10V6K
R4 31 10K _0402_5%
+3V ALW
R1 96 0_04 02_5%
R1 97 0_04 02_5%
R4 54 10K _0402_5%
+3VS
R2 20 0_04 02_5%
R2 21 0_04 02_5%
R1 13 10K _0402_5%
+3VS
R2 23 0_04 02_5%3G @
R2 22 0_04 02_5%3G @
R1 20 10K _0402_5%
+3V ALW
R2 24 0_04 02_5%
R2 25 0_04 02_5%
R4 35 10K _0402_5%
+3V ALW
R4 34 10K _0402_5%
+3V ALW
R4 57 10K _0402_5%
+3V ALW
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PCI E_PRX_ DTX_N2
PCI E_PRX_DT X_P2
PCI E_PTX _DRX_N2
PCI E_PTX_DR X_P2
PCI E_PRX_ DTX_N3
PCI E_PRX_DT X_P3
PCI E_PTX _DRX_N3
PCI E_PTX_DR X_P3
PCI E_PRX_ DTX_N4
PCI E_PRX_DT X_P4
PCI E_PTX _DRX_N4
PCI E_PTX_DR X_P4
PCI E_PRX_ DTX_N5
PCI E_PRX_DT X_P5
PCI E_PTX _DRX_N5
PCI E_PTX_DR X_P5
GPI O73 = NAT IVE,3 .3V,S US
CL K_PC IE_W LAN1# _R
CL K_PC IE_W LAN1_ R
GPI O18 = NA TIVE, 3.3V, CORE
CLK _PCIE _LAN #_R
CLK _PCIE _LAN _R
GPI O20 = NA TIVE, 3.3V, CORE
CL K_P CIE_ CARD _PCH #_R
CL K_P CIE _CAR D_PCH _R
GPI O25 = NAT IVE,3 .3V,S US
CLK _PCIE _EX P_PCH#_ R
CLK REQ_EXP #
GPI O26 = NAT IVE,3 .3V,S US
GPI O44 = NAT IVE,3 .3V,S US
GPI O56 = NAT IVE,3 .3V,S US
D D
WLAN
LAN
3G
C C
EXP
WLAN
B B
LAN
3G
EXP
A A
4
U7 B
BG30
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLKRQ# / GPIO56
IBE XPEAK- M_FCBGA1 071
WLAN
LAN
MINI1
NEW CARD
SMBus
PCI-E*
Link
Con trol ler
PEG_A_CLKRQ# / GPIO47
PEG
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
From C LK BUF FER
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
Clock Flex
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
3
R4 07
0_0402_5%
LID_ OUT#
B9
H14
C8
J14
C6
G8
M14
E10
G12
T13
T11
T9
H1
AD43
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
J42
AH51
AH53
AF38
T45
P43
T42
N50
GPI O11 = NAT IVE,3 .3V,S US
SM BCLK
SMBDA TA
GPI O60 = NAT IVE,3 .3V,S US
GPI O60
SML 0CLK
SML 0DATA
GPI O74 = NAT IVE,3 .3V,S US
GPI O74
SML 1CLK
R7 9
SML 1DATA
R8 0
PEG _CLK REQ#
PEG _CLK REQ#
GPI O47 = 10 Kohm PULL DOWN
CLK OUT_D P_N
CLK OUT_D P_P
CLK _14M_ PCH
CL K_PC I_FB
XTA L25_IN
XTAL25 _OUTCLK _PCIE _EX P_PCH_R
CL K_P CI_DB _R
1 2
CLK _PCIE _VG A#_R
CLK _PCIE _VG A_R
CLK _EXP#_R
CLK _EXP_R
R4 91 90.9_ 0402_1%
R5 24 0_04 02_5%
R5 25 0_04 02_5%
R1 05 0_04 02_5%
R1 06 0_04 02_5%
1 2
R1 98
1 2
EC_ LID_O UT# <34 >
0_0402_5%
0_0402_5%
DTS , read f rom EC
PEG _CLK REQ# <19 >
R4 1210 K_0402_ 5%
1 2
1 2
1 2
1 2
CLK _DMI# <12>
CL K_DM I < 12>
CLK _BUF_ BCLK # <12>
CLK _BUF_ BCLK <12>
CLK _BUF_ DOT96 # <12>
CLK _BUF_ DOT96 <12>
CL K_BU F_CK SSCD # < 12>
CL K_B UF_CK SSCD <12>
CLK _14M_ PCH <1 2>
CL K_PCI _FB < 16>
+1.0 5VS
22_0 402_5%
@
EC_ SMB_ CK2
EC_ SMB_ DA2
CL K_PCI _DB < 28>
SMB CLK
SMBDA TA
CLK _PCIE _VGA #
CLK _PCIE _VGA
SMB _CLK_S 3
SMB _DATA_S3
EC_ SMB_CK 2 <34>
EC_ SMB_DA 2 <34>
CLK_E XP# <5>
CLK_E XP <5>
2
1 2
R1 21 10K _0402_5%
1 2
R4 06 10K _0402_5%
Q8A
2N70 02DW -T/R7 _SOT363-6
6 1
2N70 02DW -T/R7 _SOT363-6
3
SMB _CLK_S 3
2
+3VS
Q8B
SMB _DATA_S3
4
5
EC_THERMAL
CLK _PCIE _VGA# <19>
CLK _PCIE _VGA <19>
+3VS
Q7A
6 1
5
2N70 02DW -T/R7 _SOT363-6
Q7B
3
2N70 02DW -T/R7 _SOT363-6
4
EC_ SMB_ DA2
EC_ SMB_ CK2
EMI REQUEST 0303
CLK _14M_ PCHCL K_PC I_FB
R2 09
33_0 402_5%
@
1 2
C2 63
22P _0402_5 0V8J
@
1 2
SM BCLK
+3VS +3V ALW
SMBDA TA
SML 0CLK
SML 0DATA
SML 1CLK
SML 1DATA
GPI O74
LID_ OUT#
GPI O60
SMB _CLK_S3 <10, 11,12, 28>
1 2
R1 23 2.2K _0402 _5%
1 2
R7 8 2 .2K_ 0402_5%
1 2
R1 48 2.2K _0402 _5%
1 2
R1 47 2.2K _0402 _5%
1 2
R4 04 2.2K _0402 _5%
1 2
R4 03 2.2K _0402 _5%
1 2
R3 99 10K _0402_5%
1 2
R1 45 10K _0402_5%
1 2
R4 00 10K _0402_5%
DDR3*2 AND CLK GEN
SMB_ DATA_S3 <10, 11,12,2 8>
+3VS
2
R8 1 0_04 02_5%
1 2
R8 3 0_04 02_5%
1 2
R4 13
33_0 402_5%
@
C4 39
22P _0402_50 V8J
@
+3VS
R1 24
2.2K _0402 _5%
SMB _EC_ DA2_R
@
SMB _EC_ CK2_R
@
25MHz crysta l not used, XTAL25_IN
need t o GND.
(check list R ev1.6)
XTA L25_IN
XTAL25 _OUT
1
R1 22
SM BCLK
SMBDA TA SMB _DATA_S3
R8 2
2.2K _0402 _5%
SMB _EC_ DA2_REC_ SMB_ DA2
SMB _EC_ CK2_REC_ SMB_ CK2
0_04 02_5%
@
1 2
@
1 2
0_04 02_5%
R1 19
Nvidia
thermal
sensor
1 2
R5 98 1M_ 0402_5%@
Y4
@
1 2
25M HZ_20 P_1BG 25000CK1A
18P _0402_50 V8J
C6 30
1
@
2
SMB _EC_ DA2_R <19,31>
SMB _EC_ CK2_R <19,31>
SMB _CLK_S 3
0_04 02_5%
1
2
C6 31
C631 Resi sto r P ull down
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK
LA-5752P
1
14 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
4
3
2
1
D D
DMI _CTX_PRX _N0<6>
DMI _CTX_PRX _N1<6>
DMI _CTX_PRX _N2<6>
DMI _CTX_PRX _N3<6>
DMI_CT X_PRX_P0<6>
DMI_CT X_PRX_P1<6>
DMI_CT X_PRX_P2<6>
DMI_CT X_PRX_P3<6>
DMI _CRX_PTX _N0<6>
DMI _CRX_PTX _N1<6>
DMI _CRX_PTX _N2<6>
DMI _CRX_PTX _N3<6>
DMI_CRX _PTX_P0<6>
DMI_CRX _PTX_P1<6>
DMI_CRX _PTX_P2<6>
DMI_CRX _PTX_P3<6>
+1.0 5VS
1 2
R5 20 49.9 _0402 _1%
4mil w idth a nd place
within 500mi l of t he PCH
C C
Che ckl is t0.8 M EPWRO K
can be co nnect to
PWR OK if iAMT disa ble
(2009, 05,04)
SU S_PW R_DN _ACK<34>
+3V ALW
R4 50 10K _0402_5%
VGATE
IC H_PO K
+3V ALW
1
A
2
B
+3VS
Reserv ed
(2009, 09,08)
B B
A A
：
R3 96 100K _0402_1%
VGATE<48>
IC H_PO K< 34>
+3V ALW
1 2
AC_ PRES ENT<34 >
MC7 4VHC1 G08D FT2G SC70 5P
3
@
G
Y
P
U2 8
5
12
R3 98 0_04 02_5%@
R3 97 0_04 02_5%
PM_ DRAM _PWR GD<5>
R4 01
R4 37 10K _0402_5%
1 2
1 2
R5 99 0_ 0402_5%@
PBT N_OUT#<34>
GPI O31 = GPI, 3.3V, SUS
R7 7 8.2K_0 402_1%
1 2
GPI O30 = GPI, 3.3V, SUS
R1 65 10K _0402_5%
1 2
S YS_P WROK
4
1 2
1 2
10K _0402_5%
R4 51 0_ 0402_5%
DMI _CTX_PR X_N0
DMI _CTX_PR X_N1
DMI _CTX_PR X_N2
DMI _CTX_PR X_N3
DMI_CT X_PRX_P0
DMI_CT X_PRX_P1
DMI_CT X_PRX_P2
DMI_CT X_PRX_P3
DMI _CRX_PT X_N0
DMI _CRX_PT X_N1
DMI _CRX_PT X_N2
DMI _CRX_PT X_N3
DMI_CRX _PTX_P0
DMI_CRX _PTX_P1
DMI_CRX _PTX_P2
DMI_CRX _PTX_P3
DMI _IRCO MP
+3VS
R4 48
10K _0402_5%
SYS _RS T#
1 2
S YS_P WROK
R4 55
0_04 02_5%
1 2
R1 46 10K_ 0402_5%
1 2
PM_ DRAM _PW RGD
PM_ RSMRST#
12
SU S_P WR_D N_AC K_R
PBT N_OUT#
AC_ PRES ENT_R
1 2
GPI O72
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IBE XPEAK- M_FCBGA1 071
EC_ RSMRS T#<34>
U7C
System Power Manag ement
RSMRST circuit
BAV 99DW- 7_SOT363
5
D8 B
R1 75
1 2
2.2K _0402 _5%
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_LAN# / GPIO29
@
0_04 02_5%
1 2
E
B
4
2
3
6
BA18
FDI_RXN0
BH17
FDI_RXN1
BD16
FDI_RXN2
BJ16
FDI_RXN3
BA16
FDI_RXN4
BE14
FDI_RXN5
BA14
FDI_RXN6
BC12
FDI_RXN7
BB18
FDI_RXP0
BF17
FDI_RXP1
BC16
FDI_RXP2
BG16
FDI_RXP3
AW16
FDI_RXP4
BD14
FDI_RXP5
BB14
FDI_RXP6
BD12
FDI_RXP7
BJ14
FDI_INT
BF13
FDI_FSYNC0
BH13
FDI_FSYNC1
BJ12
FDI_LSYNC0
BG14
FDI_LSYNC1
J12
WAKE#
Y1
P8
F3
E4
H7
SLP_S4#
P12
SLP_S3#
K8
SLP_M#
N2
TP23
BJ10
PMSYNCH
GPI O29 = GPO, 3.3V, SUS
F6
R4 02
C
PM_ RSMRST#
123
Q14
MMBT 3906_SOT23-3
1 2
R1 76 4. 7K_0 402_5%
1
D8 A
BAV 99DW- 7_SOT363
FDI _CTX_ PRX_N0
FDI _CTX_ PRX_N1
FDI _CTX_ PRX_N2
FDI _CTX_ PRX_N3
FDI _CTX_ PRX_N4
FDI _CTX_ PRX_N5
FDI _CTX_ PRX_N6
FDI _CTX_ PRX_N7
FDI _CTX_PR X_P0
FDI _CTX_PR X_P1
FDI _CTX_PR X_P2
FDI _CTX_PR X_P3
FDI _CTX_PR X_P4
FDI _CTX_PR X_P5
FDI _CTX_PR X_P6
FDI _CTX_PR X_P7
FD I_I NT
FD I_F SYN C0
FD I_F SYN C1
FD I_L SY NC0
FD I_L SY NC1
10K _0402_5%
1 2
PCI E_WA KE#
GPI O32 = GPO, 3.3V, CORE
GPI O61
GPI O62
R4 36
PCI E_WA KE# <2 8>
1 2
R1 08 10K _0402_5%
GPI O61 = NAT IVE,3 .3V,S US
GPI O62 = NAT IVE,3 .3V,S US
SLP _S5# <34 >
SLP _S4# <34 >
SLP _S3# <34 >
Can be l eft NC w hen I AMT i s
not su pp ort on t he pl atfro m
H_ PM_ SYNC < 5>
If not u sing inte grate d
LAN ,si gn al may be le ft as NC.
+3V ALW
FDI _CTX_ PRX_N0 <6>
FDI _CTX_ PRX_N1 <6>
FDI _CTX_ PRX_N2 <6>
FDI _CTX_ PRX_N3 <6>
FDI _CTX_ PRX_N4 <6>
FDI _CTX_ PRX_N5 <6>
FDI _CTX_ PRX_N6 <6>
FDI _CTX_ PRX_N7 <6>
FDI _CTX_PRX _P0 <6>
FDI _CTX_PRX _P1 <6>
FDI _CTX_PRX _P2 <6>
FDI _CTX_PRX _P3 <6>
FDI _CTX_PRX _P4 <6>
FDI _CTX_PRX _P5 <6>
FDI _CTX_PRX _P6 <6>
FDI _CTX_PRX _P7 <6>
FD I_I NT <6>
FD I_F SYN C0 <6>
FD I_F SYN C1 <6>
FD I_L SYN C0 <6>
FD I_L SYN C1 <6>
+3V ALW
+3VS
SLP _S3#
SLP _S4#
SLP _S5#
+3VS
1 2
R4 18 10K _0402_5%@
1 2
R4 17 10K _0402_5%@
1 2
R4 16 10K _0402_5%@
PC H_EN BKL<27>
PC H_E NVDD<27>
ED ID_C LK<2 7>
EDI D_DAT A< 27>
PCH _PWM< 27>
12
R5 02
2.37 K_040 2_1%
CR T_D DC_C LK<2 6>
CR T_DDC _DAT A<26 >
CR T_H SYN C<26>
CR T_V SYN C<26 >
LVD S_AC LK#<27>
LVD S_AC LK<27>
LVD S_A0#<27>
LVD S_A1#<27>
LVD S_A2#<27>
LVD S_A0<27>
LVD S_A1<27>
LVD S_A2<27>
DA C_B LU<26>
DA C_G RN<2 6>
DA C_R ED<26>
PCH _ENB KL
PC H_E NVD D
ED ID_ CLK
EDI D_DAT A
R4 97
1 2
10K _0402_5%
1 2
R4 96 10K _0402_5%
T10 PA D
DA C_B LU
DA C_G RN
DA C_R ED
CR T_I REF
1K_ 0402_5%
R4 92
12
U7D
T48
L_BKLTEN
T47
L_VDD_EN
Y48
L_BKLTCTL
AB48
L_DDC_CLK
Y45
L_DDC_DATA
AB46
L_CTRL_CLK
V48
L_CTRL_DATA
AP39
LVD_IBG
AP41
LVD_VBG
AT43
LVD_VREFH
AT42
LVD_VREFL
AV53
LVDSA_CLK#
AV51
LVDSA_CLK
BB47
LVDSA_DATA#0
BA52
LVDSA_DATA#1
AY48
LVDSA_DATA#2
AV47
LVDSA_DATA#3
BB48
LVDSA_DATA0
BA50
LVDSA_DATA1
AY49
LVDSA_DATA2
AV48
LVDSA_DATA3
AP48
LVDSB_CLK#
AP47
LVDSB_CLK
AY53
LVDSB_DATA#0
AT49
LVDSB_DATA#1
AU52
LVDSB_DATA#2
AT53
LVDSB_DATA#3
AY51
LVDSB_DATA0
AT48
LVDSB_DATA1
AU50
LVDSB_DATA2
AT51
LVDSB_DATA3
AA52
CRT_BLUE
AB53
CRT_GREEN
AD53
CRT_RED
V51
CRT_DDC_CLK
V53
CRT_DDC_DATA
Y53
CRT_HSYNC
Y51
CRT_VSYNC
AD48
DAC_IREF
AB51
CRT_IRTN
IBE XPEAK- M_FCBGA 1071
update R492 tolera nce for
DAC_CR T from 0.5% to 5%
(check list 2 .0)
DA C_B LU
DA C_G RN
DA C_R ED
ED ID_ CLK
EDI D_DAT A
CRT OUT
R4 93 150_0 402_1%UM A@
1 2
R4 95 150_0 402_1%UM A@
1 2
R4 94 150_0 402_1%UM A@
1 2
R4 58 2.2K _0402 _5%U MA@
R4 98 2.2K _0402 _5%U MA@
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ46
BG46
BJ48
BG48
BF45
BH45
T51
T53
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
2.2K _0402_5 %
AW38
BA38
HD MIC LK_NB
Y49
HDM IDAT _NB
AB49
BE44
BD44
AV40
TMD S_B_ DATA2#_P CH
BE40
TMD S_B_ DATA2_P CH
BD40
TMD S_B_ DATA1#_P CH
BF41
TMD S_B_ DATA1_P CH
BH41
TMD S_B_ DATA0#_P CH
BD38
TMD S_B_ DATA0_P CH
BC38
TMD S_B_ CLK#_P CH
BB36
TMD S_B_ CLK_PCH
BA36
U50
U52
BC46
BD46
AT38
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R5 10 10K _0402_5%
12
+3VS
12
12
UMA @
UMA @
R5 04
R5 03
2.2K _0402_5 %
C6 38 0.1U _0402 _10V6KUMA _HDM I@
C6 39 0.1U _0402 _10V6KUMA _HDM I@
C6 40 0.1U _0402 _10V6KUMA _HDM I@
C6 41 0.1U _0402 _10V6KUMA _HDM I@
C6 42 0.1U _0402 _10V6KUMA _HDM I@
C6 43 0.1U _0402 _10V6KUMA _HDM I@
C6 44 0.1U _0402 _10V6KUMA _HDM I@
C6 45 0.1U _0402 _10V6KUMA _HDM I@
HD MICL K_NB <25>
HDM IDAT _NB <25 >
TMD S_B_HP D# <25>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
TMDS _B_DATA 2# <25>
TMDS _B_DATA 2 <25>
TMDS _B_DATA 1# <25>
TMDS _B_DATA 1 <25>
TMDS _B_DATA 0# <25>
TMDS _B_DATA 0 <25>
TMD S_B_CLK # <25>
TMD S_B_CLK <25>
HDMI
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Disp lay In terface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(3/6)-DMI/GPIO/LVDS
LA-5752P
1
15 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
D D
PCI _PIRQ A#
PCI _PIRQ B#
GPI O18 = NAT IVE,5 V,COR E
GPI O52 = NAT IVE,5 V,COR E
GPI O54 = NAT IVE,5 V,COR E
C C
GPI O2 = G PI,5V ,CORE
GPI O3 = G PI,5V ,CORE
GPI O4 = G PI,5V ,CORE
GPI O5 = G PI,5V ,CORE
PCI _RST#<2 8,34>
R4 08 100 K_0402_1 %
12
GNT 2
Def aul t- Inte rnal pull up
Low =Co nf igu res D MI fo r ESI
com pat ib le o perat ion(f or
ser ver s only. Not f or
mob ile /des ktops )
PCI _PME#<34>
B B
CL K_PCI _LPC<34 >
CL K_PCI _FB<1 4>
PCI _REQ 0#
PC I_P IRQF#
PCI _REQ 3#
PCI _REQ 1#
PCI _FRA ME#
PC I_ TRDY#
PC I_P IRQH #
PCI _STOP#
PC I_I RD Y#
PC I_P IRQD #
PCI _REQ 2#
A A
PCI _GNT 3#
A16 sw ap ove ride S trap/T op-Block
Swap O verrid e jumper
PCI_GN T3#
R1 99 22_0 402_5%
1 2
1 2
R2 11 22_0 402_5%
RP 5
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
RP 7
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
RP 4
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_ 5%
R2 00 1K_ 0402_5%@
1 2
Low=A1 6 swap
overri de/Top -Block
Swap O verrid e enabled
High=D efault
PC I_P IRQC #
PC I_P IRQD #
PCI _REQ 0#
PCI _REQ 1#
PCI _REQ 2#
PCI _REQ 3#
PCI _GNT 0#
PCI _GNT 1#
PCI _GNT 2#
PCI _GNT 3#
PCI _PIRQ E#
PC I_P IRQF#
P CI_PI RQG#
PC I_P IRQH #
PC I_S ERR#
PC I_P ERR#
PC I_I RD Y#
*
PCI _DEV SEL#
PCI _FRA ME#
PCI _LOCK #
PCI _STOP#
PC I_ TRDY#
PLT_ RST#
CL K_P CI_LP C_R
CL K_P CI_FB _R
+3VS +3V S
*
5
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
J50
G42
H47
G34
G38
H51
B37
A44
F51
A46
B45
M53
F48
K45
F36
H53
B41
K53
A36
A48
K6
E44
E50
A42
H44
F46
C46
D49
D41
C48
M7
D5
N52
P53
P46
P51
P48
P CI_PI RQG#
PC I_P IRQC #PCI _PIRQ B#
PCI _PIRQ A#
PCI _PIRQ E#
PCI _DEV SEL#
PCI _LOCK #
PC I_S ERR#
PC I_P ERR#
U7 E
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
STOP#
TRDY#
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
IBE XPEAK- M_FCBGA1 071
RP 3
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_5 %
RP 6
1 8
2 7
3 6
4 5
8.2K _080 4_8P4R_5 %
BUF _PLT_RS T#<5, 19,28 ,29>
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV RAM
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
PC I
USB
0.1U _0402 _16V4Z
C6 46
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_WR#0_RE#
NV_WR#1_RE#
NV_WE#_CK0
NV_WE#_CK1
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
4
AY9
NV_CE#0
BD1
NV_CE#1
AP15
NV_CE#2
BD8
NV_CE#3
AV9
NV_DQS0
BG8
NV_DQS1
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
NV_ ALE
BD3
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
PCI _GNT 0#
PCI _GNT 1#
NV _CLE
NV_ RCOM P
USB 20_N0
USB 20_P0
USB 20_N1
USB 20_P1
USB 20_N2
USB 20_P2
USB 20_N3
USB 20_P3
USB 20_N5
USB 20_P5
USB 20_N8
USB 20_P8
USB 20_N 10
USB 20_P10
USB 20_N 11
USB 20_P11
USB 20_N 13
USB 20_P13
USB RBIA S
USB _OC# 0
USB _OC# 1
USB _OC# 2
USB _OC# 3
USB _OC# 4
USB _OC# 5
USB _OC# 6
USB _OC# 7
R2 12 1K_ 0402_5%@
R2 10 1K_ 0402_5%@
Boot B IOS St rap
0
0
1
R1 49 0_04 02_5%
MC7 4VHC1 G08D FT2G SC70 5P
12
1
R1 55
100K _0402_5%
2
4
GPI O8
Wea k i nt ern al PU , don 't PD
Check list R ev0.8 sectio n1.23.2
If not imple mented , the
Braidw ood
interf ace si gnals can be
left a s No C onnect (NC).
GPI O15
*
L In te l M E： Cryp to Tr anspo rt
Lay er Se cur ity( TLS) chip er su ite
wit h n o conf ident ialit y
H In te l M E： Cryp to Tr anspo rt
Lay er Se cur ity( TLS) chip er su ite
wit h c on fiden tiali ty
it hav e wea k in terna l PU 20K
within 500mil
R1 04
1 2
32.4 _0402_1 %
@
USB 20_N0 <37>
USB 20_P0 < 37>
USB 20_N1 <37>
USB 20_P1 < 37>
USB 20_N2 <27>
USB 20_P2 < 27>
USB 20_N3 <37>
USB 20_P3 < 37>
USB 20_N5 <38>
USB 20_P5 < 38>
USB 20_N8 <28>
USB 20_P8 < 28>
USB 20_N1 0 <28>
USB 20_P10 <28>
USB 20_N1 1 <37>
USB 20_P11 <37>
USB 20_N1 3 <28>
USB 20_P13 <28>
1 2
R1 64 22.6 _0402 _1%
Within 500 mi ls mini mum spa cing to other
signal i s 15mil
1 2
1 2
PCI_GN T1#PCI_GNT0#
1 2
@
4
U5
0
1
0
11
Y
+3VS
Boot B IOS
Locati on
LPC
Reserv ed(NAND)
PCI
SPI
3
1
G
A
2
B
P
5
GPI O27
Def aul t D o ：not c onnec t(flo ating )
Hig h E nab le：s the inte rnal VccVR M
to hav e a c lean sup ply f or an alog
rai ls. n o n eed to us e on board
fil ter cir cuit.
GPI O1 = GPI,3 .3V,C ORE
GPI O6 = GPI,3 .3V,C ORE
GPI O7 = GPI,3 .3V,C ORE
GPI O8 = GPO,3 .3V,S US
GPI O12 = GPI, 3.3V, SUS
LEFT USB
LEFT USB (COMBO)
USB Cam era
RIGHT USB
che ckl is t 2 .0 u pdate 2009 .0916
CARD READER
WLAN
EXPRESS
Bluetooth
3G CARD
USB _OC# 0 < 37>
USB _OC# 1 < 37>
*
PLT_ RST#
3
+3VS
+3V ALW
+3V ALW
6
DRA MRST _CNTR L_PC H<5>
PCH _TEMP_A LERT#<34 >
SUS P#<28, 34,3 9,42,4 4,46> VGA _EN <45>
+3V ALW
+3V ALW
DI S@
R5 06 0_04 02_5%
1 2
GPI O0 = GPI,3 .3V,C ORE
EC _SCI #<34>
EC_ SMI#< 34>
CP USB#<28 >
GPIO27 if p ull down to turn off 1.8V VR
DRA MRST _CNTR L_PC H GPI O46
Int el An ti- Theft Tech onlog y
High=Enabled
NV_ALE
Low=Disable(floating)
NV_ ALE
R5 15 1K_ 0402_5%@
1 2
*
+1.8V S
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
Wea k i ntern al
PU, Do not pull low
NV _CLE
R9 8 1K_ 0402_5%@
1 2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3VS
Issued Date
2
GPIO
NCTF
+3V ALW
Deciphered Date
2
RSVD
+3VS
+3VS
+3V ALW
：
AB12
AB13
BE53
BF53
BH52
BH53
BJ49
BJ50
BJ52
BJ53
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
Y3
C38
D37
J32
F10
K9
T7
AA2
F38
Y7
H10
V13
M11
V6
AB7
V3
P3
H3
F1
AB6
AA4
F8
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BF1
BH1
BH2
BJ1
BJ2
BJ4
BJ5
D1
D2
D53
E1
E53
RP 1
8.2K _080 4_8P4R_5 %
RP 2
8.2K _080 4_8P4R_5 %
U7 F
BMBUSY# / GPIO0
TACH1 / GPIO1
TACH2 / GPIO6
TACH3 / GPIO7
GPIO8
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
STP_PCI# / GPIO34
SATACLKREQ# / GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
PCIECLKRQ6# / GPIO45
PCIECLKRQ7# / GPIO46
SDATAOUT1 / GPIO48
SATA5GP / GPIO49
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
IBE XPEAK- M_FCBGA1 071
Compal Secret Data
GPI O0
1 2
R4 8310K _0402_ 5%
GPI O1
1 2
R4 2810K _0402_ 5%
GPI O6
1 2
R4 2710K _0402_ 5%
EC _SC I#
EC_ SMI#
CP USB #
GPI O15
1 2
R4 331K _0402_5%
GPI O16
GPI O17
GPI O22
1 2
R4 4910K _0402_ 5%
@
12
R5 0710K _0402_ 5%
GPI O28
1 2
R4 4610K _0402_ 5%
GPI O34
12
R4 3210K _0402_ 5%
GPI O35
12
R4 5610K _0402_ 5%
GPI O36
GPI O37
1 2
R4 8110K _0402_ 5%
GPI O38
1 2
R1 0910K _0402_ 5%
GPI O39
1 2
R1 1210K _0402_ 5%
GPI O45
1 2
R7 610K_ 0402_5%
GPI O48
1 2
R4 8010K _0402_ 5%
PCH _TEMP _ALERT#
GPI O57
1 2
R4 15 10K _0402_5%
1 2
R6 09 10K _0402_5%
@
USB _OC# 0
USB _OC# 1
USB _OC# 2
USB _OC# 3
USB _OC# 4
USB _OC# 5
USB _OC# 6
USB _OC# 7
NV_ ALE
Ena ble I ntel Anti -Thef t
Tec hno lo gy 8 .2K P U to +3VS
Dis abl e Inte l Ant i-The ft
Tec hno lo gy：float ing(i ntern al PD )
NV_ CLE
DMI te rm inat ion v oltag e.
wea k i nt ern al PU , don 't PD
2008/08/12 2009/08/12
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
MISC
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
CPU
CLKOUT_PCIE7P
PROCPWRGD
THRMTRIP#
1 2
R4 29 10K _0402_5%
1 2
R4 85 10K _0402_5%
1 2
R4 84 10K _0402_5%
12
R1 07 10K _0402_5%
@
1 2
R4 26 10K _0402_5%
@
1 2
R4 14 10K _0402_5%
1
AH45
AH46
+3VS
A20GATE
PECI
RCIN#
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
AF48
AF47
U2
AM3
AM1
BG10
T1
BE10
BD10
BA22
TP1
AW22
TP2
BB22
TP3
AY45
TP4
AY46
TP5
AV43
TP6
AV45
TP7
AF13
TP8
M18
TP9
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
C10
R1 10
10K _0402_5%
1 2
H_ PEC I
KB _RST#
H_T HERM TRIP#_L
56_0 402_5%
56 5%- ->checklist 1.6
54.9 1 %-->CRB 1.0
+3V ALW
INT 3_3V#
TP24
GATE A20 <34>
CLK _CPU_ BCLK # <5>
CL K_CPU _BCL K <5>
H_ PEC I <5>
KB_ RST# <34 >
H_ CPU PW RGD <5>
R5 18
1 2
12
R5 19
56_0 402_5%
DRA MRST _CNTR L_PC H
12
R4 05 10K_ 0402_5%
USB PORT LIST
RIGHT SIDE0
1
LEFT SIDE
CMOS
GPI O17
GPI O36
PCH _TEMP _ALERT#
GPI O16
EC _SC I#
EC_ SMI#
2
3
LEFT SIDE
4
5
CARD READER
6
7
WIRELESS8
9
NEW CARD
10
BT
11
12
3G
13
Title
Size D ocum ent N umber R ev
Cu sto m
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/RSVD
LA-5752P
1
+3VS
KB _RST#
H_T HERM TRIP# <5>
+V CCP
DEVICEPORT
16 5 1Thu rsda y, O ctobe r 29, 2009
12
R1 11
10K _0402_5%
0. 3
5
4
3
2
1
DG1.1 no M3
suppor t and not
Intel LAN, V CCLAN
Source =>GND
+1.0 5VS
R5 27
@
1 2
0_06 03_5%
D D
C C
B B
A A
12
1
R4 86
0_04 02_5%
lsolate AF32,AF34,AH34
from AH35,AJ35
for Intel request 09.09.08
C4 69
@
1U_0 402_6 .3V4Z
2
UPDATE 0210
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C5 16
C5 03
1
1
2
2
1 2
0.1U _0402 _16V4Z
C4 53
1 2
0.1U _0402 _16V4Z
C4 63
1 2
0.1U _0402 _16V4Z
C4 54
1 2
0.1U _0402 _16V4Z
C1 39
+R TCVC C
C5 15
1
2
+1.0 5VS
T8P AD
1 2
C4 61 0.1U _040 2_16V4Z
+1.0 5VS
C4 71
1
2
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C4 75
C5 04
1
1
2
2
C4 52
+VC CRTCEXT
1 2
0.1U _0402 _16V4Z
+PC H_VRM
+VC CADP LLA
+VC CADP LLB
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
C4 84
C4 72
C4 65
1
1
1
2
2
2
+VC CSST
+V1 .1A_I NT_V CCSUS
+3V ALW
0.
0. 2A @ 3. 3 V
2A @ 3. 3 V
0.0.
2A @ 3. 3 V2A@ 3 .3 V
+3VS
0.
0. 4A @ 3. 3 V
4A @ 3. 3 V
0.0.
4A @ 3. 3 V4A@ 3 .3 V
+V CCP
0.
0. 1A @ 1. 1 V
1A @ 1. 1 V
0.0.
1A @ 1. 1 V1A@ 1 .1 V
4.7U _0603 _6.3V6K
0.1U _0402 _16V4Z
C5 00
C4 89
C5 01
1
1
2
2
2m A
2m A @3 . 3V
@3 . 3V
2m A2m A
@3 . 3V@3 . 3V
0.1U _0402 _16V4Z
0.1U _0402 _16V4Z
C4 42
C4 40
1
1
2
2
AP51
AP53
AF23
AF24
AD38
AD39
AD41
1U_0 402_6 .3V6K
AF43
AF41
AF42
1U_0 402_6 .3V6K
AU24
BB51
BB53
BD51
BD53
AH23
AJ35
AH35
AF34
AH34
AF32
AT18
0.1U _0402 _16V4Z
1
AU18
2
U7 J
VCCACLK[1]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
Y20
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[2]
VCCIO[3]
VCCIO[4]
V12
DCPSST
Y22
DCPSUS
P18
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
V_CPU_IO[1]
V_CPU_IO[2]
A12
VCCRTC
IBE XPEAK- M_FCBGA1 071
0.035A
0.072A
0.073A
>1mA
0.052A
0.344A
1.998A
3.208A
2mA
POWER
USB
Clock and Mi scella neous
PCI/GPIO/LPC
0.032A
SA TA
CPU
RTC PCI/GPIO/LPC
0.163A
>1mA
0.357A
6mA
HDA
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
>1mA
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCSATAPLL[1]
VCCSATAPLL[2]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
V5REF
V24
V26
Y24
Y26
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
V23
F24
K49
J38
L38
M36
N36
P36
U35
AD13
AK3
AK1
AH22
AT20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
AA34
Y34
Y35
AA35
L30
+1.05 VS
1U_0 402_6 .3V6K
C4 66
1
2
+3V ALW
C2 24
1
2
+1.0 5VS
P CH_V5 REF_ SUS
PC H_V 5RE F_RU N
+3VS
1
C4 76
0.1U _0402 _16V4Z
2
+3VS
1 2
C4 57 0.1 U_040 2_16V4 Z
+PC H_VRM
+PC H_VCC 1_1_ 20
+PC H_VCC 1_1_ 21
+PC H_VCC 1_1_ 22
+PC H_VCC 1_1_ 23
1U_0 402_6 .3V6K
C4 35
1
2
0.1U _0402 _16V4Z
+3V ALW
0.1U _0402 _16V4Z
C4 55
1
2
+1.0 5VS
1U_0 402_6 .3V6K
C4 83
1
2
R4 88 0_04 02_5%
1 2
R4 87 0_04 02_5%
1 2
R4 89 0_04 02_5%
1 2
R4 90 0_04 02_5%
1 2
R4 10 0_040 2_5%
1 2
R4 11 0_040 2_5%
1 2
@
+1.0 5VS
+3V ALW
+1.5 V
+1.0 5VS
+1.0 5VS
C4 70
1
2
+1.0 5VS
C4 64
1
2
1U_0 402_6 .3V6K
C4 74
C4 73
1
1
2
2
+3VS
+PC H_VRM
+1.0 5VS
10uH i nductor, 120mA
L26
1 2
10UH _LB2 012T100 MR_20%
220U _B2_ 2.5VM_R3 5
10uH i nductor, 120mA
L25
10UH _LB2 012T100 MR_20%
220U _B2_ 2.5VM_R3 5
C5 07
UMA @
1 2
C5 06
UMA @
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1U_0 402_6 .3V6K
1
+
2
1
+
2
10U_ 0603_6. 3V6M
C5 02
1
2
1U_0 402_6 .3V6K
C4 62
1
2
10U_ 0603_ 6.3V6M
C5 14
1
2
C4 94
1U_0 402_6 .3V4Z
@
C4 93
1U_0 402_6 .3V4Z
@
U7 G
AB24
VCCCORE[1]
AB26
VCCCORE[2]
AB28
VCCCORE[3]
AD26
VCCCORE[4]
AD28
VCCCORE[5]
AF26
VCCCORE[6]
AF28
VCCCORE[7]
AF30
VCCCORE[8]
AF31
VCCCORE[9]
AH26
VCCCORE[10]
AH28
VCCCORE[11]
AH30
VCCCORE[12]
AH31
VCCCORE[13]
AJ30
VCCCORE[14]
AJ31
VCCCORE[15]
AK24
VCCIO[24]
BJ24
VCCAPLLEXP
AN20
VCCIO[25]
AN22
VCCIO[26]
AN23
VCCIO[27]
AN24
VCCIO[28]
AN26
VCCIO[29]
AN28
VCCIO[30]
BJ26
VCCIO[31]
BJ28
VCCIO[32]
AT26
VCCIO[33]
AT28
VCCIO[34]
AU26
VCCIO[35]
AU28
VCCIO[36]
AV26
VCCIO[37]
AV28
VCCIO[38]
AW26
VCCIO[39]
AW28
VCCIO[40]
BA26
VCCIO[41]
BA28
VCCIO[42]
BB26
VCCIO[43]
BB28
VCCIO[44]
BC26
VCCIO[45]
BC28
VCCIO[46]
BD26
VCCIO[47]
BD28
VCCIO[48]
BE26
VCCIO[49]
BE28
VCCIO[50]
BG26
VCCIO[51]
BG28
VCCIO[52]
BH27
VCCIO[53]
AN30
VCCIO[54]
AN31
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
IBE XPEAK- M_FCBGA1 071
1
12
2
1
2
POWER
1.524A
0.042A
0.035A
6mA
+VC CADP LLA+1.05 VS
R5 21
0_04 02_5%
@
+VC CADP LLB
+3V S_DAC
10U_ 0805_6. 3V6M
VCCADAC[1]
0.069A
VCCADAC[2]
VSSA_DAC[1]
CRTLVDS
VSSA_DAC[2]
0.030A
0.059A
VCCALVDS
VSSA_LVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCC CORE
C4 77
AE52
AF53
@
AF51
AH38
AH39
AP43
AP45
AT46
AT45
0.01 U_040 2_16V7K
AB34
+3VS
AB35
AD35
1
2
+VC CA_LV DS
+VC CTX_LVDS
C4 85
UMA @
C4 56 0.1U _040 2_16V4Z
0.01 U_040 2_16V7K
AE50
C2 62
1
2
1 2
12
1
2
0.1U _0402 _16V4Z
C4 78
1
2
R2 14
0_04 02_5%
DI S@
0.01 U_040 2_16V7K
1
C4 86
UMA @
2
R2 08
1 2
0_06 03_5%
C5 05
UMA @
+3VS
R2 13 0.022 _0805_1%UMA@
1 2
0.1uH inductor, 200mA
10U_ 0805_6. 3V6M
1
1
C4 92
UMA @
2
2
10U_ 0805_6. 3V6M
+3VS
+1.8V S
L28
UMA @
12
0.1U H_ML F1608 DR10K T_10%_160 8
12
R5 28
0_04 02_5%
DI S@
HVCMOS
+PC H_VRM +1.8 VS
AT24
VCCVRM[2]
VCCDMI[1]
0.061A
DMI
VCCDMI[2]
VCCPNAND[1]
PCI E*
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
0.156A
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
VCCME3_3[1]
NAND / SPI
VCCME3_3[2]
0.085A
VCCME3_3[3]
FDI
VCCME3_3[4]
AT16
AU16
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
AM8
AM9
AP11
AP9
10_0 402_1%
+V CCP
R4 23
R5 09
1 2
1 2
C4 91 1U_0 402_6 .3V6K
C4 68
0.1U _0402 _16V4Z
1
2
+3VS
0.1U _0402 _16V4Z
C4 67
1
2
21
D6
CH75 1H-4 0PT_S OD323-2
1 2
P CH_V5 REF_ SUS
1
C4 47
1U_0 402_6 .3V6K
2
0_04 02_5%
R5 08 0_040 2_5%
1 2
R5 01 0_040 2_5%
1 2
@
+5VS +3VS+3V ALW+5VALW
R4 38
10_0 402_1%
+1.8V S
+3VS
1 2
21
D9
CH75 1H-4 0PT_S OD323-2
PC H_V 5RE F_RU N
20 mi ls20 mi ls
1
C4 48
1U_0 402_6 .3V6K
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/08/12 2009/08/12
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(5/6)-PWR
LA-5752P
1
17 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
4
3
2
1
U7I
AY7
VSS[159]
B11
VSS[160]
B15
VSS[161]
B19
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BC10
BC14
BC18
BC22
BC32
BC36
BC40
BC44
BC52
BD48
BD49
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BF49
BF51
BG18
BG24
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
AF39
VSS[162]
B23
VSS[163]
B31
VSS[164]
B35
VSS[165]
B39
VSS[166]
B43
VSS[167]
B47
VSS[168]
B7
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
BB5
VSS[180]
VSS[181]
VSS[182]
VSS[183]
BC2
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
BH9
VSS[191]
VSS[192]
VSS[193]
BD5
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
BE6
VSS[206]
BE8
VSS[207]
BF3
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
BG4
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
BH7
VSS[224]
C12
VSS[225]
C50
VSS[226]
D51
VSS[227]
E12
VSS[228]
E16
VSS[229]
E20
VSS[230]
E24
VSS[231]
E30
VSS[232]
E34
VSS[233]
E38
VSS[234]
E42
VSS[235]
E46
VSS[236]
E48
VSS[237]
E6
VSS[238]
E8
VSS[239]
F49
VSS[240]
F5
VSS[241]
G10
VSS[242]
G14
VSS[243]
G18
VSS[244]
G2
VSS[245]
G22
VSS[246]
G32
VSS[247]
G36
VSS[248]
G40
VSS[249]
G44
VSS[250]
G52
VSS[251]
VSS[252]
H16
VSS[253]
H20
VSS[254]
H30
VSS[255]
H34
VSS[256]
H38
VSS[257]
H42
VSS[258]
D D
C C
B B
A A
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
U7H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
VSS[19]
AB5
VSS[20]
AB8
VSS[21]
AC2
VSS[22]
AC52
VSS[23]
AD11
VSS[24]
AD12
VSS[25]
AD16
VSS[26]
AD23
VSS[27]
AD30
VSS[28]
AD31
VSS[29]
AD32
VSS[30]
AD34
VSS[31]
AU22
VSS[32]
AD42
VSS[33]
AD46
VSS[34]
AD49
VSS[35]
AD7
VSS[36]
AE2
VSS[37]
AE4
VSS[38]
AF12
VSS[39]
Y13
VSS[40]
AH49
VSS[41]
AU4
VSS[42]
AF35
VSS[43]
AP13
VSS[44]
AN34
VSS[45]
AF45
VSS[46]
AF46
VSS[47]
AF49
VSS[48]
AF5
VSS[49]
AF8
VSS[50]
AG2
VSS[51]
AG52
VSS[52]
AH11
VSS[53]
AH15
VSS[54]
AH16
VSS[55]
AH24
VSS[56]
AH32
VSS[57]
AV18
VSS[58]
AH43
VSS[59]
AH47
VSS[60]
AH7
VSS[61]
AJ19
VSS[62]
AJ2
VSS[63]
AJ20
VSS[64]
AJ22
VSS[65]
AJ23
VSS[66]
AJ26
VSS[67]
AJ28
VSS[68]
AJ32
VSS[69]
AJ34
VSS[70]
AT5
VSS[71]
AJ4
VSS[72]
AK12
VSS[73]
AM41
VSS[74]
AN19
VSS[75]
AK26
VSS[76]
AK22
VSS[77]
AK23
VSS[78]
AK28
VSS[79]
IBE XPEAK- M_FCBGA1 071
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
IBE XPEAK- M_FCBGA1 071
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/10/31 2009/10/31
Compal Secret Data
Deciphered Date
Title
Size D ocum ent N umber R ev
Cu sto m
2
Da te: She et o f
Compal Electronics, Inc.
IBEX-M(6/6)-GND
LA-5752P
1
18 5 1Thu rsda y, O ctobe r 29, 2009
0. 3
5
DIS@
C120 0.1U_0402_16V7KDIS@
C119 0.1U_0402_16V7KDIS@
C118 0.1U_0402_16V7KDIS@
C117 0.1U_0402_16V7KDIS@
C80 0.1U_0402_16V7KDIS@
C79 0.1U_0402_16V7KDIS@
C78 0.1U_0402_16V7KDIS@
C77 0.1U_0402_16V7KDIS@
C116 0.1U_0402_16V7KDIS@
C115 0.1U_0402_16V7KDIS@
C114 0.1U_0402_16V7KDIS@
C113 0.1U_0402_16V7KDIS@
C112 0.1U_0402_16V7KDIS@
C111 0.1U_0402_16V7KDIS@
C109 0.1U_0402_16V7KDIS@
C110 0.1U_0402_16V7KDIS@
C108 0.1U_0402_16V7KDIS@
C107 0.1U_0402_16V7KDIS@
C105 0.1U_0402_16V7KDIS@
C106 0.1U_0402_16V7KDIS@
C104 0.1U_0402_16V7KDIS@
C103 0.1U_0402_16V7KDIS@
C102 0.1U_0402_16V7KDIS@
C101 0.1U_0402_16V7KDIS@
C100 0.1U_0402_16V7KDIS@
C99 0.1U_0402_16V7KDIS@
C98 0.1U_0402_16V7KDIS@
C97 0.1U_0402_16V7KDIS@
C96 0.1U_0402_16V7KDIS@
C95 0.1U_0402_16V7KDIS@
C94 0.1U_0402_16V7KDIS@
C93 0.1U_0402_16V7KDIS@
PEG_CLKREQ#<14>
PCIE_ CTX_GRX_N[0..15]
PCIE_CTX _GRX_P[0..15]
PCIE_ CRX_GTX_N[0..15]
PCIE_ CRX_GTX_P[0..15]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CLK_PC IE_VGA<14>
CLK_PCIE_VGA#<14>
12
R46
10K_0402_5%
@
+3VS
PEG_CLKREQ#
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15
CLK_PC IE_VGA
CLK_PC IE_VGA#
1 2
R540 200_0 402_5%@
1 2
R541 2.49K_04 02_1% DIS@
DIS@
10K_0402_5%
1 2
R542
1 2
R543 0_0402_5%@
PCIE_ CTX_GRX_N[0..15]<6>
PCIE_CTX _GRX_P[0..15]<6>
PCIE_ CRX_GTX_N[0..15]<6>
PCIE_CR X_GTX_P[0..15]<6>
D D
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
C C
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15
BUF_PLT_RST#< 5,16,28,29>
B B
4
U22A
AE12
PEX_RX0
AF12
PEX_RX0_N
AG12
PEX_RX1
AG13
PEX_RX1_N
AF13
PEX_RX2
AE13
PEX_RX2_N
AE15
PEX_RX3
AF15
PEX_RX3_N
AG15
PEX_RX4
AG16
PEX_RX4_N
AF16
PEX_RX5
AE16
PEX_RX5_N
AE18
PEX_RX6
AF18
PEX_RX6_N
AG18
PEX_RX7
AG19
PEX_RX7_N
AF19
PEX_RX8
AE19
PEX_RX8_N
AE21
PEX_RX9
AF21
PEX_RX9_N
AG21
PEX_RX10
AG22
PEX_RX10_N
AF22
PEX_RX11
AE22
PEX_RX11_N
AE24
PEX_RX12
AF24
PEX_RX12_N
AG24
PEX_RX13
AF25
PEX_RX13_N
AG25
PEX_RX14
AG26
PEX_RX14_N
AF27
PEX_RX15
AE27
PEX_RX15_N
AD10
PEX_TX0
AD11
PEX_TX0_N
AD12
PEX_TX1
AC12
PEX_TX1_N
AB11
PEX_TX2
AB12
PEX_TX2_N
AD13
PEX_TX3
AD14
PEX_TX3_N
AD15
PEX_TX4
AC15
PEX_TX4_N
AB14
PEX_TX5
AB15
PEX_TX5_N
AC16
PEX_TX6
AD16
PEX_TX6_N
AD17
PEX_TX7
AD18
PEX_TX7_N
AC18
PEX_TX8
AB18
PEX_TX8_N
AB19
PEX_TX9
AB20
PEX_TX9_N
AD19
PEX_TX10
AD20
PEX_TX10_N
AD21
PEX_TX11
AC21
PEX_TX11_N
AB21
PEX_TX12
AB22
PEX_TX12_N
AC22
PEX_TX13
AD22
PEX_TX13_N
AD23
PEX_TX14
AD24
PEX_TX14_N
AE25
PEX_TX15
AE26
PEX_TX15_N
AB10
PEX_REFCLK
AC10
PEX_REFCLK_N
AF10
PEX_TSTCLK_OUT
AE10
PEX_TSTCLK_OUT_N
AG10
PEX_TERMP
AD9
PEX_RST_N
AE9
PEX_CLKREQ_N
N11M-GE1-S-A2 _BGA533
DIS@
Part 1 of 5
PCI EXPRESS
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_VREF
DACA_RSET
DACB_HSYNC
DACB_VSYNC
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_VREF
DACB_RSET
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TEST
TESTMODE
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2C DACADACB
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
XTAL_SSIN
XTAL_OUTBUFF
XTAL_OUT
XTAL_IN
CLK
3
N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2
AD2
AD1
AE2
AD3
AE3
AF1
AE1
U6
U4
T5
R4
T4
R6
V6
AF3
AG4
AE4
AF4
AG3
AD25
R1
T3
R2
R3
A2
B1
A3
A4
T1
T2
NV_INVTPWM
VGA_E NVDD_R
VGA_ENBKL_R
1 2
R511 0_0402_5%DIS@
1 2
R512 0_0402_5%DIS@
VGA_GPIO11
VGA_GPIO14
PAD
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G
DACA _VREF
DACA_RSET
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
VGA_D DCCLK_C
VGA_DDC DATA_C
I2CB_SCL
I2CB_SDA
VGA_LVDS_SCL _C
VGA_LVDS_SDA _C
HDCP_SMB_CK1
HDCP _SMB_DAI
T4
R48 124_0402 _1%DIS@
SMB_EC_CK2_R
SMB_EC_DA2_R
HDMI_DETECT_VGA <24>
PAD
VGA_E NVDD_R <27>
VGA_ENBKL_R <27>
VGA_H SYNC <26>
VGA_V SYNC <26>
VGA_CRT_R <26>
VGA_CRT_B <26>
VGA_CRT_G <26>
DIS@
12
C81 0.1U_0402_16V4Z
1 2
R539 10K_0402_5%DIS@
1 2
R24 10K_0402_5%DIS@
1 2
R2510K_0402_5% @
R517 2.2K_0402_5%DIS@
1 2
R516 2.2K_0402_5%
1 2
DIS@
I2CS is internal thermal s ensor.
D11
E9
XTALOUT
E10
XTALIN
D10
T9
GPU_V ID0
GPU_V ID1
CRT OUT
PAD
T14
PAD
T13
PAD
T12
PAD
T11
+3VS
SMB_EC_CK2_R <14,31>
SMB_EC_DA2_R <14,31>
R42
10K_0402_5%
DIS@
R499
DIS@
N10M-GS
(40nm)
N11M- GE1/LP1
(40nm)
+3VS
GPU_V ID0 <45>
GPU_V ID1 <45>
+3VS
2.2K_0402_5%
I2CS is VDD33 powe r plane
same as EC +3.3VS.
12
12
R34
10K_0402_5%
DIS@
2
R478
2.2K_0402_5%
DIS@
Devic e ID
0x0A74
Devic e ID
0x0A7D
1
GPIO6GPIO5
1
VGA_COR EGPU_VID 00GPU_VID 1
00
1
1
0.8V
0.85V
1.0V
VGA_COR EGPU_VID 00GPU_VID 1
12
R505
10K_0402_5%
@
1 2
1 2
1 2
R443 4.7K_0402_5%@
R444 4.7K_0402_5%@
R64 2.2K_0402_5 %DIS@
R63 2.2K_0402_5 %DIS@
0.8V
0.85V
0.9V
12
12
12
12
00
1
1
10K_0402_5%
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_D DCCLK_C
VGA_DDC DATA_C
VGA_LVDS_SCL _C
VGA_LVDS_SDA _C
Removed external HDCP.
07/17/2009
1
VGA_GPIO11
VGA_GPIO14
12
R513
@
R537 150_0402_1%DIS@
R538 150_0402_1%DIS@
R530 150_0402_1%DIS@
Pul l Hi at CR T CO NN s ide.
P-State
Deep P1 2
P8
P0
P-State
Deep P1 2
P8
P0
+3VS
+3VS
Y2
4
GND
1
IN
27MHZ_16PF_X7S027000BG1H-U
DIS@
1
C69
20P_0402_50V8
A A
DIS@
2
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
3
OUT
2
GND
1
C56
20P_0402_50V8
2
DIS@
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
VGA_D DCCLK_C
VGA_DDC DATA_C
VGA_LVDS_SCL _C
VGA_LVDS_SDA _C
2
L17 MBK16081 21YZF_0603DIS@
1 2
1 2
L18 MBK16081 21YZF_0603DIS@
L8
L7 MBK 1608121YZF_0603DIS@
MBK16 08121YZF_0603DIS@
1 2
1 2
1
1
C450
C451
DIS@
DIS@
12P_0402_50V8J
12P_0402_50V8J
Size Doc ument Number Re v
Date: Sheet of
2
Title
N10M-GE1 PCIE,GPIO,CLK
B
1
C85
C86
DIS@
DIS@
2
2
12P_0402_50V8J
Compal Electronics, Inc.
LA-5752P
1
12P_0402_50V8J
2
1
VGA_D DCCLK <26>
VGA_LVDS_SCL <27>
VGA_DDCDATA <26>
VGA_LVDS_SDA <27>
0.3
19 51Th ursday, October 2 9, 2009
5
FBAA[ 0..13]<23>
FBBA [2..5]<23>
FBADQ M[0..7]<23>
FBAD QS[0..7]<23>
FBADQ S#[0..7]<23>
FBA D[0..63]<23>
D D
C C
B B
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
U22B
D22
FBA_D0
E24
FBA_D1
E22
FBA_D2
D24
FBA_D3
D26
FBA_D4
D27
FBA_D5
C27
FBA_D6
B27
FBA_D7
A21
FBA_D8
B21
FBA_D9
C21
FBA_D10
C19
FBA_D11
C18
FBA_D12
D18
FBA_D13
B18
FBA_D14
C16
FBA_D15
E21
FBA_D16
F21
FBA_D17
D20
FBA_D18
F20
FBA_D19
D17
FBA_D20
F18
FBA_D21
D16
FBA_D22
E16
FBA_D23
A22
FBA_D24
C24
FBA_D25
D21
FBA_D26
B22
FBA_D27
C22
FBA_D28
A25
FBA_D29
B25
FBA_D30
A26
FBA_D31
U24
FBA_D32
V24
FBA_D33
V23
FBA_D34
R24
FBA_D35
T23
FBA_D36
R23
FBA_D37
P24
FBA_D38
P22
FBA_D39
AC24
FBA_D40
AB23
FBA_D41
AB24
FBA_D42
W24
FBA_D43
AA22
FBA_D44
W23
FBA_D45
W22
FBA_D46
V22
FBA_D47
AA25
FBA_D48
W27
FBA_D49
W26
FBA_D50
W25
FBA_D51
AB25
FBA_D52
AB26
FBA_D53
AD26
FBA_D54
AD27
FBA_D55
V25
FBA_D56
R25
FBA_D57
V26
FBA_D58
V27
FBA_D59
R26
FBA_D60
T25
FBA_D61
N25
FBA_D62
N26
FBA_D63
N11M-GE1-S-A2 _BGA533
DIS@
FBAA[ 0..13]
FBB A[2..5]
FBADQ M[0..7]
FBA DQS[0..7]
FBADQ S#[0..7]
FBA_D [0..63]
Part 2 of 5
MEMORY INTERFACE
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CLK0_N
FBA_CLK1_N
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FB_VREF
FBA_CLK0
FBA_CLK1
FBA_DEBUG
FBAA4
F26
FBARAS#
J24
FBAA5
F25
FBA_BA1
M23
FBBA2
N27
FBBA4
M27
FBBA3
K26
J25
FBBACS0#
J27
FBAA11
G23
FBACAS#
G26
FBAWE#
J23
FBA_BA0
M25
FBBA5
K27
FBAA12
G25
FBA_RST
L24
FBAA7
K23
FBAA10
K24
G22
FBAA0
K25
FBAA9
H22
FBAA6
M26
FBAA2
H24
FBAA8
F27
FBAA3
J26
FBAA1
G24
FBAA13
G27
FBA_BA2
M24
FBBAODT0
K22
FBAACS0#
J22
FBAAODT0
L22
FBADQM0
C26
FBADQM1
B19
FBADQM2
D19
FBADQM3
D23
FBADQM4
T24
FBADQM5
AA23
FBADQM6
AB27
FBADQM7
T26
FBADQS#0
D25
FBADQS#1
A18
FBADQS#2
E18
FBADQS#3
B24
FBADQS#4
R22
FBADQS#5
Y24
FBADQS#6
AA27
FBADQS#7
R27
FBADQS0
C25
FBADQS1
A19
FBADQS2
E19
FBADQS3
A24
FBADQS4
T22
FBADQS5
AA24
FBADQS6
AA26
FBADQS7
T27
FB_VRE F1
A16
F24
F23
N24
N23
M22
10K_0402_5%D IS@
1 2
FBAA_CKE
R26
4
FBARAS# <23>
FBA_BA1 <23>
FBBA_CKE
FBBACS0# <23>
FBACAS# <23>
FBAWE# <23>
FBA_BA0 <23>
FBAA12 <23>
12
R23
10K_0402_5%
DIS@
FBAACS0# <23>
12
R15
10K_0402_5%
DIS@
FBACLK0 <23>
FBACLK0# <23>
FBACLK1 <23>
FBACLK1# <23>
+1.5VS
12
12
FBAA_CKE <23>
FBAAODT0 <23>
12
1.27V~0.9V
R22
10K_0402_5%
DIS@
R16
10K_0402_5%
DIS@
R18
10K_0402_5%
DIS@
FBBA_CKE <23>
FBA_RST <23>
FBA_BA2 <23>
FBBAODT0 <23>
10mil
1
C43
0.01U_0402_16V7K
@
2
HDMI
LVDS
+1.5VS
12
12
3
12P_0402_50V8J
VGA_LVDS_ACLK<27>
VGA_LVDS_ACLK#<27>
VGA_LVDS_A0<27>
VGA_LVDS_A0#<27>
VGA_LVDS_A1<27>
VGA_LVDS_A1#<27>
VGA_LVDS_A2<27>
VGA_LVDS_A2#<27>
VGA_HDMI_TX2+<24>
VGA_HDMI_TX2-<24>
VGA_HDMI_TX1+<24>
VGA_HDMI_TX1-<24>
VGA_HDMI_TX0+<24>
VGA_HDMI_TX0-<24>
VGA_HDMI_CLK+<24>
VGA_HDM I_CLK-< 24>
R30
1.3K_0402_1%
@
R29
1.3K_0402_1%
@
C649
2
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
2
2
C650
12P_0402_50V8J
1
@
1
@
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#
IFPC_AUX
IFPC_AUX_N
IFPC_AUX
U22C
AC4
IFPA_TXC
AD4
IFPA_TXC_N
V5
IFPA_TXD0
V4
IFPA_TXD0_N
AA5
IFPA_TXD1
AA4
IFPA_TXD1_N
W4
IFPA_TXD2
Y4
IFPA_TXD2_N
AB4
IFPA_TXD3
AB5
IFPA_TXD3_N
AB3
IFPB_TXC
AB2
IFPB_TXC_N
W1
IFPB_TXD4
V1
IFPB_TXD4_N
W3
IFPB_TXD5
W2
IFPB_TXD5_N
AA2
IFPB_TXD6
AA3
IFPB_TXD6_N
AB1
IFPB_TXD7
AA1
IFPB_TXD7_N
G4
IFPC_AUX_I2CW_SCL
G5
IFPC_AUX_I2CW_SDA_N
P4
IFPC_L0
N4
IFPC_L0_N
M5
IFPC_L1
M4
IFPC_L1_N
L4
IFPC_L2
K4
IFPC_L2_N
H4
IFPC_L3
J4
IFPC_L3_N
D3
IFPD_AUX_I2CX_SCL
D4
IFPD_AUX_I2CX_SDA_N
F5
IFPD_L0
F4
IFPD_L0_N
E4
IFPD_L1
D5
IFPD_L1_N
C3
IFPD_L2
C4
IFPD_L2_N
B3
IFPD_L3
B4
IFPD_L3_N
F7
IFPE_AUX_I2CY_SCL
G6
IFPE_AUX_I2CY_SDA_N
D6
IFPE_L0
C6
IFPE_L0_N
A6
IFPE_L1
A7
IFPE_L1_N
B6
IFPE_L2
B7
IFPE_L2_N
E6
IFPE_L3
E7
IFPE_L3_N
N11M-GE1-S-A2 _BGA533
DIS@
4.7K_0402_5%
DIS@
Part 3 of 5
R526
1 2
NCRFU
RFU_1
RFU_2
RFU_3
RFU_4
RFU_5
STRAP0
STRAP1
STRAP2
BUFRST_N
LVDS / TMDS
THERMDN
THERMDP
GENERAL STRAPSERIAL
SPDIF
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
IFPAB_RSET
IFPC_RSET
IFPD_RSET
IFPE_RSET
+3VS
2
Q38A
2N7002DW -T/R7_SOT363-6
DIS@
61
CEC
NC
NC
NC
+3VS
C15
D15
J5
T6
W6
Y6
AA6
N3
C7
B9
A9
N5
D8
D9
N2
F9
B10
C9
A10
C10
AB6
R5
M6
F8
STRAP0
STRAP1
STRAP2
PAD
T1
PAD
T2
PAD
T3
SP DIF_IN
R32 36K_0402_5%
ROM_SCLK
ROM_SI
ROM_SO
R44 1K_0402_1%@
R39 1K_0402_1%DIS @
R40 1K_0402_1%@
R477 1K_0402_1%@
+3VS
DIS@
1 2
1 2
1 2
1 2
1 2
VGA_HDMI_SCL <24>
STRAP0 <22>
STRAP1 <22>
STRAP2 <22>
12
R445
10K_0402_5%
DIS@
ROM_SCLK <22 >
ROM_SI <22>
ROM_SO <22>
1
+3VS
12
R468
10K_0402_5%
DIS@
R531
4.7K_0402_5%
DIS@
IFPC_AUX_N
A A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
1 2
2
5
DIS@
Q38B
2N7002DW-T/R7_SOT363-6
5V PULL UP IN CONNECTER SIDE
3
4
Title
Size Doc ument Number Re v
B
Date: Sheet
VGA_HDMI_SDA <24>
Compal Electronics, Inc.
N10M-GE1 LVDS,Memory Bus
LA-5752P
1
0.3
of
20 51Th ursday, October 2 9, 2009
5
NEAR BGA
+VGA_C ORE
NEAR BALL
4.7U 6 .3V K X5R 0603
1
C26
D D
DIS@
2
0.1U_0 402_10V7K
N10M-GS: 15.8A
N11M-GE1:16.7A
1
2
1
C68
DIS@
2
1
C73
DIS@
2
+3VS
1
C84
DIS@
2
4.7U 6 .3V K X5R 0603
1U_04 02_6.3V6K
1
C512
DIS@
2
1U_04 02_6.3V6K
1
2
1U_04 02_6.3V6K
1
C67
DIS@
2
1U_04 02_6.3V6K
1
2
5
1U_04 02_6.3V6K
C499
DIS@
C498
DIS@
C72
DIS@
0.1U_0 402_10V7K
1
2
NEAR BALL
C C
120mA
NEAR BGA
NEAR BGA
+1.8VS
L27
MBK16 08121YZF_0603
1 2
DIS@
300mA
4.7U 6 .3V K X5R 0603
B B
NEAR BGA
+1.05VS
L4
MBK16 08121YZF_0603
1 2
DIS@
285mA
4.7U 6 .3V K X5R 0603
NEAR BGA
+3VS
A A
L6
DIS@
1 2
MBK16 08121YZF_0603
220mA
4.7U 6 .3V K X5R 0603
1
C50
DIS@
2
C459
DIS@
0.1U_0 402_10V7K
NEAR BALL
1
DIS@
2
0.1U_0 402_10V7K
1
2
0.1U_0 402_10V7K
1
C74
DIS@
2
0.1U_0 402_10V7K
0.1U_0 402_10V7K
1
1
C62
DIS@
2
2
0.047U _0402_25V7K
1
C38
DIS@
2
0.01U_ 0402_16V7K
0.047U _0402_25V7K
1
C41
DIS@
2
1
DIS@
2
0.01U_ 0402_16V7K
C36
0.01U_ 0402_16V7K
0.047U _0402_25V7K
NEAR BALL
0.1U_0 402_10V7K
1
2
0.1U_0 402_10V7K
C510
0.1U_0 402_10V7K
C497
DIS@
NEAR BALL
C63
DIS@
1
C44
DIS@
2
1
C511
DIS@
2
1
C496
DIS@
2
0.1U_0 402_10V7K
1
C66
DIS@
2
1
C61
DIS@
2
0.1U_0 402_10V7K
+IFPC _PLLVDD
1
C39
DIS@
2
1
C37
DIS@
2
1
C52
DIS@
2
C55
DIS@
0.1U_0 402_10V7K
4
0.01U_ 0402_16V7K
1
C40
DIS@
2
0.01U_ 0402_16V7K
1
C29
DIS@
2
0.01U_ 0402_16V7K
1
C51
DIS@
2
1
C54
DIS@
2
NEAR BGA
+1.05VS
4
+PEX_SVDD_3V3
+IFP A_IOVDD
+IFP B_IOVDD
+IF PC_IOVDD
12
R4110K_0402_5%
DIS@
+IFPA B_PLLVDD
+IFPC _PLLVDD
1 2
R49 0_0402 _5%
DIS@
@
12
R4710 K_0402_5%
DIS@
12
R4310 K_0402_5%
L5
DIS@
1 2
MBK16 08121YZF_0603
220mA
4.7U 6 .3V K X5R 0603
1
C82
DIS@
2
U22D
J9
VDD
J10
VDD
J12
VDD
J13
VDD
L9
VDD
M9
VDD
M11
VDD
M17
VDD
N9
VDD
N11
VDD
N12
VDD
N13
VDD
N14
VDD
N15
VDD
N16
VDD
N17
VDD
N19
VDD
P11
VDD
P12
VDD
P13
VDD
P14
VDD
P15
VDD
P16
VDD
P17
VDD
R9
VDD
R11
VDD
R12
VDD
R13
VDD
R14
VDD
R15
VDD
R16
VDD
R17
VDD
T9
VDD
T11
VDD
T17
VDD
U9
VDD
U19
VDD
W9
VDD
W10
VDD
W12
VDD
W13
VDD
W18
VDD
W19
VDD
A12
VDD33
B12
VDD33
C12
VDD33
D12
VDD33
E12
VDD33
F12
VDD33
AG9
PEX_SVDD_3V3
V3
IFPA_IOVDD
V2
IFPB_IOVDD
J6
IFPC_IOVDD
H6
IFPDE_IOVDD
AD5
IFPAB_PLLVDD
P6
IFPC_PLLVDD
N6
IFPD_PLLVDD
D7
IFPE_PLLVDD
N11M- GE1-S-A2 _BGA533
DIS@
1U_04 02_6.3V6K
1
C71
DIS@
2
3
PLACE UNDER GPU
Part 4 of 5
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
POWER
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_PLLVDD
VID_PLLVDD
SP_PLLVDD
FB_PLLAVDD
FB_PLLAVDD
FB_DLLAVDD
FB_CAL_PD_VDDQ
VDD_SENSE
VDD_SENSE
+PEX_SVDD_3V3
+IFPA B_PLLVDD
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
PLLVDD
DACA_VDD
DACB_VDD
Issued Date
3
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7
AG7
AF7
AE7
AD8
AD7
AC9
+PEX_PLLVDD
AF9
K6
+SP_PLLV DD
L6
K5
R19
AC19
T19
+DACA _VDD
AG2
+DACB _VDD
W5
B15
R465 40.2_ 0402_1%DIS@
W15
E15
NEAR BALL
+3VS
120mA
1
C458
DIS@
2
0.1U_0 402_10V7K
+DACA _VDD
0.01U_ 0402_16V7K
0.1U_0 402_10V7K
0.1U_0 402_10V7K
R45 1 0K_0402_5%DIS@
NEAR BALL NEAR BGA
1
2
470P_0402_50V7K
2007/10/15 2008/10/15
0.01U_ 0402_16V7K
1
1
2
NEAR BALL
1
2
NEAR BALL NEAR BGA
1
2
C53
DIS@
2
0.1U_0 402_10V7K
1
C46
DIS@
2
0.1U_0 402_10V7K
1
C47
DIS@
2
C28
DIS@
0.01U_ 0402_16V7K
C58
DIS@
C60
DIS@
0.1U_0 402_10V7K
NEAR BALL
+1.05VS_PLL
12~ 16mil
+FB_P LLAVDD
1 2
The pow er is base on VR AM type.
+VGASENSE
4700P_0402_25V7K
C523
DIS@
0.1U_0 402_10V7K
+1.5VS
+VGASENSE <45>
1
1
C522
DIS@
2
2
0.1U_0 402_10V7K
Compal Secret Data
Deciphered Date
1
C27
DIS@
2
1
C59
DIS@
2
0.1U_0 402_10V7K
1
C480
DIS@
2
+SP_PLLV DD
+FB_P LLAVDD
0.1U_0 402_10V7K
1
C520
DIS@
2
0.047U _0402_25V7K
1U_04 02_6.3V6K
1
C481
DIS@
2
C513
DIS@
0.1U_0 402_10V7K
2
1
1
2
NEAR BGA
1U_04 02_6.3V6K
C32
C42
DIS@
DIS@
2
0.047U _0402_25V7K
1
C83
DIS@
2
1U_04 02_6.3V6K
1
C49
DIS@
2
1U_04 02_6.3V6K
NEAR BGA
1U_04 02_6.3V6K
NEAR BGA
1U_04 02_6.3V6K
1
2
1U_04 02_6.3V6K
1
C64
DIS@
2
NEAR BGA
1U_04 02_6.3V6K
1
C30
DIS@
2
1U_04 02_6.3V6K
1
C521
DIS@
2
2
0.047U _0402_25V7K
1
C31
DIS@
2
4.7U 6 .3V K X5R 0603
1
1
C537
C35
DIS@
DIS@
2
2
4.7U 6 .3V K X5R 0603
1
2
C65
DIS@
4.7U 6 .3V K X5R 0603
1
C48
DIS@
2
1
1
C45
DIS@
2
2
4.7U 6 .3V K X5R 0603
MBK16 08121YZF_0603
1
C482
DIS@
2
4.7U 6 .3V K X5R 0603
1
C488
DIS@
2
1 2
MBK16 08121YZF_0603
1
C23
DIS@
2
4.7U 6 .3V K X5R 0603
1
C519
DIS@
2
4.7U 6 .3V K X5R 0603
1
CLOSE TO GPU
+1.5VS
4.7U 6 .3V K X5R 0603
1
N10M-GS: 2.63A
C24
DIS@
N11M-GE1:2.55A
2
+1.05VS
2A
22U_0805_6.3V6M
1
1
C538
C552
DIS@
DIS@
2
2
10U_0 805_6.3V6M
+1.05VS
1
C553
C551
DIS@
DIS@
2
10U_0805_6.3V6M
1 2
MBK16 08121YZF_0603
DIS@
C57
DIS@
L21
DIS@
120mA
L3
+1.05VS
12
+1.05VS
VID_PLLVDD=45mA
SP_PLLVDD=45mA
PLLVDD=60mA
L24
1 2
MBK16 08121YZF_0603
DIS@
L1
DIS@
+1.05VS
+1.05VS
FB_PLLVDD=100mA
FB_DLLVDD=100mA
L29
MBK16 08121YZF_0603
1
C524
DIS@
2
Title
Size Do cument Number R ev
Cu stom
Da te: Sh eet of
+3VS
12
DIS@
120mA
Compal Electronics, Inc.
N10M-GE1 PWR
LA -57 52P
1
21 51Thu rsday, October 29, 20 09
0.3
5
4
3
2
1
A to tal of 8 si gnals a re require d for GB1 strapping this inclu des
2 re ference signals
6 ph ysic al strappi ng pins
4 lo gica l strappin g bits
U22E
B2
B5
B8
B11
B14
D D
C C
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13
W16
E14
N11M-GE1-S-A2 _BGA533
Place Components Close to BGA
DIS@
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_SENSE
GND_SENSE
Part 5 of 5
FB_CAL_TERM_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF0_GND
GND
FB_CAL_PU_GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6
A15
B16
F11
F10
R28 40.2_0402_1%DIS@
1 2
R27 60.4_0402_1%
1 2
DIS@
12
R463
40.2K_0402_1%
DIS@
12
R464
40.2K_0402_1%
DIS@
A to tal of 24 logi cal strap ping bits are availa ble
+3VS
12
R474
@
DIS@
STRAP2<20>
STRAP1<20>
STRAP0<20>
ROM_SCLK<20>
ROM_SI<20>
ROM_SO<20>
STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO
DIS@
30K_0402_1%
12
R475
@
30K_0402_1%
12
12
R472
R473
DIS@
34.8K_0402_1%
45.3K_0402_1%
12
12
R471
R476
@
34.8K_0402_1%
10K_0402_5%
FB M emory (DD R3)
K4W1 G1646E-HC 12
H5TQ 1G63BFR-1 2C
LP 1
(0x0A7D )
40nm
Samsung
800MHz
(defaul )
Hynix
800MHz
12
R51
DIS@
12
R50
@
ROM_SO
12
12
15K_0402_1%
12
15K_0402_1%
R467
R469
@
@
2K_0402_5%
2K_0402_5%
12
R466
R470
DIS@
X76@
20K_0402_1%
10K_0402_5%
STRA P1 u se for 3GIO _PADCFG to set 35K p ull up.
(PUN -043 35-001_V 10 HW9 upd ate)
ROM_SIR OM_SCL K STRAP0ST RAP1STRAP 2GPU
PD 15K
PD 15K
PU 30K
PD 15K6 4Mx16
PU 30KPD 10K
PU 35KN11M-GE 1
PU 35K
PU 45KPD 10K PD 20 K64Mx16
PU 45K
X76
B B
N11M-GE 1
LP 1
Memory/PKG
DDR3
+1.5VS
Must b e used 1% resister for driver calibration
A A
5
FB_CAL_PU_GND FBCAL_PD_VDDQ
40.2 ohm
DG-04642-001-V01(May 22, 2009)
4
FBCAL_TERM_GNDFBVDDQ
40.2/60.4 ohm40.2 ohm
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
2
Date: Sheet of
Compal Electronics, Inc.
N10M-GE1 GND & STRAP
LA-5752P
22 51Th ursday, October 2 9, 2009
1
0.3
5
N10x 40nm DDR3 MAPPING
NVIDIA COCUMENT FOR DA-3978-00 1
FBA A[0. .13]<20>
FBB A[2. .5]<20>
FBA DQM[ 0..7 ]<20>
FBA DQS[ 0.. 7]<2 0>
FBA DQS# [0. .7]<20>
FBA D[0 ..63 ]<20 >
D D
C C
FBA A[0. .13]
FBB A[2. .5]
FBA DQM[ 0.. 7]
FBA DQS[ 0.. 7]
FBA DQS# [0. .7]
FBA _D[ 0.. 63]
+VR AM_V REFB
+VR AM_V REFA
FBA A0
FBA A1
FBA A2
FBA A3
FBA A4
FBA A5
FBA A6
FBA A7
FBA A8
FBA A9
FBA A10
FBA A11
FBA A12
FBA A13
R1 2
240 _0402_1 %
FBA _BA0
FBA _BA1
FBA _BA2
FBA AODT 0
FBA ACS 0#
FBA RAS#
FBA CAS#
F BAWE #
FBA DQS1
FBA DQS3
FBA DQM1
FBA DQM3
FBA DQS# 1
FBA DQS# 3
FBA _RST
12
DI S@
FBA A_CK E
FBA _BA0< 20>
FBA _BA1< 20>
FBA _BA2< 20>
FBA CLK0 #< 20> FBA CLK1 #< 20>
FBA A_CK E<2 0>
FBA AODT0< 20> FBB AODT0< 20>
FBA ACS0 #<20> FBB ACS0 #<20>
FB ARAS #<20>
FB ACAS #<20>
FB AWE #< 20>
FBA _RST<20>
U2 1
M9
VREFCA
H2
VREFDQ
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12
T4
A13
T8
A14
M8
A15/BA3
M3
BA0
N9
BA1
M4
BA2
J8
CK
K8
CK
K10
CKE/CKE0
K2
ODT/ODT0
L3
CS
J4
RAS
K4
CAS
L4
WE
F4
DQSL
C8
DQSU
E8
DML
D4
DMU
G4
DQSL
B8
DQSU
T3
RESET
L9
ZQ/ZQ0
J2
NC/ODT1
L2
NC/CS1
J10
NC/CE1
L10
NCZQ1
A1
NC
A11
NC
T1
NC
T11
NC
100- BALL
SDR AM DDR 3
K4B 1G16 46D- HCF 8_FBGA10 0
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
4
+VR AM_V REFB
+VR AM_V REFA
FBA _D9
E4
FBA _D14
F8
FBA _D8
F3
FBA _D12
F9
FBA _D10
H4
FBA _D13
H9
FBA _D11
G3
FBA _D15
H8
FBA _D26
D8
FBA _D29
C4
FBA _D24
C9
FBA _D25
C3
FBA _D28
A8
FBA _D31
A3
FBA _D27
B9
FBA _D30
A4
+1. 5VS
B3
VDD
D10
VDD
G8
VDD
K3
VDD
K9
VDD
N2
VDD
N10
VDD
R2
VDD
R10
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+1. 5VS
A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
B2
B10
D2
D9
E3
E9
F10
G2
G10
1
3
R2 1
240 _0402_1 %
FBA A0
FBA A1
FBA A2
FBA A3
FBA A4
FBA A5
FBA A6
FBA A7
FBA A8
FBA A9
FBA A10
FBA A11
FBA A12
FBA A13
FBA _BA0
FBA _BA1
FBA _BA2
FBA CLK0
FBA A_CK E
FBA AODT 0
FBA ACS 0#
FBA RAS#
FBA CAS#
F BAWE #
FBA DQS2
FBA DQS0
FBA DQM2
FBA DQM0
FBA DQS# 2
FBA DQS# 0
FBA _RST
12
DI S@
U2
M9
VREFCA
H2
VREFDQ
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12
T4
A13
T8
A14
M8
A15/BA3
M3
BA0
N9
BA1
M4
BA2
J8
CK
K8
CK
K10
CKE/CKE0
K2
ODT/ODT0
L3
CS
J4
RAS
K4
CAS
L4
WE
F4
DQSL
C8
DQSU
E8
DML
D4
DMU
G4
DQSL
B8
DQSU
T3
RESET
L9
ZQ/ZQ0
J2
NC/ODT1
L2
NC/CS1
J10
NC/CE1
L10
NCZQ1
A1
NC
A11
NC
T1
NC
T11
NC
100- BALL
SDR AM DDR 3
K4B 1G16 46D- HCF 8_FBGA10 0
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E4
F8
F3
F9
H4
H9
G3
H8
D8
C4
C9
C3
A8
A3
B9
A4
B3
VDD
D10
VDD
G8
VDD
K3
VDD
K9
VDD
N2
VDD
N10
VDD
R2
VDD
R10
VDD
A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
VSS
B4
VSS
E2
VSS
G9
VSS
J3
VSS
J9
VSS
M2
VSS
M10
VSS
P2
VSS
P10
VSS
T2
VSS
T10
VSS
B2
B10
D2
D9
E3
E9
F10
G2
G10
FBA _D21
FBA _D17
FBA _D20
FBA _D16
FBA _D22
FBA _D18
FBA _D23
FBA _D19
FBA _D4
FBA _D1
FBA _D7
FBA _D0
FBA _D5
FBA _D2
FBA _D6
FBA _D3
+1. 5VS
+1. 5VS
3
+VR AM_V REFD
+VR AM_V REFC
U1
M9
VREFCA
H2
VREFDQ
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12
T4
A13
T8
A14
M8
A15/BA3
M3
BA0
N9
BA1
M4
BA2
J8
CK
K8
CK
K10
CKE/CKE0
K2
ODT/ODT0
L3
CS
J4
RAS
K4
CAS
L4
WE
F4
DQSL
C8
DQSU
E8
DML
D4
DMU
G4
DQSL
B8
DQSU
T3
RESET
L9
ZQ/ZQ0
J2
NC/ODT1
L2
NC/CS1
J10
NC/CE1
L10
NCZQ1
A1
NC
A11
NC
T1
NC
T11
NC
100- BALL
SDR AM DDR 3
K4B 1G16 46D- HCF 8_FBGA10 0
X76@
R7
240 _0402_1 %
FBA A0
FBA A1
FBB A2
FBB A3
FBB A4
FBB A5
FBA A6
FBA A7
FBA A8
FBA A9
FBA A10
FBA A11
FBA A12
FBA A13
FBA _BA0
FBA _BA1
FBA _BA2
FBA CLK1
FBA CLK 1#FBA CLK 0#
FBB A_CK E
FBB AODT 0
FBB ACS 0#
FBA RAS#
FBA CAS#
F BAWE #
FBA DQS4
FBA DQS7
FBA DQM4
FBA DQM7
FBA DQS# 4
FBA DQS# 7
FBA _RST
12
DI S@
2
0
FBA CLK1<20>FBA CLK0<20>
FBB A_CK E<2 0>
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
+VR AM_V REFD
+VR AM_V REFC
FBA _D37
E4
FBA _D36
F8
FBA _D35
F3
FBA _D32
F9
FBA _D39
H4
H9
FBA _D38
G3
FBA _D33
H8
FBA _D61
D8
FBA _D57
C4
FBA _D56
C9
FBA _D62
C3
FBA _D58
A8
FBA _D63
A3
FBA _D59
B9
FBA _D60
A4
+1. 5VS
B3
VDD
D10
VDD
G8
VDD
K3
VDD
K9
VDD
N2
VDD
N10
VDD
R2
VDD
R10
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+1. 5VS
A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
B2
B10
D2
D9
E3
E9
F10
G2
G10
FBA A0
FBA A1
4 5
FBB A2
FBB A3
FBB A4
FBB A5
FBA A6
FBA A7
FBA A8
FBA A9
FBA A10
FBA A11
7 6
FBA A12
FBA A13
FBA _BA0
FBA _BA1
FBA _BA2
FBA CLK1
FBA CLK 1#
FBB A_CK E
FBB AODT 0
FBB ACS 0#
FBA RAS#
FBA CAS#
F BAWE #
FBA DQS5
FBA DQS6
FBA DQM5
FBA DQM6
FBA DQS# 5
FBA DQS# 6
FBA _RST
12
R52 3
240 _0402_1 %
DI S@
U2 3
M9
VREFCA
H2
VREFDQ
N4
A0
P8
A1
P4
A2
N3
A3
P9
A4
P3
A5
R9
A6
R3
A7
T9
A8
R4
A9
L8
A10/AP
R8
A11
N8
A12
T4
A13
T8
A14
M8
A15/BA3
M3
BA0
N9
BA1
M4
BA2
J8
CK
K8
CK
K10
CKE/CKE0
K2
ODT/ODT0
L3
CS
J4
RAS
K4
CAS
L4
WE
F4
DQSL
C8
DQSU
E8
DML
D4
DMU
G4
DQSL
B8
DQSU
T3
RESET
L9
ZQ/ZQ0
J2
NC/ODT1
L2
NC/CS1
J10
NC/CE1
L10
NCZQ1
A1
NC
A11
NC
T1
NC
T11
NC
100- BALL
SDR AM DDR 3
K4B 1G16 46D- HCF 8_FBGA10 0
X76@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E4
F8
F3
F9
H4
H9
G3
H8
D8
C4
C9
C3
A8
A3
B9
A4
B3
VDD
D10
VDD
G8
VDD
K3
VDD
K9
VDD
N2
VDD
N10
VDD
R2
VDD
R10
VDD
A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
VSS
B4
VSS
E2
VSS
G9
VSS
J3
VSS
J9
VSS
M2
VSS
M10
VSS
P2
VSS
P10
VSS
T2
VSS
T10
VSS
B2
B10
D2
D9
E3
E9
F10
G2
G10
FBA _D42
FBA _D46
FBA _D40
FBA _D45
FBA _D41
FBA _D47FBA _D34
FBA _D44
FBA _D43
FBA _D50
FBA _D52
FBA _D49
FBA _D53
FBA _D48
FBA _D54
FBA _D51
FBA _D55
1
+1. 5VS
+1. 5VS
+1. 5VS
B B
FBA CLK0
FBA CLK 0#
FBA CLK1
FBA CLK 1#
A A
5
1 2
12
DI S@
243 _0402_1 %
R4 42
R1 4
243 _0402_1 %
DI S@
4
10U _0603_ 6.3V6M
C2 1
DI S@
+1. 5VS
DI S@
1U_ 0402 _6.3V4Z
+1. 5VS
DI S@
1U_ 0402 _6.3V4Z
1
1
C51 8
DI S@
2
2
10U _0603_ 6.3V6M
1U_ 0402 _6.3V4 Z
C50 9
C51 7
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4Z
1U_ 0402 _6.3V4 Z
C5 26
C4 38
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4Z
10U _0603_ 6.3V6M
C44 4
DI S@
1U_ 0402 _6.3V4Z
C5
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4Z
C1 0
1
1
DI S@
DI S@
2
2
1
1
C3
DI S@
2
2
10U _0603_ 6.3V6M
1U_ 0402 _6.3V4Z
C2 0
C48 7
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4 Z
1U_ 0402 _6.3V4Z
C9
C1 8
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4 Z
10U _0603_ 6.3V6M
1
C6
DI S@
DI S@
2
10U _0603_ 6.3V6M
1U_ 0402 _6.3V4Z
C43 7
C47 9
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4 Z
1U_ 0402 _6.3V4Z
1U_ 0402 _6.3V4Z
C1 7
C1 2
1
1
DI S@
DI S@
2
2
1U_ 0402 _6.3V4 Z
1U_ 0402 _6.3V4Z
1
C7
2
1U_ 0402 _6.3V4Z
C44 6
C44 5
C52 5
1
1
DI S@
2
2
+1. 5VS
Issued Date
220 U_B2 _2.5VM_ R35
C43 6
1
+
2
2007/10/15 2008/10/15
1U_ 0402 _6.3V4Z
C1 6
C1 9
C1 1
1
1
DI S@
2
2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1. 5VS
12
R2 0
1.3 3K_040 2_1%
DI S@
R1 9
1.3 3K_040 2_1%
DI S@
R9
1.3 3K_040 2_1%
DI S@
R8
1.3 3K_040 2_1%
DI S@
Compal Secret Data
+VR AM_V REFA + VRAM _VREF B
12M IL 12M IL
12
0.1 U_04 02_10V6 K
1
C2 2
DI S@
2
+1. 5VS +1 .5VS
12
+VR AM_V REFC +V RAM _VREF D
12M IL 12M IL
12
0.1 U_04 02_10V6 K
1
C8
DI S@
2
Deciphered Date
2
R1 1
1.3 3K_040 2_1%
DI S@
R1 0
1.3 3K_040 2_1%
DI S@
R52 9
1.3 3K_040 2_1%
DI S@
R52 2
1.3 3K_040 2_1%
DI S@
+1. 5VS
12
12
0.1 U_04 02_10V6 K
1
C4
DI S@
2
12
12
0.1 U_04 02_10V6 K
1
C49 5
DI S@
2
Title
Size Doc ume nt N umber R ev
C
Dat e: Shee t
Compal Electronics, Inc.
VRAM DDR3
LA-57 52P
1
o f
23 51Thu rsda y, Oct ober 29, 2009
0.3
5
4
3
2
1
C284 0 .1U_040 2_16V7KDIS @
VGA _HDMI_CL K+< 20>
VGA _HDMI_C LK-<20 >
VGA_HDM I_TX0+<20>
VGA_HDM I_TX0-<20 >
VGA_HDM I_TX1+<20>
VGA_HDM I_TX1-<20 >
VGA_HDM I_TX2+<20>
D D
C C
HD MI_CLK +_CON N
HD MI_CL K-_CON N
HDM I_TX0+_CON N
HDM I_TX0-_CO NN
HDM I_TX1+_CON N
HDM I_TX1-_CO NN
HDM I_TX2+_CON N
HDM I_TX2-_CO NN
B B
A A
NEAR CONNECT
HDM I_CLK+_ CK
HD MI_CLK -_CK
HDMI_TX0+ _CK
HDM I_TX0-_CK
HDMI_TX1+ _CK
HDM I_TX1-_CK
HDMI_TX2+ _CK
HDM I_TX2-_CK
HDM I_CLK+_ CK
HD MI_CLK -_CK
HDMI_TX0+ _CK
HDM I_TX0-_CK
HDMI_TX1+ _CK
HDM I_TX1-_CK
HDMI_TX2+ _CK
HDM I_TX2-_CK
1 2
R585 4 99_0402_1%DIS @
1 2
R583 4 99_0402_1%DIS @
1 2
R589 4 99_0402_1%DIS @
1 2
R587 4 99_0402_1%DIS @
1 2
R593 4 99_0402_1%DIS @
1 2
1 2
R597 4 99_0402_1%DIS @
1 2
R595 4 99_0402_1%DIS @
L33
@
1
1
4
4
WCM-2 012-900T_4P
L34
@
1
1
4
4
WCM-2 012-900T_4P
L35
@
1
1
4
4
WCM-2 012-900T_4P
L36
@
1
1
4
4
WCM-2 012-900T_4P
R584 0 _0402_5%H DMI@
1 2
R582 0 _0402_5%H DMI@
1 2
R588 0 _0402_5%H DMI@
1 2
R586 0 _0402_5%H DMI@
1 2
R592 0 _0402_5%H DMI@
1 2
R590 0 _0402_5%H DMI@
1 2
R596 0 _0402_5%H DMI@
1 2
R594 0 _0402_5%H DMI@
1 2
5
2
2
3
3
2
2
3
3
2
2
3
3
2
2
3
3
HD MI_CLK +_CON N
HD MI_CL K-_CON N
HDM I_TX0+_CON N
HDM I_TX0-_CO NN
HDM I_TX1+_CON N
HDM I_TX1-_CO NN
HDM I_TX2+_CON N
HDM I_TX2-_CO NN
HD MI_CLK +_CON N
HD MI_CL K-_CON N
HDM I_TX0+_CON N
HDM I_TX0-_CO NN
HDM I_TX1+_CON N
HDM I_TX1-_CO NN
HDM I_TX2+_CON N
HDM I_TX2-_CO NN
13
D
G
DIS @
S
Q41
2N7 002W-T/R7 _SOT323-3
VGA_HDM I_TX2-<20 >
VGA _HDMI_S DA<2 0>
VGA _HDMI_S CL<20>
2
+3VS
HDM I_DET_UMA< 25>
HDM I_DETECT _VGA<19>
HDM I_DET_UMA
HDM I_DETECT _VGA
4
1 2
C283 0 .1U_040 2_16V7KDIS @
1 2
C282 0 .1U_040 2_16V7KDIS @
1 2
C281 0 .1U_040 2_16V7KDIS @
1 2
C601 0 .1U_040 2_16V7KDIS @
1 2
C600 0 .1U_040 2_16V7KDIS @
1 2
C614 0 .1U_040 2_16V7KDIS @
1 2
C599 0 .1U_040 2_16V7KDIS @
1 2
L15 M BK1608 121YZF_06 03DI S@
1 2
1 2
L16 M BK1608 121YZF_06 03DI S@
@
D22
RB7 51V_SOD32 3
2 1
HD MIDAT_ R
HD MICLK _R
1
1
C302
C295
DIS @
DIS @
2
12P_040 2_50V8J
2
R579
10K_040 2_1%
1 2
DIS @
R578
100K_04 02_5%
DIS @
1 2
12P_040 2_50V8J
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HDM I_CLK+_ CK
HD MI_CLK -_CK
HDMI_TX0+ _CK
HDM I_TX0-_CK
HDMI_TX1+ _CK
HDM I_TX1-_CK
HDMI_TX2+ _CK
HDM I_TX2-_CK
DIS @
1 2
L30M BK1608 121YZF_06 03
DIS @
C603
330P_04 02_50V7K
+5VS + 5VS
3
HD MIDAT_ R
1
@
2
D24
BAT54S-7 -F_SOT23-3
2008/03/25 2008/04/
3
Compal Secret Data
HDM I_CLK+_ CK<25>
HD MI_CLK- _CK<25 >
HDMI_TX0+ _CK<25>
HDM I_TX0-_CK<25>
HDMI_TX1+ _CK<25>
HDM I_TX1-_CK<25>
HDMI_TX2+ _CK<25>
HDM I_TX2-_CK<25>
+5VS
3
1
3
2
Deciphered Date
2
@
D23
BAT54S-7 -F_SOT23-3
HD MIDAT_R<25 >
HD MICLK_ R< 25>
1
@
D25
BAT54S-7 -F_SOT23-3
HD MICLK _R
HDM I_CLK+_ CK
HD MI_CLK -_CK
HDMI_TX0+ _CK
HDM I_TX0-_CK
HDMI_TX1+ _CK
HDM I_TX1-_CK
HDMI_TX2+ _CK
HDM I_TX2-_CK
R581
0_0805_ 5%
R249
2.2K_ 0402_5%
HD MI@
HD MIDAT_ R
HD MICLK _R
2
@R591 4 99_0402_1%DIS @
1 2
+5VS
21
HD MI@
D28
RB4 91D_SC 59-3
+5V S_HDMI
C627
1
0.1U _0402_16 V4Z
HD MI@
R257
2.2K_ 0402_5%
HD MI@
1 2
HD MI_CL K-_CON N
HD MI_CLK +_CON N
HDM I_TX0-_CO NN
HDM I_TX0+_CON N
HDM I_TX1-_CO NN
HDM I_TX1+_CON N
HDM I_TX2-_CO NN
HDM I_TX2+_CON N
Title
Size Doc umen t Numb er R ev
Cu stom
Da te: Sh eet o f
2
JH DMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
TAIT W_PD VBR9-1 9FLBS4NN4N1
ME@
Compal Electronics,Ltd.
HDMI CONN
LA-5752P
1
GND
GND
GND
GND
20
21
22
23
0.3
24 51Th ursd ay, Octob er 29, 2 009
5
P/N:SA00003GT00 (ASM1442)
4
3
2
1
P/N:SA00002D700 (8101T)
P/N:SA00001U900 (CH7318A)
FOR asmedia
R428 STUFF
RESERVE THE R668 PULL UP TO 3VS
D D
RESERVE THE R670 PULL DOWN TO GND
FOR 7318C PIN6 PULL DOWN 1.2Kohm
PIN7 PULL DOWN 7.5Kohm
PIN7 PULL UP 20Kohm
CHANGE R483 FROM 499 TO 3.4K OHM
+3VS
12
@
R231
0_0402_ 5%
+3VS
12
R24 2
4.7K _0402_5%
UMA _HDMI@
C C
B B
12
@
R243
0_0402_ 5%
12
UMA _HDMI@
R230
0_0402_ 5%
+3VS
TMDS_B_ CLK<15>
TMDS_B_ CLK#<15>
TMDS_B_ DATA0<15>
TMDS_B_ DATA0#<15>
TMDS_B_ DATA1<15>
TMDS_B_ DATA1#<15>
TMDS_B_ DATA2<15>
TMDS_B_ DATA2#<15>
HDM I_DET_UMA<2 4>
R254
R255
HD MICLK_ R< 24>
HD MIDAT_R<24 >
1 2
1 2
4.7K _0402_5%
4.7K_ 0402_5%
4.7K_ 0402_5%
R24 4
@
HD MICLK _R
HD MIDAT_ R
HDM I_DET_UMA
@
@
1 2
R25 6
4.7K _0402_5%
@
1 2
U12
25
OE#
28
SCL_SINK
29
SDA_SINK
30
HPD_SINK
32
DDC_EN
34
CFG0
35
CFG1
inte rnal p ull d own
48
IN_D4+
47
IN_D4-
45
IN_D3+
44
IN_D3-
42
IN_D2+
41
IN_D2-
39
IN_D1+
38
IN_D1-
ASM1442 _QFN48_7X7
UMA _HDMI@
output
input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PC1
PC0
REXT
HPD#
SDA
SCL
RT_EN#
OUT_D4+
OUT_D4-
OUT_D3+
OUT_D3-
OUT_D2+
OUT_D2-
OUT_D1+
OUT_D1-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PAD
+3VS
2
11
1
15
21
26
33
40
46
4
3
inte rnal p ull d own
6
7
8
9
10
13
14
16
17
19
20
22
23
1
5
12
18
24
27
31
36
37
43
49
UMA _HDMI@
C280
0.1U _0402_16 V4Z
2
4.7K_ 0402_5%
R247
@
1 2
R246 4.7K_0402 _5%@
1 2
R248 4.7K_0402 _5%@
1 2
R245 3.4K_ 0402_1%UM A_HDM I@
1 2
TMD S_B_HPD#
R232 4.7K_ 0402_5%@
HDM I_CLK+_ CK
HD MI_CLK -_CK
HDMI_TX0+ _CK
HDM I_TX0-_CK
HDMI_TX1+ _CK
HDM I_TX1-_CK
HDMI_TX2+ _CK
HDM I_TX2-_CK
1 2
1
UMA _HDMI@
C602
0.1U _0402_16 V4Z
2
TMD S_B_HPD# <15>
HDM I_CLK+_ CK < 24>
HDM I_CLK-_ CK <24>
HDMI_TX0+ _CK <24>
HDM I_TX0-_CK <24>
HDMI_TX1+ _CK <24>
HDM I_TX1-_CK <24>
HDMI_TX2+ _CK <24>
HDM I_TX2-_CK <24>
1
2
+3VS
+3VS
UMA _HDMI@
C604
0.1U _0402_16 V4Z
HDM IDAT_N B <15>
HD MICLK_ NB < 15>
1
UMA _HDMI@
C285
10U _0805_10V4 Z
2
TMD S_B_HPD#
+3VS
12
12
R253
20K_040 2_1%
@
R252
7.5K_ 0402_1%
@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/03/25 2008/04/
3
Compal Secret Data
Deciphered Date
Compal Electronics,Ltd.
Title
Level Shiftter_ASM1442
Size Doc umen t Numb er R ev
Cu stom
2
Da te: Sh eet o f
LA-5752P
25 51Th ursd ay, Octob er 29, 2 009
1
0.3
A
B
+5VS +5VS +5VS +5VS +5VS
3
2
@
D1
BAT54S-7 -F_SOT23-3
C
3
1
2
1
@
D2
BAT54S-7 -F_SOT23-3
3
2
BAT54S-7 -F_SOT23-3
@
D3
D
3
R EDGREE NBLU E
1
2
1
@
D27
BAT54S-7 -F_SOT23-3
3
2
@
D26
BAT54S-7 -F_SOT23-3
E
JVG A_VSJV GA_HS
1
1 1
2 2
3 3
DA C_RED<15 >
DA C_GRN<15>
DAC _BLU<15>
VGA _CRT_R<19>
VGA _CRT_G<1 9>
VGA _CRT_B<19>
DA C_RE D
DA C_GR N
VGA _CRT_R
VGA _CRT_G
1 2
R92 0_040 2_5%UMA@
1 2
R91 0_040 2_5%UMA@
1 2
R93 0_040 2_5%UMA@
1 2
R66 0_040 2_5%DIS@
1 2
R65 0_040 2_5%DIS@
1 2
R67 0_040 2_5%DIS@
CR T_R
CRT _G
CRT _BDA C_BLU
CR T_R
CRT _G
CRT _BVGA _CRT_B
+3VS
UMA only
DIS only
+3VS
CR T_R
CRT _G
CRT _B
12
R153
150_040 2_1%
+CR T_VCC
12
R131
150_040 2_1%
CLOSE TO CONN
CR T_HS YNC<15>
VG A_HS YNC<19>
CR T_VS YNC<15>
VG A_VSYN C<19>
12
R90
150_040 2_1%
R94 0_0 402_5%UMA@
1 2
R68 0_0 402_5%DIS @
1 2
R95 0_0 402_5%UMA@
1 2
R69 0_0 402_5%DIS @
1 2
1
C158
2
10P_040 2_50V8J
1
1
C146
2
2
10P_040 2_50V8J
C61 9
0.1U _0402_ 16V4Z
HS YNC _G
C62 0
0.1U _0402_ 16V4Z
VS YNC_G
FCM 1608CF -121T03 0603
1 2
L11
FCM 1608CF -121T03 0603
1 2
L10
FCM 1608CF -121T03 0603
1 2
L9
C137
10P_040 2_50V8J
1
2
1
2
1
2
10P_040 2_50V8J
+CR T_VCC
1 2
1
5
P
OE#
A2Y
G
U26
SN7 4AHCT1 G125D CKR_SC70-5
3
+CR T_VCC
1 2
1
5
P
OE#
A2Y
G
U25
SN7 4AHCT1 G125D CKR_SC70-5
3
C157
R575
1K_0402 _5%
4
R580
1K_0402 _5%
4
R ED
GR EEN
BLU E
1
1
C145
C136
2
10P_040 2_50V8J
2
10P_040 2_50V8J
CR T_HS YNC_1
CR T_VS YNC_1 JVG A_VS
+5VS
RB4 91D_SC 59-3
R ED
CR T_DDC _DAT_ CONN
GR EEN
JVG A_HS
BLU E
JVG A_VS
CR T_DD C_CLK _CONN
+CR T_VCC
D21
2 1
1.1A _6V_SMD1812 P110TF
W=40mils
1
2
<BO M Structure>
1 2
L32 FCM16 08CF-121 T03 0603
1 2
L31 FCM16 08CF-121 T03 0603
CRT Connector
F1
21
C628
100P_04 02_50V8J
11
12
13
14
10
15
1
@
C626
10P_040 2_50V8J
2
1
C625
@
10P_040 2_50V8J
2
1
C62 9
0.1U _0402_ 16V4Z
2
JCR T1
6
1
7
2
8
3
9
G
4
G
5
TYCO_ 1775763 -1
ME@
JVG A_HS
16
17
12
12
R159
2.2K_ 0402_5%
CRT _DDC_D ATA<15>
VGA _DDCDAT A<19>
CR T_DDC _CLK< 15>
VGA _DDCC LK<1 9>
4 4
CRT _DDC_D ATA
VGA _DDCDA TA
CR T_DDC _CLK
VG A_DDC CLK
A
UMA@
R96 0 _0402_5%
DIS @
R70 0 _0402_5%
UMA@
R97 0_040 2_5%
DIS @
R71 0 _0402_5%
CRT _DDC_D ATA_R
12
12
CR T_DDC _CLK_ R
12
12
12
R162
2.2K_ 0402_5%
Q13A
2N7 002DW -T/R7_SOT363-6
B
5
2.2K_ 0402_5%
3
4
Q13B
2
2N7 002DW -T/R7_SOT363-6
61
12
R157
100P_04 02_50V8J
R158
2.2K_ 0402_5%
CR T_DDC _DAT_ CONN
CR T_DD C_CLK _CONN
1
1
@
2
Issued Date
@
C177
68P_040 2_50V8K
2
2007/10/15 2008/10/15
C
Compal Secret Data
Deciphered Date
C178
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size Doc umen t Numb er R ev
Cu stom
D
Da te: Sh eet o f
Compal Electronics, Inc.
CRT Connector
LA-5752P
26 51Th ursday, Octobe r 29, 20 09
E
0.3
5
D D
LCD POWER CIRCUIT
+LCDVD D
13
D
Q3
2N7002_SOT23
PCH_E NVDD<15>
VGA_ENVD D_R<19>
C C
PCH_PWM<15>
B B
R35 0_0402_5%
R36 0_0402_5%
2N7002_SOT23
12
UMA@
12
DIS@
G
2
INVPWM
13
D
S
Q12
@
S
LCD_E NVDD
R37
100K_0402_5%
+3VS
UMA@
5NC1
U6
P
A2Y
G
NC7SZ14P5X_NL_SC70-5
3
@
R160
1 2
0_0402_5%
10K_0402_5% @
R13
150_0603_1%
2
G
DTC12 4EK
2
12
@
PCH_PWM_R
4
R156
+5VALW
12
1
IN
3
12
4
R31
100K_0402_5%
R38 220K_0402_5%
1 2
OUT
GND
Q5
DTC124EKAT146_SC59-3
UMA@
R161
1 2
0_0402_5%
For GMCH DPST
1
2
INVPWM
2
C34
0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
+3VS
G
+3VS
1 3
470P_0402_50V7K
1
S
2
D
AO3413_SOT23-3
Q4
+LCDV DD
INVPWM
C15
@
1
2
470P_0402_50V7K
For EMI
W=60mils
C539
4.7U_0805_10V4Z
L2
1 2
4.7U_0805_10V4Z
DAC_B RIG
@
1
C13
2
W=60mils
+LCDV DD_CONN
C33
1
2
470P_0402_50V7K
1
2
DISPOF F#
3
@
C296
1
C25
0.1U_0402_16V4Z
2
+3VS
680P_0402_50V7K
C14
CONN_ LVDS_SCL
CONN_ LVDS_SDA
@
2.2K_0402_5%
1
2
+LCDV DD_CONN
LCD_C OLOR_1
INVT_PWM<34>
DAC_B RIG<34>
R392
@
VGA_ENBKL_R<19>
+3VS
PCH_ENBK L<15>
R395
2.2K_0402_5%
@
BKOFF#<34>
2
+LEDVDD B+
(60 MIL)
R17
1 2
0_0402_5% DIS@
D12
BKOFF#
CH751H-40PT_S OD323-2
R261 0_0402_5%DIS@
1 2
UMA@
R260 0_0402_5%
1 2
INVPWM
DISPOF F#
+3VS
12
R250
4.7K_0402_5%
21
100K_0402_1%
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
ACES_87142-3041
DISPOF F#
R259
1
R549 0_0805_5%
1 2
R550 0_0805_5%
1 2
1
1
C567
680P_0402_50V7K
@
JLVDS1
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
GND31GND
ME@
1 2
+CMOS_PW
USB20_N2
USB20_P2
CONN_ LVDS_A0#
CONN_ LVDS_A0
CONN_ LVDS_A1#
CONN_ LVDS_A1
CONN_ LVDS_A2#
CONN_ LVDS_A2
CONN_ LVDS_ACLK#
CONN_ LVDS_ACLK
ENBKL <34>
2
C566
4.7U_0805_25V6-K
2
USB20_N2 <16>
USB20_P2 <16>
CMOS
CMOS Camera
2
2
+5VS
CMOS@
IN
Q24 AO3413_SOT23-3
12
R270
10K_0402_5%
CMOS1
1
OUT
GND
Q21
CMOS@
DTC124EKAT146_SC59-3
3
D
S
13
CMOS@
G
2
C326
0.01U_0402_16V7K
1 2
CMOS@
Title
Size Doc ument Number Re v
B
Date: Sheet of
Compal Electronics, Inc.
LVDS/CAMERA
12
R280
0_0603_5%
CMOS@
1
C337
10U_0805_10V4Z
2
LA-5752P
1
CMOS@
1
C275
0.1U_0402_16V4Z
2
CMOS@
+CMOS_PW
27 51Th ursday, October 2 9, 2009
0.3
VGA_LVDS_SCL<19>
VGA_LVDS_SDA<19>
VGA_LVDS_A0<20>
VGA_LVDS_A0#<20>
VGA_LVDS_A1<20>
VGA_LVDS_A1#<20>
VGA_LVDS_A2<20>
VGA_LVDS_A2#<20>
VGA_LVDS_ACLK<20>
VGA_LVDS_ACLK#<20>
EDID_ CLK<15>
A A
EDID_DATA<15>
LVDS_A0<15>
LVDS_A0#<15>
LVDS_A1<15>
LVDS_A1#<15>
LVDS_A2<15>
LVDS_A2#<15>
LVDS_ACLK<15>
LVDS_ACLK#<15>
VGA_LVDS_SCL
VGA_LVDS_SDA
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
EDID_ CLK
EDID_DA TA CONN_LVDS_SDA
LVDS_A0
LVDS_A0#
LVDS_A1
LVDS_A1#
LVDS_A2
LVDS_A2#
LVDS_ACLK
LVDS_ACLK#
5
R3900_0402_5% DIS@
12
R3910_0402_5% DIS@
12
R860_0402_5% DIS@
12
R850_0402_5% DIS@
12
R1500_0402_5% DIS@
12
R1280_0402_5% DIS@
12
R1260_0402_5% DIS@
12
R1270_0402_5% DIS@
12
R840_0402_5% DIS@
12
R1250_0402_5% DIS@
12
R3930_0402_5% UMA@
12
R3940_0402_5% UMA@
12
R3830_0402_5% UMA@
12
R3820_0402_5% UMA@
12
R3890_0402_5% UMA@
12
R3880_0402_5% UMA@
12
R3860_0402_5% UMA@
12
R3870_0402_5% UMA@
12
R3840_0402_5% UMA@
12
R3850_0402_5% UMA@
12
CONN_ LVDS_SCL
CONN_ LVDS_SDA
CONN_ LVDS_A0
CONN_ LVDS_A0#
CONN_ LVDS_A1
CONN_ LVDS_A1#
CONN_ LVDS_A2
CONN_ LVDS_A2#
CONN_ LVDS_ACLK
CONN_ LVDS_ACLK#
CONN_ LVDS_SCL
CONN_ LVDS_A0
CONN_ LVDS_A0#
CONN_ LVDS_A1
CONN_ LVDS_A1#
CONN_ LVDS_A2
CONN_ LVDS_A2#
CONN_ LVDS_ACLK
CONN_ LVDS_ACLK#
CMOS_OFF#<34>
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
A
Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card for WWAN(Full)
Mini-Express Card(WLAN/WiMAX)
JP1 0
1
WAKE#
3
NC
5
NC
7
CLKREQ#
9
GND
11
REFCLK-
13
REFCLK+
15
GND
17
NC
19
NC
21
GND
23
PERn0
25
PERp0
27
GND
29
GND
31
PETn0
33
PETp0
35
GND
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
NC
53
GND
TAI TW_ PFPE T0-AFG LBG1ZZ4 N0
ME@
PCI E_PRX_ DTX_N2< 14>
PCI E_PRX_D TX_P2<14>
PCI E_PTX _C_DRX _N2< 14>
PCI E_PTX_ C_DRX_P 2<14>
CLK _PCI E_W LAN1#<14>
CLK _PCI E_W LAN1<14>
PCI E_W AKE#
BT _ACTIVE
WLA N_CL KRE Q1#
EC_T X_P80_D ATA
EC_ RX_ P80_CLK
R33 3 0 _0402 _5%@
1 2
PCI _RS T#_R
CLK _PCI _DB
+3VS
100 _0402_1 %
R27 4
1 2
1 2
R27 3
100 _0402_1 %
PCI E_W AKE#<15>
BT_A CTIVE<37>
1 1
WLA N_CL KRE Q1#<14>
EC_T X_P80_DA TA<34, 35>
EC_ RX_P 80_CLK<34,35 >
PERST#
+3.3Vaux
+1.5V
SMB_CLK
SMB_DATA
USB_D-
USB_D+
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
+3.3V
B
+1. 5VS
+3V ALW
1
J4
1
JUMP _43X79
1
@
2
+3VS
2
3.3V
4
GND
6
1.5V
8
NC
10
NC
12
NC
14
NC
16
NC
18
GND
20
NC
22
24
26
GND
28
30
32
34
GND
36
38
40
GND
42
44
46
48
50
GND
52
54
GND
2
R3 77 0 _040 2_5%
R3 76 0 _040 2_5%@
R3 75 0 _040 2_5%
R3 74 0 _040 2_5%@
R3 73 0 _040 2_5%@
2Watt
1 2
1 2
1 2
1 2
1 2
R37 2300_04 02_5% @
12
R37 1300_04 02_5%
12
C4 22
0.1 U_04 02_16V 4Z
2
LPC _FR AME#_ R
LPC _AD3 _R
LPC _AD2 _R
LPC _AD1 _R
LPC _AD0 _R
USB 20_N 8 <16>
USB 20_P8 <16>
WLA N_LE D#
WL _OFF # <34>
BUF _PLT_R ST# <5 ,16,1 9,29>
+3V ALW
+3VS
SMB _CLK_S 3 < 10,11 ,12,14>
SMB_ DATA_S3 <10, 11,12, 14>
WLA N_LE D# <36>
C
Reserve f or SW mi ni-pcie debug card.
Series resistors closed to KBC side.
LPC _FR AME#_ R
LPC _AD3 _R
LPC _AD2 _R
LPC _AD1 _R
LPC _AD0 _R
PCI _RS T#_R
CLK _PCI _DB
R28 4 0 _0402 _5%@
1 2
R28 5 0 _0402 _5%@
1 2
R28 6 0 _0402 _5%@
1 2
R28 7 0 _0402 _5%@
1 2
R28 8 0 _0402 _5%@
1 2
R29 0 0 _0402 _5%@
1 2
LPC _FR AME#
LPC _AD3
LPC _AD2
LPC _AD1
LPC _AD0
PCI _RS T#
D
LPC _FR AME# <13 ,34>
LPC _AD3 < 13,34>
LPC _AD2 < 13,34>
LPC _AD1 < 13,34>
LPC _AD0 < 13,34>
PCI _RST# <16,34 >
CLK _PCI _DB <1 4>
E
2 2
CLK _PCI E_C ARD_ PCH #<14>
CL K_PC IE_ CARD _PC H<14>
EC_T X_P80_D ATA
EC_ RX_ P80_CLK
PCI E_W AKE#
BT _ACTIVE
PCI ECL KREQ 3#
PCI E_PRX_ DTX_N4< 14>
PCI E_PRX_D TX_P4<14>
PCI E_PTX _C_DRX _N4< 14>
PCI E_PTX_ C_DRX_P 4<14>
+1. 5VS
1
C35 8
0.1 U_04 02_16V4 Z
2
+3VS
1
C38 6
0.1 U_04 02_16V4 Z
2
+3V ALW
1
C37 2
0.1 U_04 02_16V4 Z
2
PCI E_W AKE#<15>
BT_A CTIVE<37>
PCI ECL KREQ 3#<14>
Vcc 3.3V +/- 8%
Peak Ic c 2750mA
with max supply droop 50mA
Average I cc 1000mA
EC_T X_P80_DA TA<34, 35>
EC_ RX_P 80_CLK<34,3 5>
3 3
4 4
Mini-Express Card(WWAN 3G)
JP 9
1
R37 0 0 _0402 _5%@
100 _0402_1 %
R36 4
1 2
1 2
R36 3
100 _0402_1 %
1 2
3G@
3G@
+3VS
WAKE#
3
NC
5
NC
7
CLKREQ#
9
GND
11
REFCLK-
13
REFCLK+
15
GND
17
NC
19
NC
21
GND
23
PERn0
25
PERp0
27
GND
29
GND
31
PETn0
33
PETp0
35
GND
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
NC
53
GND
TAI TW_ PFPE T0-AFG LBG1ZZ4 N0
ME@
Express Card Power Switch
+3V ALW
BUF _PLT_ RST#< 5,16, 19,29>
SY SON<3 4,39,44 >
SUS P#<16 ,34,3 9,42,44 ,46>
R3 34 1 00K_ 0402_5%@
+3V ALW
1 2
CPU SB#<1 6>
+3.3Vaux
SMB_CLK
SMB_DATA
LED_WWAN#
LED_WLAN#
LED_WPAN#
+3VS
GND
GND
PERST#
GND
+1.5V
GND
USB_D-
USB_D+
GND
+1.5V
GND
+3.3V
GND
+1. 5VS
SY SON
SUS P#
C PUSB #
3.3V
1.5V
NC
NC
NC
NC
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
12
14
2
4
6
20
1
10
9
18
+3VS
+1. 5VS
+UI M_P WR
UIM _DATA
UIM _CL K
UIM _RST
UIM _VPP
USB 20_ N13
USB 20_P1 3
U1 5
1.5Vin
1.5Vin
3.3Vin
3.3Vin
AUX_IN17AUX_OUT
SYSRST#
SHDN#
STBY#
CPPE#
CPUSB#
RCLKEN
G57 7BSR 91U_ QFN20
+3VS
2Watt
R3 68 0 _040 2_5%3 G@
1 2
R3 67 0_ 0402_5 %@
1 2
R3 69 0 _040 2_5%@
1 2
R3 66 0 _040 2_5%@
1 2
R3 65 0 _040 2_5%@
1 2
USB 20_N 13 <16>
USB 20_P13 <16>
+1. 5VS_ CARD 1
11
1.5Vout
13
1.5Vout
+3V S_CA RD1
3
3.3Vout
5
3.3Vout
15
19
OC#
8
PERST#
16
NC
7
GND
1
C41 8
10U _080 5_10V4Z
2
+3V ALW_ CARD 1
PER ST#
1
@
C42 0
10U _0805 _10V4Z
2
+3V ALW
+3VS
SMB _CLK_S 3 <10 ,11,12, 14>
SMB _DATA_S 3 < 10,1 1,12,14 >
+1. 5VS
1
C4 17
0.1 U_04 02_16V 4Z
2
40mil
60mil
40mil
3G_ OFF# <34>
BUF _PLT_R ST# <5 ,16,1 9,29>
1
C41 9
0.1 U_04 02_16V4 Z
2
+1. 5VS_ CARD1
Imax = 0.75A
1
C36 0
10U _080 5_10V4Z
2
+3V S_CA RD1
Imax = 1.35A
1
C38 8
10U _080 5_10V4Z
2
+3V ALW_ CARD 1
Imax = 0.275A
1
@
C35 6
10U _080 5_10V4Z
2
1
C35 9
0.1 U_04 02_16V4 Z
2
1
C38 7
0.1 U_04 02_16V4 Z
2
1
C35 7
0.1 U_04 02_16V4 Z
2
D4
@
UIM _VPP
UIM _DATA
+UI M_P WR
JP 2
4
GND
5
VPP
6
I/O
7
DET
12
R15 1
10K _0402_5 %
TAI TW_P MPAT6-0 6GLBS7N1 4N0
ME@
CM1 293-04S O_SOT23- 6
1
CH1
2
Vn
3
CH2
4
CH4
5
Vp
6
CH3
1
VCC
2
RST
3
CLK
8
GND
9
GND
New Card 34mm Socket (Left/TOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCI E_W AKE#<15>
CLK _PCI E_EXP _PCH#< 14>
CLK _PCI E_EXP _PCH<14>
PCI E_PRX_D TX_N5< 14>
PCI E_PRX_D TX_P5<14>
PCI E_PTX _C_DRX _N5< 14>
PCI E_PTX_ C_DRX_P 5<14>
USB 20_N 10<16>
USB 20_P10< 16>
CP USB#<16>
SMB _CLK_S 3<10, 11,12, 14>
SMB _DATA_S 3<10,11 ,12,14>
+1. 5VS_ CARD1
+3V ALW_ CARD 1
+3V S_CA RD1
CLK REQ_E XP#<14>
USB 20_ N10
USB 20_P1 0
C PUSB #
PER ST#
C PUSB #
+3VS
+UI M_P WR
UIM _RST
UIM _CL K
JEXP1
GND
USB_DÂUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKÂREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
SANT A_130801 -5_LT
ME@
40mil
1
2
@
10K _0402_ 5%
1
C18 8
2
4.7 U_08 05_10V 4Z
+UI M_P WRUIM _DATA
12
R15 2
DAN 217T 146_SC 59-3
1
D5
@
C17 6
0.1 U_04 02_16V4 Z
+3VS
3
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1 0/15 2008/ 10/15
Compal Secret Data
Deciphered Date
D
Compal Electronics, Inc.
Title
Mini-C ard/Nwe Card/SIM
Size Doc ume nt N umber R ev
Dat e: Shee t
LA-5752P
E
o f
28 51Thu rsda y, Oct ober 29, 2009
0. 3
A
4 4
Place Close to Chip
+3V_LAN
1
2
C593 0.1U_0402_16V7K
C594 0.1U_0402_16V7K
CLK_P CIE_LAN<14>
CLK_P CIE_LAN#<14>
BUF_PLT_RST#<5,16,19,28>
R171 2.49K_0402_1%
12
R206 10K_0402_5%
@
Y3
1 2
25MHZ_20P
C612
30P_0402_50V8J
PCIE_PRX_DTX_P3<14>
PCIE_PRX_DTX_N3<14>
PCIE_PTX_C_DRX_P3<14 >
PCIE_PTX_C_DRX_N3<14>
CLKREQ_LAN#<14>
LAN_WAKE#<34>
3 3
+3VS
12
R204
1K_0402_5%
ISOLATEB
R205
15K_0402_5%
1 2
LAN_XTALOLAN_XTALI
B
LAN_D I
LAN_CS
PCIE_IRX_C_PTX_P3
PCIE_IRX_C_PTX_N3
ISOLATEB
LAN_XTALI
LAN_XTALO
1
C611
30P_0402_50V8J
2
1 2
R182 3.6K_0402_5%
100@
1 2
R203 1K_0402_5%
U24
20
HSOP
21
HSON
15
HSIP
16
HSIN
17
REFCLK_P
18
REFCLK_N
25
CLKREQB
27
PERSTB
46
RSET
26
LANWAKEB
28
ISOLATEB
41
CKTAL1
42
CKTAL2
23
GPO
24
NC
7
GND
14
GND
31
GND
47
GND
22
EGND
RTL8111DL-VB-GR_LQFP48_7X7
GIGA@
RTL8111 DL
U24
RTL8103EL-VB-GR
100@
+3V_LAN
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
LED0
MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
FB12
SROUT12
EVDD12
DVDD12
DVDD12
DVDD12
AVDD12
AVDD12
VDDSR
VDDSR
VDD33
VDD33
AVDD33
AVDD33
ENSR
33
34
35
32
38
2
3
5
6
8
9
11
12
4
48
19
30
36
13
10
39
44
45
29
37
1
40
43
C
LAN_D I
LAN_SK#
LAN_CS
ACTIV ITY#
MDI0+
MDI0ÂMDI1+
MDI1ÂMDI2+
MDI2ÂMDI3+
MDI3-
VCTRL12
2
C242
0.1U_0402_16V4Z
1
GIGA@
R177
R181
LAN_SK# <30>
ACTIV ITY# <30>
MDI0+ <30>
MDI0- <30>
MDI1+ <30>
MDI1- <30>
MDI2+ <30>
MDI2- <30>
MDI3+ <30>
MDI3- <30>
12
0_0402_5%GIGA@
0.1U_0402_16V4Z
12
0_0402_5%GIGA@
GIGA@
+3V_LAN
+LAN_VDD12
+EVDD12
+LAN_VDD12
C243
12
+3V_LAN
R180
0_0402_5%
GIGA@
1 2
R179
0_0402_5%
@
1 2
D
R576
1 2
0_0603_5%GIGA@
R577
1 2
1
1
2
0.1U_0402_16V4Z
For RTL8111DL pin43:
pull hi if switching regulator is enable.
pull low if external power 1.2Vis used.
For RTL8103EL is NC.
C245
2
22U_0805_6.3V6M
C244
GIGA@
Close to pin.
0_0603_5%100@
40 mil width
+3V_LAN
+LAN_VDD12
E
Close to 8111DL pins--1,29,37
+3V_LAN
0.1U_0402_16V4Z
2
2
C597
C613
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C246
1
2 2
60 mil width
VCTRL12
GIGA@
S INDU C_ 4.7UH +-20% SIA4012-4R7M
60 mil width
J1
@
JOPEN
12
R219
33K_0402_5%
+3VALW
2
C267
0.1U_0402_16V4Z
1
+5VALW
12
1 1
13
EN_WOL#<34>
EN_WOL#
2N7002_SOT23-3
D
2
G
Q18
S
A
D
1 3
2
S
Q17
AO3414_SOT23-3
G
La yout No tic e : Pl ace a s clos e
ch ip as p oss ible .
+3V_LAN
C261
4.7U_0805_10V4Z
B
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
The trace length L69 to 8111DL's pin<200mils.
L69 to C934/C941<200mils.
L12
1 2
R170
1 2
0_0603_5%100@
2006/08/04 2006/10/06
Compal Secret Data
1
C238
2
22U_0805_6.3V6M
Deciphered Date
1
C239
2
0.1U_0402_16V4Z
D
R173
1 2
R172
1 2
0_0603_5%GIGA@
0_0603_5%GIGA@
Close to U44 pin19
1U_0603_10V4Z
2
C251
1
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
2
1
C247
C250
1U_0603_10V4Z
2
C248
1
0.1U_0402_16V4Z
+EVDD12
2
C260
0.1U_0402_16V4Z
1
+LAN_VDD12
2
C259
1
Close to U44 pin10,13,30,36
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
RTL8103EL
Thursday, October 29, 2009
LA-5752P
E
29 51
0.3
5
Clos e to T14
4
3
2
1
GIGA@
C133 0.0 1U_0402_ 16V7K
D D
C C
12
GIGA@
C132 0.0 1U_0402_ 16V7K
12
C131 0.0 1U_0402_ 16V7K
12
C130 0.0 1U_0402_ 16V7K
12
MDI3+<29 >
MDI3 -<29>
MDI2+<29 >
MDI2 -<29>
MDI1+<29 >
MDI1 -<29>
MDI0+<29 >
MDI3+
MD I3-
MDI2+
MD I2-
MDI1+
MD I1-
MDI0+
Place close to TCT pin
MDI0 -<29>
MD I0- MDO0-
1
2
3
4
5
6
7
8
9
10
11
12
T16
TCT1
TD1+
TD1-
TCT2
TD2+
TD2-
TCT3
TD3+
TD3-
TCT4
TD4+
TD4-
LG- 2446S
GIGA@
T16
1:1
1:1
1:1
1:1
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
MDO3+
23
MDO3-
22
MCT2
21
MDO2+
20
MDO2-
19
MCT1
18
MDO1+
17
MDO1-
16
MCT0
15
MDO0+
14
13
MCT3
24
R55 75_0402_ 5%GIGA @
R54 75_0402_ 5%GIGA @
R53 75_0402_5%
R52 75_0402_ 5%
12
12
12
12
1000P_1 206_2KV7K
C128
1
2
RJ45 Conn.
HH-0 65
100@
B B
AC TIVITY#<29>
AC TIVITY#
1
C249
68P_040 2_50V8K
@
2
LAN _SK#<2 9>
LAN _SK#
R178 3 00_0402_5%
+3V_LAN
C70
@
470P_04 02_50V7K
12
For EMI.
R574 3 00_0402_5%
1
C60 9
68P_040 2_50V8K
2
@
12
MDO3-
MDO3+
MDO1-
MDO2-
MDO2+
MDO1+
MDO0-
MDO0+
12
+3V_LAN
JR J45
12
Amber LED-
11
Amber LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
FOX _JM36113-P222 1-7F
ME@
SHLD4
SHLD3
SHLD2
SHLD1
16
15
14
13
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/03/20 2010/03/20
3
Compal Secret Data
Deciphered Date
Title
Size Doc umen t Numb er R ev
Cu stom
2
Da te: Sh eet o f
Compal Electronics, Inc.
LAN_Transformer
LA-5752P
1
0.3
30 51Th ursday, Octobe r 29, 20 09
R430
5
1403@
4
3
2
1
1403:
0_0402_5%
D D
12
2103@
R43 0
68_0402 _5%
V DD
2
C44 3
0.1U _0402_16 V4Z
1
12
2103@
R45 9
6.8K _0402_5%
SMB _EC_CK2_R<14,19 >
2103@
R46 0
10K_040 2_5%
SMB _EC_CK2_R
12
10K_040 2_5%
SH DN_SEL
2103@
R462
FAN _PWM
12
R440
10K_040 2_5%
@
REMOTE2 -
12
FAN_PWM & TACH
for PWM FAN
C C
SMSC thermal sensor
placed near by VRAM
U20
2103@
1
DN1
3
VDD
5
GPIO2
7
SYS_SHDN#
9
SMCLK
11
PWM
13
SHDN_SEL
DN2 / DP315DP2 / DN3
EMC 2103-2-AP-TR_ QFN16_4X4
Address 0101_110xb
internal pull up 1.2K to 1.5V
DP1
GPIO1
ALERT#
SMDATA
TACH
GND
TRIP_SET
GPAD
2
4
ALERT#
6
8
TAC H
10
12
TRIP_S ET
14
16
17
+3VS+3VS +3VS
12
1 2
2103@
R46 1
10K_040 2_5%
SMB _EC_DA2_R
REMOTE2 +
R43 9
1.5K _0402_1%
@
+3VS+3VS +3VS+3VS
12
2103@
R44 1
10K_040 2_5%
SMB _EC_DA2_ R <14 ,19>
R for initial thermal
@C508/@C324=100p
REMOTE1 +
1000P_0 402_50V7K
1000P_0 402_50V7K
C508
REMOTE1 -
REMOTE2 +
C324
REMOTE2 -
@
@
Close to DDR
1
C
2
B
2
E
3 1
1
C
2
B
2
E
3 1
Q39
MMST390 4-7-F_SOT323-3
Under WWAN
Q22
MMST390 4-7-F_SOT323-3
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
shutdown temp
Close U20
1403@
C449
2200P_0 402_50V7K
B B
Shutdown
Temp
93
94
95
96
97
98
A A
99
100
101
102
103
104
105
C651
2200P_0 402_50V7K
TRIP_SET
R439 (1%)
953ohm
1020ohm
1100ohm
1150ohm
1240ohm
1330ohm
1400ohm
1500ohm
1580ohm
1690ohm
1820ohm
1960ohm
2050ohm
5
1
2
1
2
REMOTE1 +
REMOTE2 -
REMOTE1 -
REMOTE2 +
REMOTE2 -
V DD
REMOTE1 +
REMOTE1 -
REMOTE2 +
REMOTE2 -
4
2103@
1 2
R622 0_04 02_5%
2103@
1 2
R623 0_04 02_5%
U29
1403@
1
VDD
2
DP1
3
DN1
4
DP2
5
DN2
EMC 1403-2-AIZL -TR_MSOP10
SMCLK
SMDATA
ALERT#
THERM#
GND
Address 1001_101xb
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
REMOTE1 -REMOTE2 +
REMOTE1 +
10
9
8
7
6
ALERT#
+3VS
12
R62 4
10K_040 2_5%
@
SMB _EC_CK2_R
SMB _EC_DA2_R
2008/03/25 2008/04/
3
Compal Secret Data
Deciphered Date
EC_ FAN_PW M<34>
+5VS
2
1
2
TAC H
FAN _PWM
EC_ TACH<34>
C49 0
10U _0805_10V4 Z
@
1 2
R617 0_04 02_5%
@
1 2
R618 0_04 02_5%
1 2
R619 0_04 02_5%
1 2
R620 0_04 02_5%
TAC H_R
FAN _PWM_ R
FAN1 Conn
JP12
1
TAC H_R
FAN _PWM_ R
Compal Electronics,Ltd.
Title
EMC2103/1403_Thermal sensor/FAN
Size Doc umen t Numb er R ev
Cu stom
Da te: Sh eet o f
2
3
4
5
6
ACE S_85205-0400 1
ME@
LA-5752P
1
2
3
4
G5
G6
31 51Th ursd ay, Octob er 29, 2 009
1
0.3
A
1 1
B
C
D
E
F
G
H
SATA HDD Conn.
2 2
SATA_DTX_C_IRX_N0<13>
SATA_DTX_C_IRX_P0<13>
+5VS
1
C125
1000P_0402_50V7K
3 3
2
SATA_DTX_C_IRX_P0
1
C126
0.1U_0402_16V4Z
2
1
C124
1U_0603_10V4Z
2
SATA_ITX_DRX_P0<13>
SATA_ITX_DRX_N0<13>
C434 0.01U_0402_16V7K
1 2
C433 0.01U_0402_16V7K
1 2
1
C123
10U_0805_10V4Z
2
1
C122
10U_0805_10V4Z
2
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_IRX_N0SATA_DTX_C_IRX_N0
SATA_DTX_IRX_P0
+3VS
+5VS
+3VS
1
@
C121
0.1U_0402_16V4Z
2
JHD D1
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
14
VCC5
15
VCC5
16
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12
22
VCC12
SUYIN_1 27043FB0 22G208ZR_RV
ME@
SATA ODD Conn.
SATA_DTX_C_IRX_N1<13>
SATA_DTX_C_IRX_P1<13>
ODD_P ower_ON#<34>
ODD_OF F#<34>
SATA_ITX_DRX_P1<13>
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
+3VS
ODD_P ower_ON#
SATA_ITX_DRX_N1<13>
C426 0.01U_0402_16V7K
1 2
C425 0.01U_0402_16V7K
1 2
R380
1 2
10K_0402_5%@
1 2
R379 0_0402_5%@
ODD Power Control
J6
2
112
JUMP_43X79
+5VS +5V_ODD
12
R378
@
10K_0402_5%
1
OUT
2
IN
GND
Q36
DTC124EKAT146_SC59-3
3
@
Q37 AO3413_SOT23-3
S
@
G
@
2
D
13
1 2
C423
@
0.01U_0402_16V7K
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_DTX_IRX_N1
SATA_DTX_IRX_P1
+5V_ODD
@
1
C431
10U_0805_10V4Z
2
1
2
3
4
5
6
7
8
9
10
11
12
13
ME@
1
C424
0.1U_0402_16V4Z
2
JODD1
GND
A+
AÂGND
BÂB+
GND
DP
+5V
+5V
MD
GND
GND
OCTEK_SLS-13SB1G_RV
GND
GND
17
16
4 4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2007/10/15 2008/10/15
E
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
B
F
Date: Sheet of
Compal Electronics, Inc.
HDD/ODD Connector
LA-5752P
G
32 51Th ursday, October 2 9, 2009
H
0.3
5
CX2 0671
Hig h Def in iti on Audi o Codec S oC
Wit h Int eg rat ed Clas s-D Stere o
Amp li fier .
An in teg ra ted 5 V to 3 .3 V Low- drop out
vol ta ge re gula tor (LDO).
An in teg ra ted 3 .3 V to 1.8V Low -dro pout
vol ta ge re gula tor (LDO).
D D
+VAU X_3.3
+3VS
+3V ALW
To s uuport W ake-on- Jack or Wake-on-Ring, the CODEC
VAUX_3. 3 & VDD_IO pins m ust be p owerd by a rai l that
is no t removed unless AC power is rem oved.
*DSH pa ge42 has more detail.
+1. 5V
+3VS
+3V ALW
C C
C41 6
1 2
0.1 U_04 02_16V4 Z
C39 6
1 2
0.1 U_04 02_16V4 Z
C39 5
1 2
0.1 U_04 02_16V4 Z
C40 5
1 2
B B
A A
0.1 U_04 02_16V4 Z
R35 5
1 2
0_0 402_5%
R35 4
1 2
0_0 402_5%
R36 2
1 2
0_0 402_5%
J7
1 2
SHO RT PADS
GND GNDA
PC Beep
EC Beep
BEE P#<34>
0.1 U_04 02_16V 4Z@
PC H_SP KR< 13>
ICH Be ep
C3 45
C35 1
1
1U_ 0603 _10V4Z
2
1U_ 0603_ 10V4Z
C35 2
12
1 2
560 _0402_5 %
12
1 2
560 _0402_5 %
10K _0402_ 5%
5
R3 10
R31 1
R30 9
2
B
12
+3VS
12
R32 5
10K _0402_1 %
C3 68
12
12
1U_ 0603_ 10V4Z
R32 6
10K _0402_1 %
1 2
R3 27 20K _0402_5 %
1
C
Q30
2SC 2411KT1 46_SOT23 -3
E
3
D1 5
@
RB7 51V_ SOD323
2 1
12
R3 390_ 0402_5%
@
12
R3 370_ 0402_5%
C38 1
R3 300_ 0402_5% @
12
12
R3 280_ 0402_5%
@
12
R3 290_ 0402_5%
HDA _RST _CO DEC#<13>
HDA _BI TCLK _COD EC< 13>
HD A_S YN C_C ODEC<13>
HD A_S DIN 1<13>
HDA _SDO UT_ CODE C<1 3>
EAPD active low
0=power down ex AMP
1=power up ex AMP
EA PD<34>
EC_ MUTE#<3 4>
Internal SPEAKER
C3 74 1U_ 0603 _10V4Z
12
R3 35
20K _0402_5 %
@
1 2
1
2
C36 9
4
+3VS
1
1
1
C40 8
C40 0
C40 7
2
1
C38 0
2
10U _080 5_10V4Z
0.1 U_04 02_16V 4Z
1
1
C37 7
2
2
1U_ 0603 _10V4Z
0.1 U_04 02_16V4 Z
R3 32
HDA _BI TCLK _CO DEC
R3 36 33 _0402_ 5%
1 2
PC_ BEEP
EC_ MUTE#
2
2
10U _080 5_10V4Z
10K onl y needed i f suppl y to VAUX_3 .3
is re moved dur ing syst em re-s tart.
12
HDA _RST _CO DEC#
HD A_S YN C_C ODEC
HDA _SDO UT_ CODE C
1 2
SPK _L2+
SPK _L1-
SPK _R2+
SPK _R1-
0.1 U_04 02_16V4 Z
0.1 U_04 02_16V4 Z
1
1
C37 1
C37 9
2
2
10K _0402_5 %
10U _080 5_10V4Z
0.1 U_04 02_16V 4Z
10
R33 80_0 402_5%
38
12
37
R34 30_0 402_5%
40
11
13
16
14
1
C41 4
2
U1 7
9
RESET#
5
BIT_CLK
8
SYNC
6
SDATA_IN
4
SDATA_OUT
PC_BEEP
GPIO0/EAPD#
GPIO1/SPK_MUTE#
DMIC_CLK
1
DMIC_1/2
LEFT+
LEFT-
RIGHT+
RIGHT-
C41 2
1U_ 0603_ 10V4Z
7
3
VDD_IO
FILT_1.8
GND
41
1
2
0.1 U_04 02_16V4 Z
2
18
27
29
FILT_1.65
VAUX_3.3
AVDD_3.3
DVDD_3.3
CX2 0671-11 Z_QFN40 _6X6
1
C41 0
2
28
26
AVDD_5V
AVDD_HP
CLASS-D_REF
wide 20MIL
PC_ BEEPPC_ BEEP1
4
C40 9
10U _080 5_10V4Z
LPWR_5.0
RPWR_5.0
SENSE_A
PORTB_R
PORTB_L
B_BIAS
C_BIAS
PORTC_R
PORTC_L
PORTA_R
PORTA_L
AVEE
FLY_P
FLY_N
SPK _R1-
SPK _R2+
SPK _L1-
SPK _L2+
1
2
NC
NC
NC
3
+LD O_OUT _3.3V
AVDD_3.3 pinis output of
internal LDO. NOT connect
to external supply.
0.1 U_04 02_16V4 Z
1
1
C41 1
C41 3
2
2
10U _080 5_10V4Z
0.1 U_04 02_16V4 Z
12
15
17
36
35
34
33
32
31
30
HP_ OUTR _R
23
HP_ OUT L_R
22
24
25
39
21
19
20
C40 1 1U _060 3_10V4Z
3
C39 3
+MI CBIAS B
+MI CBIA SC
1 2
L19 0_060 3_5%
1 2
L20 0_060 3_5%
1 2
L22 0_060 3_5%
1 2
L23 0_060 3_5%
1 2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
+5VS
1
1
C3 92
C3 91
1
2
0.1 U_04 02_16V4 Z
C40 3 2.2U _060 3_10V7K
1 2
C41 5 2.2U _060 3_10V7K
1 2
1 2
1 2
C4 06
C3 90
2
2
0.1 U_04 02_16V4 Z
0.1 U_04 02_16V4 Z
Please bypass caps very close to device.
MIC _IN R
MIC _IN L
R60 15.1 _0402 _5%
R60 25.1 _0402 _5%
1
1
C4 04
2
2
10U _0805 _10V4Z
0.1 U_04 02_16V4 Z
2008/03/25 2008/04/
1
1
C3 99
2
2
10U _0805 _10V4Z
10U _0805 _10V4Z
R34 4 5 .11K _0402_1%
R34 5 1 0K_04 02_1%
R34 6 3 9.2K _0402_1%
Intern al MIC
R35 2 2.2 K_0402_5 %
R35 1 2.2 K_0402_5 %
HP_ OUTR <38>
HP_ OUTL < 38>
WM- 64PC Y_2P
SPK _R1- _CO NN
SPK _R2+ _CO NN
SPK _L1- _CON N
SPK _L2+ _CONN
Compal Secret Data
2
R34 8
1 2
0.1 _1206_1 %
1 2
1 2
1 2
R35 0 1 00_0 402_1%
R35 6 1 00_0 402_1%
Headph one
+MI CBIAS B
R34 9
4.7 K_0402 _5%
MIC 1
1
GN DA
2
45@
Deciphered Date
2
1
1
C3 76
C3 75
2
2
@
@
22P _0402 _50V8J
22P _0402 _50V8J
+5VS
+VAU X_3.3
MI C_J D < 38>
PLU G_IN <38>
+MI CBIA SC
EXT_M IC_R <38>
EXT_M IC_L <38>
12
C39 4 2.2U _06 03_10V7K
1 2
C40 2 2.2U _06 03_10V7K
1 2
@
1
C63 2
2
100 0P_040 2_50V7K
1
1
C63 4
C63 3
2
2
100 0P_040 2_50V7K
1
HDA _RST _CO DEC#
HD A_S YN C_C ODEC
HDA _SDO UT_ CODE C
1
C3 78
2
@
22P _0402 _50V8J
22P _0402 _50V8J
Port C
Port A
1
C3 70
2
Sense resistors must be
connected same power
that is used for VAUX_3.3
1 2
EMI
R33 13 3_0402 _5%
HDA _BI TCLK _CO DEC
Externa l MIC
MIC _IN R M IC_ INL
1 2
R6 000_04 02_5%
MIC _IN R
MIC _IN L
1
C63 5
2
100 0P_040 2_50V7K
100 0P_040 2_50V7K
Compal Electronics,Ltd.
Title
CX20671 Codec
Size Doc ume nt N umber R ev
C
Dat e: Shee t o f
LA-5752P
1
JSP K1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACE S_882 31-04001
ME@
33 51Thu rsda y, Oct ober 29, 2009
0. 3
L14
+3VALW +EC_AVCC
+3VALW
1 2
FBM-11-160808-601-T_0603
1 2
R266 47K_0402_5%
C293
0.1U_0402_16V4Z
1 2
L13 FBM-11-160808-601-T_0603
12
C340 22P _0402_50V8J@
C323
0.1U_0402_16V4Z
2
1
C294
ECAGND
2
1
1000P_0402_50V7K
2
12
R289 10_0402_5%@
+3VALW
R614
@
1 2
4.7K_0402_5%
R615
@
1 2
4.7K_0402_5%
1
KB_RST#<16>
EC_I D to identif y KB926 D or E
KSO[0.. 17]<35>
KSI [0..7]<35>
+3VALW
R265 47K_0402_5%
1 2
R263 47K_0402_5%
1 2
KSO1
KSO2
ENE UPDATE 08/10/21
10K_0402_5%
LAN_WAKE#<29>
PCI_PME#<16>
+3VALW
+3VS
R611
+3VALW
1 2
R262 100K_0402_1%@
1 2
R271 100K_0402_1%@
12
EC_TACH
1 2
R293 0_0402_5%
1 2
R303 0_0402_5%@
S
G
2
FRD#S PI_SO
FSEL#SP ICS#
+3VALW
R292
10K_0402_5%
1 2
D
13
Q26
@
2N7002_SOT23
chan ged 09 .09.08
+3VS
EC_PME#
EC_TACH<31>
1 2
1 2
R291
R294
H_PROCH OT#<5,48>
C290
0.1U_0402_16V4Z
LPC_FRAME#<13,28>
CLK_P CI_LPC<16>
EC_SC I#<16>
KSO[0.. 17]
KSI [0..7]
EC_SMB_CK1<41>
EC_SMB_DA1<41>
EC_SMB_CK2<14>
EC_SMB_DA2<14>
SLP_S3#<15>
SLP_S5#<15>
EC_SMI#<16>
LID_SW #<35>
KILL_SW#<35>
EC_TACH
EC_TX_P80_DATA<28,35>
EC_RX_P80_CLK<28,35>
NUM_LED#<38>
4.7K_0402_5%
4.7K_0402_5%
1
2
PCI_RST#<16,28>
ESB_CLK<3 8>
ESB_DAT<38>
3G_OFF#<28>
ON/OF F#<38>
GATEA20<16>
SERIR Q<13>
LPC_AD3<13,28>
LPC_AD2<13,28>
LPC_AD1<13,28>
LPC_AD0<13,28>
EC_ ID
0.1U_0402_16V4Z
KSI3<35>
KSI4<35>
ESB_CLK
ESB_DAT
+3VALW
C339
0.1U_0402_16V4Z
C319
1
1
2
2
KB_RST#
LPC_AD3
LPC_AD2
LPC_AD1 BATT_TEMP
LPC_AD0
EC_RST#
EC_SC I#
EC_ ID
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT
EC_TX_P80_DATA
EC_RX_P80_CLK
H_PROCH OT#
XCLKI
XCLKO
1000P_0402_50V7K
C329
0.1U_0402_16V4Z
1
2
1
2
3
4
5
7
8
10
12
13
37
20
38
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
C341
C327
1000P_0402_50V7K
1
1
2
2
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LPC & MISC
LAD0
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
Int . K/B
KSO5/GPIO25
Matr ix
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
XCLK1
XCLK0
KB926QFA1_LQFP128
SM Bu s
+EC_AVCC
9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC
PW M Outp ut
AD In pu t
DA Ou tput
PS 2 Inter face
TP_DATA/PSDAT3/GPIO4F
SP I Device Inte rfa ce
SP I Fl ash ROM
GP IO
G PO
GP IO
GP I
GND
GND
GND
GND
GND
11
24
35
94
113
67
AVCC
INVT_PWM/PWM 1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
AGND
69
SPICS#
GPXO10
GPXO11
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R
U13
INVT_PWM
21
BEEP#
23
EC_FAN_PWM
26
ACOF F
27
63
BATT_OVP
64
65
66
PCH_TEMP_ALERT#
75
ODD_P ower_ON#
76
DAC_B RIG
68
70
IRE F
71
72
83
USB_ON
84
85
86
TP_CLK
87
TP_DATA
88
97
98
99
109
FRD#S PI_SO
119
FWR #SPI_SI
120
SPI_CLK
126
FSEL#SP ICS#
128
PM_BTN#
73
I2C_INT
74
89
CHAR GE_LED0#
90
CAPS_LED#
91
CHAR GE_LED1#
92
93
SYS ON
95
121
AC IN
127
100
EC_LID_OUT#
101
EC_ON
102
ODD_OF F#
103
ICH_P OK_EC ICH_P OK
104
BKOFF#
105
106
107
RST#
108
110
112
114
115
SUSP#
116
PBTN_OUT#
117
118
124
1
2
C320
4.7U_0805_10V4Z
INVT_PWM <27>
BEEP# <33>
EC_FAN_PWM <31>
ACOF F <40,42>
BATT_TEMP <41>
BATT_OVP <42>
ADP_I <42>
NOVO# <38>
PCH_TEMP_ALERT# <16>
DAC_B RIG <27>
IREF <42>
CHGVA DJ <42>
EC_MUTE#
EC_MUTE# <33>
TP_CLK <3 5>
TP_DATA <35>
R607
R234 4.7K_0402_5%@
EN_WOL# <29>
BATT_SEL_EC <42>
CMOS_OFF# <27>
FRD#S PI_SO <36>
FWR #SPI_SI <36>
SPI_CLK <36>
FSEL#SP ICS# <36>
PM_BTN# <38>
I2C_INT <38>
FSTCHG <42>
CHAR GE_LED0# <36>
CAPS_LED# <38>
CHAR GE_LED1# <36>
PWR_LED# <36>
SYSO N <28,39,44>
VR_ON <48>
ACIN <40>
EC_RSMRST# <15>
EC_LID_OUT# <14>
EC_ON <38>
ODD_OF F# <32>
BKOFF# <27>
WL_O FF# <28>
AC_PRESENT <15>
RST# <38>
SLP_S4# <15>
ENBKL <27>
EAPD <33>
SUSP# <16,28 ,39,42,44,46>
PBTN_OUT# <15>
BT_OFF# <37>
+3VS
12
R613
10K_0402_5%
EC_FAN_PWM
@
FAN cont rol by EC 09.09.08
chan ged 09 .09.08
chan ged 09 .09.08
ODD_P ower_ON# <32>
R238 10K_0402_5%
1 2
USB_ON# <37>
ME_FLASH <13>
SUS_P WR_DN_ACK <15>
1 2
1 2
D11 RB751V_S OD323
4.7K_0402_5%
@
21
1 2
R258 0_0402_5%
+3VALW
USB_ON#
+3VALW
KB92 6 SPI S TRAP PIN
+3VS
12
I2C_INT
1 2
R251 10K _0402_5%
@
R237 10K_0402_5%
R241
10K_0402_5%
6
DRAMRS T_CNTRL_EC <5>
SUSP#
1
@
C318
1000P_0402_50V7K
2
1 2
ICH_P OK <15>
+3VS
+3VALW
TP_CLK
R236 4.7K_0402_5%
TP_DATA
BATT_OVP
BATT_TEMP
AC IN
1 2
R235 4.7K_0402_5%
1 2
C297 100P_0402_50V8J
C298 100P_0402_50V8J
C328 100P_0402_50V8J
+5VS
1 2
1 2
1 2
+3VS
R226
2.2K_0402_5%
@
1
@
C291
100P_0402_50V8J
2
R227
2.2K_0402_5%
@
EC_SMB_CK2
EC_SMB_DA2
1
@
C292
100P_0402_50V8J
2
+3VALW
R240
1 2
R239
1 2
32.768 KHZ_12.5PF_1TJS125DJ4A420P
EC_SMB_CK1
4.7K_0402_5%
EC_SMB_DA1
4.7K_0402_5%
1 2
C322 15P_0402_50V8J
3
OUT
NC
2
IN
NC
X2
1 2
C321 15P_0402_50V8J
needed to update to D3 version
ECAGND
SA00001J580
XCLKO
12
@
4
R264
20M_0603_5%
1
XCLKI
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet of
Compal Electronics, Inc.
BIOS & EC I/O Port
LA-5752P
34 51Th ursday, October 2 9, 2009
0.3
5
4
3
2
1
reversal of NIWE1
JP5
1
1
2
INT_KBD Conn.
KS I[0..7 ]
D D
C C
KS O[0..17 ]
KSO2
C203 100P_ 0402_50V8J@
KSO15
C153 100P_ 0402_50V8J@
KSO6
C175 100P_ 0402_50V8J@
KSO8
C185 100P_ 0402_50V8J@
KSO13
C172 100P_ 0402_50V8J@
KSO12
C173 100P_ 0402_50V8J@
KSO11
C155 100P_ 0402_50V8J@
KSO10
C154 100P_ 0402_50V8J@
KSO3
C174 100P_ 0402_50V8J@
KSO4
C187 100P_ 0402_50V8J@
KS I0
C204 100P_ 0402_50V8J@
KSO0
C227 100P_ 0402_50V8J@
CONN PIN define need double check
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
KS I[0..7 ] <34 >
KS O[0..17 ] <34 >
KSO16
KSO17
KSO1
KSO7
KS I2
KSO5
KS I3
KSO14
KS I7
KS I6
KS I5
KS I4
KSO9
KS I1
C636 100P_ 0402_50V8J@
1 2
C637 100P_ 0402_50V8J@
1 2
C205 100P_ 0402_50V8J@
1 2
C186 100P_ 0402_50V8J@
1 2
C226 100P_ 0402_50V8J@
1 2
C206 100P_ 0402_50V8J@
1 2
C225 100P_ 0402_50V8J@
1 2
C156 100P_ 0402_50V8J@
1 2
C236 100P_ 0402_50V8J@
1 2
C235 100P_ 0402_50V8J@
1 2
C228 100P_ 0402_50V8J@
1 2
C233 100P_ 0402_50V8J@
1 2
C234 100P_ 0402_50V8J@
1 2
C241 100P_ 0402_50V8J@
1 2
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KS I0
KSO1
KSO5
KS I3
KS I2
KSO0
KS I5
KS I4
KSO9
KS I6
KS I7
KS I1
To TP/B Conn.
+5VS
C150
0.1U _0402_16 V4Z
TP_CLK<34>
TP_DATA<34>
1
@
C151
100P_04 02_50V8J
2
TP_CLK
TP_DATA
1
@
C152
100P_04 02_50V8J
2
CONN PIN define need double check
B B
JP4
4
4
3
3
2
2
1
1
E&T _6905-E04N-0 0R
ME@
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
G1
29
30
G2
30
ACE S_85201-30 05N
ME@
EC DEBUG PORT
JP11
+3VALW
EC_TX_P 80_DATA<28,34>
EC_ RX_P80_CLK<28,34>
31
32
+3VALW
+3VALW
KILL_ SW#<34>
KILL_SW#
1 2
R347 0_04 02_5%
Kill Switch
R295
Lid Switch
C398
0.1U _0402_16 V4Z
100K_04 02_5%
12
+V CC_LID
1
OUTPUT
2
LSSM12-P -V-T-R_3P
3
3
2
2
1
1
SW2
R353 100K_0402 _5%
2
A3212EL HLT-T_SOT23W -3
VDD
GND
U18
1
EC_TX_P 80_DATA
EC_ RX_P80_CLK
1 2
3
Kill
STATUS
1,2(LOW)
2,3(HI) ON
1
2
3
4
ACE S_85205-0400
ME@
2
C397
10P_040 2_50V8J
1
OFF
1
2
3
4
LID_ SW# <34>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/10/15 2008/10/15
3
Compal Secret Data
Deciphered Date
Title
Size Doc umen t Numb er R ev
B
2
Da te: Sh eet o f
Compal Electronics, Inc.
KB /SW /LPC Debug Conn.
LA-5752P
35 51Th ursday, Octobe r 29, 20 09
1
0.3
FOR EC 256KB SPI ROM
(150mil PACKAGE)
P/N : SA00003GK00
FRD#S PI_SO<34>
SC500005B00
SC500006M00
SC500005B00
SC500005B00
FSEL#SPICS#<34>
R218 15_0402_5%
1 2
PWR_LED#<34>
Amber
CHAR GE_LED1#<34>
CHAR GE_LED0#<34>
White
WLAN_LED#<28>
BT_LED#<37>
HDD_L ED#<13>
+3VALW
1
C265
0.1U_0402_16V4Z
2
FSEL#SP ICS#
BATT_LOW_LED#
BATT_CHG_LED#
D17
21
RB751V_SOD323
D16
21
RB751V_SOD323
20mils
U9
1
CS#
2
DO
3
WP#
4
GND
MX25L2005CMI-12G SOP
VCC
HOLD#
CLK
DIO
8
7
6
5
LED
19-213 A-T1D-CP2Q2HY-3T_WHITE
LED2
O
W
18-225A-S2T3D-C01-3T_ORG-WHITE
19-213 A-T1D-CP2Q2HY-3T_WHITE
19-213 A-T1D-CP2Q2HY-3T_WHITE
LED1
White
21
43
LED3
White
LED4
White
HOLD#FRD#S PI_SO SPI_SO
SPI_S I_EC
21
21
21
12
R217
10K_0402_5%
Changed to BEAD for EMI.
Close to EC after C1059.
R215 FBMA-10-100505-101T 0402
1 2
15_0402_5%
1 2
R201
12
R357300_0402_5%
12
R358300_0402_5%
12
R359300_0402_5%
12
R360300_0402_5%
12
R361300_0402_5%
+5VALW
+3VALW
+5VALW
+5VS
+5VS
SPI_CLKSPI_ CLK_R
FWR #SPI_SI
SPI_CLK <34>
FWR #SPI_SI <34>
H6
HOLEA
1
H7
HOLEA
1
SPI_CLK_R
Colse to EC
10P_0402_50V8J
EMI 3G
1
H1
H24
HOLEA
HOLEA
1
1
H22
HOLEA
1
C:H_3P8
H9
HOLEA
1
D:H_3P8 X2
H10
H13
HOLEA
HOLEA
1
1
1
C266
2
FD4
FD1
1
A:H_2P8
H18
HOLEA
1
H14
HOLEA
1
1
H11
HOLEA
1
H5
HOLEA
1
H4
HOLEA
1
R216
0_0402_5%
C264
12P_0402_50V8J
FD2
FD3
1
H15
HOLEA
1
J:H_2P8 X1
12
@
1
2
@
H2
H12
HOLEA
HOLEA
1
1
I:H_3P0 X1
H3
HOLEA
1
H23
HOLEA
1
H16
H20
HOLEA
HOLEA
1
1
G:H_3P2 X2
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/10/15 2008/10/15
Compal Secret Data
Deciphered Date
G:H_3P2 X2
H27
HOLEA
1
H17
HOLEA
H_4P5X3P0N H_6 P0N
H19
HOLEA
1
Title
Size Doc ument Number Re v
B
Date: Sheet of
1
H_3P0X4P0N
Compal Electronics, Inc.
H8
HOLEA
1
H21
HOLEA
1
LED/EC SPI ROM
LA-5752P
36 51Th ursday, October 2 9, 2009
0.3
A
+5VALW
USB20_N1
USB20_P1
2
1
+USB_VCCA
OUT
OUT
OUT
OC#
+USB_VCCB
OUT
OUT
OUT
OC#
D10
@
8
7
6
5
8
7
6
5
RIGHT USB PORT X1
1
2
E-SATA COMBO
LEFT USB PORT
1
2
U19
1
C421 0.1U_0 402_16V4Z
1 1
2 2
C621 0.1U_0 402_16V4Z
3 3
4 4
12
USB_ON#<34>
12
USB_ON#<34>
USB_ON#
+5VALW
USB_ON#
GND
2
IN
3
IN
4
EN
APL3510BKI_SO8
Low Active
U27
1
GND
2
IN
3
IN
4
EN
APL3510BKI_SO8
Low Active
3
PJDLC05_SOT23-3
B
USB_OC#1 <16>
C429
1000P_0402_50V7K
@
USB_OC#0 <16>
C610
1000P_0402_50V7K@
C
D
E
Right USB Conn.
+USB_VCCA
C430
150U_B2_6.3VM_R35M
1
+
2
+USB_VCCA
W=80mils
1
C432
470P_0402_50V7K
2
JUSB1
1
USB20_N3<16>
USB20_P3<16>
USB20_N3
USB20_P3
1
2
2
3
3
4
4
5
G5
6
G6
ACES_85205-04001
ME@
Left USB Conn.
+USB_VCCB
1
C237
470P_0402_50V7K
2
ESATA and USB Conn.
+USB_VCCB
+USB_VCCB
1
+
C615
150U_B2_6.3VM_R35M
SATA_DTX_C_IRX_N4<13>
SATA_DTX_C_IRX_P4<13>
BT_OFF#<34>
BT_LED#<36>
2
SATA_DTX_C_IRX_P4
+5VALW
12
R304
BT@
100K_0402_5%
1
2
OUT
IN
GND
3
1
OUT
GND
3
SATA_ITX_DRX_P4_CONN<13>
SATA_ITX_DRX_N4_CONN<13>
W=80mils
USB20_N0<16>
USB20_P0<16>
W=80mils
1
C622
470P_0402_50V7K
2
0.01U_0402_16V7K ESATA@
BT MODULE CONN
R616
1 2
100K_0402_5%
BT@
Q31
DTC124EKAT146_SC59-3
BT@
Q29
DTC124EKAT146_SC59-3
BT@
2
IN
+3VS
USB20_N0
USB20_P0
USB20_N1<16>
USB20_P1<16>
SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN
ESATA@
SATA_DTX_IRX_N4SATA_DTX_C_IRX_N4
C6240.01U_0402_16V7K
12
SATA_DTX_IRX_P4
C623
12
C353
0.1U_0402_16V4Z
1 2
BT@
Q32 AO3413_SOT23-3
S
G
2
USB20_P11<16>
USB20_N11<16>
BT_ACTIVE<28>
D
13
BT@
PJDLC05_SOT23-3
USB20_N1
USB20_P1
+3VS_BT
USB20_P11
USB20_N11
BTON_LED
BT_ACTIVE
2
3
1
30mils
1
0.1U_0402_16V4Z
C354
2
D7
@
BT@
JUSB2
1
1
2
2
3
3
4
4
5
GND
6
GND
7
GND
8
GND
SUYIN_020 173MR004S558ZL
ME@
JESAT1
USB
1
VBUS
2
D-
3
D+
4
GND
5
GND
6
A+
ESATA
7
A-
8
GND
9
B-
10
B+
11
GND
12
GND
13
GND
14
GND
15
GND
TYCO_1759576-1
ME@
JP7
1
1
2
2
3
3
4
4
5
7
5
G1
6
8
6
G2
ACES_87213-0600G
ME@
USB
A+ = RXP
A- = RXN
B- = TXN
B+ = TXP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
C
Compal Secret Data
Deciphered Date
Title
Size Docume nt Number R ev
Cus tom
D
Date : Sheet of
Compal Electronics, Inc.
USB ports/BT/E-SATA
LA-5752P
E
0.3
37 51Thursda y, October 2 9, 2009
ON/OFF switch
Power Button
TOP Side
Bottom Side
ON /OFFBT N#
EC_ ON<34>
EC _ON
SW1
1
2
1 2
@
5
6
J5
SHO RT PAD S
R30 2
10K_040 2_5%
1 2
3
4
SMT1-05_4P
D14
1
DAN 202UT1 06_SC70-3
2N7002_ SOT23-3
Cap Sensor Board Conn. 6pin
Power Bottom Board Conn. 8pin
+3VALW
R272
100K_04 02_5%
1 2
3
2
13
D
2
G
Q28
S
ON /OFF#
51_ ON#
ON /OFF# <34 >
51_ ON# <4 0>
+5VS
NUM _LED#<34 >
CAP S_LED#<34>
PM_BTN#<34>
PM_BTN#
+3VS
PM_BTN#
NOV O_BTN#
ON /OFFBT N#
12
R60 3
100K_04 02_1%
JP3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND
10
GND
ACE S_85201-0805 1
ME@
I2C _INT<34>
ESB_DAT<34 >
ESB _CLK< 34>
RST#<34>
ENE SB3534
R3 0_0 402_5%
1 2
R2 0_0 402_5%
1 2
R1 0_0 402_5%
1 2
+3VS
+5VS
33P_040 2_50V8J
@
C1
ME@
ACE S_85201-0805 1
10
GND
9
GND
8
I2C _INT_ R
2
2
@
C2
1
33P_040 2_50V8J
1
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JP1
+3VALW
NOV O#<34>
51_ ON#<40>
NOV O#
51_ ON#
Card Reader/Audio Jack SB CONN
PL UG_IN
HP_ OUTR
HP_ OUTL
MIC _JD
EXT_MIC_L
EXT_MIC_R
USB 20_P5
USB 20_N5
+3VALW
PL UG_IN< 33>
HP_ OUTR<33 >
HP_ OUTL<33>
MIC _JD<33>
EXT_MIC_L<33>
EXT_MIC_R<33>
USB 20_P5<16>
USB 20_N5<16>
R296
100K_04 02_5%
1 2
D13
2
1
3
DAN 202UT1 06_SC70-3
JP8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
GND
12
12
GND
ACE S_85201-12 05N
ME@
NOV O_BTN#
13
14
NOV O_BTN# O N/OFF BTN#
2
3
D19
PJS OT24C 3P C/A SOT-23
@
1
PM_BTN#
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
2
3
D20
PJS OT24C 3P C/A SOT-23
@
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/03/25 2008/04/
Compal Secret Data
Deciphered Date
Compal Electronics,Ltd.
Title
Audio Jack & SW connector
Size Doc umen t Numb er R ev
Cu stom
Da te: Sh eet o f
LA-5752P
38 51Th ursd ay, Octob er 29, 2 009
0.3
A
B
C
D
E
+3VALW TO +3VS+5VALW TO +5VS +1.5V to +1.5VS
+5VALW
U10
8
D
1
C279
2
G
12
13
D
S
10U_0805_10V4Z
2
B+
R229
20K_0402_5%
13
D
Q20
2N7002_SOT23
S
R142
470_0603_5%
@
2
G
Q10
2N7002_SOT23
@
1 1
2 2
7
D
6
D
5
D
SI4800BD Y-T1-E3_SO8
5VS_GATE_R
R228
12
10K_0402_5%
+1.5V +VCCP+1.8VS +0.75VS
S
S
S
G
12
13
D
S
+5VS
1
2
3
4
1
C278
0.1U_0603_25V7K
2
R342
470_0603_5%
@
SYSO N# SUSP SUSPSUSP
2
G
Q35
2N7002_SOT23
@
1
C277
10U_0805_10V4Z
2
1
C276
1U_0603_10V4Z
2
12
R174
470_0603_5%
@
13
D
G
Q15
S
2N7002_SOT23
@
12
R202
470_0603_5%
@
13
D
SUSP
2
G
Q16
S
2N7002_SOT23
@
SUSP
12
R568
22_0603_5%
13
D
2
S
2
G
Q40
2N7002_SOT23
B+
2
G
1
C127
10U_0805_10V4Z
2
12
R89
47K_0402_5%
13
D
Q9
2N7002_SOT23
S
+1.05VS
12
R143
470_0603_5%
@
13
D
G
Q11
S
2N7002_SOT23
@
+3VALW
U4
8
D
7
D
6
D
5
D
SI4800BD Y-T1-E3_SO8
R88
0_0402_5%
@
1 2
SUSP
2
S
S
S
G
+3VS
1
2
1
3
4
2
1
C144
0.1U_0603_25V7K
2
C134
10U_0805_10V4Z
1
C135
1U_0603_10V4Z
2
12
R87
470_0603_5%
@
13
D
S
SUSP
2
G
Q6
2N7002_SOT23
@
Q33
SUSPSUSP
2
G
2N7002_SOT23
B+
12
100K_0402_5%
R312
13
D
S
1
C389
10U_0805_10V4Z
2
R313
0_0402_5%
1 2
+1.5V
8
7
6
5
@
0.1U_0603_25V7K
+1.5VS
U16
1
S
D
2
S
D
3
S
D
4
G
D
SI4800BD Y-T1-E3_SO8
1.5VS_GATE5VS_GATE
1
1
DIS@
C373
C361
2
0.1U_0603_25V7K
2
1
C362
10U_0805_10V4Z
2
1
C363
1U_0603_10V4Z
2
12
R314
470_0603_5%
@
13
D
Q34
S
2N7002_SOT23
@
SUSP
2
G
For Intel S3 Pow er Reduction.
3 3
12
SUSP<8,44,45>
SUSP#<16,28, 34,42,44,46> SYSON<28,34,44>
4 4
SUSP
DTC124EKAT146_SC59-3
A
R4
100K_0402_5%
Q1
2
IN
+5VALWRTC VREF
12
1
3
@
R5
100K_0402_5%
OUT
GND
100K_0402_5%
SYSO N#
DTC124EK AT146_SC59-3
SYSO N
B
+5VALW
12
@
R6
Q2
1
@
OUT
2
IN
GND
3
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2007/8/18
C
Compal Secret Data
Deciphered Date
Title
Size Do cument Number R ev
Cust om
D
Date: S heet
Compal Electronics, Inc.
DC Interface
LA-5752P
39 51T hursday, Octobe r 29, 2009
E
0.3
o f
A
DC030006J00
PF1
7A_24 VDC_4290 07.WRML
APD IN APDI N1
4
4
3
3
1 1
@
2
2
1
1
4602- Q04C-09 R 4P P2.5
JD CIN
21
12
12
PC8
PC9
0.1U_0 603_25V7K
SMB3 025500YA_2P
12
1000P _0402_50V7K
PL2
1 2
PC10
100P_ 0402_50V8J
Vin Detector
Min. typ. Max.
B
ACIN
VIN
Precharge detector
Min. typ. Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V
12
12
PC7
0.1U_0 603_25V7K
12
PC6
PC5
100P_ 0402_50V8J
1000P _0402_50V7K
VI N
12
PD13
RLS41 48_LL34-2
C
D
BATT ONLY
Precharge detector
Min. typ. Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V
PR142
1K_12 06_5%
1 2
PR38
1K_12 06_5%
1 2
PR31
1K_12 06_5%
1 2
12
PR143
100K_ 0402_1%
PQ26
TP0610K-T1-E3_SOT23- 3
12
PR138
100K_ 0402_1%
13
2
L-->H 17.430V 17.901V 18.384V
H-->L 16.976V 17.262V 17.728V
2
12
12
5
+
6
-
12
12
+RTCBATT
+CHGRTC
13
PQ11
DTC11 5EUA_SC 70-3
PC99
0.01U_ 0402_25V7K
PC11
1000P _0402_50V7K
PR26
1M_0402_1%
1 2
VIN DE-2
PD12
PR16
3
2
PR20
10K_0 402_5%
12
12
PR15
VS
8
P
+
-
G
4
12
1
O
PU10A
LM393 DG_SO8
12
RTC VREF
51ON- 2
PC4
1 2
0.22U_ 0603_25V7K
PC97
0.01U_ 0402_25V7K
TP0610K-T1-E3_SOT23- 3
51ON- 3
2 2
PC14
3 3
VI N
12
PR134
84.5K _0402_1%
PR27
12
PR135
BATT+
51_ON#<38>
22K_0 402_1%
1 2
20K_0 402_1%
CH GRTCP
VIN DE-3
12
PC13
0.1U_0 402_16V7K
LL414 8_LL34-2
PR122
200_0 603_5%
1 2
100K_ 0402_1%
22K_0 402_1%
1 2
VIN DE-1
12
1000P _0603_50V7K
RTCVREF
4 4
+CHGRTC
PR125
560_0 603_5%
1 2
PR124
560_0 603_5%
1 2
A
3.3V
12
PC91
10U_0 603_6.3V6M
PU8
G920A T24U_SOT89-3
3
OUT
GND
1
2
IN
PD9
LLZ4V 3B_LL34-2
3.3V
PQ4
12
PR123
200_0 603_5%
CHG RTC INRTC VREF-1
12
PC90
1U_08 05_25V6K
VI N
12
2 1
2
PR21
10K_0 805_5%
PR141
68_12 06_5%
13
PR18
10K_0 402_1%
1 2
PAC IN
12
PR19
10K_0 402_5%
VIN
PD2
LL414 8_LL34-2
1 2
51ON- 1
12
12
PC16
0.1U_ 0603_25V7K
B
12
PR140
68_12 06_5%
ACO FF<34,42>
AC IN <34>
PU10B
7
O
PR25
2.2M _0402_5%
VS
8
P
G
4
PR17
10K_0 402_5%
PAC IN <42>
VL
12
PR137
PD10
RB715 F_SOT323-3
MAINPWON<41 ,43>
ACON<42>
2
3
100K_ 0402_1%
1
LM393 DG_SO8
12
PC98
0.1U_0 603_25V7K
RTCVREF
VS
JR TC
- +
MAXEL_ML1220T10@
12
PD8
1 2
RB751 V-40_SOD3 23-2
RTC Battery
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/01/06 2010/01/06
Compal Secret Data
Deciphered Date
C
12
PR39
100K_ 0402_1%
13
2
12
PR23
PRG++
PQ3
SSM3 K7002F_SC59-3
13
D
S
Title
Size D ocum ent Nu mber R ev
Dat e: Sheet of
205K_ 0402_1%
2
G
Cus tom
PQ12
DTC11 5EUA_SC 70-3
PR136
47K_0 402_5%
13
PQ25
DTC11 5EUA_SC 70-3
Compal Electronics, Inc.
DCIN & DETECTOR
B+
12
PR22
499K_ 0402_1%
12
12
PC12
PR24
499K_ 0402_1%
0.01U_ 0402_25V7K
12
2
PACIN <4 2>
+5VALW
D
40 51Th ursday, October 29, 20 09
0.1
A
1 1
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 92 degree C
JBATT
VMB2
1
1
2
2
EC_SM CA
3
2 2
3
4
4
5
5
6
6
7
7
8
GND
9
GND
TYCO _1775789-1
@
EC_SM DA
12
12
PR3
PR4
100_0 402_1%
100_0 402_1%
PF2
12A_6 5V_451012MRL
21
VMB
SMB3 025500YA_2P
12
PC110
1000P _0402_50V7K
PL3
1 2
BATT+
12
PC109
0.01U _0402_25V7K
100K_ 0402_1%_ TSM0B104F4251RZ
EC_SM B_CK1 <34>
EC_SM B_DA1 <34>
1 2
PR6
6.49K _0402_1%
1 2
PR5
10K_0 402_5%
3 3
+3VALW
BATT_TEMP <34>
A/D
Recovery at 56 degree C
VL
12
PH1
PR87
13.7K _0402_1%
TM-1
1 2
12
12
PC63
0.22U_ 0603_25V7K
12
PR88
15.4K_ 0402_1%
TM_REF1
PC64
1000P _0402_50V7K
12
PC62
0.01U_ 0402_25V7K
3
+
2
-
PR85
12
100K_ 0402_1%
PR86
100K_ 0402_1%
VS
8
P
G
4
TM-2
1
O
PU4A
LM393 DG_SO8
12
VL
PR83
47K_0 402_1%
1 2
VL
PR84
47K_0 402_1%
1 2
TM-3
5
+
6
-
2
8
P
O
G
LM393 DG_SO8
4
13
G
7
PU4B
MAINP WON <40,43>
D
PQ20
SSM3 K7002FU_SC 70-3
S
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2010/01/062009/01/06
Title
Size D ocum ent Nu mber R ev
Dat e: Sheet of
Compal Electronics, Inc.
BATTERY CONN / OTP
D
41 51Thur sday, O ctober 29 , 2009
0.1
5
PQ27
FDS66 75BZ_SO 8
VIN
D D
C C
12
PR145
47K_0 402_5%
13
2
G
PAC IN<40>
ACO N<40>
ACO FF<3 4,40>
D
2N700 2KW_SOT323-3
S
8
7
5
DTA14 4EUA_SC70-3
2
13
2
PQ8
PAC IN
PQ10
DTC11 5EUA_SC 70-3
ACO FF
4
PQ7
1 3
PQ28
DTC11 5EUA_SC 70-3
PR37
3K_04 02_1%
1 2
2
CHGVAD J=(Vcell-4)/0.10627
Vcell
4V
B B
4.2V
4.35V
CC=0.25A~3A
CHGVADJ
0V
1.88 2V
3.2 935V
UMA CP mode
Vaclim=2.39*{(2.26K//514K)/((2.26K//514K)+(21K//514K))}=0.239V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Va clim=0 .239V , Iinput=2.75A
P2
1
2
36
12
12
PR30
PC107
200K_ 0402_1%
0.1U_0 603_25V7K
PQ6
FDS66 75BZ_SO 8
1
2
3 6
4
FSTCHG<34>
12
PR29
150K_ 0402_1%
PQ9
13
D
2N700 2KW_SOT323-3
2
G
S
13
IREF<34>
0.01U _0402_25V7K
ADP _I<34>
PR173
154K_ 0402_1%
PR167
100K_ 0402_1%
Connect to EC A/D Pin.
IREF=1.016*Icharge
IREF=0.254V~3.048V
VCHLIM need over 95mV
P3
A A
DIS CP mo de
Vaclim=2.39*{(31.6K//514K)/((31.6K//514K)+(21K//514K))}=1.425V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vacl im=1.4 25V, Iinput=4 A
12
PR14
10_06 03_5%
1 2
13
625 1_DCIN
2
1
PD1
RB715 F_SOT323-3
12
PR13
100K_ 0402_1%
5
PQ2 TP0610K- T1-E3_SOT23-3
13
PR12
2
100K_ 0402_1%
PQ38
DTC11 5EUA_SC 70-3
8
7
5
PC3
1 2
12
CHGVADJ<34>
4
P3
12
12
PC2
0.01U_ 0402_25V7K
FST CHG
2
SUSP #
3
4
0.02_ 1206_1%
1
2
PD15
RB751 V-40TE17_SOD323 -2
1 2
PR7
10K_0 402_1%
12
1 2
PC132
0.1U_ 0402_16V7K
PC131 6800P_04 02_25V7K
1 2
PR175 6.81K_040 2_1%
1 2
1 2
PC130
100P_ 0402_50V8J@
6251_ VREF
1 2
PC1
0.1U_ 0402_16V7K
PR172
21K_0 402_1%
1 2
PR2
31.6K _0402_1%
PR171
15.4K _0402_1%
1 2
PR174
100_0 402_1%
31.6K _0402_1%
VS
PU1B
LM358DT_SO 8@
8
7
0
4
FSTCHG <34>
SUSP# < 16,2 8,34 ,39,44,46>
3
B+
PR152
4
3
6251 _VDD
12
PC128
12
PR8
6251_ EN CS ON
100K_ 0402_1%
CELLS
1 2
6251_ VREF
12
PR1
2.2U_0 603_6.3V 6K
12
PU11
1
VDD
2
ACSET
3
EN
4
CELLS
5
ICOMP
6
VCOMP
7
ICM
8
VREF
9
CHLIM
10
ACLIM
11
VADJ
12
GND
ISL625 1AHAZ-T_Q SOP24
DCIN
ACPRN
CSON
CSOP
CSIN
CSIP
PHASE
UGATE
BOOT
VDDP
LGATE
PGND
12
PC15
470P_ 0603_50V8J
24
23
22
21
20
19
18
17
16
15
14
13
LI- 3S :13.5 V----B ATT-OV P=1.5012V
BAT T-OVP =0.111 2*VMB
Per cell= 3.5V
5
P
+
6
-
G
BATT_OVP<34>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
625 1_DCIN
12
PC124
0.047 U_0402_16V7K
PC12 3
0.1U_ 0402_16V7K
1 2
LX_CHG
DH_ CHG
2.2_0 402_5%
BST_C HG
6251_ VDDP
DL_ CHG
PJ11
2
112
JUMP_43X118@
PC125
0.1U_ 0603_25V7K
12
20_04 02_5%
1 2
PR160
20_04 02_5%
12
1 2
PR157
1 2
12
PC122
4.7U_ 0805_6.3V 6K
PR139
10K_0 402_1%@
1 2
CS IN
CSI P
PR161
1 2
PR159
20_04 02_5%
PR158
2.2_0 402_5%
0.1U_ 0603_25V7K
BST_C HGA
12
PD14
RB751 V-40TE17_SOD323 -2
1 2
PR163
4.7_0 402_5%
PU1A
LM358DT_SO 8@
Compal Secret Data
CSOP
PC120
12
6251 _VDD
1
Deciphered Date
2
CHG_ B+
1 2
1 2
PC114
PC112
4.7U_1 206_25V6K
4.7U_1 206_25V6K
PC111
1 2
1 2
PC113
4.7U_1 206_25V6K
2200P _0402_50V7K
PR155
10K_0 402_1%
1 2
13
PQ32
DTC11 5EUA_SC 70-3
PQ29
3 5
241
SIS41 2DN-T1-GE 3 _PAK1212-8
PQ31
3 5
241
SI7716 ADN-T1-G E3 _PAK1212-8
PL5
10U_L F919AS-1 00M-P3_4.5A_20%
1 2
12
PR154
4.7_12 06_5%
12
PC118
680P_ 0603_50V7K
PQ34
FDS66 75BZ_SO 8
1
2
3 6
4
PR28
47K_0 402_1%
1 2
1
PD3
RB715 F_SOT323-3
2
0.02_ 1206_1%
C HGC HG
1
2
6251_ VDD 6251_V DD
8
7
5
3
2
PC121
PR151
VIN
12
0.1U_0 603_25V7K
ACO FF
200K_ 0402_1%
D
S
4
3
1 2
13
PC106
1
PR162
PAC IN
2
G
PQ5
2N700 2KW_SOT323-3
12
12
PC103
10U_1 206_25V6M
PC105
10U_1 206_25V6M
VI N
BATT+
12
10U_1 206_25V6M
VMB2
12
VS
12
8
3
P
+
0
2
-
G
4
PR9
340K_ 0402_1%@
12
PC100
PR10
499K_ 0402_1%@
0.01U_ 0402_25V7K@
12
PR11
105K_ 0402_1%@
2008/6/222007/6/22
2
CELLS
12
PR176
0_0402_5%
2N700 2KDW- 2N_SOT363-6@
12
PC101
0.01U_ 0402_25V7K@
Title
Size D ocum ent Nu mber R ev
Dat e: Sheet of
PR168
100K_ 0402_1%@
1 2
61
PQ1A
Compal Electronics, Inc.
CHARGER
PR178
100K_ 0402_1%@
1 2
34
2
5
PQ1B
2N700 2KDW- 2N_SOT363-6@
1
12
PR177
0_0402_5%@
BATT_SEL_E C<34>
42 51Thur sday, O ctober 29 , 2009
0.1
5
4
3
2
1
ISL6237_B+
12
12
PC36
PC25
10U_1 206_25V6M
2200P _0402_50V7K
PL6
4.7UH _PCMC0 63T-4R7M N_5.5A_20%
12
PR156
4.7_1 206_5%
5V_SN B
12
680P_ 0402_50V7K
PC119
12
PJ10
2
112
JUMP_43X118@
PJ12
2
112
JUMP_43X118@
12
PC37
0.1U_0 402_25V6
+5VALWP
1
+
PC117
150U_ B2_6.3VM_R45M
PR36
61.9K_ 0402_1%@
1 2
PR35
1 2
0_040 2_5%
2
12
0_0402_5%
100K_ 0402_1%
1 2
PR32
ISL6237_B+
PQ14
SIS41 2DN-T1- GE3_PAK1212-8
3 5
241
3 5
241
PQ30
SI7716 ADN-T1- GE3_PAK1212-8
PR44
PR144
1 2
200K_ 0402_1%
12
BST3A-1
PC43
0.1U_ 0603_25V7K
1 2
PC42
0.22U _0603_25V7K
1 2
VL
PR146
1 2
806K_ 0603_1%
12
PR41
0_0402_5%
1 2
PR42
2.2_0 603_5%
2VREF_ISL6237
PR33
47K_0 402_1%@
1 2
PC104
0.047U _0402_16V7K
0.1U_ 0603_25V7K
UG3
BST3A
12
SW3
LG3
FB3
VL
1 2
PC102
0.22U _0603_25V7K
EN_ LDO
3/5V_ EN1
3/5V_ EN2
12
PC108
0.047U _0402_16V7K
@
PC27
PR50
0_0402_5%
1 2
2VREF _ISL6237
33
26
24
25
23
30
32
1
8
20
4
14
27
1 2
TP
UGATE2
BOOT2
PHASE2
LGATE2
OUT2
REFIN2
REF
LDOREFIN
NC
EN_LDO
EN1
EN2
PC28
1U_06 03_10V6K
VL
1 2
PC41
3/5 V_VIN
3/5 V_VCC
3
6
VIN
VCC
TON
NC
2
5
3/5 V_NC
12
3/5V_T ON
12
PR43
0_0402_5%
12
1U_06 03_10V6K
PC23
7
19
PVCC
LDO
15
UGATE1
17
BOOT1
16
PHASE1
18
LGATE1
22
PGND
10
OUT1
11
FB1
9
BYP
29
SKIP
28
POK2
13
POK1
12
ILIM1
31
ILIM2
GND
PU2
21
ISL623 7IRZ-T_Q FN32_5X5
4.7U_0 805_6.3V 6K
PC40
1U_06 03_10V6K
1 2
HG5
BST5A
PR40
2.2_0 603_5%
SW5
LG5
FB5
5V_SK IP
ILM1
ILIM 2
BST5A-1
12
PC22
0.1U_ 0603_25V7K
PR150
0_0402_5%@
1 2
PR149
0_0402_5%
PR51
0_0402_5%@
PR34
301K_ 0402_1%
PR147
301K_ 0402_1%
1 2
12
12
PQ33
SI7716 ADN-T1- GE3_PAK1212-8
2VREF _ISL6237
12
12
PQ13
SIS41 2DN-T1- GE3_PAK1212-8
3 5
241
3 5
241
VL
+3VALWP +3VALW
+5VALWP +5VALW
2VREF _ISL6237
B+
PJ4
JUMP_43X118@
2
112
D D
+3VALWP
150U_ B2_6.3VM_R45M
C C
B B
PC116
12
PC21
330P_ 0402_50V7K
4.7UH _PCMC0 63T-4R7M N_5.5A_20%
1
+
1 2
2
1 2
VS
PR52
0_040 2_5%
PR148
10K_0 402_1%
@
12
PC38
0.1U_0 402_25V6
PL4
1 2
680P_ 0402_50V7K
PD5
21
LLZ5V 1B_LL34-2
12
PC39
PC26
10U_1 206_25V6M
2200P _0402_50V7K
12
PR153
4.7_1 206_5%
3V_SN B
12
PC115
PD11
1 2
RB751 V-40_SOD3 23-2
EN_LD O-1
PD4
1 2
RB751 V-40_SOD3 23-2
MAINP WON <40 ,41>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/01/06 2010/01/06
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
3VALW/5VALW
Size D ocum ent Nu mber R ev
Thursday, October 29, 2009
2
Dat e: Sheet of
43 51
1
0.1Cus tom
5
4
3
2
1
1.5 V_IN
578
3 6
241
PQ49
4
123 5
VCC P_IN
3 5
241
3 5
241
PQ48
SI4686 DY-T1-E 3_SO8
TPCA8 028-H_SO P-ADVANC E8-5
PQ40
SI7716 ADN-T1- GE3_PAK1212-8
@
PR247
240K_ 0402_1%
1 2
BST_1.5V BST _1.5V-1
1 2
PR249
1
2
TON
EN_PSV
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
1.5V_ PGOOD
@
240K_ 0402_1%
1 2
1
2
TON
EN_PSV
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
1.05V _PGOOD <46>
+3VALW
12
PC151
1U_04 02_6.3V6K
GND7PGND
GND7PGND
2.2_0 603_5%
14TP15
DRVH
TRIP
DRVL
DRVH
TRIP
DRVL
LL
LL
13
12
11
10
9
PR131
2.2_0 603_5%
1 2
13
12
11
10
9
@
UG_1. 5V
1.5V_ TRIP
SW _1.5V
LG_1. 5V
UG_ VCCP
SW _VCCP
VC CP_TRIP
PR128
23.7K _0402_1%
LG_ VCCP
VBST
V5DRV
8
PU14
TPS 51117RGY R_QFN14 _3.5x3.5
PR133
BST_V CCP BST_VCCP -1
14TP15
VBST
V5DRV
8
PU9
TPS 51117RGY R_QFN14 _3.5x3.5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
PR245
7.15K _0402_1%
@
1 2
1 2
PC182
0.1U_ 0603_25V7K
+5VALW
12
PC183
4.7U_ 0805_6.3V 6K
SIS41 2DN-T1- GE3_PAK1212-8
PC95
@
1 2
0.1U_ 0603_25V7K
+5VALW
@
12
PC92
4.7U_ 0805_6.3V 6K
@
Compal Secret Data
PQ41
@
+1.05VSP +1.05VS
Deciphered Date
1 2
PR243
100K_ 0402_1%@
+3VS
PR126
100K_ 0402_1%
1 2
@
6
5
NC
7
NC
8
NC
9
TP
1.5V_ TON
1.5V_ EN
1.5V_ V5FILT
1.5V_ FB
12
@
VCCP _TON
VCC P_EN
VCC P_V5FILT
VCC P_FB
PC179
0.1U_ 0402_16V7K
D D
SYS ON<28,3 4,39>
+5VALW
C C
SUSP #<1 6,28,34, 39,42,46>
+5VALW
B B
+1.5V
1
PJ17
1
JUMP_43X79@
2
2
12
PC146
4.7U_ 0805_6.3V 6K
PR250
A A
S3_0. 75V_EN<5>
@
0_0402_5%
1 2
PR190
0_0402_5%
0.75V _EN
SUSP< 8,39,45>
1 2
0.1U_ 0402_16V7K@
5
PC147
12
13
D
2
G
S
1K_04 02_1%
1K_04 02_1%
PQ46
SSM3 K7002FU_SC 70-3
PR239
PR240
PR248
0_0402_5%
1 2
PR242
100_0 603_1%
1 2
PC178
4.7U_ 0603_6.3V 6K
PR132
@
100K_ 0402_1%
1 2
PR127
100_0 603_1%
1 2
@
PC93
4.7U_ 0603_6.3V 6K
@
0. 75V_IN
12
0.7 5V_REF
12
PC176
0.1U_ 0402_16V7K
12
PC184
0.1U_ 0402_16V7K
@
12
12
12
PC96
0.22U _0402_6. 3V6K
@
12
12
12
12
PC181
47P_0 402_50V8J@
1 2
PR244
31.6K _0402_1%
1 2
PR246
30.1K _0402_1%
PC94
47P_0 402_50V8J@
1 2
PR129
13.7K _0402_1%
1 2
@
PR130
31.6K _0402_1%
@
PU13
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G2992 F1U_SO8
+0.75VS P
PC149
10U_0 603_6.3V6M
4
12
PL13
@
PC175
PC180
12
PC138
PL9
12
PC173
10U_1 206_25V6M
0.1U_0 402_25V6
2
12
PC141
0.1U_0 402_25V6
2200P _0402_50V7K
@
@
@
@
12
PC169
10U_1 206_25V6M
1UH_P CMB103E -1R0MS_20A_20%
1 2
12
PR241
4.7_1 206_5%
1.5V _SNB
12
680P_ 0402_50V7K
12
PC140
10U_1 206_25V6M
@
2.2UH _PCMC0 63T-2R2M N_8A_20%
1 2
12
PR181
4.7_1 206_5%
VC CP_SNB
12
PC135
680P_ 0402_50V7K
PJ14
2
112
JUMP_43X118@
2010/01/062009/01/06
2
PJ16
JUMP_43X79@
PJ20
2
112
JUMP_43X79@
12
PC174
2200P _0402_50V7K
+1.5VP
1
+
PC172
2
112
1
+
2
PC136
@
Title
Size D ocum ent Nu mber R ev
Dat e: Sheet of
12
220U_ B2_2.5VM_R15M
PC177
10U_0 603_6.3V6M
+1.05VS P
12
220U_ B2_2.5VM_R15M
PC137
10U_0 603_6.3V6M
@
PJ21
+1.5VP +1.5V
2
JUMP_43X118@
PJ19
2
JUMP_43X79@
Compal Electronics, Inc.
1.5V/VCCP/0.75V
1
B+
B+
112
112
+0.75VS+0.75VSP
44 51Thur sday, O ctober 29 , 2009
0.1
5
B+
D D
C C
JUMP_43X79@
PJ3
2
N11M-GE1/LP1
N11 M-GE 1/LP1 PR620= 22.6k
B B
VG A_IN
112
12
12
12
12
PC24
PC35
PC186
10U_1 206_25V6M
10U_1 206_25V6M
VGA_E N<16>
0
0
1
GPU_VID1<19>
10K_0 402_5%
1 2
PR62
2.2K_ 0402_5%
GPIO6GPIO5
GPU_ VID1G PU_V ID0 VG A_CORE
0
1
1
PR166
12
10K_0 402_1%
PR165
GPU_VID0<19>
10K_0 402_5%
PC185
0.1U_0 402_25V6
2200P _0402_50V7K
12
PC50
2.2U_ 0603_6.3V 6K
VGA_E N_2 ISEN_ VGA
PC51
1U_04 02_6.3V6K
0.8V
0.85 V
0.9V
PR72
GVID1 -1
12
PR169
22.6K _0402_1%
1 2
GVID1 -2
61
PQ37A
2
2N700 2KDW- 2N_SOT363-6
12
PC127
0.01U F_0402_2 5V7K
PR170
12
10K_0 402_1%
VGA _VCC
12
PC134
GVID0 -1
12
12
PC129
0.01U F_0402_2 5V7K
4
3
VIN
4
VCC
5
EN
VGA_COM P
12
22P_0 402_50V8J
+3VS
@
PR47
10K_0 402_5%
8
GND
PU3
ISL626 8CAZ-T_SS OP16
COMP6FB7FSET
12
PR68
22.1K_ 0402_1%
VGA_C OMP-1
12
PC54
6800P _0402_25V7K
VFB= 0.6V
12
PR67
6.04K _0402_1%
34
PQ37B
5
2N700 2KDW- 2N_SOT363-6
3
UG_V GA
BST_VGA
PR48
2.2_0 603_5%
1 2
1UG16
PHASE
FSET_V GA
12
PC55
@
9
0.01U_ 0402_25V7K
15
BOOT
PVCC
PGND
ISEN
VO
10
1 2
PR69
42.2K_ 0402_1%
12
PR180
5.36K _0402_1%
14
13
LG
12
11
2
PGOOD
VGA_F B
1 2
+5VALW
12
PR49
0_0603_5%
1 2
+VGA_ PVCC
2.2U_ 0603_6.3V 6K
LG_VGA
12
PR179
1.82K _0402_1%
BST_VGA-1
PR46
4.7_0 603_5%
1 2
PC52
1 2
PR63
3.6K_ 0402_1%
VGA_F B-1
1 2
PC49
0.1U_ 0603_25V7K
VGA _VCC
Rds=4.0mΩ
SW_VGA
4
5
4
5
PQ35
TPCA8 030-H_SO P-ADV8-5
123
786
PQ39
123
SI4634 DY-T1-E3 _SO8
4
2
PL7
0.88U H_PCMB1 03E-R88MS_20A _20%
786
5
PQ36
123
1 2
12
1
PR164
4.7_12 06_5%
VGA_S NB
12
SI4634 DY-T1-E3 _SO8
PC126
680P_ 0402_50V7K
1
+
12
2
PC17
PR70
100_0 402_5%
330 U_D2_2.5 VY_R9M
+VGA_COREP +VGA_CORE
+
2
PC133
PR71
0_0402_5%
1 2
12
330 U_D2_2.5 VY_R9M
PJ2
2
JUMP_43X118@
PJ13
2
JUMP_43X118@
PC19
PJ606
112
JUMP_43X39@
10U_0 603_6.3V6M
112
112
1
12
12
PC18
10U_0 603_6.3V6M
+VGAS ENSE <21>
2
+VGA_ COREP
PC20
10U_0 603_6.3V6M
+1.8VS+1.8VSP
+3VS
1
PJ8
JUMP_43X39@
4.7U_ 0805_6.3V 6K
A A
PR103
100K_ 0402_1%
LDO_1 .8V_EN
SUSP< 8,39,44>
1 2
PC76
0.1U_ 0402_16V7K
5
12
PC75
2
G
1
2
2
12
PR104
1K_04 02_1%
13
D
PR105
1.24K _0402_1%
S
PQ22
SSM3 K7002FU_SC 70-3
LD O_1.8V_I N
12
LDO _1.8V_R EF
12
PC77
0.1U_ 0402_16V7K
12
PU6
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G2992 F1U_SO8
+1.8VSP
12
PC78
10U_0 603_6.3V6M
4
6
5
NC
7
NC
8
NC
9
TP
12
PC79
1U_04 02_6.3V6K
+5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Deciphered Date
2010/01/062009/01/06
2
Title
Size D ocum ent Nu mber R ev
Dat e: Sheet of
Compal Electronics, Inc.
VGA_CORE/1.8VS/1.1VS
45 51Thur sday, O ctober 29 , 2009
1
0.1
5
4
3
2
1
D D
C C
B B
PJ9
2
B+
JUMP_43X118
@
1.05V _PGOOD<44>
112
SUSP #<1 6,28,34, 39,42,44>
VTT_SELECT<8>
VTT_B+
12
12
12
PC85
PC83
PC188
10U_1 206_25V6M
10U_1 206_25V6M
0_0402_5%
1 2
0_0402_5%@
1 2
H_V TTVI D1= Lo w, 1.1 V
H_V TTVI D1= Hi gh, 1. 05V
0.1U_0 402_25V6
PR116
PR117
12
PC187
2200P _0402_50V7K
VCCP _POK<5>
1 2
PR121
35.7K _0402_1%
12
0.1U_ 0402_16V7K@
VTT_VCC
12
PC86
2.2U_ 0603_6.3V 6K
VTT_EN-1
PC87
12
PC88
PR114
0_0402_5%
1 2
3
VIN
4
VCC
5
EN
VTT_COMP
22P_0 402_50V8J
PC89
VFB= 0.6V
+5VS
12
2
8
GND
PU7
ISL626 8CAZ-T_SS OP16
COMP6FB7FSET
12
PR118
22.1K_ 0402_1%
VTT_COMP-1
12
6800P _0402_25V7K
PR115
1K_04 02_5%
1.1 VS_PGOOD
1UG16
PHASE
PGOOD
VTT_FB
12
PR119
1.96K _0402_1%
9
VTT_FSET
12
SW_VTT
UG_VTT
PR113
42.2K_ 0402_1%
VTT_BOOT
15
BOOT
PVCC
LG
PGND
ISEN
VO
10
12
PC82
0.01U _0402_25V7K
@
1 2
PR112
2.2_0 603_5%
1 2
+5VALW
12
VTT_PVCC
14
2.2U_ 0603_6.3V 6K
LG_VTT
13
12
VTT_ISEN
11
PR120
1.58K _0402_1%
VTT_BOOT-1
PR106
0_0603_5%
PR108
4.7_0 603_5%
1 2
1 2
PC81
1 2
3K_04 02_1%
PR109
VTT_FB-1
1 2
PC84
0.1U_ 0603_25V7K
VTT_VCC
Rds=4.0mΩ
4
4
5
PQ24
TPCA8 030-H_SO P-ADV8-5
123
PQ23
123 5
TPCA8 028-H_SO P-ADVANC E8-5
PL8
0.56U H_MMD- 10CZ-R56M-M 1_19A_20%
1 2
12
PR107
PQ21
4.7_1 206_5%
4
VTT_SNB
12
PC80
1000P _0603_50V7K
123 5
TPCA8 028-H_SO P-ADVANC E8-5
PR11 0
10_04 02_5%
1 2
1
+
2
@
PR111
0_0402_5%
1
+
2
PC74
330U_ D2E_2.5VM
12
+1.1V _VCCPP
PC139
330U_ D2E_2.5VM
VTT_SENSE <8>
PJ15
+1.1V_ VCCPP +VCCP
+1.1V_ VCCPP +1.05VS
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/01/06 2010/01/06
3
Compal Secret Data
Deciphered Date
Title
Size D ocum ent Nu mber R ev
Cus tom
2
Dat e: Sheet of
2
112
JUMP_43X118@
PJ7
2
112
JUMP_43X118@
PJ1
2
112
JUMP_43X118@
Compal Electronics, Inc.
+1.1VS_VTT
46 51Th ursday, October 29, 20 09
1
0.1
5
D D
B+
PJ5
2
112
@
JUMP _43X118
PR1 01
10_ 0402_5%
C C
B B
VSS _AXG_S ENSE<8>
VCC _AXG _SENSE<8>
+GF X_COR EP
1 2
@
PR1 02
10_ 0402_5%
1 2
@
150 P_0402 _50V8J
PC7 3
PR2 26
10K _0402_1 %
@
GF X_FB-2
12
@
1 2
PC1 66
100 0P_040 2_50V7K
@
1 2
PC1 67
330 P_0402 _50V7K
@
1 2
12
12
PR1 00
17. 8K_040 2_1%
@
PR 99
825 K_0402_ 1%
100 P_0402 _50V8J
@
PC1 70
22P _0402_ 50V8J
1 2
12
@
12
@
GF X_FB-1
1 2
PC 71
@
@
GFX VR_P WRGD
GFX VR_C LKEN#
4
GFX_B+
12
PC 61
10U _1206_2 5V6M
@
PC7 2
330 P_0402_ 50V7K
PC1 71
100 0P_040 2_50V7K
@
PR 98
8.0 6K_040 2_1%
@
3
12
12
PC 59
PC1 60
10U _1206_2 5V6M
12
12
PC1 61
0.1 U_04 02_25V6
220 0P_040 2_50V7K
@
@
PR2 30
47K _0402_1 %
+GF X_COR EP
12
PR9 7
1.9 1K_040 2_1%
@
@
12
+5V ALW
@
PR2 38
10K _0402_ 1%
PR9 6
1_0 603_5%
@
628 81_FB
628 81_COM P
628 81_VW
628 81_R BIAS
12
12
12
PC1 65
1U_ 0603_1 0V6K
@
7
VSEN
6
FB
5
COMP
4
VW
3
RBIAS
2
PGOOD
1
CLK_EN#
@
29
0_0 603_5%
628 81_V DD
IS UM+
IS UM-
10
9
8
RTN
ISUM
AGND
ISUM+
PU 5
ISL 6288 1HRZ- T_QFN28 _4X4
28
628 81_V R_ON
628 81_D PRSL PVR
628 81_VI D6
PR 95
1 2
12
@
@
628 81_VI N
11
12
13
VIN
VDD
VID5
25
628 81_VI D3
628 81_VI D4
628 81_VI D5
12
12
PR 91
PC1 64
0.2 2U_0 603_25V7K
22. 6K_040 2_1%
@
BST_GF X BST_GFX1
1 2
@
PR 92
2.2 _0603_ 5%
@
14
IMON
BOOT
UG_ GFX
15
UGATE
LX_GFX
16
PHASE
17
VSSP
LG_G FX
18
LGATE
628 81_V CCP
19
VCCP
20
VID0
21
VID1
VID2
VID323VID424VID626VR_ON27DPRSLPVR
22
628 81_VI D2
628 81_VI D0
628 81_VI D1
PC1 63
0.2 2U_0 402_6.3 V6K
0.2 2U_0 603_16V 7K
1 2
0_0 603_5%
12
@
PC 66
2.2 U_06 03_6.3V 6K
@
1 2
PR2 24
0_0 402_5%@
1 2
PC1 62
@
PR2 25
@
@
@
@
@
@
@
@
@
GFX VR_IM ON <8>
VSS _AXG_S ENSE <8>
578
+5V ALW
@
PR2 280_ 0402_5%
12
PR2 290_ 0402_5%
12
PR2 310_ 0402_5%
12
PR2 320_ 0402_5%
12
PR2 330_ 0402_5%
12
PR2 340_ 0402_5%
12
PR2 350_ 0402_5%
12
PR2 360_ 0402_5%
12
PR2 370_ 0402_5%
12
3 6
3 5
2
PQ4 7
@
SI4 686D Y-T1- E3_SO8
241
12
GFX _SN
PQ1 9
@
241
TPC A8028_ PSO8
1 2
@
GFX VR_V ID_0 <8>
GFX VR_V ID_1 <8>
GFX VR_V ID_2 <8>
GFX VR_V ID_3 <8>
GFX VR_V ID_4 <8>
GFX VR_V ID_5 <8>
GFX VR_V ID_6 <8>
GFX VR_EN <8>
GFX VR_D PRSL PVR <8>
0.5 6UH _MMD -10CZ- R56M-M1 _19A_20%
1 2
12
PR 80
2.2 _1206_ 5%
PC 60
680 P_0402 _50V7K
IS UM+
IS UM-
PR8 2
3.6 5K_040 2_1%
1 2
PR2 27
@
2.6 1K_040 2_1%
@
PC7 0
0.0 68U_ 0402_10V6 K
PR9 4
82. 5_0402 _1%
1 2
@
1 2
PR 90
11K _0402_ 1%
PC 65
0.1 U_04 02_16V7K
0.0 1U_0 402_25V 7K
PL12
@
IS UM-2
1 2
@
1 2
@
1 2
@
3.0 1K_040 2_1%
IS UM-3
@
PR 93
1 2
PC 68
@
PC 67
1
+
12
PR 81
2
0_0 402_5%
PH 4
@
10K B_06 03_5 %_ERTJ1 VR103J
IS UM-1
1 2
@
330 U_D2 _2. 5VY_R9M
@
PR 89
@
100 _0402_1 %
1 2
IS UM-4
PC 69
@
180 P_040 2_50V8J
1 2
1
+GFX_COREP
PC1 58
1
+
2
330 U_D2 _2. 5VY_R9M
@
PJ1 8
+GF X_CORE P
A A
2
JUMP _43X118@
PJ 6
2
JUMP _43X118@
+GF X_CORE
112
112
(15A,6 00mils ,Via NO.= 30)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/01/06 2010/01/06
Compal Secret Data
Deciphered Date
2
Compal Electronics, Inc.
Title
Size Doc ume nt N umber R ev
Dat e: Shee t o f
GFX _CORE
1
47 51Thu rsda y, Oct ober 29, 2009
0. 1
8
H H
7
6
5
4
3
2
1
+3VS
PR 77
1.9 1K_040 2_1%
G G
F F
C PU_C SP2
E E
CP U_C SN2
CP U_C SN1
C PU_C SP1
12
PR2 23 47 0_040 2_1%
PR2 21 47 0_040 2_1%
PR2 20 47 0_040 2_1%
PR2 19 47 0_040 2_1%
PC1 56
100 P_0402 _50V8J
12
12
PC1 53
100 P_0402 _50V8J
12
VGATE<15 >
CLK _EN#<12>
VR _ON<34>
12
12
12
D D
C C
B B
PR6 6
0_0 402_5%
VSS SENSE
1 2
PR1 99 0_ 0402_ 5%
1 2
PR2 00 0_ 0402_ 5%
1 2
PR2 09 0_ 0402_ 5%
CPU _MO DE
1 2
PR 73 0_0402 _5%
CPU _CSP 2-2
1 2
PC1 57 33P _0402_ 50V8J
CPU _CSN 2-1
1 2
PC1 55 33P _0402_ 50V8J
CPU _CSN 1-1
1 2
PC1 54 33P _0402_ 50V8J
CPU _CSP 1-2
1 2
PC1 52 33P _0402_ 50V8J
CP U_ GNDS NS
C PU_V SNS
CPU _TH ERM
12
CPU _VR_T T#
PR6 5
0_0 402_5%
1 2
PR 53 20K _0402_ 1%
<8>
<8>
VC CSEN SE
12
12
PR 45
PR2 12
0_0 402_5%
@
12. 4K_040 2_1%
1 2
PC 57
0.2 2U_0 603_10V 7K
1
2
3
4
5
6
7
8
9
10
1 2
1 2
PR2 16 68_0 402_5%
PR2 17 0 _0402_ 5%
+VC CP
H_P ROCH OT#
12
PC 44
0.2 2U_0 402_6. 3V6K
<8>
1 2
PC1 50
2.2 U_06 03_6.3 V6K
1 2
PC 58
CP U_V REF
40
41
GND
MODE
GND
CSP2
CSN2
CSN1
CSP1
GNDSNS
VSNS
THERM
VR_TT#
CPU _IM ON
1 2
<5,3 4>
VSS SENSE
A A
8
7
12
PR7 6
1K_ 0402_5%
1 2
1 2
PR7 5
1K_ 0402_5%@
+5VS
+3VS
12
PR2 18
68P _0402_ 50V8J
5.1 1K_040 2_1%
PR 74249 K_0402 _1%
1 2
1 2
CPU _TON SEL CP U_VR EF
CP U_D ROO P
C PU_I SLEW
36
37
38
39
VREF
ISLEW
V5FILT
DROOP
PU 12
TPS 5162 1RHAR _QFN40_ 6X6
PR 780_0 402_5%@
PR2 100_0 402_5%
1 2
CPU _OSR SEL
CPU _CLK _EN #
C PU_P GOOD
CP U_V R_O N
32
33
34
35
VR_ON
PGOOD
TONSEL
OSRSEL
CLK_EN#
IMON11DPRSLPVR12PSI#13VID614VID515VID416VID317VID218VID119VID0
VI D1
VI D2
VI D3
VI D4
VI D5
VI D6
C PU_D PRSL PVRPR OC_D PRSL PVR
1 2
1 2
1 2
PR2 15 0_ 0402_ 5%
PR2 14 0_ 0402_ 5%
PR2 13 0_ 0402_ 5%
PSI # CP U_PS I#
H _VID 6
PSI#
H_ VID 6
IMV P_IMON
1 2
1 2
1 2
PR2 08 0_ 0402_ 5%
H _VID 5
<8>
H_ VID 5
1 2
1 2
PR1 96 0_ 0402_ 5%
PR2 05 0_ 0402_ 5%
PR2 07 0_ 0402_ 5%
PR2 06 0_ 0402_ 5%
H _VID 2
H _VID 3
H _VID 4
H _VID 1
<8>
<8>
<8>
<8>
H_ VID 1
H_ VID 2
H_ VID 3
H_ VID 4
PR OC_D PRS LPVR
6
+5VS
@
PR1 970_ 0402_ 5%
1 2
PR 790_0 402_5%
PR1 980_0 402_5%
1 2
1 2
CPU _TR IPSEL
+5VS
31
UGA TE_C PU2
TRIPSEL
DRVH2
VBST2
DRVL2
PGND
DRVL1
VBST1
DRVH1
30
29
28
LL2
27
26
V5IN
25
24
23
LL1
22
21
BOO T_CP U2 BOOT_ CPU2-1
1 2
PR1 89 2 .2_0 603_5%
PHA SE_C PU2
LGA TE_C PU2
PC 53 10U _0603_ 6.3V6M
LGA TE_C PU1
PHA SE_C PU1
BOO T_CP U1 BOOT_ CPU1-1
PR1 87 2.2_ 0603_5%
UGA TE_C PU1
1 2
12
1 2
PD 6
1SS 355_S OD323-2
20
VI D0
1 2
PR1 94 0_ 0402_ 5%
PR1 95 0_ 0402_ 5%
H _VID 0
<8>
<8>
<8>
<8>
<8>
H_ VID 0
H _VID 0
H _VID 1
H _VID 2
H _VID 3
H _VID 4
H _VID 5
H _VID 6
PR OC_ DPRS LPVR
Cla rk fiel d:VI D( 0- 5):0 0110 1
Aub ur ndal e:VI D( 0- 5):0 0111 0
PR 61 1K_ 0402_5 %@
12
PR 60 1K_ 0402_5 %@
12
PR 59 1K_ 0402_5 %
12
PR 58 1K_ 0402_5 %
12
PR 57 1K_ 0402_5 %
12
PR 56 1K_ 0402_5 %@
12
PR 55 1K_ 0402_5 %@
12
PR 54 10K _0402_ 5%
12
PD 7
1SS 355_ SOD323-2
1 2
PC1 45
0.2 2U_0 603_10V7K
+5VS
1 2
PC1 44
0.2 2U_0 603_10V7K
1 2
+V CCP
5
+5VS
H _VID 0
H _VID 1
H _VID 2
H _VID 3
H _VID 4
H _VID 5
H _VID 6
PR OC_ DPRS LPVR
CPU_B+
12
12
12
5
4
PQ18
@
123
TPC A803 0-H_SO P-ADV8-5
PQ43
4
123 5
TPC A802 8-H _SOP-A DVANCE8 -5
UGA TE_C PU2
5
4
PQ1 7
TPC A803 0-H_SO P-ADV8-5
123
PQ4 2
4
123 5
TPC A802 8-H _SOP-AD VANCE8- 5
PC4 8
0.1 U_04 02_25V6
12
PR1 84
4.7 _1206_5 %
@
C PU_S NB2
12
PC1 42
680 P_0402 _50V7K
PC2 9
PC 47
220 0P_040 2_50V7K
0.3 6UH _PCM C104 T-R36M N1R17_3 0A_20%
CPU _CSP 2-1
12
PR1 82
17. 8K_040 2_1%
1 2
PR1 83
28. 7K_040 2_1%
C PU_C SP2
12
5
UGA TE_C PU1
4
PQ16
TPC A803 0-H_SO P-ADV8-5
123
@
PQ44
4
123 5
TPC A802 8-H _SOP-AD VANCE8- 5
5
4
PQ1 5
TPC A803 0-H_SO P-ADV8-5
123
PQ4 5
@
4
123 5
TPC A802 8-H _SOP-A DVANCE8 -5
PC4 6
0.1 U_04 02_25V6
12
PR1 85
4.7 _1206_ 5%
C PU_S NB1
12
PC1 43
680 P_0402 _50V7K
12
PC 45
220 0P_040 2_50V7K
0.3 6UH _PCM C104 T-R36M N1R17_3 0A_20%
CPU _CSP 1-1
12
PR1 86
17. 8K_040 2_1%
1 2
PR1 88
28. 7K_040 2_1%
C PU_C SP1
PR1 91 1K_ 0402_5%
12
PR1 92 1K_ 0402_5%
12
PR1 93 1K_ 0402_5%@
12
PR2 01 1K_ 0402_5%@
12
PR2 02 1K_ 0402_5%@
12
PR2 03 1K_ 0402_5%
12
PR2 04 1K_ 0402_5%
12
PR2 11 1K_ 0402_5%@
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2009/01/06 2010/01/06
Compal Secret Data
Deciphered Date
3
12
PC3 0
10U _1206_2 5V6M
10U _1206_2 5V6M
PL10
1
2
PR2 22
69. 8K_040 2_1%
1 2
PH 2
100 K_04 02_1% _TSM0B10 4F4251R Z
CPU _SN- 2
1 2
1 2
PC 56
0.0 33U_ 0402_16 V7K
12
12
PC3 3
PC3 2
10U _1206_2 5V6M
10U _1206_2 5V6M
PL11
1
2
PR 64
69. 8K_040 2_1%
1 2
PH 3
100 K_04 02_1%_T SM0B104F 4251RZ
CPU _SN- 1
1 2
1 2
PC1 59
0.0 33U_ 0402_16 V7K
PL1
HCB 4532 KF-800T 90_1812
1 2
1
12
PC3 1
10U _1206_2 5V6M
4
3
CP U_C SN2
CPU_B+
12
PC3 4
1
+
+
PC1 68
PC1 48
100 U_25V_M
100 U_25V_M
2
2
B+
+C PU_C ORE
10U _1206_2 5V6M
4
3
CP U_C SN1
Compal Electronics, Inc.
Title
Size Doc ume nt N umber R ev
Dat e: Shee t o f
2
CPU_CORE
48 51Thu rsda y, Oct ober 29, 2009
1
0. 1
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 2
for PWR
Reason for change PG# Modify List Date PhaseItem
D D
1
2
3
4
5
6
C C
7
8
9
10
B B
11
12
13
14
15
16
A A
17
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/01/06 2009/01/06
3
Compal Secret Data
Deciphered Date
2
20081022
Title
Size D ocum ent Nu mber R ev
Cus tom
Dat e: Sheet of
Compal Electronics, Inc.
PIR (PWR)
<Doc>
49 51Th ursday, October 29, 20 09
1
0.1
5
4
3
2
1
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
D D
C C
EVT TO DVT
B B
A A
Title
Size Do cument N umber R ev
B
5
4
3
2
Dat e: Sheet o f
Compal Electronics, Inc.
HW PIR
LA-5752P 0.3
50 51Thur sday, Octobe r 29, 2009
1
5
D D
C C
4
3
2
1
B B
A A
Title
Size Do cument N umber R ev
B
5
4
3
2
Dat e: Sheet o f
Compal Electronics, Inc.
HW PIR
LA-5751 0.3
51 51Thur sday, Octobe r 29, 2009
1
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