Compal LA-5631P NCL20 ULV, EC14, EC14D Schematic

1 1

Compal Confidential

2 2

NCL20 ULV M/B Schematics Document

Intel Penryn Processor with Cantiga SFF + DDRIII + ICH9M SFF

3 3

2009-10-08

REV:0.4

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2010/01/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Page

NCL20 M/B LA-5631P Schematic

141Tuesday, November 10, 2009

0.1

Compal confidential

File Name : LA-5631P

LS5631P I/O Board

1 1

Mobile Penym

LV/ULV Dual Core

uFCPGA-956 CPU - SFF

page 4,5,6,7

Thermal Sensor

EMC1402-1-ACZL

page4

CK505

Clock Generator ICS9LPRS387

page 19

LS5632P C/R Board

FSB

667/800/1066MHz 1.05V

DDR3 800MHz 1.5V

Dual Channel

DDR3 SO-DIMM X2

page 14,15

LS5633P LED Board

LS5634P SW Board

LS5635P TP/B Board

HDMI Conn.

Level shift

LCD CONN. CRT CONN.

LVDS

TMDS

H_A#(3..35) H_D#(0..63)

page 18page 17page25

Intel Cantiga GS45

FCBGA 1363 - SFF

page 8,9,10,11,12,13

LS5636P ODD/B Board

2 2

DMI X4

USB conn x2

page 28

Bluetooth conn

page 28

CMOS Camera 1.3M

page23

IO board

PCI-Express

Intel ICH9-M

WBMMAP-569 - SFF

S-ATA

USB conn x1

MINI Card x1

WLAN

page 27

SIM CONN.

3 3

LAN ATHEROS AR8131L

page 24

RJ45 LAN connector

page 25

port 0

HDD connector

page 23

port 1

page 19,20,21,22

LPC BUS

ENE KB926 D2

page 29

CDROM connector

RTC CKT.

page 24

Power On/Off CKT.

page 32

DC/DC Interface CKT.

4 4

page 35

IO/B Conn.

page 29

TP/B Conn.

page 31

Power Circuit DC/DC

page 36~~42

Speaker Conn.

page 31

page 23

Touch Pad

page 30

Int.KBD

BIOS

page 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

3.3V 48MHz

3.3V 24.576MHz/48Mhz

page 30

Deciphered Date

HD Audio

SPEAKER

USB

page 33

HDA Codec

ALC269X-GR

page 32

Card Reader

RTS5159-GR

page23

IO board

Audio Jack

page 33

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Block Diagram

NCL20 M/B LA-5631P Schematic

241Tuesday, October 20, 2009

0.1

Voltage Rails

Power Plane

VIN

1 1

B+ +CPU_CORE +1.05VS

Description

Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail

S1 S3 S5

N/A N/A N/A

ON ON ON

N/AN/AN/A OFF

OFF OFF

OFF

OFF OFF

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

OFF

ON ON

OFF

LOW

OFF

+1.5V +1.5VS +0.75V

+3VALW +3V_LAN +3VS

+5VALW +5VS

2 2

+VSB +RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

1.5V power rail for DDR

1.5V switched power rail

0.75V switched power rail for DDR terminator

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail 5V switched power rail VSB always on power rail RTC power

ON ON ON ON

ON ON ON ON ON

ON ON ON ON

OFF

OFF OFF

OFF

ON ON*

OFF

ON*

ON OFF

OFF

ON ON*

ONON

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

max

BOARD ID Table BTO Option Table

External PCI Devices

Device

IDSEL#

REQ#/GNT#

Interrupts

Board ID

0 1 2 3 4 5 6 7

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

EC SM Bus2 address

Device

ADI ADT7421

1001 100X b0001 011X b

USB table

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

ICH9M SMBUS Address

Device

DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR

4 4

(ICS9LPRS387, SLG8SP556V)

HEX

Address

1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0A4 1 1 0 1 0 0 1 0

EHCI2

UHCI5

UHCI6

Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port10 Port11

PCB Revision

0.1

MB USB Conn1. MB USB Conn2. sub board WLAN Card Reader 3G BT CMOS Camera

BTO Item BOM Structure

PCIE table

PCIE port1 PCIE port2 PCIE port3 PCIE port4 PCIE port5 PCIE port6

3G Card Wireless Card GLAN

SATA table

SATA port0 SATA port1 SATA port2 SATA port3 SATA port4 SATA port5

HDD ODD

ZZZ1

PCB-MB

DA80000GO00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2010/01/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Notes List

NCL20 M/B LA-5631P Schematic

341Tuesday, October 20, 2009

0.1

+5VS

R111

D D

H_A#[3..16](8)

H_ADSTB#0(8)

H_A#[17..35](8)

C C

H_ADSTB#1(8)

H_A20M#(18)

H_FERR#(18)

H_IGNNE#(18) H_STPCLK#(18)

H_INTR(18)

B B

A A

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0(8) H_REQ#1(8) H_REQ#2(8) H_REQ#3(8) H_REQ#4(8)

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_NMI(18) H_SMI#(18)

U1A

A[3]#

A[4]#

A[5]#

A[6]#

AA1

A[7]#

AB4

A[8]#

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

A20M#

AG5

AL5

F10

F8 C9 C5 E5

V2 Y2

J9 F4 H8

ICH

FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07

PENRYN SFF_UFCBGA956

BPRI#

ADDR GROUP 0

DEFER#

DRDY#

DBSY#

IERR#

CONTROL

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HITM#

ADDR GROUP 1

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TRST#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

Place close to U1.

ADS#

BNR#

L5 N5

F38 J1

BR0#

B40 D8

INIT#

N1 G5

K2 H4 K4 L1

HIT#

F2 AY8

BA7 BA5 AY2 AV10 AV2 AV4

TCK

AW7

TDI

AU1

TDO

AW5

TMS

AV8 J7

DBR#

D38 BB34 BD34

B10

A35 C35

RESERVED

H_ADS# (8) H_BNR# (8)

H_BPRI# (8) H_DEFER# (8)

H_DRDY# (8) H_DBSY# (8)

H_BR0# (8)

H_INIT# (18)

H_RESET#

H_LOCK# (8)

H_RS#0 (8) H_RS#1 (8) H_RS#2 (8)

H_TRDY# (8)

H_HIT# (8) H_HITM# (8)

Del XDP_BPM#5 net.071309.

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

R558 0_0402_5%@R558 0_0402_5%@

1 2

H_THERMDA_R H_THERMDC_R

H_THERMTRIP#

R22 68_0402_5%R22 68_0402_5% R23 0_0402_5%R23 0_0402_5% R24 0_0402_5%R24 0_0402_5%

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK (16) CLK_CPU_BCLK# (16)

XDP_DBRESET# XDP_TDO

XDP_TRST# XDP_TDI

XDP_TMS XDP_TCK

For ESD

+VCCP

1 2 1 2 1 2

add it 073109.

R10

R10 51_0402_1%

51_0402_1%

9/20

1 2

56_0402_5%

Change to NU 072709.

XDP_DBRESET# (19)

H_PROCHOT# (40)

+VCCP

H_THERMTRIP# (8,18)

D9 PJDLC05_SOT23-3

PJDLC05_SOT23-3

H_RESET# (8)

H_THERMDA H_THERMDC

D10

D10 PJDLC05_SOT23-3

PJDLC05_SOT23-3

XDP_TDI XDP_TMS XDP_TDO

XDP_TRST# XDP_TCK

Add it 090909.

+VCC_FAN1

EN_FAN1(29)

Change from 54.9 ohm to 51ohm 072709.

D11

D11 PJDLC05_SOT23-3

PJDLC05_SOT23-3

EN_FAN1

R1 51_0402_1%R1 51_0402_1%

1 2

R2 51_0402_1%R2 51_0402_1%

1 2

R3 51_0402_1%R3 51_0402_1%

1 2

R6 51_0402_1%R6 51_0402_1%

1 2

R7 51_0402_1%R7 51_0402_1%

1 2

This shall place near CPU

0_0603_5%

1 2

0_0402_5%

R1007

H_THERMDA

2200P_0402_50V7K

H_THERMDC

1 2 3 4

C949

0.1U_0402_16V4Z

FAN_SPEED1(29)

+VCCP

C1035

C638

1 2

10U_0805_10V4Z

U19

VEN VIN VO VSET

G990P11U SOP

SA00002GW00

GND GND GND GND

+3VS

8 7 6 5

+3VS

R1586

R1586 10K_0402_5%

10K_0402_5%

C641

C641 1000P_0402_50V7K

1000P_0402_50V7K

0.1U_0402_16V4Z

1 2

FAN_PWM(29)

C1034

VDD

THERM#

EMC1402-1-ACZL-TR_MSOP8

40mil

+VCC_FAN1

SMDATA

+5VS

SMCLK

ALERT#

GND

D53

@D53

1SS355_SOD323-2

D54

1 2

BAS16_SOT23-3

C639

1 2

C640

1000P_0402_50V7K

1 2

FAN_PWM

Change footprint 073109.

8 7 6 5

10U_0805_10V4Z

JP32

E-T_3801-E04N-01R

CONN@ SP020907300

EC_SMB_CK2 (29) EC_SMB_DA2 (29)

1 2

R305

R305 10K_0402_5%

10K_0402_5%

+3VS

Security Classification

2009/02/27 2010/01/21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2010/01/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

NCL20 M/B LA-5631P Schematic

Date: Sheet

Compal Electronics, Inc.

Penryn (1/3) & FAN

441Tuesday, October 20, 2009

0.1

H_D#[0..15](8)

D D

H_DSTBN#0(8) H_DSTBP#0(8) H_DINV#0(8) H_D#[16..31](8)

C C

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1(8) H_DSTBP#1(8) H_DINV#1(8)

CPU_BSEL0(16) CPU_BSEL1(16) CPU_BSEL2(16)

V_CPU_GTLREF

T8T8

T9T9 T10T10

H_D#0 H_D#1

H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST2

TEST5 TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

D[32]# D[33]# D[34]#

DATA GROUP 0

D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02

AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

H_PSI#

H_D#33 H_D#34H_D#2 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_D#32

AP44

H_DPRSTP# (8,18,40)

H_DPSLP# (18) H_DPWR# (8) H_PWRGOOD (18)

H_CPUSLP# (8)

T11T11

H_D#[32..47] (8)

H_DSTBN#2 (8) H_DSTBP#2 (8) H_DINV#2 (8) H_D#[48..63] (8)

H_DSTBN#3 (8) H_DSTBP#3 (8) H_DINV#3 (8)

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

27.4_0402_1% R33

R33

R32

R30

R31

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

266 0 0 0

+CPU_CORE +CPU_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

R27 0_0402_5%R27 0_0402_5%

J11

1 2

R28 0_0402_5%R28 0_0402_5%

E11

1 2

R29 0_0402_5%R29 0_0402_5%

G11

1 2 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP

330U_D2E_2.5VM_R9

CPU_VID0 (40) CPU_VID1 (40) CPU_VID2 (40) CPU_VID3 (40) CPU_VID4 (40) CPU_VID5 (40) CPU_VID6 (40)

VCCSENSE (40)

VSSSENSE (40)

0.01U_0402_16V7KC60.01U_0402_16V7K

Near pin B34

Change to 330u_R9, casue high limitation. 12/14

+1.5VS

10U_0805_6.3V6MC710U_0805_6.3V6M

Near pin D34

+CPU_CORE

R34

+VCCP

R36

R36 1K_0402_1%

V_CPU_GTLREF

A A

1K_0402_1%

R37

R37 2K_0402_1%

2K_0402_1%

1 2

100_0402_1%

100_0402_1% R35

R35

1 2

100_0402_1%

Close to CPU pin within 500mils.

VCCSENSE

VSSSENSE

Close to CPU pin AW43 within 500mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

NCL20 M/B LA-5631P Schematic

541Tuesday, October 20, 2009

0.1

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

VCCP_040

VCCP_041

VCC_120

VCC_121

V22

VCCP_042

VCC_122

Y24

VCCP_043

VCC_123

Y22

AB24

VCCP_044

VCCP_045

VCC_124

VCC_125

AB22

AJ35

VCCP_046

VCC_126

AD24

AD22

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

M24

M22

AF36

VCCP_047

VCCP_048

VCC_127

VCC_128

AF24

AL35

AN35

VCCP_049

VCC_129

AF22

AH24

AK36

VCCP_050

VCCP_051

VCC_130

VCC_131

AH22

AP36

B12

VCCP_052

VCC_132

AK24

AK22

B14

VCCP_053

VCCP_054

VCC_133

VCC_134

AM24

C13

D12

VCCP_055

VCC_135

AP24

AM22

D14

E13

VCCP_056

VCCP_057

VCC_136

VCC_137

AT24

AP22

F14

VCCP_058

VCCP_059

VCC_138

VCC_139

AT22

F12

G13

VCCP_060

VCC_140

AV24

AV22

H14

VCCP_061

VCCP_062

VCC_141

VCC_142

AY24

H12

J13

VCCP_063

VCC_143

AY22

BB24

K14

VCCP_064

VCCP_065

VCC_144

VCC_145

BB22

K12

L13

VCCP_066

VCC_146

BD24

BD22

L11

VCCP_067

VCCP_068

VCC_147

VCC_148

B16

M14

N13

VCCP_069

VCC_149

B18

B20

N11

VCCP_070

VCCP_071

VCC_150

VCC_151

D16

K10

P14

VCCP_072

VCC_152

F18

D18

P12

VCCP_073

VCCP_074

VCC_153

VCC_154

F16

R13

R11

VCCP_075

VCC_155

H18

H16

T14

VCCP_076

VCCP_077

VCC_156

VCC_157

D20

U13

U11

VCCP_078

VCC_158

F20

H20

V14

V12

VCCP_079

VCCP_080

VCC_159

VCC_160

K18

K16

W13

VCCP_081

VCCP_082

VCC_161

VCC_162

M18

W11

P10

VCCP_083

VCC_163

K20

M16

V10

VCCP_084

VCCP_085

VCC_164

VCC_165

M20

Y14

VCCP_086

VCC_166

P18

AA13

AA11

VCCP_087

VCC_167

T18

P16

AB14

VCCP_088

VCCP_089

VCC_168

VCC_169

T16

AB12

AC13

VCCP_090

VCC_170

V18

V16

AC11

VCCP_091

VCCP_092

VCC_171

VCC_172

P20

AD14

AB10

VCCP_093

VCC_173

T20

V20

AE13

VCCP_094

VCCP_095

VCC_174

VCC_175

Y18

AE11

AF14

VCCP_096

VCC_176

Y16

AB18

AF12

VCCP_097

VCCP_098

VCC_177

VCC_178

AB16

AG13

AG11

VCCP_099

VCC_179

AD18

AD16

AH14

VCCP_100

VCCP_101

VCC_180

VCC_181

Y20

AJ13

AJ11

VCCP_102

VCC_182

AB20

AD20

AF10

VCCP_103

VCCP_104

VCC_183

VCC_184

AF18

AK14

AK12

VCCP_105

VCC_185

AF16

AH18

AL13

VCCP_106

VCCP_107

VCC_186

VCC_187

AH16

AL11

AN13

VCCP_108

VCC_188

AF20

AH20

AN11

VCCP_109

VCCP_110

VCC_189

VCC_190

AK18

AP12

AR13

VCCP_111

VCC_191

AK16

AM18

AR11

VCCP_112

VCCP_113

VCC_192

VCC_193

AM16

AK10

AP10

VCCP_114

VCC_194

AP18

AP16

AU13

VCCP_115

VCCP_116

VCC_195

VCC_196

AK20

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

VCC_204

VCC_205

AT18

AT16

AP20

AM20

AT20

AV18

AV16

AY18

AY16

VCC_206

AV20

AA9

VCC_207

AY20

BB18

AA7

VCCP_129

VCC_208

VCC_209

BB16

AC9

AC7

VCCP_130

VCC_210

BD18

BD16

AE9

AE7

VCCP_131

VCCP_132

VCC_211

VCC_212

BB20

BD20

AG9

VCCP_133

VCCP_134

VCC_213

VCC_214

AM14

AG7

AJ9

VCCP_135

VCC_215

AT14

AP14

AJ7

AL9

VCCP_136

VCCP_137

VCC_216

VCC_217

AV14

AY14

AL7

AN9

VCCP_138

VCCP_139

VCC_218

VCC_219

BB14

BD14

AN7

VCCP_140

VCCP_141

VCC_220

+VCCP

AR9

AR7

A33

A13

VCCP_142

VCCP_143

VCCP_144

VCCP_145

VCCP_020

VCCP_018

VCCP_019

VCCP_017

AJ37

AF38

AK38

AG37

U1F

U1F PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

+CPU_CORE +VCCP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-Power

NCL20 M/B LA-5631P Schematic

0.1

641Tuesday, October 20, 2009

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

+CPU_CORE

10U_0603_6.3V6MC810U_0603_6.3V6M

Mid Frequence Decoupling

10U_0603_6.3V6MC910U_0603_6.3V6M

10U_0603_6.3V6M

C10

10U_0603_6.3V6M

C11

10U_0603_6.3V6M

C12

C13

10U_0603_6.3V6M

C15

C14

10U_0603_6.3V6M

C16

10U_0603_6.3V6M

C17

C18

10U_0603_6.3V6M

C19

C20

10U_0603_6.3V6M

C22

C21

10U_0603_6.3V6M

C23

10U_0603_6.3V6M

C24

C25

10U_0603_6.3V6M

C27

C26

10U_0603_6.3V6M

C28

C29

10U_0603_6.3V6M

C31

C30

Replace 10uF_0805 to 10uF_0603.071309.

+CPU_CORE

High Frequence Decoupling

1U_0402_6.3V6K

C33

C32

1U_0402_6.3V6K

C34

C35

1U_0402_6.3V6K

C36

C37

1U_0402_6.3V6K

C38

1U_0402_6.3V6K

C39

C40

1U_0402_6.3V6K

C42

C41

1U_0402_6.3V6K

C43

1U_0402_6.3V6K

C44

C45

1U_0402_6.3V6K

C47

C46

1U_0402_6.3V6K

C49

C48

1U_0402_6.3V6K

C51

C50

1U_0402_6.3V6K

C53

C52

1U_0402_6.3V6K

C55

C54

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+CPU_CORE

220U_D2_2VK_R9

C56

C57

Del C37 to improve power plan. 6/14

+VCCP

1U_0402_6.3V6K

C59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

C61

C60

1U_0402_6.3V6K

Compal Secret Data

C63

C62

Deciphered Date

1U_0402_6.3V6K

C64

220U_D2_2VK_R9

C58

1U_0402_6.3V6K

C65

1U_0402_6.3V6K

C66

C67

C68

1U_0402_6.3V6K

C70

C69

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-GND/Bypass

NCL20 M/B LA-5631P Schematic

0.1

741Tuesday, October 20, 2009

U3A

H_D#[0..63](5)

D D

C C

H_RESET#(4)

H_CPUSLP#(5)

layout note:

B B

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

trace width and spacing is 10/20

+VCCP

1K_0402_1%

R592K_0402_1% R592K_0402_1%

A A

Trace < = 500mils

Layout Note: H_RCOMP / H_VREF / H_SWNG

R55

H_VREF

C78

0.1U_0402_16V4Z

within 100 mils from NB

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWNG H_RCOMP

H_VREF

H_RCOMP

R60

24.9_0402_1%

U3A

H_D#_0

H_D#_1

L11

H_D#_2

H_D#_3

H_D#_4

H_D#_5

K10

H_D#_6

K12

H_D#_7

H_D#_8

M10

H_D#_9

H_D#_10

N11

H_D#_11

H_D#_12

H_D#_13

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

P10

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

H_D#_27

V10

H_D#_28

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

H_SWING

H_RCOMP

J11

H_CPURST#

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

R56

221_0603_1%

R61

100_0402_1%

0.1U_0402_16V4Z

Near B6 pin

H_SWNG

C79

H_ADSTB#_0 H_ADSTB#_1

H_DEFER#

HOST

HPLL_CLK#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

layout note: Place them close to U4 pin BC51.

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31

H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR# H_BPRI#

H_BREQ# H_DBSY#

HPLL_CLK H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

TSATN#

L15 B14 C15 D12 F14 G17 B12 J15 D16 C17 D14 K16 F16 B16 C21 D18 J19 J21 B18 D22 G19 J17 L21 L19 G21 D20 K22 F18 K20 F20 F22 B20 A19

F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

R327

1 2

330_0402_5%

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

+3VS

H_A#[3..35] (4)

H_ADS# (4) H_ADSTB#0 (4) H_ADSTB#1 (4) H_BNR# (4) H_BPRI# (4) H_BR0# (4) H_DEFER# (4) H_DBSY# (4) CLK_MCH_BCLK (16) CLK_MCH_BCLK# (16) H_DPWR# (5) H_DRDY# (4) H_HIT# (4) H_HITM# (4) H_LOCK# (4) H_TRDY# (4)

H_DINV#0 (5) H_DINV#1 (5) H_DINV#2 (5) H_DINV#3 (5)

H_DSTBN#0 (5) H_DSTBN#1 (5) H_DSTBN#2 (5) H_DSTBN#3 (5)

H_DSTBP#0 (5) H_DSTBP#1 (5) H_DSTBP#2 (5) H_DSTBP#3 (5)

H_REQ#0 (4) H_REQ#1 (4) H_REQ#2 (4) H_REQ#3 (4) H_REQ#4 (4)

H_RS#0 (4) H_RS#1 (4) H_RS#2 (4)

+V_DDR_MCH_REF

R326

R326 1K_0402_5%

1K_0402_5%

Q2 MMBT3904_SOT23-3

MMBT3904_SOT23-3

3 1

Add them for Boundary Scan. 10/23

R38 1K_0402_5%@R38 1K_0402_5%@

1 2

R39 4.7K_0402_5%@R39 4.7K_0402_5%@

1 2

R40 4.7K_0402_5%@R40 4.7K_0402_5%@

1 2

R41 1K_0402_5%@R41 1K_0402_5%@

1 2

C71

C72

2.2U_0603_6.3V4Z

SMRCOMP_VOH

SMRCOMP_VOL

C74

C73

2.2U_0603_6.3V4Z

PM_BMBUSY#(19)

H_DPRSTP#(5,18,40) PM_EXTTS#0(14) PM_EXTTS#1(15)

PLT_RST#(17,29)

1 2

R51 0_0402_5%R51 0_0402_5%

Add R428 in 9/26

DDR3

1K_0402_5%

1K_0402_5% R54

R54

1K_0402_5%

1K_0402_5% R57

R57

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_THERMTRIP#(4,18)

PM_DPRSLPVR(19,40)

C77

0.1U_0402_16V4Z

+3VS

R325

R325 1K_0402_5%

1K_0402_5%

Q1 MMBT3904_SOT23-3

MMBT3904_SOT23-3

3 1

+3VS

+1.5V

MCH_TSATN_EC# (29)

U3B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

TCK TDI TDO TMS

+1.5V

DDR3

R42

0.01U_0402_25V7K

0.01U_0402_25V7K 1K_0402_1%

1K_0402_1%

R45

3.01K_0402_1%

R48

R48 1K_0402_1%

1K_0402_1%

0.01U_0402_25V7K

MCH_CLKSEL0(16) MCH_CLKSEL1(16) MCH_CLKSEL2(16)

T30T30

T31T31

CFG5(10) CFG6(10) CFG7(10)

T32T32

CFG9(10)

CFG10(10)

T33T33

CFG12(10) CFG13(10)

T34T34

T35T35

CFG16(10)

T36T36

T37T37

CFG19(10) CFG20(10)

PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK

R50 100_0402_1%R50 100_0402_1%

1 2

C750.1U_0402_16V4Z@ C750.1U_0402_16V4Z@

2009/02/27 2009/02/20

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

NC_22

CANTIGA GMCH SFF_FCBGA1363

Compal Secret Data

Deciphered Date

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST# DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2

CFGRSVD

DMI_TXN_3 DMI_TXP_0

DMI_TXP_1

DMI

DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

SMRCOMP

BL25

SMRCOMP#

BK26

SMRCOMP_VOH

BK32

SMRCOMP_VOL

BL31

+V_DDR_MCH_REF

BC51

SM_PWROK

AY37

SM_REXT

BH20

SM_DRAMRST#

BA37 B42

D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

R455

1 2

100K_0402_5%

G39

Refer to spec. pull low 100k.062909

AK52 AK54

M_PWROK

AW40 AL53

CL_VREF

AL55

F34 F32

SDVO_SCLK

B38

SDVO_SDAT

A37 C31 K42

TSATN#

D10

C29 B30 D28 A27 B28

Title

Size Document Number Rev

Custom

Date: Sheet

R43 80.6_0402_1%R43 80.6_0402_1% R44 80.6_0402_1%R44 80.6_0402_1%

D2 CH751H-40_SC76D2 CH751H-40_SC76 R26

R26 R46 10K_0402_1%@R46 10K_0402_1%@

R47 499_0402_1%R47 499_0402_1%

CLK_DREF_96M (16) CLK_DREF_96M# (16) CLK_DREF_SSC (16) CLK_DREF_SSC# (16)

CLK_MCH_3GPLL (16) CLK_MCH_3GPLL# (16)

DMI_TXN0 (19) DMI_TXN1 (19) DMI_TXN2 (19) DMI_TXN3 (19)

DMI_TXP0 (19) DMI_TXP1 (19) DMI_TXP2 (19) DMI_TXP3 (19)

DMI_RXN0 (19) DMI_RXN1 (19) DMI_RXN2 (19) DMI_RXN3 (19)

DMI_RXP0 (19) DMI_RXP1 (19) DMI_RXP2 (19) DMI_RXP3 (19)

VGATE(16,19,40)

M_PWROK(19)

T38T38

T39T39

SDVO_SCLK (24) SDVO_SDAT (24)

MCH_CLKREQ# (16)

MCH_ICH_SYNC# (19)

R58 54.9_0402_1%R58 54.9_0402_1%

1 2

HDA_BITCLK_MCH HDA_RST#_MCH HDA_SDIN2_MCH HDA_SDOUT_MCH HDA_SYNC_MCH

PM_EXTTS#0 PM_EXTTS#1

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

NCL20 M/B LA-5631P Schematic

M_CLK_DDR0 (14) M_CLK_DDR1 (14) M_CLK_DDR2 (15) M_CLK_DDR3 (15)

M_CLK_DDR#0 (14) M_CLK_DDR#1 (14) M_CLK_DDR#2 (15) M_CLK_DDR#3 (15)

DDR_CKE0_DIMMA (14) DDR_CKE1_DIMMA (14) DDR_CKE2_DIMMB (15) DDR_CKE3_DIMMB (15)

DDR_CS0_DIMMA# (14) DDR_CS1_DIMMA# (14) DDR_CS2_DIMMB# (15) DDR_CS3_DIMMB# (15)

M_ODT0 (14) M_ODT1 (14) M_ODT2 (15) M_ODT3 (15)

1 2 1 2

2 1

1 2

0_0402_5%

1 2 1 2

SM_DRAMRST# (14,15)

VGATE M_PWROK

DFGT_VID_0 (39) DFGT_VID_1 (39) DFGT_VID_2 (39) DFGT_VID_3 (39) DFGT_VID_4 (39)

GFXVR_EN (39)

CL_CLK0 (19) CL_DATA0 (19)

CL_RST# (19)

0.1U_0402_16V4Z

R313

1 2

33_0402_5%

R62 10K_0402_5%R62 10K_0402_5%

1 2

R63 10K_0402_5%R63 10K_0402_5%

1 2

SYSON (29,31,37) DDR3_PG (37)

add it for change to use DDR3.070309

GMCH_PWROK

1 2

R106 0_0402_5%@R106 0_0402_5%@

1 2

R107 0_0402_5%R107 0_0402_5%

add it.062309

Modify in 9/26

+VCCP

C76

+VCCP

HDA_BITCLK_MCH (18) HDA_RST#_MCH (18)

HDA_SDIN2 (18) HDA_SDOUT_MCH (18) HDA_SYNC_MCH (18)

841Tuesday, October 20, 2009

+1.5V

DDR3

R52

R52 1K_0402_1%

1K_0402_1%

R53

R53 499_0402_1%

499_0402_1%

Change from 511 to 499.070709.

+3VS

0.1

D D

DDR_A_D[0..63](14)

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 (14) DDR_A_BS1 (14) DDR_A_BS2 (14)

DDR_A_RAS# (14) DDR_A_CAS# (14)

DDR_A_WE# (14)

DDR_A_DM[0..7] (14)

DDR_A_DQS[0..7] (14)

DDR_A_DQS#[0..7] (14)

DDR_A_MA[0..14] (14)

DDR_B_D[0..63](15)

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U3E

AP54 AM52 AR55 AV54

AM54

AN53 AT52 AU53

AW53

AY52 BB52 BC53 AV52

AW55

BD52 BC55 BF54 BE51 BH48 BK48 BE53 BH52 BK46

BJ47

BL45

BJ45 BL41 BH44 BH46 BK44 BK40

BJ39 BK10 BH10

BK6 BH6

BJ9

BL11

BG5

BJ5 BG3 BF4 BD4 BA3 BE5 BF2 BB4 AY4 BA1 AP2 AU1 AT2 AT4 AV4 AU3 AR3 AN1 AP4

AL3

AJ1 AK4 AM4 AH2 AK2

CANTIGA GMCH SFF_FCBGA1363

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS#0

DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 (15) DDR_B_BS1 (15) DDR_B_BS2 (15)

DDR_B_RAS# (15) DDR_B_CAS# (15) DDR_B_WE# (15)

DDR_B_DM[0..7] (15)

DDR_B_DQS[0..7] (15)

DDR_B_DQS#[0..7] (15)

DDR_B_MA[0..14] (15)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

NCL20 M/B LA-5631P Schematic

0.1

941Tuesday, October 20, 2009

DPST_PWM(22)

ENBKL(29)

+3VS

LVDS_DDC2_CLK(22) LVDS_DDC2_DATA(22)

D D

GMCH_ENVDD(22)

LVDS_A_C-(22) LVDS_A_C+(22)

LVDS_A_0-(22) LVDS_A_1-(22) LVDS_A_2-(22)

LVDS_A_0+(22) LVDS_A_1+(22) LVDS_A_2+(22)

R65 10K_0402_5%R65 10K_0402_5%

1 2

R66 10K_0402_5%R66 10K_0402_5%

1 2

Change from 4.22k to2.4k 072709.

R67 2.4K_0402_1%R67 2.4K_0402_1%

1 2

T42T42

LVDS_A_CLVDS_A_C+

LVDS_A_0LVDS_A_1LVDS_A_2-

LVDS_A_0+ LVDS_A_2+

D38 C37 K38

L37 J37 L35

B36 F50 H46 P44 K46 D46 B46 D44 B44

G45

F46

G41

C45 F44

G47

F40 A45

B40 A41 F42 D48

D40 C41

G43

B48

For EMI. 9/26

R68 75_0402_5%R68 75_0402_5%

1 2

R69 75_0402_5%R69 75_0402_5%

C C

1 2

R70 75_0402_5%R70 75_0402_5%

1 2

Del TV_LUMA & CRMA in 10/12.

Change to mount 072709.

J27 E27

G27

F26

B34 D34

Tie to GND. 9/28

R15

150_0402_1%

R16

GMCH_CRT_B GMCH_CRT_G GMCH_CRT_R

CRT_HSYNC_R CRT_VSYNC_R

1.02K_0402_1%

GMCH_CRT_B GMCH_CRT_G GMCH_CRT_R

150_0402_1%

GMCH_CRT_B(23) GMCH_CRT_G(23) GMCH_CRT_R(23)

GMCH_CRT_CLK(23)

GMCH_CRT_DATA(23)

GMCH_CRT_HSYNC(23) GMCH_CRT_VSYNC(23)

B B

A A

R71 30.1_0402_1%R71 30.1_0402_1% R73 30.1_0402_1%R73 30.1_0402_1%

Close to pin D32 and keep 30mil space to other part/trace.

1 2 1 2

R13

GMCH_CRT_CLK GMCH_CRT_DATA

150_0402_1%

J29

G29

F30 E29 D36

C35 J33 D32

G31

R76

1 2

U3C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK

CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

PEGCOMP trace width and spacing is 20/25 mils.

PEGCOMP

U45

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T44

D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

+3VS

R559 2.2K_0402_5%R559 2.2K_0402_5% R560 2.2K_0402_5%R560 2.2K_0402_5%

R561 2.2K_0402_5%

R561 2.2K_0402_5% R562 2.2K_0402_5%

R562 2.2K_0402_5%

Nu it 101309.

1 2

R469 100K_0402_5%R469 100K_0402_5%

PEG_COMPO

LVDS

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

VGA

1 2

R64 49.9_0402_1%R64 49.9_0402_1%

layout note: Place R64 <500mils to U4 pin U45&T44.

HDMI_HPD#LVDS_A_1+

HDMI_C_TX2HDMI_C_TX1HDMI_C_TX0HDMI_C_CLK-

HDMI_C_TX2+ HDMI_C_TX1+ HDMI_C_TX0+ HDMI_C_CLK+

1 2 1 2

1 2

ENBKL

+VCC_PEG

C1036 0.1U_0402_16V4ZC1036 0.1U_0402_16V4Z

1 2

C1037 0.1U_0402_16V4ZC1037 0.1U_0402_16V4Z

1 2

C1038 0.1U_0402_16V4ZC1038 0.1U_0402_16V4Z

1 2

C1039 0.1U_0402_16V4ZC1039 0.1U_0402_16V4Z

1 2

C1040 0.1U_0402_16V4ZC1040 0.1U_0402_16V4Z

1 2

C1041 0.1U_0402_16V4ZC1041 0.1U_0402_16V4Z

1 2

C1042 0.1U_0402_16V4ZC1042 0.1U_0402_16V4Z

1 2

C1043 0.1U_0402_16V4ZC1043 0.1U_0402_16V4Z

1 2

LVDS_DDC2_CLK LVDS_DDC2_DATA

GMCH_CRT_CLK GMCH_CRT_DATA

HDMI_HPD# (24)

TX2D- (24) TX1D- (24) TX0D- (24) TXCD- (24)

TX2D+ (24) TX1D+ (24) TX0D+ (24) TXCD+ (24)

CFG[2:0] FSB Freq select

CFG[4:3]

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11 CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

Strap Pin Table

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved

Reserved 0 = DMI x 2

1 = DMI x 4 0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable 0 =(TLS)chiper suite with no confidentiality 1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1 1 = Normal Operation,Lane Number in order

0 = Enable 1 = Disable Reserved 00 = Reserved

01 = XOR Mode Enabled 10 = All Z Mode Enabled

ReservedCFG[15:14]

0 = Disabled 1 = Enabled

ReservedCFG[18:17]

0 = Normal Operation

1 = Reverse Lane

0 = Only PCIE or SDVO is operational. 1 = PCIE/SDVO are operating simu.

CFG5(8) CFG6(8) CFG7(8)

CFG9(8) CFG10(8) CFG12(8) CFG13(8) CFG16(8)

CFG19(8) CFG20(8)

(Lane number in Order)

R72 2.21K_0402_1%@R72 2.21K_0402_1%@

1 2

R74 2.21K_0402_1%@R74 2.21K_0402_1%@

1 2

R75 2.21K_0402_1%@R75 2.21K_0402_1%@

1 2

R77 2.21K_0402_1%@R77 2.21K_0402_1%@

1 2

R78 2.21K_0402_1%@R78 2.21K_0402_1%@

1 2

R79 2.21K_0402_1%@R79 2.21K_0402_1%@

1 2

R80 2.21K_0402_1%@R80 2.21K_0402_1%@

1 2

R81 2.21K_0402_1%@R81 2.21K_0402_1%@

1 2

R82 4.02K_0402_1%@R82 4.02K_0402_1%@

1 2

R83 4.02K_0402_1%@R83 4.02K_0402_1%@

1 2

(Default)11 = Normal Operation

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

NCL20 M/B LA-5631P Schematic

10 41Tuesday, October 20, 2009

0.1

+3VS

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

D D

C89

install 0.1U & 10U for wavy issue. 7/29

change 0.1U to 22U for wavy issue. 5/20

+1.5VS

C C

B B

+1.05VM_HPLL

+3VS_DAC_CRT

R86

10U_0603_6.3V

0.1U_0402_16V4Z

C90

C91

R94 0_0603_5%R94 0_0603_5%

1 2

9/27

+VCCP

+1.05VM_PEGPLL

9/27

C125

0.1U_0402_16V4Z

0.01U_0402_16V7K

+3VS

R87

C92

0.1U_0402_16V4Z

R97 0_0805_5%R97 0_0805_5%

C146

220U_D2_4VM_R15

Change to use 220uf_D2 090909.

R100 0_0805_5%R100 0_0805_5%

R87

BLM18PG181SN1D_0603

+1.5VS_PEG_BG

C105

1 2

R102 0_0603_5%R102 0_0603_5%

+1.8V

C126

0.1U_0402_16V4Z

+1.8V_TXLVDS

9/27

+3VS_DAC_BG

22U_0805_6.3V

C93

C102

C102 1000P_0402_50V7K

1000P_0402_50V7K

10U_0805_6.3V6M

0.01U_0402_16V7K

9/27

C94

+1.05VM_DPLLA

+1.05VM_DPLLB

+1.05VM_HPLL +1.05VM_MPLL

+1.05VM_PEGPLL

+1.05VM_A_SM

1U_0603_10V4Z

4.7U_0805_10V4Z

C111

C112

+1.05VM_A_SM_CK

10U_0805_6.3V6M

0.1U_0402_16V4Z

C119

C120

C113

1U_0603_10V4Z

C127

AW24 AW22

AW20 AW18 AW16

AW14

+1.8V_LVDS

M33

AF10

AE1

U43 U41

AJ43

AG43

AU24 AU22

AU21 AU19 AU18 AU16

AT16 AR16 AU15 AT15 AR15

AT24 AR24 AT22 AR22 AT21 AR21 AT19 AR19 AT18 AR18

AU27 AU28 AU29 AU31 AT31 AR31 AT29 AR29 AT28 AR28 AT27 AR27

AH12 AE43

M46

J31

L31

J45 L49

V44

L45

U3H

VCCA_CRT_DAC

VCCA_DAC_BG VSSA_DAC_BG

VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL

VCCA_LVDS1 VCCA_LVDS2

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_12 VCCA_SM_13 VCCA_SM_14 VCCA_SM_15 VCCA_SM_16 VCCA_SM_17

VCCA_SM_NCTF_1 VCCA_SM_NCTF_2 VCCA_SM_NCTF_3 VCCA_SM_NCTF_4 VCCA_SM_NCTF_5 VCCA_SM_NCTF_6 VCCA_SM_NCTF_7 VCCA_SM_NCTF_8 VCCA_SM_NCTF_9 VCCA_SM_NCTF_10

VCCA_SM_CK_4 VCCA_SM_CK_3 VCCA_SM_CK_2 VCCA_SM_CK_1 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

VCCD_HPLL VCCD_PEG_PLL

VCCD_LVDS_1 VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13

VTT

VCCA_TV_DAC

TVD TV/CRT

VCC_HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

Change to 330u_R9, casue high limitation. 12/14

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

R92

+VCC_HDA

0_0402_5%

A31

1 2

N34

+1.5VS_QDAC

N32

+1.5VS_TVDAC

9/27

M25 N24 M23

BK24 BL23 BJ23 BK22

T41 C33

A33

AB44 Y44 AC43 AA43

AM44 AN43 AL43

K14 Y12 P2

+1.5V_SM_CK

0.47U_0603_10V7K

C128

+V1.05VM_AXF

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

0.47U_0603_10V7K

2.2U_0805_16V4Z

C85

9/29

0.47U_0603_10V7K

C129

4.7U_0805_10V4Z

C87

C86

+3VS_TVDAC

0.01U_0402_16V7K

Disable HDMI audio

+VCC_HDA

R321 0_0603_5%R321 0_0603_5%

0.1U_0402_16V4Z

C1045

DDR3

+3VS_HV

0.1U_0402_16V4Z

C121

C130

C88

C100

+VCCP

C84

0.1U_0402_16V4Z

1 2

330U_D2E_2.5VM_R9

R91

1 2

BLM18PG181SN1D_0603

C101

Enable HDMI audio

+VCCP

9/27

+3VS

+1.5VS

9/27

2 1

D1 CH751H-40_SC76D1 CH751H-40_SC76

+3VS

+1.05VM_DPLLA +VCCP

BLM18PG181SN1D_0603

22U_0805_6.3V

C80

C81

0.1U_0402_16V4Z

+1.05VM_DPLLB

BLM18PG181SN1D_0603

22U_0805_6.3V

C95

C96

0.1U_0402_16V4Z

+1.05VM_HPLL

1 2

BLM18PG181SN1D_0603

C103

C104

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+1.05VM_MPLL

1 2

BLM18PG181SN1D_0603

C106

C107

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.8V_TXLVDS +1.8V

+1.05VM_PEGPLL

R98 0_0603_5%R98 0_0603_5%

C115

C114

1000P_0402_50V7K

BLM18PG121SN1D_0603

10U_0805_10V4Z

0.1U_0402_16V4Z

C123

C122

+VCCP_D

R103 10_0402_5%R103 10_0402_5%

1 2

+1.5VS_QDAC

0.1U_0402_16V4Z

0.01U_0402_16V7K

C132

C131

1 2

10U_0805_6.3V6M@

1 2

4.7U_0603_6.3V

C133

R84

1 2

R88

1 2

9/27

+VCCP

R93

9/27

+VCCP

R95

9/27

+VCCP

1 2

BLM18PG181SN1D_0603

9/27

+VCCP

9/29

R104 0_0402_5%R104 0_0402_5%

R105

+V1.05VM_AXF

10U_0805_10V4Z

C82

+1.5V_SM_CK

0.1U_0402_16V4Z

R90

0_0603_5%

1 2

10U_0603_6.3V6M

C99

+1.5VS_TVDAC

0.1U_0402_16V4Z

0.01U_0402_16V7K

C108

+VCC_PEG

10U_0805_6.3V6M

4.7U_0805_10V4Z

220U_D2_4VM_R15

C118

C117

+1.05VM_DMI

R101 0_0603_5%R101 0_0603_5%

1 2

0.1U_0402_16V4Z

C124

1 2

+1.5VS

R85 0_0603_5%R85 0_0603_5%

1 2

1U_0603_10V4Z

C83

DDR3

R89 0_0603_5%R89 0_0603_5%

1 2

Change package 081709.

10U_0603_6.3V6M

C98

C97

R96

1 2

BLM18PG181SN1D_0603

C109

R99 0_0805_5%R99 0_0805_5%

1 2

C116

9/21

+3VS_HV

+VCCP

9/27

+VCCP

+1.5V

+1.5VS

9/21

+VCCP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

install 4.7U for wavy issue. 7/29

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(4/6)-PWR

NAV30 M/B LA-5451P Schematic

0.1

11 41Tuesday, October 20, 2009

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

U3F

9/21

C144

+VCCP

0.1U_0402_16V4Z

C145

D D

0.22U_0402_10V4Z

330U_D2E_2.5VM_R9

10U_0805_6.3V6M

C141

C C

B B

A A

0.22U_0402_10V4Z

C142

C143

U3F

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

W41

VCC_9

AT40

VCC_10

AM40

VCC_11

AL40

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38

AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

9/21

+VCCP

+1.5V

Change to D2 size.073109.

C110

330U_D2E_2.5VM_R9

C110

+VCCGFX

DDR3

330U_B2_2.5VM_R15M

C147

10U_0805_6.3V

C137

10U_0805_6.3V6M

C138

C148

10U_0805_6.3V

0.01U_0402_16V7K

10U_0805_6.3V6M

C139

C149

C150

1U_0603_10V4Z

6326.84mA

T43PAD T43PAD T44PAD T44PAD

3000mA

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61

VCC_AXG_SENSE VSS_AXG_SENSE

VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23

POWER

VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31

VCC SMVCC GFX

VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39

VCC GFX NCTF

VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9

VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

AU45 BF52 BB38 BA19 BE9 AU9 AL9

+VCCGFX

change from +VCCP to +VCCGFX 062909.

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

U3G

BB36

BE35 AW34 AW32

BK30

BH30

BF30

C140

BD30

BB30 AW30

BL29

BJ29 BG29 BE29 BC29 BA29 AY29 BK28 BH28 BF28 BD28 BB28 BL27

BJ27 BG27 BE27 BC27 BA27 AY27

AW26

BF24 BL19 BB16

W32 AG31 AE31 AD31 AC31 AA31

Y31

W31 AH29

0.1U_0402_16V4Z

AG29 AE29 AD29 AC29 AA29

Y29

W29 AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27

Y27

W27 AH25 AD25 AC25

W25

AJ24 AH24 AG24 AE24 AD24 AC24 AA24

Y24

W24

AM22

AL22

AJ22 AH22 AG22 AE22 AD22 AC22 AA22

AM21

AL21

AJ21 AH21 AD21 AC21 AA21

Y21

W21

AM16

AL16

AG13 AE13

C134

0.1U_0402_16V4Z

C156 0.1U_0402_16V4ZC156 0.1U_0402_16V4Z

C135

C136

4.7U_0805_10V4Z

0.22U_0402_10V4Z

C157 0.1U_0402_16V4ZC157 0.1U_0402_16V4Z

C151 0.22U_0603_10V7KC151 0.22U_0603_10V7K

C152 0.22U_0603_10V7KC152 0.22U_0603_10V7K

C155 1U_0603_10V4ZC155 1U_0603_10V4Z

C154 1U_0603_10V4ZC154 1U_0603_10V4Z

C153 0.47U_0402_6.3V6KC153 0.47U_0402_6.3V6K

CANTIGA GMCH SFF_FCBGA1363

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

NCL20 M/B LA-5631P Schematic

0.1

12 41Tuesday, October 20, 2009

U3I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51

VSS_34

N51

VSS_35

L51

VSS_36

J51

VSS_37

G51

VSS_38

C51

VSS_39

BK50

VSS_40

AM50

VSS_41

K50

VSS_42

BG49

VSS_43

E49

VSS_44

C49

VSS_45

BD48

VSS_46

BB48

VSS_47

AY48

VSS_48

AV48

VSS_49

AT48

VSS_50

AP48

VSS_51

AM48

VSS_52

AK48

VSS_53

AH48

VSS_54

AF48

VSS_55

AD48

VSS_56

AB48

VSS_57

Y48

VSS_58

V48

VSS_59

T48

VSS_60

P48

VSS_61

M48

VSS_62

K48

VSS_63

H48

VSS_64

BL47

VSS_65

BG47

VSS_66

E47

VSS_67

C47

VSS_68

A47

VSS_69

BD46

VSS_70

AY46

VSS_71

AM46

VSS_72

AK46

VSS_73

AH46

VSS_74

BG45

VSS_75

AE45

VSS_76

AC45

VSS_77

AA45

VSS_78

W45

VSS_79

R45

VSS_80

N45

VSS_81

E45

VSS_82

BD44

VSS_83

BB44

VSS_84

AV44

VSS_85

AK44

VSS_86

AH44

VSS_87

AF44

VSS_88

AD44

VSS_89

K44

VSS_90

H44

VSS_91

BL43

VSS_92

BG43

VSS_93

AY43

VSS_94

AR43

VSS_95

W43

VSS_96

R43

VSS_97

M43

VSS_98

E43

VSS_99

CANTIGA GMCH SFF_FCBGA1363

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

U3J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19

AY19

M19

BD18

BL17

BG17

AY17

M17

BD16 AN16 AG16

AE16

W16

BG15

AY15 AN15 AD15 AC15

M15

BD14

BL13 BG13

AY13 AU13 AR13

AJ13 AC13

AA13

W13 M13

BD12

AV12

AP12 AM12

AK12

AB12

BG11 AG11

BD10

AY10

AP10

BG9

BD8

E19 N18

H18

E17 A17

Y16 N16

H16

R15 E15 H14

U13 E13

A13

V12 P12 H12

E11

H10 BL9

E9 A9

BB8 AY8 AV8 AT8 AP8

VSS

VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12

VSS NCTF

VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

VSS SCB

VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358

VSS_359 VSS_360 VSS_361 VSS_362

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

BL55 BL1 A55 D1 B55 B2 A4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/02/27 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

NCL20 M/B LA-5631P Schematic

0.1

13 41Tuesday, October 20, 2009

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