Compal LA-5581P, IdeaPad U450 Schematic

ZZZ

PCB_LS5581P

Part Number = DA80000FB20

1 1

Compal confidential

Schematics Document

Mobile Penryn ULV singal/dual

2 2

core with Intel Cantiga_GS45/GS40 +ICH9-M SFF core logic

3 3

ULV core logic board

009-07-23

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LS-5581P

2.0

1 30Thursday, July 23, 2009

1 1

2 2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LS-5581P

2.0

2 30Tuesday, July 21, 2009

Voltage Rails

State

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

( O MEANS ON X MEANS OFF )

+3VL

power plane

Descrebtion

+5VALW

+3VALW

+1.5V

X X

X X X

Descrebtion

+5VS

+3VS

+1.5VS

+0.75V

+VCCP

+CPU_CORE

SMBUS Control Table

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2 SMB_EC_DA2

SMB_CK_CLK1 SMB_CK_DAT1 ICH9

LCD_CLK LCD_DAT

Descrebtion

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build CONN@ : means ME part. 45@ : means install after SMT.

SOURCE

KB926

INVERTER BATT EEPROM

X X

Cantiga

X X

SERIAL

V V

X X

THERMAL SENSOR (CPU)

X X

SODIMM CLK CHIP

MINI CARD

V V V

X X

LCD

X X X

USB port 0

USB port 1

USB port 2

USB port 3

USB port 4

USB port 5

USB port 6

USB port 7

USB port 8

USB connector

BT Module

cardreader

USB connector

WLAN Conn.

WWAN/SSD

USB connector

CMOS

Fingerprint

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

CLOCK GENERATOR (EXT.)

HEX ADDRESS

PCI-e port 0

PCI-e port 1

PCI-e port 2

PCI-e port 3

PCI-e port 4

PCI-e port 5

1 0 1 0 0 0 0 0

1 1 0 1 0 0 1 0

WLAN Conn.

LAN

SATA port 0

SATA port 1

SATA port 2

SATA HDD

WWAN/SSD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LS-5581P

3 30Tuesday, July 21, 2009

2.0

CPU SU2700

2700@

D D

CPU SU9600

9600@

CPU SU3500

3500@

CPU 743

743@

07/06 Add U1 SA00003BZ10 for 3500@

07/23 Add U1 SA00003IA50 for 7300@ Add U1 SA00003I950 for 4100@ Add U1 SA00003H060 for 2300@ Add U1 SA00003JO60 for 743@

H_A#[3..16]<8>

C C

H_ADSTB#0<8>

H_A#[17..35]<8>

B B

H_ADSTB#1<8>

H_FERR#<18>

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0<8> H_REQ#1<8> H_REQ#2<8> H_REQ#3<8> H_REQ#4<8>

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A20M#<18>

H_IGNNE#<18>

H_STPCLK#<18> H_INTR<18>

H_NMI<18> H_SMI#<18>

U1A

A[3]#

A[4]#

A[5]#

A[6]#

AA1

A[7]#

AB4

A[8]#

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

A20M#

FERR#

F10

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD01

RSVD02

AG5

RSVD03

AL5

RSVD04

RSVD05

RSVD06

RSVD07

PENRYN SFF_UFCBGA956

723@

07/06 Change U1 from SA000038J40 to SA000038J60

ADDR GROUP 0 ADDR GROUP 1

CONTROL

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

TDI

RESERVED

CPU SU7300

7300@

Place close to U1.

M4 J5 L5

N5 F38 J1

B40 D8

G5 K2 H4 K4 L1

H2 F2

AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 J7

D38

H_THERMDA_R

BB34

H_THERMDC_R

BD34

B10

A35 C35

CPU SU4100

4100@

H_ADS# <8> H_BNR# <8>

H_BPRI# <8>

H_DEFER# <8>

H_DRDY# <8> H_DBSY# <8>

H_BR0# <8>

H_INIT# <18>

H_LOCK# <8>

H_RESET#

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_RS#0 <8> H_RS#1 <8> H_RS#2 <8>

H_TRDY# <8>

H_HIT# <8> H_HITM# <8>

Place Close to U1.

R22 68_0402_5%R22 68_0402_5% R23 0_0402_5%R23 0_0402_5%

H_THERMTRIP#

R24 0_0402_5%R24 0_0402_5%

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

CPU SU2300

2300@

+VCCP

1 2

Add 0 ohm per EMI request. 10/17

XDP_DBRESET# <19>

H_PROCHOT# <28>

1 2 1 2 1 2

H_THERMTRIP# <8,18>

H_PROCHOT#

XDP_TDI

XDP_DBRESET#

XDP_TDO

XDP_TMS

XDP_TRST#

XDP_TCK

D9 PJDLC05_SOT23-3

PJDLC05_SOT23-3

R10

R10 51_0402_1%

51_0402_1%

1 2

56_0402_5%

C1046

0.1U_0402_16V4Z

+VCCP

H_THERMDA H_THERMDC

For ESD

H_RESET# <8>

For ESD

+3VS

0.1U_0402_16V4Z

C1035

1 2

2200P_0402_50V7K

R306

1 2

10K_0402_5%

C1034

H_THERMDA

H_THERMDC

THERM#

D10

D10 PJDLC05_SOT23-3

PJDLC05_SOT23-3

VDD

THERM#

EMC1402-1-ACZL-TR_MSOP8

SMDATA

D11

D11 PJDLC05_SOT23-3

PJDLC05_SOT23-3

SMCLK

ALERT#

GND

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TRST#

XDP_TCK

R305 10K_0402_5%

1 2

R1 54.9_0402_ 1%R1 54.9_0402_ 1%

1 2

R2 54.9_0402_ 1%R2 54.9_0402_ 1%

1 2

R3 54.9_0402_ 1%R3 54.9_0402_ 1%

1 2

R6 51_0 402_1%R6 51_0 402_1%

1 2

R7 54.9_0402_ 1%R7 54.9_0402_ 1%

1 2

This shall place near CPU

EC_SMB_CK2 <21>

EC_SMB_DA2 <21>

+3VS

+VCCP

Address:100_1100

C1057

For EMI

0.1U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

LS-5581P

2.0

4 30Thursday, July 23, 2009

H_D#[0..15]<8>

D D

H_DSTBN#0<8> H_DSTBP#0<8> H_DINV#0<8> H_D#[16..31]<8>

C C

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1<8> H_DSTBP#1<8> H_DINV#1<8>

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

V_CPU_GTLREF

T8T8

T9T9 T10T10

H_D#0 H_D#1

H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST2

TEST5 TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

0 1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

D[32]# D[33]# D[34]#

DATA GROUP 0

D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP# PSI#

Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02

AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

H_PSI#

H_D#33 H_D#34H_D#2 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_D#32

AP44

H_DPRSTP# <8,18,28>

H_DPSLP# <18> H_DPWR# <8> H_PWRGOOD <18>

H_CPUSLP# <8>

T11T11

H_D#[32..47] <8>

H_DSTBN#2 <8> H_DSTBP#2 <8> H_DINV#2 <8> H_D#[48..63] <8>

H_DSTBN#3 <8> H_DSTBP#3 <8> H_DINV#3 <8>

R33

R32

R31

R30

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

R27 0_0402_5%R27 0_0402_5%

1 2

J11

R28 0_0402_5% R28 0_0402_5%

1 2

E11

R29 0_0402_5% R29 0_0402_5%

1 2

G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP

330U_D2E_2.5VM_R9

CPU_VID0 <28> CPU_VID1 <28> CPU_VID2 <28> CPU_VID3 <28> CPU_VID4 <28> CPU_VID5 <28> CPU_VID6 <28>

VCCSENSE <28>

VSSSENSE <28>

Change to 330u_R9, casue high limitation. 12/14

+1.5VS

0.01U_0402_16V7K

Near pin B34

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R34

+VCCP

R36

R36 1K_0402_1%

1K_0402_1%

V_CPU_GTLREF

A A

R37

R37 2K_0402_1%

2K_0402_1%

1 2

100_0402_1%

R35

1 2

100_0402_1%

Close to CPU pin within 500mils.

VCCSENSE

VSSSENSE

Close to CPU pin AW43 within 500mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LS-5581P

5 30Thursday, July 23, 2009

2.0

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

M24

M22

AJ35

VCCP_040

VCCP_041

VCCP_042

VCCP_043

VCCP_044

VCCP_045

VCCP_046

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

V22

Y24

Y22

AB24

AB22

AD24

AD22

AF36

AL35

AN35

AK36

AP36

B12

B14

C13

D12

D14

E13

F14

F12

G13

H14

H12

J13

K14

K12

L13

L11

M14

N13

N11

K10

P14

P12

R13

R11

T14

U13

U11

V14

V12

VCCP_047

VCCP_048

VCCP_049

VCCP_050

VCCP_051

VCCP_052

VCCP_053

VCCP_054

VCCP_055

VCCP_056

VCCP_057

VCCP_058

VCCP_059

VCCP_060

VCCP_061

VCCP_062

VCCP_063

VCCP_064

VCCP_065

VCCP_066

VCCP_067

VCCP_068

VCCP_069

VCCP_070

VCCP_071

VCCP_072

VCCP_073

VCCP_074

VCCP_075

VCCP_076

VCCP_077

VCCP_078

VCCP_079

VCCP_080

VCCP_081

VCC_127

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_154

VCC_155

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

VCC_161

F18

F16

B16

B18

B20

AF24

AF22

AH24

AH22

AT24

AK24

AT22

AK22

AP24

AP22

AV24

AV22

AY24

AY22

AM24

AM22

BB24

D16

BB22

BD24

BD22

F20

K18

D18

K16

H18

H16

D20

H20

W13

W11

P10

V10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

AJ13

AJ11

AF10

AK14

AK12

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AK10

AP10

AU13

VCCP_082

VCCP_083

VCCP_084

VCCP_085

VCCP_086

VCCP_087

VCCP_088

VCCP_089

VCCP_090

VCCP_091

VCCP_092

VCCP_093

VCCP_094

VCCP_095

VCCP_096

VCCP_097

VCCP_098

VCCP_099

VCCP_100

VCCP_101

VCCP_102

VCCP_103

VCCP_104

VCCP_105

VCCP_106

VCCP_107

VCCP_108

VCCP_109

VCCP_110

VCCP_111

VCCP_112

VCCP_113

VCCP_114

VCCP_115

VCCP_116

VCC_162

VCC_163

VCC_164

VCC_165

VCC_166

VCC_167

VCC_168

VCC_169

VCC_170

VCC_171

VCC_172

VCC_173

VCC_174

VCC_175

VCC_176

VCC_177

VCC_178

VCC_179

VCC_180

VCC_181

VCC_182

VCC_183

VCC_184

VCC_185

VCC_186

VCC_187

VCC_188

VCC_189

VCC_190

VCC_191

VCC_192

VCC_193

VCC_194

VCC_195

VCC_196

T18

T16

K20

P18

M18

M16

M20

T20

P16

V18

V16

P20

V20

Y18

Y16

Y20

AF18

AF16

AB18

AB16

AD18

AD16

AF20

AB20

AD20

AK18

AK16

AP18

AP16

AH18

AH16

AH20

AK20

AM18

AM16

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

AT18

AT16

AP20

AV18

AV16

AY18

AM20

AY16

+VCCP

AA9

AA7

AC9

AC7

AE9

AE7

AG9

AG7

AJ9

AJ7

AL9

AL7

AN9

AN7

AR9

AR7

A33

A13

U1F

U1F PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCCP_129

VCCP_130

VCCP_131

VCCP_132

VCCP_133

VCCP_134

VCCP_135

VCCP_136

VCCP_137

VCCP_138

VCCP_139

VCCP_140

VCCP_141

VCCP_142

VCCP_143

VCCP_144

VCCP_145

VCC_204

VCC_205

VCC_206

VCC_207

VCC_208

VCC_209

VCC_210

VCC_211

VCC_212

VCC_213

VCC_214

VCC_215

VCC_216

VCC_217

VCC_218

VCC_219

VCC_220

VCCP_020

VCCP_018

VCCP_019

VCCP_017

AT20

AV20

AY20

BB18

BB16

AT14

BB20

AP14

BD18

AV14

BD16

BD20

AM14

AJ37

AF38

AY14

BB14

AK38

BD14

AG37

+VCC_CORE +VCCP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-Power

LS-5581P

2.0

6 30Tuesday, July 21, 2009

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

+VCC_CORE

10U_0603_6.3V6MC810U_0603_6.3V6M

+VCC_CORE

1U_0402_6.3V6K

C32

Mid Frequence Decoupling

10U_0603_6.3V6MC910U_0603_6.3V6M

10U_0603_6.3V6M

C10

1U_0402_6.3V6K

C34

C33

10U_0603_6.3V6M

C12

C11

High Frequence Decoupling

1U_0402_6.3V6K

C36

C35

10U_0603_6.3V6M

C13

C14

1U_0402_6.3V6K

C37

C38

10U_0603_6.3V6M

C16

C15

1U_0402_6.3V6K

C39

C40

10U_0603_6.3V6M

C18

C17

1U_0402_6.3V6K

C42

C41

10U_0603_6.3V6M

C19

1U_0402_6.3V6K

C43

C20

C21

C22

1U_0402_6.3V6K

C44

1U_0402_6.3V6K

C45

C46

10U_0603_6.3V6M

C23

C24

1U_0402_6.3V6K

C48

C47

10U_0603_6.3V6M

C25

1U_0402_6.3V6K

C49

10U_0603_6.3V6M

C26

C27

1U_0402_6.3V6K

C50

C51

10U_0603_6.3V6M

C28

C29

1U_0402_6.3V6K

C52

C53

10U_0603_6.3V6M

C31

C30

1U_0402_6.3V6K

C54

C55

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

C56

Del C37 to improve power plan. 6/14

+VCCP

1U_0402_6.3V6K

C59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

1U_0402_6.3V6K

C61

C60

1U_0402_6.3V6K

Compal Secret Data

C63

C62

Deciphered Date

1U_0402_6.3V6K

220U_D2_2VK_R9

C57

C64

220U_D2_2VK_R9

C58

1U_0402_6.3V6K

C66

C65

1U_0402_6.3V6K

C67

1U_0402_6.3V6K

C68

1U_0402_6.3V6K

C69

C70

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-GND/Bypass

LS-5581P

2.0

7 30Tuesday, July 21, 2009

U3A

H_D#[0..63]<5>

D D

C C

H_RESET#<4>

H_CPUSLP#<5>

layout note:

B B

Route H_SCOMP an d H_SCOMP# with trace width, spacing and impe dance (55 ohm) same as FSB data traces

trace width and spacing is 10/20

+VCCP

1K_0402_1%

R59

2K_0402_1%

A A

Trace < = 500mil s

Layout Note: H_RCOMP / H_VREF / H_SWNG

R55

H_VREF

C78

0.1U_0402_16V4Z

within 100 mils from NB

H_SWNG H_RCOMP

H_VREF

24.9_0402_1%

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_RCOMP

R60

U3A

H_D#_0

H_D#_1

L11

H_D#_2

H_D#_3

H_D#_4

H_D#_5

K10

H_D#_6

K12

H_D#_7

H_D#_8

M10

H_D#_9

H_D#_10

N11

H_D#_11

H_D#_12

H_D#_13

H_D#_14

H_D#_15

H_D#_16

H_D#_17

H_D#_18

H_D#_19

P10

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

H_D#_27

V10

H_D#_28

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

H_SWING

H_RCOMP

J11

H_CPURST#

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

221_0603_1%

100_0402_1%

R56

R61

0.1U_0402_16V4Z

Near B6 pin

H_SWNG

C79

H_ADSTB#_0 H_ADSTB#_1

HOST

HPLL_CLK#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

layout note:

Place them close to U4 pin BC51 .

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

PM_EXTTS#0

PM_EXTTS#1

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19

F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

DDR3_NB_REF

R62 10K_0402_5%

1 2

R63 10K_0402_5%R63 10K_0402_5%

1 2

Del R48. 9/27

H_A#[3..35] <4>

Add them for Bou ndary Scan. 10/ 23

R38 1K_0402_5%@R38 1K_0402_5%@ R39 4.7K_0402_5%@R39 4.7K_0402_5%@ R40 4.7K_0402_5%@R40 4.7K_0402_5%@ R41 1K_0402_5% @R41 1K_0402_5% @

SMRCOMP_VOH

SMRCOMP_VOL

R51 0_0402_5%R51 0_0402_5%

+1.5V

R54

R54 10K_0402_1%

10K_0402_1%

R57

R57 10K_0402_1%

10K_0402_1%

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

H_THERMTRIP#<4,18>

PM_DPRSLPVR<19,28>

C77

0.1U_0402_16V4Z

+3VS

1 2 1 2 1 2 1 2

+1.5V

C72

C71

2.2U_0603_6.3V4Z

PM_BMBUSY#<19>

H_DPRSTP#<5,18,28> PM_EXTTS#0<14> PM_EXTTS#1<15> PM_PWROK<19,21,28> PLT_RST#<17,21>

1 2

0.01U_0402_25V7K

C74

C73

0.01U_0402_25V7K

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

Add R428 in 9/26

T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19 T20T20

TCK TDI TDO TMS

T21T21 T22T22

T23T23

T24T24

R42

R42 1K_0402_1%

1K_0402_1%

R45

3.01K_0402_1%

R48

R48 1K_0402_1%

1K_0402_1%

CFG5<10> CFG6<10> CFG7<10>

CFG9<10>

CFG10<10>

CFG12<10> CFG13<10>

CFG16<10>

CFG19<10> CFG20<10>

PM_EXTTS#0 PM_EXTTS#1

R49 0_0402_5%R49 0_0402_5%

1 2

R50 100_0402_1% R50 100_0402_1%

1 2

T26T26 T27T27 T28T28

T30T30 T31T31

T32T32

T33T33

T34T34 T35T35

T36T36 T37T37

C750.1U_0402_16V4Z @ C7 50.1U_0402_16V4Z @

U3B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

NC_22

CANTIGA GMCH SFF_FCBGA1363

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2

DMI

GRAPHICS VID

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

HDA

DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

CFGRSVD

BL25 BK26

BK32 BL31

BC51 AY37 BH20 BA37

B42 D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

G39

AK52 AK54 AW40 AL53 AL55

F34 F32 B38 A37 C31 K42

D10

C29 B30 D28 A27 B28

SMRCOMP SMRCOMP#

SMRCOMP_VOH SMRCOMP_VOL

DDR3_NB_REF SM_PWROK SM_REXT

CLK_MCH_DREFCLK <16> CLK_MCH_DREFCLK# <16> MCH_SSCDREFCLK <16> MCH_SSCDREFCLK# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_TXN0 <19> DMI_TXN1 <19> DMI_TXN2 <19> DMI_TXN3 <19>

DMI_TXP0 <19> DMI_TXP1 <19> DMI_TXP2 <19> DMI_TXP3 <19>

DMI_RXN0 <19> DMI_RXN1 <19> DMI_RXN2 <19> DMI_RXN3 <19>

DMI_RXP0 <19> DMI_RXP1 <19> DMI_RXP2 <19> DMI_RXP3 <19>

CL_VREF

TSATN#

R58 54.9_0402_1%R58 54.9_0402_1%

1 2

HDA_SDIN2_NB

R43 80.6_0402_1%

R43 80.6_0402_1% R44 80.6_0402_1%R44 80.6_0402_1%

T38T38

M_CLK_DDR0 <14> M_CLK_DDR1 <14> M_CLK_DDR2 <15> M_CLK_DDR3 <15>

M_CLK_DDR#0 <14> M_CLK_DDR#1 <14> M_CLK_DDR#2 <15> M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14> DDR_CKE1_DIMMA <14> DDR_CKE2_DIMMB <15> DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14> DDR_CS2_DIMMB# <15> DDR_CS3_DIMMB# <15>

M_ODT0 <14> M_ODT1 <14> M_ODT2 <15> M_ODT3 <15>

1 2 1 2

1 2

R429 0_0402_5%R429 0_0402_5%

1 2 1 2

SM_DRAMRST# <14,15>

CL_CLK0 <19> CL_DATA0 <19> M_PWROK <19> CL_RST# <19>

C76

0.1U_0402_16V4Z

T39T39

HDMICLK <21> HDMIDAT <21> CLKREQ#_B <16> MCH_ICH_SYNC# <19>

R313

1 2

33_0402_5%

1.5V_PGOOD <25>

R46 10K_0402_1%@ R46 10K_0402_1%@ R47 499_0402_1%R47 499_0402_1%

+VCCP

R52

R52 1K_0402_1%

1K_0402_1%

R53

R53 499_0402_1%

499_0402_1%

+VCCP

HDA_BITCLK_NB <21> HDA_RST#_NB <21>

HDA_SDOUT_NB <21> HDA_SYNC_NB <21>

+1.5V

HDA_SDIN2 <18>

NB_GS45

GS45@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

LS-5581P

8 30Thursday, July 23, 2009

2.0

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U3E

AP54

SB_DQ_0

AM52

SB_DQ_1

AR55

SB_DQ_2

AV54

SB_DQ_3

AM54

SB_DQ_4

AN53

SB_DQ_5

AT52

SB_DQ_6

AU53

SB_DQ_7

AW53

SB_DQ_8

AY52

SB_DQ_9

BB52

SB_DQ_10

BC53

SB_DQ_11

AV52

SB_DQ_12

AW55

SB_DQ_13

BD52

SB_DQ_14

BC55

SB_DQ_15

BF54

SB_DQ_16

BE51

SB_DQ_17

BH48

SB_DQ_18

BK48

SB_DQ_19

BE53

SB_DQ_20

BH52

SB_DQ_21

BK46

SB_DQ_22

BJ47

SB_DQ_23

BL45

SB_DQ_24

BJ45

SB_DQ_25

BL41

SB_DQ_26

BH44

SB_DQ_27

BH46

SB_DQ_28

BK44

SB_DQ_29

BK40

SB_DQ_30

BJ39

SB_DQ_31

BK10

SB_DQ_32

BH10

SB_DQ_33

BK6

SB_DQ_34

BH6

SB_DQ_35

BJ9

SB_DQ_36

BL11

SB_DQ_37

BG5

SB_DQ_38

BJ5

SB_DQ_39

BG3

SB_DQ_40

BF4

SB_DQ_41

BD4

SB_DQ_42

BA3

SB_DQ_43

BE5

SB_DQ_44

BF2

SB_DQ_45

BB4

SB_DQ_46

AY4

SB_DQ_47

BA1

SB_DQ_48

AP2

SB_DQ_49

AU1

SB_DQ_50

AT2

SB_DQ_51

AT4

SB_DQ_52

AV4

SB_DQ_53

AU3

SB_DQ_54

AR3

SB_DQ_55

AN1

SB_DQ_56

AP4

SB_DQ_57

AL3

SB_DQ_58

AJ1

SB_DQ_59

AK4

SB_DQ_60

AM4

SB_DQ_61

AH2

SB_DQ_62

AK2

SB_DQ_63

CANTIGA GMCH SFF_FCBGA1363

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LS-5581P

2.0

9 30Thursday, July 23, 2009

L_BKLT_CTRL<21> ENABLT<21>

+3VS

DDC2_CLK<21> DDC2_DATA<21>

D D

C C

CRT_DDC_CLK<21>

CRT_DDC_DATA<21>

CRT_HSYNC<21>

CRT_VSYNC<21>

B B

ENAVDD<21>

TXCLK_L-<21> TXCLK_L+<21>

TXOUT_L0-<21> TXOUT_L1-<21> TXOUT_L2-<21>

TXOUT_L0+<21> TXOUT_L1+<21> TXOUT_L2+<21>

D_BLUE<21>

D_GREEN<21>

D_RED<21>

R71 30.1_0402_1%

1 2

R73 30.1_0402_1%

1 2

Close to pin D32 and keep 30mil space to other part/trace.

R65 10K_0402_5%

R66 10K_0402_5%

R67 2.4K_0402_1%~DR67 2.4K_0402_1%~D

R68 75_0402_5%R68 75_0402_5% R69 75_0402_5%R69 75_0402_5% R70 75_0402_5%R70 75_0402_5%

D_BLUE

D_GREEN

D_RED

1 2

T42T42

1 2 1 2 1 2

Tie to GND. 9/28

D_BLUE

D_GREEN

D_RED

CRT_HSYNC_R

CRT_VSYNC_R

R76

1.02K_0402_1%

1 2

U3C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

Del R82, R83. 10/18

PEGCOMP trace width and spacing is 20/25 mils.

PEGCOMP

U45

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T44

D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

PEG_COMPO

LVDS

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

VGA

Remove R84 ~ R86 since already have 75ohm of page17. 10/27

1 2

R64 49.9_0402_1%R64 49.9_0402_1%

layout note:

Place R64 <500mils to U4 pin U45&T44.

HDMI_C_TX2HDMI_C_TX1HDMI_C_TX0HDMI_C_CLK-

HDMI_C_TX2+ HDMI_C_TX1+ HDMI_C_TX0+ HDMI_C_CLK+

+VCC_PEG

HDMI_HPD#

C1036 0.1U_0402_16V4Z

1 2

C1037 0.1U_0402_16V4Z

1 2

C1038 0.1U_0402_16V4Z

1 2

C1039 0.1U_0402_16V4Z

1 2

C1040 0.1U_0402_16V4Z

1 2

C1041 0.1U_0402_16V4Z

1 2

C1042 0.1U_0402_16V4Z

1 2

C1043 0.1U_0402_16V4Z

1 2

HDMI_HPD# <21>

TX2D- <21> TX1D- <21> TX0D- <21> TXCD- <21>

TX2D+ <21> TX1D+ <21> TX0D+ <21> TXCD+ <21>

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9

(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R72 2.21K_0402_1% @R72 2.21K_0402_1% @

CFG5<8>

CFG6<8>

CFG7<8>

CFG9<8>

CFG10<8>

CFG12<8>

CFG13<8>

CFG16<8>

CFG19<8>

CFG20<8>

1 2

R74 2.21K_0402_1% @R74 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @R75 2.21K_0402_1% @

1 2

R77 2.21K_0402_1% @R77 2.21K_0402_1% @

1 2

R78 2.21K_0402_1% @R78 2.21K_0402_1% @

1 2

R79 2.21K_0402_1%@R79 2.21K_0402_1%@

1 2

R80 2.21K_0402_1% @R80 2.21K_0402_1% @

1 2

R81 2.21K_0402_1% @R81 2.21K_0402_1% @

1 2

R82 4.02K_0402_1%@ R82 4.02K_0402_1%@

1 2

R83 4.02K_0402_1% @R83 4.02K_0402_1% @

1 2

+3VS

R16

R15

R13

150_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

LS-5581P

10 30Thursday, July 23, 2009

2.0

+ 21 hidden pages