Compal LA-5581P, IdeaPad U450 Schematic

A

ZZZ

PCB_LS5581P

Part Number = DA80000FB20

1 1

B

C

D

E

Compal confidential

Schematics Document

Mobile Penryn ULV singal/dual

2 2

core with Intel Cantiga_GS45/GS40 +ICH9-M SFF core logic

3 3

ULV core logic board

2

009-07-23

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LS-5581P

E

2.0

of

1 30Thursday, July 23, 2009

of

1 30Thursday, July 23, 2009

of

1 30Thursday, July 23, 2009

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LS-5581P

E

2.0

of

2 30Tuesday, July 21, 2009

of

2 30Tuesday, July 21, 2009

of

2 30Tuesday, July 21, 2009

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

1 1

( O MEANS ON X MEANS OFF )

+B

+3VL

power plane

O

X

Descrebtion

+5VALW

+3VALW

+1.5V

O

X

O

X X

X

X X X

Descrebtion

+5VS

+3VS

+1.5VS

+0.75V

+VCCP

+CPU_CORE

OO

X

SMBUS Control Table

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2 SMB_EC_DA2

SMB_CK_CLK1 SMB_CK_DAT1 ICH9

LCD_CLK LCD_DAT

Descrebtion

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build CONN@ : means ME part. 45@ : means install after SMT.

SOURCE

KB926

INVERTER BATT EEPROM

X X

X

Cantiga

X X

SERIAL

V V

X X

X

X X

THERMAL SENSOR (CPU)

X X

V

X

SODIMM CLK CHIP

MINI CARD

X

V V V

X X

LCD

X X X

X

V

USB port 0

USB port 1

USB port 2

USB port 3

USB port 4

USB port 5

USB port 6

USB port 7

USB port 8

USB connector

BT Module

cardreader

USB connector

WLAN Conn.

WWAN/SSD

USB connector

CMOS

Fingerprint

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

CLOCK GENERATOR (EXT.)

HEX ADDRESS

A0

D2

PCI-e port 0

PCI-e port 1

PCI-e port 2

PCI-e port 3

PCI-e port 4

PCI-e port 5

1 0 1 0 0 0 0 0

1 1 0 1 0 0 1 0

WLAN Conn.

LAN

SATA port 0

SATA port 1

SATA port 2

SATA HDD

WWAN/SSD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LS-5581P

of

3 30Tuesday, July 21, 2009

of

3 30Tuesday, July 21, 2009

of

3 30Tuesday, July 21, 2009

2.0

5

U1

CPU SU2700

2700@

D D

U1

CPU SU9600

9600@

U1

CPU SU3500

3500@

U1

CPU 743

743@

07/06 Add U1 SA00003BZ10 for 3500@

07/23 Add U1 SA00003IA50 for 7300@ Add U1 SA00003I950 for 4100@ Add U1 SA00003H060 for 2300@ Add U1 SA00003JO60 for 743@

H_A#[3..16]<8>

C C

H_ADSTB#0<8>

H_A#[17..35]<8>

B B

H_ADSTB#1<8>

H_FERR#<18>

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0<8> H_REQ#1<8> H_REQ#2<8> H_REQ#3<8> H_REQ#4<8>

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A20M#<18>

H_IGNNE#<18>

H_STPCLK#<18> H_INTR<18>

H_NMI<18> H_SMI#<18>

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

C7

A20M#

D4

FERR#

F10

IGNNE#

F8

STPCLK#

C9

LINT0

C5

LINT1

E5

SMI#

V2

RSVD01

Y2

RSVD02

AG5

RSVD03

AL5

RSVD04

J9

RSVD05

F4

RSVD06

H8

RSVD07

PENRYN SFF_UFCBGA956

723@

07/06 Change U1 from SA000038J40 to SA000038J60

ADDR GROUP 0 ADDR GROUP 1

CONTROL

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

BCLK[0] BCLK[1]

TDI

RESERVED

4

U1

CPU SU7300

7300@

Place close to U1.

M4 J5 L5

N5 F38 J1

M2

B40 D8

N1

G5 K2 H4 K4 L1

H2 F2

AY8 BA7 BA5 AY2 AV10 AV2 AV4 AW7 AU1 AW5 AV8 J7

D38

H_THERMDA_R

BB34

H_THERMDC_R

BD34

B10

A35 C35

U1

CPU SU4100

4100@

H_ADS# <8> H_BNR# <8>

H_BPRI# <8>

H_DEFER# <8>

H_DRDY# <8> H_DBSY# <8>

H_BR0# <8>

H_INIT# <18>

H_LOCK# <8>

H_RESET#

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_RS#0 <8> H_RS#1 <8> H_RS#2 <8>

H_TRDY# <8>

H_HIT# <8> H_HITM# <8>

Place Close to U1.

R22 68_0402_5%R22 68_0402_5% R23 0_0402_5%R23 0_0402_5%

H_THERMTRIP#

R24 0_0402_5%R24 0_0402_5%

H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

U1

CPU SU2300

2300@

+VCCP

1 2

Add 0 ohm per EMI request. 10/17

XDP_DBRESET# <19>

H_PROCHOT# <28>

1 2 1 2 1 2

H_THERMTRIP# <8,18>

H_PROCHOT#

3

XDP_TDI

XDP_DBRESET#

XDP_TDO

XDP_TMS

XDP_TRST#

XDP_TCK

@

2

3

D9

D9 PJDLC05_SOT23-3

PJDLC05_SOT23-3

R10

R10 51_0402_1%

51_0402_1%

1 2

R9

56_0402_5%

1

C1046

@

2

0.1U_0402_16V4Z

+VCCP

H_THERMDA H_THERMDC

For ESD

H_RESET# <8>

For ESD

1

+3VS

0.1U_0402_16V4Z

C1035

1 2

2200P_0402_50V7K

R306

1 2

10K_0402_5%

1

2

C1034

H_THERMDA

H_THERMDC

THERM#

2

3

1

@

D10

D10 PJDLC05_SOT23-3

PJDLC05_SOT23-3

2

3

1

U7

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

SMDATA

@

2

D11

D11 PJDLC05_SOT23-3

PJDLC05_SOT23-3

SMCLK

ALERT#

GND

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TRST#

XDP_TCK

8

7

R305 10K_0402_5%

1 2

6

5

1

R1 54.9_0402_ 1%R1 54.9_0402_ 1%

1 2

R2 54.9_0402_ 1%R2 54.9_0402_ 1%

1 2

R3 54.9_0402_ 1%R3 54.9_0402_ 1%

1 2

R6 51_0 402_1%R6 51_0 402_1%

1 2

R7 54.9_0402_ 1%R7 54.9_0402_ 1%

1 2

This shall place near CPU

EC_SMB_CK2 <21>

EC_SMB_DA2 <21>

+3VS

+VCCP

Address:100_1100

1

C1057

@

2

For EMI

0.1U_0402_16V4Z

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

LS-5581P

1

2.0

of

4 30Thursday, July 23, 2009

of

4 30Thursday, July 23, 2009

of

4 30Thursday, July 23, 2009

5

4

3

2

1

H_D#[0..15]<8>

D D

H_DSTBN#0<8> H_DSTBP#0<8> H_DINV#0<8> H_D#[16..31]<8>

C C

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

H_DSTBN#1<8> H_DSTBP#1<8> H_DINV#1<8>

CPU_BSEL0<16> CPU_BSEL1<16> CPU_BSEL2<16>

V_CPU_GTLREF

T8T8

T9T9 T10T10

H_D#0 H_D#1

H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1

TEST2

TEST5 TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

0 1

0

1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

CPU_BSEL0

1

0

D[32]# D[33]# D[34]#

DATA GROUP 0

D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP# PSI#

Cause CPU core power change to 1 phase, and not need support the pin, leave it as TP. 10/02

AR43 AH40 AF40 AJ43 AG41 AF44 AH44 AM44 AN43 AM40 AK40 AG43 AP40 AN41 AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

H_PSI#

H_D#33 H_D#34H_D#2 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3

COMP0 COMP1 COMP2 COMP3

H_D#32

AP44

H_DPRSTP# <8,18,28>

H_DPSLP# <18> H_DPWR# <8> H_PWRGOOD <18>

H_CPUSLP# <8>

T11T11

H_D#[32..47] <8>

H_DSTBN#2 <8> H_DSTBP#2 <8> H_DINV#2 <8> H_D#[48..63] <8>

H_DSTBN#3 <8> H_DSTBP#3 <8> H_DINV#3 <8>

R33

R32

R31

R30

12

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

R27 0_0402_5%R27 0_0402_5%

1 2

J11

R28 0_0402_5% R28 0_0402_5%

1 2

E11

R29 0_0402_5% R29 0_0402_5%

1 2

G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils. The trace width/space/other is 20/7/25.

+VCCP

1

+

C5

330U_D2E_2.5VM_R9

2

CPU_VID0 <28> CPU_VID1 <28> CPU_VID2 <28> CPU_VID3 <28> CPU_VID4 <28> CPU_VID5 <28> CPU_VID6 <28>

VCCSENSE <28>

VSSSENSE <28>

Change to 330u_R9, casue high limitation. 12/14

+1.5VS

1

C6

C7

2

0.01U_0402_16V7K

Near pin B34

C7

2

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R34

+VCCP

12

R36

R36 1K_0402_1%

1K_0402_1%

V_CPU_GTLREF

A A

12

R37

R37 2K_0402_1%

2K_0402_1%

1 2

100_0402_1%

R35

1 2

100_0402_1%

Close to CPU pin within 500mils.

VCCSENSE

VSSSENSE

Close to CPU pin AW43 within 500mils.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LS-5581P

1

of

5 30Thursday, July 23, 2009

of

5 30Thursday, July 23, 2009

of

5 30Thursday, July 23, 2009

2.0

5

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

M24

M22

AJ35

VCCP_040

VCCP_041

VCCP_042

VCCP_043

VCCP_044

VCCP_045

VCCP_046

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

V22

Y24

Y22

AB24

AB22

AD24

AD22

4

AF36

AL35

AN35

AK36

AP36

B12

B14

C13

D12

D14

E13

F14

F12

G13

H14

H12

J13

K14

K12

L13

L11

M14

N13

N11

K10

P14

P12

R13

R11

T14

U13

U11

V14

V12

VCCP_047

VCCP_048

VCCP_049

VCCP_050

VCCP_051

VCCP_052

VCCP_053

VCCP_054

VCCP_055

VCCP_056

VCCP_057

VCCP_058

VCCP_059

VCCP_060

VCCP_061

VCCP_062

VCCP_063

VCCP_064

VCCP_065

VCCP_066

VCCP_067

VCCP_068

VCCP_069

VCCP_070

VCCP_071

VCCP_072

VCCP_073

VCCP_074

VCCP_075

VCCP_076

VCCP_077

VCCP_078

VCCP_079

VCCP_080

VCCP_081

VCC_127

VCC_128

VCC_129

VCC_130

VCC_131

VCC_132

VCC_133

VCC_134

VCC_135

VCC_136

VCC_137

VCC_138

VCC_139

VCC_140

VCC_141

VCC_142

VCC_143

VCC_144

VCC_145

VCC_146

VCC_147

VCC_148

VCC_149

VCC_150

VCC_151

VCC_152

VCC_153

VCC_154

VCC_155

VCC_156

VCC_157

VCC_158

VCC_159

VCC_160

VCC_161

F18

F16

B16

B18

B20

AF24

AF22

AH24

AH22

AT24

AK24

AT22

AK22

AP24

AP22

AV24

AV22

AY24

AY22

AM24

AM22

BB24

D16

BB22

BD24

BD22

F20

K18

D18

K16

H18

H16

D20

H20

3

W13

W11

P10

V10

Y14

AA13

AA11

AB14

AB12

AC13

AC11

AD14

AB10

AE13

AE11

AF14

AF12

AG13

AG11

AH14

AJ13

AJ11

AF10

AK14

AK12

AL13

AL11

AN13

AN11

AP12

AR13

AR11

AK10

AP10

AU13

VCCP_082

VCCP_083

VCCP_084

VCCP_085

VCCP_086

VCCP_087

VCCP_088

VCCP_089

VCCP_090

VCCP_091

VCCP_092

VCCP_093

VCCP_094

VCCP_095

VCCP_096

VCCP_097

VCCP_098

VCCP_099

VCCP_100

VCCP_101

VCCP_102

VCCP_103

VCCP_104

VCCP_105

VCCP_106

VCCP_107

VCCP_108

VCCP_109

VCCP_110

VCCP_111

VCCP_112

VCCP_113

VCCP_114

VCCP_115

VCCP_116

VCC_162

VCC_163

VCC_164

VCC_165

VCC_166

VCC_167

VCC_168

VCC_169

VCC_170

VCC_171

VCC_172

VCC_173

VCC_174

VCC_175

VCC_176

VCC_177

VCC_178

VCC_179

VCC_180

VCC_181

VCC_182

VCC_183

VCC_184

VCC_185

VCC_186

VCC_187

VCC_188

VCC_189

VCC_190

VCC_191

VCC_192

VCC_193

VCC_194

VCC_195

VCC_196

T18

T16

K20

P18

M18

M16

M20

T20

P16

V18

V16

P20

V20

Y18

Y16

Y20

AF18

AF16

AB18

AB16

AD18

AD16

AF20

AB20

AD20

AK18

AK16

AP18

AP16

AH18

AH16

AH20

AK20

AM18

AM16

2

AU11

VCCP_117

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_197

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

AT18

AT16

AP20

AV18

AV16

AY18

AM20

AY16

1

+VCCP

AA9

AA7

AC9

AC7

AE9

AE7

AG9

AG7

AJ9

AJ7

AL9

AL7

AN9

AN7

AR9

AR7

A33

A13

U1F

U1F PENRYN SFF_UFCBGA956

PENRYN SFF_UFCBGA956

VCCP_129

VCCP_130

VCCP_131

VCCP_132

VCCP_133

VCCP_134

VCCP_135

VCCP_136

VCCP_137

VCCP_138

VCCP_139

VCCP_140

VCCP_141

VCCP_142

VCCP_143

VCCP_144

VCCP_145

VCC_204

VCC_205

VCC_206

VCC_207

VCC_208

VCC_209

VCC_210

VCC_211

VCC_212

VCC_213

VCC_214

VCC_215

VCC_216

VCC_217

VCC_218

VCC_219

VCC_220

VCCP_020

VCCP_018

VCCP_019

VCCP_017

AT20

AV20

AY20

BB18

BB16

AT14

BB20

AP14

BD18

AV14

BD16

BD20

AM14

AJ37

AF38

AY14

BB14

AK38

BD14

AG37

+VCC_CORE +VCCP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-Power

LS-5581P

1

2.0

of

6 30Tuesday, July 21, 2009

of

6 30Tuesday, July 21, 2009

of

6 30Tuesday, July 21, 2009

5

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

5

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

4

+VCC_CORE

10U_0603_6.3V6MC810U_0603_6.3V6M

1

C8

2

+VCC_CORE

1U_0402_6.3V6K

1

C32

2

Mid Frequence Decoupling

10U_0603_6.3V6MC910U_0603_6.3V6M

10U_0603_6.3V6M

1

C9

C10

2

1U_0402_6.3V6K

1

C34

C33

2

3

10U_0603_6.3V6M

1

C12

C11

2

High Frequence Decoupling

1U_0402_6.3V6K

1

C36

C35

2

10U_0603_6.3V6M

1

C13

C14

2

1U_0402_6.3V6K

1

C37

C38

2

C38

2

10U_0603_6.3V6M

1

2

1

2

C16

C15

2

1U_0402_6.3V6K

1

C39

C40

2

10U_0603_6.3V6M

1

C18

C17

2

1U_0402_6.3V6K

1

C42

C41

2

10U_0603_6.3V6M

1

2

1

2

1

C19

2

1U_0402_6.3V6K

1

C43

2

1

C20

C21

C22

2

1U_0402_6.3V6K

C44

1U_0402_6.3V6K

1

C45

C46

2

10U_0603_6.3V6M

1

C23

C24

2

1U_0402_6.3V6K

1

C48

C47

2

10U_0603_6.3V6M

1

C25

2

1U_0402_6.3V6K

1

C49

2

10U_0603_6.3V6M

1

2

1

2

1

C26

C27

2

1U_0402_6.3V6K

1

C50

C51

2

1

10U_0603_6.3V6M

1

C28

C29

2

1U_0402_6.3V6K

1

C52

C53

2

10U_0603_6.3V6M

1

2

1

2

C31

C30

2

1U_0402_6.3V6K

1

C54

C55

2

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 1.5m ohm

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

1

+

C56

2

Del C37 to improve power plan. 6/14

+VCCP

1U_0402_6.3V6K

C59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

1U_0402_6.3V6K

1

C61

C60

2

1U_0402_6.3V6K

1

2

Compal Secret Data

1

C63

C62

2

Deciphered Date

1U_0402_6.3V6K

220U_D2_2VK_R9

1

+

C57

2

C64

220U_D2_2VK_R9

1

+

C58

2

1U_0402_6.3V6K

1

2

C66

C65

2

1U_0402_6.3V6K

1

C67

2

1U_0402_6.3V6K

1

C68

2

1U_0402_6.3V6K

1

C69

C70

2

C70

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-GND/Bypass

LS-5581P

1

2.0

of

7 30Tuesday, July 21, 2009

of

7 30Tuesday, July 21, 2009

of

7 30Tuesday, July 21, 2009

5

U3A

H_D#[0..63]<5>

D D

C C

H_RESET#<4>

H_CPUSLP#<5>

layout note:

B B

Route H_SCOMP an d H_SCOMP# with trace width, spacing and impe dance (55 ohm) same as FSB data traces

trace width and spacing is 10/20

+VCCP

12

1K_0402_1%

12

R59

2K_0402_1%

A A

Trace < = 500mil s

Layout Note: H_RCOMP / H_VREF / H_SWNG

R55

H_VREF

1

C78

2

0.1U_0402_16V4Z

@

within 100 mils from NB

H_SWNG H_RCOMP

H_VREF

12

24.9_0402_1%

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_RCOMP

R60

U3A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

12

221_0603_1%

12

100_0402_1%

R56

1

R61

2

0.1U_0402_16V4Z

Near B6 pin

H_SWNG

C79

H_ADSTB#_0 H_ADSTB#_1

HOST

HPLL_CLK#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

layout note:

Place them close to U4 pin BC51 .

Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

PM_EXTTS#0

PM_EXTTS#1

4

H_A#3

L15

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19

F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

DDR3_NB_REF

R62 10K_0402_5%

1 2

R63 10K_0402_5%R63 10K_0402_5%

1 2

Del R48. 9/27

H_A#[3..35] <4>

Add them for Bou ndary Scan. 10/ 23

R38 1K_0402_5%@R38 1K_0402_5%@ R39 4.7K_0402_5%@R39 4.7K_0402_5%@ R40 4.7K_0402_5%@R40 4.7K_0402_5%@ R41 1K_0402_5% @R41 1K_0402_5% @

SMRCOMP_VOH

SMRCOMP_VOL

R51 0_0402_5%R51 0_0402_5%

+1.5V

12

R54

R54 10K_0402_1%

10K_0402_1%

12

R57

R57 10K_0402_1%

10K_0402_1%

H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4>

H_DINV#0 <5> H_DINV#1 <5> H_DINV#2 <5> H_DINV#3 <5>

H_DSTBN#0 <5> H_DSTBN#1 <5> H_DSTBN#2 <5> H_DSTBN#3 <5>

H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5>

H_REQ#0 <4> H_REQ#1 <4> H_REQ#2 <4> H_REQ#3 <4> H_REQ#4 <4>

H_RS#0 <4> H_RS#1 <4> H_RS#2 <4>

H_THERMTRIP#<4,18>

PM_DPRSLPVR<19,28>

C77

1

2

0.1U_0402_16V4Z

+3VS

3

1 2 1 2 1 2 1 2

+1.5V

1

C72

C71

2.2U_0603_6.3V4Z

PM_BMBUSY#<19>

H_DPRSTP#<5,18,28> PM_EXTTS#0<14> PM_EXTTS#1<15> PM_PWROK<19,21,28> PLT_RST#<17,21>

1 2

0.01U_0402_25V7K

2

1

C74

C73

2

0.01U_0402_25V7K

MCH_CLKSEL0<16> MCH_CLKSEL1<16> MCH_CLKSEL2<16>

Add R428 in 9/26

T12T12 T13T13 T14T14 T15T15 T16T16 T17T17 T18T18 T19T19 T20T20

TCK TDI TDO TMS

T21T21 T22T22

T23T23

T24T24

12

R42

R42 1K_0402_1%

1K_0402_1%

12

R45

3.01K_0402_1%

12

R48

R48 1K_0402_1%

1K_0402_1%

CFG5<10> CFG6<10> CFG7<10>

CFG9<10>

CFG10<10>

CFG12<10> CFG13<10>

CFG16<10>

CFG19<10> CFG20<10>

PM_EXTTS#0 PM_EXTTS#1

R49 0_0402_5%R49 0_0402_5%

1 2

R50 100_0402_1% R50 100_0402_1%

1 2

T26T26 T27T27 T28T28

T30T30 T31T31

T32T32

T33T33

T34T34 T35T35

T36T36 T37T37

C750.1U_0402_16V4Z @ C7 50.1U_0402_16V4Z @

1

2

U3B

J43

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

CANTIGA GMCH SFF_FCBGA1363

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2

DMI

GRAPHICS VID

ME

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

HDA

DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

CFGRSVD

PM

NC

BL25 BK26

BK32 BL31

BC51 AY37 BH20 BA37

B42 D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

G39

AK52 AK54 AW40 AL53 AL55

F34 F32 B38 A37 C31 K42

D10

C29 B30 D28 A27 B28

SMRCOMP SMRCOMP#

SMRCOMP_VOH SMRCOMP_VOL

DDR3_NB_REF SM_PWROK SM_REXT

CLK_MCH_DREFCLK <16> CLK_MCH_DREFCLK# <16> MCH_SSCDREFCLK <16> MCH_SSCDREFCLK# <16>

CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16>

DMI_TXN0 <19> DMI_TXN1 <19> DMI_TXN2 <19> DMI_TXN3 <19>

DMI_TXP0 <19> DMI_TXP1 <19> DMI_TXP2 <19> DMI_TXP3 <19>

DMI_RXN0 <19> DMI_RXN1 <19> DMI_RXN2 <19> DMI_RXN3 <19>

DMI_RXP0 <19> DMI_RXP1 <19> DMI_RXP2 <19> DMI_RXP3 <19>

CL_VREF

TSATN#

R58 54.9_0402_1%R58 54.9_0402_1%

1 2

HDA_SDIN2_NB

R43 80.6_0402_1%

R43 80.6_0402_1% R44 80.6_0402_1%R44 80.6_0402_1%

T38T38

1

M_CLK_DDR0 <14> M_CLK_DDR1 <14> M_CLK_DDR2 <15> M_CLK_DDR3 <15>

M_CLK_DDR#0 <14> M_CLK_DDR#1 <14> M_CLK_DDR#2 <15> M_CLK_DDR#3 <15>

DDR_CKE0_DIMMA <14> DDR_CKE1_DIMMA <14> DDR_CKE2_DIMMB <15> DDR_CKE3_DIMMB <15>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14> DDR_CS2_DIMMB# <15> DDR_CS3_DIMMB# <15>

M_ODT0 <14> M_ODT1 <14> M_ODT2 <15> M_ODT3 <15>

1 2 1 2

1 2

R429 0_0402_5%R429 0_0402_5%

1 2 1 2

SM_DRAMRST# <14,15>

CL_CLK0 <19> CL_DATA0 <19> M_PWROK <19> CL_RST# <19>

C76

0.1U_0402_16V4Z

T39T39

HDMICLK <21> HDMIDAT <21> CLKREQ#_B <16> MCH_ICH_SYNC# <19>

R313

1 2

33_0402_5%

1.5V_PGOOD <25>

R46 10K_0402_1%@ R46 10K_0402_1%@ R47 499_0402_1%R47 499_0402_1%

+VCCP

12

R52

R52 1K_0402_1%

1K_0402_1%

12

1

R53

R53 499_0402_1%

499_0402_1%

2

+VCCP

HDA_BITCLK_NB <21> HDA_RST#_NB <21>

HDA_SDOUT_NB <21> HDA_SYNC_NB <21>

+1.5V

HDA_SDIN2 <18>

U3

NB_GS45

GS45@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

LS-5581P

8 30Thursday, July 23, 2009

1

2.0

5

D D

DDR_A_D[0..63]<14>

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

U3D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

4

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 <14> DDR_A_BS1 <14> DDR_A_BS2 <14>

DDR_A_RAS# <14> DDR_A_CAS# <14> DDR_A_WE# <14>

DDR_A_DM[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_DQS#[0..7] <14>

DDR_A_MA[0..14] <14>

3

DDR_B_D[0..63]<15>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8

DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

U3E

AP54

SB_DQ_0

AM52

SB_DQ_1

AR55

SB_DQ_2

AV54

SB_DQ_3

AM54

SB_DQ_4

AN53

SB_DQ_5

AT52

SB_DQ_6

AU53

SB_DQ_7

AW53

SB_DQ_8

AY52

SB_DQ_9

BB52

SB_DQ_10

BC53

SB_DQ_11

AV52

SB_DQ_12

AW55

SB_DQ_13

BD52

SB_DQ_14

BC55

SB_DQ_15

BF54

SB_DQ_16

BE51

SB_DQ_17

BH48

SB_DQ_18

BK48

SB_DQ_19

BE53

SB_DQ_20

BH52

SB_DQ_21

BK46

SB_DQ_22

BJ47

SB_DQ_23

BL45

SB_DQ_24

BJ45

SB_DQ_25

BL41

SB_DQ_26

BH44

SB_DQ_27

BH46

SB_DQ_28

BK44

SB_DQ_29

BK40

SB_DQ_30

BJ39

SB_DQ_31

BK10

SB_DQ_32

BH10

SB_DQ_33

BK6

SB_DQ_34

BH6

SB_DQ_35

BJ9

SB_DQ_36

BL11

SB_DQ_37

BG5

SB_DQ_38

BJ5

SB_DQ_39

BG3

SB_DQ_40

BF4

SB_DQ_41

BD4

SB_DQ_42

BA3

SB_DQ_43

BE5

SB_DQ_44

BF2

SB_DQ_45

BB4

SB_DQ_46

AY4

SB_DQ_47

BA1

SB_DQ_48

AP2

SB_DQ_49

AU1

SB_DQ_50

AT2

SB_DQ_51

AT4

SB_DQ_52

AV4

SB_DQ_53

AU3

SB_DQ_54

AR3

SB_DQ_55

AN1

SB_DQ_56

AP4

SB_DQ_57

AL3

SB_DQ_58

AJ1

SB_DQ_59

AK4

SB_DQ_60

AM4

SB_DQ_61

AH2

SB_DQ_62

AK2

SB_DQ_63

CANTIGA GMCH SFF_FCBGA1363

2

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6

DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

1

DDR_B_BS0 <15> DDR_B_BS1 <15> DDR_B_BS2 <15>

DDR_B_RAS# <15> DDR_B_CAS# <15> DDR_B_WE# <15>

DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7] <15>

DDR_B_DQS#[0..7] <15>

DDR_B_MA[0..14] <15>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LS-5581P

1

2.0

of

9 30Thursday, July 23, 2009

of

9 30Thursday, July 23, 2009

of

9 30Thursday, July 23, 2009

5

L_BKLT_CTRL<21> ENABLT<21>

+3VS

DDC2_CLK<21> DDC2_DATA<21>

D D

C C

CRT_DDC_CLK<21>

CRT_DDC_DATA<21>

CRT_HSYNC<21>

CRT_VSYNC<21>

B B

ENAVDD<21>

TXCLK_L-<21> TXCLK_L+<21>

TXOUT_L0-<21> TXOUT_L1-<21> TXOUT_L2-<21>

TXOUT_L0+<21> TXOUT_L1+<21> TXOUT_L2+<21>

D_BLUE<21>

D_GREEN<21>

D_RED<21>

R71 30.1_0402_1%

1 2

R73 30.1_0402_1%

1 2

Close to pin D32 and keep 30mil space to other part/trace.

R65 10K_0402_5%

R66 10K_0402_5%

R67 2.4K_0402_1%~DR67 2.4K_0402_1%~D

R68 75_0402_5%R68 75_0402_5% R69 75_0402_5%R69 75_0402_5% R70 75_0402_5%R70 75_0402_5%

D_BLUE

D_GREEN

D_RED

1 2

T42T42

1 2 1 2 1 2

4

Tie to GND. 9/28

D_BLUE

D_GREEN

D_RED

CRT_HSYNC_R

CRT_VSYNC_R

R76

1.02K_0402_1%

1 2

U3C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

Del R82, R83. 10/18

3

PEGCOMP trace width and spacing is 20/25 mils.

PEGCOMP

U45

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T44

D52 G49 K54 H50 M52 N49 P54 V46 Y50 V52 W49 AB54 AD46 AC55 AE49 AF54

E51 F48 J55 J49 M54 M50 P52 U47 AA49 V54 V50 AB52 AC47 AC53 AD50 AF52

L47 F52 P46 H54 L55 T46 R53 U49 T54 Y46 AB46 W53 Y54 AC49 AF46 AD54

J47 F54 N47 H52 L53 R47 R55 T50 T52 W47 AA47 W55 Y52 AB50 AE47 AD52

PEG_COMPO

LVDS

TV

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

VGA

Remove R84 ~ R86 since already have 75ohm of page17. 10/27

1 2

R64 49.9_0402_1%R64 49.9_0402_1%

layout note:

Place R64 <500mils to U4 pin U45&T44.

HDMI_C_TX2HDMI_C_TX1HDMI_C_TX0HDMI_C_CLK-

HDMI_C_TX2+ HDMI_C_TX1+ HDMI_C_TX0+ HDMI_C_CLK+

+VCC_PEG

HDMI_HPD#

C1036 0.1U_0402_16V4Z

1 2

C1037 0.1U_0402_16V4Z

1 2

C1038 0.1U_0402_16V4Z

1 2

C1039 0.1U_0402_16V4Z

1 2

C1040 0.1U_0402_16V4Z

1 2

C1041 0.1U_0402_16V4Z

1 2

C1042 0.1U_0402_16V4Z

1 2

C1043 0.1U_0402_16V4Z

1 2

HDMI_HPD# <21>

TX2D- <21> TX1D- <21> TX0D- <21> TXCD- <21>

TX2D+ <21> TX1D+ <21> TX0D+ <21> TXCD+ <21>

2

Strap Pin Table

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG7 (Intel Management Engine Crypto strap)

CFG8

CFG9

(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

1

000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

Others = Reserved

0 = DMI x 2

1 = DMI x 4

0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable

0 =(TLS)chiper suite with no confidentiality

1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1

1 = Normal Operation,Lane Number in order

0 = Enable

1 = Disable

Reserved

00 = Reserved

01 = XOR Mode Enabled

10 = All Z Mode Enabled

*

(Default)11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled

1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

R72 2.21K_0402_1% @R72 2.21K_0402_1% @

CFG5<8>

CFG6<8>

CFG7<8>

CFG9<8>

CFG10<8>

CFG12<8>

CFG13<8>

CFG16<8>

CFG19<8>

CFG20<8>

1 2

R74 2.21K_0402_1% @R74 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @R75 2.21K_0402_1% @

1 2

R77 2.21K_0402_1% @R77 2.21K_0402_1% @

1 2

R78 2.21K_0402_1% @R78 2.21K_0402_1% @

1 2

R79 2.21K_0402_1%@R79 2.21K_0402_1%@

1 2

R80 2.21K_0402_1% @R80 2.21K_0402_1% @

1 2

R81 2.21K_0402_1% @R81 2.21K_0402_1% @

1 2

R82 4.02K_0402_1%@ R82 4.02K_0402_1%@

1 2

R83 4.02K_0402_1% @R83 4.02K_0402_1% @

1 2

*

+3VS

12

R16

R15

R13

150_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

LS-5581P

10 30Thursday, July 23, 2009

1

2.0

of

5

R86

0.1U_0402_16V4Z

12

10U_0603_6.3V

1

C90

2

R94 0_0603_5% R94 0_0603_5%

9/27

+VCCP

+1.05VM_PEGPLL

1

C125

2

+3VS_DAC_CRT

C92

0.1U_0402_16V4Z

0.01U_0402_16V7K

+3VS

1

BLM18PG181SN1D_0603

C91

2

1 2

BLM18PG181SN1D_0603

C92

2

0.1U_0402_16V4Z

R97 0_0805_5% R97 0_0805_5%

1 2

1

+

2

C110

100U_D2_6.3VM

R100 0_0603_5%

1 2

9/27

C126

0.1U_0402_16V4Z

R87

+1.5VS_PEG_BG

1

C105

2

1

+1.8V

2

12

+1.8V_TXLVDS

9/27

R102 0_0603_5% R102 0_0603_5%

+3VS_DAC_BG

C94

0.01U_0402_16V7K

22U_0805_6.3V

1

C94

C93

2

1

C102

C102 1000P_0402_50V7K

1000P_0402_50V7K

2

+1.05VM_PEGPLL

10U_0805_6.3V6M

4.7U_0805_10V4Z

1

2

C111

+1.05VM_A_SM_CK

10U_0805_6.3V6M

12

1

9/27

+1.05VM_DPLLA

2

+1.05VM_DPLLB

+1.05VM_HPLL

+1.05VM_MPLL

+1.05VM_A_SM

1U_0603_10V4Z

1

2

C112

C113

0.1U_0402_16V4Z

1

C120

C119

2

1

2

1

2

1U_0603_10V4Z

1

C127

2

+3VS

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

D D

C89

2

install 0.1U & 1 0U for wavy iss ue. 7/29

change 0.1U to 2 2U for wavy iss ue. 5/20

+1.5VS

C C

B B

+1.05VM_HPLL

+1.8V_LVDS

4

U3H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13

VTT

VCCA_TV_DAC

TVD TV/CRT

VCC_HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3

DMI

VTTLF1 VTTLF2 VTTLF3

VTTLF

3

Change to 330u_R 9, casue high limitation. 12/1 4

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

+VCC_HDA

A31

N34

+1.5VS_QDAC

N32

+1.5VS_TVDAC

+VCC_HDA

0.1U_0402_16V4Z

9/27

M25 N24 M23

BK24 BL23 BJ23 BK22

T41

C33 A33

AB44 Y44 AC43 AA43

AM44 AN43 AL43

K14 Y12 P2

0.47U_0603_10V7K

1

C128

2

+V1.05VM_AXF

+1.5V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

0.47U_0603_10V7K

2.2U_0805_16V4Z

4.7U_0805_10V4Z

1

C85

C87

2

C85

C86

R92

R92 0_0402_5%@

0_0402_5%@

1 2

Tie to GND. 9/27

R321 0_0603_5%R321 0_0603_5%

1 2

1

C1045

2

+3VS_HV

0.1U_0402_16V4Z

9/29

0.47U_0603_10V7K

1

C130

C129

2

4.7U_0805_10V4Z

1

2

C88

+3VS_TVDAC

0.01U_0402_16V7K

1

C100

2

1

2

C121

+VCCP

1

+

2

C84

330U_D2E_2.5VM_R9

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C101

2

+1.5VS

Enable HDMI audio

R91

1 2

+VCCP

+3VS

2

+1.05VM_DPLLA +VCCP

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

1

@

+

C80

C81

2

0.1U_0402_16V4Z

+1.05VM_DPLLB

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

1

@

+

+3VS

+1.05VM_PEGPLL

2 1

D1 CH751H-40_SC76

+

C96

C95

2

0.1U_0402_16V4Z

+1.05VM_HPLL

1

2

C103

0.1U_0402_16V4Z

+1.05VM_MPLL

1

C106

2

0.1U_0402_16V4Z

+1.8V_TXLVDS +1.8V

1

2

C114

1000P_0402_50V7K

0.1U_0402_16V4Z

1

C122

2

+VCCP_D

+1.5VS_QDAC

C131

0.01U_0402_16V7K

1

C131

2

1 2

BLM18PG181SN1D_0603

1

2

C104

4.7U_0805_10V4Z

1 2

BLM18PG181SN1D_0603

1

C107

2

10U_0805_6.3V6M

R98 0_0603_5% R98 0_0603_5%

1 2

1

C115

10U_0805_6.3V6M @

2

1 2

BLM18PG121SN1D_0603

10U_0805_10V4Z

1

C123

2

R103 10_0402_5% R103 10_0402_5%

1 2

4.7U_0603_6.3V

0.1U_0402_16V4Z

1

C133

C132

2

R93

R95

L1

R84

R88

+VCCP

9/29

R104 0_0402_5% R104 0_0402_5%

R105

1 2

BLM18PG181SN1D_0603

+VCCP

4.7U_0805_10V4Z

+1.05VM_DMI

1 2

+1.5VS

+V1.05VM_AXF

10U_0805_10V4Z

+1.5V_SM_CK

R90

0_0603_5%

1 2

10U_0805_6.3V6M

1

C99

2

+1.5VS_TVDAC

C108

0.01U_0402_16V7K

1

C108

2

+VCC_PEG

10U_0805_6.3V6M

1

C117

C118

2

R101 0_0603_5% R101 0_0603_5%

0.1U_0402_16V4Z

C124

1

C124

2

1

R85 0_0603_5%

1U_0603_10V4Z

1

C83

C82

2

R89 0_0805_5%

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

C97

C98

2

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C109

2

1 2

R99 0_1206_5%R99 0_1206_5%

220U_D2_4VM_R15

1

+

C116

2

1 2

+3VS_HV

1 2

R96

+VCCP

+1.5V

+1.5VS

+VCCP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

install 4.7U fo r wavy issue. 7 /29

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LS-5581P

1

2.0

of

11 30Tuesday, July 21, 2009

5

Extnal Graphic: 1210.34mA integrated Graphic: 1930.4mA

U3F

D D

0.22U_0402_10V4Z

220U_D2_4VM_R15

10U_0805_6.3V6M

1

C141

+

2

C C

B B

A A

0.22U_0402_10V4Z

C143

C142

1

2

1

2

+VCCP

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

W41

VCC_9

0.1U_0402_16V4Z

C145

C144

1

2

AT40

VCC_10

AM40

VCC_11

AL40

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363

4

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38

AT38 AR38 AN38 AM38 AL38 AG38 AE38 AA38 Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

+VCCP

+1.5V

C146

330U_D2E_2.5VM_R9

C146

3

+VCCP

U3G

BB36

VCC_SM_1

BE35

VCC_SM_2

AW34

VCC_SM_3

10U_0805_6.3V6M

330U_D2E_2.5VM_R9

1

+

C147

2

10U_0805_6.3V6M

0.01U_0402_16V7K

1

C137

+

2

1

C148

2

10U_0805_6.3V

0.01U_0402_16V7K

C138

C139

1

2

1

C150

C149

C150

2

10U_0805_6.3V

1U_0603_10V4Z

6326.84mA

T43PAD T43PA D T44PAD T44PA D

AW32

VCC_SM_4

BK30

VCC_SM_5

BH30

VCC_SM_6

BF30

C140

2

1

0.1U_0402_16V4Z

BD30 BB30

AW30

BL29

BJ29 BG29 BE29 BC29 BA29 AY29 BK28 BH28 BF28 BD28 BB28

BL27

BJ27 BG27 BE27 BC27 BA27 AY27

AW26

BF24

BL19 BB16

W32 AG31 AE31 AD31 AC31 AA31

W31 AH29 AG29 AE29 AD29 AC29 AA29

W29 AH28 AG28 AE28 AA28 AH27 AG27 AE27 AD27 AC27 AA27

W27 AH25 AD25 AC25

W25

AJ24 AH24 AG24 AE24 AD24 AC24 AA24

W24

AM22

AL22

AJ22 AH22 AG22 AE22 AD22 AC22 AA22

AM21

AL21

AJ21 AH21 AD21 AC21 AA21

W21

AM16

AL16

AG13 AE13

Y31

Y29

Y27

Y24

Y21

VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61

VCC_AXG_SENSE VSS_AXG_SENSE

2

3000mA

VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23

POWER

VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31

VCC SMVCC GFX

VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39

VCC GFX NCTF

VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9

VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

AU45 BF52 BB38 BA19 BE9 AU9 AL9

+VCCP

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

1

2

C134

0.1U_0402_16V4Z

0.22U_0402_10V4Z

C156 0.1U_ 0402_16V4Z C156 0.1U_ 0402_16V4Z

1

2

1

2

C136

C135

4.7U_0805_10V4Z

C152 0.22U_0603_10V7K C152 0.22U_0603_10V7K

C151 0.22U_0603_10V7K C151 0.22U_0603_10V7K

1

C157 0.1U_ 0402_16V4Z C157 0.1U_ 0402_16V4Z

2

C153 0.47U_0402_6.3V6KC153 0.47U_0402_6.3V6K

C155 1U_0603_10V4Z C155 1U_0603_10V4Z

C154 1U_0603_10V4Z C154 1U_0603_10V4Z

1

2

CANTIGA GMCH SFF_FCBGA1363

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

LS-5581P

1

2.0

of

12 30Tuesday, July 21, 2009

of

12 30Tuesday, July 21, 2009

of

12 30Tuesday, July 21, 2009

5

U3I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51

VSS_34

N51

VSS_35

L51

VSS_36

J51

VSS_37

G51

VSS_38

C51

VSS_39

BK50

VSS_40

AM50

VSS_41

K50

VSS_42

BG49

VSS_43

E49

VSS_44

C49

VSS_45

BD48

VSS_46

BB48

VSS_47

AY48

VSS_48

AV48

VSS_49

AT48

VSS_50

AP48

VSS_51

AM48

VSS_52

AK48

VSS_53

AH48

VSS_54

AF48

VSS_55

AD48

VSS_56

AB48

VSS_57

Y48

VSS_58

V48

VSS_59

T48

VSS_60

P48

VSS_61

M48

VSS_62

K48

VSS_63

H48

VSS_64

BL47

VSS_65

BG47

VSS_66

E47

VSS_67

C47

VSS_68

A47

VSS_69

BD46

VSS_70

AY46

VSS_71

AM46

VSS_72

AK46

VSS_73

AH46

VSS_74

BG45

VSS_75

AE45

VSS_76

AC45

VSS_77

AA45

VSS_78

W45

VSS_79

R45

VSS_80

N45

VSS_81

E45

VSS_82

BD44

VSS_83

BB44

VSS_84

AV44

VSS_85

AK44

VSS_86

AH44

VSS_87

AF44

VSS_88

AD44

VSS_89

K44

VSS_90

H44

VSS_91

BL43

VSS_92

BG43

VSS_93

AY43

VSS_94

AR43

VSS_95

W43

VSS_96

R43

VSS_97

M43

VSS_98

E43

VSS_99

CANTIGA GMCH SFF_FCBGA1363

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

4

3

U3J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19

AY19

M19

BD18

BL17

BG17

AY17

M17

BD16 AN16 AG16 AE16

W16

BG15

AY15 AN15 AD15 AC15

M15

BD14

BL13 BG13

AY13 AU13 AR13

AJ13 AC13 AA13

W13

M13

BD12 AV12 AP12 AM12 AK12 AB12

BG11 AG11

BD10

AY10 AP10

BG9

BD8

E19

N18 H18

E17 A17

Y16

N16 H16

R15

E15

H14

U13

E13 A13

V12 P12 H12

E11

H10 BL9

E9 A9

BB8 AY8 AV8 AT8 AP8

VSS

VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12

VSS NCTF

VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

VSS SCB

VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358

VSS_359 VSS_360 VSS_361 VSS_362

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7

2

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

BL55 BL1 A55 D1 B55 B2 A4

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LS-5581P

1

2.0

of

13 30Tuesday, July 21, 2009

of

13 30Tuesday, July 21, 2009

of

13 30Tuesday, July 21, 2009

5

DDR_A_DQS#[0..7]<9>

DDR_A_D[0..63]<9>

DDR_A_DM[0..7]<9>

DDR_A_DQS[0..7]<9>

DDR_A_MA[0..14]<9>

DDR_A_BS[0..2]<9>

D D

1

C1237

0.1U_0402_16V4Z

2

Layout Note: Place near JP3

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.5V

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

C C

B B

A A

1

C1241

C1240

C1239

2

Layout Note: Place near JP3.203 & JP3.204

+0.75VS

1U_0603_10V4Z

2

C1251

1

10U_0805_6.3V6M

1

C1242

2

1U_0603_10V4Z

2

C1252

1

10U_0805_6.3V6M

1

C1243

2

1U_0603_10V4Z

2

C1254

C1253

1

0.1U_0402_16V4Z

10U_0805_6.3V6M

C1245

1

C1244

2

10U_0805_6.3V6M

1

C1255

2

4

+1.5V

12

R431

R431 100_0402_1%

100_0402_1%

12

R432

R432 100_0402_1%

100_0402_1%

0.1U_0402_16V4Z

C1246

C1247

1

2

C1248

1

2

+V_DDR3_DIMM_REF

1

+

C1238

C1238 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

2

+3VS

1

C1256

2.2U_0603_6.3V4Z

2

DDR_CKE0_DIMMA<8>

DDR_CS1_DIMMA#<8>

M_CLK_DDR0<8> M_CLK_DDR#0<8>

DDR_A_WE#<9>

1

C1257

0.1U_0402_16V4Z

2

3

+V_DDR3_DIMM_REF

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R434 10K_ 0402_5%R434 10K_ 0402_5%

1 2

R435 10K_ 0402_5%R435 10K_ 0402_5%

1 2

2

+1.5V +1.5V

JP4

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME

ME

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

+0.75VS

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 SM_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0 CLK_SMBDATA CLK_SMBCLK

+0.75VS

SM_DRAMRST# <8,15>

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8> M_CLK_DDR#1 <8>

DDR_A_RAS# <9>

DDR_CS0_DIMMA# <8> M_ODT0 <8>DDR_A_CAS#<9>

M_ODT1 <8>

R433 0_0402_5%R433 0_0402_5%

1 2

PM_EXTTS#0 <8>

ICH_SMBDATA <15,16,19,21> ICH_SMBCLK <15,16,19,21>

1

C1249

0.1U_0402_16V4Z

2

1

+V_DDR3_DIMM_REF

1

C1250

2.2U_0805_16V4Z

2

TOP Side DDR3 SO-DIMM A Standard TYPE (4.0mm)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/09/29 2007/09/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

DDR3-SODIMM SLOT1

LS-5581P

1

of

14 30Thursday, July 23, 2009

of

14 30Thursday, July 23, 2009

of

14 30Thursday, July 23, 2009

2.0

5

DDR_B_DQS#[0..7]<9>

DDR_B_D[0..63]<9>

DDR_B_DM[0..7]<9>

D D

C C

B B

A A

DDR_B_DQS[0..7]<9>

DDR_B_MA[0..14]<9>

DDR_B_BS[0..2]<9>

Layout Note: Place near JP4

+1.5V

10U_0805_6.3V6M

1

C1259

C1260

2

Layout Note: Place near JP4.203 & JP4.204

+0.75VS

1U_0603_10V4Z

2

C1269

1

10U_0805_6.3V6M

1

C1262

C1261

2

1U_0603_10V4Z

2

C1271

C1270

1

5

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

C1263

2

10U_0805_6.3V6M

2

1

C1272

C1273

1

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

C1265

1

C1264

2

4

1

C1303

0.1U_0402_16V4Z

2

DDR_CKE2_DIMMB<8>

0.1U_0402_16V4Z

C1266

C1267

1

2

1

C1268

1

+

C1258

C1258 470U_D2_2.5VM_R15

470U_D2_2.5VM_R15

@

2

M_CLK_DDR2<8> M_CLK_DDR#2<8>

4

DDR_B_WE#<9> DDR_B_CAS#<9>

DDR_CS3_DIMMB#<8>

+3VS

1

C1276

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+V_DDR3_DIMM_REF

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R437 10K_ 0402_5%R437 10K_ 0402_5%

1 2

R438 10K_ 0402_5%R438 10K_ 0402_5%

1 2

2007/09/29 2007/09/29

3

+1.5V

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F

FOX_AS0A626-U4RN-7F ME

ME

+0.75VS

Compal Secret Data

@

Deciphered Date

DQS#0

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

DQ4 DQ5

VSS3

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

CK1 CK1#

BA1 RAS#

ODT0

ODT1

NC2

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5

DQ46 DQ47

DQ52 DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7

DQ62 DQ63

SDA

SCL

VTT2

2

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE3_DIMMBDDR_CKE2_DIMMB

74 76 78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#1 CLK_SMBDATA CLK_SMBCLK

2

+0.75VS

SM_DRAMRST# <8,14>

DDR_CKE3_DIMMB <8>

M_CLK_DDR3 <8> M_CLK_DDR#3 <8>

DDR_B_RAS# <9>

DDR_CS2_DIMMB# <8> M_ODT2 <8>

M_ODT3 <8>

R436 0_0402 _5%R436 0_0402_5%

1 2

PM_EXTTS#1 <8> ICH_SMBDATA <14,16,19,21> ICH_SMBCLK <14,16,19,21>

Title

Size Document Number Rev

Date: Sheet

1

C1274

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

DDR3-SODIMM SLOT2

LS-5581P

1

+V_DDR3_DIMM_REF

1

C1275

2.2U_0805_16V4Z

2

Bottom Side DDR3 SO-DIMM B Reverse TYPE (4.0 mm)

15 30Thursday, July 23, 2009

1

2.0

of

5

PCI

CLKSEL1

FSLA

CLKSEL0

MHz

FSLC1FSLB

CLKSEL2

CPU

0 1000 2660 33.3

1

0

1

D D

FSA

R130 2.2K_0402_5%

CPU_BSEL0<5>

C C

CPU_BSEL1<5>

FSC

R146 10K_0402_5%

B B

CPU_BSEL2<5>

R146 10K_0402_5%

200

166

12

1 2

R134 0_0402_5%R134 0_0402_5%

FSB

1 2

R138

R138 0_0402_5%

0_0402_5%

9/20

12

1 2

R148 0_0402_5%R148 0_0402_5%

SRC

FSB

MHz

1066

800

1000

667

100

+VCCP

R123

56_0402_5%@

1 2

R131 1K_0402_5%

12

R135

1K_0402_5%@

+VCCP

R136

1K_0402_5%@

R137

1 2

1K_0402_5%

1 2

12

R141

0_0402_5%@

1 2

R147 1K_0402_5% R147 1K_0402_5%

12

R150

R150 0_0402_5%

0_0402_5%

MHz

33.30

33.3

MCH_CLKSEL1 <8>

MCH_CLKSEL2 <8>

Install. 11/06

14.31818MHZ_20P_1BX14318BE1A

CLK_XTAL_OUT

CLK_XTAL_IN

Y1

A A

12

2

C23333P_0402_50V8J C23333P_0402_50V8J

C234

33P_0402_50V8J

1

5

33P_0402_50V8J

1

+3VS

R153

R153 10K_0402_5%

10K_0402_5%

1 2

@

R156

1 2

10K_0402_5%

4

+3VS

1 2

R121 0_1206_5%

MCH_CLKSEL0 <8>

CLK_PCI_EC<21>

CLK_PCI_ICH< 17>

CLK_48M_ICH<19> CLK_48M_CR< 21>

CLK_14M_ICH<19>

+3VS +3VS

R154

R154 10K_0402_5%

10K_0402_5%

@

1 2

27_SELITP_EN

R157

10K_0402_5%

1 2

4

+3VM_CK505

1

2

C216

10U_0805_10V4Z

CLK_PCI_EC PCI_CLK1

CLK_PCI_ICH

1 2

1

2

C217

C218

C219

0.1U_0402_16V4Z

CLK_48M_ICH

CLK_14M_ICH FSC

R155

R155 10K_0402_5%

10K_0402_5%

PCI2_TME

R158

@

10K_0402_5%

C219

0.1U_0402_16V4Z

CLKREQ#_B_R CLKREQG_WWAN #_R

1 2

1

2

C221

C220

0.1U_0402_16V4Z

9/14

+1.05VM_CK505

1 2 1 2

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

R126 475_04 02_1%

R126 475_04 02_1% R127 475_04 02_1%

R127 475_04 02_1%

+3VM_CK505

+1.05VM_CK505

R14233_040 2_1%

R14533_040 2_1%

CLK_XTAL_IN

CLK_XTAL_OUT

R14933_0402_1%

R17715_0402_1%

@

R15133_0402_1%

Issued Date

3

1

2

C222

PCI2_TME

27_SEL

ITP_EN

3

+1.05VM_CK505+VCCP

1 2

R122 0_1206_5%

1

2

47P_0402_50V8J~D

C1079

@

12 12

U4

6

VDDREF

12

VDDPCI

19

VDD48

23

VDD96_IO

27

VDDPLL3

55

VDDSRC

72

VDDCPU

31

VDDPLL3_IO

38

VDDSRC_IO

52

VDDSRC_IO

62

VDDSRC_IO

66

VDDCPU_IO

13

PCI

14

PCI2/TME

15

PCI3

16

PCI4/27_Select

17

PCI_F5/ITP_EN

5

X1

4

X2

FSA

20

USB_48MHz/FSLA

FSB

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

59

GNDSRC

18

GNDPCI

22

GND48

26

GND

30

GND

69

GNDCPU

34

GNDSRC

42

GNDSRC

3

GNDREF

ICS9LPRS387DKLFT MLF 72P

R124 10K_0402_5% R124 10K_0402_5%

1 2

R132 10K_0402_5%

1 2

27MHz_NonSS/SRCT1_LPR/SE1

1

2

C223

10U_0805_10V4Z

CLKREQ#_B <8> CLKREQG_WWAN # <21> CLKREQ_WLAN# <21>

CPUT0_LPR_F CPUC0_LPR_F

CPUT1_LPR_F CPUC1_LPR_F

CPUT2_ITP_LPR/SRCT8_LPR

CPUC2_ITP_LPR/SRCC8_LPR

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_SS/SRCC1_LPR/SE2

CK_PWRGD/PD#

PCI_STOP#

CPU_STOP#

SRCT7_LPR

SRCC7_LPR

SRCT6_LPR

SRCC6_LPR

SRCT10_LPR

SRCC10_LPR

SRCT11_LPR

SRCC11_LPR

SRCT9_LPR

SRCC9_LPR

SRCT4_LPR

SRCC4_LPR

SRCT3_LPR

SRCC3_LPR

397 Modify to 387

Compal Secret Data

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

0.1U_0402_16V4Z

+3VS

SDATA

1

2

C224

SCLK

CR7#

CR#6

CR10#

CR#11

CR#9

CR#4

CR#3

CR#A

REF1

T_PAD

NC

1

2

C225

0.1U_0402_16V4Z

11

10 9

54 53

71 70

68 67

65

64 63

61 60

58

57 56

49

50 51

46

48 47

43

44 45

41

39 40

37

35 36

32 33

24 25

28 29

1

21

8

73

2

CLKREQ#_B_R

2

1

2

C226

C227

10U_0805_10V4Z

0.1U_0402_16V4Z

CLKREQ_WLAN#_R CLKSATAREQ#_R

CLKREQ_WLAN#_R

CLKREQG_WWAN #_R

R_PCIE_ICH R_PCIE_ICH#

CLKSATAREQ#_R

1

2

C228

0.1U_0402_16V4Z

0.1U_0402_16V4Z 47P_0402_50V8J~D

47P_0402_50V8J~D

C1080

@

R128 475_0402_1% R128 475_0402_1% R129 475_0402_1% R129 475_0402_1%

ICH_SMBCLK <14,15,19,21> ICH_SMBDATA <14,15,19,21>

H_STP_PCI# <19> H_STP_CPU# <19>

CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <8> CLK_MCH_BCLK# <8>

CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8>

CLK_PCIE_MCARD <21> CLK_PCIE_MCARD# <21>

CLK_PCIE_WAN <21> CLK_PCIE_WAN# <21 >

CLKREQA# <21>

CLK_PCIE_LAN <21> CLK_PCIE_LAN# <21>

RP28 0_0404_4P2R_5%RP28 0_0404_4P2R_5%

2 3 1 4

CLK_PCIE_SATA <18> CLK_PCIE_SATA# <18>

CLK_MCH_DREFCLK <8> CLK_MCH_DREFCLK# <8>

MCH_SSCDREFCLK <8> MCH_SSCDREFCLK# <8>

CK_PWRGD <19>

Title

Size Document Number Rev

LS-5581P

Date: Sheet

1

C212

C213

C214

C229

C1048

1 2

12

12P_0402_50V8J

12

Place close to U5

Mount C157 & C166 tp solve

WWAN noise issue. 1/23

R125 10K_ 0402_5%

12 12

Compal Electronics, Inc.

CLOCK GENERATOR

1 2

R133 10K_ 0402_5% R133 10K_0 402_5%

1 2

CLK_PCIE_ICH <19> CLK_PCIE_ICH# <19>

1

CLK_48M_ICH

5P_0402_50V8C@

CLK_14M_ICH

CLK_PCI_ICH

4.7P_0402_50V8C@

CLK_PCI_EC

4.7P_0402_50V8C@

CLK_48M_CR

4.7P_0402_50V8C@

CLKSATAREQ# <19>

of

16 30Thursday, July 23, 2009

of

16 30Thursday, July 23, 2009

of

16 30Thursday, July 23, 2009

+3VS

2.0

5

+3VS

1 2

R159 8.2K_0402_5%

1 2

12

R160 8.2K_0402_5%

R161 8.2K_0402_5%

R162 8.2K_0402_5%

D D

C C

R162 8.2K_0402_5%

R163 8.2K_0402_5%

R164 8.2K_0402_5%

R165 8.2K_0402_5%

R166 8.2K_0402_5%

+3VS

R167 8.2K_0402_5%

R168 8.2K_0402_5%

R169 8.2K_0402_5%

R170 8.2K_0402_5%

R171 8.2K_0402_5%

R172 47K_0402_5%R172 47K_0402_5%

R173 8.2K_0402_5%

R174 8.2K_0402_5%

R175 8.2K_0402_5%

R176 8.2K_0402_5%

R178 8.2K_0402_5%

R179 8.2K_0402_5%

PCI_DEVSEL#

PCI_STOP#

PCI_TRDY#

PCI_FRAME#

PCI_PLOCK#

PCI_IRDY#

PCI_SERR#

PCI_PERR#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

PCI_PIRQE#

PCI_PIRQF#

PCI_PIRQG#

PCI_PIRQH#

PCI_REQ0#

PCI_REQ1#

PCI_REQ2#

PCI_REQ3#

4

U5B

A11

AD0

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

B12 A10

C12

A8 A12 E10 C11

B9

D8 A4 E8 A3 D9 C8 C2 D7 B3

D11

B6 D5 D3 F4 E3 E4 B2 C4 C1 D1 E2

J4

H2

F1 F5 F2

PCI

AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

Interrupt I/F

PIRQA# PIRQB# PIRQC# PIRQD#C7PIRQH#/GPIO5

ICH9-M SFF ES_FCBGA569

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4

PAR

3

PCI_REQ0#

G4

PCI_GNT0#

E1

PCI_REQ1#

A9 E12

PCI_REQ2#

B11 C10

PCI_REQ3#

D6

PCI_GNT3#

C6

D10 A5 E6 C9

PCI_IRDY#

C3 B1 T3

PCI_DEVSEL#

A7

PCI_PERR#

D4

PCI_PLOCK#

C5

PCI_SERR#

H5

PCI_STOP#

A6

PCI_TRDY#

A2

PCI_FRAME#

B8

PLT_RST#

A21 B5 T1

G3 G1 F3 H4

CLK_PCI_ICH PCI_PME#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PLT_RST# <8,21> CLK_PCI_ICH <16> PCI_PME# <21>

2

1

B B

PCI_GNT3#

A A

A16 swap override Strap

Low= A16 swap override Enble High= Default

PCI_GNT3#

5

*

12

R181

1K_0402_5% @

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

12

R182

R182 1K_0402_5%

1K_0402_5%

@

1

0

1

0

1

PCI_GNT0#

DEL J3. 9/29

4

Boot BIOS Location

SPI

PCI

LPC

*

KBC_SPI_CS1#<19>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place closely pin B10

CLK_PCI_ICH

12

R183

1K_0402_5%@

2006/02/20 2009/02/20

12

@

R180

R180 10_0402_5%

10_0402_5%

1

@

C235

8.2P_0402_50V

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

LS-5581P

1

of

17 30T hursday, July 23, 2009

of

17 30T hursday, July 23, 2009

of

17 30T hursday, July 23, 2009

2.0

+RTCVCC

1 2

R184 330K _0402_1%

1 2

R185 1M _0402_5%R185 1M_0402_5%

1 2

R186 330K _0402_1%R186 330K_0402_1%

1 2

R187 20K_ 0402_5%

Change from 180K to 20K & 0.1u to 1u. 9/29

D D

5

LAN100_SLP

SM_INTRUDER#

ICH_INTVRMEN

ICH_SRTCRST#

C236

1U_0603_10V4Z

1

2

0_0402_5%

@

1 2

R189

R188

4

3

2

1

ICH_RSVD HDA_SDOUT_CODEC

0 0 0 1 1 1

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

1 2

R191 1K_0402_5%@R 191 1K_0402_5%@

1 2

R193 1K_0402_5%@R 193 1K_0402_5%@

C C

Remove R227 & C199

B B

1 0

HDA_SDOUT

ICH_RSVD

Add C599 ~ C602 to solve WWAN noise issue. 1/23

Normal(D) PCIE Bit1

HDA_BITCLK

Description

RV XOR

ICH_RSVD <19>

C1047 12P_0402_50V8J@ C1047 12P_0402_50V8J@

1 2

ICH_RTCRST#<21>

U5A

ICH_RTCX1

R318

IDE_LED#<21>

1 2

20K_0402_5%

1U_0603_10V4Z

+1.5VS

HDA_SDIN0<21> HDA_SDIN1<21> HDA_SDIN2<8>

+3VS

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_CR SATA_TXP0_CR

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_CR SATA_TXP1_CR

C1044

HDA_SDOUT<21>

R209 10K_0402_5% R 209 10K_0402_5%

R198 24.9_0402_1% R198 24.9_0402_1%

HDA_BITCLK<21> HDA_SYNC<21>

+RTCVCC

SATA_RXN0_C<21>

SATA_RXP0_C<21> SATA_TXN0_CR<21> SATA_TXP0_CR<21>

SATA_RXN1_C<21>

SATA_RXP1_C<21> SATA_TXN1_CR<21> SATA_TXP1_CR<21>

ICH_RTCRST#

1

12

CLRP1

CLRP1 SHORT PADS

SHORT PADS

2

1 2

HDA_RST#<21>

12

C1051 0.01U_0402_16V7KC1051 0.01U_0402_16V 7K

1 2

C1052 0.01U_0402_16V7KC1052 0.01U_0402_16V 7K

1 2

C1053 0.01U_0402_16V7KC1053 0.01U_0402_16V 7K

1 2

C1054 0.01U_0402_16V7KC1054 0.01U_0402_16V 7K

1 2

ICH_RTCX2

ICH_SRTCRST# SM_INTRUDER#

ICH_INTVRMEN LAN100_SLP

T47PAD T47PA D

HDA_SDOUT

T49PAD T49PAD

SATA_TXN0_R SATA_TXP0_R

SATA_TXN1_R SATA_TXP1_R

GLAN_COMP

HDA_BITCLK HDA_SYNC

HDA_RST#

U5A

F25

RTCX1

G25

RTCX2

G24

RTCRST#

C24

SRTCRST#

C23

INTRUDER#

E25

INTVRMEN

D25

LAN100_SLP

G22

GLAN_CLK

D14

LAN_RSTSYNC

A14

LAN_RXD0

D12

LAN_RXD1

B14

LAN_RXD2

D13

LAN_TXD0

C13

LAN_TXD1

A13

LAN_TXD2

D15

GPIO56

H22

GLAN_COMPI

H21

GLAN_COMPO

AE7

HDA_BIT_CLK

AB7

HDA_SYNC

AA7

HDA_RST#

AB6

HDA_SDIN0

AE6

HDA_SDIN1

AC6

HDA_SDIN2

AA5

HDA_SDIN3

AC7

HDA_SDOUT

AD8

HDA_DOCK_EN#/GPIO33

AB8

HDA_DOCK_RST#/GPIO34

AC9

SATALED#

AE14

SATA0RXN

AD14

SATA0RXP

AC15

SATA0TXN

AD15

SATA0TXP

AD13

SATA1RXN

AC13

SATA1RXP

AA14

SATA1TXN

AB14

SATA1TXP

ICH9-M SFF ES_FCBGA569

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

SATA4RXN SATA4RXP

IHDA

SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

10M_0402_5%

C24612P_0402_50V8J C24612P_0402_50V8J

1

2

INIT# INTR

NMI

SMI#

TP11

1 2

R215

1

2

IN

LPC_AD0

H3

LPC_AD1

J3

LPC_AD2

K5

LPC_AD3

L3

J2

H1 J1

GATEA20

N3 AB23

H_DPRSTP_R#

AE23 AE24

H_FERR#_R

AD25

AE22

AD23

AE21 AD24

KB_RST#

L1

AD21

H_SMI#

AC21

H_STPCLK#

AC25

THRMTRIP_ICH#

AC23

AC22

AD12 AE12 AB12 AA12

AC11 AD11 AB10 AA10

AC16 AB16

AD10 AE10

Y2

4

T48 PADT48 PAD

SATA_TXN2_R

SATA_TXP2_R

CLK_PCIE_SATA# CLK_PCIE_SATA

R212 24.9_0402_1%

Within 500 mils

ICH_RTCX1

ICH_RTCX2

C24712P_0402_50V8J C24712P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ2A251Y232.768KHZ_12.5P_1TJS125BJ2A251

1

OUT

2

NC3NC

LPC_AD[0..3] <21>

LPC_FRAME# <21>

T46 PADT46 PAD

GATEA20 <21> H_A20M# <4>

R194 0_0402_5% R194 0_0402_5%

1 2

H_DPSLP# <5>

R195 56_0402_5%R195 56_0402_5%

1 2

H_PWRGOOD <5>

H_IGNNE# <4>

H_INIT# <4> H_INTR <4>

KB_RST# <21>

H_NMI <4> H_SMI# <4>

H_STPCLK# <4>

R206 54.9_0402_1%R206 54.9_0402_1%

1 2

placed within 2" from ICH9M

C1056 0.01U_0402_16V7KC1056 0.01U_0402_16V 7K

1 2

C1065 0.01U_0402_16V7KC1065 0.01U_0402_16V 7K

1 2

0408

CLK_PCIE_SATA# <16> CLK_PCIE_SATA <16>

1 2

SATA_TXN2_CR

SATA_TXP2_CR

9/27

for H_DPRSTP# & H_DPSLP#.

H_DPRSTP# <5,8,28>

H_FERR#

Place Close to U8.

+VCCP

12

R201

R201 56_0402_5%

56_0402_5%

SATA_RXN2_C SATA_RXP2_C

9/27Del PU R203~R204

+VCCP

GATEA20 KB_RST#

H_THERMTRIP# <4,8>

SATA_RXN2_C <21> SATA_RXP2_C <21>

SATA_TXN2_CR <21>

SATA_TXP2_CR <21>

R192

R192 56_0402_5%

56_0402_5%

1 2

H_FERR# <4>

R196 10K_0402_5%R196 10K_0402_5%

1 2

R197 10K_0402_5%R197 10K_0402_5%

1 2

+3VS

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

LS-5581P

1

2.0

of

18 30T hursday, July 23, 2009

of

18 30T hursday, July 23, 2009

of

18 30T hursday, July 23, 2009

GPIO48

GPIO1

SIRQ

PM_CLKRUN#

THERM_SCI#

GPIO22

NPCI_RST#

GPIO17

GPIO37

GPIO18

GPIO57

LINKALERT#

PCIE_WAKE#

EC_SWI#

XDP_DBRESET#

S4_STATE#

ICH_LOW_BAT#

GPIO24

AC_IN

ME__EC_CLK1

ME__EC_DATA1

USB_OC#7

45

USB_OC#5

36

USB_OC#0

27

USB_OC#4

18

USB_OC#1

45

USB_OC#6

36

GPIO44

27

USB_OC#2

18

USB_OC#10

USB_OC#11

USB_OC#9

LID_SW#

GPIO42

WOL_EN

ICH_SMBDATA<14,15,16,21>

ICH_SMBCLK<14,15,16,21>

5

Add R621 in 12/03.

GPIO38

GPIO21

HDD_HALTLED

GPIO39

GPIO38

GPIO21

HDD_HALTLED

GPIO39

R274

2.2K_0402_5%

ICH_SMBDATA

5

+3VS

12

H_STP_PCI#<16> H_STP_CPU#< 16>

R275

12

2.2K_0402_5%

S

10K_0402_5%@

VGATE<21,28>

+3VS

Q8

Q8 RHU002N06_SOT323

RHU002N06_SOT323

D

13

S

G

2

G

9/21

+3VS

12

R236

R235

2

10K_0402_5%@

R247 0_0402_5% R247 0_0402_5% R248 100K_0402_5% R2 48 100K_0402_5%

GPIO1<21> GPIO6<21>

R264 1K_0402_5% @R264 1K_0402_5% @

1 2

KBC_SPI_CS1#<17>

ICH_SMB_DATA

D

ICH_SMB_CLKICH_SMBCLK

13

Q9

Q9 RHU002N06_SOT323

RHU002N06_SOT323

+3VS

1 2

R271 10K_0402_5%R271 10K_0402_5%

1 2

R220 10K_0402_5%

1 2

R222 10K_0402_5%

1 2

R225 8.2K_0402_5%

1 2

R227 8.2K_0402_5%@ R227 8.2K_0402_5%@

1 2

R231 8.2K_0402_5%

D D

C C

B B

A A

1 2

R232 10K_0402_5%

1 2

R233 8.2K_0402 _5%@ R233 8.2K_0402_5%@

1 2

R237 8.2K_0402_5%

1 2

R238 10K_0402_5%

1 2

R239 10K_0402_5%@ R239 10 K_0402_5%@

+3VALW

1 2

R244 10K_0402_5%R244 10K_0402_5%

1 2

R245 10K_0402_5%

1 2

R246 10K_0402_5%

1 2

R250 1K_0402_5%R250 1K_0402_5%

1 2

R252 10K_0402_5%

1 2

R254 10K_0402_5%

1 2

R256 10K_0402_5%R256 10K_0402_5%

1 2

R258 100K_0402_5%@R258 100K_0402_5%@

1 2

R259 10K_0402_5%R259 10K_0402_5%

1 2

R261 10K_0402_5%R261 10K_0402_5%

RP29

10K_1206_8P4R_5%

RP30

10K_1206_8P4R_5%

1 2

R281 10K_0402_5%R281 10K_0402_5%

1 2

R282 10K_0402_5%R282 10K_0402_5%

1 2

R272 10K_0402_5%R272 10K_0402_5%

1 2

R269 10K_0402_5%R269 10K_0402_5%

1 2

R270 10K_0402_5%R270 10K_0402_5%

1 2

R277 10K_0402_5%R277 10K_0402_5%

+3VS

R262 8.2K_0402 _5% R262 8.2K_0402_5%

R234 8.2K_0402_5%

R230 47K_0402 _5%R230 47K_0402_5%

R240 8.2K_0402_5%R24 0 8.2K_0402_5%

R279 10K_0402_5%@R279 10K_0402_5%@

R280 10K_0402_5%@R280 10K_0402_5%@

R242 47K_0402 _5%@ R242 47K_0402_5%@

R285 10K_0402_5%@R285 10K_0402_5%@

1 2

4

2.2K_0402_5%

EC_SWI#<21>

XDP_DBRESET#<4>

PM_BMBUSY#<8>

LID_SW#<21>

R444 0_0402_5%R444 0_0402_5%

1 2

PCIE_WAKE#<21>

THERM_SCI#<21>

1 2 1 2

EC_SMI#<21> EC_SCI#<21>

CLKSATAREQ#<16>

GPIO48<21>

SB_SPKR<21>

MCH_ICH_SYNC#<8>

ICH_RSVD<18>

GLAN_RXN<21> GLAN_RXP<21> GLAN_TXN<21>

GLAN_TXP<21>

PCIE_RXN2<21> PCIE_RXP2<21> PCIE_TXN2<21>

PCIE_TXP2<21>

PCIE_RXN4<21> PCIE_RXP4<21> PCIE_TXN4<21>

PCIE_TXP4<21>

GPIO42<21>

GPIO44<21>

4

+3VALW

12

R224

R223

2.2K_0402_5%

ICH_SMB_CLK ICH_SMB_DATA LINKALERT# ME__EC_CLK1 ME__EC_DATA1

EC_SWI#

XDP_DBRESET#

PM_BMBUSY#

LID_SW#

H_STP_PCI#

PM_CLKRUN#

PCIE_WAKE# SIRQ

SIRQ<21>

THERM_SCI#

VRMPWRGD

PAD

T51

GPIO1 GPIO6

T55PAD T55PA D

GPIO17 GPIO18

T52PAD T52PA D

GPIO22

T53PAD T53PA D T54PAD T54PA D

GPIO38 GPIO39 GPIO48

GPIO57

SB_SPKR MCH_ICH_SYNC# ICH_RSVD

T59PAD T59PA D

C271 0.1U_0402_10V7K C271 0.1U_0402_1 0V7K

1 2

C272 0.1U_0402_10V7K C272 0.1U_0402_1 0V7K

1 2

C265 0.1U_0402_10V7K

1 2

C266 0.1U_0402_10V7K

1 2

C269 0.1U_0402_10V7K

1 2

C270 0.1U_0402_10V7K

1 2

USB_OC#0<21> USB_OC#1<21> USB_OC#2<21>

12

R287

22.6_0402_1%

U5C

C18

SMBCLK

C15

SMBDATA

B21

LINKALERT#/GPIO60/CLGPIO4

E18

SMLINK0

A24

SMLINK1

C20

RI#

T5

SUS_STAT#/LPCPD#

C25

SYS_RESET#

L2

PMSYNC#/GPIO0

A23

SMBALERT#/GPIO11

B15

STP_PCI#/GPIO15

A20

STP_CPU#/GPIO25

M5

CLKRUN#/GPIO32

C21

WAKE#

L4

SERIRQ

AD20

THRM#

B24

VRMPWRGD

A19

TP12

AE16

GPIO1

AE18

GPIO6

AD18

GPIO7

B25

GPIO8

C14

GPIO12

D20

GPIO13

AE17

GPIO17

K3

GPIO18

AC8

GPIO20

AC19

SCLOCK/GPIO22

D17

GPIO27

E20

GPIO28

M4

SATACLKREQ#/GPIO35

AB18

SLOAD/GPIO38

AC18

SDATAOUT0/GPIO39

AB19

SDATAOUT1/GPIO48

AC20

GPIO49

A16

GPIO57/CLGPIO5

K4

SPKR

AB20

MCH_SYNC#

C19

TP3

AB17

TP8

AC17

TP9

AD17

TP10

ICH9-M SFF ES_FCBGA569

GLAN_RXN GLAN_RXP GLAN_TXN_C GLAN_TXP_C

PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2

PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4

USB_OC#0 USB_OC#1 USB_OC#2 GPIO42 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 GPIO44 USB_OC#9 USB_OC#10 USB_OC#11

USBRBIAS

Within 500 mils

3

GPIO21

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

V25 V24 U24 U23

W23 W24 V21 V22

Y24 Y25 Y21 Y22

AB24 AB25 AA23 AA24

T21 T22

AB21 AB22

AE2 AD1 AD3 AD4 AC2 AC3 AC5 AB4 AB2 AB1 AA3 AA2 Y1 Y2 W2 W3 V1 V2 Y5 Y4 U3 U2 V4 V5

AE19

HDD_HALTLED

AA18

NPCI_RST#

AE20

GPIO37

AA20

CLK_14M_ICH

K1

CLK_48M_ICH

AB5

ICH_SUSCLK

R3

SLP_S3#

D18

SLP_S4#

B20

SLP_S5#

D16

S4_STATE#

E14

D23

DPRSLPVR

M1

C16

U4

D22

D19

U1

T4

B23

C22 A18

E22 B18

F21 A17

C17 B17

A22 E16 A15 D21

ICH_LOW_BAT#

LAN_RST

EC_RSMRST#R

CK_PWRGD_R

M_PWROK

CL_CLK0

CL_DATA0

CL_VREF0_ICH

CL_RST#

GPIO24

AC_IN WOL_EN

R243 0_0402_5%R243 0_0402_5%

R253 0_0402_5%R253 0_0402_5%

Add WOL_EN back. 10/10

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0

DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1

DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2

DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

CLK_PCIE_ICH# CLK_PCIE_ICH

DMI_IRCOMP

USB20_N0 <21> USB20_P0 <21> USB20_N1 <21> USB20_P1 <21> USB20_N2 <21> USB20_P2 <21>

USB20_N3 <21>

USB20_P3 < 21> USB20_N4 <21> USB20_P4 <21> USB20_N5 <21> USB20_P5 <21> USB20_N6 <21> USB20_P6 <21>

USB20_N7 <21>

USB20_P7 < 21> USB20_N8 <21> USB20_P8 <21>

Compal Secret Data

Deciphered Date

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

SYS GPIO

Power MGTController Link

GPIO

MEM_LED/GPIO24

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

WOL_EN/GPIO9

MISC

U5D

T25

PERN1

T24

PERP1

R24

PETN1

R23

PETP1

P25

PERN2

P24

PERP2

P21 P22

N23

N24 M21 M22

M25 M24

K24

K25

K21

K22

H24

H25

E24

E23

F23

F22 G23

AE5 AD5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WLAN

PETN2 PETP2

PERN3 PERP3

EXP

PETN3 PETP3

PERN4 PERP4

L24

WWAN

PETN4

L23

PETP4

PERN5 PERP5 PETN5 PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP

J24

PETN6/GLAN_TXN

J23

PETP6/GLAN_TXP

SPI_CLK SPI_CS0# SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI SPI_MISO

P4

OC0#/GPIO59

N4

OC1#/GPIO40

N1

OC2#/GPIO41

P5

OC3#/GPIO42

P1

OC4#/GPIO43

P2

OC5#/GPIO29

M3

OC6#/GPIO30

M2

OC7#/GPIO31

P3

OC8#/GPIO44

R1

OC9#/GPIO45

R4

OC10#/GPIO46

R2

OC11#/GPIO47

USBRBIAS USBRBIAS#

ICH9-M SFF ES_FCBGA569

3

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N

GLAN

USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N

SPI

USBP5P USBP6N

USB

USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

2006/02/20 2009/02/20

2

CLK_14M_ICH <16> CLK_48M_ICH <16>

T50 PADT50 PAD

SLP_S3# <21> SLP_S4# <21> SLP_S5# <21>

R241 100K_0402_5% R2 41 100K_0402_5%

1 2

ON/OFFBTN# <21>

1 2

R453 10K_0402 _5%

1 2

M_PWROK <8>

CL_CLK0 <8>

CL_DATA0 <8>

CL_RST# <8>

GPIO24 < 21>

AC_IN <21>

DMI_RXN0 <8> DMI_RXP0 <8> DMI_TXN0 <8> DMI_TXP0 <8>

DMI_RXN1 <8> DMI_RXP1 <8> DMI_TXN1 <8> DMI_TXP1 <8>

DMI_RXN2 <8> DMI_RXP2 <8> DMI_TXN2 <8> DMI_TXP2 <8>

DMI_RXN3 <8> DMI_RXP3 <8> DMI_TXN3 <8> DMI_TXP3 <8>

CLK_PCIE_ICH# <16> CLK_PCIE_ICH <16>

R276 24.9_0402_1% R276 24.9_0402_1%

1 2

2

PM_PWROK <8,21,28>

PM_DPRSLPVR <8,28>

CK_PWRGD <16>

1

2

C263

0.1U_0402_16V4Z

EC_RSMRST#<21 >

Within 500 mils

1

1 2

R221 0_0402_5%R221 0_0402_5%

R257

3.24K_0402_1%

1 2

12

R260

453_0402_1%

M_PWROKPM_PWROK

+3VS

LAN_RST

12

R27310K_0402_5% R27310K_0402_5%

RSMRST circuit

R454

@R454

@

0_0402_5%

1 2

C

EC_RSMRST#R

1

3

E

Q26

Q26 MMBT3906_SOT23-3

BAV99DW-7_SOT363

5

D13B

@

R456

2.2K_0402_5%

1 2

R457

1 2

2.2K_0402_5%

+1.5VS

Title

Size Document Number Rev

Custom

Date: Sheet

3

12

@

R283

R283 10_0402_5%

10_0402_5%

@

1

C273

4.7P_0402_50V8C

2

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

LS-5581P

B

2

4

1

2

6

MMBT3906_SOT23-3

1 2

R455 4.7K_0402_5%R455 4.7K_0402_5%

D13A

D13A BAV99DW-7_SOT363

BAV99DW-7_SOT363

Place closely pin H1Place closely pin AF3

CLK_14M_ICHCLK_48M_ICH

12

@

R284

R284 10_0402_5%

10_0402_5%

@

1

C274

4.7P_0402_50V8C

2

19 30T hursday, July 23, 2009

1

+3VALW

of

2.0

5

+RTCVCC

C275

0.1U_0402_16V4Z

R289

BLM18PG181SN1D_0603

21

D5

CH751H-40_SC76

ICH_V5REF_RUN

1

C291

1U_0402_6.3V6K

2

1 2

MBK1608301YZF 0603

R298

0.1U_0402_16V4Z

1 2

20 mils

R296

+1.5VS_USBPLL

0.1U_0402_16V4Z

+1.5VS

1

2

C309

5

1U_0402_6.3V6K

1

2

C307

C306

0.1U_0402_16V4Z

R304

R304 MBK1608301YZF 0603

MBK1608301YZF 0603

1 2

C296

D D

C C

B B

+1.5VS

MBK1608301YZF 0603

A A

+1.5VS

+5VS +3VS +3VALW+5VALW

12

R293

100_0402_5%

9/19

+1.5VS

1 2

+3VS

R303

1 2

1

C276

2

0.1U_0402_16V4Z

1

+

C279

2

C282

220U_D2_4VM_R15

R294

100_0402_5%

1

2

C297

10U_0603_6.3V6M

C308

0.1U_0402_16V4Z

12

C310

20 mils

+1.5VS_PCIE_ICH

40 mils

1

2

C280

10U_0603_6.3V6M

12

+1.5VS

+1.5VS_PCIE_ICH

1

2

10U_0603_6.3V6M

ICH_V5REF_RUN

ICH_V5REF_SUS

1

2

C281

10U_0603_6.3V6M

2.2U_0402_6.3V6M

21

D6

CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C292

0.1U_0402_16V4Z

2

+1.5VS_VCCSATAPLL

1

2

C298

1U_0603_10V4Z

1

2

C299

1U_0603_10V4Z

1

2

C303

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH

+1.5VS_GLAN

1

2

C311

10U_0603_6.3V6M

+3VS

4

U5F

G17

VCCRTC

G7

V5REF

U7

V5REF_SUS

J19

VCC1_5_B[01]

K18

VCC1_5_B[02]

K19

VCC1_5_B[03]

L18

VCC1_5_B[04]

L19

VCC1_5_B[05]

M18

VCC1_5_B[06]

M19

VCC1_5_B[07]

N18

VCC1_5_B[08]

N19

VCC1_5_B[09]

P18

VCC1_5_B[10]

R18

VCC1_5_B[11]

T18

VCC1_5_B[12]

T19

VCC1_5_B[13]

U18

VCC1_5_B[14]

U19

VCC1_5_B[15]

W17

VCCSATAPLL

U13

VCC1_5_A[01]

V13

VCC1_5_A[02]

W13

VCC1_5_A[03]

U12

VCC1_5_A[04]

V12

VCC1_5_A[05]

W12

VCC1_5_A[06]

W10

VCC1_5_A[07]

U15

VCC1_5_A[08]

V15

VCC1_5_A[09]

W18

VCC1_5_A[10]

G9

VCC1_5_A[11]

H9

VCC1_5_A[12]

V11

VCC1_5_A[13]

U11

VCC1_5_A[14]

U8

VCCUSBPLL

T9

VCC1_5_A[15]

U9

VCC1_5_A[16]

G11

VCCLAN1_05[1]

H11

VCCLAN1_05[2]

G12

VCCLAN3_3[1]

H13

VCCLAN3_3[2]

J17

VCCGLANPLL

H19

VCCGLAN1_5[1]

J18

VCCGLAN1_5[2]

K16

VCCGLAN3_3

ICH9-M SFF ES_FCBGA569

4

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03]

VCCPSUSVCCPUSB

VCCSUS3_3[04]

VCCSUS3_3[05] VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01]

VCC3_3[02]

VCC3_3[03] VCC3_3[04] VCC3_3[05]

VCC3_3[06] VCC3_3[07] VCC3_3[08]

VCCHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

L11 L12 L13 L14 L15 M11 M15 N11 N15 P11 P15 R11 R12 R13 R14 R15

P19

T17 U17

V16 U16

V18

AE9

AA9 V14 W14

G8 H7 H8

AD7

V10

T7 H15

H16

V7

G14 G15 H14

W8

J7 J8 K7 K8 L7 L8 M7 M8 N7 N8 P7 P8

G18

H17

J14 K14

+VCCP

+1.5VS_DMIPLL

VCCSUS1_05_ICH_1 VCCSUS1_05_ICH_2

VCCSUS1_5_ICH_1

VCCSUS1_5_ICH_2

VCCCL1_05_ICH

1 2

C305 1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

2

C277

C278

0.1U_0402_16V4Z

1

2

C283

1U_0603_10V4Z

0.01U_0402_16V7K

9/29

VCC_DMI

(DMI)

+3VS

1

2

C293

0.1U_0402_16V4Z

T60T60 T61T61

T62T62

T63T63

+3VALW

1

2

C302

4.7U_0603_6.3V6K

9/21

C304

0.1U_0402_16V4Z

1 2

+3VS

9/21

3

R290

1 2

MBK1608301YZF 0603

1

2

C284

R292

1 2

MBK1608301YZF 0603

0.1U_0402_16V4Z

1

2

C289

C290

C288

R322 0_0603 _5%@ R322 0_0603_5%@

R323 0_0603 _5%R323 0_0603_5%

R319 180 _0402_1%R319 180_0402_1%

1 2

12

1

2

C295

0.1U_0402_16V4Z

1

2

C300

0.1U_0402_16V4Z

1 2

R320

R324 0_0603_5%

150_0402_1%

@

+3VALW

1

2

C301

0.1U_0402_16V4Z

2006/02/20 2009/02/20

+1.5VS

9/29

+VCCP

+3VS

1 2

+1.5VALW

Compal Secret Data

9/29

VCC_DMI

1

2

C285

1U_0603_10V4Z

0.1U_0402_16V4Z

+3VALW

Deciphered Date

+VCCP

1

2

C286

C287

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

+3VS

+1.5VS

1

2

C294

2

U5E

B4

VSS[001]

B7

VSS[002]

B10

VSS[003]

B13

VSS[004]

B16

VSS[005]

B19

VSS[006]

B22

VSS[007]

D2

VSS[008]

D24

VSS[009]

E5

VSS[010]

E7

VSS[011]

E9

VSS[012]

E11

VSS[013]

E13

VSS[014]

E15

VSS[015]

E17

VSS[016]

E19

VSS[017]

E21

VSS[018]

F24

VSS[019]

G2

VSS[020]

G5

VSS[021]

G10

VSS[022]

G13

VSS[023]

G16

VSS[024]

G19

VSS[025]

G21

VSS[026]

H10

VSS[027]

H12

VSS[028]

H18

VSS[029]

H23

VSS[030]

J5

VSS[031]

J9

VSS[032]

J10

VSS[033]

J11

VSS[034]

J12

VSS[035]

J13

VSS[036]

J15

VSS[037]

J21

VSS[038]

J22

VSS[039]

J25

VSS[040]

K2

VSS[041]

K9

VSS[042]

K10

VSS[043]

K11

VSS[044]

K12

VSS[045]

K13

VSS[046]

K15

VSS[047]

K17

VSS[048]

K23

VSS[049]

L5

VSS[050]

L9

VSS[051]

L10

VSS[052]

L16

VSS[053]

L17

VSS[054]

L21

VSS[055]

L22

VSS[056]

L25

VSS[057]

M9

VSS[058]

M10

VSS[059]

M12

VSS[060]

M13

VSS[061]

M14

VSS[062]

M16

VSS[063]

M17

VSS[064]

M23

VSS[065]

N2

VSS[066]

N5

VSS[067]

N9

VSS[068]

N10

VSS[069]

N12

VSS[070]

N13

VSS[071]

N14

VSS[072]

N16

VSS[073]

N17

VSS[074]

N21

VSS[075]

N22

VSS[076]

N25

VSS[077]

P9

VSS[078]

P10

VSS[079]

P12

VSS[080]

P13

VSS[081]

P14

VSS[082]

P16

VSS[083]

P17

VSS[084]

P23

VSS[085]

R5

VSS[086]

R7

VSS[087]

R8

VSS[088]

R9

VSS[089]

R10

VSS[090]

R16

VSS[091]

R17

VSS[092]

R19

VSS[093]

R21

VSS[094]

R22

VSS[095]

R25

VSS[096]

T2

VSS[097]

T8

VSS[098]

T10

VSS[099]

T11

VSS[100]

T12

VSS[101]

T13

VSS[102]

T14

VSS[103]

T15

VSS[104]

T16

VSS[105]

T23

VSS[106]

ICH9-M SFF ES_FCBGA569

2

1

U5

VSS[107]

U10

VSS[108]

W11

VSS[109]

U14

VSS[110]

W16

VSS[111]

U21

VSS[112]

U22

VSS[113]

U25

VSS[114]

V3

VSS[115]

V8

VSS[116]

V19

VSS[117]

V23

VSS[118]

W1

VSS[119]

W4

VSS[120]

W5

VSS[121]

W7

VSS[122]

W9

VSS[123]

W15

VSS[124]

W19

VSS[125]

W21

VSS[126]

W22

VSS[127]

W25

VSS[128]

Y3

VSS[129]

Y23

VSS[130]

AA1

VSS[131]

AA4

VSS[132]

AA6

VSS[133]

AA8

VSS[134]

AA11

VSS[135]

AA13

VSS[136]

AA15

VSS[137]

AA16

VSS[138]

AA17

VSS[139]

AA19

VSS[140]

AA21

VSS[141]

AA22

VSS[142]

AA25

VSS[143]

AB3

VSS[144]

AB9

VSS[145]

AB11

VSS[146]

AB13

VSS[147]

AB15

VSS[148]

AC24

VSS[149]

AC1

VSS[150]

AC4

VSS[151]

AC10

VSS[152]

AC12

VSS[153]

AC14

VSS[154]

AD2

VSS[155]

AD6

VSS[156]

AD9

VSS[157]

AD16

VSS[158]

AD19

VSS[159]

AD22

VSS[160]

AE3

VSS[161]

AE4

VSS[162]

AE11

VSS[163]

AE13

VSS[164]

AE15

VSS[165]

V17

VSS[166]

AE8

VSS[167]

V9

VSS[168]

J16

VSS[169]

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04]

A1 A25 AE1 AE25

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

LS-5581P

1

2.0

of

20 30T uesday, July 21, 2009

of

20 30T uesday, July 21, 2009

of

20 30T uesday, July 21, 2009

5

+RTCVCC

1

2

C1055

GPIO

WWAN

WLAN

LAN

C1055

2.2U_0603_6.3V4Z

EC_SMB_DA2<4> EC_SMB_CK2<4>

L_BKLT_CTRL<10>

EC_RSMRST#<19>

PM_PWROK<8,19,28>

USB_OC#2<19> USB_OC#1<19> USB_OC#0<19>

ON/OFFBTN#<19>

LPC_FRAME#<18>

CLKREQG_WWAN #<16>

CLKREQ_WLAN#<16>

ICH_SMBDATA<14,15,16,19>

PCIE_WAKE#<19>

PCI_PME#<17>

CLK_48M_CR< 16>

CLK_PCIE_WAN#<16> CLK_PCIE_WAN<16>

CLK_PCIE_MCARD#<16> CLK_PCIE_MCARD<16>

CLK_PCIE_LAN#<16> CLK_PCIE_LAN<16>

+RTCVCC

GPIO1<19>

GPIO6<19> GPIO48<19>

EC_SMI#<19>

PCIE_TXP4<19> PCIE_TXN4<19>

PCIE_RXP4<19> PCIE_RXN4<19>

PCIE_TXP2<19> PCIE_TXN2<19>

PCIE_RXP2<19> PCIE_RXN2<19>

GLAN_TXN<19> GLAN_TXP<19>

GLAN_RXN<19> GLAN_RXP<19>

SLP_S4#<19>

VGATE<19,28>

LID_SW#<19> GPIO24<19>

EC_SWI#<19>

SUSP#<22,26,27,29> AC_IN<19>

SLP_S5#<19>

SLP_S3#<19> EC_SCI#<19>

PLT_RST#<8,17>

SYSON<22,25,29> LPC_AD0<18> LPC_AD1<18> LPC_AD2<18> LPC_AD3<18>

SIRQ<19> KB_RST#<18> GATEA20<18>

HDMI_HPD#<10> CLK_PCI_EC<16>

HDMIDAT<8> HDMICLK<8>

TX2D+<10> TX2D-<10>

TX1D+<10> TX1D-<10>

TX0D+<10> TX0D-<10>

TXCD+<10> TXCD-<10>

ICH_SMBCLK<14,15,16,19>

CLKREQA#<16>

D D

C C

B B

HDMI

WWAN_CLK

WLAN_CLK

LAN_CLK

VS

MAINPWON<28>

ICH_RTCRST#<18>

4

B+

0.1U_0603_50V4Z~D

C1033

1

2

JP6

1

B+

3

B+

5

B+

7

B+

9

B+

11

B+

13

B+

15

RESERVED

17

GND

19

GND

21

GND

23

MAINPWON

25

+RTCVCC

27

ICH_RTCRST#

29

GPIO1

31

EC_SMB_DA2

33

EC_SMB_CK2

35

GPIO6

37

GPIO48

39

EC_SMI#

41

L_BKLT_CTRL

43

PETP4

45

PETN4

47

GND

49

PERP4

51

PERN4

53

GND

55

PETP2

57

PETN2

59

GND

61

PERP2

63

PERN2

65

GND

67

PETN1

69

PETP1

71

GND

73

PERN1

75

PERP1

77

GND

79

SLP_S4#

81

VGATE

83

PM_RSMRST#

85

LID_SW#

87

GPIO24

89

PM_PWROK

91

EC_SWI#

93

SUSP#

95

AC_IN

97

USB_OC2#

99

USB_OC1#

101

USB_OC0#

103

ON/OFFBTN#

105

SLP_S5#

107

SLP_S3#

109

EC_SCI#

111

PLT_RST#

113

SYSON

115

LPC_AD0

117

LPC_AD1

119

LPC_AD2

121

LPC_AD3

123

LPC_FRAME#

125

SIRQ

127

KB_RST#

129

GATEA20

131

CLKREQG_WWAN #

133

RESERVED

135

HDMI_HPD#

137

CLK_PCI_EC

139

GND

141

HDMIDAT

143

HDMICLK

145

GND

147

TX2D+

149

TX2D-

151

GND

153

TX1D+

155

TX1D-

157

GND

159

TX0D+

161

TX0D-

163

GND

165

TXCD+

167

TXCD-

169

GND

171

CLKREQ_WLAN#

173

ICH_SMBDATA

175

ICH_SMBCLK

177

PCIE_WAKE#

179

PCI_PME#

181

CLK_48M_CR

183

CLKREQA#

185

CLK_PCIE_WAN#

187

CLK_PCIE_WAN

189

GND

191

CLK_PCIE_MCARD#

193

CLK_PCIE_MCARD

195

HDI_B_DET/GND

197

CLK_PCIE_LAN#

199

CLK_PCIE_LAN

HDI_B_DET/GND

THERM_SCI#

L_DDC_DATA

CRT_DDC_DATA

CRT_DDC_CLK

LCDSA_DATA_1

LCDSA_DATA#_1

LCDSA_DATA_0

LCDSA_DATA#_0

LCDSA_DATA_2

LCDSA_DATA#_2

LCDSA_CLK#

+5VS

+5VALW

+3VALW

+3VS +3VS +3VS

VR_ON

GND GND GND

SB_SPKR

HDA_RST#

HDA_SDOUT

HDA_SYNC

HDA_BITCLK

HDA_SDIN0 HDA_SDIN1

DE_LED#

SATA0TXP

SATA0TXN

GND

GPIO42

GND

SATA1TXP

SATA1TXN

GND

1.5VS

1.5VS GND

SATA2TXP

SATA2TXN

GND

SATA2RXP SATA2RXN

GND

SATA0RXP SATA0RXN

GND

USB20_P7

USB20_N7

GND

SATA1RXP SATA1RXN

GND

USB20_P5

USB20_N5

GND

USB20_P4

USB20_N4

GND

USB20_P3

USB20_N3

GND

GPIO44

GND

USB20_P8

USB20_N8

GND

USB20_P6

USB20_N6

GND

USB20_P1

USB20_N1

GND

USB20_P2

USB20_N2

GND

USB20_P0

USB20_N0

GND

ENABLT

ENAVDD

L_DDC_CLK

CRT_VSYNC

CRT_HSYNC

GND

CRT_RED

GND

CRT_GREEN

GND

CRT_BLUE

GND

LCDSA_CLK

3

2

1

HDI_B_DET

2 4 6

+VL

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

+1.5VS

+5VS +5VALW VL +3VALW +3VS

VR_ON <28>

SB_SPKR <19> HDA_RST# <18> HDA_SDOUT <18> HDA_SYNC <18> HDA_BITCLK <18> HDA_SDIN0 <18> HDA_SDIN1 <18>

IDE_LED# <18>

SATA_TXP0_CR <18> SATA_TXN0_CR <18>

THERM_SCI# <19>

GPIO42 <19>

SATA_TXP1_CR <18> SATA_TXN1_CR <18>

SATA_TXP2_CR <18> SATA_TXN2_CR <18>

SATA_RXP2_C <18> SATA_RXN2_C <18>

SATA_RXP0_C <18> SATA_RXN0_C <18>

USB20_P7 <19> USB20_N7 <19>

SATA_RXP1_C <18> SATA_RXN1_C <18>

USB20_P5 < 19> USB20_N5 <19>

USB20_P4 < 19> USB20_N4 <19>

USB20_P3 <19> USB20_N3 <19>

GPIO44 <19>

USB20_P8 < 19> USB20_N8 <19>

USB20_P6 < 19> USB20_N6 <19>

USB20_P1 < 19> USB20_N1 <19>

USB20_P2 < 19> USB20_N2 <19>

USB20_P0 < 19> USB20_N0 <19>

ENABLT <10> ENAVDD <10>

DDC2_DATA <10> DDC2_CLK <10> CRT_VSYNC <10> CRT_HSYNC <10>

CRT_DDC_DATA <10> CRT_DDC_CLK <10>

D_RED <10>

D_GREEN <10>

D_BLUE <10>

TXOUT_L1+ <10> TXOUT_L1- <10>

TXOUT_L0+ <10> TXOUT_L0- <10>

TXOUT_L2+ <10> TXOUT_L2- <10>

TXCLK_L+ <10> TXCLK_L- <10>

GPIO

USB

LVDS

SATA

R314

R315

R316

R317

HDA_BITCLK

HDA_RST#

HDA_SDOUT

HDA_SYNC

HDA_BITCLK_NB<8>

HDA_RST#_NB<8>

HDA_SDOUT_NB<8>

HDA_SYNC_NB<8>

1 2

33_0402_5%

1 2

33_0402_5%

1 2

33_0402_5%

1 2

33_0402_5%

A A

0409

5

HDI_B_DET

4

FPC_O0P45X2P35

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LCD CONN & Q-Switch & GPIO Ext.

LS-5581P

1

of

21 30T hursday, July 23, 2009

of

21 30T hursday, July 23, 2009

of

21 30T hursday, July 23, 2009

2.0

5

D D

2

C241

33P_0402_50V8J

1

@

2

C240

33P_0402_50V8J

1

@

2

C239

33P_0402_50V8J

1

@

4

+VCCP+1.5V

SYSON<21,25,29> SUSP# <21,26,27,29>

100K_0402_5%

SYSON# SUSP

SYSON

Q17A

R307

2

3

+5VALW+5VA LW

12

61

R308

100K_0402_5%

3

Q17B

SUSP#

2N7002DW-7-F_SOT363-6

5

4

2N7002DW-7-F_SOT363-6

2

1

R311

470_0402_5%

Q19A

2

+1.5V

12

61

2N7002DW-7-F_SOT363-6

+1.8V

12

R309

470_0402_5%

C C

SUSP SUSPSYSON#SUSP

Q18A

61

2

2N7002DW-7-F_SOT363-6

R310

470_0402_5%

Q18B

5

12

3

4

2N7002DW-7-F_SOT363-6

+1.5V to +1.5VS

+1.5V

U13

8

S

D

7

S

D

6

S

D

1

C1178

R396

R396 100K_0402_5%

100K_0402_5%

SUSP

Q25

Q25 2N7002_SOT23

2N7002_SOT23

C1178

2

G

2

10U_0805_10V4Z

13

+1.5VS_GATE

D

S

B B

B+

5

SI4800BDY-T1-E3_SO8

R443

R443 0_0402_5%

0_0402_5%

@

1 2

G

D

0.1U_0603_25V7K

1 2 3 4

1

2

C1281

@

+1.5VS

1

C1176

2

1

C1180

0.1U_0603_25V7K

2

1

C1177

2

10U_0805_10V4Z

+0.75VS+VCCP

12

R312

470_0402_5%

3

Q19B

5

4

2N7002DW-7-F_SOT363-6

R395

470_0603_5%

1 2

13

D

1U_0603_10V4Z

S

SUSP

2

G

Q24

Q24 2N7002_SOT23

2N7002_SOT23

H1 HOLEAH1HOLEA

1

H10

H10 HOLEA

HOLEA

1

H2 HOLEAH2HOLEA

1

H9 HOLEAH9HOLEA

1

H3 HOLEAH3HOLEA

1

H4 HOLEAH4HOLEA

1

H8 HOLEAH8HOLEA

1

FM1FM11FM2FM2

1

Modify to 4.0mm

H6

H5

HOLEAH6HOLEA

HOLEAH5HOLEA

1

FM4FM4

FM3FM3

1

H7 HOLEAH7HOLEA

1

H11

H11 HOLEA

HOLEA

1

H12

H12 HOLEA

HOLEA

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

LEDS & LID

LS-5581P

1

2.0

of

22 30T uesday, July 21, 2009

of

22 30T uesday, July 21, 2009

of

22 30T uesday, July 21, 2009

5

D ate

D ate D es c rebtio n

D ateD at e

4/1 6

4/1 6 R e l a ese L S 55 81 PR 01 sch e m atic.

4/1 64 /1 6

5/8

5/8 R 53 ch a ng e t o 4 99 O hm

5/85/8

D D

C C

B B

D escreb t i o n

D escreb t i o nD e screb t i o n

R e l a ese L S 55 81 PR 01 sch e m atic.

R e l a ese L S 55 81 PR 01 sch e m atic.R e l a ese L S 55 81 PR 01 sch e m atic.

R 5 3 c h an g e to 49 9 O hm

R 5 3 c h an g e to 49 9 O hm R 5 3 c h an g e to 49 9 O hm

R 6 8,R 69 ,R 7 0 im ple m en t 7 5O hm

R 6 8,R 69 ,R 7 0 im ple m en t 7 5O hmR 6 8,R 69 ,R 7 0 im ple m en t 7 5O hm

A d d C 13 03 fo r D D R3 req u e st

A d d C 13 03 fo r D D R3 req u e stA d d C 13 03 fo r D D R3 req u e st

C h an g e R 14 9 ,R 1 77 fr o m 3 3 t o 1 5O hm

C h an g e R 14 9 ,R 1 77 fr o m 3 3 t o 1 5O hmC h an g e R 14 9 ,R 1 77 fr o m 3 3 t o 1 5O hm

C h an g e C 233 , C 23 4 fro m 3 3 P t o 2 2P

C h an g e C 233 , C 23 4 fro m 3 3 P t o 2 2PCh a ng e C 23 3,C 23 4 from 3 3 P t o 2 2P

R 1 53 im plem ent 1 0 K_O hm a n d R 15 6 rem ov e

R 1 53 im plem ent 1 0 K_O hm a n d R 15 6 rem ov eR 1 53 im plem ent 1 0 K_O hm a n d R 15 6 rem ov e

A d d C 1 07 9,C 10 80 f o r E M I

A d d C 1 07 9,C 10 80 f o r E M IA d d C 1 07 9,C 10 80 f o r E M I

D elete R 2 49 ,R 2 55 ,R 2 67 ,R 2 68 for op t io n US B an d G PI O

D elete R 2 49 ,R 2 55 ,R 2 67 ,R 2 68 for op t io n US B an d G PI OD elete R 2 49 ,R 2 55 ,R 2 67 ,R 2 68 for op t io n US B an d G PI O

D elete C 1 06 6,C 1 06 7,C 10 68 ,C1 0 69 ,C 1 07 0 ,C 1 07 1 fo r S A TA A C c ap

D elete C 1 06 6,C 1 06 7,C 10 68 ,C1 0 69 ,C 1 07 0 ,C 1 07 1 fo r S A TA A C c apD elete C 1 06 6,C 1 06 7,C 10 68 ,C1 0 69 ,C 1 07 0 ,C 1 07 1 fo r S A TA A C c ap

A d d V L vo lta g e on JP 6.6 f o r O CP u s e

A d d V L vo lta g e on JP 6.6 f o r O CP u s eAdd V L v o l t a ge o n J P 6.6 for O C P u se

M od ify SB V CC SU SH DA po w er le v el

M od ify SB V CC SU SH DA po w er le v elM odify S B V CC SU SH DA p o w er l e v el

M od ify SB G LA N fro m PC I E4 to P C IE 1

M od ify SB G LA N fro m PC I E4 to P C IE 1M od ify SB G LA N fro m PC I E4 to P C IE 1

D elete R 2 65 ,C 2 64 ,C2 6 6 f o r C L_ RE F1

D elete R 2 65 ,C 2 64 ,C2 6 6 f o r C L_ RE F1D elete R 2 65 ,C 2 64 ,C2 6 6 f o r C L_ RE F1

D elete R 2 40 for H _S TP _C PU # a nd A dd R 4 44 for H _S TP _P CI#

D elete R 2 40 for H _S TP _C PU # a nd A dd R 4 44 for H _S TP _P CI#D elete R 2 40 for H _S TP _C PU # a nd A dd R 4 44 for H _S TP _P CI#

C h an g e R 22 1 con n e ct from V G A T E t o P M _ P W R OK

C h an g e R 22 1 con n e ct from V G A T E t o P M _ P W R OKC h an g e R 22 1 con n e ct from V G A T E t o P M _ P W R OK

C h an g e R 24 0 fr o m H _S T P_ CP U # to H _S TP _P CI#

C h an g e R 24 0 fr o m H _S T P_ CP U # to H _S TP _P CI#C h an g e R 24 0 fr o m H _S T P_ CP U # to H _S TP _P CI#

C h an g e E C_ SC I# fro m G PI O7 to G PI O1 2

C h an g e E C_ SC I# fro m G PI O7 to G PI O1 2C h an g e E C_ SC I# fro m G PI O7 to G PI O1 2

D elete T 5 6,T 5 7,T 58 , R 26 3 f o r n o use

D elete T 5 6,T 5 7,T 58 , R 26 3 f o r n o useD elete T 5 6,T 5 7,T 58 , R 26 3 f o r n o use

A d d R 28 1,R 28 2 fo r U SB O C# p ull high

A d d R 28 1,R 28 2 fo r U SB O C# p ull highA d d R 28 1,R 28 2 fo r U SB O C# p ull high

A d d R 24 2,R 28 5 fo r P roject ID d e f i n e

A d d R 24 2,R 28 5 fo r P roject ID d e f i n eA d d R 24 2,R 28 5 fo r P roject ID d e f i n e

M od ify H 5,H 6, H 7,H 11 ,H 12 foo t p rint for M E reco m ma n d

M od ify H 5,H 6, H 7,H 11 ,H 12 foo t p rint for M E reco m ma n dM od ify H 5,H 6, H 7,H 11 ,H 12 foo t p rint for M E reco m ma n d

D elete R 2 51 an d A d d Q 26 ,D 13 ,R 4 53 -R 4 57 for R SM RS T # fu n ction

D elete R 2 51 an d A d d Q 26 ,D 13 ,R 4 53 -R 4 57 for R SM RS T # fu n ctionD elete R 2 51 an d A d d Q 26 ,D 13 ,R 4 53 -R 4 57 for R SM RS T # fu n ction

D elete U SB 9 p air on S B fo r n o t u se

D elete U SB 9 p air on S B fo r n o t u seD ele te U SB 9 p air on S B fo r n o t use

M od ify C L K_ P CI_ E C from U 4.1 5 to U 4. 1 3

M od ify C L K_ P CI_ E C from U 4.1 5 to U 4. 1 3M od ify C L K_ P CI_ E C from U 4.1 5 to U 4. 1 3

M od ify p o w er plan e f r o m + 1.8 V S t o + 1 .8V for N B u se

M od ify p o w er plan e f r o m + 1.8 V S t o + 1 .8V for N B u seM od ify p o w er plan e f r o m + 1.8 V S t o + 1 .8V for N B u se

C h an g e N am e from D DR 3_ DIM M _R EF to D DR 3_ NB _ RE F fo r D D R 3 r e c o mm a nd

C h an g e N am e from D DR 3_ DIM M _R EF to D DR 3_ NB _ RE F fo r D D R 3 r e c o mm a ndC h an g e N am e from D DR 3_ DIM M _R EF to D DR 3_ NB _ RE F fo r D D R 3 r e c o mm a nd

C h an g e D D R P M _E XTT S# 1 from no t u s e t o J P 3

C h an g e D D R P M _E XTT S# 1 from no t u s e t o J P 3C h an g e D D R P M _E XTT S# 1 from no t u s e t o J P 3

D el R 10 6 fo r Inte l R ecom ma n d for H DM I s e t t i n g

D el R 10 6 fo r Inte l R ecom ma n d for H DM I s e t t i n gD el R 10 6 fo r Inte l R ecom ma n d for H DM I s e t t i n g

4

3

2

1

R e v .

R e v .Rev .

01

0101

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/20 2009/02/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-1

LS-5581P

1

of

23 30T uesday, July 21, 2009

of

23 30T uesday, July 21, 2009

of

23 30T uesday, July 21, 2009

2.0

5

4

3

2

1

AC

D D

Adapter in

Page37

VIN

SWITCHADP_EN#

EN0

LM393 Thermal Protector

Page39

2VREF_51125

+5VALW

B+

VDD VR_ON

PWR_GD

+3VALWP 3A

B+

TPS51125 DC/DC (3V/5V)

C C

51125_PWR

Page39

+5VALWP 4.5A

ISL6261ACRZ-T DC/DC (CPU_CORE)

Page47

CPU_CORE (ICCDES=18A)

+1.05VCCP 8A

Page41

BQ24740 Charger

Page41

B+

SLP_S4#

TPS51117 D (1.8V)

EN_PSV

C/DC

Page40

+1.8VP 8A

G2992

Page42

+0.9VP 2A

SLP_S3#

B+

EN1

TPS51117 DC/DC (1.05V)

B B

TPS51117

Switch

B+

ISL6263 DC/DC

VGA_COREP 5A

B+

SLP_S3#

EN2

DC/DC (1.5V)

Page42

+1.5ALWP 4A

(VGA_CORE)

GFXVN_EN

Page45

Battery

A A

Title

POWER BLOCK DIAGRAM

Size Document Number Rev

Date: Sheet

Date: Sheet of

5

4

3

2

of

24 30Tuesday, July 21, 2009

1

A

1 1

PR400

0_0402_ 5%

+1.5VP

1 2

@0.1U_04 02_16V7K

10.5K_04 02_1%

PR407

1 2

PC408

@10P_04 02_50V8J

PR409

10K_040 2_1%

PC400

12

+1.5VP

12

1 2

PR404 0_0402 _5%P R404 0_ 0402_5%

PC412

1 2

@22P_0402_50V8J

1.5V_PGO OD<8>

PR402

255K_04 02_1%

1 2

1.5V_VOU T

1.5V_VF5 FILT+5VALW

1.5V_VFB

SYSON<21,22,29 >

2 2

PR405

100_040 2_1%

1 2

+5VALW

3 3

PC406

4.7U_060 3_6.3V6K

12

PC413

0.47U_04 02_6.3V6K@

1.5V_EN

PU400

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

PR410

PR410 100K_04 02_1%

100K_04 02_1%

1 2

B

14

15

1

TP

VBST

EN_PSV

DRVH

V5DRV

GND7PGND

TPS5111 7RGYR_QFN14_3.5x3.5

8

+1.5VP

LL

TRIP

DRVL

PR401

0_0402_ 5%

1 2

13

12

11

10

9

BST_1.5V -1BST_1.5V

UG_1.5V

LX_1.5V

1.5V_TRIP

+5VALW

LG_1.5V

PC405

0.1U_040 2_10V7K

1 2

PR406

1 2

0_0402_ 5%

1 2

13.7K_04 02_1%

12

PC407

4.7U_080 5_10V6K

PR403

UG1_1.5V

C

PL400

HCB1608 KF-121T30_060 3

1 2

12

PC404

4.7U_0805_25V6M

578

3 6

241

PQ400

PQ400 AO4466_ SO8

AO4466_ SO8

+1.5V_B+

12

PC402

PC401

0.1U_0402_25V6

2200P_0402_50V7K

2.2UH_PC MC063T-2R2MN_ 8A_20%

12

PC403

4.7U_0805_25V6-K

PL401

1 2

D

B+

+1.5VP

12

786

5

PQ401

PQ401 AO4710_ SO8

AO4710_ SO8

4

123

+1.5VP

PR408

4.7_1206 _5%

12

PC411

PC411 680P_06 03_50V8J

680P_06 03_50V8J

PJP400

2

JUMP_43 X118@

4.7U_080 5_6.3V6K

112

PC409

+1.5V

1

12

+

PC410

2

220U_B2 _2.5VM_R25M

4 4

Security Class ification

2008/10/ 31 2 009/10/3 1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/10/ 31 2 009/10/3 1

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet

Compal Electronics, Inc.

1.5VP

LS-5581P

D

of

25 30Tuesday, July 21, 2009

of

25 30Tuesday, July 21, 2009

of

25 30Tuesday, July 21, 2009

2.0

5

D D

SUSP#<21,22,27,29>

C C

+5VALW

1 2

PR518

100_0402_1%

4.7U_0603_6.3V6K

PC520

PR516

0_0402_5%

+1.05VCCP

12

4

12

PC519

12

@1000P_0402_50V7K

PR524

PR524 255K_0402_1%

255K_0402_1%

1 2

PR519 0_0402_5%PR519 0_0402_5%

PR503

1 2

4.12K_0402_1%

1 2

PC526

@10P_0402_50V8J

PR504

10K_0402_1%

1 2

12

3

PC511

PR511

0.1U_0402_10V7K

0_0402_5%

BST_VCCP

1 2

1

15

PU501

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

PC527

1 2

@22P_0402_50V8J

14

TP

VBST

EN_PSV

V5DRV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

DRVH

TRIP

DRVL

13

12

LL

11

10

9

UG_VCCP

LX_VCCP

PR517

1 2

+5VALW

LG_VCCP

1 2

13.7K_0402_1%

12

PC521

4.7U_0805_10V6K

PR509

0_0402_5%

1 2

UG1_VCCP

578

3 6

5

4

241

786

123

PQ502

PQ502 AO4466_SO8

AO4466_SO8

PQ504

AO4710_SO8

2

VCCP_B+

12

PC504

2200P_0402_50V7K

12

HCB1608KF-121T30_0603

12

PC507

PC506

PC505

0.1U_0402_25V6

4.7U_0805_25V6-K

PL503

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

PR513

4.7_1206_5%

4.7U_0805_6.3V6K

PC517

PC517 680P_0603_50V8J

680P_0603_50V8J

4.7U_0805_6.3V6K

PL501

1 2

4.7U_0805_25V6-K

12

PC514

B+

+1.05VCCP

1

+

2

PC515

PC515 220U_B2_2.5VM_R25M

220U_B2_2.5VM_R25M

1

B B

+1.05VCCP

A A

5

PJP500

1 2

PAD-OPEN 4x4m

(8A,120mils ,Via NO.= 6)

+VCCP

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.05VCCP

LS-5581P

1

26 30Tuesday, July 21, 2009

2.0

A

1 1

2 2

SUSP#<21,22,26,29>

@0.1U_04 02_16V7K

B

1 2

PR603

0_0402_ 5%

PC605

12

+5VALW

2

G

+1.5V

12

10U_0805_6.3V6M

12

PR601

10K_040 2_5%

13

D

PQ601

PQ601 SSM3K70 02FU_SC70-3

SSM3K70 02FU_SC70-3

S

PC600

2

G

12

PC601

10U_0805_10V4Z

12

13

D

S

PQ600

PQ600 SSM3K70 02FU_SC70-3

SSM3K70 02FU_SC70-3

PR600

PR600 1K_0402 _1%

1K_0402 _1%

PR602

PR602 1K_0402 _1%

1K_0402 _1%

C

PU600

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1 U_SO8

6

5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC602

PC602 1U_0603 _10V6K

1U_0603 _10V6K

D

+0.75VSP

12

PC604

PC604 10U_080 5_6.3V6M

10U_080 5_6.3V6M

0.1U_0402_10V7K

PC603

3 3

PJP600

+0.75VSP

4 4

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

1 2

PAD-OPEN 3x3m

2008/09/ 15 2 009/09/1 5

(2A,80mils ,Via NO.= 4)

+0.75VS

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet

Compal Electronics, Inc.

0.75VSP

LS-5581P

D

of

27 30Tuesday, July 21, 2009

of

27 30Tuesday, July 21, 2009

of

27 30Tuesday, July 21, 2009

2.0

5

+VCCP

PR200

@

68_0402_5%

1 2

D D

H_PROCHOT#<4>

C C

H_PROCHOT#

@

0_0402_5%

VGATE<19,21>

@

0_0402_5%

PM_PWROK<8,19,21>

PM_DPRSLPVR<8,19>

VR_ON< 21>

12

PR229

12

PR209

PR215

1 2

@4.22K_0402_1%

PR217

6.81K_0402_1%

H_DPRSTP#<5,8,18>

+3VALW

PR211 147K_0402_1%PR211 147K_0402_1%

1 2

PH201

1 2

14.7K_0402_1%

1 2

12

PR207

1.91K_0402_1%

12

PC200

PC200 @0.1U_0402_16V7K

@0.1U_0402_16V7K

PR210 @40.2K_0402_1%PR210 @40.2K_0402_1%

1 2

H_PROCHOT#

@100K_0603_1%_TH11-4H104FT

1 2

PC212

0.015U_0603_25V7K

PR216

PC214

1000P_0402_50V7K

1 2

PR205

0_0402_5%

1 2

10

0_0402_5%

1 2

1

2

3

4

5

6

7

8

9

PR203

PU200

FDE

PMON

RBIAS

VR_TT#

NTC

SOFT

OCSET

VW

COMP

FB

12

41

GND PAD

4

1 2

PC208

1U_0603_6.3V6M

40

PGOOD

11

PR202

PR202 0_0402_5%

0_0402_5%

38

39

3V3

CLK_EN

VSEN12VDIFF

RTN

13

3

PC210

+5VALW

1 2

12

1U_0603_10V6K

PR204

PR204 1_0603_5%

1_0603_5%

4

3 5

758

PQ200

PQ200 NTMS4816NR2G_SO8

NTMS4816NR2G_SO8

123 6

PQ201

PQ201 NTMFS4946NT1G_SO8FL-5

NTMFS4946NT1G_SO8FL-5

241

<5>

<21>

CPU_VID5

CPU_VID6

CPU_VID3

CPU_VID4

VR_ON

12

0_0402_5%

PR208

34

35

36

37

VR_ON

DPRSTP#

DPRSLPVR

DFB

VO

DROOP

15

16

14

VID331VID432VID533VID6

VID2

VID1

VID0

VCCP

LGATE

VSSP

PHASE

UGATE

BOOT

VSS

VSUM

VDD

VIN

19

17

20

18

CPU_VID2

30

29

28

27

LGATE_CPU1

26

25

PHASE_CPU1

24

UGATE_CPU1

23

BOOT_CPU1

22

21

NC

ISL6261ACRZ-T_QFN40_6X6

<5>

CPU_VID0

CPU_VID1

12

PC209

0.01U_0402_16V7K

PC211

0.22U_0603_10V7K

1 2

0_0603_5%

PR212

1 2

2

+CPU_B+

12

4.7U_0805_25V6-K

PR213

4.7_1206_5%

12

PC206

PC205

4.7U_0805_25V6-K

12

PR214

7.68K_0805_1%

VSUM

12

PC201

0.1U_0603_50V7K

12

PC204

PC202

4.7U_0805_25V6-K

2200P_0402_50V7K

12

PC213

PC213 680P_0603_50V8J

680P_0603_50V8J

1

PL200

HCB2012KF-121T50_0805

1 2

PL201

0.45UH_ETQP4LR45XFC_25A_-25+20%

1 2

+VCC_CORE

B+

PR218 464K_0402_1%PR218 464K_0402_1%

12

PC215

1 2

PC216 47P_0402_50V8JPC216 47P_0402_50V8J

B B

VCCSENSE<5>

VSSSENSE<5>

A A

5

1 2

0_0402_5%

1 2

0_0402_5%

330P_0402_50V7K

PR223

PR225

330_0402_1%

1 2

PC222

PR221

12

0.22U_0603_10V7K

PC218

390P_0402_50V7K

1 2

PR222

2.21K_0402_1%

1 2

PC220 1000P_0603_50V7KPC220 1000P_0603_50V7K

1 2

12

PC221

PC221 1000P_0402_50V7K

1000P_0402_50V7K

PC223 330P_0402_50V7KPC223 330P_0402_50V7K

1 2

PR227

1K_0402_1%

PC226

1 2

PR228

11K_0402_1%

12

PC224 0.1U_0402_10V7KPC224 0.1U_0402_10V7K

2008-07-17

4

12

PC217

PC217 1U_0603_10V6K

1U_0603_10V6K

PR220

PR220 10_0603_5%

10_0603_5%

1 2

PC219

0.22U_0603_25V7K

12

0.1U_0402_10V7K

1 2

PC225

1 2

PR219

PR219 10_0603_5%

10_0603_5%

4.53K_0402_1%

PR226

+5VALW

+CPU_B+

VSUM

12

PR224

12

3.57K_0402_1%

PH200

PH200 10KB_0603_5%_ERTJ1VR103J

10KB_0603_5%_ERTJ1VR103J

1 2

+VCC_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2006/10/22

1 2

150P_0402_50V8J

PC215

PH3 under CPU botten side :

CPU thermal protection at 89 degree C

Recovery at 70 degree C

VL

12

PH1

100K_0603_1%_TH11-4H104FT

PH

12

PR33

PC18

PR33

11.8K_0402_1%

0.22U_0402_6.3V6K

Compal Secret Data

Deciphered Date

PR30

PR30 18K_0402_1%

18K_0402_1%

1 2

12

TM_REF1

PC19

PC64

0.01U_0402_25V7K

1000P_0402_50V7K

2

TM-2

3

2

PR34

12

100K_0402_1%

PR35

PR35 100K_0402_1%

100K_0402_1%

VL

8

P

+

-

G

4

100K_0402_1%

1

O

PU7A

PU7A LM393DG_SO8

LM393DG_SO8

12

VL

PR29

1 2

VL

PR28

PR28 100K_0402_1%

100K_0402_1%

1 2

TM-3

2

G

8

5

P

+

7

O

6

-

G

PU7B

PU7B LM393DG_SO8

LM393DG_SO8

4

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

CPU_CORE

LS-5581P

Thursday, July 23, 2009

13

D

PQ4

PQ4 2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

MAINPWON <21>

1

of

28 30

of

28 30

of

28 30

2.0

A

1 1

B

C

D

+3VALW

PC701

10U_080 5_6.3V6M

2 2

PR701

PR701 0_0402_ 5%

0_0402_ 5%

1 2

SYSON<21,22,25 >

SUSP#<21,2 2,26,27>

3 3

PR704

PR704 0_0402_ 5%

0_0402_ 5%

@

1 2

0.47U_04 02_6.3V6K

+5VALW

12

PC703

+1.8VP

12

PC702

PC702 1U_0402 _6.3V6K

1U_0402 _6.3V6K

12

PU701

6

VCNTL

5

VIN

9

VIN

8

EN

7

POK

PJP701

1 2

PAD-OPEN 4x4m

3

VOUT

4

VOUT

2

FB

GND

APL5913 -KAC-TRL_SO8

1

+1.8V

PR702

4.64K_04 02_1%

12

PR703

3.65K_04 02_1%

12

PC704

0.01U_04 02_25V7K

12

PC705

PC705 10U_080 5_6.3V6M

10U_080 5_6.3V6M

+1.8VP

4 4

Security Class ification

2008/10/ 31 2 009/10/3 1

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2008/10/ 31 2 009/10/3 1

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet

Compal Electronics, Inc.

1.8VP

LS-5581P

D

of

29 30Thursday, July 23, 2009

of

29 30Thursday, July 23, 2009

of

29 30Thursday, July 23, 2009

2.0

Version change list (P.I.R. List) Power section Page 1 of 1

5

4

3

2

1

Item Reason for change PG# Modify List

change OTP 89 degree protect

1

70 degre e recover

D D

Change 1.8vp sequence to SYSON

2

Change 1.5vp Voltage set for h w request

3

4

For slove RT8209 issue

5

modify PQ600 PQ601 PN follow C 38 bom

change PR33=11.8k PR30=18k PR2 9=100k PR28=100K

B

Del PR704

B

change PR407 to 10.5K

B

change PR405 PR518 to 100

B

PC406 PC520 to 4. 7U

C

modify 2N7002 from Rohm to tos hiba

Date

Phase

6

7

8

9

C C

10

11

12

13

14

15

16

17

B B

18

19

20

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS

DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS

DEPART MENT EXCE PT AS AUT HORIZE D BY COMPA L ELECT RONICS , INC. NEITHE R THIS SHE ET NOR T HE INFORMA TION IT C ONTAINS MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMP AL ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMP AL ELECTRONICS, INC.

5

4

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMP AL ELECTRONICS, INC.

3

Compal Secret Data

2005/03/10 2006/03/10

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

LS-5581P

GM VGA_CORE

1

of

30 30Tuesday, July 2 1, 2009

of

30 30Tuesday, July 2 1, 2009

of

30 30Tuesday, July 2 1, 2009

Compal LA-5581P, IdeaPad U450 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual