Compal LA-5541P NAT20, Inspiron 1370 Schematic

A

1 1

2 2

B

C

D

E

Compal Confidential

Schematic Document

Rev: 1.0

3 3

4 4

A

B

2009.09.10

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/04/01 2010/12/31

Compal Secret Data

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Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-5541P

E

1.0

of

143Thursday, September 10, 2009

A

B

C

D

E

Compal Confidential

Model Name : NAT20

1 1

Fan Control

page 31

Mobile Penym
LV/ULV Dual Core

uFCPGA-956 CPU - SFF

FSB

page 4,5,6,7

Thermal Sensor

EMC 1402

page 4

Clock Generator

ICS9LPRS387

page 16

800MHz/1066MHz

HDMI Conn.

page 17

HDMI
Level Shift

page 17

2 2

LAN(GbE)

RTL 8111DL

page 25

BTB Conn.

page 27

MINI Card x1

RJ45

page 25

3 3

WLAN

LCD Conn.

page 19

TMDS

LVDS

PCI-Express

SATA

port 1 port 0

DVD-ROM
Conn.

page 24

SATA HDD
Conn.

Intel Cantiga GS

FCBGA 1363 - SFF

page 8,9,10,11,12,13

DMI

Intel ICH9-M

WBMMAP-569 - SFF

page 20,21,22,23

page 24

ENE KB926

C-Link

LPC BUS

page 29

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066

3.3V 48MHz

1.5V 24.576MHz/48Mhz

USB

GMCH HDA

page 08

Audio AMP

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

HD Audio

Small Board
Conn.

page 27

HDA Codec

ALC272

HeadPhone Jack x1

page 14,15

Port0

Port1

Port2

Port3

Port4

Port5

USB conn

page 28

USB conn

page 27

USB conn

page 27

Card Reader

page 26

Camera

page 19

WLAN

page 27

Port6

Port7

WWAN

page 27

Blue Tooth

page 27

RTC Conn.

page 33

Touch Pad

page 30

SPI

Int.KBD

page 30

BIOS

page 29

Speaker 2W X 2

POWER SW
Power On/Off CKT.

page 31

4 4

DC/DC Interface CKT.

page 32

Power Circuit DC/DC

page 34~41

A

LS-5541P

USB + AUDIO/B

USB port 1, USB Port 2

LS-5542P

SIM/B Conn.

Security Classification

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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/04/01 2010/12/31

Compal Secret Data

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Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-5541P

E

1.0

of

243Thursday, September 10, 2009

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

SMBUS Control Table

100K +/- 5%Ra

Rb V min

00 V
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

SOURCE

AD_BID

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

INVERTER BATT EEPROM

V typ

AD_BID

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

SERIAL SENSOR

THERMAL
(CPU)

V

max

0 V 0 V

SODIMM

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

A

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

Symbol Note :

: means Digital Ground

: means Analog Ground

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

ICH_SMBCLK
ICH_SMBDATA ICH9

MCP_SMB_CLK

1 1

MCP_SMB_DATA

KB926

KB926

X
X

X

ICH9

MINI CARD 1 RESERVED +3VALW TO PULL HIGH

XX

X

V

XX
X

X
XX

XX

V

X

X

V

X

I2C / SMBUS ADDRESSING

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-5541P

of

343Thursday, September 10, 2009

1.0

5

4

3

2

1

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5

D D

Place close to U1.

H_A#[3..16]8

H_ADSTB#08

H_A#[17..35]8

C C

H_ADSTB#18

H_FERR#21

B B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#08
H_REQ#18
H_REQ#28
H_REQ#38
H_REQ#48

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#21
H_IGNNE#21
H_STPCLK#21

H_INTR21

H_NMI21
H_SMI#21

U1A

P2

A[3]#

V4

A[4]#

W1

A[5]#

T4

A[6]#

AA1

A[7]#

AB4

A[8]#

T2

A[9]#

AC5

A[10]#

AD2

A[11]#

AD4

A[12]#

AA5

A[13]#

AE5

A[14]#

AB2

A[15]#

AC1

A[16]#

Y4

ADSTB[0]#

R1

REQ[0]#

R5

REQ[1]#

U1

REQ[2]#

P4

REQ[3]#

W5

REQ[4]#

AN1

A[17]#

AK4

A[18]#

AG1

A[19]#

AT4

A[20]#

AK2

A[21]#

AT2

A[22]#

AH2

A[23]#

AF4

A[24]#

AJ5

A[25]#

AH4

A[26]#

AM4

A[27]#

AP4

A[28]#

AR5

A[29]#

AJ1

A[30]#

AL1

A[31]#

AM2

A[32]#

AU5

A[33]#

AP2

A[34]#

AR1

A[35]#

AN5

ADSTB[1]#

C7

A20M#

D4

ICH

FERR#

F10

IGNNE#

F8

STPCLK#

C9

LINT0

C5

LINT1

E5

SMI#

V2

RSVD01

Y2

RSVD02

AG5

RSVD03

AL5

RSVD04

J9

RSVD05

F4

RSVD06

H8

RSVD07

PENRYN SFF_UFCBGA956

SU2700@

ADS#
BNR#

BPRI#

ADDR GROUP 0

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

CONTROL

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP 1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

M4
J5
L5

N5
F38
J1

M2
B40

D8
N1
G5

K2
H4
K4
L1

H2
F2

AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7

H_RESET#

T149
T150
T151
T152
T153

XDP_BPM#5_R
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_ADS# 8
H_BNR# 8

H_BPRI# 8
H_DEFER# 8

H_DRDY# 8
H_DBSY# 8

H_BR0# 8

H_INIT# 21
H_LOCK# 8

H_TRDY# 8

H_HIT# 8
H_HITM# 8

Place Close to U1.

D38

H_THERMDA_R

BB34

H_THERMDC_R

BD34

H_THERMTRIP#

B10

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

A35
C35

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

+VCCP

R9

1 2

1 2

56_0402_5%

H_RS#0 8
H_RS#1 8
H_RS#2 8

R22 68_0402_5%

1 2

R23 0_0402_5%

1 2

R24 0_0402_5%

1 2

H_PROCHOT#

1

2

0.1U_0402_16V4Z

R14
0_0402_5%

1 2

XDP_DBRESET# 22

H_PROCHOT# 39

H_THERMTRIP# 8,21

0.1U_0402_16V4Z

@

R10
51_0402_1%

9/20

C1046

@

XDP_BPM#5

+VCCP

H_THERMDA
H_THERMDC

1

C1057

2

XDP_DBRESET#
XDP_TRST#
XDP_TCK

0.1U_0402_16V4Z

H_RESET# 8

For EMI

Add 0 ohm per EMI request.
10/17

@

For EMI

@

1

C1058

2

@

1

C1059

2

0.1U_0402_16V4Z

@

1

C1060

2

0.1U_0402_16V4Z

@

1

C1061

2

0.1U_0402_16V4Z

@

1

C1062

2

0.1U_0402_16V4Z

@

1

C1063

2

0.1U_0402_16V4Z

@

1

C1064

2

0.1U_0402_16V4Z

For EMI

+3VS

1

+3VS

0.1U_0402_16V4Z

C1035

1 2

2200P_0402_50V7K

R306

1 2

10K_0402_5%

C1034

2

H_THERMDA

H_THERMDC
THERM#

U7

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

SMCLK

SMDATA

ALERT#

Address:100_1100

GND

8
7
6
5

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5

XDP_TRST#
XDP_TCK

EC_SMB_CK2 29

R305 10K_0402_5%

1 2

EC_SMB_DA2 29

R1 54.9_0402_1%

1 2

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R6 51_0402_1%

1 2

R7 54.9_0402_1%

1 2

This shall place near CPU

+3VS

+VCCP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(1/4)-AGTL/ITP/XDP

LA-5541P

443Thursday, September 10, 2009

1

1.0

of

5

4

3

2

1

H_D#[0..15]8

D D

H_DSTBN#08
H_DSTBP#08
H_DINV#08
H_D#[16..31]8

C C

layout note: Route TEST3 & TEST5 traces on
ground referenced layer to the TPs

H_DSTBN#18
H_DSTBP#18
H_DINV#18

CPU_BSEL016
CPU_BSEL116
CPU_BSEL216

V_CPU_GTLREF

T148
T8

T9
T10

H_D#0
H_D#1

H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

TEST1
TEST2

TEST5
TEST6

CPU_BSEL CPU_BSEL2 CPU_BSEL1

B B

166

200

01

0

1

U1B

F40

D[0]#

G43

D[1]#

E43

D[2]#

J43

D[3]#

H40

D[4]#

H44

D[5]#

G39

D[6]#

E41

D[7]#

L41

D[8]#

K44

D[9]#

N41

D[10]#

T40

D[11]#

M40

D[12]#

G41

D[13]#

M44

D[14]#

L43

D[15]#

K40

DSTBN[0]#

J41

DSTBP[0]#

P40

DINV[0]#

P44

D[16]#

V40

D[17]#

V44

D[18]#

AB44

D[19]#

R41

D[20]#

W41

D[21]#

N43

D[22]#

U41

D[23]#

AA41

D[24]#

AB40

D[25]#

AD40

D[26]#

AC41

D[27]#

AA43

D[28]#

Y40

D[29]#

Y44

D[30]#

T44

D[31]#

U43

DSTBN[1]#

W43

DSTBP[1]#

R43

DINV[1]#

AW43

GTLREF

E37

TEST1

D40

TEST2

C43

TEST3

AE41

TEST4

AY10

TEST5

AC43

TEST6

A37

BSEL[0]

C37

BSEL[1]

B38

BSEL[2]

PENRYN SFF_UFCBGA956

SU2700@

CPU_BSEL0

1

0

D[32]#
D[33]#
D[34]#

DATA GROUP 0

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#

DATA GROUP 2DATA GROUP 3

D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GROUP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

SLP#

PSI#

Cause CPU core power change to
1 phase, and not need support
the pin, leave it as TP. 10/02

AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41

AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37

AE43
AD44
AE1
AF2

G7
B8
C41
E7
D10
BD10

H_PSI#

H_D#33
H_D#34H_D#2
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_D#32

AP44

H_DPRSTP# 8,21,39

H_DPSLP# 21
H_DPWR# 8
H_PWRGOOD 21

H_CPUSLP# 8

T11

H_D#[32..47] 8

H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[48..63] 8

H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8

R32

R33

R31

R30

12

12

12

12

27.4_0402_1%

54.9_0402_1%

54.9_0402_1%

27.4_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

266 0 0 0

+VCC_CORE +VCC_CORE

U1C

F32

VCC[001]

G33

VCC[002]

H32

VCC[003]

J33

VCC[004]

K32

VCC[005]

L33

VCC[006]

M32

VCC[007]

N33

VCC[008]

P32

VCC[009]

R33

VCC[010]

T32

VCC[011]

U33

VCC[012]

V32

VCC[013]

W33

VCC[014]

Y32

VCC[015]

AA33

VCC[016]

AB32

VCC[017]

AC33

VCC[018]

AD32

VCC[019]

AE33

VCC[020]

AF32

VCC[021]

AG33

VCC[022]

AH32

VCC[023]

AJ33

VCC[024]

AK32

VCC[025]

AL33

VCC[026]

AM32

VCC[027]

AN33

VCC[028]

AP32

VCC[029]

AR33

VCC[030]

AT34

VCC[031]

AT32

VCC[032]

AU33

VCC[033]

AV32

VCC[034]

AY32

VCC[035]

BB32

VCC[036]

BD32

VCC[037]

B28

VCC[038]

B30

VCC[039]

B26

VCC[040]

D28

VCC[041]

D30

VCC[042]

F30

VCC[043]

F28

VCC[044]

H30

VCC[045]

H28

VCC[046]

D26

VCC[047]

F26

VCC[048]

H26

VCC[049]

K30

VCC[050]

K28

VCC[051]

M30

VCC[052]

M28

VCC[053]

K26

VCC[054]

M26

VCC[055]

P30

VCC[056]

P28

VCC[057]

T30

VCC[058]

T28

VCC[059]

V30

VCC[060]

V28

VCC[061]

P26

VCC[062]

T26

VCC[063]

V26

VCC[064]

Y30

VCC[065]

Y28

VCC[066]

AB30

VCC[067]

PENRYN SFF_UFCBGA956

SU2700@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30

+VCCP_001

J11

+VCCP_002

E11

+VCCP_003

G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37

B34
D34

BD8
BC7
BB10
BB8
BC5
BB4
AY4

VCCSENSE

BD12

VSSSENSE

BC13

Length match within 25 mils.
The trace width/space/other is
20/7/25.

+VCCP

R27 0_0402_5%

1 2

R28 0_0402_5%

1 2

R29 0_0402_5%

1 2

1

+

2

CPU_VID0 39
CPU_VID1 39
CPU_VID2 39
CPU_VID3 39
CPU_VID4 39
CPU_VID5 39
CPU_VID6 39

VCCSENSE 39

VSSSENSE 39

C5
330U_D2E_2.5VM_R9

1

C6

2

0.01U_0402_16V7K

Near pin B34

Change to 330u_R9,
casue high
limitation. 12/14

+1.5VS

1

C7

2

10U_0805_6.3V6M

Near pin D34

+VCC_CORE

R34

+VCCP

12

R36

V_CPU_GTLREF

A A

1K_0402_1%

12

R37
2K_0402_1%

1 2

100_0402_1%
R35

1 2

100_0402_1%

Close to CPU pin
within 500mils.

VCCSENSE

VSSSENSE

Close to CPU pin AW43
within 500mils.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(2/4)-AGTL/PWR

LA-5541P

1

of

543Thursday, September 10, 2009

1.0

5

D D

AL37

AN37

AP38

B32

C33

D32

E35

E33

F34

G35

F36

H36

J35

L35

N35

K36

R35

U35

P36

V36

W35

AA35

AC35

AB36

AE35

AG35

VCCP_041

VCC_121

V22

Y24

VCCP_042

VCCP_043

VCC_122

VCC_123

Y22

AB24

VCCP_044

VCCP_045

VCC_124

VCC_125

AB22

AJ35

VCCP_046

VCC_126

AD24

AD22

C C

VCCP_021

VCCP_022

VCCP_023

VCCP_024

VCCP_025

VCCP_026

VCCP_027

VCCP_028

VCCP_029

VCCP_030

VCCP_031

VCCP_032

VCCP_033

VCCP_034

VCCP_035

VCCP_036

VCCP_037

VCCP_038

VCCP_039

VCCP_040

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112

VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

VCC_120

F24

F22

B22

B24

D22

D24

H24

BB26

BD28

BD26

H22

T24

K24

T22

K22

P24

P22

V24

M24

M22

AF36

VCCP_047

VCCP_048

VCC_127

VCC_128

AF24

AL35

AN35

VCCP_049

VCC_129

AF22

AH24

AK36

VCCP_050

VCCP_051

VCC_130

VCC_131

AH22

AP36

B12

VCCP_052

VCC_132

AK24

AK22

4

B14

VCCP_053

VCCP_054

VCC_133

VCC_134

AM24

C13

D12

VCCP_055

VCC_135

AP24

AM22

D14

VCCP_056

VCCP_057

VCC_136

VCC_137

AP22

E13

F14

VCCP_058

VCC_138

AT24

AT22

F12

VCCP_059

VCCP_060

VCC_139

VCC_140

AV24

G13

H14

VCCP_061

VCC_141

AV22

AY24

H12

VCCP_062

VCCP_063

VCC_142

VCC_143

AY22

J13

K14

VCCP_064

VCC_144

BB24

BB22

K12

VCCP_065

VCCP_066

VCC_145

VCC_146

BD24

L13

L11

VCCP_067

VCC_147

B16

BD22

M14

VCCP_068

VCCP_069

VCC_148

VCC_149

B18

N13

N11

VCCP_070

VCC_150

B20

D16

K10

VCCP_071

VCCP_072

VCC_151

VCC_152

D18

P14

P12

VCCP_073

VCC_153

F18

F16

R13

VCCP_074

VCCP_075

VCC_154

VCC_155

H18

R11

T14

VCCP_076

VCC_156

H16

D20

U13

U11

VCCP_077

VCCP_078

VCC_157

VCC_158

F20

H20

V14

V12

VCCP_079

VCCP_080

VCC_159

VCC_160

K18

K16

W13

VCCP_081

VCCP_082

VCC_161

VCC_162

M18

W11

P10

VCCP_083

VCC_163

K20

M16

V10

VCCP_084

VCCP_085

VCC_164

VCC_165

M20

Y14

AA13

VCCP_086

VCC_166

P18

P16

3

AA11

VCCP_087

VCCP_088

VCC_167

VCC_168

T18

AB14

AB12

VCCP_089

VCC_169

T16

V18

AC13

VCCP_090

VCCP_091

VCC_170

VCC_171

V16

AC11

AD14

VCCP_092

VCC_172

T20

P20

AB10

VCCP_093

VCCP_094

VCC_173

VCC_174

V20

AE13

AE11

VCCP_095

VCC_175

Y18

Y16

AF14

VCCP_096

VCCP_097

VCC_176

VCC_177

AB18

AF12

AG13

VCCP_098

VCC_178

AB16

AD18

AG11

VCCP_099

VCCP_100

VCC_179

VCC_180

AD16

AH14

AJ13

VCCP_101

VCC_181

Y20

AB20

AJ11

VCCP_102

VCCP_103

VCC_182

VCC_183

AD20

AF10

AK14

VCCP_104

VCC_184

AF18

AF16

AK12

VCCP_105

VCCP_106

VCC_185

VCC_186

AH18

AL13

AL11

VCCP_107

VCC_187

AF20

AH16

AN13

VCCP_108

VCCP_109

VCC_188

VCC_189

AH20

AN11

AP12

VCCP_110

VCC_190

AK18

AK16

AR13

VCCP_111

VCCP_112

VCC_191

VCC_192

AM18

AR11

AK10

VCCP_113

VCC_193

AP18

AM16

AP10

VCCP_114

VCCP_115

VCC_194

VCC_195

AP16

AU13

AU11

VCCP_116

VCC_196

AK20

AM20

VCCP_117

VCC_197

2

VCCP_118L9VCCP_119L7VCCP_120N9VCCP_121N7VCCP_122R9VCCP_123R7VCCP_124U9VCCP_125U7VCCP_126W9VCCP_127W7VCCP_128

VCC_198

VCC_199

VCC_200

VCC_201

VCC_202

VCC_203

VCC_204

VCC_205

VCC_206

VCC_207

AT18

AT16

AP20

AT20

AV18

AV16

AY18

AY16

AV20

AY20

AA9

AA7

VCC_208

BB18

BB16

AC9

VCCP_129

VCCP_130

VCC_209

VCC_210

BD18

AC7

AE9

VCCP_131

VCC_211

BB20

BD16

AE7

AG9

VCCP_132

VCCP_133

VCC_212

VCC_213

BD20

AM14

AG7

VCCP_134

VCCP_135

VCC_214

VCC_215

AP14

AJ9

AJ7

VCCP_136

VCC_216

AT14

AV14

AL9

VCCP_137

VCCP_138

VCC_217

VCC_218

AY14

AL7

AN9

VCCP_139

VCC_219

BB14

BD14

AN7

VCCP_140

VCCP_141

VCC_220

+VCCP

AR9

AR7

A33

A13

VCCP_142

VCCP_143

VCCP_144

VCCP_145

VCCP_020

VCCP_018

VCCP_019

VCCP_017

AJ37

AF38

AK38

AG37

U1F
PENRYN SFF_UFCBGA956

SU2700@

1

+VCC_CORE +VCCP

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(3/4)-PWR

LA-5541P

1

1.0

of

643Thursday, September 10, 2009

5

U1D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

D D

C C

B B

A A

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

PENRYN SFF_UFCBGA956

SU2700@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

5

AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21

U1E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

PENRYN SFF_UFCBGA956

SU2700@

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4

4

+VCC_CORE

10U_0603_6.3V6M

1

C8

2

@

+VCC_CORE

Mid Frequence Decoupling

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C10

C9

2

2

3

10U_0603_6.3V6M

1

C12

C11

2

@

10U_0603_6.3V6M

1

1

C13

C14

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C15

2

10U_0603_6.3V6M

1

1

C16

C17

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C18

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C19

2

C21

C20

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C22

2

C23

2

10U_0603_6.3V6M

1

1

C24

2

C25

2

@

10U_0603_6.3V6M

1

1

2

1

C26

C27

2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C29

C28

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

1

1

C31

C30

2

2

High Frequence Decoupling

1U_0402_6.3V6K

1U_0402_6.3V6K

C32

1U_0402_6.3V6K

1

1

C33

C34

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C35

2

1U_0402_6.3V6K

1

1

C36

C37

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

C39

C38

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C41

C40

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C43

C42

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C45

C44

2

2

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C46

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

1

C47

C48

2

C49

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C51

C50

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C53

C52

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1

1

C55

C54

2

2

ESR <= 1.5m ohm

+VCC_CORE

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C1364

2

4

1

C1365

2

1

C1366

2

+VCCP

1U_0402_6.3V6K

1

C59

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Near CPU CORE regulator

+VCC_CORE

220U_D2_2VK_R9

1

+

C56

2

Del C37 to improve power plan. 6/14

1U_0402_6.3V6K

1U_0402_6.3V6K

C60

1U_0402_6.3V6K

1

1

2

1

C61

C62

2

2

Compal Secret Data

Deciphered Date

220U_D2_2VK_R9

1

+

C57

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C63

2

1

1

C65

C64

2

2

220U_D2_2VK_R9

1

+

C58

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C67

C66

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C68

2

1U_0402_6.3V6K

1

1

2

1

C69

C70

2

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Penryn(4/4)-GND/Bypass

LA-5541P

1

1.0

of

743Thursday, September 10, 2009

5

H_D#[0..63]5

D D

C C

H_RESET#4

H_CPUSLP#5

layout note:

B B

Route H_SCOMP and H_SCOMP# with trace width,
spacing and impedance (55 ohm) same as FSB data
traces

trace width and spacing is 10/20

+VCCP

12

1K_0402_1%

12

R592K_0402_1%

A A

Trace < = 500mils

Layout Note:
H_RCOMP / H_VREF / H_SWNG

R55

H_VREF

1

C78

2

0.1U_0402_16V4Z

@

within 100 mils from NB

H_SWNG
H_RCOMP

H_VREF

12

R60

24.9_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_RCOMP

U3A

J7

H_D#_0

H6

H_D#_1

L11

H_D#_2

J3

H_D#_3

H4

H_D#_4

G3

H_D#_5

K10

H_D#_6

K12

H_D#_7

L1

H_D#_8

M10

H_D#_9

M6

H_D#_10

N11

H_D#_11

L7

H_D#_12

K6

H_D#_13

M4

H_D#_14

K4

H_D#_15

P6

H_D#_16

W9

H_D#_17

V6

H_D#_18

V2

H_D#_19

P10

H_D#_20

W7

H_D#_21

N9

H_D#_22

P4

H_D#_23

U9

H_D#_24

V4

H_D#_25

U1

H_D#_26

W3

H_D#_27

V10

H_D#_28

U7

H_D#_29

W11

H_D#_30

U11

H_D#_31

AC11

H_D#_32

AC9

H_D#_33

Y4

H_D#_34

Y10

H_D#_35

AB6

H_D#_36

AA9

H_D#_37

AB10

H_D#_38

AA1

H_D#_39

AC3

H_D#_40

AC7

H_D#_41

AD12

H_D#_42

AB4

H_D#_43

Y6

H_D#_44

AD10

H_D#_45

AA11

H_D#_46

AB2

H_D#_47

AD4

H_D#_48

AE7

H_D#_49

AD2

H_D#_50

AD6

H_D#_51

AE3

H_D#_52

AG9

H_D#_53

AG7

H_D#_54

AE11

H_D#_55

AK6

H_D#_56

AF6

H_D#_57

AJ9

H_D#_58

AH6

H_D#_59

AF12

H_D#_60

AH4

H_D#_61

AJ7

H_D#_62

AE9

H_D#_63

B6

H_SWING

D4

H_RCOMP

J11

H_CPURST#

G9

H_CPUSLP#

L17

H_AVREF

K18

H_DVREF

CANTIGA GMCH SFF_FCBGA1363

+VCCP

12

R56

221_0603_1%

12

R61

100_0402_1%

0.1U_0402_16V4Z

Near B6 pin

H_SWNG

1

C79

2

H_ADSTB#_0
H_ADSTB#_1

HOST

HPLL_CLK#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

layout note:
Place them close to U3 pin BC51.

4

H_A#3

L15

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK
H_DPWR#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

PM_EXTTS#0
PM_EXTTS#1

H_A#4

B14

H_A#5

C15

H_A#6

D12

H_A#7

F14

H_A#8

G17

H_A#9

B12

H_A#10

J15

H_A#11

D16

H_A#12

C17

H_A#13

D14

H_A#14

K16

H_A#15

F16

H_A#16

B16

H_A#17

C21

H_A#18

D18

H_A#19

J19

H_A#20

J21

H_A#21

B18

H_A#22

D22

H_A#23

G19

H_A#24

J17

H_A#25

L21

H_A#26

L19

H_A#27

G21

H_A#28

D20

H_A#29

K22

H_A#30

F18

H_A#31

K20

H_A#32

F20

H_A#33

F22

H_A#34

B20

H_A#35

A19
F10

A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8

L9
N7
AA7
AG3

K2
N3
AA3
AF4

L3
M2
Y2
AF2

J13
L13
C13
G13
G15

F4
F2
G7

R62 10K_0402_5%
R63 10K_0402_5%

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

+V_DDR_MCH_REF

1

2

0.1U_0402_16V7K

1 2
1 2

H_A#[3..35] 4

Add them for Boundary Scan. 10/23

R39
R38
R40 4.7K_0402_5%@

SMRCOMP_VOH

SMRCOMP_VOL

R51 0_0402_5%

12

R1498
1K_0402_1%

12

R1499
1K_0402_1%

R41 1K_0402_5% @

PM_BMBUSY#22

1 2

H_THERMTRIP#4,21

PM_DPRSLPVR22,39

+V_DDR_MCH_REF

C1347

+3VS

+3VS

+1.5V

3

1 2
1 2
1 2
1 2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

H_DPRSTP#5,21,39
PM_EXTTS#014
PM_EXTTS#115
PM_PWROK22,29,39
PLT_RST#20,25,27,29

1K_0402_5% @

4.7K_0402_5%@

+1.5V

1

1

12

C72

C71

0.01U_0402_25V7K

2

2

12

12

1

1

C73

C74

2

2

0.01U_0402_25V7K

MCH_CLKSEL016
MCH_CLKSEL116
MCH_CLKSEL216

R49 0_0402_5%
R50 100_0402_1%

Add R428 in 9/26

H_DPRSTP#

For ESD

R42
1K_0402_1%

R45

3.01K_0402_1%

R48
1K_0402_1%

T30

T31

CFG510
CFG610
CFG710

T32

CFG910

CFG1010

T33

CFG1210
CFG1310

T34

T35

CFG1610

T36

T37

CFG1910
CFG2010

PM_EXTTS#0
PM_EXTTS#1

1 2
1 2

1

C10560.1U_0402_16V4Z@

2

U3B

J43

T12
T13
T14
T15
T16
T17
T18
T19
T20

TCK
TDI
TDO
TMS

T21
T22

T23

T24

T25
T26
T27
T28

C750.1U_0402_16V4Z@

1

2

RSVD1

L43

RSVD2

J41

RSVD3

L41

RSVD4

AN11

RSVD5

AM10

RSVD6

AK10

RSVD7

AL11

RSVD8

F12

RSVD9

AN45

RSVD10

AP44

RSVD11

AT44

RSVD12

AN47

RSVD13

C27

RSVD14

D30

RSVD15

J9

RSVD17

AW42

RSVD20

BB20

RSVD22

BE19

RSVD23

BF20

RSVD24

BF18

RSVD25

K26

CFG_0

G23

CFG_1

G25

CFG_2

J25

CFG_3

L25

CFG_4

L27

CFG_5

F24

CFG_6

D24

CFG_7

D26

CFG_8

J23

CFG_9

B26

CFG_10

A23

CFG_11

C23

CFG_12

B24

CFG_13

B22

CFG_14

K24

CFG_15

C25

CFG_16

L23

CFG_17

L33

CFG_18

K32

CFG_19

K34

CFG_20

J35

PM_SYNC#

F6

PM_DPRSTP#

J39

PM_EXT_TS#_0

L39

PM_EXT_TS#_1

AY39

PWROK

BB18

RSTIN#

K28

THERMTRIP#

K36

DPRSLPVR

A7

NC_1

A49

NC_2

A52

NC_3

A54

NC_4

B54

NC_5

D55

NC_6

G55

NC_7

BE55

NC_8

BH55

NC_9

BK55

NC_10

BK54

NC_11

BL54

NC_12

BL52

NC_13

BL49

NC_14

BL7

NC_15

BL4

NC_16

BL2

NC_17

BK2

NC_18

BK1

NC_19

BH1

NC_20

BE1

NC_21

G1

NC_22

CANTIGA GMCH SFF_FCBGA1363

2

BB32

SA_CK_0

BA25

SA_CK_1

BA33

SB_CK_0

BA23

SB_CK_1

BA31

SA_CK#_0

BC25

SA_CK#_1

BC33

SB_CK#_0

BB24

SB_CK#_1

BC35

SA_CKE_0

BE33

SA_CKE_1

BE37

SB_CKE_0

BC37

SB_CKE_1

BK18

SA_CS#_0

BK16

SA_CS#_1

BE23

SB_CS#_0

BC19

SB_CS#_1

BJ17

SA_ODT_0

BJ19

SA_ODT_1

BC17

SB_ODT_0

BE17

SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#
DPLL_REF_CLK

DPLL_REF_CLK#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2

DMI

DMI_TXN_3
DMI_TXP_0

DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CFGRSVD

PM

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

ME

NC

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

MISC

TSATN#

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

HDA_BITCLK_NB

R152

1 2

BL25
BK26

BK32
BL31

BC51
AY37
BH20
BA37

B42
D42
B50
D50

R49
P50

AG55
AL49
AH54
AL47

AG53
AK50
AH52
AL45

AG49
AJ49
AJ47
AG47

AF50
AH50
AJ45
AG45

G33
G37
F38
F36
G35

G39

AK52
AK54
AW40
AL53
AL55

F34
F32
B38
A37
C31
K42

D10

C29
B30
D28
A27
B28

For EMI

@

SMRCOMP
SMRCOMP#

SMRCOMP_VOH
SMRCOMP_VOL

+V_DDR_MCH_REF
SM_PWROK_R
SM_REXT
SM_DRAMRST#

CL_VREF

TSATN#

R58 54.9_0402_1%

HDA_BITCLK_NB
HDA_SDIN2_NB

C237

33_0402_1%

R43 80.6_0402_1%
R44 80.6_0402_1%

R1515 0_0402_5%
R46 10K_0402_1%@

R47 499_0402_1%

CLK_MCH_DREFCLK 16
CLK_MCH_DREFCLK# 16
MCH_SSCDREFCLK 16
MCH_SSCDREFCLK# 16

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_TXN0 22
DMI_TXN1 22
DMI_TXN2 22
DMI_TXN3 22

DMI_TXP0 22
DMI_TXP1 22
DMI_TXP2 22
DMI_TXP3 22

DMI_RXN0 22
DMI_RXN1 22
DMI_RXN2 22
DMI_RXN3 22

DMI_RXP0 22
DMI_RXP1 22
DMI_RXP2 22
DMI_RXP3 22

T38
T39

1 2

@

1 2

1

M_CLK_DDR0 14
M_CLK_DDR1 14
M_CLK_DDR2 15
M_CLK_DDR3 15

M_CLK_DDR#0 14
M_CLK_DDR#1 14
M_CLK_DDR#2 15
M_CLK_DDR#3 15

DDR_CKE0_DIMMA 14
DDR_CKE1_DIMMA 14
DDR_CKE2_DIMMB 15
DDR_CKE3_DIMMB 15

DDR_CS0_DIMMA# 14
DDR_CS1_DIMMA# 14
DDR_CS2_DIMMB# 15
DDR_CS3_DIMMB# 15

M_ODT0 14
M_ODT1 14
M_ODT2 15
M_ODT3 15

1 2
1 2

1 2
1 2

1 2

SM_DRAMRST# 14,15

CL_CLK0 22
CL_DATA0 22
M_PWROK 22
CL_RST# 22

C76

0.1U_0402_16V4Z

HDMICLK 17

HDMIDAT 17

CLKREQ#_B 16

MCH_ICH_SYNC# 22

R313

1 2

33_0402_5%

33P_0402_50V8J

+1.5V

SM_PWROK 38

Modify in 9/26

+VCCP

12

R52
1K_0402_1%

12

1

R53
511_0402_1%

2

+VCCP

HDA_BITCLK_NB 21
HDA_RST#_NB 21

HDA_SDIN2 21
HDA_SDOUT_NB 21
HDA_SYNC_NB 21

Del R48. 9/27

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DDR/DMI

LA-5541P

843Thursday, September 10, 2009

1

1.0

of

5

D D

DDR_A_D[0..63]14

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3D

AP46

SA_DQ_0

AU47

SA_DQ_1

AT46

SA_DQ_2

AU49

SA_DQ_3

AR45

SA_DQ_4

AN49

SA_DQ_5

AV50

SA_DQ_6

AP50

SA_DQ_7

AW47

SA_DQ_8

BD50

SA_DQ_9

AW49

SA_DQ_10

BA49

SA_DQ_11

BC49

SA_DQ_12

AV46

SA_DQ_13

BA47

SA_DQ_14

AY50

SA_DQ_15

BF46

SA_DQ_16

BC47

SA_DQ_17

BF50

SA_DQ_18

BF48

SA_DQ_19

BC43

SA_DQ_20

BE49

SA_DQ_21

BA43

SA_DQ_22

BE47

SA_DQ_23

BF42

SA_DQ_24

BC39

SA_DQ_25

BF44

SA_DQ_26

BF40

SA_DQ_27

BB40

SA_DQ_28

BE43

SA_DQ_29

BF38

SA_DQ_30

BE41

SA_DQ_31

BA15

SA_DQ_32

BE11

SA_DQ_33

BE15

SA_DQ_34

BF14

SA_DQ_35

BB14

SA_DQ_36

BC15

SA_DQ_37

BE13

SA_DQ_38

BF16

SA_DQ_39

BF10

SA_DQ_40

BC11

SA_DQ_41

BF8

SA_DQ_42

BG7

SA_DQ_43

BC7

SA_DQ_44

BC9

SA_DQ_45

BD6

SA_DQ_46

BF12

SA_DQ_47

AV6

SA_DQ_48

BB6

SA_DQ_49

AW7

SA_DQ_50

AY6

SA_DQ_51

AT10

SA_DQ_52

AW11

SA_DQ_53

AU11

SA_DQ_54

AW9

SA_DQ_55

AR11

SA_DQ_56

AT6

SA_DQ_57

AP6

SA_DQ_58

AL7

SA_DQ_59

AR7

SA_DQ_60

AT12

SA_DQ_61

AM6

SA_DQ_62

AU7

SA_DQ_63

CANTIGA GMCH SFF_FCBGA1363

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

BC21
BJ21
BJ41

BH22
BK20
BL15

AT50
BB50
BB46
BE39
BB12
BE7
AV10
AR9

AR47
BA45
BE45
BC41
BC13
BB10
BA7
AN7
AR49
AW45
BC45
BA41
BA13
BA11
BA9
AN9

BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 14
DDR_A_BS1 14
DDR_A_BS2 14

DDR_A_RAS# 14
DDR_A_CAS# 14
DDR_A_WE# 14

DDR_A_DM[0..7] 14

DDR_A_DQS[0..7] 14

DDR_A_DQS#[0..7] 14

DDR_A_MA[0..14] 14

3

DDR_B_D[0..63]15

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U3E

AP54

AM52

AR55
AV54

AM54

AN53
AT52
AU53

AW53

AY52
BB52
BC53
AV52

AW55

BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46

BJ47
BL45
BJ45

BL41
BH44
BH46
BK44
BK40

BJ39
BK10
BH10

BK6
BH6

BJ9

BL11

BG5

BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4

AL3

AJ1
AK4
AM4
AH2
AK2

CANTIGA GMCH SFF_FCBGA1363

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

BJ13

SB_BS_0

BK12

SB_BS_1

BK38

SB_BS_2

BE21

SB_RAS#

BH14

SB_CAS#

BK14

SB_WE#

DDR_B_DM0

AP52

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3

AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3

BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6

DDR_B_MA7
DDR_B_MA8

DDR_B_MA9

DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS0 15
DDR_B_BS1 15
DDR_B_BS2 15

DDR_B_RAS# 15
DDR_B_CAS# 15
DDR_B_WE# 15

DDR_B_DM[0..7] 15

DDR_B_DQS[0..7] 15

DDR_B_DQS#[0..7] 15

DDR_B_MA[0..14] 15

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(2/6)-DDR3 Channel A/B

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

943Thursday, September 10, 2009

1

1.0

of

5

BKLT19,29
ENBKL29

+3VS

DDC2_CLK19
DDC2_DATA19

D D

ENAVDD19,29

TXCLK_L-19
TXCLK_L+19

TXOUT_L0-19
TXOUT_L1-19
TXOUT_L2-19

TXOUT_L0+19
TXOUT_L1+19
TXOUT_L2+19

For make layout clearance, del
TP for channel B. 10/18

R65 10K_0402_5%

1 2

R66 10K_0402_5%

1 2

1 2

R67 2.4K_0402_1%~D

For EMI. 9/26

R68 75_0402_5%

1 2

R69 75_0402_5%

C C

1 2

R70 75_0402_5%

1 2

Del TV_LUMA & CRMA in 10/12.

GMCH_CRT_B18
GMCH_CRT_G18
GMCH_CRT_R18

GMCH_CRT_CLK18

GMCH_CRT_DATA18

GMCH_CRT_HSYNC18

GMCH_CRT_VSYNC18

B B

R71 30.1_0402_1%

1 2

R73 30.1_0402_1%

1 2

Close to pin D32 and keep
30mil space to other
part/trace.

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R

4

T42

10/18

10/19

10/19

Tie to GND. 9/28

GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R

CRT_HSYNC_R
CRT_VSYNC_R

R76

1.02K_0402_1%

U3C

D38

L_BKLT_CTRL

C37

L_BKLT_EN

K38

L_CTRL_CLK

L37

L_CTRL_DATA

J37

L_DDC_CLK

L35

L_DDC_DATA

B36

L_VDD_EN

F50

LVDS_IBG

H46

LVDS_VBG

P44

LVDS_VREFH

K46

LVDS_VREFL

D46

LVDSA_CLK#

B46

LVDSA_CLK

D44

LVDSB_CLK#

B44

LVDSB_CLK

G45

LVDSA_DATA#_0

F46

LVDSA_DATA#_1

G41

LVDSA_DATA#_2

C45

LVDSA_DATA#_3

F44

LVDSA_DATA_0

G47

LVDSA_DATA_1

F40

LVDSA_DATA_2

A45

LVDSA_DATA_3

B40

LVDSB_DATA#_0

A41

LVDSB_DATA#_1

F42

LVDSB_DATA#_2

D48

LVDSB_DATA#_3

D40

LVDSB_DATA_0

C41

10/18

LVDSB_DATA_1

G43

LVDSB_DATA_2

B48

LVDSB_DATA_3

J27

TVA_DAC

E27

TVB_DAC

G27

TVC_DAC

F26

TVA_RTN

B34

TV_DCONSEL_0

D34

TV_DCONSEL_1

J29

CRT_BLUE

G29

CRT_GREEN

F30

CRT_RED

E29

CRT_IRTN

D36

CRT_DDC_CLK

C35

CRT_DDC_DATA

J33

CRT_HSYNC

D32

CRT_TVO_IREF

G31

CRT_VSYNC

CANTIGA GMCH SFF_FCBGA1363

1 2

Del R82, R83. 10/18

3

PEGCOMP trace width
and spacing is 20/25 mils.

PEGCOMP

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9

PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

U45
T44

D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54

E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52

L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54

J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52

HDMI_C_TX2­HDMI_C_TX1­HDMI_C_TX0­HDMI_C_CLK-

HDMI_C_TX2+
HDMI_C_TX1+
HDMI_C_TX0+
HDMI_C_CLK+

PEG_COMPI

PEG_COMPO

LVDS

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

TV

PEG_TX#_10

PCI-EXPRESS GRAPHICS

PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

VGA

Remove R84 ~ R86 since
already have 75ohm of
page17. 10/27

1 2

R64 49.9_0402_1%

layout note:
Place R64 <500mils to U3 pin U45&T44.

TMDS_B_HPD#

C1036 0.1U_0402_16V4Z
C1037 0.1U_0402_16V4Z
C1038 0.1U_0402_16V4Z
C1039 0.1U_0402_16V4Z

C1040 0.1U_0402_16V4Z
C1041 0.1U_0402_16V4Z
C1042 0.1U_0402_16V4Z
C1043 0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+VCC_PEG

TMDS_B_HPD# 17

HDMI_UMA_TX2- 17
HDMI_UMA_TX1- 17
HDMI_UMA_TX0- 17
HDMI_UMA_CLK- 17

HDMI_UMA_TX2+ 17
HDMI_UMA_TX1+ 17
HDMI_UMA_TX0+ 17
HDMI_UMA_CLK+ 17

2

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management
Engine Crypto strap)

CFG8

CFG9
(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

Strap Pin Table

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order

0 = Enable
1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

ReservedCFG[18:17]

0 = Normal Operation

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

CFG58
CFG68
CFG78

CFG98
CFG108
CFG128
CFG138
CFG168

CFG198
CFG208

*

*

*

(Lane number in Order)

R72 2.21K_0402_1% @

1 2

R74 2.21K_0402_1% @

1 2

R75 2.21K_0402_1% @

1 2

R77 2.21K_0402_1% @

1 2

R78 2.21K_0402_1% @

1 2

R79 2.21K_0402_1%@

1 2

R80 2.21K_0402_1% @

1 2

R81 2.21K_0402_1% @

1 2

R82 4.02K_0402_1%@

1 2

R83 4.02K_0402_1% @

1 2

1

*

*

*

(Default)11 = Normal Operation

*

*

*

+3VS

12

R15

150_0402_1%

150_0402_1%

R16

12

150_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(3/6)-LVDS/TV/CRT

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

10 43Thursday, September 10, 2009

1

1.0

of

12

R13

A A

5

5

+3VS

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

D D

C89

2

install 0.1U & 10U for wavy issue. 7/29

change 0.1U to 22U for wavy issue. 5/20

+1.5VS

C C

B B

+1.05VM_HPLL

+3VS_DAC_CRT

R86

12

10U_0603_6.3V6M

0.1U_0402_16V4Z

1

1

C90

C91

2

2

R94 0_0603_5%

1 2

9/27

+VCCP

+1.05VM_PEGPLL

1

9/27

C125

2

0.1U_0402_16V4Z

0.01U_0402_16V7K

+3VS

1

C92

2

0.1U_0402_16V4Z

R97 0_0805_5%

1

+

2

C110

R100 0_0603_5%

R87

BLM18PG181SN1D_0603

+1.5VS_PEG_BG

1

C105

2

1 2

150U_D2_6.3VM

1 2

1

R102 0_0603_5%

C126

+1.8V

2

0.1U_0402_16V4Z

+3VS_DAC_BG

12

22U_0805_6.3V

1

C93

2

+1.8V_TXLVDS

1

C102
1000P_0402_50V7K

2

9/27

10U_0805_6.3V6M

0.01U_0402_16V7K

1

9/27

C94

+1.05VM_DPLLA

2

+1.05VM_DPLLB

+1.05VM_HPLL
+1.05VM_MPLL

10mA

+1.05VM_PEGPLL

+1.05VM_A_SM

1U_0603_10V4Z

4.7U_0805_10V4Z

1

1

2

2

C111

C112

+1.05VM_A_SM_CK

10U_0805_6.3V6M

0.1U_0402_16V4Z

1

C119

C120

2

12

1

2

C113

1

2

1U_0603_10V4Z

1

C127

2

30mA

+1.8V_LVDS

4

U3H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGA GMCH SFF_FCBGA1363

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VCCA_TV_DAC

TVD TV/CRT

VCC_HDA

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

3

Change to 330u_R9,
casue high
limitation. 12/14

R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1

K30

+VCC_HDA

A31

N34

+1.5VS_QDAC

N32

+1.5VS_TVDAC

+VCC_HDA

9/27

M25
N24
M23

BK24
BL23
BJ23
BK22

T41
C33

A33

AB44
Y44
AC43
AA43

AM44
AN43
AL43

K14
Y12
P2

80mA

+VTTLF1
+VTTLF2
+VTTLF3

+V1.05VM_AXF

+1.5V_MEM_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VM_DMI

0.47U_0603_10V7K

1

C128

2

0.47U_0603_10V7K

2.2U_0805_16V4Z

1

1

2

2

C85

C86

R92 0_0402_5%@

1 2

R321 0_0603_5%

0.1U_0402_16V4Z

1

C1045

2

9/29

0.47U_0603_10V7K

0.47U_0603_10V7K

1

C129

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

1

C87

2

2

C88

+3VS_TVDAC

0.01U_0402_16V7K

C100

Disable HDMI audio

1 2

+3VS_HV

0.1U_0402_16V4Z

1

2

C121

1

C130

2

+VCCP

1

+

2

C84

@

330U_D2E_2.5VM_R9

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

1

C101

2

2

R91

1 2

+1.5VS

Enable HDMI audio

+VCCP

+3VS

2

+1.05VM_DPLLA +VCCP

9/27

1

1

@

+

C80

C81

2

2

0.1U_0402_16V4Z

+1.05VM_DPLLB

9/27

1

1

@

+3VS

+1.05VM_HPLL

9/27

+1.05VM_PEGPLL

2 1

D1 CH751H-40_SC76

+

C95

C96

2

2

0.1U_0402_16V4Z

1

1

2

2

C103

C104

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+1.05VM_MPLL

1

1

C106

C107

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

+1.8V_TXLVDS +1.8V

1

1

2

2

C114

1000P_0402_50V7K

0.1U_0402_16V4Z

10U_0805_10V4Z~D

1

1

C122

C123

2

2

+VCCP_D

R103 10_0402_5%

+1.5VS_QDAC

0.1U_0402_16V4Z

0.01U_0402_16V7K

1

1

C132

C131

2

2

R84

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

R88

1 2

BLM18PG181SN1D_0603

220U_D2_4VM_R15

R93

1 2

BLM18PG181SN1D_0603

R95

1 2

BLM18PG181SN1D_0603

R98 0_0603_5%

1 2

C115

10U_0805_6.3V6M @

L1

1 2

BLM18PG121SN1D_0603

1 2

BLM18PG181SN1D_0603

4.7U_0603_6.3V

1

C133

2

9/27

9/27

+VCCP

9/27

+VCCP

9/27

+VCCP

R105

1 2

+V1.05VM_AXF

9/27

+VCCP

R90

0_0603_5%

10U_0805_6.3V6M

C99

+1.5VS_TVDAC

0.01U_0402_16V7K

C108

+VCC_PEG

10U_0805_6.3V6M

4.7U_0805_10V4Z

1

C118

C117

2

+1.05VM_DMI

9/29

R101 0_0603_5%

0.1U_0402_16V4Z

1

C124

2

R104 0_0402_5%

1 2

+1.5VS

1

R85 0_0603_5%

1U_0603_10V4Z

10U_0805_10V4Z~D

1

1

C83

C82

2

2

+1.5V_MEM_SM_CK

R89 0_0805_5%

0.1U_0402_16V4Z

10U_0805_6.3V6M

1

1

C97

C98

1 2

2

2

1

2

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

1

C109

2

2

R99 0_0805_5%

1 2

220U_D2_4VM_R15

1

1

+

C116

2

2

1 2

1 2

1 2

R96

+3VS_HV

9/21

9/27

+VCCP

+VCCP

+1.5V

+1.5VS

9/21

+VCCP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

install 4.7U for wavy issue. 7/29

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LA-5541P

1

1.0

of

11 43Thursday, September 10, 2009

5

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

9/21

C144

+VCCP

0.1U_0402_16V4Z

C145

1

2

D D

220U_D2_4VM_R15

C141

C C

B B

A A

0.22U_0402_10V4Z

10U_0805_6.3V6M

1

+

2

0.22U_0402_10V4Z

C143

C142

1

1

2

1

2

2

U3F

AT41

VCC_1

AR41

VCC_2

AN41

VCC_3

AJ41

VCC_4

AH41

VCC_5

AD41

VCC_6

AC41

VCC_7

Y41

VCC_8

W41

VCC_9

AT40

VCC_10

AM40

VCC_11

AL40

VCC_12

AJ40

VCC_13

AH40

VCC_14

AG40

VCC_15

AE40

VCC_16

AD40

VCC_17

AC40

VCC_18

AA40

VCC_19

Y40

VCC_20

AN35

VCC_21

AM35

VCC_22

AJ35

VCC_23

AH35

VCC_24

AD35

VCC_25

AC35

VCC_26

W35

VCC_27

AM34

VCC_28

AL34

VCC_29

AJ34

VCC_30

AH34

VCC_31

AG34

VCC_32

AE34

VCC_33

AD34

VCC_34

AC34

VCC_35

AA34

VCC_36

Y34

VCC_37

W34

VCC_38

AM32

VCC_39

AL32

VCC_40

AJ32

VCC_41

AH32

VCC_42

AE32

VCC_43

AD32

VCC_44

AA32

VCC_45

AM31

VCC_46

AL31

VCC_47

AJ31

VCC_48

AH31

VCC_49

AM29

VCC_50

AL29

VCC_51

AM28

VCC_52

AL28

VCC_53

AJ28

VCC_54

AM27

VCC_55

AL27

VCC_56

AM25

VCC_57

AL25

VCC_58

AJ25

VCC_59

AM24

VCC_60

N36

VCC_61

CANTIGA GMCH SFF_FCBGA1363

4

VCC CORE

POWER

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8

VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31

VCC NCTF

VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38

AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34

9/21

+VCCP

+1.5V

330U_D2E_2.5VM_R9

C146

3

+VCCP

3000mA

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61

VCC_AXG_SENSE
VSS_AXG_SENSE

2

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23

POWER

VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31

VCC SMVCC GFX

VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39

VCC GFX NCTF

VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44

VCC GFX

VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18

AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15

AU45
BF52
BB38
BA19
BE9
AU9
AL9

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

U3G

BB36
BE35

AW34

330U_D2E_2.5VM_R9

10U_0805_6.3V6M

1

C137

+

2

1

1

C147

2

10U_0805_6.3V

1

C148

2

+

2

10U_0805_6.3V6M

C138

1

2

1

C149

2

10U_0805_6.3V

0.01U_0402_16V7K

C139

1

2

1

C150

2

1U_0603_10V4Z

6326.84mA

T43PAD
T44PAD

AW32

BK30
BH30
BF30

C140

2

BD30
BB30

AW30

1

BL29

BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28

BL27

BJ27
BG27
BE27
BC27
BA27
AY27

AW26

BF24

BL19
BB16

W32
AG31
AE31
AD31
AC31
AA31

Y31

W31
AH29

0.1U_0402_16V4Z

AG29
AE29
AD29
AC29
AA29

Y29

W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27

Y27

W27
AH25
AD25
AC25

W25

AJ24
AH24
AG24
AE24
AD24
AC24
AA24

Y24

W24

AM22

AL22

AJ22
AH22
AG22
AE22
AD22
AC22
AA22

AM21

AL21

AJ21
AH21
AD21
AC21
AA21

Y21

W21

AM16

AL16

AG13
AE13

1

1

2

C134

0.1U_0402_16V4Z

C156 0.1U_0402_16V4Z

1

2

1

1

2

2

C136

C135

4.7U_0805_10V4Z

0.22U_0402_10V4Z

C152 0.22U_0603_10V7K

C151 0.22U_0603_10V7K

1

1

C157 0.1U_0402_16V4Z

1

2

1

2

2

2

C155 1U_0603_10V4Z

C154 1U_0603_10V4Z

C153 0.47U_0402_6.3V6K

1

1

2

2

CANTIGA GMCH SFF_FCBGA1363

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(5/6)-PWR/GND

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

12 43Thursday, September 10, 2009

1

1.0

of

5

U3I

BA55

VSS_1

AU55

VSS_2

AN55

VSS_3

AJ55

VSS_4

AE55

VSS_5

AA55

VSS_6

U55

VSS_7

N55

VSS_8

BD54

VSS_9

BG53

VSS_10

AJ53

VSS_11

AE53

D D

C C

B B

A A

VSS_12

AA53

VSS_13

U53

VSS_14

N53

VSS_15

J53

VSS_16

G53

VSS_17

E53

VSS_18

K52

VSS_19

BG51

VSS_20

BA51

VSS_21

AW51

VSS_22

AU51

VSS_23

AR51

VSS_24

AN51

VSS_25

AL51

VSS_26

AJ51

VSS_27

AG51

VSS_28

AE51

VSS_29

AC51

VSS_30

AA51

VSS_31

W51

VSS_32

U51

VSS_33

R51

VSS_34

N51

VSS_35

L51

VSS_36

J51

VSS_37

G51

VSS_38

C51

VSS_39

BK50

VSS_40

AM50

VSS_41

K50

VSS_42

BG49

VSS_43

E49

VSS_44

C49

VSS_45

BD48

VSS_46

BB48

VSS_47

AY48

VSS_48

AV48

VSS_49

AT48

VSS_50

AP48

VSS_51

AM48

VSS_52

AK48

VSS_53

AH48

VSS_54

AF48

VSS_55

AD48

VSS_56

AB48

VSS_57

Y48

VSS_58

V48

VSS_59

T48

VSS_60

P48

VSS_61

M48

VSS_62

K48

VSS_63

H48

VSS_64

BL47

VSS_65

BG47

VSS_66

E47

VSS_67

C47

VSS_68

A47

VSS_69

BD46

VSS_70

AY46

VSS_71

AM46

VSS_72

AK46

VSS_73

AH46

VSS_74

BG45

VSS_75

AE45

VSS_76

AC45

VSS_77

AA45

VSS_78

W45

VSS_79

R45

VSS_80

N45

VSS_81

E45

VSS_82

BD44

VSS_83

BB44

VSS_84

AV44

VSS_85

AK44

VSS_86

AH44

VSS_87

AF44

VSS_88

AD44

VSS_89

K44

VSS_90

H44

VSS_91

BL43

VSS_92

BG43

VSS_93

AY43

VSS_94

AR43

VSS_95

W43

VSS_96

R43

VSS_97

M43

VSS_98

E43

VSS_99

CANTIGA GMCH SFF_FCBGA1363

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25

4

3

U3J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19
AY19

M19

BD18

BL17
BG17
AY17

M17

BD16
AN16
AG16
AE16

W16

BG15
AY15
AN15
AD15
AC15

M15

BD14

BL13
BG13
AY13
AU13
AR13

AJ13
AC13
AA13

W13
M13

BD12
AV12
AP12
AM12
AK12
AB12

BG11
AG11

BD10
AY10
AP10

BG9

BD8

E19
N18

H18

E17
A17

Y16
N16

H16

R15
E15
H14

U13
E13

A13

V12
P12
H12

E11

H10
BL9

E9
A9

BB8
AY8
AV8
AT8
AP8

VSS

VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299

CANTIGA GMCH SFF_FCBGA1363

VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12

VSS NCTF

VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

VSS SCB

VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358

VSS_359
VSS_360
VSS_361
VSS_362

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7

2

AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13

N42
N40
N38
M39

AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18

BL55
BL1
A55
D1
B55
B2
A4

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cantiga(6/6)-GND

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

13 43Thursday, September 10, 2009

1

1.0

of

5

4

3

2

1

DDR_A_DQS#[0..7]9

DDR_A_D[0..63]9

DDR_A_DM[0..7]9

DDR_A_DQS[0..7]9

DDR_A_MA[0..14]9

D D

Layout Note:
Place near JP3

+1.5V

10U_0603_6.3V6M

C1313

2

1

C C

Layout Note:
Place near JP3.203,204

+0.75VS

10U_0603_6.3V6M

10U_0603_6.3V6M

B B

A A

C1321

C1320

2

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

2

1

C1322

C1314

1U_0402_6.3V4Z

C1315

2

1

1U_0402_6.3V4Z

2

C1323

1

10U_0603_6.3V6M

10U_0603_6.3V6M

C1316

2

1

1U_0402_6.3V4Z

2

2

C1324

1

1

1U_0402_6.3V4Z

C1325

10U_0603_6.3V6M

C1317

C1318

2

2

1

1

2

C1326

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C167

1

1

2

2

C168

+1.5V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

C1065

C1066

1

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C1319

C169

1

1

2

2

For EMI

2

DDR_CKE0_DIMMA8

M_CLK_DDR08

M_CLK_DDR#08

DDR_A_CAS#9

DDR_CS1_DIMMA#8

+3VS

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

DDR_A_BS29

DDR_A_BS09

DDR_A_WE#9

C1311

2.2U_0805_16V4Z
C1329

1

2

C1312

1

2

DDR_A_BS2

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

DDR_CS1_DIMMA#

0.1U_0402_16V4Z

1

2

+1.5V +1.5V+V_DDR_MCH_REF

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_DQS#1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_A_MA12

DDR_A_MA5 DDR_A_MA4
DDR_A_MA3

DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

R1494 10K_0402_5%

1 2

R1495 10K_0402_5%

C1330

+0.75VS

JP3

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U2RN-7F
CONN@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

A15
A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13DDR_A_D9

24
26

DDR_A_DM1

28

SM_DRAMRST#DDR_A_DQS1

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMADDR_CKE0_DIMMA

74
76
78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7DDR_A_MA9

86

A7

88

DDR_A_MA6DDR_A_MA8

90

A6

92

A4

94

DDR_A_MA2

96

A2
A0

G2

98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA0
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63
PM_EXTTS#0

ICH_SMBDATA
ICH_SMBCLK

+0.75VS

SM_DRAMRST# 8,15

DDR_CKE1_DIMMA 8

T147

M_CLK_DDR1 8
M_CLK_DDR#1 8

DDR_A_BS1 9
DDR_A_RAS# 9

DDR_CS0_DIMMA# 8
M_ODT0 8

M_ODT1 8

2.2U_0805_16V4Z

1

2

PM_EXTTS#0 8
ICH_SMBDATA 15,16,22
ICH_SMBCLK 15,16,22

C1327

0.1U_0402_16V4Z
C1328

1

2

+V_DDR_MCH_REF

Top side

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

DDR3 SO-DIMM Slot A

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

14 43Thursday, September 10, 2009

1

1.0

of

5

DDR_B_DQS#[0..7]9

DDR_B_D[0..63]9

DDR_B_DM[0..7]9

DDR_B_DQS[0..7]9

DDR_B_MA[0..14]9

D D

Layout Note:
Place near JP4

+1.5V

Reserve C524. 9/26

1

C187

+

2

330U_D2E_2.5VM_R9

@

C C

Layout Note:
Place near JP4.203,204

+0.75VS

1U_0402_6.3V4Z

2

C1339

1

B B

A A

C1334

C1333

2

2

1

1

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

2

C1340

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

C1341

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

5

C1336

C1335

2

2

1

1

2

C1342

1

10U_0603_6.3V6M

10U_0603_6.3V6M

C1338

C1337

2

2

1

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C193

1

2

2

C194

4

+1.5V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C196

C195

1

1

2

2

@

@

C1067

C1068

1

1

For EMI

2

2

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2.2U_0805_16V4Z
C1331

1

2

DDR_CKE2_DIMMB8

DDR_B_BS29

M_CLK_DDR28

M_CLK_DDR#28

DDR_B_BS09
DDR_B_WE#9

DDR_B_CAS#9

DDR_CS3_DIMMB#8

1 2

R1496 10K_0402_5%

3

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

+0.75VS

0.1U_0402_16V4Z

C1345

1

1

2

2

+1.5V

C1346

Compal Secret Data

+V_DDR_MCH_REF

0.1U_0402_16V4Z
C1332

1

2

DDR_CKE2_DIMMB

DDR_B_BS2

M_CLK_DDR2
M_CLK_DDR#2

+3VS

10K_0402_5%

2.2U_0805_16V4Z

R1497

1 2

2009/04/01 2010/12/31

JP4

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

FOX_AS0A626-U8SN-7F

CONN@

Deciphered Date

2

VREF_CA

SO-DIMM B

Bottom side

2

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1
CK1#

VDD

BA1
RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

A15
A14

A11

S0#

NC

A7
A6

A4
A2

A0

+1.5V+V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

1

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
SM_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

ICH_SMBDATA
ICH_SMBCLK

+0.75VS

Title

Size Document Number Rev

Custom

Date: Sheet

SM_DRAMRST# 8,14

DDR_CKE3_DIMMB 8

T146

PAD~D

M_CLK_DDR3 8
M_CLK_DDR#3 8

DDR_B_BS1 9
DDR_B_RAS# 9

DDR_CS2_DIMMB# 8
M_ODT2 8

M_ODT3 8

2.2U_0805_16V4Z

PM_EXTTS#1 8
ICH_SMBDATA 14,16,22
ICH_SMBCLK 14,16,22

0.1U_0402_16V4Z

C1343

1

2

C1344

1

2

Compal Electronics, Inc.

DDR3 SO-DIMM Slot B

LA-5541P

1

+V_DDR_MCH_REF

Check PM_EXTTS# spec

1.0

of

15 43Thursday, September 10, 2009

5

PCI

FSB
MHz

1066

800

667

+VCCP

SRC
MHz

1000

100

MHz

33.30

33.3

CLKSEL1

FSLA

CLKSEL0

MHz

FSLC1FSLB

CLKSEL2

CPU

0 1000 2660 33.3

1

0

1

D D

200

166

4

+3VS

1 2

R121 0_0805_5%

+1.5VS

1 2

R1535 0_0805_5%

3

+3VM_CK505

1 2

R122 0_0805_5%

1

1

2

2

C217

C218

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C220

C219

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z~D

1

2

C216

@

1

1

2

2

C222

C221

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+1.05VM_CK505+VCCP

1

1

1

10U_0805_10V4Z~D

1

2

C223

2

2

C224

C225

0.1U_0402_16V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z~D

2

C226

1

1

2

2

C227

C228

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

R123

56_0402_5%@

FSA

R130 2.2K_0402_5%

CPU_BSEL05

C C

CPU_BSEL15

FSC

CPU_BSEL25

B B

22P_0402_50V8J

CLK_PCI_EC

A A

CLK_PCI_ICH
CLK_48M_ICH
CLK_48M_CR
CLK_14M_ICH

R146 10K_0402_5%

Y1

2

14.318MHZ_16PF_X5H01431AFG1H-X

C233

1

For RF

C1304 10P_0402_50V8J
C1305 10P_0402_50V8J
C1306 10P_0402_50V8J
C1307 10P_0402_50V8J
C1308 10P_0402_50V8J

12

1 2

R134 0_0402_5%

FSB

1 2

R138
0_0402_5%

9/20

12

1 2

R148 0_0402_5%

CLK_XTAL_OUT

CLK_XTAL_IN

12

9/149/14

2

C234
22P_0402_50V8J

1

@
@
@
@
@

1 2

1 2

R131 1K_0402_5%

12

R135

1K_0402_5%@

+VCCP

R136

1K_0402_5%@

R137

1 2

1K_0402_5%

1 2

12

R141

0_0402_5%@

1 2

R147 1K_0402_5%

12

R150
0_0402_5%

Install. 11/06

ITP_EN

27_SEL

PCI2_TME

MCH_CLKSEL0 8

MCH_CLKSEL1 8

CLK_DEBUG_PORT27

CLK_PCI_EC29

CLK_PCI_ICH20

MCH_CLKSEL2 8

CLK_DEBUG_PORT PCI_CLK

CLK_PCI_EC PCI_CLK3

CLK_PCI_ICH

CLK_48M_ICH22
CLK_48M_CR26

CLK_14M_ICH22

0 = SRC8/SRC8#
1 = ITP/ITP#

*

0 = Enable DOT96 & SRC1(UMA)

*

1 = Enable SRC0 & 27MHz(DIS)
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed

*

+3VS

R153
10K_0402_5%

1 2

R156

@

1 2

10K_0402_5%

+3VS +3VS

R154

@

10K_0402_5%

1 2

27_SELITP_EN

R157
10K_0402_5%

1 2

1 2

PCI2_TME

1 2

CLKREQ#_B_R

CLK_48M_ICH

CLK_14M_ICH FSC

R155
10K_0402_5%

R158

@

10K_0402_5%

R126 475_0402_1%

9/14

+1.05VM_CK505

R150233_0402_1%

1 2

R14233_0402_1%

1 2

R14533_0402_1%

1 2

1 2

1 2

FBMA-11-100505-600T 0402

1 2

+3VM_CK505

+1.05VM_CK505

PCI2_TME

27_SEL
ITP_EN

CLK_XTAL_IN
CLK_XTAL_OUT

R14933_0402_1%
R177

R15133_0402_1%

Security Classification

12

FSA

FSB

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R124 10K_0402_5%

1 2

CLKREQ#_B 8

U4

6

VDDREF

12

VDDPCI

19

VDD48

23

VDD96_IO

27

VDDPLL3

55

VDDSRC

72

VDDCPU

31

VDDPLL3_IO

38

VDDSRC_IO

52

VDDSRC_IO

62

VDDSRC_IO

66

VDDCPU_IO

13

PCI

14

PCI2/TME

15

PCI3

16

PCI4/27_Select

17

PCI_F5/ITP_EN

5

X1

4

X2

20

USB_48MHz/FSLA

2

FSLB/TEST_MODE

7

FSLC/TEST_SEL/REF0

59

GNDSRC

18

GNDPCI

22

GND48

26

GND

30

GND

69

GNDCPU

34

GNDSRC

42

GNDSRC

3

GNDREF

ICS9LPRS397DKLFT MLF 72P

2009/04/01 2010/12/31

CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR

SRCT2_LPR/SATAT_LPR

SRCC2_LPR/SATAC_LPR

SRCT0_LPR/DOTT_96_LPR

SRCC0_LPR/DOTC_96_LPR

27MHz_NonSS/SRCT1_LPR/SE1

27MHz_SS/SRCC1_LPR/SE2

Compal Secret Data

+3VS

SDATA

PCI_STOP#

CPU_STOP#

CPUT0_LPR_F

CPUC0_LPR_F

CPUT1_LPR_F

CPUC1_LPR_F

SRCT7_LPR
SRCC7_LPR

SRCT6_LPR
SRCC6_LPR

CR10#

SRCT10_LPR
SRCC10_LPR

CR#11

SRCT11_LPR
SRCC11_LPR

SRCT9_LPR
SRCC9_LPR

SRCT4_LPR
SRCC4_LPR

SRCT3_LPR
SRCC3_LPR

CK_PWRGD/PD#

T_PAD

Deciphered Date

SCLK

CR7#

CR#6

CR#9

CR#4

CR#3

CR#A

REF1

NC

11

10
9

54
53

71
70

68
67

65
64

63
61

60
58
57

56
49
50

51
46
48

47
43
44

45

41
39

40
37
35

36

32
33

24
25

28
29

1

21

8
73

CLKREQ#_B_R

2

CLKREQ_WLAN#_R
CLKSATAREQ#_R

CLKREQ_WLAN#_R

CLKSATAREQ#_R

R_PCIE_ICH
R_PCIE_ICH#

R128 475_0402_1%
R129 475_0402_1%

ICH_SMBCLK 14,15,22
ICH_SMBDATA 14,15,22

H_STP_PCI# 22
H_STP_CPU# 22

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8

CLK_PCIE_MCARD 27
CLK_PCIE_MCARD# 27

CLKREQA_LAN# 25

CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25

RP28 0_0404_4P2R_5%

CLK_PCIE_SATA 21
CLK_PCIE_SATA# 21

CLK_MCH_DREFCLK 8
CLK_MCH_DREFCLK# 8

MCH_SSCDREFCLK 8
MCH_SSCDREFCLK# 8

CK_PWRGD 22

12
12

SA000020H10 for Compal
SA00001YJ20 for HP

2 3
1 4

Title

Clock Generator CK505

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

R125 10K_0402_5%

1 2

CLKREQ_WLAN# 27

R133 10K_0402_5%

CLKSATAREQ# 22

1 2

CLK_PCIE_ICH 22
CLK_PCIE_ICH# 22

Compal Electronics, Inc.

16 43Thursday, September 10, 2009

1

+3VS

+3VS

1.0

of

5

4

3

2

1

+3VS +3VS

1

1

C1254

C1253

@

@

2

2

0.1U_0402_16V4Z

D D

C C

0.1U_0402_16V4Z

Intel Cantiga TMDS Pin Definition

TMDS_B_CLK
TMDS_B_CLK#

TMDS_B_DATA0
TMDS_B_DATA0#

TMDS_B_DATA1
TMDS_B_DATA1#

TMDS_B_DATA2
TMDS_B_DATA2#

TMDS_B_HPD#

B B

A A

UMA_DVI_TXC+ HDMI_R_CK+

UMA_DVI_TXD0+

UMA_DVI_TXD1-

UMA_DVI_TXD1+

UMA_DVI_TXD2-

UMA_DVI_TXD2+

5

C1255

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HDMIDAT8

HDMICLK8

PEG_TXP_3
PEG_TXN_3

PEG_TXP_2
PEG_TXN_2

PEG_TXP_1
PEG_TXN_1

PEG_TXP_0
PEG_TXN_0

PEG_RXP_3

R508 0_0402_5%

4

1

R509 0_0402_5%

R510 0_0402_5%

4

1

R511 0_0402_5%

R512 0_0402_5%

4

1

R513 0_0402_5%

R514 0_0402_5%

4

1

R515 0_0402_5%

1

C1256

@

2

2.2K_0402_5%

1 2

L15 WCM-2012-900T_0805@

4

1

1 2

1 2

L16 WCM-2012-900T_0805@

4

1

1 2

1 2

L17 WCM-2012-900T_0805@

4

1

1 2

1 2

L18 WCM-2012-900T_0805@

4

1

1 2

R501

+3VS

12

3

2

3

2

3

2

3

2

10U_0805_10V4Z~D

12

3

2

3

2

3

2

3

2

1

C1257

2

+3VS

+3VS

R502

2.2K_0402_5%

HDMIDAT
HDMICLK

+3VS

1

1

1

1

C1259

C1258

2

2

2

0.1U_0402_16V4Z

R492 4.7K_0402_5%X76@
R493 4.7K_0402_5%X76@
R494 4.7K_0402_5%X76@
R499 4.7K_0402_5%X76@

R1527 4.7K_0402_5%X76@

R507 4.7K_0402_5%

Trace AS Short PASS

HDMI_R_CK-UMA_DVI_TXC-

HDMI_R_D0-UMA_DVI_TXD0-

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

DP139 R503 = 3.9K

X76@

1 2

R503 3.6K_0402_1%

1 2

X76@

1 2

UMA_DVI_TXC+
UMA_DVI_TXC-

UMA_DVI_TXD2+
UMA_DVI_TXD2-

UMA_DVI_TXD1+
UMA_DVI_TXD1-

UMA_DVI_TXD0+
UMA_DVI_TXD0-

HDMI_DET HDMI_DET_R

10K_0402_5%

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

4

C1260

+3VS

TMDS_B_HPD#_R

R1514

1 2

HDMI_SDATA_R
HDMI_SCLK_R

X76@

U8

2

VCC3V

11

VCC3V

15

VCC3V

21

VCC3V

26

VCC3V

33

VCC3V

40

VCC3V

46

VCC3V

3

FUNCTION1

4

FUCNTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

ASM1442T QFN 48P

DP139 need stuff R492,R494,
,R498 and change R503 value to 3.9K

SCL_SINK
SDA_SINK

HPD_SINK

DDC_EN

FUNCTION3
FUNCTION4

IN_D4+

IN_D4-

IN_D3+

IN_D3-

IN_D2+

IN_D2-

IN_D1+

IN_D1-

THERMAL_GND

ASM1442T need stuff R503 value 3.6K

+HDMI_5V_OUT

(pin 19) plug in 5V

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

GND

11

CK_shield

GND

10

CK+

GND

9

D0-

GND

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042MR019S153ZL

CONN@

20
21
22
23

HDMI_SDATA

2N7002DW-7-F_SOT363-6

HDMI_SCLK

Q38 Please close to JHDMI1

3

+HDMI_5V_OUT

R491

R495

12

HDMI_DET#

25

OE*

28
29

HDMI_DET

30

R497 4.7K_0402_5%

32

R498 4.7K_0402_5%X76@

34
35

R500 4.7K_0402_5%X76@
R504 4.7K_0402_5%X76@
R505 4.7K_0402_5%X76@

HDMI_UMA_CLK+

48

HDMI_UMA_CLK-

47

HDMI_UMA_TX2+

45

HDMI_UMA_TX2-

44

HDMI_UMA_TX1+

42

HDMI_UMA_TX1-

41

HDMI_UMA_TX0+

39

HDMI_UMA_TX0-

38
49

20071031:
Add U1. 49 (THERMAL_GND) to GND Plane

+HDMI_5V_OUT

2

Q38A

61

5

4

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

2.2K_0402_5%

2.2K_0402_5%

HDMI_SCLK

HDMI_SDATA

1 2

1 2
1 2
1 2
1 2

HDMI_UMA_CLK+ 10
HDMI_UMA_CLK- 10

HDMI_UMA_TX2+ 10
HDMI_UMA_TX2- 10

HDMI_UMA_TX1+ 10
HDMI_UMA_TX1- 10

HDMI_UMA_TX0+ 10
HDMI_UMA_TX0- 10

HDMI_SDATA_R

Q38B

HDMI_SCLK_R

3

2009/04/01 2010/12/31

+3VS

+3VS

+3VS

Compal Secret Data

SUSP31,37

Pin34 Pin35

00

01

11

Deciphered Date

2

G

Equalization

12dB

9dB

6dB

01

3dB *

TMDS_B_HPD#10

@

Pin 3Pin 10

Pin 4 Swing Pre-amp Slew-rate Default

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

2

1U_0603_10V6K

B+_BIAS

R1500

470K_0402_5%

1 2
13

D

S

Default

R506

C1261

1 2

100K_0402_5%

450

0

420

1

450

0

460

1

340

0

400

1

400

0

420

1

+5VS

@

1

C1348

2

EN_HDMI

Q33
SSM3K7002FU_SC70-3

2.2K_0402_5%

HDMI_DET

1

2

0.1U_0402_16V4Z

0

0

0

0

0

2dB

2dB

0

Q32

SI3456BDV-T1-E3 1N TSOP6

D

S

6

+HDMI_5V

4 5

2

W=40mils

1

G

3

R1501

1.5M_0402_5%

1 2

+VCCP

1 2

R496

2

G

For Power Saving Application
When Plug-in HDMI
HDMI_HPD=High OE#=Low Enable Level Shift
When Plug-out HDMI
HDMI_HPD=Low OE#=High Disable Level Shift

0

0

0

-4dB

0

0

0

0

+3VS

@

R1528
10K_0402_5%

+3VS

C

12

12

1 2

HDMI_DET#

13

D

Q16
2N7002_SOT23

S

*

Compal Electronics, Inc.

Title

HDMI Level Shift_AS1442T

Size Document Number Rev

LA-5541P

Date: Sheet

F2

2 1

1.1A_6VDC_FUSE

@

R1489
20K_0402_5%

1 2

R549 0_0402_5%

@

R1492

7.5K_0402_1%

1

TMDS_B_HPD#_R

W=40mils

+HDMI_5V_OUT

17 43Thursday, September 10, 2009

1.0

of

close to U8 VCC (+3VS) pins (one Pin one Capacitor)

A

1 1

+5VS +5VS

C1085

0.1U_0402_16V4Z

1 2

1

5

U11
SN74AHCT1G125GW_SOT353-5

2 2

CRT_HSYNC

CRT_VSYNC

P

A2Y

G

3

4

OE#

B

C1086

0.1U_0402_16V4Z

1 2

HSYNC_G_A

1

5

P

A2Y

G

3

VSYNC_G_A D_VSYNC

4

OE#

U12
SN74AHCT1G125GW_SOT353-5

MSEN#29

R364

1 2

R369

1 2

0_0603_5%

0_0603_5%

RED

GREEN

BLUE

D_HSYNC

@

1

C1087
5P_0402_50V8C

2

C

D10

2 1

RB491D_SC59-3

@

1

C1088
5P_0402_50V8C

2

F1

1.1A_6VDC_FUSE

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

W=40mils

21

0.1U_0402_16V4Z

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015S200ZR

CONN@

12

R365

2.2K_0402_5%

+CRTVDD+RCRT_VCC+5VS

C1084

16
17

12

R366

2N7002DW-7-F_SOT363-6

D

1

2

+3VS+CRTVDD +CRTVDD

2

6 1

Q1A

BLUE
GREEN
RED

Place closed to chipset

2.2K_0402_5%

CRT_DDC_DATA

5

3

4

Q1B

2N7002DW-7-F_SOT363-6

D8

@

+3VS

12

12

R367

CRT_DDC_CLK

1

2

1

3

2

DAN217T146_SC59-3

2

3

DAN217T146_SC59-3

D9

@

D11

@

pull-up 10k on AMD M82M MXM side
pull-up 2.2k on GPU side

R368

2.2K_0402_5%

12

R370 0_0402_5%

12

R371 0_0402_5%

E

Place close to
JCRT1

1

3

+CRTVDD

DAN217T146_SC59-3

GMCH_CRT_DATA 10

GMCH_CRT_CLK 10

pull-up 2.2k on GPU side
pull-up 10k on AMD M82M MXM side

3 3

GMCH_CRT_VSYNC10

GMCH_CRT_HSYNC10

4 4

R372 0_0402_5%

1 2

R373 0_0402_5%

1 2

A

CRT_VSYNC
CRT_HSYNC

B

CRT Termination/EMI Filter

GMCH_CRT_R10

GMCH_CRT_G10

GMCH_CRT_B10

12

R374

12

R375

150_0402_1%

150_0402_1%

12

R376

150_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

GMCH_CRT_R

GMCH_CRT_G GREEN

22P_0402_50V8J

1

1

2

2

C1089

@

C1090

@

2009/04/01 2010/12/31

22P_0402_50V8J

22P_0402_50V8J

1

2

C1091

@

Compal Secret Data

L6

1 2

HLC0603CSCCR11JT_0603

L7

1 2

HLC0603CSCCR11JT_0603

L8

1 2

HLC0603CSCCR11JT_0603

Deciphered Date

10P_0402_50V8J

1

1

2

2

C1093

C1092

D

RED

BLUEGMCH_CRT_B

10P_0402_50V8J

10P_0402_50V8J

1

2

C1094

MSEN#

10P_0402_50V8J

1

2

C1130

Compal Electronics, Inc.

Title

CRT Connector

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

E

of

18 43Thursday, September 10, 2009

1.0

5

4

3

2

1

EMI request.

C1095

INV_PWM_R

12

C1096

12

680P_0402_50V7K

R377 0_0402_5%@

R387 0_0402_5%

+LCDVDD+3VS

BKOFF# 29

LCD_CBL_DET# 29
+5VS

DMIC_DAT 27

DMIC_CLK 27

USB20_N4 22
USB20_P4 22

+3VS
+LCDVDD

LCD_TST 29

DDC2_CLK 10
DDC2_DATA 10

TXOUT_L0- 10
TXOUT_L0+ 10

TXOUT_L1- 10
TXOUT_L1+ 10

TXOUT_L2- 10
TXOUT_L2+ 10

TXCLK_L- 10

TXCLK_L+ 10

@

680P_0402_50V7K

D D

INVPWR_B+

C1102

C C

B B

HONDA_LVD-A40SFYG+

12

680P_0402_50V7K

JLVDS1

1

1

2

2

3

3

4

4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

CONN@

INV_PWM_R

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

INVPWR_B+
INVPWR_B+
INVPWR_B+

12

12

C1103

1

2

INV_PWM

INV_PWM 29

BKLT 10,29

for DPST Function

DMIC_CLK

680P_0402_50V7K

R190

1 2

W=60mils

1

2

C1360

@

0.1U_0603_50V4Z~D

1

1

C1361

2

2

@

@

2200P_0402_50V7K~D

USB20_P4

@

B+

12

C1362

1000P_0402_50V7K~D

+5VS

For EMI

33_0402_1%

FDS4435: P Channel MOS

FDS4435BZ_SO8~D

R1536
200K_0402_5%~D

@

R1537

100K_0402_5%~D

@

SUSP#29,31,34,36,37

D12

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

@

C238

1 2

Q39

1
2
3

2N7002W-7-F_SOT323-3~D

D

12

1 3

4

Q40

IO1

GND

2

2
1

@

@

8
7
6
5

S

G

USB20_N4

33P_0402_50V8J

@

INVPWR_B+

1

2

0.1U_0402_16V4Z

R383

2.2K_0402_5%

DDC2_CLK
DDC2_DATA

W=60mils

C1359

0.1U_0603_50V4Z~D

@

+LCDVDD

C1099

LCD_VCC_TEST_EN29

1

1

C1100

0.1U_0402_16V4Z

2

2

Limited Current < 1A

ENAVDD10,29

+3VS

R384

2.2K_0402_5%

1 2

1 2

+LCDVDD

12

R378

100_0805_5%

61

2

2N7002DW-7-F_SOT363-6
Q2A

@

1 2

R3880_0402_5%

1 2

R3860_0402_5%

12

R381

100K_0402_5%

Avoid Panel display garbage after
power on.

EMI request

TXCLK_L+
TXCLK_L­DDC2_CLK
DDC2_DATA

C1106 100P_0402_50V8J@

1 2

C1107 100P_0402_50V8J@

1 2

C1108 100P_0402_50V8J@

1 2

C1109 100P_0402_50V8J@

1 2

+5VALW

12

R379
47K_0402_5%

4.7U_0805_10V4Z

R380

12

220K_0402_1%

3

Q2B
2N7002DW-7-F_SOT363-6

5

4

Must close JLVDS1pin 27, 28.

DMIC_DAT DMIC_CLK

1

C1104

@

220P_0402_25V8J

2

+LCDVDD

1

W=60mils

C1097

2

0.047U_0402_16V7K
C1101

Q13

SI2301BDS-T1-E3_SOT23-3

1 3

D

L10
FBMA-L11-201209-221LMA30T_0805

1

C1105

@

220P_0402_25V8J

2

S

G

2

C1098

1 2

BKOFF#

BKOFF#

+3VS

1

2

+3VS

4.7U_0805_10V4Z

@

10K_0402_5%

1 2

@

10K_0402_5%

1 2

INVPWR_B+B+

R1521

R382

LVDS CONN & USB Camera +

A A

Dig Mic

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

LCD/Camera/DMIC Connector

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

19 43Thursday, September 10, 2009

1

1.0

of

5

+3VS

1 2

R159 8.2K_0402_5%

1 2

R160 8.2K_0402_5%

1 2

R161 8.2K_0402_5%

1 2

R162 8.2K_0402_5%

D D

C C

1 2

R163 8.2K_0402_5%

1 2

R164 8.2K_0402_5%

1 2

R165 8.2K_0402_5%

1 2

R166 8.2K_0402_5%

+3VS

1 2

R167 8.2K_0402_5%

1 2

R168 8.2K_0402_5%

1 2

R169 8.2K_0402_5%

1 2

R170 8.2K_0402_5%

1 2

R171 8.2K_0402_5%

1 2

R172 8.2K_0402_5%

1 2

R173 8.2K_0402_5%
R174 8.2K_0402_5%

1 2

R175 8.2K_0402_5%

1 2

R176 8.2K_0402_5%

1 2

R178 8.2K_0402_5%

1 2

R179 8.2K_0402_5%

12

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

4

U5B

A11

AD0

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

B12
A10
C12

A8
A12
E10
C11

B9

D8

A4

E8

A3

D9
C8
C2
D7

B3
D11

B6

D5
D3

F4

E3

E4

B2

C4
C1
D1

E2

J4

H2

F1

F5

F2

C7

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

ICH9-M SFF ES_FCBGA569

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

3

PCI_REQ0#

G4

PCI_GNT0#

E1

PCI_REQ1#

A9
E12

PCI_REQ2#

B11
C10

PCI_REQ3#

D6

PCI_GNT3#

C6
D10

A5
E6
C9

PCI_IRDY#

C3
B1
T3

PCI_DEVSEL#

A7

PCI_PERR#

D4

PCI_PLOCK#

C5

PCI_SERR#

H5

PCI_STOP#

A6

PCI_TRDY#

A2

PCI_FRAME#

B8

PLT_RST#

A21
B5
T1

G3
G1
F3
H4

CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

10K_0402_5%

R453

1 2

PLT_RST# 8,25,27,29
CLK_PCI_ICH 16

+3VALW

2

1

B B

PCI_GNT3#

A A

A16 swap override Strap

Low= A16 swap override Enble
High= Default

PCI_GNT3#

*

12

R181

1K_0402_5% @

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

12

R182
1K_0402_5%

@

1

0

1

0

1

1

PCI_GNT0#

DEL J3. 9/29

Boot BIOS Location

SPI

PCI

LPC

KBC_SPI_CS1#22

*

KBC_SPI_CS1#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Place closely pin B10

CLK_PCI_ICH

+3VALW

12

R1516

1K_0402_5%@

12

R183

1K_0402_5%@

2009/04/01 2010/12/31

12

@

R180
10_0402_5%

1

@

C235

8.2P_0402_50V

2

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ICH9M(1/4)-PCI/INT

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

20 43Thursday, September 10, 2009

1

1.0

of

+RTCVCC

1 2

R184 330K_0402_1%

1 2

R185 1M_0402_5%

1 2

R186 330K_0402_1%

1 2

R187 20K_0402_5%

Change from 180K to 20K
& 0.1u to 1u. 9/29

D D

5

LAN100_SLP
SM_INTRUDER#
ICH_INTVRMEN
ICH_SRTCRST#

C236

1U_0603_10V4Z

R188

@

1 2

R189

0_0402_5%

0_0402_5%

@

1 2

1

2

4

3

2

1

ICH_RSVD HDA_SDOUT_CODEC

00
0
1
11

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

1 2

R191 1K_0402_5%@

1 2

R193 1K_0402_5%@

C C

Remove R227 & C199

B B

1
0

HDA_SDOUT_ICH
ICH_RSVD

Add C599 ~ C602 to solve WWAN noise issue. 1/23

Description

RV

XOR
Normal(D)
PCIE Bit1

ICH_RSVD 22

HDA_BITCLK27

HDA_RST#27

HDA_SDOUT27

HDA_SYNC27

HDA_BITCLK_NB8

HDA_RST#_NB8

HDA_SDOUT_NB8

HDA_SYNC_NB8

R318

+RTCVCC

SATA_RXN0_C24

SATA_RXP0_C24
SATA_TXN0_CR24
SATA_TXP0_CR24

SATA_RXN1_C24

SATA_RXP1_C24
SATA_TXN1_CR24
SATA_TXP1_CR24

1 2

20K_0402_5%

1U_0603_10V4Z

+1.5VS

HDA_SDIN027
HDA_SDIN28

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_CR
SATA_TXP0_CR

SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1_CR
SATA_TXP1_CR

R308 33_0402_5%

1 2

R307 33_0402_5%

1 2

R295 33_0402_5%

1 2

R297 33_0402_5%

1 2

R302 33_0402_5%

1 2

R299 33_0402_5%

1 2

R300 33_0402_5%

1 2

R301 33_0402_5%

1 2

10P_0402_50V8J

10P_0402_50V8J

C1355

C1354

1

1

2

2

place under RAM door

1

2

1 2

1 2
1 2

1 2
1 2

12

CLRP1
SHORT PADS

HDA_BITCLK_ICH

HDA_RST#_ICH

HDA_SDOUT_ICH

HDA_SYNC_ICH

HDA_BITCLK_ICH

HDA_RST#_ICH

HDA_SDOUT_ICH

HDA_SYNC_ICH

C1044

R198 24.9_0402_1%

C1051 0.01U_0402_16V7K
C1052 0.01U_0402_16V7K

C1053 0.01U_0402_16V7K
C1054 0.01U_0402_16V7K

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#

ICH_SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN
LAN100_SLP

T47PAD

GLAN_COMP

HDA_BITCLK_ICH
HDA_SYNC_ICH

HDA_RST#_ICH

HDA_SDOUT_ICH

T49PAD

SATA_TXN0_R
SATA_TXP0_R

SATA_TXN1_R
SATA_TXP1_R

U5A

F25

RTCX1

G25

RTCX2

G24

RTCRST#

C24

SRTCRST#

C23

INTRUDER#

E25

INTVRMEN

D25

LAN100_SLP

G22

GLAN_CLK

D14

LAN_RSTSYNC

A14

LAN_RXD0

D12

LAN_RXD1

B14

LAN_RXD2

D13

LAN_TXD0

C13

LAN_TXD1

A13

LAN_TXD2

D15

GPIO56

H22

GLAN_COMPI

H21

GLAN_COMPO

AE7

HDA_BIT_CLK

AB7

HDA_SYNC

AA7

HDA_RST#

AB6

HDA_SDIN0

AE6

HDA_SDIN1

AC6

HDA_SDIN2

AA5

HDA_SDIN3

AC7

HDA_SDOUT

AD8

HDA_DOCK_EN#/GPIO33

AB8

HDA_DOCK_RST#/GPIO34

AC9

SATALED#

AE14

SATA0RXN

AD14

SATA0RXP

AC15

SATA0TXN

AD15

SATA0TXP

AD13

SATA1RXN

AC13

SATA1RXP

AA14

SATA1TXN

AB14

SATA1TXP

ICH9-M SFF ES_FCBGA569

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

LDRQ1#/GPIO23

IHDA

SATA

C246

15P_0402_50V8J

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP11

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

10M_0402_5%

1

2

NMI

1 2

R215

1

2

IN

LPC_AD0

H3

LPC_AD1

J3

LPC_AD2

K5

LPC_AD3

L3
J2
H1

J1

GATEA20

N3
AB23

H_DPRSTP_R#

AE23
AE24

H_FERR#_R

AD25
AE22
AD23
AE21

AD24

KB_RST#

L1
AD21

H_SMI#

AC21

H_STPCLK#

AC25

THRMTRIP_ICH#

AC23
AC22

AD12
AE12
AB12
AA12

AC11
AD11
AB10
AA10

AC16
AB16

AD10
AE10

T48 PAD

CLK_PCIE_SATA#
CLK_PCIE_SATA

R212 24.9_0402_1%

Within 500 mils

ICH_RTCX1

ICH_RTCX2

Y2

4

32.768KHZ_12.5P_1TJS125BJ2A251

1

C247

OUT

12P_0402_50V8J

2

NC3NC

LPC_AD[0..3] 27,29

LPC_FRAME# 27,29

T46 PAD

GATEA20 29
H_A20M# 4

R194 0_0402_5%

1 2

H_DPSLP# 5

R195 56_0402_5%

1 2

H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 29

H_NMI 4
H_SMI# 4

H_STPCLK# 4

R206 54.9_0402_1%

1 2

placed within 2" from
ICH9M

CLK_PCIE_SATA# 16
CLK_PCIE_SATA 16

1 2

9/27

for H_DPRSTP# &
H_DPSLP#.

W=20mils

1

C231

2.2U_0603_6.3V4Z

2

Place near ICH9

H_DPRSTP# 5,8,39

H_FERR#

Place Close to U8.

+VCCP

12

R226

1 2

0_0402_5%

R201
56_0402_5%

W=20mils

D27

1

DAN202U_SC70

GATEA20
KB_RST#

9/27Del PU R203~R204

+VCCP

R192
56_0402_5%

1 2

H_FERR# 4

R196 10K_0402_5%

1 2

R197 10K_0402_5%

1 2

H_THERMTRIP# 4,8

RTCVREF+RTCVCC

2
3

W=20mils

W=20mils

R228

1 2

1K_0402_5%

0.1U_0402_16V4Z

PV for ESD

C230

+3VS

BATT1.1

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ICH9M(2/4)-LAN/HDA/SATA/LPC

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

21 43Thursday, September 10, 2009

1

1.0

of

45
36
27
18

USB_OC#1
USB_OC#0
LID_SW#

5

GPIO48
GPIO1
SIRQ
PM_CLKRUN#

THERM_SCI#

HDD_HALTLED
GPIO22
NPCI_RST#
GPIO17

GPIO21

GPIO37

GPIO18

GPIO57

EC_SCI#

LINKALERT#

WAKE#

ICH_RI#

XDP_DBRESET#

S4_STATE#

ICH_LOW_BAT#

ME__EC_CLK1

ME__EC_DATA1

LID_SW#

R274

2.2K_0402_5%

ICH_SMBDATA

5

Add R621 in 12/03.

+3VS

12

+3VS

R275

12

2.2K_0402_5%

S

G

2

H_STP_PCI#16
H_STP_CPU#16

PCIE_WAKE#25,27,29

Q8
RHU002N06_SOT323

D

13

S

G

2

9/21

+3VS

R235

10K_0402_5%@

VGATE29,39

+3VS

R264 1K_0402_5% @

+3VS

ICH_SMB_DATA

D

ICH_SMB_CLKICH_SMBCLK

13

Q9
RHU002N06_SOT323

12

12

R236

10K_0402_5%@

H_STP_PCI#

1 2

0_0402_5%

R247 0_0402_5%
R248 100K_0402_5%

@

1 2

R262 8.2K_0402_5%

1 2

KBC_SPI_CS1#20

+3VS

D D

+3VALW

C C

+3VALW

B B

@

1 2

R271 10K_0402_5%

@

1 2

R220 10K_0402_5%

1 2

R222 8.2K_0402_5%

1 2

R225 8.2K_0402_5%

@

1 2

R227 8.2K_0402_5%

1 2

R230 8.2K_0402_5%

@

1 2

R231 8.2K_0402_5%

1 2

R232 10K_0402_5%

@

1 2

R233 8.2K_0402_5%

1 2

R234 8.2K_0402_5%

1 2

R237 8.2K_0402_5%

@

1 2

R238 10K_0402_5%

@

1 2

R239 10K_0402_5%

@

1 2

R1517 10K_0402_5%

1 2

R244 10K_0402_5%

1 2

R245 10K_0402_5%

1 2

R246 10K_0402_5%

1 2

R250 10K_0402_5%

@

1 2

R252 10K_0402_5%

1 2

R254 10K_0402_5%

1 2

R259 10K_0402_5%

1 2

R261 10K_0402_5%

@

1 2

R1518 10K_0402_5%

RP29

10K_1206_8P4R_5%

Add in 9/14.

Add RP15 back. 9/27

ICH_SMBDATA14,15,16

ICH_SMBCLK14,15,16

For / DDR3 / CLKGEN

A A

4

2.2K_0402_5%

XDP_DBRESET#4

PM_BMBUSY#8

LID_SW#29

R1503 0_0402_5%

1 2

R240 0_0402_5%

1 2

R1533

WAKE#

THERM_SCI#29

1 2
1 2

EC_SMI#29
EC_SCI#29

CLKSATAREQ#16

SB_SPKR27

MCH_ICH_SYNC#8

ICH_RSVD21

PCIE_RXN227
PCIE_RXP227
PCIE_TXN227

PCIE_TXP227

GLAN_RXN25
GLAN_RXP25
GLAN_TXN25

GLAN_TXP25

4

+3VALW

12

12

R224

R223

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

ICH_RI#

XDP_DBRESET#
PM_BMBUSY#
LID_SW#
H_STP_PCI#_R

R_STP_CPU#
PM_CLKRUN#

SIRQ

SIRQ29

THERM_SCI#
VRMPWRGD

PAD

T51

GPIO1

EC_SMI#
EC_SCI#

GPIO17
GPIO18

T52PAD

GPIO22

T53PAD
T54PAD

GPIO38
GPIO39

T55PAD

GPIO48

T56PAD

GPIO57

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

T57PAD
T58PAD
T59PAD

C265 0.1U_0402_10V7K

1 2

C266 0.1U_0402_10V7K

1 2

C271 0.1U_0402_10V7K

1 2

C272 0.1U_0402_10V7K

1 2

USB_OC#028
USB_OC#127

12

R287

22.6_0402_1%

3

U5C

C18

SMBCLK

C15

SMBDATA

B21

LINKALERT#/GPIO60/CLGPIO4

E18

SMLINK0

A24

SMLINK1

C20

RI#

T5

SUS_STAT#/LPCPD#

C25

SYS_RESET#

L2

PMSYNC#/GPIO0

A23

SMBALERT#/GPIO11

B15

STP_PCI#/GPIO15

A20

STP_CPU#/GPIO25

M5

CLKRUN#/GPIO32

C21

WAKE#

L4

SERIRQ

AD20

THRM#

B24

VRMPWRGD

A19

TP12

AE16

GPIO1

AE18

GPIO6

AD18

GPIO7

B25

GPIO8

C14

GPIO12

D20

GPIO13

AE17

GPIO17

K3

GPIO18

AC8

GPIO20

AC19

SCLOCK/GPIO22

D17

GPIO27

E20

GPIO28

M4

SATACLKREQ#/GPIO35

AB18

SLOAD/GPIO38

AC18

SDATAOUT0/GPIO39

AB19

SDATAOUT1/GPIO48

AC20

GPIO49

A16

GPIO57/CLGPIO5

K4

SPKR

AB20

MCH_SYNC#

C19

TP3

AB17

TP8

AC17

TP9

AD17

TP10

ICH9-M SFF ES_FCBGA569

PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

USB_OC#0
USB_OC#1

USBRBIAS

Within 500 mils

U5D

T25

PERN1

T24

PERP1

R24

PETN1

R23

PETP1

P25

PERN2

P24

PERP2

P21

PETN2

P22

PETP2

N23

PERN3

N24

PERP3

M21

PETN3

M22

PETP3

M25

PERN4

M24

PERP4

L24

PETN4

L23

PETP4

K24

PERN5

K25

PERP5

K21

PETN5

K22

PETP5

H24

PERN6/GLAN_RXN

H25

PERP6/GLAN_RXP

J24

PETN6/GLAN_TXN

J23

PETP6/GLAN_TXP

E24

SPI_CLK

E23

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

F22

SPI_MOSI

G23

SPI_MISO

P4

OC0#/GPIO59

N4

OC1#/GPIO40

N1

OC2#/GPIO41

P5

OC3#/GPIO42

P1

OC4#/GPIO43

P2

OC5#/GPIO29

M3

OC6#/GPIO30

M2

OC7#/GPIO31

P3

OC8#/GPIO44

R1

OC9#/GPIO45

R4

OC10#/GPIO46

R2

OC11#/GPIO47

AE5

USBRBIAS

AD5

USBRBIAS#

ICH9-M SFF ES_FCBGA569

Security Classification

WLAN

EXP

WWAN

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

SMB

Clocks

SYS GPIO

Power MGTController Link

GPIO

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

MISC

V25

DMI0RXN

V24

DMI0RXP

U24

DMI0TXN

U23

DMI0TXP

W23

DMI1RXN

W24

DMI1RXP

V21

DMI1TXN

V22

DMI1TXP

Y24

DMI2RXN

Y25

DMI2RXP

Y21

DMI2TXN

Y22

DMI2TXP

AB24

DMI3RXN

AB25

DMI3RXP

AA23

DMI3TXN

AA24

DMI3TXP

T21

DMI_CLKN

PCI-Express

DMI_ZCOMP

DMI_IRCOMP

GLAN

SPI

USB

2009/04/01 2010/12/31

T22

DMI_CLKP

Direct Media Interface

AB21
AB22

AE2

USBP0N

AD1

USBP0P

AD3

USBP1N

AD4

USBP1P

AC2

USBP2N

AC3

USBP2P

AC5

USBP3N

AB4

USBP3P

AB2

USBP4N

AB1

USBP4P

AA3

USBP5N

AA2

USBP5P

Y1

USBP6N

Y2

USBP6P

W2

USBP7N

W3

USBP7P

V1

USBP8N

V2

USBP8P

Y5

USBP9N

Y4

USBP9P

U3

USBP10N

U2

USBP10P

V4

USBP11N

V5

USBP11P

GPIO21

AE19

HDD_HALTLED

AA18

NPCI_RST#

AE20

GPIO37

AA20

CLK_14M_ICH

K1

CLK_48M_ICH

AB5

ICH_SUSCLK

R3

SLP_S3#

D18

SLP_S4#

B20

SLP_S5#

D16

S4_STATE#

E14
D23

DPRSLPVR

M1

ICH_LOW_BAT#

C16
U4

LAN_RST

D22

RSMRST#

D19

CK_PWRGD_R

U1

M_PWROK

T4
B23

CL_CLK0

C22
A18

CL_DATA0

E22
B18

CL_VREF0_ICH

F21
A17

CL_RST#

C17
B17

A22
E16
A15
D21

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1PCIE_RXN2
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP

Compal Secret Data

Deciphered Date

T50 PAD

R241 10K_0402_5%

1 2

R243 0_0402_5%

1 2

R251 0_0402_5%

1 2

R253 0_0402_5%

USB20_N0 28
USB20_P0 28
USB20_N1 27
USB20_P1 27
USB20_N2 27
USB20_P2 27
USB20_N3 26
USB20_P3 26
USB20_N4 19
USB20_P4 19
USB20_N5 27
USB20_P5 27
USB20_N6 27
USB20_P6 27
USB20_N7 27
USB20_P7 27

2

CLK_14M_ICH 16
CLK_48M_ICH 16

SLP_S3# 29
SLP_S4# 29
SLP_S5# 29

1 2

ON/OFFBTN# 29

PM_RSMRST# 29

M_PWROK 8

CL_CLK0 8

CL_DATA0 8

CL_RST# 8

DMI_RXN0 8
DMI_RXP0 8
DMI_TXN0 8
DMI_TXP0 8

DMI_RXN1 8
DMI_RXP1 8
DMI_TXN1 8
DMI_TXP1 8

DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8

DMI_RXN3 8
DMI_RXP3 8
DMI_TXN3 8
DMI_TXP3 8

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

R276 24.9_0402_1%

1 2

2

CK_PWRGD 16

1

R221 0_0402_5%

PM_PWROK 8,29,39

PM_DPRSLPVR 8,39

R257

3.24K_0402_1%

1 2

12

1

R260

2

453_0402_1%

C263

0.1U_0402_16V4Z

Within 500 mils

+1.5VS

1 2

M_PWROKPM_PWROK

PM_RSMRST#

+3VS

LAN_RST

1 2

R1522 10K_0402_5%

Place closely pin H1Place closely pin AF3

12

@

R283
10_0402_5%

@

1

C273

4.7P_0402_50V8C

2

Compal Electronics, Inc.

Title

ICH9M(3/4)-DMI/USB/GPIO/PCIE

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

12

1

2

22 43Thursday, September 10, 2009

1

12

R27310K_0402_5%

CLK_14M_ICHCLK_48M_ICH

@

R284
10_0402_5%

@

C274

4.7P_0402_50V8C

of

1.0

5

+RTCVCC

C275

0.1U_0402_16V4Z

R289

BLM18PG181SN1D_0603

21

D5
CH751H-40_SC76

ICH_V5REF_RUN

1

C291
1U_0402_6.3V6K

2

1 2

MBK1608301YZF 0603

R298

C309

0.1U_0402_16V4Z

1 2

20 mils

R296

+1.5VS_USBPLL

1

2

C306

0.1U_0402_16V4Z

+1.5VS

1

2

5

C296

1U_0402_6.3V6K

1

2

C307

0.1U_0402_16V4Z

R304
MBK1608301YZF 0603

1 2

D D

C C

B B

+1.5VS

MBK1608301YZF 0603

MBK1608301YZF 0603

A A

+1.5VS

+5VS +3VS +3VALW+5VALW

12

R293

100_0402_5%

9/19

+1.5VS

1 2

+3VS

R303

1 2

1

1

C276

2

2

1

+

2

C282

220U_D2_4VM_R15

R294

100_0402_5%

1

1

2

2

C297

C308

0.1U_0402_16V4Z

12

20 mils

+1.5VS_PCIE_ICH

0.1U_0402_16V4Z

40 mils

1

1

2

2

C280

C279

10U_0603_6.3V6M

12

+1.5VS

10U_0603_6.3V6M

+1.5VS_PCIE_ICH

1

2

C310

10U_0603_6.3V6M

ICH_V5REF_RUN
ICH_V5REF_SUS

1

2

C281

10U_0603_6.3V6M

2.2U_0402_6.3V6M

21

D6
CH751H-40_SC76

ICH_V5REF_SUS

20 mils

1

C292

0.1U_0402_16V4Z

2

+1.5VS_VCCSATAPLL

1

2

C298

1U_0603_10V4Z

1

2

C299

1U_0603_10V4Z

1

2

C303

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH

+1.5VS_GLAN

1

2

C311

10U_0603_6.3V6M

+3VS

4

U5F

G17

VCCRTC

G7

V5REF

U7

V5REF_SUS

J19

VCC1_5_B[01]

K18

VCC1_5_B[02]

K19

VCC1_5_B[03]

L18

VCC1_5_B[04]

L19

VCC1_5_B[05]

M18

VCC1_5_B[06]

M19

VCC1_5_B[07]

N18

VCC1_5_B[08]

N19

VCC1_5_B[09]

P18

VCC1_5_B[10]

R18

VCC1_5_B[11]

T18

VCC1_5_B[12]

T19

VCC1_5_B[13]

U18

VCC1_5_B[14]

U19

VCC1_5_B[15]

W17

VCCSATAPLL

U13

VCC1_5_A[01]

V13

VCC1_5_A[02]

W13

VCC1_5_A[03]

U12

VCC1_5_A[04]

V12

VCC1_5_A[05]

W12

VCC1_5_A[06]

W10

VCC1_5_A[07]

U15

VCC1_5_A[08]

V15

VCC1_5_A[09]

W18

VCC1_5_A[10]

G9

VCC1_5_A[11]

H9

VCC1_5_A[12]

V11

VCC1_5_A[13]

U11

VCC1_5_A[14]

U8

VCCUSBPLL

T9

VCC1_5_A[15]

U9

VCC1_5_A[16]

G11

VCCLAN1_05[1]

H11

VCCLAN1_05[2]

G12

VCCLAN3_3[1]

H13

VCCLAN3_3[2]

J17

VCCGLANPLL

H19

VCCGLAN1_5[1]

J18

VCCGLAN1_5[2]

K16

VCCGLAN3_3

ICH9-M SFF ES_FCBGA569

4

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]

VCCPSUSVCCPUSB

VCCSUS3_3[04]
VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

VCCCL3_3[1]
VCCCL3_3[2]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]

VCC3_3[06]
VCC3_3[07]
VCC3_3[08]

VCCHDA

VCCCL1_05

VCCCL1_5

L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15

P19
T17

U17
V16

U16
V18
AE9

AA9
V14
W14

G8
H7
H8

AD7
V10
T7

H15
H16
V7

G14
G15
H14

W8
J7

J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8

G18
H17
J14

K14

+VCCP

+1.5VS_DMIPLL

VCCSUS1_05_ICH_1
VCCSUS1_05_ICH_2

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

VCCCL1_05_ICH
VCCCV1_5_ICH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

1

2

2

C278

C277

0.1U_0402_16V4Z

0.1U_0402_16V4Z

MBK1608301YZF 0603

1

1

2

2

C283

C284

1U_0603_10V4Z

0.01U_0402_16V7K

9/29

VCC_DMI

(DMI)

+3VS

1

2

C293

+3.3/1.5VCCSUS_HDA

+3VALW

C304

0.1U_0402_16V4Z

1 2
1 2

C305 1U_0402_6.3V6K

+3VS

+3.3/1.5VCC_HDA

0.1U_0402_16V4Z

T60

T61
T62
T63

0.1U_0402_16V4Z

1

2

C302

4.7U_0603_6.3V6K

9/21

9/21

3

MBK1608301YZF 0603

0.1U_0402_16V4Z

1

2

C288

1

2

C295

0.1U_0402_16V4Z

R290

1 2

R292

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C290

C289

R322 0_0603_5%@

1 2

R323 0_0603_5%

1 2

R319 180_0402_1%

1 2

12

1 2

R324 0_0603_5%@

R320

150_0402_1%

+3VALW

1

1

If it support 3.3V audio signals

2

2

POP:R322/R324,

C301

C300

Depop R319/R320/R323

0.1U_0402_16V4Z

If it support 1.5V audio signals
POP:R319/R320/R323,
Depop R322/R324

2009/04/01 2010/12/31

+1.5VS

9/29

+VCCP

+3VS

+3VALW
+3VALW

+1.5VALW

Compal Secret Data

9/29

VCC_DMI

1

2

C285

1U_0603_10V4Z

0.1U_0402_16V4Z

1

2

C286

+3VS
+1.5VS

1

2

C294

0.1U_0402_16V4Z

Deciphered Date

+VCCP

4.7U_0603_6.3V6K

1

2

C287

2

U5E

B4

VSS[001]

B7

VSS[002]

B10

VSS[003]

B13

VSS[004]

B16

VSS[005]

B19

VSS[006]

B22

VSS[007]

D2

VSS[008]

D24

VSS[009]

E5

VSS[010]

E7

VSS[011]

E9

VSS[012]

E11

VSS[013]

E13

VSS[014]

E15

VSS[015]

E17

VSS[016]

E19

VSS[017]

E21

VSS[018]

F24

VSS[019]

G2

VSS[020]

G5

VSS[021]

G10

VSS[022]

G13

VSS[023]

G16

VSS[024]

G19

VSS[025]

G21

VSS[026]

H10

VSS[027]

H12

VSS[028]

H18

VSS[029]

H23

VSS[030]

J5

VSS[031]

J9

VSS[032]

J10

VSS[033]

J11

VSS[034]

J12

VSS[035]

J13

VSS[036]

J15

VSS[037]

J21

VSS[038]

J22

VSS[039]

J25

VSS[040]

K2

VSS[041]

K9

VSS[042]

K10

VSS[043]

K11

VSS[044]

K12

VSS[045]

K13

VSS[046]

K15

VSS[047]

K17

VSS[048]

K23

VSS[049]

L5

VSS[050]

L9

VSS[051]

L10

VSS[052]

L16

VSS[053]

L17

VSS[054]

L21

VSS[055]

L22

VSS[056]

L25

VSS[057]

M9

VSS[058]

M10

VSS[059]

M12

VSS[060]

M13

VSS[061]

M14

VSS[062]

M16

VSS[063]

M17

VSS[064]

M23

VSS[065]

N2

VSS[066]

N5

VSS[067]

N9

VSS[068]

N10

VSS[069]

N12

VSS[070]

N13

VSS[071]

N14

VSS[072]

N16

VSS[073]

N17

VSS[074]

N21

VSS[075]

N22

VSS[076]

N25

VSS[077]

P9

VSS[078]

P10

VSS[079]

P12

VSS[080]

P13

VSS[081]

P14

VSS[082]

P16

VSS[083]

P17

VSS[084]

P23

VSS[085]

R5

VSS[086]

R7

VSS[087]

R8

VSS[088]

R9

VSS[089]

R10

VSS[090]

R16

VSS[091]

R17

VSS[092]

R19

VSS[093]

R21

VSS[094]

R22

VSS[095]

R25

VSS[096]

T2

VSS[097]

T8

VSS[098]

T10

VSS[099]

T11

VSS[100]

T12

VSS[101]

T13

VSS[102]

T14

VSS[103]

T15

VSS[104]

T16

VSS[105]

T23

VSS[106]

ICH9-M SFF ES_FCBGA569

2

1

U5

VSS[107]

U10

VSS[108]

W11

VSS[109]

U14

VSS[110]

W16

VSS[111]

U21

VSS[112]

U22

VSS[113]

U25

VSS[114]

V3

VSS[115]

V8

VSS[116]

V19

VSS[117]

V23

VSS[118]

W1

VSS[119]

W4

VSS[120]

W5

VSS[121]

W7

VSS[122]

W9

VSS[123]

W15

VSS[124]

W19

VSS[125]

W21

VSS[126]

W22

VSS[127]

W25

VSS[128]

Y3

VSS[129]

Y23

VSS[130]

AA1

VSS[131]

AA4

VSS[132]

AA6

VSS[133]

AA8

VSS[134]

AA11

VSS[135]

AA13

VSS[136]

AA15

VSS[137]

AA16

VSS[138]

AA17

VSS[139]

AA19

VSS[140]

AA21

VSS[141]

AA22

VSS[142]

AA25

VSS[143]

AB3

VSS[144]

AB9

VSS[145]

AB11

VSS[146]

AB13

VSS[147]

AB15

VSS[148]

AC24

VSS[149]

AC1

VSS[150]

AC4

VSS[151]

AC10

VSS[152]

AC12

VSS[153]

AC14

VSS[154]

AD2

VSS[155]

AD6

VSS[156]

AD9

VSS[157]

AD16

VSS[158]

AD19

VSS[159]

AD22

VSS[160]

AE3

VSS[161]

AE4

VSS[162]

AE11

VSS[163]

AE13

VSS[164]

AE15

VSS[165]

V17

VSS[166]

AE8

VSS[167]

V9

VSS[168]

J16

VSS[169]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]

A1
A25
AE1
AE25

Compal Electronics, Inc.

Title

ICH9M(4/4)-PWR/GND

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

1

1.0

of

23 43Thursday, September 10, 2009

5

D D

4

3

2

1

HDD Connector

JHDD1

1

GND

2

A+

3

A-

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5

C C

OCTEK_SAT-22DJ1G_22P

GND

Reserved

GND

CONN@

V5
V5

V12

V12

V12

4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

0.01U_0402_16V7K

SATA_RXN0
SATA_RXP0

0.01U_0402_16V7K

SATA_TXP0_CR
SATA_TXN0_CR

Close to JHDD1.

+5VS

12
12

C1116
C1117

SATA_RXN0_C
SATA_RXP0_C

SATA_TXP0_CR 21

SATA_TXN0_CR 21

SATA_RXN0_C 21

SATA_RXP0_C 21

C1111

+5VS

1

2

Close to JHDD1.

1

C1112

2

10U_0805_10V4Z~D

1

1

C1114

C1113

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DVD-ROM Connector

JODD1

1

GND

2

TX+

3

GND
GND

GND

RX+

GND

GND
GND

CONN@

TX­RX-

DP

5V
5V

MD

0.01U_0402_16V7K

4

SATA_RXN1

5

SATA_RXP1 SATA_RXP1_C

6

0.01U_0402_16V7K

7

8
9
10
11
12
13

B B

14
15

SUYIN_127382FB013S266ZR

A A

SATA_TXP1_CR
SATA_TXN1_CR

C1120

12

C1121

12

Close to JODD1.

+5VS

SATA_RXN1_C

SATA_TXP1_CR 21

SATA_TXN1_CR 21

SATA_RXN1_C 21
SATA_RXP1_C 21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+5VS

Close to JODD1.

1

C1123

2

0.1U_0402_16V4Z

1

C1124

2

1U_0603_10V4Z

Compal Secret Data

Deciphered Date

C1122

2009/04/01 2010/12/31

1

1

C1125

2

2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

Compal Electronics, Inc.

Title

HDD/ODD Connector

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

1

of

24 43Thursday, September 10, 2009

1.0

5

4

3

2

1

Y6

20
21
15
16

25
17

27

48

43
46

26
28

41
42

45

14
31
47

LAN_X2LAN_X1

MCT3
RJ45_MIDI3+LAN_MDI3+
RJ45_MIDI3-

MCT2
RJ45_MIDI2+
RJ45_MIDI2-

MCT1
RJ45_MIDI1+
RJ45_MIDI1-

MCT0
RJ45_MIDI0+

U14

HSOP
HSON
HSIP
HSIN

CLKREQB
REFCLK_P
REFCLK_N18NC/MDIP2
PERSTB

VCTRL12A/SROUT12

4

NC/FB12

VDDTX/EVDD12

NC/ENSWREG
RSET

LANWAKEB
ISOLATEB

CKTAL1

DVDD12/AVDD12

CKTAL2

VCTRL12D/VDDSR

7

GND
GND
GND
GND

RTL8111DL-GR_LQFP48_7X7

1

C1278
15P_0402_50V8J

2

33

LED3/EEDO

LED2/EEDI

LED1/EESK

NC/MDIN2
NC/MDIP3
NC/MDIN3

NC/VDDSR

NC/AVDD33

NC/AVDD12

R539 75_0402_5%

R540 75_0402_5%

R541 75_0402_5%

R543 75_0402_5%

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

DVDD12
DVDD12
DVDD12

VDD33
VDD33

AVDD33

NC/GPO

NC

EGND

1 2

1 2

1 2

1 2

34
35
32

38
2

3
5
6
8
9
11
12

13
30
36

19
29

37
44
1

40
10

39

23
24

22

LAN_LED2
LAN_LED1

LAN_ACTIVITY#

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1­LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

1 2

R523 3.6K_0402_5%

+LAN_DVDD12

+LAN_EVDD12

+3V_LAN

+LAN_DVDD12

T1

W=40mil

2

C1279

0.1U_0402_16V4Z

1

Close Pin 44 within 200mils

RJ45_GND

2

C1290
1000P_1206_2KV7K

1

LAN_LED1 LAN_LED2

1

@

C1288

100P_0402_50V8J

2

+3V_LAN

C1350

100P_0402_50V8J

+3V_LAN

EN_WOL#29

2

C1280
22U_0805_6.3V6M

1

1

@

2

1U_0402_6.3V6K

B+_BIAS

1 2
13

D

2

G

S

+3V_LAN

0.01U_0402_16V7K

W=60mils

+3VALW

1

C1349

2

R1504
470K_0402_5%

EN_WOL

Q35
SSM3K7002FU_SC70-3

W=60mil

+LAN_CTRL12A

Close Pin 48 within 200mils

Q34

D

6

S

2
1

SI3456BDV-T1-E3 1N TSOP6

G

3

R1505

1.5M_0402_5%

1 2

L22

1 2

4.7UH_1098AS-4R7M_1.3A

45

2

C1268
10U_0805_10V4Z~D

1

2

C1269

0.1U_0402_16V4Z

1

1

C1270

0.1U_0402_16V4Z

2

Layout Notice : Place as close chip as possible.

1

C1363

0.1U_0603_50V_X7R

2

+LAN_AVDD12 +LAN_EVDD12

1 2

1

C1273
22U_0805_6.3V6M

2

R533 0_0603_1%

1

C1274

0.1U_0402_16V4Z

2

1

C1275
1U_0603_10V4Z

2

Close U14 Pin 19

Close L18 within 200mils

+LAN_AVDD12 +LAN_DVDD12

1 2

R385 0_0603_1%

2

C1126

0.1U_0402_16V4Z

1

2

C1127

0.1U_0402_16V4Z

1

2

C1128

0.1U_0402_16V4Z

1

2

C1129

0.1U_0402_16V4Z

1

Close U14 Pin 10, 13, 30, 36, 39

LED1 ,LED0, LED3, LED2

LEDCFG = 5F 06 ; for NAT20 8111DL LED setting

JLAN1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

9

Green LED-

10

G/O LED+

11

ORANGE LED-

12

Yellow LED+

13

Yellow LED-

14

Detect

SANTA_130452-9

CONN@

C1282

1

2

LAN_LED1

LAN_LED2

LAN_ACTIVITY#

RJ45_MIDI3­RJ45_MIDI3+
RJ45_MIDI1­RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+
RJ45_MIDI0­RJ45_MIDI0+

1 2

R1506 330_0402_5%

1 2

R542 330_0402_5%

1 2

R538 330_0402_5%

1

@

C1284
100P_0402_50V8J

2

+3V_LAN

1

C1271
1U_0603_10V4Z

2

1

C1276
1U_0603_10V4Z

2

2

C1281

0.1U_0402_16V4Z

1

SHLD1
SHLD2

15

LANGND

16

D D

C C

ISOLATEB29

B B

A A

GLAN_RXP22
GLAN_RXN22
GLAN_TXP22
GLAN_TXN22

1 2

C1285 0.1U_0402_16V4Z

1 2

C1283 0.1U_0402_16V4Z

1 2

C1286 0.1U_0402_16V4Z

1 2

C1287 0.1U_0402_16V4Z

PCIE_WAKE#22,27,29

C1144 0.1U_0402_16V7K
C1143 0.1U_0402_16V7K

CLKREQA_LAN#16

CLK_PCIE_LAN16

CLK_PCIE_LAN#16

PLT_RST#8,20,27,29

+LAN_DVDD12

+3V_LAN

+3V_LAN

+3VS

12

R534
1K_0402_5%

ISOLATEB

12

R536
15K_0402_5%

TCT

LAN_MDI3-

TCT

LAN_MDI2+

LAN_MDI2-

TCT

LAN_MDI1+

LAN_MDI1-

TCT
LAN_MDI0+
LAN_MDI0- RJ45_MIDI0-

PCIE_IRX_C_PTX_P6
PCIE_IRX_C_PTX_N6

CLKREQA_LAN#

+LAN_CTRL12A

1 2

R528 2.49K_0402_1%

ISOLATEB

LAN_X1
LAN_X2

1 2

25MHZ_12PF_X5H025000FC1H-H

1

C1277
15P_0402_50V8J

2

T64

1
2
3

4
5
6

7
8
9

10
11
12

NS892406 1G ETHERNET

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

MCT1
MX1+

MX1-

MCT2
MX2+

MX2-

MCT3
MX3+

MX3-

MCT4
MX4+

MX4-

24
23
22

21
20
19

18
17
16

15
14
13

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Gigabit LAN_RTL8111DL

Size Document Number Rev

C

LA-5541P

Date: Sheet

1

25 43Thursday, September 10, 2009

of

1.0

5

+3VS change to +3VS_READER

+3VS

+3VALW

@

R479 0_0402_5%

C1242
1U_0402_6.3V4Z

10/20

R516
R517

@

RST#

12

1 2

R484 0_0402_5%

0.1U_0402_16V4Z

D D

1

C1251

0.1U_0402_16V4Z

2

47P_0402_50V8J

C C

CLK_48M_CR16

1

C1240

2

4.7U_0603_6.3V6K

1

C1243

@

2

CLK_48M_CR

@

R478
100K_0402_5%

1 2

RST#_L

Vender suggesttion

1

2

MODE_SEL

12

@

R481
0_0402_5%

12

R486
33_0402_5%

0_0603_5%

12

0_0603_5%

12

XTLI

4

+CARD_PWR

C1356

1

1

C1241

2

2

CLOSE to U19 Pin11

C1238 0.1U_0402_16V4Z

12

+XDPWR_SDPWR_MSPWR

RST#
MODE_SEL

0.1U_0402_16V4Z

XTLI

USB20_N322
USB20_P322

10MIL

AGND_CR_R

R483

6.19K_0402_1%

1 2

AGND_CR

USB20_N3
USB20_P3

AGND_CR

+VREG

10MIL

U19

1

AV_PLL

3

NC0

7

NC1

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5159-GR LQFP 48P

3

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18

XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12

SD_CLK/XD_D1/MS_CLK_SP11

SD_DAT6/XD_D7/MS_D3_SP10

XD_RDY_SP14

MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO
EECS
EESK

SD_CMD

2

10MIL10MIL

+VREG

10
22
30

NC

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

1 2

C1239 1U_0402_6.3V4Z

SDDAT2_XDRE#
SDDAT3_XDWE#

XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1

XDD5_MSBS

XDD4_SDDAT1

XTAL_CTR

R482 0_0603_5%

SD_CMD

XDCLE
XDCE#
XDALE

SDCD
SDWP
XDCD

12

SDCLK_XDD1_MSCLK

12

R480 0_0402_5%

+CARD_PWR

XTAL_CTR
If Open , use 12MHz. crystal
If Pull high , use CLKGEN 48MHz.

1

CKPS

1

C1245

@

22P_0402_50V8J

2

EMI

B B

MSCLK and SDCLK
solutionࠌش, (

A A

5

+XDPWR_SDPWR_MSPWR

R487

100K_0402_5%

ᇠԲሽቃఎ࿯
܀ᓮᔾ

1 2

RTS5158Eೡ).

R202 33_0402_1%@

1

2

4

1

C1247

0.1U_0402_16V4Z

2

EMI

1 2

C1249
22P_0402_50V8J@

SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3

SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE

SDCLK_XDD1_MSCLK

SD_CMD

SDCD
SDWP

MS_INS#

+XDPWR_SDPWR_MSPWR

0.1U_0402_16V4Z

C1248

1

2

CLOSE to U19 Pin9

2

C1357

1

2

JREAD1

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

7 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

TAITW_R015-A10-LM

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

21

SD-VCC

28

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW
SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

2009/04/01 2010/12/31

20
14
12
30
29

SDDAT4_XDWP#_MSD7

27
23
18
16
25
1

2

26
17
15
19
24
22
13

Compal Secret Data

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0

XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#

SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2

SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3

XDD5_MSBS

Deciphered Date

0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

Card Reader_RTL5159-GR

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

1

26 43Thursday, September 10, 2009

1.0

of

A

B

C

D

E

BTB Conn.

1 1

WL_OFF#29

WAN_RADIO_OFF#29

C717

1 2

1 2

1 2

560_0402_5%

1 2

560_0402_5%

BEEP#29

SB_SPKR22

2 2

1U_0402_6.3V4Z

C718

1U_0402_6.3V4Z

R249 0_0402_5%

R519

BEEP_R

R520

CLKREQ_WLAN#16

CLK_PCIE_MCARD#16
CLK_PCIE_MCARD16

1 2

USB20_N522

USB20_P522

+1.5VS

B+

R267 0_0402_5%

1 2

USB_EN#28,29
LID_SW_IN#29

PLT_RST#8,20,25,29

DMIC_DAT19

DMIC_CLK19
USB20_N122

USB20_P122
USB20_N222

USB20_P222

USB_OC#122
E51TXD_P80DATA29
E51RXD_P80DATA29

40mil

+3VALW

+3VS

2800mA

140mil

CLKREQ_WLAN#

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

WLAN_ACT
BT_PRI

40mil

E51TXD_P80DATA
E51RXD_P80DATA EAPD

JP20

2

2

4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

81

81

82

82

E-T_1001-F80C-01L

CONN@

1

1
334
556
778

9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
616162
636364
656566
676768
696970
717172
737374
757576
777778
797980

PCIE_C_RXN2

PCIE_C_RXP2

EN_WLAN#
LPC_FRAME#
LPC_AD3LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_DEBUG_PORT

PCIE_WAKE#
BEEP_R

PCIE_TXN2

PCIE_TXP2

LPC_FRAME# 21,29
LPC_AD3 21,29
LPC_AD2 21,29
LPC_AD1 21,29
LPC_AD0 21,29
CLK_DEBUG_PORT 16

EC_MUTE_R 29

PCIE_WAKE# 22,25,29

60mil

+5VS

HDA_BITCLK 21

HDA_SDIN0 21

HDA_RST# 21

HDA_SYNC 21

HDA_SDOUT 21

100mil

+5VALW

2000mA

EAPD 29

USB20_N6 22
USB20_P6 22

R4750_0402_5%

12

R4760_0402_5%

12

PCIE_TXN2 22
PCIE_TXP2 22

EN_WLAN# 29

PCIE_RXN2 22

PCIE_RXP2 22

HDA_BITCLK

R200

@

1 2

For EMI

33_0402_1%

C239

1 2

@

33P_0402_50V8J

Blue Tooth Conn.

3 3

4 4

A

BT_DET#29

B

JBT1

BT_DET# BT_PRI
WLAN_ACT

HRS_DF12(3.0)-14DP-0.5V(86)~D

112
334
556
778
9910
111112
131314

GND15GND

CONN@

2
4
6
8
10
12
14

16

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

W=40mils

USB20_P7 22
USB20_N7 22BT_OFF#29

C

+3VS

+3VS

W=40mils

1

C1176

4.7U_0805_10V4Z

2

2009/04/01 2010/12/31

1

C1177

2

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

BTB/Blue Tooth Connector

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

E

of

27 43Thursday, September 10, 2009

1.0

5

D D

4

3

2

1

USB Conn.

+5VALW

1

C1180

0.1U_0402_16V7K~D

C C

2

USB_EN#27,29

Left side USB Power Switch

U15

1

GND

OUT

IN

OUT
OUT

IN

OC#

EN#

USB_EN#

2
3
4

APL3510BKI-TRG SOP 8P

8
7
6
5

W=80mils

1

+

C1181

2

150U_B_6.3VM_R40M

C1182

USB_VCCA

USB20_P022

1

2

0.1U_0402_16V4Z

USB20_N022

USB20_N0

Change to FB EMI

USB_OC#0 22

USB_VCCA

USB20_P0_1

1 2

R418 0_0402_5%

L12

1

1

4

4

WCM2012F2S-900T04_0805 @

1 2

R419 0_0402_5%

@

D15

4
3

2

IO1

VIN

1

GND

IO2

PRTR5V0U2X_SOT143-4

2

2

3

3

USB20_N0_1

USB20_P0_1USB20_P0

USB20_N0_1

USB20_N0_1
USB20_P0_1

W=80mils

USB_VCCA

JUSB1

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004S50DZL

CONN@

CPU

B B

A A

H1
H_4P0

1

H17
H_3P0

@

1

H30
H_3P2

@

1

5

H3

@

H19
H_3P2

H_4P0

1

H4
H_4P0

@

@

1

1

H20
H_3P2

@

@

1

H2
H_4P0

@

1

H18
H_3P2

@

1

H7
H_2P5N

1

H21
H_3P0

1

H29
H_1P3N

1

H8
H_1P2N

@

@

1

H26
H_3P0

@

@

1

@

H11
H_6P0N

1

H9

H10

H_3P0

H_3P2

@

@

1

1

FM1

FM2

@

1

4

H12
H_3P2

@

1

1

FM3

@

@

1

@

FM4

H13

H14

@

H_3P0

@

1

H22
H_2P7X4P0N

1

H15
H_3P0

@

1

@

H_3P0

1

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H23
H_8P5N

3

H6
H_1P2N

@

1

H25
H_8P0X6P0N

@

1

@

1

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

USB/Screws

Size Document Number Rev

Custom

LA-5541P

2

Date: Sheet

28 43Thursday, September 10, 2009

1

1.0

of

+3VALW

0.1U_0402_16V4Z

1

1

C1190

R452

1 2

C1191

2

1 2
1 2

1 2

PCIE_WAKE#_R

1000P_0402_50V7K

1 2

1 2
1 2

C1224 0.1U_0402_16V4Z@

2

0.1U_0402_16V4Z

+3VS

+3VALW

10K_0402_5%

+5VS

EMI request for WWAN noise

SPI_CLK

1 2

C1222

22P_0402_50V8J

@

SUSP#

R442 8.2K_0402_5%

PLT_RST#

CLK_PCI_EC

1 2
2

1

1 2

R1493 100K_0402_5%

R433
33_0402_5%

@

C1201
15P_0402_50V8J

@

SPI_FSEL#

1

2

1 2

12
12

C1192

12
12
12

R4394.7K_0402_5%
R4404.7K_0402_5%

0.1U_0402_16V4Z

1

C1193

2

+3VALW

R46110K_0402_5%
R4322.2K_0402_5%

12

R4312.2K_0402_5%

12

R4364.7K_0402_5%

12

R4434.7K_0402_5% @

12

R150810K_0402_5% @
R150910K_0402_5% @
R5504.7K_0402_5%

R48947K_0402_5%
R49047K_0402_5%

LID_SW_IN#

R151910K_0402_5%

R4292.2K_0402_5%

12

R4302.2K_0402_5%

12

R43410K_0402_5% @
R153810K_0402_5%@

TP_CLK
TP_DATA

R425

@

12

33_0402_5%

1000P_0402_50V7K

1

C1194

2

R437 47K_0402_5%

1 2

MSEN#

EC_SMB_DA2
EC_SMB_CK2

LCD_CBL_DET#

LCD_TST

KSO0
KSO3
EC_SMI#
KSO1
KSO2

EC_SMB_DA1

EC_SMB_CK1
EC_MUTE
EN_WOL#

PCIE_WAKE#22,25,27

32.768KHZ_12.5PF_9H03200413

C1186

@

12

22P_0402_50V8J

EC_SMB_CK132
EC_SMB_DA132
EC_SMB_CK24
EC_SMB_DA24

BKLT10,19

1 2

3

NC

2

NC

1 2

1

C1196

0.1U_0402_16V4Z

2

KSI[0..7]30

KSO[0..16]30

DIAG_LOOP330

SLP_S3#22
SLP_S5#22
EC_SMI#22

LID_SW_IN#27

INV_PWM19
FAN_SPEED30
EAPD27

E51TXD_P80DATA27

E51RXD_P80DATA27

ON/OFFBTN_LED#30

C1226
33P_0402_50V

Y4

OSC
OSC

C1228
33P_0402_50V

GATEA2021
KB_RST#21

SIRQ22

LPC_FRAME#21,27
LPC_AD321,27
LPC_AD221,27
LPC_AD121,27
LPC_AD021,27

CLK_PCI_EC16

R1534 0_0402_5%@

1 2

ON_OFF30

4
1

PLT_RST#8,20,25,27
EC_SCI#22

R518

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW_IN#

INV_PWM
FAN_SPEED
EAPD

BKLT

R1526

DPST FUNCTION

1 2

PCIE_WAKE#_R

E51TXD_P80DATA
E51RXD_P80DATA

ON/OFFBTN_LED#

1 2

CRY2

12

@

R460
20M_0402_5%

CRY1

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PLT_RST#
ECRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

0_0402_5%

ON_OFF

@

U17

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

0_0402_5%

122

XCLK1

123

XCLK0

+3VALW

LPC & MISC

Int. K/B
Matrix

9

22

33

96

VCC

VCC

VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

SM Bus

GPIO

GND

GND

11

24

35

+EC_AVCC

111

125

67

VCC

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

GND

KB926QFD2_LQFP128_14X14

69

94

113

ECAGND

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

C1263

ECAGND AD_BID

21
23
26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65

AD_BID

66
75
76

68

FAN_SET

70

IREF

71

CHGVADJ

72

EC_MUTE

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100

R455

101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

R438

LCD_TST
LCD_CBL_DET#

TP_CLK
TP_DATA

EN_WLAN#
EN_WOL#

R448 15_0402_5%

1 2

R449 15_0402_5%

1 2
1 2

R450

WAN_RADIO_OFF#
FSTCHG

BAT_CHG_LED#
CAPS_LED#

R1524

@

1 2

0_0402_5%

SYSON
VR_ON
ACIN

PM_RSMRST#

1 2

EC_ON

0_0402_5%

PM_PWROK_R
BKOFF#

SLP_S4#
ENBKL

THERM_SCI#
SUSP#
ON/OFFBTN#

W=40mil

1

C1227

4.7U_0603_6.3V6K

2

L19

1

1

2

1000P_0402_50V7K~D

R457 100_0402_5%

+V18R

FBM-11-160808-601-T_0603

C1264

2

FBM-11-160808-601-T_0603

0.1U_0402_16V7K~D

BEEP# 27
ACOFF 33,34

BATT_TEMP 32
BATT_OVP 32
ADP_I 34

BT_DET# 27

FAN_SET 30

IREF 34

CHGVADJ 34

0_0402_5%

EC_MUTE_R

12

LCD_TST 19

LCD_CBL_DET# 19
TP_CLK 30
TP_DATA 30

EN_WLAN# 27
EN_WOL# 25
BT_OFF# 27

VGATE 22,39

FRD#
FWR#
SPI_CLK
FSEL#SPICS#

15_0402_5%

WAN_RADIO_OFF# 27
MSEN# 18
FSTCHG 34
BAT_CHG_LED# 30

PAD

T71

ISOLATEB 25

ENAVDD 10,19

SYSON 31,37,38

VR_ON 39
ACIN 33

PM_RSMRST# 22

LID_SW# 22
EC_ON 30

1 2

BKOFF# 19

WL_OFF# 27

LCD_VCC_TEST_EN 19

PSID_DISABLE# 33

SLP_S4# 22

ENBKL 10

USB_EN# 27,28
THERM_SCI# 22

SUSP# 19,31,34,36,37

ON/OFFBTN# 22

PS_ID 33

0.1U_0402_16V4Z

L20

+3VALW

C1185

SPI_CLK

12

+3VALW+EC_AVCC

12

BATT_TEMP

1

C1266
100P_0402_50V8J~D

2

ECAGND

BATT_OVP

1

C1267
100P_0402_50V8J~D

2

ECAGND

EC_MUTE_R 27

FRD#
FWR#
SPI_CLK
FSEL#

PM_PWROK 8,22,39

12

1

2

1 2

R421 0_0402_5%

1 2

R423 0_0402_5%

20mils

R1507
10K_0402_5%

SPI_FSEL#FSEL#

Board ID

Ra

R522
100K_0402_5%~D

Rb

M/B rev:0.1; 0.2; 0.3; 0.4; 1.0
Voltage:0.0; 0.4; 0.8; 1.2; 1.6

ACIN

1

C1358
100P_0402_50V8J

2

ENBKL

R1525
100K_0402_1%

1 2

SPI ROM

U16

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

16M MX25L1605DM2I-12G SOP 8P ROM

VSS

4

2

Q

SPI_SOSPI_FWR#FWR#

R424 0_0402_5%

+3VALW

12

2007-09-19 change Brd ID

R521
100K_0402_5%~D

1 2

R15294.7K_0402_5%

12

FRD#

1 2

1

C1265

0.1U_0402_16V7K~D

2

LCD_TST

SPI_FWR#

EMI request

R427

33_0402_5%

@

12

C1188

12

22P_0402_50V8J

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

EC_KB926/BIOS ROM

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

of

29 43Thursday, September 10, 2009

1.0

A

B

C

D

E

For EMI

KSO16

C1262 100P_0402_50V8J

KSO15
KSO10
KSO11

1 1

2 2

KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2

1 2

C1195 100P_0402_50V8J

1 2

C1197 100P_0402_50V8J

1 2

C1198 100P_0402_50V8J

1 2

C1199 100P_0402_50V8J

1 2

C1200 100P_0402_50V8J

1 2

C1203 100P_0402_50V8J

1 2

C1204 100P_0402_50V8J

1 2

C1205 100P_0402_50V8J

1 2

C1206 100P_0402_50V8J

1 2

C1207 100P_0402_50V8J

1 2

C1208 100P_0402_50V8J

1 2

C1209 100P_0402_50V8J

1 2

KSI0

C1210 100P_0402_50V8J

KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1 2

C1211 100P_0402_50V8J

1 2

C1212 100P_0402_50V8J

1 2

C1213 100P_0402_50V8J

1 2

C1214 100P_0402_50V8J

1 2

C1215 100P_0402_50V8J

1 2

C1216 100P_0402_50V8J

1 2

C1217 100P_0402_50V8J

1 2

C1218 100P_0402_50V8J

1 2

C1219 100P_0402_50V8J

1 2

C1220 100P_0402_50V8J

1 2

C1221 100P_0402_50V8J

1 2

DIAG_LOOP329

KSI[0..7]29

KSO[0..16]29

INT KBD Conn.

DIAG_LOOP3

KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5

10

KSO4

11

KSO7

12

KSO6

13

KSO8

14

KSO3

15

KSO1

16

KSO2

17

KSO0

18

KSO12

19

KSO16

20

KSO15

21

KSO13

22

KSO14

23

KSO9

24

KSO11

25

KSO10

26
27
28
29
30

JKB1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

GND

30

GND

TYCO_3-2041084-0

CONN@

@

R1532

1 2

0_0603_5%

PWR_ON-OFF_BTN#

2

3

D13

1

PESD24VS2UT

31
32

SW1

3
4

NTC014-BB1G-A100T SPST T-MEC H4.3 4P

EC_ON29

EC_ON

1
2

Power Button

PWR_ON-OFF_BTN#

1 2

R291
0_0402_5%~D

R1520

10K_0402_5%

1

CHN202UPT SC-70

1 2

+3VALW

R315

D18

2
3

2

G

1 2

100K_0402_5%~D

51ON#

13

D

Q31

SSM3K7002FU_SC70-3

S

ON_OFF 29
51ON# 33

Fan Control Circuit

+5VS

+3VS

R465

3 3

FAN_SPEED29

10K_0402_5%

FAN_SPEED

C1237

1000P_0402_50V7K

1 2

1

2

8
7
6
5

APL5607KI-TRG_SO8

GND
GND
GND
GND

U18

1

EN

2

VIN

3

VOUT

4

VSET

FAN_SET29

place as close as EC

LED1

4 4

ON/OFFBTN_LED#29

BAT_CHG_LED#29

A

ON/OFFBTN_LED#

BAT_CHG_LED#

HT-297UY5/BP5_YELLOW-WHITE

WHITE

YELLOW

C1232

1

2.2U_0603_6.3V4Z

2

1

C1236
10U_0603_6.3V6M

2

21

43

+5VS_FAN

R467

1 2

200_0402_5%~D

R1510

1 2

200_0402_5%~D

B

+5VALW

1

C1234
1000P_0402_50V7K~D

2

JFAN1

1

FAN_SPEED

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

ACES_85201-0405N

CONN@

2009/04/01 2010/12/31

+5VS

JTP1

6

G2

5

G1

4

4
3
2
1

TP_CLK

3

TP_DATA

2
1

Compal Secret Data

Deciphered Date

1

C1231

0.1U_0402_16V4Z

2

@

100P_0402_50V8J

Touch Pad Connector

TP_CLK 29
TP_DATA 29

1

1

C1233

D

2

2

C1235

@

100P_0402_50V8J

TP_DATA

TP_CLK

2

3

@

D20
SM05_SOT23

1

MV-1 For ESD request, close to JTP1

Compal Electronics, Inc.

Title

KB/BTN/FAN/TP

Size Document Number Rev

Custom

LA-5541P

Date: Sheet

E

of

30 43Thursday, September 10, 2009

1.0

A

B

C

D

E

+5VALW to +5VS

1

2

1 2

R545
20K_0402_5%

SUSP

+5VALW

C1294
10U_0805_10V4Z~D

2

G

1 1

1

C1293
10U_0805_10V4Z~D

2

B+_BIAS

13

D

Q22
2N7002_SOT23

S

8
7

5

Q20
SI4800BDY-T1-E3_SO8

4

1

C1297

0.01U_0402_25V7K~D

2

+5VS

2

G

B+_BIAS

1
2
36

1

C1295
10U_0805_10V4Z~D

2

1

C1296
1U_0603_10V4Z

2

R544
470_0603_5%

1 2
13

D

S

SUSP

2

G

Q21
2N7002_SOT23

SUSP

+1.5V To +1.5VS

12

13

D

S

+1.5V +1.5VS

R1511
100K_0402_5%~D

R1512

1 2

10K_0402_5%

Q36

SSM3K7002FU_SC70-3

U20

8

D

7

D

6

D

5

D

AO4478L 1N SO8

1

S

2

S

3

S

4

G

1

C1353

0.1U_0603_50V_X7R

2

C1351

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

C1352

1

1

2

2

+3VALW to +3VS

1

2

1 2

R547
102K_0402_1%

SUSP

+3VALW

C1299
10U_0805_10V4Z~D

13

D

Q25

2

2N7002_SOT23

G

S

Q23

SI4800BDY-T1-E3_SO8

8
7

5

4

1

2

1
2
36

C1302

0.1U_0603_50V_X7R

+3VS

1

C1300
10U_0805_10V4Z~D

2

1

C1301
1U_0603_10V4Z

2

R546
470_0603_5%

1 2
13

D

S

SUSP

2

G

Q24
2N7002_SOT23

2 2

1

C1298
10U_0805_10V4Z~D

2

B+_BIAS

3 3

SUSP#19,29,34,36,37

4 4

SYSON29,37,38

A

2

G

2

G

+5VALW

12

13

+5VALW

12

13

D

S

D

S

R548
100K_0402_5%

SUSP

Q26
2N7002_SOT23

R1513
100K_0402_5%

SYSON#

Q37
2N7002_SOT23

SUSP 17,37

SYSON# 37

B

+1.5VS

12

R309

470_0402_5%

61

Q29A

SUSP SUSPSYSON#SUSP

2

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

R310

470_0402_5%

Q29B

5

12

3

4

2N7002DW-7-F_SOT363-6

D

+1.5V

R311

470_0402_5%

Q27A

2

+0.75VS+VCCP

12

61

2N7002DW-7-F_SOT363-6

B

Date: Sheet

12

R312
470_0402_5%

3

Q27B

5

4

2N7002DW-7-F_SOT363-6

Compal Electronics, Inc.

Title

DC/DC Interface

Size Document Number Rev

LA-5541P

E

of

31 43Thursday, September 10, 2009

1.0

5

A

4

3

2

1

CPU OTP

1

PD20

BATT+

D D

BATT+

12

12

PC194

100P_0402_50V8J~D

PJPB1 battery connector

SMART
Battery:

1.BAT+

2.BAT+

3.ID

4.B/I

C C

5.TS

6.SMD

7.SMC

8.GND

9.GND

PL14

SMB3025500YA_2P

1 2

PC195

0.01U_0402_25V7K~D

BATT++

12

PC193
1000P_0402_50V7K~D

@

PJP31

1
2
3
4
5
6

10
11

SUYIN_200275MR009G186ZL

7
8

GND

9

GND

14" change to TOP side

BATT++

12

PC196

100P_0402_50V8J~D

1
2
3
4
5
6
7
8
9

3S/4S#

+3VALWP

1 2

1 2

PR219

100_0402_5%~D

1 2

PR222

100_0402_5%~D

PR212
47K_0402_5%~D

3S/4S# 34

PESD24VS2UT_SOT23-3

2

3

EC_SMB_DA1 29

EC_SMB_CK1 29

PR217

1K_0402_5%~D

1

PD21
PESD24VS2UT_SOT23-3

2

3

Place clsoe to EC pin

PR213

1K_0402_5%~D

1 2

BATT_TEMP

PC198

0.1U_0402_16V7K~D

1 2

@

+3VALWP

PR215

6.49K_0402_1%~D

BATT_TEMP 29

PC22

1000P_0402_50V7K~D

1 2

12

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS

12

PR39

10.7K_0402_1%~D

PR43

OTP_IN OTP_IN+

12

61.9K_0402_1%~D

1 2

VL

12

PH1

100K_0603_1%_TH11-4H104FT

1 2

PR45

150K_0402_1%~D

PR47

150K_0402_1%~D

PR40

147K_0402_1%~D

1 2

OTP_IN-

12

12

PC23
1U_0603_10V6K~D

3
2

8

P

+

-

G

PU11A

4

LM358ADR_SO8

0

PD11

OTP_OUT

1

1 2

1SS355TE-17_SOD323-2

VL

PR41
205K_0402_1%~D

1 2

MAINPWON 33,35

BATT+

12

PR223
453K_0402_1%~D

VS

B B

1 2

B+

100_0805_5%~D

+5VALW

PR228

1 2

220K_0402_5%

12

PC204

PR230

0.1U_0603_25V7K~D

PR225

12

PD22

1 2

PR226

1 2

470K_0402_5%~D

1SS355TE-17_SOD323-2

220K_0402_5%

PQ66

2

G

PQ65

TP0610K-T1-E3_SOT23-3

13

32.8

2

13

D

RHU002N06_SOT323-3

S

PC202

B+_BIAS

1 2

0.1U_0805_25V7M~D

COIN RTC Battery

PJP32

1
2

GND
GND

ACES_88231-02001

1
2

3
4

BATT1.1

12

PR227

12

BATT_OVP29

10K_0402_1%~D

LM358ADR_SO8

7

PU11B

8

5

P

+

0

6

-

G

4

LI-3S :13.5V----BATT-OVP=1.126V
LI-4S :18V----BATT-OVP=1.5V
BATT-OVP=0.08338*BATT+

12

499K_0402_1%~D

PC201

0.01U_0402_25V7K~D

12

86.6K_0402_1%~D

PR224

PR229

12

PC203

0.01U_0402_25V7K~D

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/2/6 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

A3

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN/OTP

LA-5541P

32 43Thursday, September 10, 2009

of

1.0

A

PL2

FBM-L11-160808-601LMT 0603~D

PD2

12

DC_IN_S1

ACOFF29,34

PR9

1K_1206_5%~D

1 2

PR11

1K_1206_5%~D

1 2

PR14

1K_1206_5%~D

1 2

1K_1206_5%~D

1 2

PJPDC1

1 1

9

GND4

8

GND3

7

GND2

6

GND1

FOX_JPD113E-LB103-7F

SINGAL

DC+_1
DC+_2
DC-_1
DC-_2

5
1
2
3
4

VIN

RLS4148_LL34

2 2

PR15

DOCK_PSID

12

12

2

PC2

ADPIN

FBMA-L18-453215-900LMA90T_1812

12

1000P_0402_50V7K~D

12

12

PR16

PR18

100K_0402_5%~D

13

PQ4
DTC115EUA_SC70-3

PL1

1 2

PC3

100P_0402_50V8J~D

PQ1

TP0610K-T1-E3_SOT23-3

2

100K_0402_5%~D

12

PR20

13

2

12

13

100K_0402_5%~D

PQ5
DTC115EUA_SC70-3

B

Vin Detector
Max. typ. Min.

VIN

L-->H 18.234 17.841 17.449
H-->L 17.597 17.210 16.813

12

PC4

100P_0402_50V8J~D

PC5

1000P_0402_50V7K~D

B+

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

BATT ONLY

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

12

PC8

0.1U_0402_16V7K~D

DOCK_PSID

2

1

VIN

PR7

20.5K_0402_1%~D

3

@

PD4
SM24_SOT23

C

12

PR3

82.5K_0402_1%~D
PR6

22K_0402_1%~D

1 2

12

12

PR19

1 2

100K_0402_1%~D

PR22

1 2

15K_0402_1%~D

PC1

2200P_0402_50V7K~D

1 2

N40N41
N35

PC7
1000P_0402_50V7K~D

56K_0402_5%~D

1 2

PR2
1M_0402_1%~N

1 2

VS

8

PU1A

3

P

+

2

-

G

LM393DR_SO8

4

PR10

10K_0402_5%~D

12

@

1 2

0_0402_5%~D

1 3

2

B

PR1

12

PC6

0.01U_0402_25V7K~D

1

O

RLZ4.3B_LL34

RTCVREF

3.3V

PR12

D

S

PQ2
FDV301N_NL_SOT23-3~D

G

2

C

PQ3
MMST3904-7-F_SOT323~D

E

3 1

VIN

PD1

PR17

33_0402_5%~D

1 2

12

PR5
10K_0402_5%~D

12

3

PD3

DA204U_SOT323~D

1

2

+5VALW

D

PR4
1K_0402_5%~D

1 2

12

PR8
10K_0402_5%~D

12

PR21

10K_0402_1%~D

1 2

VIN

PR23

10K_0402_1%~D@

ACIN

+3VALW+5VALW

PR13

@

2.2K_0402_5%~D

PD5

1 2

+5VALW

DA204U_SOT323~D

2

3

1

ACIN 29

PACIN 34

PS_ID 29

PSID_DISABLE# 29

PD6

PD7

CHGRTCP

PC14

RLS4148_LL34-2

PR28

200_0805_5%~D

1 2

PR30

100K_0402_5%~D

PR31

22K_0402_5%~D

1 2

RTCVREF

3.3V

12

12

12

PC9

PU2

3

OUT

APL5156_SOT89-3

68_1206_5%~D

PQ6

N1

12

TP0610K-T1-E3_SOT23-3

2

0.22U_1206_25V7K~D

12

PR34
200_0805_5%~D

N2

2

IN

GND

1

12

PC15
1U_0805_25V4Z~D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PR24

VS

7

O

PU1B

PR35

34K_0402_1%~D

2.2M_0402_5%~D

12

8

5

P

+

6

-

G

4

12

12

PC12

1000P_0402_50V7K~D

12

PR32

191K_0402_1%~D

PRG++

PQ7

13

D

RHU002N06_SOT323-3

2

G

S

B

499K_0402_1%~D

499K_0402_1%~D

VL

3 3

12

PR29

100K_0402_1%~D

MAINPWON32,35

ACON34

PD8

2
3

RB715F_SOT323-3

1

12

PC11

0.1U_0603_25V7K~D

LM393DR_SO8

RTCVREF

4 4

A

B+

12

PR27

12

PR33

47K_0402_5%~D

13

12

PC13

0.01U_0402_25V7K~D

PR36

PACIN

12

PQ8
DTC115EUA_SC70-3

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VALW

2009/2/6 2010/12/31

Compal Secret Data

BATT+

51ON#30

10U_0805_10V4Z~D

Deciphered Date

C

RLS4148_LL34-2

1 2

12

12

PR25

13

PR26
68_1206_5%~D

12

PC10

0.1U_0603_25V7K~D

DCIN & DETECTOR

D

33 43Thursday, September 10, 2009

VS

1.0

of

A

Iada=0~3.42A(65W)

ADP_I = 19.9*Iadapter*Rsense

PQ11

AO4407A_SO8

VIN

1 1

12

PR58
47K_0402_1%~D

DTA144EUA_SC70-3

2

13

D

2

G

PQ21

2 2

3 3

S

RHU002N06_SOT323-3

PACIN33

ACON33

ACOFF29,33

CP mode

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)

PQ16

2

13

PQ17
DTC115EUA_SC70-3

22K_0402_5%~D

PACIN

1 2

ACON

ACOFF

8
7

5

PR76

4

1 3

150K_0402_1%~D

2

1
2
36

12

PC31

PR68

2

G

13

PQ25
DTC115EUA_SC70-3

P2

12

PR59

0.1U_0603_25V7K~D

12

13

D

PQ23
RHU002N06_SOT323-3

S

IREF29

Vaclim=2.87*((11.5K//152K)/((2.87K//152K)+(11.5K//152K)))

PQ12

AO4407A_SO8

1
2
3 6

4

200K_0402_1%~D

FSTCHG29

6251VDD

1 2

PR66

47K_0402_5%~D

3S/4S#32

PR79

150K_0402_1%~D

100K_0402_1%~D

8
7

5

1 2

PC32

5600P_0402_25V7K~D

1SS355TE-17_SOD323-2

13

2

PC41

1 2

0.01U_0402_25V7K~D

ADP_I29

12

12

PR80

6251VREF

PC48

1 2

11.5K_0402_1%~D

P3

P3

PD15

1 2

10K_0402_5%~D

0.1U_0402_16V7K~D

PQ19
DTC115EUA_SC70-3

PC37

@

680P_0402_50V7K~D

CSON

1 2

PC39 6800P_0402_25V7K~D

1 2

PR72 10K_0402_1%~D

1 2

1 2

100P_0402_50V8J~D

@

0.1U_0402_16V7K~D

12

0.01U_0402_25V7K~D

PR82

CHGVADJ29

CC=0.22~3.3A
IREF=1*Icharge
IREF=0.22V~3.294V

CHGVADJ CV mode

0V

4V per cell

0.02_2512_1%

1
2

12

PR61

100K_0402_1%~D

PR65

1 2

PC34

PC42

PC43

1 2

12

PR83

2.87K_0402_1%~D

B

B+

PR57

4
3

TP0610K-T1-E3_SOT23-3

2

6251VDD

12

PR67

100K_0402_1%~D

PR74

100_0402_1%~D

1 2

6251VREF

6251aclim

PR84

1 2

PR85

PC33

2.2U_0603_6.3V6K~D

6251_EN

12

25.5K_0402_1%~D

100K_0402_1%~D

12

PC74

PC75

2200P_0402_25V7K~D

2200P_0402_25V7K~D

PQ14

13

PR62

100K_0402_1%~D

12

1

2

3

4

5

6

7

8

9

10

11

12

12

12

12

12

PC76

PC77

PC78

2200P_0402_25V7K~D

2200P_0402_25V7K~D

2200P_0402_25V7K~D

PR107
10_1206_5%~D

1 2

12

PU4

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

24

23

22

21

20

19

18

17

16

15

14

13

VDD

ACSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

ISL6251AHAZ-T_QSOP24

FBMA-L18-453215-900LMA90T_1812

12

12

12

PC79

2200P_0402_25V7K~D

DCIN

PQ15

13

DTC115EUA_SC70-3

RB715F_SOT323-3

DCIN

LX_CHG

DH_CHG

BST_CHG BST_CHGA

6251VDDP

DL_CHG

PC73

PC72

0.1U_0603_25V7K~D
2200P_0402_25V7K~D

CSIN
CSIP

PD13

FSTCHG

2

2

1

3

PC35

0.1U_0603_25V7K~D

12

20_0603_5%

1 2

PC38

0.047U_0603_16V7K~D

1 2

1 2

PR70

20_0603_5%

12

PR71 20_0603_5%

PC40 0.1U_0603_25V7K~D

1 2

1 2

PR78

2.2_0603_5%~D

1 2

PC50

1 2

4.7U_0805_6.3V6K~D

PL3

1 2

12

SUSP#

PR69

PR73

2.2_0603_5%~D

0.1U_0603_25V7K~D

12

PD17
RB751V-40TE17_SOD323-2

1 2

PR81

4.7_0603_5%~D

C

12

12

PC28

PC27

10U_1206_25V6M~D

PC29

10U_1206_25V6M~D

SUSP# 19,29,31,36,37

CSON

AO4710_SO8

CSOP

PC44

6251VDD

AO4466_SO8

12

CHG_B+

12

12

PC30

0.1U_0603_25V7K~D
2200P_0402_25V7K~D

578

PQ22

3 6

578

PQ24

3 6

10K_0402_1%~D

PQ18

DTC115EUA_SC70-3

241

10UH_PCMB104T-100MS_6A_20%

1 2

12

PR77

4.7_1206_5%~D

12

241

PC49

680P_0402_50V7K~D

PQ13

AO4407A_SO8

1
2
3 6

4

47K_0402_1%~D

1 2

PR63

1 2

13

PL4

CHG

8
7

5

PR60

PD14

1SS355TE-17_SOD323-2

1 2

PD16

1SS355TE-17_SOD323-2

2

1 2

PC36

0.1U_0603_25V7K~D

PR75

0.02_2512_1%

1
2

D

VIN

ACOFF

PR64

200K_0402_1%~D

1 2

13

D

12

S

4
3

PC45

10U_1206_25V6M~D

VIN

PQ20
RHU002N06_SOT323-3

PACIN

2

G

12

12

PC47

PC46

10U_1206_25V6M~D

BATT+

12

10U_1206_25V6M~D

1.882V

3.294V

4 4

-

A

4.2V per cell

4.45V per cell

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2010/12/312009/2/6

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

ULV

D

34 43Thursday, September 10, 2009

1.0

of

5

4

3

2

1

TPS51427_B+

PL7

FBMA-L18-453215-900LMA90T_1812

B+

D D

C C

B B

12

1000P_0402_50V7K~D

+3VALWP

+3.3VALWP

Thermal Design current=4.2A

A A

OCP min=7A

1 2

12

PC145

PC144

1000P_0402_50V7K~D

12

PC200

0.1U_0402_10V7K~D

PJP5

112

JUMP_43X118 @

PJP6

112

JUMP_43X118 @

PJP7

112

JUMP_43X118 @

PJP8

112

JUMP_43X118 @

12

12

PC51

PC199

0.1U_0603_25V7K~D

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

12

PR90

1

+

PC61

2

330U_D3L_6.3VM_R25M

0_0402_5%~D

PR93

@

10K_0402_1%~D

1 2

PC52

4.7U_0805_25V6-K~D

4.7U_0805_25V6-K~D

PL5

1 2

680P_0402_50V7K~D

VS

2

2

2

2

CH355PT_SOD323-2

+3VALWP+3VALW

+5VALWP+5VALW

PD19

12

PC53

2200P_0402_50V7K~D

PR87

4.7_1206_5%~D

PC64

PD18

RLZ5.1B_LL34-2

1 2

12

12

12

12

1 2

MAINPWON32,33

2

578

3 6

241

786

5

123

PR97

100K_0402_1%~D

PR98

806K_0603_1%~D

0_0402_5%~D

1 3

PQ26
AO4466_SO8

PQ28
AO4710_SO8

4

PC68

0.22U_0603_10V7K~D

1 2

1 2

200K_0402_1%~D

VL

PR103

PR105

1 2

12

PQ30

TP0610K-T1-E3_SOT23-3

Security Classification

Fsw=300KHZ

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

PR86

0_0805_5%~D

1 2

PR88 2.2_0603_5%~D

PC62

0.1U_0603_25V7K~D

1 2

PC67

0.22U_0603_10V7K~D

PR101

@

0_0402_5%~D

PR106

@

47K_0402_5%~D

1 2

12

PC70

.1U_0603_25V7K~D

Issued Date

PC57

0.1U_0603_25V7K~D

DH3

BST3A

12

LX3

DL3

FB3

VL

2VREF_TPS51427

1 2

PR102

1 2

1 2

2VREF_TPS51427

12

PC71

@

0.047U_0402_16V7K~D

3

VL

1 2

PU5

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1

REF

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

0_0402_5%~D

PC69

1 2

PC58

1U_0603_10V6K~D

3

6

VIN

VCC

TON

NC

2

5

12

PR104
0_0402_5%~D

1 2

1U_0603_10V6K~D

2VREF_TPS51427

2009/2/6 2010/12/31

12

PC59

4.7U_0805_6.3V6K~D

7

19

LDO

PVCC

UGATE1

BOOT1

PHASE1

LGATE1

PGND

OUT1

FB1

BYP

SKIP

POK2

POK1

ILIM1

ILIM2

GND

TPS51427_QFN32_5X5

21

DH5

15

BST5A

17

0.1U_0603_25V7K~D

LX5

16

DL5

18

22

10

FB5

11

9

29

28

13

ILM1

12

ILIM2

31

Compal Secret Data

Deciphered Date

PC60

1U_0603_10V6K~D

1 2

PR89 2.2_0603_5%~D

12

PC63

PR95 0_0402_5%~D@

12

PR96 0_0402_5%~D

1 2

@

1 2

PR99
267K_0402_1%~D

PR100
169K_0402_1%~D

2

578

PQ27

AO4466_SO8

3 6

241

786

5

PQ29

AO4710_SO8

4

123

VL

POK

12

12

+5VALWP

Thermal Design current=5.8A

OCP min=10A

Fsw=400KHZ

Title

Size Document Number Rev

Custom

Date: Sheet

TPS51427_B+

12

PC54

4.7U_0805_25V6-K~D

1 2

2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

12

PR91

4.7_1206_5%~D

12

PC65

680P_0402_50V7K~D

PC56

PC55

4.7U_0805_25V6-K~D

2200P_0402_50V7K~D

PL6

@

PC197

0.1U_0603_25V7K~D

PR92

1 2

61.9K_0402_1%~D

PR94

0_0402_5%~D

1 2

12

12

Compal Electronics, Inc.

+5VALWP/+3VALWP

1

12

+5VALWP

1

2

35 43Thursday, September 10, 2009

+

PC66

of

12

PC206

0.1U_0402_10V7K~D

330U_D3L_6.3VM_R25M

1.0

A

B

C

D

+VCCPP

Thermal Design current=11.5A

OCP min=19.5A

1 1

+3VALW

Fsw=290KHZ

+VCCPP_B+

12

PC174

2200P_0402_50V7K~D

12

PC175

PC176

0.1U_0603_25V7K~D

PL9

FBMA-L18-453215-900LMA90T_1812

1 2

@

12

12

12

PC185

PC177

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

12

PC187

PC186

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

B+

12

12

@

PR204

FB_VCCPP

12

PR209
470K_0402_5%~D

100K_0402_1%~D

PG_VCCPP
TRIP_VCCPP
EN_VCCPP

RF_VCCPP

PU15

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51218DSCR_SON10_3X3~D

2 2

PR207

0_0402_5%~D

SUSP#19,29,31,34,37

1 2

PC106

@

0.1U_0402_16V7K~D

PR206

69.8K_0402_1%~D

1 2

12

VBST

DRVH

V5IN

DRVL

BST_VCCPP

10

UG_VCCPP

9

SW_VCCPP

8

SW

TP

V5IN_VCCPP

7

LG_VCCPP

6
11

PR205

2.2_0603_5%~D

1 2

1

PC179

2

PC178

0.22U_0603_10V7K~D

1 2

+5VALW

1U_0603_6.3V6M~D

3

D

PQ47

2

G

S

SI7686DP-T1-E3_SO8

1

3

D

PQ48

2

G

S

1

1UH_FDUE1040D-1R0M-P3_21.3A_20%

12

4.7_1206_5%~D

PR208

12

680P_0402_50V7K~D

PC184

PL13

1 2

12

PC181

PC180

0.1U_0402_10V7K~D

10U_0805_6.3V6M~D

+VCCPP

1

330U_Y_2.5VM

1

+

+

PC183

2

2

330U_Y_2.5VM

1

PC182

2

SI7170DP-T1-GE3-POWERPAK8-5

PR210

20K_0402_1%~D

3 3

1 2

PR211

10K_0402_1%~D

12

+VCCPP

@

PJP29
JUMP_43X118

112

PJP30
JUMP_43X118

112

2

+VCCP

2

@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2010/12/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

+VCCPP

Size Document Number Rev

Thursday, September 10, 2009

Date: Sheet

D

of

36 43

1.0Custom

A

B

C

D

+1.5VP

1

PJP12

1

1 1

PC91

4.7U_0805_6.3V6K~D

PR116

10K_0402_1%~D

SUSP17,31

SYSON#31

1 2

PR118

10K_0402_1%~D

1 2

@

PC95

0.1U_0402_16V7K~D

12

2

2

1 2

13

D

2

G

S

JUMP_43X79

@

12

PR115

1K_0402_1%~D

12

PR117

PQ33
RHU002N06_SOT323-3

1K_0402_1%~D

12

PC93

0.1U_0402_16V7K~D

PU7

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.75VSP

12

PC94
10U_0603_6.3V6M~D

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC92
1U_0603_10V6K~D

2 2

PJP13

2

112

JUMP_43X118@

+0.75VS+0.75VSP

+3VALW

+5VALW

12

PC96

1U_0603_10V6K~D

PR119
10K_0402_1%~D

SUSP#

3 3

SUSP#19,29,31,34,36

SYSON29,31,38

1 2

1U_0603_10V6K~D

@

SYSON

PC98

PR123
10K_0402_1%~D

1 2

PC101

@

12

@

12

1U_0603_10V6K~D

12

PR120
47K_0402_5%~D

1

2
12

PU8

6
5
9

8
7

PJP14

1

JUMP_43X79

2

@

VCNTL
VIN
VIN

EN
POK

PC97

4.7U_0805_6.3V6K~D

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

PJP15

+1.8VP +1.8V

2

JUMP_43X118@

PR121

1.5K_0402_1%~D

PR122

1.2K_0402_1%~D

112

12

12

12

PC100

PC99

0.01U_0402_25V7K~D

+1.8VP

12

22U_0805_6.3V4Z~D

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2010/12/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

+1.8VP / +0.75VP

Thursday, September 10, 2009

D

of

37 43

1.0Custom

A

B

C

D

+1.5VSP

Thermal Design current=11.5A

OCP min=20A

1 1

+1.5VSP_B+

Fsw=300KHZ

PL12

FBMA-L18-453215-900LMA90T_1812

1 2

B+

330U_Y_2.5VM

1

+

2

12

PC116

2200P_0402_50V7K~D

+1.5VP

PC111

10U_0805_6.3V6M~D

PC115

10U_1206_25V6M~D

1

2

12

PC112

@

330U_Y_2.5VM

1

+

PC113

2

12

PC102

+1.5VP

PC103

2200P_0402_50V7K~D

12

PR124

100K_0402_1%~D

VBST

DRVH

V5IN

DRVL

BST_1.5VSP

10

UG_1.5VSP

9

SW_1.5VSP

8

SW

TP

V5IN_1.5VSP

7

LG_1.5VSP

6
11

2 2

SYSON29,31,37

SM_PWROK8

PR127

0_0402_5%~D

1 2

PC108

@

0.1U_0402_16V7K~D

PR126

71.5K_0402_1%~D

1 2

12

PG_1.5VSP
TRIP_1.5VSP
EN_1.5VSP
FB_1.5VSP
RF_1.5VSP

12

PR129
470K_0402_5%~D

PU9

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51218DSCR_SON10_3X3~D

PR125

2.2_0603_5%~D

1 2

1

2

0.22U_0603_10V7K~D

+5VALW

PC109

PC107

1 2

1U_0603_6.3V6M~D

3

D

PQ34

2

G

S

1

SI7686DP-T1-E3_SO8~D

3

D

PQ35

2

G

S

1

1UH_FDUE1040D-1R0M-P3_21.3A_20%

12

PR128

4.7_1206_5%

12

PC114
680P_0402_50V7K~D

PL8

1 2

12

12

PC104

0.1U_0805_50V7M~D

12

PC105

10U_1206_25V6M~D

10U_1206_25V6M~D

12

PC110

0.1U_0402_10V7K~D

SI7170DP-T1-GE3-POWERPAK8-5~D

PR130

10K_0402_1%~D

3 3

1 2

PR131

11.5K_0402_1%~D

12

+1.5VP

@

PJP17
JUMP_43X118

112

PJP18
JUMP_43X118

112

2

+1.5V

2

@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/2/5 2010/12/31

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

+1.5VSP

Thursday, September 10, 2009

of

D

38 43

1.0Custom

+VCCP

5

4

3

2

1

D D

C C

PR143

68_0402_5%~D

VGATE22,29

PM_PWROK8,22,29

H_PROCHOT#4

1 2

H_PROCHOT#

0_0402_5%~D

PC148

@

1 2

0.1U_0402_10V7K~D

PM_DPRSLPVR8,22

H_DPRSTP#5,8,21

CLK_ENABLE#

@

12

PR151

@

PR157

1 2

4.22K_0402_1%~D

+3VALW

@
12

PR154 147K_0402_1%~D

1 2

PH2

@

470K_0402_5%_TSM0B474J4702RE

1 2

1 2

0.015U_0603_25V7K

PR158

10K_0402_1%~D

1 2

0_0402_5%~D

1 2

12

12

PR149

PR171

1.91K_0402_1%~D

0_0402_5%~D

PC125

0.1U_0402_16V7K~D

@

PR15240.2K_0402_1%~D

1 2

H_PROCHOT#

PC127

PR145

0_0402_5%~D

1 2

PR147 0_0402_5%~D

1 2

PR148

PU10

1
2
3
4
5
6
7
8
9

10

PR159

6.81K_0402_1%~D

PC130

12

PC129

1000P_0402_50V7K~D

1 2

1 2

PR160 464K_0402_1%~D

1 2

150P_0402_50V8J~D

B B

VCCSENSE5

VSSSENSE5

1 2

PC131 47P_0402_50V8J~D

330_0402_1%~D

1 2

1 2

PR165

0_0402_5%~D

1 2

PR168

0_0402_5%~D

PC137

330P_0402_50V7K~D

PR163

PR164

2.21K_0402_1%~D

1 2

PC135 1000P_0603_50V7K~D

12

PC136
1000P_0402_50V7K~D

12

1 2

1K_0402_1%~D

PC133

390P_0402_50V7K~D

1 2

1 2

PC138 330P_0402_50V7K~D

1 2

PR169

12

PC122

41

FDE

GND PAD
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB

1 2

PR170

9.1K_0402_1%~D

PR144
0_0402_5%~D

1 2

1U_0603_6.3V6M~D

40

39

3V3

PGOOD

VSEN12VDIFF

11

PC124

1U_0603_10V6K~D

+5VALW

PR146
1_0603_5%~D

1 2

12

+CPU_B+

12

12

12

3

D

PQ63

2

G

S

SI7686DP-T1-E3_SO8

1

PC205

2200P_0402_50V7K~D

3

D

PQ62

2

G

S

1

PC118

PC117

0.1U_0603_25V7K~D
1000P_0402_50V7K~D

12

12

12

PC119

4.7U_0805_25V6-K~D

PR155

4.7_1206_5%~D

PC128
680P_0402_50V7K~D

12

PC120

4.7U_0805_25V6-K~D

12

PR156

7.68K_0805_1%~D

VSUM

PC121

4.7U_0805_25V6-K~D

0.45UH_ETQP4LR45XFC_25A_-25+20%

PL10

HCB2012KF-121T50_0805

1 2

PL11

1 2

B+

12

12

PC146

PC147

1000P_0402_50V7K~D

1000P_0402_50V7K~D

+VCC_CORE

SI7170DP-T1-GE3-POWERPAK8-5

5

5

5

5

5

5

5

29

CPU_VID2

CPU_VID1

CPU_VID0

12

PC123

12

PR150

VR_ON

CPU_VID6

0_0402_5%~D

CPU_VID5

CPU_VID4

CPU_VID3

0.01U_0402_16V7K~D

34

36

35

37

38

17

VSUM

VIN

18

12

VID331VID432VID533VID6

30

VID2

29

VID1

28

VID0

27

VCCP

26

LGATE

25

VSSP

24

PHASE

23

UGATE

22

BOOT

21

NC

VSS

VDD

ISL6261ACRZ-T_QFN40_6X6

19

20

1 2

PR161

12

10_0603_5%~D
PC132
1U_0603_10V6K~D

PR162
10_0603_5%~D

1 2

PC134

0.22U_0603_25V7K~D

LGATE_CPU1

PHASE_CPU1
UGATE_CPU1
BOOT_CPU1

+CPU_B+

VSUM

12

1 2

2.2_0603_5%~D

+5VALW

12

PR166

3.57K_0402_1%~D

VR_ON

CLK_EN

DPRSTP#

DPRSLPVR

DFB

VO

DROOP

RTN

15

16

14

13

PR153

PC126

0.22U_0603_10V7K~D

1 2

12

1 2

0.1U_0402_10V7K~D
.068U_0402_10V7K~D

PC139

PC140

4.53K_0402_1%~D

PR167

PH3
10KB_0402_5%_ERTJ0ER103J

1 2

+VCC_CORE

A A

PC141

0.22U_0603_10V7K~D

5

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/06/23 2010/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

CPU_CORE

Thursday, September 10, 2009

1

39 43

1.0

of

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1

Request

Item Issue DescriptionDate

1 39 CPU_CORE 09' 09/09 Compal_Will Modify CPU load line PR170 change 6.65K_1%_0402 to 9.1K_1%_0402 0.5

D D

C C

Owner

Solution Description Rev.Page# Title

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-PIR

Size Document Number Rev

LA-5541P

Thursday, September 10, 2009 4340

Date: Sheet

1

of

1.0

5

4

3

2

1

Version Change List ( P. I. R. List )

Page 1/1

Request

Item Issue DescriptionDate

1

D D

2

3

19 2009/06/05 Compal Change JLVDS connect

4

24 2009/06/05 Compal Change JODD1 connect

5

17 2009/06/05 Compal Change Level sfift IC to ASMEDIA

6

16 2009/06/18 Compal reserve R1535 to using LOW POWER CLK GEN RTM890~397 0.3

7

26 2009/06/24 Compal

8

19 2009/07/08 Compal

9

30 2009/07/08 Compal

10

29,30 2009/07/08 Compal

11

25

12

C C

30

13

14

15

16

17

18

19

20

21

22

2009/06/05 0.2Compal21, 23 HDMI NO SOUND ADD R319, R320, R323, R321 DEL R322, R324, R92

2009/07/23

2009/07/23

Owner

Compal

Compal

Battery LED can't work ADD NET BAT_CHG_LED#Compal2009/06/0529, 30 0.2

reserve Q39,Q40,R1536, R1537, C1359, C1360, C1361, C1362 0.3

Del C313 D14 0.3

Add EAPD trace 0.3

Add C1363 1.0

Solution Description Rev.Page# Title

0.2

0.2

0.2

0.3DEL Y5 C1244, C1246

1.0Change Keyboard footprint

B B

23

24

25

26

27

28

29

30

31

32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

EE PIR-1

LA-5541P

1.0

of

41 43Thursday, September 10, 2009

1

5

A

4

3

2

1

ZZZ1

D D

C C

X76

U5_R3@

U3_R3@

PCB-MB

U1

PENRYN SFF_UFCBGA956

R3_SU3500@

U1

PENRYN SFF_UFCBGA956

R3_SU4100@

U1

PENRYN SFF_UFCBGA956

723@

U1

PENRYN SFF_UFCBGA956

SU4100@

U1

PENRYN SFF_UFCBGA956

R3_SU9400@

U1

PENRYN SFF_UFCBGA956

R3_SU7300@

U1

PENRYN SFF_UFCBGA956

SU3500@

U1

PENRYN SFF_UFCBGA956

SU7300@

U1

PENRYN SFF_UFCBGA956

SU9400@

B B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/04/01 2010/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BOM structure

42 43Thursday, September 10, 2009

of

1.0

A

5

4

3

2

1

+3/5VALW

ON/OFF#

ON/OFFBTN#

D D

SYSON

+1.5V

PM_RSMRST#

ICH_SUSCLK

> 110ms

SLP_S5#

programmable

SLP_S4#

C C

30~120us

SLP_S3#

SUSP#

+5VS > +3VS > +1.5VS > +VCCP

VR_ON

+CPU_CORE

B B

VGATE

CK_PWRGD

PM_PWROK

This signal is
asserted high when
both SLP_S3# and
VRMPWRGD are high

VCCP to PM_PWROK

> 99ms

VGATE to PM_PWROK

> 5ms

PM_PWROK to PLT_RST#

1.05ms~2.22ms

PLT_RST#

H_PWRGOOD

A A

H_RESET#

Title

<Title>

Size Document Number Rev

LA-5541P 1.0

Custom

5

4

3

2

Date: Sheet

of

43 43Thursday, September 10, 2009

1