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LA-5381P NSKAE Bradford 10AT
Schematic
47 pgs1.45 Mb0

Compal LA-5381P NSKAE Bradford 10AT, Satellite A500 Schematic

A
1 1
B
C
D
E
Compal confidential
2 2
Bradford 10AT
NSKAE LA-5381P REV 0.2 Schematics Document
Mobile AMD SIG3/RS880M&RS880MC/SB710
2009-04-10 Rev. 0.2
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-5381P
LA-5381P
LA-5381P
146Friday, Apri l 10, 2009
146Friday, Apri l 10, 2009
146Friday, Apri l 10, 2009
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of
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0.2
0.2
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B
C
D
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Compal Confidential
Model Name : NSKAE File Name : LA-5381P
1 1
Fan Control
page 4
AMD S1G3 CPU
uFCPGA-638 Package
page 4,5,6,7
Hyper Transport Link 2.6GHz
16X16
Display Port
page 16
CRT
page 16
LCD Conn.
page 17
ATI
RS880M
Memory BUS(DDRII)
Dual Channel
1.8V DDRII 667/800MHZ
NEW Card USB Port 11
PCIeMini Card
PCIe 4x
1.5V 2.5GHz(250MB/s)
WLAN (Slot 1) USB Port 8
ADM1032ARMZ
200pin DDRII-SO-DIMM X2
PCIe port 0
page 25
PCIe Port 2
page 27
page 6
BANK 0, 1, 2, 3
PCIe port 1
Thermal Sensor
Clock Generator
SLG8SP626
JMB380
5IN1
page 31
page 8,9
page 15
5IN1
page 31
1394
page 31
RS880MC
EC SMBUS
2 2
HDMI CEC Controller
R5F211A4SP
page 18
HDMI Conn.
page 18
page 10,11,12,13,14
A-Link Express II 4X PCI-E
ATI
FM Tuner/B LS-430GP
3 3
Touch Pad BTN/B LS-5003P
page 26
page 34
Light Pipe/B LS-4991P
Right USB/B LS-5006P
RTC CKT.
page 19
Power On/Off CKT.
page 34
DC/DC Interface CKT.
4 4
page 35
Finger Printer/B LS-5004P
Power/B LS-4992P
Cap Sensor/B LS-4993P
page 34
page 26
page 26
page 34
page 34
FM tuner Conn
page 26
I2C from SB
Debug Port
page 33
Int.KBD
page 33
LPC BUS
3.3V 33 MHz
SB710
page 20,21,22,23,24
ENE KB926 D3
page 32
SPI ROM
page 33
HD Audio
CIR
page 32
USB
5V 480MHz
SATA port 1
5V 1.5GHz(150MB/s)
SATA port 0
5V 1.5GHz(150MB/s)
SATA port 3
5V 1.5GHz(150MB/s)
SATA port 2
5V 1.5GHz(150MB/s)
USB port 2
5V 480MHz
3.3V 24.576MHz/48Mhz
MDC 1.5 Conn
GSENSOR
page 33
SATA HDD0
SSD
SATA ODD
page 24
page 24
page 24
eSATA
page 24
page 26 page 29
MIC CONN
RTL8111D/8103E LAN 1G/10/100M
PCIe port 3
PCIeMini Card GPS/TV Tuner (Slot2)
USB Port 10 USB Port 5
HDA Codec
ALC272
Int.
page 30
page 28
PCIeMini Card WUSB (Slot 3)
PCIe Port 5
page 27
USB/B Right
USB port 0,1
page 26
BT conn
USB port 6
page 26
Touch Screen conn
USB port 13
page 26
USB/B Left
USB port 4
page 24
Felica
USB port 3
page 26
AMP.
MIC CONN
page 30 page 30
HP CONN
page 30
TPA6017
LED/B
Power Circuit DC/DC
page 36,37,38,39 40,41,42,43
A
LS-4994P Left USB/B
LS-4995P
page 34
page 24
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-5381P
LA-5381P
LA-5381P
E
RJ45
page 28
BCAS
page 25
FP conn
USB port 7
Int. Camera
USB port 9
SPK CONN
page 30
246Friday, Apri l 10, 2009
246Friday, Apri l 10, 2009
246Friday, Apri l 10, 2009
PCIe Port 4
page 28
page 26
page 26
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of
of
0.2
0.2
0.2
A
B
C
D
E
Voltage Rails
1 1
State
S0
2 2
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
SB SM Bus1 Address
Power
3 3
+3VS +3VS +3VS +3VS New Card
Device
DDR SO-DIMM 0 DDR SO-DIMM 1 Clock Generator
EC SM Bus1 Address
Device Address Address
+5VL +5VL
4 4
+3VL Cap. Sensor
HDMI-CEC 34 H 0011 010X b
O MEANS ON X MEANS OFF
power plane
B+
+3VL
+5VL
+RTCVCC
O
O
O
O
O
X
+3VALW
+1.2VALW
+3V_LAN
O
O
O
O
X
XX X
+1.8V+5VALW
+0.9V
SB SM Bus2 Address
HEX
A0 H
D2 H
Address
1010 0000 b 1010 0100 bA4 H 1101 0010 b
+3VALW
+3VS Virtual I2C
DevicePower
WLAN/WIMAX
DevicePower
FM Tuner
EC SM Bus2 Address
HEX HEX
16 H
0001 011X bSmart Battery
HEXDevice AddressPower
Virtual I2C
A
PowerPower
+3VS +3VS +3VS +3VS Light Sensor
Device
VGA_ADM1032-2 G-Sensor
+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.1VS
+VGA_CORE
+1.2V_HT
+VDDNB
+CPU_CORE_0
+CPU_CORE_1
OO
OO
O
X
XX
X
98 H 9A H
B
X
HEX Address
HEX Address
1001 100X bCPU_ADM1032-1 1001 101X b
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
Item CPU SBNB VGA
S1G3 NA SB710
S1G3
RS880MC
BTO Option Table
Function
description
explain
BTO
Function
description
explain
BTO
Function
description
explain
BTO
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_CLK1
DDC_DATA1
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KB926
KB926
RS780M
RS780M
RS780M
SB700
SB700
SB700
SB700
C
New Card
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
HDMI
HDMI@ H@
MINI PCI-E SLOT
3G B-CAS WIMAX
3G@ TV@ WIMAX@
HDD PROTECT
GSENSOR@
BATT
X
V
X X X
X X
X
V
X X X
X XXX XXXXXX XXXXX
DIPLAY PORT
CEC
DP@
Modem
Modem
RJ11@
THERMAL SENSOR
CEC
CPU &
V
XXX
V
Side PortDIPLAY PORTHDMI No Side Port
SIDE@
LAN
10/100M Giga
8103EL@ 8111DL@
FM TUNERG-SENSOR
FM TUNER
FM@
SODIMM
I / IIADM1032
XX
Fingerprint
Fingerprint
CLK
X X
XXXX
VV
XX
XX
X
XX
Deciphered Date
Deciphered Date
Deciphered Date
D
Samsung Hynix
SAMSIDE@ HYNSIDE@
FP@
3G/TV
X XXXXX XXX
XX
V
X X
NA SB710RS880M
Side Port
Memory
NOSIDE@
Felica BLUETOOTH
BLUE TOOTHFELICA
FEL@
LCD
XX X
V
XXX XXXX XXX
SSD
SSD@
HDMI
X X X
V
CIR
CIR@
BT@
Display Port
X X X X
V
X X X X
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-5381P
LA-5381P
LA-5381P
E
CRT
CRT
CRT@
G-Sensor
X
V
X X X X X X X
346Friday, Apri l 10, 2009
346Friday, Apri l 10, 2009
346Friday, Apri l 10, 2009
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0.2
0.2
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1 1
B
C
D
E
+1.2V_HT
EN_DFAN1<32>
250 mil
1
C1
C1 10U_0805_10V6K
10U_0805_10V6K
2
1
2
+FAN1
C2
C2 10U_0805_10V6K
10U_0805_10V6K
+5VS
1A
1
C192
C192 10U_0805_10V6K
10U_0805_10V6K
2
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C5
C5 180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket
FAN Control Circuit
12
@
@
1SS355_SOD323-2
1SS355_SOD323-2
2
D1
10U_0805_10V6K
10U_0805_10V6K
U6
U6
1
EN
GND
2
VIN
GND
3
VOUT
GND
4
VSET
GND
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
C183
C183
8 7 6 5
1
D1
12
2
@
@
D2
D2
1
1SS355_SOD323-2
1SS355_SOD323-2
+FAN1
C9
C9 1000P_0402_50V7K
1000P_0402_50V7K
@
@
1
C6
C6 180P_0402_50V8J
180P_0402_50V8J
2
2
C8
@ C8
@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
JFAN
JFAN
@
@
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N
ACES_85204-0300N
R12
R12
12
10K_0402_5%
10K_0402_5%
FAN_SPEED1 <32>
+3VS
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
+VLDT_B
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
H_CTLOP0H_CTLIP0 H_CTLON0 H_CTLOP1 H_CTLON1H_CTLIN1
H_CADOP[0..15] H_CADON[0..15]
1 2
H_CADOP[0..15] <10> H_CADON[0..15] <10>H_CADIN[0..15]<10>
C7
C7 10U_0805_10V6K
10U_0805_10V6K
H_CLKOP0 <10> H_CLKON0 <10> H_CLKOP1 <10> H_CLKON1 <10>
H_CTLOP0 <10> H_CTLON0 <10>H_CTLIN0<10>
H_CTLON1 <10>
H_CADIP[0..15]<10>
2 2
3 3
H_CLKIP0<10> H_CLKIN0<10> H_CLKIP1<10> H_CLKIN1<10>
H_CTLIP0<10> H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>
H_CADIP[0..15] H_CADIN[0..15]
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1
H_CTLIN0 H_CTLIP1
+1.2V_HT
D1 D2 D3 D4
E3 E2 E1
F1 G3 G2 G1
H1
J1
K1
L3 L2 L1
M1
N3
N2
E5
F5
F3
F4 G5
H5
H3
H4
K3
K4
L5 M5 M3 M4
N5 P5
J3
J2
J5
K5 N1
P1 P3 P4
VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3
L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15
L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1
L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1
6090022100G_B
6090022100G_B
JCPUA
JCPUA
HT LINK
HT LINK
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
@
@
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
LA-5381P
LA-5381P
LA-5381P
446Friday, Apri l 10, 2009
446Friday, Apri l 10, 2009
446Friday, Apri l 10, 2009
of
of
E
of
0.2
0.2
0.2
A
B
C
D
E
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
AD10 AF10
AE10
AA16
D10 C10 B10
H16 T19
V22 U21 V19
T20 U19 U20 V20
N19 N20 E16 F16 Y16
P19 P20
N21 M20 N22 M19 M22
M24
K22 R21
K20 V24 K24 K19
R20 R23
R19 T22 T24
J22 J20
L20 L21
L19
L22
J21
JCPUB
JCPUB
VTT1 VTT2 VTT3 VTT4
MEMZP MEMZN
RSVD_M1 MA0_ODT0
MA0_ODT1 MA1_ODT0 MA1_ODT1
MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1
MA_CKE0 MA_CKE1
MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3
MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15
MA_BANK0 MA_BANK1 MA_BANK2
MA_RAS_L MA_CAS_L MA_WE_L
DDR_A_CLK0
DDR_A_CLK#0 DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK0
DDR_B_CLK#0 DDR_B_CLK1
DDR_B_CLK#1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
1
C10
C10
1.5P_0402_50V9C
1.5P_0402_50V9C
2
1
C11
C11
1.5P_0402_50V9C
1.5P_0402_50V9C
2
1
C14
C14
1.5P_0402_50V9C
1.5P_0402_50V9C
2
1
C15
C15
1.5P_0402_50V9C
1.5P_0402_50V9C
2
VTT5 VTT6 VTT7 VTT8 VTT9
@
@
W10 AC10 AB10 AA10 A10
Y10 W17 B18 W26
W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
+0.9V+0.9V
+MCH_REF
DDR_B_ODT0 DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_CKE0_DIMMB DDR_CKE1_DIMMB
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1DDR_A_CLK#1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
T1PAD T1PAD
T3PAD T3PAD
DDR_B_ODT0 <8> DDR_B_ODT1 <8>
DDR_CS1_DIMMB# <8>
DDR_CKE0_DIMMB <8> DDR_CKE1_DIMMB <8>
DDR_B_CLK0 <8> DDR_B_CLK#0 <8> DDR_B_CLK1 <8> DDR_B_CLK#1 <8>
DDR_B_BS#0 <8> DDR_B_BS#1 <8> DDR_B_BS#2 <8>
DDR_B_RAS# <8> DDR_B_CAS# <8> DDR_B_WE# <8>
1 1
2 2
R1
R1
1K_0402_1%
1K_0402_1%
R2
R2
1K_0402_1%
1K_0402_1%
+1.8V
1 2
1 2
+MCH_REF
1
C12
C12
2
1
C13
C13
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1000P_0402_50V7K
1000P_0402_50V7K
Place them close to CPU within 1"
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
+1.8V
DDR_A_ODT0<9> DDR_A_ODT1<9>
DDR_CS0_DIMMA#<9> DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <8>
DDR_CKE0_DIMMA<9> DDR_CKE1_DIMMA<9>
DDR_A_CLK0<9>
DDR_A_CLK#0<9>
DDR_A_CLK1<9>
DDR_A_CLK#1<9>
3 3
DDR_A_MA[15..0]<9> DDR_B_MA[15..0] <8>
DDR_A_BS#0<9> DDR_A_BS#1<9> DDR_A_BS#2<9>
DDR_A_RAS#<9> DDR_A_CAS#<9> DDR_A_WE#<9>
1 2
R3 39.2_0402_1%R3 39.2_0402_1%
MEM_P MEM_N VTT_SENSE
T2 PADT2 PAD
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_B_D[63..0]<8>
DDR_B_DM[7..0]<8> DDR_A_DM[7..0] <9>
DDR_B_DQS0<8> DDR_B_DQS#0<8> DDR_B_DQS1<8> DDR_B_DQS#1<8> DDR_B_DQS2<8> DDR_B_DQS#2<8> DDR_B_DQS3<8> DDR_B_DQS#3<8> DDR_B_DQS4<8> DDR_B_DQS#4<8> DDR_B_DQS5<8> DDR_B_DQS#5<8> DDR_B_DQS6<8> DDR_B_DQS#6<8> DDR_B_DQS7<8> DDR_B_DQS#7<8>
Processor DDR2 Memory Interface
JCPUC
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
JCPUC
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23
G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11 AE14 AF14 AF11 AD11
A12
B16
A22
E25 AB26 AE22 AC16 AD12
C12
B12
D16
C16
A24
A23
F26
E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
6090022100G_B @
6090022100G_B @
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MEM:DATA
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] <9>
DDR_A_DQS0 <9> DDR_A_DQS#0 <9> DDR_A_DQS1 <9> DDR_A_DQS#1 <9> DDR_A_DQS2 <9> DDR_A_DQS#2 <9> DDR_A_DQS3 <9> DDR_A_DQS#3 <9> DDR_A_DQS4 <9> DDR_A_DQS#4 <9> DDR_A_DQS5 <9> DDR_A_DQS#5 <9> DDR_A_DQS6 <9> DDR_A_DQS#6 <9> DDR_A_DQS7 <9> DDR_A_DQS#7 <9>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
LA-5381P
LA-5381P
LA-5381P
546Friday, Apri l 10, 2009
546Friday, Apri l 10, 2009
546Friday, Apri l 10, 2009
of
of
E
of
0.2
0.2
0.2
A
B
C
D
E
L1
+2.5VS
C16
C16
@
100U_B2_6.3VM_R45M
100U_B2_6.3VM_R45M
1 1
CLK_CPU_BCLK<15>
CLK_CPU_BCLK#<15>
+1.8VS
R15
R15 300_0402_5%
300_0402_5%
1 2
LDT_RST#<19> CPU_VDDNB_RUN_FB_H <43>
2 2
H_PWRGD<19,43>
LDT_STOP#<11,19>
3 3
LDT_RST#
1
C22
C22
0.01U_0402_25V7K
0.01U_0402_25V7K
@
@
2
+1.8VS
R21
R21 300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C23
C23
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+1.8VS
R36
R36 300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C25
C25
0.01U_0402_25V7K
0.01U_0402_25V7K
2
@
@
Place close to CPU wihtin 1.5"
+CPU_CORE_0
+CPU_CORE_1
@
1 2
C20
C20
1 2
C21 3900P_0402_50V7KC21 3900P_0402_50V7K
R487 10_0402_5%R487 10_0402_5%
1 2 1 2
R486 10_0402_5%R486 10_0402_5%
Close to CPU
R489 10_0402_5%@R489 10_0402_5%@
1 2 1 2
R488 10_0402_5%@R488 10_0402_5%@
Un-Mount R27 For Caspian
CPU_LDT_REQ#_R
L1
1 2
FBM_L11_201209_300L_0805
FBM_L11_201209_300L_0805
1
+
+
2
3900P_0402_50V7K
3900P_0402_50V7K
12
R8
R8 169_0402_1%
169_0402_1%
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
R27
R27
1 2
0_0402_5%
0_0402_5%
@
@
Thermal Sensor
+3VS
1
C26
C26
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C27
C27
4 4
1 2
THERMDA_CPU THERMDC_CPU
2200P_0402_50V7K
2200P_0402_50V7K
U2
U2
1
VDD
2
D+
3
D­THERM#4GND
ADM1032ARM-1 ZREEL_MSOP8
ADM1032ARM-1 ZREEL_MSOP8
SCLK
SDATA
ALERT#
8 7 6 5
+2.5VDDA
3300P_0402_50V7K
3300P_0402_50V7K
1
C174.7U_0805_10V4Z C174.7U_0805_10V4Z
2
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
R13 44.2_0402_1%R13 44.2_0402_1% R14 44.2_0402_1%R14 44.2_0402_1%
+1.2V_HT
CPU_VDD0_RUN_FB_H<43> CPU_VDD0_RUN_FB_L<43>
CPU_VDD1_RUN_FB_H<43> CPU_VDD1_RUN_FB_L<43>
+1.8VS
R30
R30 300_0402_5%
300_0402_5%
1 2
1
C24
C24
0.01U_0402_25V7K
0.01U_0402_25V7K
@
@
2
EC_SMB_CK2 <32,33,34> EC_SMB_DA2 <32,33,34>
1
1
C18
C18
2
2
1 2 1 2
CPU_LDT_REQ# <11,19>
C19
C19
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1 2
VDDA=300mA
LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ#_R
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD T19 PADT19 PAD
CPU_TEST23_TSTUPD
T29 PADT29 PAD T30 PADT30 PAD
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1
T31 PADT31 PAD T25 PADT25 PAD T26 PADT26 PAD
R25
R25
0_0402_5%
0_0402_5%
R493
R493
1 2
510_0402_5%
510_0402_5%
R497
1 2
510_0402_5%
510_0402_5%
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
6090022100G_B @
6090022100G_B @
KEY1 KEY2
SVC SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC THERMDA
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
Add R497 and R498 at PVT
CPU_TEST25_H_BYPASSCLK_H
@R497
@
CPU_TEST25_L_BYPASSCLK_L
M11 W18
CPU_SVC
A6
CPU_SVD
A4
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7 AA8
W7 W8
W9 Y9
H6 G6
E10 AE9
J7 H8
D7 E7 F7 C7
C3 K8
C4
C9 C8
H18 H19 AA7 D5 C5
1 2
510_0402_5%
510_0402_5% R492
R492
1 2
510_0402_5%
510_0402_5%
R42 300_0402_5%@ R42 300_0402_5%@
THERMDC_CPU THERMDA_CPU
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N
CPU_TEST17_BP3 CPU_TEST16_BP2
CPU_TEST10_ANALOGOUT
Add R32 at PVT
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
+1.8V
R498
@R498
@
CPU_SVC <43> CPU_SVD <43>
12
T22PAD T22PAD T21PAD T21PAD
T20PAD T20PAD
T27PAD T27PAD T28PAD T28PAD
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
+1.8V
+1.8V
CPU_VDDNB_RUN_FB_L <43>
T7PAD T7PAD T8PAD T8PAD
R32
R32
300_0402_5%
300_0402_5%
@
@
CPU_DBREQ#
1 2
R10 10K_0402_5%R10 10K_0402_5%
1 2
R5 300_0402_5%R5 300_0402_5%
CPU_THERMTRIP#_R
1 2
+1.8V
R9 300_0402_5%R9 300_0402_5%
CPU_PROCHOT#_1.8
route as differential
T5PAD T5PAD
as short as possible
T6PAD T6PAD
testpoint under package
12
+1.2V_HT
T13PAD T13PAD T14PAD T14PAD
+1.8V
R39220_0402_5%@ R39220_0402_5%@
R38220_0402_5%@ R38220_0402_5%@
R37220_0402_5%@ R37220_0402_5%@
R40220_0402_5%@ R40220_0402_5%@
12
12
12
12
B
B
2
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R11
@R11
@
1 2
0_0402_5%
0_0402_5%
CPU_SVC CPU_SVD
CPU_TEST21_SCANEN CPU_TEST24_SCANCLK1 CPU_TEST20_SCANCLK2 CPU_TEST23_TSTUPD
R41300_0402_5% R41300_0402_5%
HDT Connector
12
@
@
R494 0_0402_5%
R494 0_0402_5%
1 2
T23 PADT23 PAD
T24 PADT24 PAD
D12 CH751H-40PT_SOD323-2D12 CH751H-40PT_SOD323-2
D16 CH751H-40PT_SOD323-2D16 CH751H-40PT_SOD323-2
Q3
Q3
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
JP3 @
JP3 @
1 3 5 7 9 11 13 15 17 19 21
SAMTEC_ASP-68200-07
SAMTEC_ASP-68200-07
21
21
R484 10_0402_5%R484 10_0402_5%
1 2 1 2
R485 10_0402_5%R485 10_0402_5%
Close to CPU
R22 1K_0402_5%R22 1K_0402_5%
1 2
R23 1K_0402_5%R23 1K_0402_5%
1 2
R26 300_0402_5%R26 300_0402_5%
1 2
R28 300_0402_5%R28 300_0402_5%
12
R31 300_0402_5%R31 300_0402_5%
1 2
R29 300_0402_5%R29 300_0402_5%
12
2 4 6
8 10 12 14 16 18 20 22 2423 26
LDT_RST#
ENTRIP2 <37,39>
H_THERMTRIP# <20>
H_PROCHOT# <19>
+VDDNB
+1.8VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
LA-5381P
LA-5381P
LA-5381P
646Friday, Apri l 10, 2009
646Friday, Apri l 10, 2009
646Friday, Apri l 10, 2009
of
of
E
of
0.2
0.2
0.2
A
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
1
+
+
C30
1 1
C30 330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
+
+
C28
C28 330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
+CPU_CORE_0
C42
C42 180P_0402_50V8J
180P_0402_50V8J
1
C35
C35 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
1
C32
C32 22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE_0
1
C40
C40
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2 2
1
C33
C33 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C41
C41
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C34
C34 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
2
VDDIO decoupling.
+1.8V
1
C46
C46 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C47
C47 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C48
C48
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
1
C49
C49
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
+CPU_CORE_1
+CPU_CORE_1
1
C36
C36 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C50
C50
180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C31
C31 330U_X_2VM_R6M
330U_X_2VM_R6M
2
+CPU_CORE_1
1
C51
C51 180P_0402_50V8J
180P_0402_50V8J
2
1
C37
C37 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C43
C43
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C
JCPUE
G4 H2
J9 J11 J13 J15
K6 K10 K12 K14
L4 L7
L9 L11 L13 L15
M2 M6 M8
M10
N7 N9
N11
K16
M16
P16 T16 V16
H25
J17 K18 K21 K23 K25 L17
M18 M21 M23 M25 N17
6090022100G_B
6090022100G_B
Athlon 64 S1 Processor Socket
@
@
JCPUE
VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23
VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12
1
+
+
C29
C29 330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C38
C38 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C44
C44
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C39
C39 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C45
C45 180P_0402_50V8J
180P_0402_50V8J
2
+CPU_CORE_0
+VDDNB
+1.8V
+CPU_CORE_NB decoupling.
+VDDNB
1
C52
C52 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C53
C53 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C54
C54 22U_0805_6.3V6M
22U_0805_6.3V6M
2
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
D
JCPUF
JCPUF
AA4
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
+CPU_CORE_1
+1.8V
AA11 AA13 AA15 AA17 AA19
AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21
AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23
AB2 AB7 AB9
AD6 AD8
B11 B13 B15 B17 B19 B21 B23 B25
D11 D13 D15 D17 D19 D21 D23 D25
H21 H23
B4 B6 B8 B9
D6 D8 D9
E4
F2 F11 F13 F15 F17 F19 F21 F23 F25
H7 H9
J4
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65
6090022100G_B
6090022100G_B
Athlon 64 S1 Processor Socket
@
@
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
E
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
3 3
4 4
+1.8V
1
C55
C55
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C60
C60
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.8V
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C56
C56
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C61
C61
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C75
C75
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
2
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
2
C57
C57
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C62
C62 180P_0402_50V8J
180P_0402_50V8J
2
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C58
C58
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C63
C63 180P_0402_50V8J
180P_0402_50V8J
2
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C64
C64 180P_0402_50V8J
180P_0402_50V8J
2
1
+
+
C78
C78 220U_B2_4VM_R45M
220U_B2_4VM_R45M
@
@
2
1
C65
C65 180P_0402_50V8J
180P_0402_50V8J
2
VTT decoupling.
+0.9V
1
C66
C66
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+0.9V
1
C79
C79
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C67
C67
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C80
C80
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C68
C68
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C81
C81
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+0.9V
1
+
+
C59
C59 220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
1
C69
C69
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C70
C70 1000P_0402_50V7K
1000P_0402_50V7K
2
Near CPU Socket Right side
1
C82
C82
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C83
C83 1000P_0402_50V7K
1000P_0402_50V7K
2
1
C71
C71 1000P_0402_50V7K
1000P_0402_50V7K
2
1
C84
C84 1000P_0402_50V7K
1000P_0402_50V7K
2
1
C72
C72 180P_0402_50V8J
180P_0402_50V8J
2
1
C85
C85 180P_0402_50V8J
180P_0402_50V8J
2
1
C73
C73 180P_0402_50V8J
180P_0402_50V8J
2
1
C86
C86 180P_0402_50V8J
180P_0402_50V8J
2
Near CPU Socket Left side
Security Classification
Security Classification
Between CPU Socket and DIMM
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
LA-5381P
LA-5381P
LA-5381P
746Friday, April 10, 2009
746Friday, April 10, 2009
746Friday, April 10, 2009
of
of
E
of
0.2
0.2
0.2
A
B
C
D
E
+1.8V
+V_DDR_MCH_REF<9>
1
1 1
2 2
3 3
4 4
2
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5> DDR_B_WE#<5>
DDR_B_CAS#<5> DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
SMB_CK_DAT0<9,15,20,25> SMB_CK_CLK0<9,15,20,25>
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
C104
C104
DDR_B_D2 DDR_B_D3
DDR_B_D8
1000P_0402_50V7K
1000P_0402_50V7K
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_CS1_DIMMB#
DDR_B_ODT1 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D47 DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7 DDR_B_D58
DDR_B_D59 SMB_CK_DAT0
SMB_CK_CLK0
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C119
C119
1
2
JDDRH
JDDRH
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
P-TWO_A5692B-A0G16-P@
P-TWO_A5692B-A0G16-P@
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0
CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD
BA1
RAS#
S0#
VDD ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1
CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
SA1
NC
A11
A7 A6
A4 A2 A0
NC
+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_B_D4 DDR_B_D5
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D13 DDR_B_DM1 DDR_B_CLK0
DDR_B_CLK#0 DDR_B_D14
DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_ODT0 DDR_B_MA13
DDR_B_D36 DDR_B_D37
DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D52
DDR_B_CLK1 DDR_B_CLK#1
DDR_B_DM6 DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
+3VS
DDR_B_CLK0 <5> DDR_B_CLK#0 <5>
DDR_CKE1_DIMMB <5>
DDR_B_BS#1 <5> DDR_B_RAS# <5> DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_B_CLK1 <5> DDR_B_CLK#1 <5>
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>
DDR_B_MA[0..15] <5>
DDR_B_DQS#[0..7] <5>
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS#
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_MA15 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_CKE1_DIMMB
DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9
DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5
DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE#
DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0
RP8
RP8
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP9
RP9
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP10
RP10
47_0804_8P4R_5%
47_0804_8P4R_5%
RP11
RP11
47_0804_8P4R_5%
47_0804_8P4R_5%
RP12
RP12
47_0804_8P4R_5%
47_0804_8P4R_5%
RP13
RP13
47_0804_8P4R_5%
47_0804_8P4R_5%
RP14
RP14
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
+0.9V
C105 0.1U_0402_16V4ZC105 0.1U_0402_16V4Z
1 2
C106 0.1U_0402_16V4ZC106 0.1U_0402_16V4Z
C108 0.1U_0402_16V4ZC108 0.1U_0402_16V4Z
1 2
C107 0.1U_0402_16V4ZC107 0.1U_0402_16V4Z
18
C109 0.1U_0402_16V4ZC109 0.1U_0402_16V4Z
27 36
1 2
C110 0.1U_0402_16V4ZC110 0.1U_0402_16V4Z
45
18
C111 0.1U_0402_16V4ZC111 0.1U_0402_16V4Z
27
1 2
36
C112 0.1U_0402_16V4ZC112 0.1U_0402_16V4Z
45
18
C114 0.1U_0402_16V4ZC114 0.1U_0402_16V4Z
27
1 2
36
C113 0.1U_0402_16V4ZC113 0.1U_0402_16V4Z
45
18
C116 0.1U_0402_16V4ZC116 0.1U_0402_16V4Z
27 36
1 2
C115 0.1U_0402_16V4ZC115 0.1U_0402_16V4Z
45
C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z
1 2
C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z
+1.8V
12
12
12
12
12
12
12
DIMM0 STD H:9.2mm (Bot)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
DDRII SO-DIMM 0
DDRII SO-DIMM 0
DDRII SO-DIMM 0
LA-5381P
LA-5381P
LA-5381P
846Friday, April 10, 2009
846Friday, April 10, 2009
846Friday, April 10, 2009
of
of
E
of
0.2
0.2
0.2
A
B
C
D
E
JDDRL
+V_DDR_MCH_REF
DDR_A_D0 DDR_A_D1
1 1
2 2
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5> DDR_A_WE#<5>
DDR_A_CAS#<5> DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
3 3
SMB_CK_DAT0<8,15,20,25> SMB_CK_CLK0<8,15,20,25>
4 4
+3VS
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D20 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
DDR_A_ODT1 DDR_A_D32
DDR_A_D33 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D34
DDR_A_D35 DDR_A_D40
DDR_A_D41 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D58
DDR_A_D59 SMB_CK_DAT0
SMB_CK_CLK0
1
C103
C103
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
JDDRL
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
PTI_A5652D-A0G16-P@
PTI_A5652D-A0G16-P@
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0
CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
VDD
VDD
BA1 RAS#
VDD ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1
CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
SA1
NC
A11
A7 A6
A4 A2 A0
S0#
NC
+1.8V+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_A_D4 DDR_A_D5
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D12
DDR_A_D13 DDR_A_DM1 DDR_A_CLK0
DDR_A_CLK#0 DDR_A_D14
DDR_A_D15
DDR_A_D21
DDR_A_DM2 DDR_A_D22
DDR_A_D23 DDR_A_D28
DDR_A_D29 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D30
DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7 DDR_A_MA6
DDR_A_MA4 DDR_A_MA2
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_ODT0 DDR_A_MA13
DDR_A_D36 DDR_A_D37
DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D47 DDR_A_D52
DDR_A_D53 DDR_A_CLK1
DDR_A_CLK#1 DDR_A_DM6 DDR_A_D54
DDR_A_D55 DDR_A_D60
DDR_A_D61 DDR_A_DQS#7
DDR_A_DQS7 DDR_A_D62
DDR_A_D63
DDR_A_D[0..63]
DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_CLK0 <5> DDR_A_CLK#0 <5>
+V_DDR_MCH_REF
1
C95
C95
2
1000P_0402_50V7K
1000P_0402_50V7K
DDR_CKE1_DIMMA <5>
DDR_A_BS#1 <5> DDR_A_RAS# <5> DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_CLK1 <5> DDR_A_CLK#1 <5>
DDR_A_DQS[0..7] <5>
DDR_A_MA[0..15] <5>
DDR_A_DQS#[0..7] <5>
+1.8V
1
C96
C96
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D[0..63] <5>
DDR_A_DM[0..7] <5>
R43
R43 1K_0402_1%
1K_0402_1%
1 2
1 2
R44
R44 1K_0402_1%
1K_0402_1%
+V_DDR_MCH_REF <8>
DDR_A_MA6 DDR_A_MA7 DDR_A_MA14 DDR_A_MA11
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1
DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#
DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA#
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
+0.9V
RP1
RP1
1 8 2 7 3 6 4 5
RP2
RP2
18 27 36 45
RP3
RP3
1 8 2 7 3 6 4 5
RP4
RP4
18 27 36 45
RP5
RP5
18 27 36 45
RP6
RP6
18 27 36 45
RP7
RP7
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
1 2
C87 0.1U_0402_16V4ZC87 0.1U_0402_16V4Z
1 2
C88 0.1U_0402_16V4ZC88 0.1U_0402_16V4Z
1 2
C90 0.1U_0402_16V4ZC90 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4ZC89 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4ZC91 0.1U_0402_16V4Z
1 2
C92 0.1U_0402_16V4ZC92 0.1U_0402_16V4Z
1 2
C93 0.1U_0402_16V4ZC93 0.1U_0402_16V4Z
1 2
C94 0.1U_0402_16V4ZC94 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4ZC98 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4ZC97 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4ZC100 0.1U_0402_16V4Z
1 2
C99 0.1U_0402_16V4ZC99 0.1U_0402_16V4Z
1 2
C102 0.1U_0402_16V4ZC102 0.1U_0402_16V4Z
1 2
C101 0.1U_0402_16V4ZC101 0.1U_0402_16V4Z
+1.8V
Security Classification
Security Classification
DIMM0 STD H:5.2mm (Bot)
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
LA-5381P
LA-5381P
LA-5381P
946Friday, Apri l 10, 2009
946Friday, Apri l 10, 2009
946Friday, Apri l 10, 2009
of
of
E
of
0.2
0.2
0.2
A
1 1
B
C
D
E
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
2 2
PCIE_PTX_C_IRX_P0<25> PCIE_PTX_C_IRX_N0<25> PCIE_PTX_C_IRX_P1<31> PCIE_PTX_C_IRX_N1<31> PCIE_PTX_C_IRX_P2<27> PCIE_PTX_C_IRX_N2<27> PCIE_PTX_C_IRX_P3<28> PCIE_PTX_C_IRX_N3<28> PCIE_PTX_C_IRX_P4<27> PCIE_PTX_C_IRX_N4<27> PCIE_PTX_C_IRX_P5<27> PCIE_PTX_C_IRX_N5<27>
SB_RX0P<19> SB_RX0N<19> SB_RX1P<19> SB_RX1N<19> SB_RX2P<19> SB_RX2N<19>
3 3
SB_RX3P<19> SB_RX3N<19>
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS880M_FCBGA528
RS880M_FCBGA528
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
RS780MN@
RS780MN@
HDMI_TXD2+
A5
HDMI_TXD2-
B5
HDMI_TXD1+
A4
HDMI_TXD1-
B4
HDMI_TXD0+
C3
HDMI_TXD0-
B2
HDMI_CLK0+
D1
HDMI_CLK0-
D2
DP_L0+
E2
DP_L0-
E1
DP_L1+
F4
DP_L1-
F3
DP_L2+
F1
DP_L2-
F2
DP_L3+
H4
DP_L3-
H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
PCIE_ITX_PRX_P0
AC1
PCIE_ITX_PRX_N0
AC2
PCIE_ITX_PRX_P1
AB4
PCIE_ITX_PRX_N1
AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2
PCIE_ITX_PRX_P4
Y4
PCIE_ITX_PRX_N4
Y3
PCIE_ITX_PRX_P5
V1
PCIE_ITX_PRX_N5
V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
R55 1.27K_0402_1%R55 1.27K_0402_1%
AC8
R56 2K_0402_1%R56 2K_0402_1%
AB8
RS880M Display Port Support (muxed on GFX)
DP0
DP1
C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K C156 0.1U_0402_16V7KC156 0.1U_0402_16V7K C157 0.1U_0402_16V7KC157 0.1U_0402_16V7K C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K C199 0.1U_0402_16V7KC199 0.1U_0402_16V7K C200 0.1U_0402_16V7KC200 0.1U_0402_16V7K C160 0.1U_0402_16V7KC160 0.1U_0402_16V7K C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K
C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K
1 2 1 2
HDMI_TXD2+ <18> HDMI_TXD2- <18> HDMI_TXD1+ <18> HDMI_TXD1- <18> HDMI_TXD0+ <18> HDMI_TXD0- <18> HDMI_CLK0+ <18> HDMI_CLK0- <18> DP_L0+ <16> DP_L0- <16> DP_L1+ <16> DP_L1- <16> DP_L2+ <16> DP_L2- <16> DP_L3+ <16> DP_L3- <16>
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
+1.1VS
PCIE_ITX_C_PRX_P0 <25> PCIE_ITX_C_PRX_N0 <25> PCIE_ITX_C_PRX_P1 <31> PCIE_ITX_C_PRX_N1 <31> PCIE_ITX_C_PRX_P2 <27> PCIE_ITX_C_PRX_N2 <27> PCIE_ITX_C_PRX_P3 <28> PCIE_ITX_C_PRX_N3 <28> PCIE_ITX_C_PRX_P4 <27> PCIE_ITX_C_PRX_N4 <27> PCIE_ITX_C_PRX_P5 <27> PCIE_ITX_C_PRX_N5 <27>
SB_TX0P <19> SB_TX0N <19> SB_TX1P <19> SB_TX1N <19> SB_TX2P <19> SB_TX2N <19> SB_TX3P <19> SB_TX3N <19>
New Card
Card Reader
WLAN
LAN
WUSB
3G/TV Tuner
H_CLKOP0<4> H_CLKON0<4> H_CLKOP1<4> H_CLKON1<4>
H_CTLOP0<4>
H_CTLON0<4> H_CTLON1<4>
R57 301_0402_1%R57 301_0402_1%
0718 Place within 1" layout 1:2
H_CADOP[0..15]<4> H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9
H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
1 2
H_CADON[0..15]
U3A
U3A
Y25
HT_RXCAD0P
Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25
AB25 AB24 AA24 AA25
Y22
Y23 W21 W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23
R21
R20
C23
A24
RS880M_FCBGA528 RS780MN@
RS880M_FCBGA528 RS780MN@
HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
PART 1 OF 6
PART 1 OF 6
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_TXCALP HT_TXCALN
H_CADIP[0..15] <4>
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H_CLKIP0
H24
H_CLKIN0
H25
H_CLKIP1
L21
H_CLKIN1
L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
R58 301_0402_1%R58 301_0402_1%
B24 B25
1 2
0718 Place within 1" layout 1:2
H_CLKIP0 <4> H_CLKIN0 <4> H_CLKIP1 <4> H_CLKIN1 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
H_CTLIP1 <4>H_CTLOP1<4>
H_CTLIN1 <4>
4 4
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
LA-5381P
LA-5381P
LA-5381P
10 46Friday, April 10, 2009
10 46Friday, April 10, 2009
10 46Friday, April 10, 2009
of
of
E
of
0.2Custom
0.2Custom
0.2Custom
A
+3VS
1 1
+1.8VS
L2
L2
1 2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
L4
L4
0_0603_5%
0_0603_5%
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C172
C172
C170
C170
1
2
+AVDD1
1
2
+AVDD2
1
C198
C198
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
B
1 2
R62 140_0402_1%R62 140_0402_1%
1 2
R63 150_0402_1%R63 150_0402_1%
1 2
R64 150_0402_1%R64 150_0402_1%
C
CRT_R CRT_G CRT_B
D
+VDDLTP18
+VDDLT18
C173
C173
0.1U_0402_16V4Z
0.1U_0402_16V4Z
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C171
C171
2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
C174
C174
2
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
E
L3
L3
1 2
L5
L5
1 2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+1.8VS
+1.8VS
+1.8VS
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
2 2
+1.1VS
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+1.8VS +VDDA18HTPLL
BLM18PG121SN1D_0603
3 3
4 4
BLM18PG121SN1D_0603
+1.8VS +VDDA18PCIEPLL
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+1.8VS
1 2
R371 300_0402_5%R371 300_0402_5%
1 2
1 2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1 2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
L10
L10
1 2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
L11
L11
1 2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
L6
L6
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
L9
L9
C178
C178
L7
L7
C176
C176
C179
C179
C180
C180
NB_PWRGD
C175
C175
1
2
+NB_PLLVDD
1
2
1
2
1
2
1
2
+AVDDQ
+NB_HTPVDD+1.8VS
PLT_RST#<14,19,25,27,28,31,32,33>
R71
R71
4.7K_0402_5%
4.7K_0402_5%
R72
R72
4.7K_0402_5%
4.7K_0402_5%
+1.1VS
R67 0_0402_5%R67 0_0402_5%
1 2 12
UMA_CRT_CLK<16> UMA_CRT_DATA<16>
1 2
CLK_SBLINK_BCLK<15> CLK_SBLINK_BCLK#<15>
LCD_EDID_CLK<17>
LCD_EDID_DATA<17>
+AVDD1 +AVDD2 +AVDDQ
CRT_R<16> CRT_G<16> CRT_B<16>
CRT_HSYNC<14,16> CRT_VSYNC<14,16>
R65 715_0402_1%R65 715_0402_1%
+NB_PLLVDD +NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
NB_PWRGD<20>
LDT_STOP#<6,19>
CPU_LDT_REQ#<6,19>
CLK_NBHT<15> CLK_NBHT#<15>
NB_OSC_14.318M<15>
NBGFX_CLK<15> NBGFX_CLK#<15>
HDMIDAT_UMA<18> HDMICLK_UMA<18>
DP_AUXP<16> DP_AUXN<16>
+3VS
R88 10K_0402_5%
R88 10K_0402_5%
R104 150_0402_1%
R104 150_0402_1%
AVDD=100mA
1 2
CLK_SBLINK_BCLK CLK_SBLINK_BCLK#
@
@
DP@
DP@
12
UMA_CRT_CLK UMA_CRT_DATA
NB_RESET# NB_PWRGD LDT_STOP# CPU_LDT_REQ#
CLK_NBHT CLK_NBHT#
NB_OSC_14.318M
NBGFX_CLK NBGFX_CLK#
LCD_EDID_CLK LCD_EDID_DATA HDMIDAT_UMA HDMICLK_UMA DP_AUXP DP_AUXN
12
AUX_CAL
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS880M_FCBGA528
RS880M_FCBGA528
PART 3 OF 6
PART 3 OF 6
TXOUT_L2N(DBG_GPIO0) TXOUT_L3N(DBG_GPIO2)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
SUS_STAT#(PWM_GPIO5)
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L3P(NC)
TXOUT_U0P(NC) TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
THERMALDIODE_P THERMALDIODE_N
TESTMODE
RS780MN@
RS780MN@
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
+VDDLTP18
A13 B13
+VDDLT18
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
UMA_ENVDD
E9
UMA_ENBKL
F7 G12
UMA_ENBKL
D9 D10
D12 AE8
AD8 D13
R73 100K_0402_5%R73 100K_0402_5%
HPD_NB DP_HPD_R
SUS_STAT#
1 2
R80 1.8K_0402_5%R80 1.8K_0402_5%
T4PAD T4PAD
LCD_TXOUT0+ <17> LCD_TXOUT0- <17> LCD_TXOUT1+ <17> LCD_TXOUT1- <17> LCD_TXOUT2+ <17> LCD_TXOUT2- <17>
LCD_TZOUT0+ <17> LCD_TZOUT0- <17> LCD_TZOUT1+ <17> LCD_TZOUT1- <17> LCD_TZOUT2+ <17> LCD_TZOUT2- <17>
LCD_TXCLK+ <17> LCD_TXCLK- <17> LCD_TZCLK+ <17> LCD_TZCLK- <17>
12
R78 0_0402_5%R78 0_0402_5%
1 2
 0_0402_5% 0_0402_5%
1 2
Strap pin
UMA_ENVDD <17> UMA_ENBKL <32>
SUS_STAT# <14,20>
HPD <18,20> DP_HPD <16>
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
LA-5381P
LA-5381P
LA-5381P
11 46Frid ay, April 10, 2009
11 46Frid ay, April 10, 2009
11 46Frid ay, April 10, 2009
of
of
E
of
0.2
0.2
0.2
2
1
220 ohm @ 100MHz,2A
L24
L24
1 2
SIDE@
1
SIDE@
SIDE@
C213
C213
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SIDE@
SIDE@
C281
C281
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE@
SIDE@
C282
C282
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE@
SIDE@
C280
C280
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SIDE@
SIDE@
C255
C255
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SIDE@
SIDE@
C610
C610 1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
SIDE@
SIDE@
C611
C611 1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
+1.8V_MEM_VDDQ
1
2
B B
A A
1
2
+1.8V_MEM_VDDQ
1
2
1
2
SIDE@
SIDE@
R98
R98 1K_0402_1%
1K_0402_1%
1 2
+MEM_VREF
SIDE@
SIDE@
R121
R121 1K_0402_1%
1K_0402_1%
1 2
SIDE@
SIDE@
R120
R120 1K_0402_1%
1K_0402_1%
1 2
+MEM_VREF1
SIDE@
SIDE@
R113
R113 1K_0402_1%
1K_0402_1%
1 2
1
SIDE@
SIDE@
C284
C284
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SIDE@
1
SIDE@
SIDE@
C205
C205 22U_0805_6.3V6M
22U_0805_6.3V6M
2
+1.8V_MEM_VDDQ
+1.8VS+1.8V_MEM_VDDQ
0_0805_5%
0_0805_5%
R123
SIDE@ R123
SIDE@
SIDE@ R124
SIDE@
MEM_COMP_P and MEM_ COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions
R124
40.2_0402_1%
40.2_0402_1%
12
40.2_0402_1%
40.2_0402_1%
12
@
@
12
R122
R122 100_0402_1%
100_0402_1%
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12
MEM_BA0 MEM_BA1 MEM_BA2
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT
MEM_CLKP MEM_CLKN
MEM_COMP_P
MEM_COMP_N
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14
AD16 AE17 AD17
W12
Y12 AD18 AB13 AB18
V14 V15
W14
AE12 AD12
MEM_BA0 MEM_BA1
MEM_A12 MEM_A11 MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0
MEM_CLKN MEM_CLKP
MEM_CKE
MEM_CS# MEM_WE# MEM_RAS# MEM_CAS# MEM_DM0
MEM_DM1
MEM_ODT
MEM_DQS_P0 MEM_DQS_N0
MEM_DQS_P1 MEM_DQS_N1
+MEM_VREF
MEM_BA2
U3D
U3D
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
L2 L3
R2
P7
M2
P3 P8
P2 N7 N3 N8 N2 M7 M3 M8
K8
J8
K2
L8
K3
K7
L7
F3
B3
K9
F7
E8
B7
A8
J2
A2
E2
L1 R3 R7 R8
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
RS880M_FCBGA528RS780MCR3@
RS880M_FCBGA528RS780MCR3@
U61
U61
BA0 BA1
A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
CK CK
CKE
CS WE RAS CAS LDM
UDM
ODT
LDQS LDQS
UDQS UDQS
VREF NC
NC NC NC NC NC
H5PS1G63EFR-20L_FBGA_84P
H5PS1G63EFR-20L_FBGA_84P
HYNSIDE@
HYNSIDE@
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD
VDDL
VSSDL
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS
MEM_DQ0
AA18
MEM_DQ1
AA20
MEM_DQ2
AA19
MEM_DQ3
Y19
MEM_DQ4
V17
MEM_DQ5
AA17
MEM_DQ6
AA15
MEM_DQ7
Y15
MEM_DQ8
AC20
MEM_DQ9
AD19
MEM_DQ10
AE22
MEM_DQ11
AC18
MEM_DQ12
AB20
MEM_DQ13
AD22
MEM_DQ14
AC22
MEM_DQ15
AD21
MEM_DQS_P0
Y17
MEM_DQS_N0
W18
MEM_DQS_P1
AD20
MEM_DQS_N1
AE21
MEM_DM0
W17
MEM_DM1
AE19
+1.8V_IOPLLVDD
AE23
+NB_IOPLLVDD
AE24 AD23
+MEM_VREF1
AE18
MEM_DQ15
B9
MEM_DQ11
B1
MEM_DQ13
D9
MEM_DQ12
D1
MEM_DQ8
D3
MEM_DQ10
D7
MEM_DQ9
C2
MEM_DQ14
C8
MEM_DQ3
F9
MEM_DQ7
F1
MEM_DQ1
H9
MEM_DQ6
H1
MEM_DQ5
H3
MEM_DQ0
H7
MEM_DQ4
G2
MEM_DQ2
G8
A9 C1 C3 C7 C9 E9 G1 G3 G7 G9
A1 E1 J9 M9 R1
J1 J7
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8
A3 E3 J3 N1 P9
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
1
SIDE@
SIDE@
Layout Note: 50 mil for VSSDL
C283
C283 1U_0603_10V6K
1U_0603_10V6K
2
U61 K4N1G164QE-HC20
K4N1G164QE-HC20
SA00002UH00 : Hynix SA000031O00 : Samsung
SAMSIDE@U61
SAMSIDE@
1 2
1
SIDE@
SIDE@
C261
C261
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
1 2
1
SIDE@
SIDE@
C260
C260
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
L21
L21
0_0603_5%
0_0603_5%
L13
L13
0_0603_5%
0_0603_5%
+1.8VS
+1.1VS
1
SIDE@
SIDE@
C277
C277
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
64M*16 DDR2 400MHZ
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
1
Date: Sheet
Compal Electronics, Inc.
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
LA-5381P
LA-5381P
LA-5381P
12 46Frid ay, April 10, 2009
12 46Frid ay, April 10, 2009
12 46Frid ay, April 10, 2009
of
of
of
0.2
0.2
0.2
A
1 1
2 2
3 3
+1.1VS
+1.2V_HT
+1.8VS
L16
L16
0_0805_5%
0_0805_5%
L18
L18
0_0805_5%
0_0805_5%
L19
L19
0_0805_5%
0_0805_5%
L22
L22
12
0_0805_5%
0_0805_5%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
C209
C209
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
C215
C215
10U_0805_10V6K
10U_0805_10V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2A
12
C225
C225
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2A
1
C235
C235
C246
C246
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2A
1
1
C206
C206
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C214
C214
C216
C216
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C226
C226
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C236
C236
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C208
C208
C207
C207
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C217
C217
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C227
C227
C228
C228
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C238
C238
C237
C237
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C210
C210
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHTRX
1
C218
C218
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C229
C229
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C239
C239
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS
1
C251
C251
2
+VDDHT
1
2
+VDDHTTX
1
2
+VDDA18PCIE
1
2
1 2
0_0603_5%
0_0603_5%
B
U3E
U3E
J17
VDDHT_1
K16
AE25 AD24 AC23 AB22 AA21
W19
M17
M10
AD9
AE11 AD11
1
SIDE@
SIDE@
C252
C252 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
L16 M16 P16 R16 T16
H18 G19 F20 E21 D22 B23 A23
Y20 V18
U17 T17 R17 P17
P10 K10
L10
T10 R10
AA9 AB9
AE9 U10
J10
W9
H9
Y9
F9
G9
2A
L89
L89
PART 5/6
PART 5/6
VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
RS880M_FCBGA528 RS780MN@
RS880M_FCBGA528 RS780MN@
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
2.5A
C
+VDDA11PCIE
1
C2470.1U_0402_16V4Z C2470.1U_0402_16V4Z
2
+3VS
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C211
C211 C212
C212
C220 1U_0402_6.3V4ZC220 1U_0402_6.3V4Z C219 1U_0402_6.3V4ZC219 1U_0402_6.3V4Z C222 1U_0402_6.3V4ZC222 1U_0402_6.3V4Z C221 1U_0402_6.3V4ZC221 1U_0402_6.3V4Z C224 0.1U_0402_16V4ZC224 0.1U_0402_16V4Z C223 0.1U_0402_16V4ZC223 0.1U_0402_16V4Z
+1.1VS
VDD_CORE:GM=5A/PM=10A
1
1
1
1
C2420.1U_0402_16V4Z C2420.1U_0402_16V4Z
C2410.1U_0402_16V4Z C2410.1U_0402_16V4Z
2
C2430.1U_0402_16V4Z C2430.1U_0402_16V4Z
2
2
+VDD_MEM
C2300.1U_0402_16V4Z C2300.1U_0402_16V4Z
1 2 1 2
C2400.1U_0402_16V4Z C2400.1U_0402_16V4Z
2
L17
L17
1 2 1 2 1 2 1 2
PJP3
PJP3
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1
1
C2310.1U_0402_16V4Z C2310.1U_0402_16V4Z
2
2
10U_0805_10V6K
10U_0805_10V6K 10U_0805_10V6K
10U_0805_10V6K
12 12
1
1
C2440.1U_0402_16V4Z C2440.1U_0402_16V4Z
C2320.1U_0402_16V4Z C2320.1U_0402_16V4Z
2
2
C2500.1U_0402_16V4Z C2500.1U_0402_16V4Z C2530.1U_0402_16V4Z C2530.1U_0402_16V4Z
D
U3F
U3F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
0_0402_5%
0_0402_5% R625
R625
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS880M_FCBGA528 RS780MN@
RS880M_FCBGA528 RS780MN@
1
1
1
C2861U_0402_6.3V4Z SIDE@C2861U_0402_6.3V4Z SIDE@
C2851U_0402_6.3V4Z SIDE@C2851U_0402_6.3V4Z SIDE@
C5970.1U_0402_16V4Z SIDE@C5970.1U_0402_16V4Z SIDE@
2
2
2
+1.1VS
+NB_CORE
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
1
C234
C234
1
1
C23310U_0805_10V6K C23310U_0805_10V6K
C24510U_0805_10V6K C24510U_0805_10V6K
+
+
2
2
2
12
NOSIDE@
NOSIDE@
PART 6/6
PART 6/6
1
1
C5980.1U_0402_16V4Z SIDE@C5980.1U_0402_16V4Z SIDE@
C5990.1U_0402_16V4Z SIDE@C5990.1U_0402_16V4Z SIDE@
2
2
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
L82
1 2
0_0603_5%
0_0603_5%
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
SIDE@L82
SIDE@
E
+1.8VS
4 4
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
LA-5381P
LA-5381P
LA-5381P
13 46Friday, April 10, 2009
13 46Friday, April 10, 2009
13 46Friday, April 10, 2009
of
of
E
of
0.2Custom
0.2Custom
0.2Custom
A
B
C
D
E
RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K
SI2: Change to 3K pull high
CRT_VSYNC<11,16>
1 1
12
R101 3K_0402_5%R101 3K_0402_5%
@
@
12
R102 3K_0402_5%
R102 3K_0402_5%
+3VS
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO. 1 : Enable (RX780, RS780) 0 : Disable (RX780, RS780) PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]
These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010
RS780 use register to control PCI-E configure
2 2
010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects Loading of STRAPS from EPROM
RS780 DFT_GPIO1
D4
@D4
@
SUS_STAT#<11,20>
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
PLT_RST# <11,19,25,27,28,31,32,33>
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
3 3
RS780 use HSYNC to enable SIDE PORT (internal pull high)
@
@
CRT_HSYNC<11,16>
4 4
A
12
R125 3K_0402_5%
R125 3K_0402_5%
SIDE@
SIDE@
12
R136 3K_0402_5%
R136 3K_0402_5%
+3VS
B
DFT_GPIO0: STRA P_DEBUG_BUS_PCIE_E NABLEb
RX780: Enables the Test Debug Bus using PCIE bus 1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780) 0 : Enable (RS780)
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
LA-5381P
LA-5381P
LA-5381P
14 46Friday, April 10, 2009
14 46Friday, April 10, 2009
14 46Friday, April 10, 2009
of
of
E
of
0.2Custom
0.2Custom
0.2Custom
A
B
C
D
E
+1.2V_HT
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1
+3VS_CLK
R179
R179
8.2K_0402_5%
8.2K_0402_5%
@
@
1 2
SEL_SATA
R181
R181
8.2K_0402_5%
8.2K_0402_5%
2 2
R180
R180
8.2K_0402_5%
8.2K_0402_5%
3 3
1 2
+3VS_CLK
1 2
SEL_SATA
27M_SEL
27M_SEL
+VDDCLK_IO
73
U10
U10
GND
SCL SDA VDD_DOT SRC_7#/27M SRC_7/27M_SS VSS_DOT SRC_5# SRC_5 SRC_4# SRC_4 VSS_SRC VDD_SRC_IO SRC_3# SRC_3 SRC_2# SRC_2 VDD_SRC VDD_SRC_IO
+3VS
71
72
VSS_48
48MHz_17048MHz_0
R168
R168
1 2
0_0805_5%
0_0805_5%
1*0configure as SATA outp ut configure as sing le-ended 66MHz output1
* default
configure as 27M and 27M_SS output1*
0
configure as SRC_7 output
* default
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
configure as nor mal SRC(SRC_6) output
C452
C452
C453
C453
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C454
C454
C455
C455
2
22P_0402_50V8J
22P_0402_50V8J
WUSB
SB LINK SB SRC
3G/TV Tuner
WLAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C456
C456
C457
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C464
C464
SMB_CK_CLK0<8,9,20,25> SMB_CK_DAT0<8,9,20,25>
CLK_PCIE_MCARD3#<27> CLK_PCIE_MCARD3<27>
CLK_SBLINK_BCLK#<11>
CLK_SBLINK_BCLK<11> CLK_SBSRC_BCLK# <19>
CLK_PCIE_MCARD1#<27> CLK_PCIE_MCARD1<27> CLK_PCIE_MCARD2#<27> CLK_PCIE_MCARD2<27>
C457
2
CLK_XTAL_OUT CLK_XTAL_IN
Y2
Y2
12
14.31818MHZ_20P_6X1430004201
14.31818MHZ_20P_6X1430004201
1
1
C465
C465 22P_0402_50V8J
2
22P_0402_50V8J
2
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+VDDCLK_IO
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18
R167
R167
1 2
0_0805_5%
0_0805_5%
+3VS_CLK
CLK_XTAL_OUT
CLK_XTAL_IN
67
69
68
VDD_48
XTAL_IN
XTAL_OUT
+3VS_CLK
1
C444
C444 22U_0805_6.3V6M
22U_0805_6.3V6M
2
+3VS_CLK
CLK_48M_CRUSB NB_OSC_14.318M_R
R175 33_0402_5%R175 33_0402_5%
1 2
SEL_SATA
27M_SEL
+3VS_CLK
+3VS_CLK
64
60
REF_0/SEL_HTT66
58
57
59
63
62
61
PD#
VSS_HTT
VDD_HTT
VDD_REF
HTT_0/66M_0
HTT_0#/66M_1
REF_2/SEL_27
REF_1/SEL_SATA
66
65
VSS_REF
1
C445
C445
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C458
C458
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
R174 8.2K_0402_5%R174 8.2K_0402_5%
1 2
C629 1U_0402_6.3V4ZC629 1U_0402_6.3V4Z
CLK_CPU_R_BCLK
CLK_CPU_R_BCLK#
56
55
CPU_K8_0
CPU_K8_0#
VDD_CPU
VDD_CPU_I/O
VSS_CPU CLKREQ_1# CLKREQ_2#
VDD_A VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA CLKREQ_3# CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO
1
C446
C446
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C459
C459
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R170 33_0402_5%R170 33_0402_5%
1 2
R379 158_0402_1%R379 158_0402_1%
1 2
SB_14.318M <19>
+3VS_CLK
1 2
R946 0_0402_5%R946 0_0402_5%
1 2
R945 0_0402_5%R945 0_0402_5%
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3VS_CLK +VDDCLK_IO
+3VS_CLK
+3VS_CLK
1 2
R372 10K_0402_5%R372 10K_0402_5%
+3VS_CLK +VDDCLK_IO
1
C447
C447
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C460
C460
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R186
R186 261_0402_1%
261_0402_1%
@
@
1 2
+3VS_CLK
1
C448
C448
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C461
C461
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CLK_48M_USB <20> NB_OSC_14.318M <11>
1 2
R380 90.9_0402_1%R380 90.9_0402_1%
CLK_NBHT <11> CLK_NBHT# <11>
CLK_CPU_BCLK <6>
CPU
CLK_CPU_BCLK# <6>
CLKREQ_NCARD# <25> CLKREQ_MCARD2# <27>
CLK_SBSRC_BCLK <19>
CLKREQ_MCARD1# <27>
1
C449
C449
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C450
C450
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
2
OSC_14M_NB
RS780 1.1V 158R/90.9R
Use voltage divider resistor R379 & R380 to pull low
NB
NB_OSC_14.318M
CLKREQ_NCARD# CLKREQ_MCARD2# CLKREQ_MCARD1#
*0 configure as differential 100MHz output
* default
1 2
R324 8.2K_0402_5%R324 8.2K_0402_5%
1 2
R325 8.2K_0402_5%R325 8.2K_0402_5%
1 2
R326 8.2K_0402_5%R326 8.2K_0402_5%
C451
C451 1U_0402_6.3V4Z
1U_0402_6.3V4Z
+3VS_CLK
VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0
4 4
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
33
SLG8SP626VTR_QFN72_10x10
SLG8SP626VTR_QFN72_10x10
+3VS_CLK
+VDDCLK_IO
C
NBGFX_CLK <11> NBGFX_CLK# <11>
CLK_PCIE_MCARD0 <31> CLK_PCIE_MCARD0# <31>
CLK_PCIE_LAN <28> CLK_PCIE_LAN# <28>
CLK_PCIE_NCARD <25> CLK_PCIE_NCARD# <25>
2008/04/14 2009/04/14
2008/04/14 2009/04/14
2008/04/14 2009/04/14
NB GFX
Card Reader
LAN
New Card
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
NB CLOCK INPUT TABLE
NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF 100M DIFF
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RX780 RS780
100M DIFF 100M DIFF
14M SE (1.8V) 14M SE (1.1V) NC vref
100M DIFF 100M DIFF
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Compal Electronics, Inc.
100M DIFF 100M DIFF
100M DIFF(IN/OUT)*
NC or 100M DIFF OUTPUT
Clock Generator
Clock Generator
Clock Generator
LA-5381P
LA-5381P
LA-5381P
E
0.2Custom
0.2Custom
15 46Friday, April 10, 2009
15 46Friday, April 10, 2009
15 46Friday, April 10, 2009
0.2Custom
of
of
of
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