COMPAL LA-5371P Schematics

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

Arrandale/Clarksfield

with Intel IBEX PEAK-M core logic

NIWBA

3 3

REV:0.1

4 4

Security Classification

Security Classification

Security Classification

2008/03/25 2008/04/

2008/03/25 2008/04/

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2008/03/25 2008/04/

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Compal Electronics,Ltd.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

NIWBA_LA5371P

NIWBA_LA5371P

NIWBA_LA5371P

1 52Tuesday, March 24, 2009

1 52Tuesday, March 24, 2009

E

1 52Tuesday, March 24, 2009

0.1

0.1

0.1

A

ompal confidential

C

F

ile Name :

V

RAM 64*16

1 1

DDR3*8

page20

PCI-E X16

NVidia N10M-GS

B

ZZ1

ZZ1

Z

Z

1

1

5.6W_PCB_LA5371P

5.6W_PCB_LA5371P

C

i

ntel

Arrandale/Clarksfield

(UMA/DIS) (DIS)

POWER BD

ower on X1

P
L

ED X1 (G)
:POWER
N

OVO X1

Clock Generator

ICS9LRS3199AKLFT

page12

D

lide Bar LED X 10 (B)

S
USER-DEFINED (W)
DOLBY (W)
LED X 3
WIRELESS LED (G)
B

LUETOOTH LED (G)
3G LED (G)
HDD LED (G)

E

RIGHT BD
VOLUME UP X1
V

OLUME DOWN X1
MUTE X1
MUTE LED X1(G)

Socket-rPGA989

37.5mm*37.5mm

FDI *8

page5~9

DMI *4

Dual Channel

DDR3-800(1.5V)
DDR3-1067(1.5V)

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

page 10,11

HDMI
CONN

page26

NVidia N10P-GS

switchable

graphic

page26

page19~25

level shift IC

8110T

page27

100MHz

2.7GT/s

switchable

CRT cable

page28

2 2

LVDS
Connector

page29

PCI Express
Mini card Slot 1

page30

PCI Express
Mini card Slot 2

page30

graphic

page28

switchable

graphic

page29

6*PCI-E BUS

Intel Ibex Peak M

FCBGA 951

25mm*25mm

page 13~18

AZALIA

14*USB2.0

6*SATA serial

SPK amplifier

page35

WOOFER amplifier

Audio Codec

Realtek ALC272

page35

CMOS Camera

page40

2Channel Speaker

page36

1Channel Speaker

HP X 1+
MIC_Ext X1

2Channel MIC_Int

page36

page36

page36

page36

PCI Express

SPI ROM
BIOS

page38

LPC BUS

BlueTooth CONN

page40

Mini card Slot 3

3 3

page30

USB CONN X1

page40

EC

BCM57790/57780

SIM Card

page30

10/100/1G LAN

page31

RJ45 CONN

page32

Touch Pad

4 4

A

B

ENE KB926D

page37

New Card X1

M-PCIE CONN X 3

Int.KBD

page38

page39

SPI ROM

page39

SATA HDD CONN

SATA ODD CONN

Security Classification

Security Classification

Security Classification

2008/03/24 2008/04/

2008/03/24 2008/04/

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

C

2008/03/24 2008/04/

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

page29

Realtek 5159E
MS/MS

page29

pro/SD/SD
pro/mmc/XD

page33

ESATA HDD AND USB CONN

page34

page34

page34

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

MB Block Diagram

MB Block Diagram

NIWBA_LA5371P

E

2 52Tuesday, March 24, 2009

2 52Tuesday, March 24, 2009

2 52Tuesday, March 24, 2009

0.1

0.1

0.1

A

DR3 Voltage Rails

D

power
plane

1 1

+B

State

+5VALW

+3VALW

+1.5V

B

MBUS Control Table

S

5VS

+

+3VS

+

1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+1.8VS

+0.75VS

+1.05VS

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

C

S

OURCE

KB926

+3VALW

KB926

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

D

RAM M2 BATT KE926 SODIMM CLK CHIP

X

X

V

+3VALW

X

V

3VALW

+

X

X

X

X

X

X

X

X

V V

+3VS

X

X

X

+3VS

X

V

+3VALW

N

WLAN
WWAN

X

X

X

X X

10x
Thermal
Sensor

X

X X

X

X

V

+3VS

N

10x

X

X

X

C

ap sensor

board

X

XX

X

X

V

+3VS

E

N

EW

CARD

X

X

V

+3VS

XXX X X X X X

P

CH

X

V

+3VALW

X

X

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

X

O

O

O

X

O

X X

X

OO

X

X

X X X

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

@ FUNCTION

EVT NON-USE

45@

GIGA@ 100@

3 3

ARRAY@ MONO@

S512@

H512@

S1024@

H1024@

X76@

M1@ (DDR M1 MODE)

3G@ (3G MODE)

10M@

10P@

4 4

UMA@

DIS@

(45 BOM)

(GIGA LAN)

(NON TV POWER SW)

(ARRAY MIC)

FOR X76 BOM

FOR X76 BOM

FOR X76 BOM

FOR X76 BOM

(X76 BOM)

FOR 10M CHIP

FOR 10P CHIP

FOR Auberndale

FOR Auberndale/Clarksfield

(100 LAN)

TVSW@NO_TVSW@

(TV POWER SW)

PCIE PORT LIST

DEVICEPORT

USB PORT LIST

DEVICEPORT

(MONO MIC)

1

NEW CARD
2
3
4

LAN

3G
5
6

TV TUNNER
7
8

0
1WLAN
2
3
4
5
6
7

10
11
12
13

LEFT SIDE
RIGHT SIDE
CMOS

RIGHT SIDE
CARD READER

WIRELESS8
TV TUNNER9
NEW CARD
BT

3G

VGA@ FOR NVIDIA PART

A

Security Classification

Security Classification

Security Classification

2008/03/24 2008/04/

2008/03/24 2008/04/

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

C

2008/03/24 2008/04/

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

B

B

B

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

MB Notes List

MB Notes List

NIWBA_LA5371P

E

3 52Tuesday, March 24, 2009

3 52Tuesday, March 24, 2009

3 52Tuesday, March 24, 2009

0.1

0.1

0.1

A

GPIO I/O ACTIVE Function Description

G

PIO0

GPIO1

GPIO2

1 1

GPIO3

GPIO4

N

/A

I

N

OUT

OUT

OUT

N/A

-

H

H

H

Hot plug detect for IFP link C

Panel Back-Light brightness(PWM capable)

Panel Power Enable

Panel Back-Light On/Off (PWM)

B

C

P

erformance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

P

N
128bit
1024MB
DDR3

N10P-GE
128bit
1024MB
DDR3

roducts

10P-GS

D

3.09

3.05

FBVDDQ
(

GPU+Mem)

(1.5V)(1.5V)

4.09

6.14

4.09 6.14

G
(

(W) (W)

21.07

20.97

M

PU

4) (1,5) (6)

emNVCLK

/MCLK NVVDD

(MHz)

6.67

6.73

TBD

TBD

V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(

TBD

18.25

17.34

TBD

19.17

17.25

F

2.06

2.03

BVDD

P

CI Express I/O and

(1.05V)

850 75 0.14

0.89

0.88840

PLLVDD

75 0.14

E

I/O and
PLLVDD

63 0.07

63 0.07

O

ther

(3.3V)(1.05V)(1.8V)

55 0.18

55 0.18

GPIO5

GPIO6

GPIO7

OUT

OUT

OUT

-

-

-

GPU VID0

GPU VID1

GPU VID2

N10P-LP
128bit
1024MB
DDR3

15.48

6.44

TBD

TBD

13.95

11.86

1.90

2.85

3.99

5.99

810

0.85

75 0.14

63 0.07

55 0.18

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

2 2

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

3 3

I/O

OUT

OUT

I/O

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

I/O

L

L

Thermal Catastrophic Overtemp

Thermal Alert

Memory VREF switch

L

-

-

SLI raster sync

AC power detect pin

MEM_VID orPower supply control

- Power supply control

-

-

Hot plug detect for IFP Link E

Programmable Fan Control

-

-

-

Hot plug detect for IFP Link D

-

-

-

Hot plug detect for IFP link F

SLI swap ready signal

GPU
(4) (1,5) (6)

Products

N10M-GE
64bit
512MB
DDR3

N10M-GS
64bit
512MB
DDR3

N10M-LP
64bit
512MB
DDR3

(W) (W)

13.36

14.29

8.28

Power Sequence

(+3VS)

(1.1VS)

VDD33

PEX_VDD

Mem

2.93

3.10

2.91

NVCLK
/MCLK NVVDD

(MHz)

TBD

TBD

TBD

(V) (A) (W) (A) (W)

TBD

11.89

TBD

11.53

TBD

6.60

10.70

11.53

5.61

FBVDD

0.66

0.70

0.62

FBVDDQ
(GPU+Mem)
(1.5V)(1.5V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

0.99

2.16

1.05

2.28 3.42

0.93

2.20

The ramp time for any rail must be more than 40us

PEX_VDD can ramp up any time

tNVVDD

PCI Express I/O and
(1.05V)

3.24

792 75 0.14

0.83

0.86817

3.3

782

0.82

PLLVDD

75 0.14

75 0.14

I/O and
PLLVDD

63 0.07

63 0.07

63 0.07

Other

(3.3V)(1.05V)(1.8V)

100 0.33

100 0.33

100 0.33

(+VGA_CORE)

NVVDD

GPIO5GPIO6 N10M-GS N10P-GS

GPU_VID11GPU_VID011VGA_CORE P-State

0 0.8V

0

0

0.85V

0.9V

4 4

A

12

12

0, 10

IFPAB_IOVDD

(1.8VS)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

C

FBVDDQ

Compal Secret Data

Compal Secret Data

2009/03/16 2010/03/15

2009/03/16 2010/03/15

2009/03/16 2010/03/15

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

tNV-IFPAB_IOVDD

tNV-FBVDDQ

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Compal Electronics, Inc.

VGA Notes List

VGA Notes List

VGA Notes List

KIWB1/B2_LA4602P

4 52Tuesday, March 24, 2009

4 52Tuesday, March 24, 2009

E

4 52Tuesday, March 24, 2009

0.1

0.1

0.1

5

4

3

2

1

D D

Layout rule：10mil width trace
length < 0.5", spacing 20mil

JCPU1B

COMP3

R83320_0402_1% R83320_0402_1%

1 2

COMP2

R83420_0402_1% R83420_0402_1%

1 2

COMP1

R83549.9_0402_1% R83549.9_0402_1%

1 2

COMP0

R83749.9_0402_1% R83749.9_0402_1%

1 2

TP_SKTOCC#

H_CATERR#

+VCCP

H_PECI<16>

+VCCP

H_PROCHOT#<51>

H_THERMTRIP#<16>

C C

+VCCP

+1.5V

R855

R855

4.75K_0402_1%

4.75K_0402_1%

1 2

1.07V

B B

VDDPW RGOOD_R

12

R860

R860
12K_0402_1%

12K_0402_1%

H_CPUPW RGD<16>

FROM POWER VTT POWER GOOD SIGNAL

H_PM_SYNC<15>

PM_DRAM_PW RGD<15>

VCCP_POK<49>

BUF_PLT_RST#<16,19,30,31>

R841 0_0402_5%R841 0_0402_5%

1.5K_0402_5%

1.5K_0402_5%

12

R84050_04 02_1% R84050_0402_1%

1 2

R842 68_0402_5%R842 68_0402_5%

R850

R850

1 2

R852

R852

1 2

R857

R857

1 2

R858

R858

1 2

R861

R861

1 2

H_PECI_ISO

12

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#_R

12

R84868_0402_5% R84868_0402_5%

H_PM_SYNC_R

0_0402_5%

0_0402_5%

VCCPW RGOOD_1

0_0402_5%

0_0402_5%

VCCPW RGOOD_0

0_0402_5%

0_0402_5%

VDDPW RGOOD_R

0_0402_5%

0_0402_5%

PLT_RST#_R

12

R862

R862
750_0402_1%

750_0402_1%

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

MISC THERMAL

MISC THERMAL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

CLOCKS

DDR3

DDR3

MISC

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TCK
TMS

TRST#

TDI

TDO

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

AR30
AT30

CLK_EXP

E16

CLK_EXP#

D16

A18
A17

F6

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI

AT29

XDP_TDO

AR27
AR29

R853 0_0402_5%R853 0_0402_5%

AP29

XDP_DBRESET#

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

pins unused by
Clarksfield on the
rPGA989 Package

1 2

R844 0_0402_5%R844 0_0402_5%

12

CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>

CLK_EXP <14>
CLK_EXP# <14>

DRAMRST# < 10,11>

PM_EXTTS#1_R <10,11>

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PM_EXTTS#0

PM_EXTTS#1

XDP_PREQ#

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

1 2

R836 100_0402_1%R 836 100_0402_1%

1 2

R838 24.9_0402_1%R838 24.9_0402_1%

1 2

R839 130_0402_1%R 839 130_0402_1%

Layout Note:Please these
resistors near Processor

1 2

R843 10K_0402_5%R843 10K_0402_5%

1 2

R845 10K_0402_5%R845 10K_0402_5%

R846 51_0402_1%@R846 51_0402_1%@

1 2

R847 51_0402_1%@R847 51_0402_1%@

1 2

R849 51_0402_1%@R849 51_0402_1%@

1 2

R851 51_0402_5%R851 51_0402_5%

1 2

R854 51_0402_1%@R854 51_0402_1%@

1 2

R856 51_0402_5%R856 51_0402_5%

1 2

R859

R859

1 2

1K_0402_5%@

1K_0402_5%@

+VCCP

+3VS

CHECK INTEL DOCUMENT #385422
Debug Port Design Guide Rev1.3

Address:100_1100

FAN1 Conn

+VCC_FAN1

EN_FAN1<37>

EN_FAN1

FAN +5VS DROOP

A A

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+VCC_FAN1

R863 100_0402_5%R863 100_0402_5%

1 2

FAN_SPEED1<37>

+5VS

1

C865

C865
2200P_0402_50V7K

2200P_0402_50V7K

2

R864

R864

10K_0402_5%

10K_0402_5%

C868

1000P_0402_50V7K

1000P_0402_50V7K

C868

C864 10U_0805_10V4ZC864 10U _0805_10V4Z

1 2

U41

U41

1

VEN

2

VIN

3

VO

4

VSET

G990P11U_SO8

G990P11U_SO8

+3VS

12

+VCC_FAN1

1

2

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

8

GND

7

GND

6

GND

5

GND

+VCC_FAN1

Clarksfiel(1/5)-Thermal/XDP

Clarksfiel(1/5)-Thermal/XDP

Clarksfiel(1/5)-Thermal/XDP

+5VS

12

@

@
D34

D34
1SS355TE-17_SOD323-2

1SS355TE-17_SOD323-2

D35 BA S16_SOT23-3@D35 BA S16_SOT23-3@

1 2

C866 1U_0603_10V4ZC866 1U_0603_10V4Z

1 2

C867 0.1U_0402_16V4ZC867 0.1U_0402_16V4Z

1 2

40mil

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

JP1

JP1

1

1

2

2

3

3

4

GND

5

GND

E&T_3801-F03N-01RME@

E&T_3801-F03N-01RME@

NIWBA_LA5371P

1

0.2

0.2

0.2

5 52Tuesday, March 24, 2009

5 52Tuesday, March 24, 2009

5 52Tuesday, March 24, 2009

5

4

ayout rule

L

：

race

t

3

2

1

length < 0.5"

J

J

J

CPU1A

CPU1A

D

MI_CRX_PTX_N0< 15>

D

MI_CRX_PTX_N1< 15>

D

MI_CRX_PTX_N2< 15>
MI_CRX_PTX_N3< 15>

D

D

MI_CRX_PTX_P0<15>

DMI_CRX_PTX_P1<15>

D D

DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N 0<15>
DMI_CTX_PRX_N 1<15>
DMI_CTX_PRX_N 2<15>
DMI_CTX_PRX_N 3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>

C C

FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

B B

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

A24

D

MI_RX#[0]

C23

D

MI_RX#[1]

B22

MI_RX#[2]

D

A21

MI_RX#[3]

D

B24

D

MI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

DMI Intel(R) FDI

DMI Intel(R) FDI

P

EG_ICOMPI

P

EG_ICOMPO

P

EG_RCOMPO

P

EG_RBIAS

EG_RX#[0]

P
P

EG_RX#[1]

P

EG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

E

XP_ICOMPI

B26
A26
B27

E

XP_RBIAS

A25

P

CIE_CRX_GTX_N15

K35

CIE_CRX_GTX_N14

P

J34

P

CIE_CRX_GTX_N13

J33

P

CIE_CRX_GTX_N12

G35

PCIE_CRX_GTX_N11

G32

PCIE_CRX_GTX_N10

F34

PCIE_CRX_GTX_N9

F31

PCIE_CRX_GTX_N8

D35

PCIE_CRX_GTX_N7

E33

PCIE_CRX_GTX_N6

C33

PCIE_CRX_GTX_N5

D32

PCIE_CRX_GTX_N4

B32

PCIE_CRX_GTX_N3

C31

PCIE_CRX_GTX_N2

B28

PCIE_CRX_GTX_N1

B30

PCIE_CRX_GTX_N0

A31

PCIE_CRX_GTX_P15

J35

PCIE_CRX_GTX_P14

H34

PCIE_CRX_GTX_P13

H33

PCIE_CRX_GTX_P12

F35

PCIE_CRX_GTX_P11

G33

PCIE_CRX_GTX_P10

E34

PCIE_CRX_GTX_P9

F32

PCIE_CRX_GTX_P8

D34

PCIE_CRX_GTX_P7

F33

PCIE_CRX_GTX_P6

B33

PCIE_CRX_GTX_P5

D31

PCIE_CRX_GTX_P4

A32

PCIE_CRX_GTX_P3

C30

PCIE_CRX_GTX_P2

A28

PCIE_CRX_GTX_P1

B29

PCIE_CRX_GTX_P0

A30

PCIE_CTX_GRX_C_N 15

L33

PCIE_CTX_GRX_C_N 14

M35

PCIE_CTX_GRX_C_N 13

M33

PCIE_CTX_GRX_C_N 12

M30

PCIE_CTX_GRX_C_N 11

L31

PCIE_CTX_GRX_C_N 10

K32

PCIE_CTX_GRX_C_N 9

M29

PCIE_CTX_GRX_C_N 8

J31

PCIE_CTX_GRX_C_N 7

K29

PCIE_CTX_GRX_C_N 6

H30

PCIE_CTX_GRX_C_N 5

H29

PCIE_CTX_GRX_C_N 4

F29

PCIE_CTX_GRX_C_N 3

E28

PCIE_CTX_GRX_C_N 2

D29

PCIE_CTX_GRX_C_N 1

D27

PCIE_CTX_GRX_C_N 0

C26

PCIE_CTX_GRX_C_P 15

L34

PCIE_CTX_GRX_C_P 14

M34

PCIE_CTX_GRX_C_P 13

M32

PCIE_CTX_GRX_C_P 12

L30

PCIE_CTX_GRX_C_P 11

M31

PCIE_CTX_GRX_C_P 10

K31

PCIE_CTX_GRX_C_P 9

M28

PCIE_CTX_GRX_C_P 8

H31

PCIE_CTX_GRX_C_P 7

K28

PCIE_CTX_GRX_C_P 6

G30

PCIE_CTX_GRX_C_P 5

G29

PCIE_CTX_GRX_C_P 4

F28

PCIE_CTX_GRX_C_P 3

E27

PCIE_CTX_GRX_C_P 2

D28

PCIE_CTX_GRX_C_P 1

C27

PCIE_CTX_GRX_C_P 0

C25

R

R

865 49.9_0402_1%

865 49.9_0402_1%

1 2

866 750_0402_1%

866 750_0402_1%

R

R

1 2

P

CIE_CRX_GTX_N[0..15] < 19>

PCIE_CRX_GTX_P[0..15] <19>

PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal

VGA@

C869 0.1U_0402_10V6KC869 0.1U_0402_10V6K

1 2

C870 0.1U_0402_10V6KC870 0.1U_0402_10V6K

1 2

C871 0.1U_0402_10V6KC871 0.1U_0402_10V6K

1 2

C872 0.1U_0402_10V6KC872 0.1U_0402_10V6K

1 2

C873 0.1U_0402_10V6KC873 0.1U_0402_10V6K

1 2

C874 0.1U_0402_10V6KC874 0.1U_0402_10V6K

1 2

C875 0.1U_0402_10V6KC875 0.1U_0402_10V6K

1 2

C876 0.1U_0402_10V6KC876 0.1U_0402_10V6K

1 2

C877 0.1U_0402_10V6KC877 0.1U_0402_10V6K

1 2

C878 0.1U_0402_10V6KC878 0.1U_0402_10V6K

1 2

C879 0.1U_0402_10V6KC879 0.1U_0402_10V6K

1 2

C880 0.1U_0402_10V6KC880 0.1U_0402_10V6K

1 2

C881 0.1U_0402_10V6KC881 0.1U_0402_10V6K

1 2

C882 0.1U_0402_10V6KC882 0.1U_0402_10V6K

1 2

C883 0.1U_0402_10V6KC883 0.1U_0402_10V6K

1 2

C884 0.1U_0402_10V6KC884 0.1U_0402_10V6K

1 2

C885 0.1U_0402_10V6KC885 0.1U_0402_10V6K

1 2

C886 0.1U_0402_10V6KC886 0.1U_0402_10V6K

1 2

C887 0.1U_0402_10V6KC887 0.1U_0402_10V6K

1 2

C888 0.1U_0402_10V6KC888 0.1U_0402_10V6K

1 2

C889 0.1U_0402_10V6KC889 0.1U_0402_10V6K

1 2

C890 0.1U_0402_10V6KC890 0.1U_0402_10V6K

1 2

C891 0.1U_0402_10V6KC891 0.1U_0402_10V6K

1 2

C892 0.1U_0402_10V6KC892 0.1U_0402_10V6K

1 2

C893 0.1U_0402_10V6KC893 0.1U_0402_10V6K

1 2

C894 0.1U_0402_10V6KC894 0.1U_0402_10V6K

1 2

C895 0.1U_0402_10V6KC895 0.1U_0402_10V6K

1 2

C896 0.1U_0402_10V6KC896 0.1U_0402_10V6K

1 2

C897 0.1U_0402_10V6KC897 0.1U_0402_10V6K

1 2

C898 0.1U_0402_10V6KC898 0.1U_0402_10V6K

1 2

C899 0.1U_0402_10V6KC899 0.1U_0402_10V6K

1 2

C900 0.1U_0402_10V6KC900 0.1U_0402_10V6K

1 2

PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

+V_DDR_CPU _REF1

FOR ES1 SAMPLE ONLY

PCIE_CTX_GRX_N[0..15 ] <19>

PCIE_CTX_GRX_P[0..15] <19>

CFG Straps for PROCESSOR

CFG0

PCI-Express Configuration Select

CFG0

Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

1 2

R873 3.01K_0402_1%@R873 3.01K_0402_1%@

1: Single PEG
0: Bifurcation enabled

10=2*8 PEG

R867

@ R867

@

R871

R871
0_0402_5%

0_0402_5%

1 2
1 2

R872

R872
0_0402_5%

0_0402_5%

V_DDR_CPU_R EF0

+

1 2

3.01K_0402_1%

3.01K_0402_1%

H_RSVD17_R

@

@

H_RSVD18_R

@

@

CFG0

CFG3
CFG4

CFG7

J

CPU1E

CPU1E

AP25

SVD1

R

AL25

SVD2

R

AL24

R

SVD3

AL22

R

SVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59

RESERVED

RESERVED

RSVD_TP_60

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

R

SVD32

R

SVD33

SVD34

R
R

SVD35

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

KEY
RSVD62
RSVD63
RSVD64
RSVD65

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

RSVD64_R
RSVD65_R

R868

R868
0_0402_5%

0_0402_5%

R869

R869
0_0402_5%

0_0402_5%

@

@

12

@

@

12

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

A A

5

R870 1K_0402_5%DIS@R870 1K_0402 _5%DIS@

1 2

R930 1K_0402_5%DIS@R930 1K_0402 _5%DIS@

1 2

R943 1K_0402_5%DIS@R943 1K_0402 _5%DIS@

1 2

R990 1K_0402_5%DIS@R990 1K_0402 _5%DIS@

1 2

R991 1K_0402_5%DIS@R991 1K_0402 _5%DIS@

1 2

4

CFG3

CFG3-PCI Express Static Lane Reversal

CFG4

CFG4-Display Port Presence

CFG4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R874 3.01K_0402_1%R874 3.01K_0402_1%

CFG3

1 2

1: Normal Operation

0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

R875

@R875

@

1 2

3.01K_0402_1%

3.01K_0402_1%

1: Disabled; No Physical Display Port
attached to Embedded Display Port

0: Enabled; An external Display Port
device is connected to the Embedded
Display Port

2008/10/31 2009/10/31

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Clarksfiel(2/5)-DMI/PEG/FDI

Clarksfiel(2/5)-DMI/PEG/FDI

Clarksfiel(2/5)-DMI/PEG/FDI

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

NIWBA_LA5371P

1

6 52Tuesday, March 24, 2009

6 52Tuesday, March 24, 2009

6 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

CPU1C

CPU1C

J

J

4

3

J

J

CPU1D

CPU1D

2

1

D D

C C

B B

DDR_A_D[0..63]<10>

DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>

DDR_A_CAS#<10>
DDR_A_RAS#<10>
DDR_A_W E#< 10>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

A10

C10

B10

D10

E10

F10

H10

G10

J10

AH5
AF5
AK6
AK7
AF6
AG5

AJ7
AJ6

AJ10

AJ9
AL10
AK12

AK8

AL7
AK11

AL8

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

AC3
AB2

AE1
AB3
AE9

C7
A7

A8
D8

E6
F7
E9
B7
E7
C6

G8
K7

J8

G7

J7

L7
M6
M8

L9

L6
K8
N8
P9

U7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_CKE0_DIM MA <10>

M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_CKE1_DIM MA <10>

DDR_CS0_DIM MA# <10>
DDR_CS1_DIM MA# <10>

M_ODT0 <10>
M_ODT1 <10>

DDR_A_DM[0..7] <10>

DDR_A_DQS#[0..7] < 10>

DDR_A_DQS[0..7] <10>

DDR_A_MA[0..15] <10>

DDR_B_D[0..63]<11>

DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>

DDR_B_CAS#<11>
DDR_B_RAS#<11>
DDR_B_W E#<11>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AF3
AG1

AJ3
AK1
AG4
AG3

AJ4
AH4
AK3
AK4

AM6
AN2

AK5
AK2

AM4
AM3

AP3

AN5

AT4

AN6
AN4
AN3

AT5
AT6

AN7

AP6
AP8
AT9
AT7
AP9

AR10

AT10

AB1

AC5

AC6

G4

G2

G1
G5

M1

M4

W5

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3

H6

J6
J3

J2
J1
J5

K2

L3

K5
K4

N5

R7

Y7

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

W8
W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <11>
M_CLK_DDR#2 <11>
DDR_CKE2_DIM MB <11>

M_CLK_DDR3 <11>
M_CLK_DDR#3 <11>
DDR_CKE3_DIM MB <11>

DDR_CS2_DIM MB# <11>
DDR_CS3_DIM MB# <11>

M_ODT2 <11>
M_ODT3 <11>

DDR_B_DM[0..7] <11>

DDR_B_DQS#[0..7] <11>

DDR_B_DQS[0..7] <11>

DDR_B_MA[0..15] < 11>

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

A A

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(3/5)-DDR III

Clarksfiel(3/5)-DDR III

Clarksfiel(3/5)-DDR III

NIWBA_LA5371P

1

7 52Tuesday, March 24, 2009

7 52Tuesday, March 24, 2009

7 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

V

+

CPU_CORE

J

J

CPU1F

CPU1F

8A 15A18A

D D

C C

B B

A A

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

4

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VTT_SELECT

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

TT0(1.1V) = 7*0805 22uf under cavity

8*0805 10uf edge caps

3*330uf/6m ohm 1*330uf

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

VTT_SELECT

10U_0805_10V4K

10U_0805_10V4K

C903

C903

1

2

10U_0805_10V4K

10U_0805_10V4K

C905

C905

1

@

@

2

10U_0805_10V4K

10U_0805_10V4K

C922

C922

1

2

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR _R

1

2

1

2

R877 0_0402_5%R877 0_0402_5%

10U_0805_10V4K

10U_0805_10V4K

C901

C901

10U_0805_10V4K

10U_0805_10V4K

C906

C906

@

@

+VCCP

10U_0805_10V4K

10U_0805_10V4K

C923

C923

1

2

1 2

10U_0805_10V4K

10U_0805_10V4K

C902

C902

1

2

10U_0805_10V4K

10U_0805_10V4K

C907

C907

1

2

PSI# <51>

H_VID[0..6] < 51>

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

H_VTTVID1 = High, 1.05V FOR Auburndale

AN35

AJ34
AJ35

B15
A15

VCC_SENSE
VSS_SENSE

1 2
1 2

IMVP_IMON < 51>

0_0402_5%

0_0402_5%

R878

R878

R879 0_0402_5%R879 0_0402_5%

@

VCCSENSE
VSSSENSE

VTT_SENSE <49>

T81PAD@T81PAD

Close to CPU

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

VCCSENSE

VSSSENSE

5

1 2

R880 100_0402_1%R880 100_0402_1%

1 2

R881 100_0402_1%R881 100_0402_1%

10U_0805_10V4K

10U_0805_10V4K

C904

C904

1

2

10U_0805_10V4K

10U_0805_10V4K

C908

C908

1

2

10U_0805_10V4K

10U_0805_10V4K

1

2

+CPU_CORE

4

VCCP

+

10U_0805_10V4K

10U_0805_10V4K

C909

C909

1

2

10U_0805_10V4K

10U_0805_10V4K

C915

C915

C916

C916

1

2

PROC_DPRSLPV R <51>

VTT_SELECT <49>

VCCSENSE <51>
VSSSENSE <51>

4

3

+

GFX_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

278

278

600

600

C

C

C

C

@

@

@

@

2

22U_0805_6.3V6M

22U_0805_6.3V6M

12

R313

R313
0_0402_5%

0_0402_5%
DIS@

DIS@

+VCCP

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C917

C917

C918

1

2

C918

1

2

22U_0805_6.3V6M

1

1

270

270

274

274

C

C

C

C

@

@

@

@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

644

644

279

279

C

C

C

C

UMA@

UMA@

UMA@

UMA@

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCCP

10U_0805_10V4K

10U_0805_10V4K

1

2

C928

C928

10U_0805_6.3V6M

10U_0805_6.3V6M

1

1

275

275

271

271

C

C

C

C

UMA@

UMA@

UMA@

UMA@

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

+VCCP

1

2

10U_0805_10V4K

10U_0805_10V4K

C929

C929

1

1

2

2

1

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C924

C924

C925

C925

1

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C930

C930

C931

C931

1

2

J

J

CPU1G

CPU1G

AT21

AXG1

V

AT19

AXG2

V

AT18

V

AXG3

AT16

V

AXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

2

AXG_SENSE

V

V

SSAXG_SENSE

SENSE

SENSE

LINES

LINES

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

GRAPHICS VIDs

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

3A

0.6A

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65

1.1V1.8V

1.1V1.8V

VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

GFX_VR_EN

GFX_IMON_R

1U_0603_10V4Z

1U_0603_10V4Z

1

2

330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

1

+

+

2

1U_0603_10V4Z

1U_0603_10V4Z

C934

C934

1

2

1 2

C910

C910

1

2

C919

C919

1

2

1U_0603_10V4Z

1U_0603_10V4Z

1

2

V

CC_AXG_SENSE <50>
SS_AXG_SENSE <50>

V

UMA@

UMA@

1U_0603_10V4Z

1U_0603_10V4Z

C911

C911

1

2

10U_0805_10V4K

10U_0805_10V4K

C920

C920

1

2

1

2

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

C935

C935

C936

C936

1

2

GFXVR_VID_0 <50>
GFXVR_VID_1 <50>
GFXVR_VID_2 <50>
GFXVR_VID_3 <50>
GFXVR_VID_4 <50>
GFXVR_VID_5 <50>
GFXVR_VID_6 <50>

R314 0_0402_5%

R314 0_0402_5%

+1.5V

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C913

C913

C912

C912

1

2

10U_0805_10V4K

10U_0805_10V4K

C921

C921

+VCCP

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C926

C926

C927

C927

1

2

+VCCP

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C933

C933

C932

C932

1

2

+1.8VS

10U_0805_10V4K

10U_0805_10V4K

C937

C937

1

1

2

2

1

876

876

R

FX_IMON_R

G

A

S NO CONNECT

R

DIS@

DIS@

12

BUT A SMALL AMOUNT OF POWER

(~15MW) MAYBE WASTED

ESIGN GUIDE REV1.1

D

R91

GFX_VR_EN

GFXVR_EN <50>
GFXVR_DPRSLPV R <50>

GFXVR_IMON <50>

1U_0603_10V4Z

1U_0603_10V4Z

C914

C914

1

2

R91

1 2

UMA@

UMA@

VDDQ(CPU) = 5*0402 1uf

2*0805 22uf

TOTAL 3*330uf FOR 2 SO-DIMMs

VDDQ(SO DIMM) = 14*0402 1uf
(7*0402 PER CONNECTOR)

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C938

C938

1K_0402_5%

1K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

VCCPLL(1.8V) = 1*0805 22uf

1*0805 1uf

CPU

1*0805 22uf

1*0603 4.7uf

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(4/5)-PWR

Clarksfiel(4/5)-PWR

Clarksfiel(4/5)-PWR

NIWBA_LA5371P

1

8 52Tuesday, March 24, 2009

8 52Tuesday, March 24, 2009

8 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

J

J

CPU1H

CPU1H

AT20

V

SS1

AT17

V

SS2

AR31

V

SS3

AR28

SS4

V

AR26

SS5

V

AR24

V

SS6

AR23

V

SS7

AR20

D D

C C

B B

AR17
AR15
AR12

AR9
AR6

AR3
AP20
AP17
AP13
AP10

AP7

AP4

AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AM8

AM5

AM2

AL34
AL31
AL23
AL20
AL17
AL12

AL9
AL6

AL3
AK29
AK27
AK25
AK20
AK17

AJ31
AJ23
AJ20
AJ17
AJ14
AJ11

AJ8

AJ5

AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13

AH9
AH6
AH3

AG10

AF8
AF4
AF2

AE35

VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

VSS

V

SS81

V

SS82

V

SS83
SS84

V

SS85

V
V

SS86

V

SS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27

J32
J30
J21

J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11

G34
G31
G20

F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11

D33
D30
D26

C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11

A29
A27
A23

4

J

J

CPU1I

CPU1I

V

SS161

K9

SS162

V

K6

SS163

V

K3

V

SS164

V

SS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178

H8

VSS179

H5

VSS180

H2

VSS181
VSS182
VSS183
VSS184

G9

VSS185

G6

VSS186

G3

VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201

E8

VSS202

E5

VSS203

E2

VSS204
VSS205
VSS206
VSS207

D9

VSS208

D6

VSS209

D3

VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226

B8

VSS227

B6

VSS228

B4

VSS229
VSS230
VSS231
VSS232

A9

VSS233

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

VSS_NCTF1_R
VSS_NCTF2_R
VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R
VSS_NCTF6_R
VSS_NCTF7_R

3

CPU_CORE

+

2

PU CORE

C

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C941

C941

C940

C940

C939

C939

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C952

C952

C951

C951

1

1

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C953

C953

1

1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C942

C942

C943

C943

C944

C944

1

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C955

C955

C954

C954

1

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C956

C956

1

1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C945

C945

C946

C946

C947

C947

C948

1

1

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C957

C957

C958

C958

1

1

C948

1

1

2

2

C959

C959

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C950

C950

C949

C949

1

I

nside cavity

2

1

between Inductor and socket

2

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C960

C960

1

1

2

2

10U_0805_6.3V6M

C961

C961

C962

C962

1

2

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C964

C964

C963

C963

1

1

2

2

Under cavity

+CPU_CORE = 12*0805 22uf INSIDE CAVITY

7*0805 10uf UNDER CAVITY AND 9*0805 10uf BETWEEN INDUCTOR AND SOCKET ON TOP LAYER

4*470uf/4m ohm 2*470uf

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C965

C965

1

2

2

2

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

10U_0805_6.3V6M

10U_0805_6.3V6M

C966

C966

1

2

1

+

+

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

C968

C968

C967

C967

1

1

2

+

+

+

+

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

C970

C970

C969

C969

1

+

+

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C971

C971

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

C972

C972

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C973

C973

C974

C974

1

2

470uF 4.5mohm

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

A A

5

IC,AUB_CFD_r PGA,R1P0

IC,AUB_CFD_r PGA,R1P0

4

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(5/5)-GND/Bypass

Clarksfiel(5/5)-GND/Bypass

Clarksfiel(5/5)-GND/Bypass

NIWBA_LA5371P

1

9 52Tuesday, March 24, 2009

9 52Tuesday, March 24, 2009

9 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

VREF_DQ_DIMMA

+

+

VREF_DQ_DIMMA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

1

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

2

D D

C C

B B

A A

C976

C976

C

C
975

975

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

2

D

DR_A_D0

D

DR_A_D1

DR_A_DM0

D

D

DR_A_D2

DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIM MA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_W E#
DDR_A_CAS# M_ODT0

DDR_A_MA13
DDR_CS1_DIM MA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R889

R889

1 2

10K_0402_5%

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K

C1002

C1002

C1003

C1003

1

2

1.5V

+

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

D

DR3 SO-DIMM A

JD

JD

DR1

DR1

1

V

REF_DQ

3

V

SS2

5

D

Q0

7

Q1

D

9

SS4

V

11

D

M0

13

V

SS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

10K_0402_5%

10K_0402_5%

12

203

R890

R890

VTT1

205

G1

TYCO_2-2013289-1

TYCO_2-2013289-1

VREF_CA

V

SS1
D
D

SS3

V
QS#0

D

D

QS0

V

SS6
DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

RESET#

VSS12

DQ14
DQ15

VSS14

DQ20
DQ21

VSS16

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30
DQ31

VSS26

CKE1

VDD2

A15

A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA
SCL

VTT2

2
4

Q4

6

Q5

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

4

1.5V

+

DR_A_D4

D
D

DR_A_D5

D

DR_A_DQS#0
DR_A_DQS0

D

D

DR_A_D6

DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DRAMRST# <5,11>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 < 7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K
C980

C980

1

1

2

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R <5,11>

SMB_DATA_S3 <11,12,14,30>
SMB_CLK_S3 <11,12,14,30>

D

DR_A_D[0..63]<7>

D

DR_A_DM[0..7]<7>

D

DR_A_DQS[0..7]<7>

DR_A_DQS#[0..7]<7>

D

D

DR_A_MA[0..15]<7>

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
C981

C981

SMBCLK<11,14>

SMBDATA<11,14>

4*0402 1uf

1*0402 2.2uf

3

+

VREF_DQ_DIMMA

1 2

R

R

882 0_0402_5%

882 0_0402_5%

1 2

R

R

884 0_0402_5%

884 0_0402_5%

1 2

R885 0_0402_5%

R885 0_0402_5%

2

C977

C977

M2@

M2@

1

1U_0603_10V4Z X5R

1U_0603_10V4Z X5R

SMBCLK

SMBDATA

U42

U42

1

VDD

2

GND

3

SCL

ISL90727WIE627Z-TK_SC70-6

ISL90727WIE627Z-TK_SC70-6
M2@

M2@

I2C address 5Ch

RW

SDA

6

RH

5

4

2

V

_DDR_CPU_REF

M1@

M1@

M2@

M2@

M3@

M3@

R887

R887
M2@

M2@

12.1k_0402_1%

12.1k_0402_1%

1 2

VREF_RW_POT0

R888

R888
M2@

M2@

12.1k_0402_1%

12.1k_0402_1%

1 2

+

V_DDR_CPU_REF

+

V_DDR_M2_REF0

3

2

+VREF_OPAMP_POT0

+3VALW+3VALW +1.5V+1.5V

8

+

-

4

+

P

1

O

G

U43A

U43A
M2@

M2@
LM393M_SO8

LM393M_SO8

V_DDR_CPU_REF0

2

C978

C978
M2@

M2@
1U_0603_10V4Z X5R

1U_0603_10V4Z X5R

1

+

R

R

883

883

1K_0402_1%

1K_0402_1%

R886

R886

1K_0402_1%

1K_0402_1%

+V_DDR_M2_REF0

2

1

1

1.5V

12

+

V_DDR_CPU_REF

12

C979

C979

1U_0603_10V4Z X5R

1U_0603_10V4Z X5R
@

@

Layout Note:
Place near DIMM

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C982

C982

1

@

@

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C984

C984

C983

C983

@

@

1

1

2

2

+0.75VS

C996

C996

1

2

10U_0603_6.3V6M

C985

C985

C986

C986

1

1

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C997

C997

C998

C998

1U_0603_10V4Z

1U_0603_10V4Z

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C987

C987

1

2

1U_0603_10V4Z

1U_0603_10V4Z

C1000

C1000

C999

C999

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

C988

C988

C989

C989

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K
C990

C990

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C991

C991

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

C992

C992

C993

C993

1

1

2

+

+

C994

C994
220U_B_2.5VM_R35M

220U_B_2.5VM_R35M

2

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

TOP SLOT

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

NIWBA_LA5371P

1

10 52Tuesday, March 24, 2009

10 52Tuesday, March 24, 2009

10 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

VREF_DQ_DIMMB

+

+

0.1U_0402_10V6K

0.1U_0402_10V6K
C1028

C1028

10K_0402_5%

10K_0402_5%

VREF_DQ_DIMMB

D

DR_B_D0

D

DR_B_D1

DR_B_DM0

D

D

DR_B_D2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

R896

R896

1 2

1 2

R897 10K_0402_5%R897 10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

2

D D

C C

B B

A A

1

C1005

C1005

C

C
1004

1004

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z
C1027

C1027

1

1

2

2

1.5V

+

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JD

JD

DR2

DR2

1

V

REF_DQ

3

V

SS

5

D

Q0

7

Q1

D

9

SS

V

11

D

M0

13

V

SS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

TYCO_2-2013310-1_204P

TYCO_2-2013310-1_204P
CONN@

CONN@

V
D
D
V

QS0#

D

D

QS0
V
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

A15
A14

VDD

A11

VDD

VDD

VDD

CK1
CK1#

VDD

BA1
RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36
DQ37

VSS

DM4

VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

DM6

VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

SS
Q4
Q5
SS

SS

A7

A6
A4

A2
A0

NC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

1.5V

+

D
D

D
D

D
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D22
DDR_B_D23DDR_B_D18

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

+VREF_CA

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

BOT SLOT

5

DR_B_D4
DR_B_D5

DR_B_DQS#0
DR_B_DQS0

DR_B_D6

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

DR_B_DQS#[0..7]<7>

D

D

DR_B_D[0..63]<7>

D

DR_B_DM[0..7]<7>

D

DR_B_DQS[0..7]<7>

DR_B_MA[0..15]<7>

D

DRAMRST# <5,10>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 < 7>
M_CLK_DDR#3 <7>

DDR_B_BS1 < 7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

C1009

C1009

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

C1018

C1018

1

2

3

+

VREF_DQ_DIMMB

R

R

891

891

1 2

1 2

892 0_0402_5%M2@

892 0_0402_5%M2@

R

R

1 2

R893 0_0402_5%M3@R893 0_0402_5%M3@

2

C1006

C1006

M2@

M2@

1

1U_0603_10V4Z X5R

1U_0603_10V4Z X5R

SMBCLK<10,14>

SMBDATA<10,14>

SMBCLK

SMBDATA

U44

U44

1

VDD

2

GND

3

SCL

ISL90728WIE627Z-TK_SC70-6

ISL90728WIE627Z-TK_SC70-6
M2@

M2@

I2C address 7Ch

RH

RW

SDA

6

5

4

0_0402_5%M1@

0_0402_5%M1@

+1.5V+1.5V

1 2

1 2

2

+

V_DDR_CPU_REF

R894

R894
M2@

M2@

12.1k_0402_1%

12.1k_0402_1%

VREF_RW_POT1

R895

R895
M2@

M2@

12.1k_0402_1%

12.1k_0402_1%

V_DDR_M2_REF1

+

+3VALW+3VALW

5

+

6

-

+VREF_OPAMP_POT1

+

V_DDR_CPU_REF1

CAP 1UF OVERPAGE

8

P

7

O

G

U43B

U43B
M2@

M2@

4

LM393M_SO8

LM393M_SO8

+V_DDR_M2_REF1

2

C1008

C1008

1U_0603_10V4Z X5R

1U_0603_10V4Z X5R

1

M2@

M2@

1

Layout Note:
Place near DIMM

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C1012

C1010

C1010

1

@

@

@

@

2

C1012

C1011

C1011

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C1013

C1013

C1014

C1014

C1015

1

2

C1015

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C1016

C1016

1

2

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K
C1019

C1017

C1017

1

2

C1019

1

1

2

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C1020

C1020

1

2

0.1U_0402_10V6K

C1021

C1021

C1022

C1022

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

Layout Note:
Place near DIMM

+0.75VS

VDDSPD (3.3V)=

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R <5,10>

SMB_DATA_S3 <10,12,14,30>
SMB_CLK_S3 <10,12,14,30>

+0.75VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

1U_0603_10V4Z

C1024

C1024

C1023

C1023

1

1

2

1

2

2

2008/10/31 2009/10/31

2008/10/31 2009/10/31

2008/10/31 2009/10/31

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C1026

C1026

C1025

C1025

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

NIWBA_LA5371P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

11 52Tuesday, March 24, 2009

11 52Tuesday, March 24, 2009

11 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

4

3

2

1

D D

C C

CLK GEN TO PCH

1. CLK_DMI

2. CLK_BUF_BCLK

3. CLK_BUF_CKSSCD

4. CLK_BUF_DOT96

5. CLK_14M_PCH

1 2

CLK GEN TO VGA

1. 27M_CLK

1. 27M_CLK_SS

+1.05VS_CK505+1.05VS

R9090_0603_5% R9090_0603_5%

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C1029

C1029

C1030

1

2

C1030

1

2

SCL

SDA

CPU_0

CPU_1

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17

SMB_CLK_S3
SMB_DATA_S3
REF_0/CPU_SEL

CLK_XTAL_IN
CLK_XTAL_OUT

CK_PWRGD

R_CLK_BUF_BCLK CLK_BUF_BCLK
R_CLK_BUF_BCLK# CLK_BUF_BCLK#

R903 0_0402_5%R903 0_0402_5%

R904 0_0402_5%R904 0_0402_5%

1 2
1 2

33_0402_1%

33_0402_1%

R899

R899

12

CLK_14M_PCH

CK_PWRGD

CLK_BUF_BCLK <14>
CLK_BUF_BCLK# <14>

Q60

2N7002_SOT23-3

2N7002_SOT23-3

Q60

SMB_CLK_S3 <10,11,14,30>
SMB_DATA_S3 <10,11,14,30>

CLK_14M_PCH <14>

R908

R908

1 2

10K_0402_5%

10K_0402_5%

13

D

D

2

G

G

S

S

+3VS_CK505

CLK_EN# <51>

U45

U45

1

CLK_BUF_DOT96<14>

CLK_BUF_DOT96#<14>

27M_CLK<19>

27M_CLK_SS<19>

CLK_BUF_CKSSCD<14>

CLK_BUF_CKSSCD#<14>

CLK_DMI<14>

CLK_DMI#<14>

CLK_BUF_DOT96
CLK_BUF_DOT96#

27M_CLK
27M_CLK_SS

CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#

CLK_DMI
CLK_DMI#

+3VS_CK505

R898 0_0402_5%R898 0_0402_5%

1 2
1 2

R900 0_0402_5%R900 0_0402_5%

R901 33_0402_1%R901 33_0402_1%

1 2

R902 33_0402_1%R902 33_0402_1%

1 2

CLOSE U5

R905 0_0402_5%R905 0_0402_5%

1 2

R906

R906

R907

R907

1 2

1 2

0_0402_5%

0_0402_5%

10K_0402_5%

10K_0402_5%

L_CLK_BUF_DOT96
L_CLK_BUF_DOT96#

27M_CLK_L
27M_CLK_SS_L

CLK_48M_CR_R

L_CLK_DMI
L_CLK_DMI#

CPU_STOP#

VDD_DOT

2

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11

SRC_1#/SATA#

12

VSS_SRC

13

SRC_2

14

SRC_2#

15

VDD_SRC_IO

16

CPU_STOP#

SLG8SP585VTR_QFN32_5X5

SLG8SP585VTR_QFN32_5X5

REF_0/CPU_SEL

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

CKPWRGD/PD#

VDD_CPU

CPU_0#

VSS_CPU

CPU_1#

VDD_CPU_IO

VDD_SRC

TGND

33

S IC ICS9LRS3199AKLFT MLF 32P CLK GEN (SA000030P00)1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C1031

C1031

C1032

1

2

C1032

1

2

0.1U_0402_10V6K
C1033

C1033

1

2

CLK_48M_CR<33>

1 2

CLK_48M_CR_R

R9100_0402_5% R9100_0402_5%

12

R9110_0402_5%@R9110_0402_5%

@

PIN8 IS GND FOR ICS3197
PIN8 IS 48MHz FOR ICS3199

R9120_0603_5% R9120_0603_5%

+3VS_CK505

1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

C1035

C1035

1

1

2

2

(Default)

0 133MHz

1

0.1U_0402_10V6K

0.1U_0402_10V6K

C1036

C1036

C1037

C1037

1

1

2

2

100MHz 100MHz

0.1U_0402_10V6K

0.1U_0402_10V6K
C1038

C1038

1

2

CPU_1PIN 30 CPU_0

133MHz

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C1039

C1039

C1040

C1040

1

1

2

2

C1034

C1034

0.1U_0402_10V6K

0.1U_0402_10V6K
C1041

C1041

C1042

C1042

EMI Capacitor

+1.05VS

1 2

R913 10K_0402_5%@R913 10K_0402_5%@

1 2

R914 10K_0402_5%R914 10K_0402_5%

CLK_14M_PCH

12

10P_0402_50V8J@

10P_0402_50V8J@

12

REF_0/CPU_SEL

REF_0/CPU_SEL

10P_0402_50V8J@

10P_0402_50V8J@

C1043

C1043

33P_0402_50V8J

33P_0402_50V8J

CLK_XTAL_OUT

CLK_XTAL_IN

Y6

Y6

12

2

14.31818MHZ_16PF_DSX840GA

14.31818MHZ_16PF_DSX840GA

1

2

1

C1044

C1044

33P_0402_50V8J

33P_0402_50V8J

+3VS

1 2

B B

A A

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

NIWBA_LA5371P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

12 52Tuesday, March 24, 2009

12 52Tuesday, March 24, 2009

12 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

P

CH_RTCX1

P

1

C

C

1046

1046

18P_0402_50V8J

18P_0402_50V8J

2

32.768KHZ_12.5P_1TJS125BJ2A251

32.768KHZ_12.5P_1TJS125BJ2A251

SM_INTRUDER#

PCH_INTVRMEN

PCH_SPKR

CH_RTCX2

1 2

R

R

915 10M_0402_5%

915 10M_0402_5%

18P_0402_50V8J

18P_0402_50V8J

1

C

C

1045

D D

+RTCVCC

R917

R917

1 2

100_0603_1%

100_0603_1%

2

C1049

C1049

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C C

+RTCBATT

+RTCVCC

+3VS

1045

2

R916

R916

1 2

R918

R918

1 2

H：Integrated VRM enable

*

L：Integrated VRM disable

2

1M_0402_5%

1M_0402_5%

330K_0402_5%

330K_0402_5%

1 2

R924 1K_0402_5%@R924 1K_0402_5%@

4IN1

7

7

X

X

OUT

NC3NC

GPIO33 = GPO , internal pull-up,should not be pulled low

flash ME core of strap pin pull down

+3VALW+3VALW +3VALW +3VALW +3VS

12

R932

R932
200_0402_5%

200_0402_5%
@

@

12

B B

R939

R939
100_0402_1%

100_0402_1%
@

@

12

R933

R933
200_0402_5%

200_0402_5%
@

@

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

12

R940

R940
100_0402_1%

100_0402_1%
@

@

R934

R934
20K_0402_5%

20K_0402_5%

@

@

1 2

R941

R941
10K_0402_1%

10K_0402_1%

@

@

1 2

R935

R935
20K_0402_5%

20K_0402_5%

@

@

1 2

12

R942

R942
10K_0402_5%

10K_0402_5%
@

@

4

+RTCVCC

HDA_BITCLK_CODEC<35>

HDA_SYNC_CODEC<35>

HDA_RST_CODEC#<35>

HDA_SDOUT_CODEC<35>

C1047

C1047

1U_0603_10V4Z

1U_0603_10V4Z

1 2

R920 20K_0402_1%R920 20K_0402_1%

1 2

R921 20K_0402_1%R921 20K_0402_1%

C1048

C1048

1U_0603_10V4Z

1U_0603_10V4Z

PCH_SPKR< 35>

HDA_SDIN1<35>

ME_FLASH<37>

+3VALW

SPI_CLK_PCH

1

12

CLRP1

CLRP1

SHORT PADS

SHORT PADS

2

1

12

CLRP2

CLRP2

SHORT PADS

SHORT PADS

2

R919 33_0402_5%R919 33_0402_5%

1 2

R923 33_0402_5%R923 33_0402_5%

1 2

R925 33_0402_5%R925 33_0402_5%

1 2

R926 33_0402_5%R926 33_0402_5%

1 2

R927 100K_0402_5%@R927 100K_0402_5%@

1 2

R928 0_0402_5%R928 0_0402_5%

1 2

R929 10K_0402_5%R929 10K_0402_5%

1 2

R1076

R1076

1 2

0_0402_5%

0_0402_5%

GPIO13 = GPI,3.3V,SUS

PCH_RTCX1
PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

BITCLK

HDA_SYNC

PCH_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDOUT

GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SI

SPI_SO_R

3

U46A

U46A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

SATA

SATA

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

LPC

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

D33
B33
C32
A32

C34

A34

GPIO23

F34

SERIRQ

AB9

AK7
AK6

SATA_ITX_C_DRX_N0

AK11

SATA_ITX_C_DRX_P0

AK9

AH6
AH5

SATA_ITX_C_DRX_N1

AH9

SATA_ITX_C_DRX_P1

AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

SATA_DTX_C_IRX_N4

AD9

SATA_DTX_C_IRX_P4

AD8

SATA_ITX_C_DRX_N4

AD6

SATA_ITX_C_DRX_P4

AD5

AD3
AD1
AB3
AB1

AF16

SATAICOMPPCH_JTAG_RST#

AF15

T3

GPIO21

Y9

GPIO19

V1

2

LPC_AD0 <37,38>
LPC_AD1 <37,38>
LPC_AD2 <37,38>
LPC_AD3 <37,38>

LPC_FRAME# <37,38>

T82 PADT82 PAD

GPIO23 = NATIVE,3.3V,CORE

R931

R931

1 2

37.4_0402_1%

37.4_0402_1%

1 2

R936 10K_0402_5%R936 10K_0402_5%

LPC_DRQ0# <38>

SERIRQ <37,38>

+1.05VS

+3VS

DRIVE_LED# <41>

GPIO21 = GPI,3.3V,CORE

GPIO19 = GPI,3.3V,CORE

1

+3VS

12

R92210K_0402_5% R92210K_0402_5%

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

C10500.01U_0402_16V7K C10500.01U_0402_16V7K

12

C10510.01U_0402_16V7K C10510.01U_0402_16V7K

12

C10520.01U_0402_16V7K C10520.01U_0402_16V7K

12

C10530.01U_0402_16V7K C10530.01U_0402_16V7K

12

C10540.01U_0402_16V7K C10540.01U_0402_16V7K

12

C10550.01U_0402_16V7K C10550.01U_0402_16V7K

12

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N1
SATA_ITX_DRX_P1

SATA_ITX_DRX_N4_CONN

SATA_ITX_DRX_P4_CONN

R937

R937

10K_0402_5%

10K_0402_5%

GPIO21

GPIO19

1 2

SATA_DTX_C_IRX_N0 <34>

SATA_DTX_C_IRX_P0 <34>
SATA_ITX_DRX_N0 < 34>
SATA_ITX_DRX_P0 <34>

SATA_DTX_C_IRX_N1 <34>

SATA_DTX_C_IRX_P1 <34>
SATA_ITX_DRX_N1 < 34>

SATA_ITX_DRX_P1 <34>

SATA_DTX_C_IRX_N4 <34>

SATA_DTX_C_IRX_P4 <34>
SATA_ITX_DRX_N4_CONN <34>

SATA_ITX_DRX_P4_CONN <34>

R938

R938
10K_0402_5%

10K_0402_5%

1 2

SPI_CLK_PCH

12

R572

SPI ROM on ME

RefDesPCH Pin

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

A A

PCH_JTAG_RST#

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

R104

No Install

R108

No Install

200ohm

R105

100ohm 100ohm

R109

200ohm

100ohm 100ohm

R110

51ohm 51ohm 51ohm

R97

20Kohm 20Kohm

R107

10Kohm 10Kohm

R110

200ohm

100ohm

200ohm

200ohm

No Install

No Install

No Install

No Install

No Install

20Kohm

10Kohm

No Install

No Install

No Install

No Install

No InstallR106

No Install

51ohm

No Install

No InstallNo Install

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_RST#

PCH_JTAG_TCK

R806 51_0402_5%@R806 51_0402_5%@

1 2

R807 51_0402_5%@R807 51_0402_5%@

1 2

R808 51_0402_5%@R808 51_0402_5%@

1 2

R809 51_0402_5%@R809 51_0402_5%@

1 2

R90 4.7K_0402_5%R90 4.7K_0402_5%

1 2

CRB 1.0 Change to 4.7K

+1.05VS

SPI_SB_CS0#
SPI_SO_R SPI_SO_L

+3VS

R944

R944

R945

R945

R946

R946

15_0402_5%

15_0402_5%

1 2

<BOM Structure>

<BOM Structure>

1 2

1 2

R947

R947

15_0402_5%

15_0402_5%

SPI_WP#

3.3K_0402_5%

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

3.3K_0402_5%

12

SPI_WP#

<BOM Structure>

<BOM Structure>

U37

U37

1

CS#
SO
WP#
GND

VCC

HOLD#

SCLK

SI

2
3
4

MX25L1605AM2C-12G_SO8

MX25L1605AM2C-12G_SO8

8
7
6
5

+3VS

SPI_HOLD#
SPI_CLK_PCH

C1056

C1056

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SPI_SI

R572

33_0402_5%

33_0402_5%

@

@

C748

@

@

C748

22P_0402_50V8J

22P_0402_50V8J

FOR EVT

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

NIWBA_LA5371P

1

13 52Tuesday, March 24, 2009

13 52Tuesday, March 24, 2009

13 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

P

CIE PORT LIST

DEVICEPORT

1
2
3

D D

4
5
6
7
8

EXP

WLAN

LAN

3G

C C

TV

EXP

WLAN

B B

LAN

3G

TV

A A

CLK_PCIE_EXP_PCH#<30>
CLK_PCIE_EXP_PCH<30>

CLK_PCIE_CARD_PCH#<30>
CLK_PCIE_CARD_PCH<30>

PCIE_PRX_DTX_N1<30>
PCIE_PRX_DTX_P1<30>
PCIE_PTX_C_DRX_N1<30>
PCIE_PTX_C_DRX_P1<30>

PCIE_PRX_DTX_N2<30>
PCIE_PRX_DTX_P2<30>
PCIE_PTX_C_DRX_N2<30>
PCIE_PTX_C_DRX_P2<30>

PCIE_PRX_DTX_N3<31>
PCIE_PRX_DTX_P3<31>
PCIE_PTX_C_DRX_N3<31>
PCIE_PTX_C_DRX_P3<31>

PCIE_PRX_DTX_N4<30>
PCIE_PRX_DTX_P4<30>
PCIE_PTX_C_DRX_N4<30>
PCIE_PTX_C_DRX_P4<30>

PCIE_PRX_DTX_N6<30>
PCIE_PRX_DTX_P6<30>
PCIE_PTX_C_DRX_N6<30>
PCIE_PTX_C_DRX_P6<30>

CLKREQ_EXP#<30>

CLK_PCIE_WLAN1#<30>
CLK_PCIE_WLAN1<30>

WLAN_CLKREQ1#<30>

CLK_PCIE_LAN#<31>
CLK_PCIE_LAN<31>

CLKREQ_LAN#<31>

PCIECLKREQ3#<30>

CLK_PCIE_WLAN#<30>
CLK_PCIE_WLAN<30>

PCIECLKREQ4#<30>

NEW CARD
WLAN
LAN
3G
X
TV TUNNER
X
X

+3VALW

+3VS

+3VS

+3VALW

+3VALW

+3VALW

+3VALW

C1058 0.1U_0402_10V6KC1058 0.1U_0402_10V6K

1 2

C1057 0.1U_0402_10V6KC1057 0.1U_0402_10V6K

1 2

C1059 0.1U_0402_10V6KC1059 0.1U_0402_10V6K

1 2

C1060 0.1U_0402_10V6KC1060 0.1U_0402_10V6K

1 2

C1061 0.1U_0402_10V6KC1061 0.1U_0402_10V6K

1 2

C1064 0.1U_0402_10V6KC1064 0.1U_0402_10V6K

1 2

C1062 0.1U_0402_10V6KC1062 0.1U_0402_10V6K

1 2

C1063 0.1U_0402_10V6KC1063 0.1U_0402_10V6K

1 2

C1065 0.1U_0402_10V6KC1065 0.1U_0402_10V6K

1 2

C1066 0.1U_0402_10V6KC1066 0.1U_0402_10V6K

1 2

R967 0_0402_5%R967 0_0402_5%

1 2

R968 0_0402_5%R968 0_0402_5%

1 2

R969 10K_0402_5%R969 10K_0402_5%

1 2

R970 0_0402_5%R970 0_0402_5%

1 2

R971 0_0402_5%R971 0_0402_5%

1 2

R973 10K_0402_5%R973 10K_0402_5%

1 2

R974 0_0402_5%R974 0_0402_5%

1 2

R976 0_0402_5%R976 0_0402_5%

1 2

R977 10K_0402_5%R977 10K_0402_5%

1 2

R978 0_0402_5%R978 0_0402_5%

1 2

R979 0_0402_5%R979 0_0402_5%

1 2

R980 10K_0402_5%R980 10K_0402_5%

1 2

R984 10K_0402_5%R984 10K_0402_5%

1 2

R981 0_0402_5%R981 0_0402_5%

1 2

R982 0_0402_5%R982 0_0402_5%

1 2

R986 10K_0402_5%R986 10K_0402_5%

1 2

R989 10K_0402_5%R989 10K_0402_5%

1 2

GPIO73 = NATIVE,3.3V,SUS

GPIO18 = NATIVE,3.3V,CORE

GPIO20 = NATIVE,3.3V,CORE

GPIO25 = NATIVE,3.3V,SUS

GPIO26 = NATIVE,3.3V,SUS

GPIO44 = NATIVE,3.3V,SUS

GPIO56 = NATIVE,3.3V,SUS

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6

CLK_PCIE_EXP_PCH#_R
CLK_PCIE_EXP_PCH_R

CLKREQ_EXP#

CLK_PCIE_MCARD_PCH#_R
CLK_PCIE_MCARD_PCH_R

CLK_PCIE_CARD_PCH#_R
CLK_PCIE_CARD_PCH_R

PCIECLKREQ4#

4

U46B

U46B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

NEW CARD

WLAN

LAN

MINI1

CR

PCI-E*

PCI-E*

MINI2

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

Link

Link

Controller

Controller

PEG_A_CLKRQ# / GPIO47

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

Clock Flex

Clock Flex

CLKOUTFLEX3 / GPIO67

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N

CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

LID_OUT#

B9

H14

C8

GPIO11 = NATIVE,3.3V,SUS

SMBCLK

SMBDATA

GPIO60 = NATIVE,3.3V,SUS

GPIO60

J14

SML0CLK

C6

SML0DATA

G8

GPIO74 = NATIVE,3.3V,SUS

GPIO74

M14

E10

G12

T13

T11

T9

H1

SML1CLK

SML1DATA

PEG_CLKREQ#

PEG_CLKREQ#

R962

R962

R963

R963

1 2

GPIO47 = 10Kohm PULL DOWN

CLK_PCIE_VGA#

AD43

CLK_PCIE_VGA

AD45

AN4
AN2

CLKOUT_DP_N

AT1

CLKOUT_DP_P

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

CLK_14M_PCH

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R983 90.9_0402_1%R983 90.9_0402_1%

AF38

T45

P43

T42

N50

1 2

R987

R987

1 2

R988

R988

1 2

22_0402_5%

22_0402_5%

22_0402_5%

22_0402_5%

EC_LID_OUT# < 37>

R959

R959
0_0402_5%

0_0402_5%
<BOM Structure>

<BOM Structure>

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

DTS , read from EC

PEG_CLKREQ# <19>

R96410K_0402_5% R96410K_0402_5%

CLK_PCIE_VGA# <19>

CLK_PCIE_VGA <19>

CLK_EXP# <5>
CLK_EXP <5>

CLK_DMI# <12>
CLK_DMI <12>

CLK_BUF_BCLK# <12>
CLK_BUF_BCLK <12>

CLK_BUF_DOT96# < 12>
CLK_BUF_DOT96 <12>

CLK_BUF_CKSSCD# <12>
CLK_BUF_CKSSCD <12>

CLK_14M_PCH <12>

CLK_PCI_FB <16>

CLK_PCI_DB <38>

CLK_14M_SIO <38>

EC_SMB_CK2

EC_SMB_DA2

+1.05VS

MB_CLK_S3

S

S

MB_DATA_S3

SMBCLK <10,11>

SMBDATA <10,11>

EC_SMB_CK2 <37>

EC_SMB_DA2 <37>

2

1 2

948 10K_0402_5%

948 10K_0402_5%

R

R

1 2

R

R

950 10K_0402_5%

950 10K_0402_5%

Q61A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q61A

6 1

2

Q61B

Q61B

3

5

4

SMB_CLK_S3

+3VS

SMB_DATA_S3

EC_THERMAL

+3VS

+3VS

Q62A

Q62A

6 1

5

2N7002DW-T/R7_SOT363-6

Q62B

Q62B

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

EC_SMB_DA2

EC_SMB_CK2

EMI REQUEST 0303

CLK_14M_PCHCLK_PCI_FB

R666

R666
33_0402_5%

33_0402_5%
@

@

1 2

C809

C809
22P_0402_50V8J

22P_0402_50V8J

@

@

1 2

+

S

MBDATA

S

ML0CLK

S

ML0DATA

ML1CLK

S

S

ML1DATA

PIO74

G

L

ID_OUT#

GPIO60

SMB_CLK_S3 <10,11,12,30>

MBCLK

S

3VS

DDR3*2 AND CLK GEN

SMB_DATA_S3 <10,11,12,30>

+3VS

R965

R965

2.2K_0402_5%

2.2K_0402_5%

2

R9720_0402_5%

R9720_0402_5%

@

@

1 2

R9750_0402_5%

R9750_0402_5%

@

@

1 2

R667

R667
33_0402_5%

33_0402_5%
@

@

C810

C810
22P_0402_50V8J

22P_0402_50V8J

@

@

SMB_EC_DA2_R

SMB_EC_CK2_R

1 2
949 2.2K_0402_5%

949 2.2K_0402_5%

R

R

1 2

R

R

951 2.2K_0402_5%

951 2.2K_0402_5%
1 2

R

R

952 2.2K_0402_5%

952 2.2K_0402_5%
1 2

R

R

953 2.2K_0402_5%

953 2.2K_0402_5%
1 2

954 2.2K_0402_5%

954 2.2K_0402_5%

R

R

1 2

R

R

955 2.2K_0402_5%

955 2.2K_0402_5%
1 2

956 10K_0402_5%

956 10K_0402_5%

R

R

1 2

R957 10K_0402_5%R957 10K_0402_5%

1 2

R958 10K_0402_5%R958 10K_0402_5%

SMBCLK

SMBDATA SMB_DATA_S3

R966

R966

2.2K_0402_5%

2.2K_0402_5%

SMB_EC_DA2_REC_SMB_DA2

SMB_EC_CK2_REC_SMB_CK2

XTAL25_IN

XTAL25_OUT

18P_0402_50V8J

18P_0402_50V8J

1

3VALW

+

R960

R960
0_0402_5%

0_0402_5%

@

@

1 2

@

@

1 2

0_0402_5%

0_0402_5%
R961

R961

SMB_EC_DA2_R <19,41>

Nvidia thermall sensor

SMB_EC_CK2_R <19,41>

1 2

R985 1M_0402_5%@ R985 1M_0402_5%@

Y8

@Y8

@

1 2

25MHZ_20P_1BG25000CK1A

25MHZ_20P_1BG25000CK1A

C1067

@C1067

@

1

2

SMB_CLK_S3

18P_0402_50V8J

18P_0402_50V8J

C1068

1

2

@C1068

@

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

IBEX-M(2/6)-PCI-E/SMBUS/CLK

IBEX-M(2/6)-PCI-E/SMBUS/CLK

NIWBA_LA5371P

1

14 52Tuesday, March 24, 2009

14 52Tuesday, March 24, 2009

14 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

4

3

2

1

D D

DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>

DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>

DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>

+1.05VS

1 2

R993 49.9_0402_1%R993 49.9_0402_1%

4mil width and place

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

within 500mil of the PCH

C C

SUS_PWR_DN_ACK<37>

+3VALW

B B

Checklist0.8：MEPWROK
can be connect to
PWROK if iAMT disable

R998 100K_0402_1%R998 100K_0402_1%

VGATE<51>

ICH_POK<37>

PM_DRAM_PWRGD<5>

+3VALW

R1008 10K_0402_5%R1008 10K_0402_5%

1 2

R1009 10K_0402_5%R1009 10K_0402_5%

1 2

AC_PRESENT<37>

+3VALW

R1012 8.2K_0402_1%R1012 8.2K_0402_1%

R1013 10K_0402_5%R1013 10K_0402_5%

R999 0_0402_5%

R999 0_0402_5%

R1001 0_0402_5%@R1001 0_0402_5%@

1 2

R1024 0_0402_5%@R1024 0_0402_5%@

PBTN_OUT#<37>

GPIO31 = GPI,3.3V,SUS

1 2

1 2

+3VS

R996

R996
10K_0402_5%

10K_0402_5%

12

1 2

1 2

R1003 10K_0402_5%

R1003 10K_0402_5%

R1006

R1006

10K_0402_5%

10K_0402_5%

1 2

R1010 0_0402_5%R1010 0_0402_5%

1 2

0_0402_5%

0_0402_5%

1 2

PM_DRAM_PWRGD

PM_RSMRST#

12

SUS_PWR_DN_ACK_R

AC_PRESENT_R

GPIO72

GPIO30 = GPI,3.3V,SUS

R1002

R1002

SYS_RST#

1 2

PBTN_OUT#

U46C

U46C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

FDI_CTX_PRX_N0

FDI_INT

WAKE#

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PCIE_WAKE#

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

GPIO32 = GPO,3.3V,CORE

GPIO61

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

System Power Management

System Power Management

PMSYNCH

SLP_LAN# / GPIO29

P8

F3

E4

H7

P12

K8

SLP_M#

N2

TP23

BJ10

GPIO29 = GPO,3.3V,SUS

F6

GPIO62

FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

1K_0402_5%

1K_0402_5%

1 2

R997

R997

PCIE_WAKE# <30,31>

1 2

R1000 10K_0402_5%R1000 10K_0402_5%

+3VALW

+3VS

GPIO61 = NATIVE,3.3V,SUS

GPIO62 = NATIVE,3.3V,SUS

SLP_S5# <37>

SLP_S4# <37>

SLP_S3# <37>

Can be left NC when IAMT is
not support on the platfrom

H_PM_SYNC <5>

If not using integrated
LAN,signal may be left as NC.

+3VS

PCH_ENBKL_R<29>

PCH_ENVDD_R< 29>

INV_PWM

EDID_CLK<29>
EDID_DATA<29>

12

R1308

R1308

2.37K_0402_1%

2.37K_0402_1%

LVDS_ACLK#<29>
LVDS_ACLK<29>

LVDS_A0#<29>
LVDS_A1#<29>
LVDS_A2#<29>

LVDS_A0<29>
LVDS_A1<29>
LVDS_A2<29>

LVDS_BCLK#<29>
LVDS_BCLK<29>

LVDS_B0#<29>
LVDS_B1#<29>
LVDS_B2#<29>

LVDS_B0<29>
LVDS_B1<29>
LVDS_B2<29>

DAC_BLU< 28>
DAC_GRN<28>
DAC_RED<28>

CRT_DDC_CLK<28>
CRT_DDC_DATA<28>

CRT_HSYNC<28>
CRT_VSYNC< 28>

PCH_ENBKL

PCH_ENVDD

1 2

R1306 10K_0402_5%R1306 10K_0402_5%

1 2

R1307 10K_0402_5%R1307 10K_0402_5%

T110 PADT110 PAD

DAC_BLU
DAC_GRN
DAC_RED

CRT_IREF

1K_0402_0.5%

1K_0402_0.5%

R1011

R1011

12

U46D

U46D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

DAC_BLU

DAC_GRN

DAC_RED

R1162 150_0402_1%UMA@R1162 150_0402_1%UMA@

R1186 150_0402_1%UMA@R1186 150_0402_1%UMA@

R1184 150_0402_1%UMA@R1184 150_0402_1%UMA@

LVDS

LVDS

CRT

CRT

CRT OUT

1 2

1 2

1 2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N

Digital Display Interface

Digital Display Interface

DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

R1309 10K_0402_5%R1309 10K_0402_5%

UMA@

UMA@

R1310

R1310

2.2K_0402_5%

2.2K_0402_5%

HDMICLK_NB
HDMIDAT_NB

12

+3VS

12

12

UMA@

UMA@
R1311

R1311

2.2K_0402_5%

2.2K_0402_5%

HDMICLK_NB <27>
HDMIDAT_NB <27>

TMDS_B_HPD# <27>

TMDS_B_DATA2# <27>
TMDS_B_DATA2 <27>
TMDS_B_DATA1# <27>
TMDS_B_DATA1 <27>
TMDS_B_DATA0# <27>
TMDS_B_DATA0 <27>
TMDS_B_CLK# <27>
TMDS_B_CLK <27>

HDMI

RSMRST circuit

R1014

@R1014

@
0_0402_5%

0_0402_5%

1 2

C

C

PM_RSMRST#

1

3

E

EC_RSMRST#<37>

A A

5

BAV99DW-7_SOT363

BAV99DW-7_SOT363

D36B

D36B

R1016

R1016

1 2

2.2K_0402_5%

2.2K_0402_5%

4

E

Q3

Q3
MMBT3906_SOT23-3

MMBT3906_SOT23-3

B

B

1 2

2

R1015 4.7K_0402_5%R1015 4.7K_0402_5%

1

2

4

5

D36A

D36A
BAV99DW-7_SOT363

BAV99DW-7_SOT363

6

3

+3VALW

SLP_S3#

SLP_S4#

SLP_S5#

3

1 2

R1004 10K_0402_5%@R1004 10K_0402_5%@

1 2

R1005 10K_0402_5%@R1005 10K_0402_5%@

1 2

R1007 10K_0402_5%@R1007 10K_0402_5%@

Security Classification

Security Classification

Security Classification

2008/10/31 2009/10/31

2008/10/31 2009/10/31

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/31 2009/10/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

IBEX-M(3/6)-DMI/GPIO/LVDS

IBEX-M(3/6)-DMI/GPIO/LVDS

NIWBA_LA5371P

1

15 52Tuesday, March 24, 2009

15 52Tuesday, March 24, 2009

15 52Tuesday, March 24, 2009

0.2

0.2

0.2

5

D D

PCI_CBE#3

GPIO18 = NATIVE,5V,CORE
GPIO52 = NATIVE,5V,CORE
GPIO54 = NATIVE,5V,CORE

C C

GPIO2 = GPI,5V,CORE
GPIO3 = GPI,5V,CORE
GPIO4 = GPI,5V,CORE
GPIO5 = GPI,5V,CORE

DGPU_SELECT#<26,28,29>

PCI_RST#<37,38>

GNT2

Default-Internal pull up

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

B B

CLK_PCI_LPC<37>
CLK_PCI_FB<14>

PCI_REQ0#

PCI_PIRQF#
PCI_REQ3#

PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCI_PIRQH#

PCI_STOP#
PCI_IRDY#
PCI_PIRQD#

A A

DGPU_SELECT#

PCI_GNT3#

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

R1051 1K_0402_5%@R1051 1K_0402_5%@

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

*

PCI_PME#<37>

1 2
1 2

RP3

RP3

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP5

RP5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP7

RP7

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#
DGPU_SELECT#
PCI_REQ3#

PCI_GNT0#
PCI_GNT1#

PCI_GNT3#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_SERR#
PCI_PERR#

PCI_IRDY#

PCI_DEVSEL#
PCI_FRAME#

PCI_LOCK#

PCI_STOP#
PCI_TRDY#

PLT_RST#

R1044

R1044

47_0402_1%

47_0402_1%
47_0402_1%

47_0402_1%

R1045

R1045

+3VS +3VS

PCI_PIRQG#
PCI_PIRQC#PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQE#

PCI_DEVSEL#
PCI_LOCK#
PCI_SERR#
PCI_PERR#

*

5

U

U

46E

46E

H40

D0

A

N34

D1

A

C44

A

D2

A38

D3

A

C36

A

D4

J34

A

D5

A40

A

D6

D45

A

D7

E36

A

D8

H48

D9

A

E40

D10

A

C40

A

D11

M48

A

D12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

RP4

RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP6

RP6
1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

V_CE#0

N

V_CE#1

N
N

V_CE#2
V_CE#3

N

N

V_DQS0

N

V_DQS1

N

V_DQ0 / NV_IO0
V_DQ1 / NV_IO1

N

V_DQ2 / NV_IO2

N
N

V_DQ3 / NV_IO3

N

V_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

NV_ALE
NV_CLE

NV_RCOMP

PCI

PCI

USB

USB

BUF_PLT_RST#<5,19,30,31>

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

4

AY9
BD1
AP15
BD8

C

AV9

implemented, the Braidwood interface

BG8

signals can be left as No Connect (NC).

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ALE

BD3

NV_CLE

AY6

NV_RCOMP

AU2

AV7

AY8
AY5

AV11
BF5

USB20_N0

H18

USB20_P0

J18

USB20_N1

A18

USB20_P1

C18

USB20_N2

N20

USB20_P2

P20

USB20_N3

J20

USB20_P3

L20

USB20_N4

F20

USB20_P4

G20

USB20_N5

A20

USB20_P5

C20

USB20_N6

M22

USB20_P6

N22

USB20_N7

B21

USB20_P7

D21

USB20_N8

H22

USB20_P8

J22

USB20_N9

E22

USB20_P9

F22

USB20_N10

A22

USB20_P10

C22

USB20_N11

G24

USB20_P11

H24

USB20_N12

L24

USB20_P12

M24

USB20_N13

A24

USB20_P13

C24

USBRBIAS

B25

D25

Within 500 mils minimum spacing to other signal
is 15mil

USB_OC#0

N16

USB_OC#1

J16

USB_OC#2

F16

USB_OC#3

L16

USB_OC#4

E14

USB_OC#5

G16

USB_OC#6

F12

USB_OC#7

T15

PCI_GNT0#

PCI_GNT1#

R1046 1K_0402_5%

R1046 1K_0402_5%

R1047 1K_0402_5%@R1047 1K_0402_5%@

Boot BIOS Strap

PCI_GNT1#PCI_GNT0#

0

0

1

1 2

R1049 0_0402_5%R1049 0_0402_5%

@

@

4

12

R1052

R1052
100K_0402_5%

100K_0402_5%

U49

U49

4

PIO8

G
Weak internal PU, don't PD

heck list Rev0.8 section1.23.2 If not

GPIO15

*

：

I

L

ntel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

H：Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

it have weak internal PU 20K

GPIO27
Default：Do not connect(floating)

High：Enables the internal VccVRM
to have a clean supply for analog
rails. no need to use on board
filter circuit.

12

R1043 22.6_0402_1%R1043 22.6_0402_1%

@

@

1 2

1 2

R1032

R1032

32.4_0402_1%

32.4_0402_1%

USB20_N0 <40>
USB20_P0 <40>
USB20_N1 <34>
USB20_P1 <34>
USB20_N2 <40>
USB20_P2 <40>

USB20_N4 <40>
USB20_P4 <40>
USB20_N5 <33>
USB20_P5 <33>

USB20_N8 <30>
USB20_P8 <30>
USB20_N9 <30>
USB20_P9 <30>
USB20_N10 <30>
USB20_P10 <30>
USB20_N11 <40>
USB20_P11 <40>

USB20_N13 <30>
USB20_P13 <30>

1 2

GPIO1 = GPI,3.3V,CORE
GPIO6 = GPI,3.3V,CORE
GPIO7 = GPI,3.3V,CORE
GPIO8 = GPO,3.3V,SUS
GPIO12 = GPI,3.3V,SUS

RIGHT USB

LEFT USB

USB Camera

RIGHT USB

CARD READER

WLAN

TV

EXPRESS

Bluetooth

3G CARD

USB_OC#0 <34,40>

USB_OC#2 <34,40>

DGPU_PWR_EN#<42>

Intel Anti-Theft Techonlogy

NV_ALE

Boot BIOS
Location

LPC

0

1

Reserved(NAND)

0

PCI

11

SPI

*

+3VS

3

1

G

A

Y

2

B

P

5

PLT_RST#

NV_ALE

NV_CLE

3

3VS

+

+3VALW

+3VALW

+3VALW

PCH_TEMP_ALERT#<37>

DIS@

DIS@

R992 0_0402_5%

R992 0_0402_5%

SUSP#<30,37,42,47,49>

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

1 2

R994 0_0402_5%

R994 0_0402_5%

1 2

HYBRID@

HYBRID@

RP1

RP1
1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RP2

RP2
1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

High=Enabled

Low=Disable(floating)

R1048 1K_0402_5%@R1048 1K_0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

R1050 1K_0402_5%@R1050 1K_0402_5%@

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPIO0 = GPI,3.3V,CORE

1 2

R

101710K_0402_5%R101710K_0402_5%

1 2

R

101810K_0402_5%R101810K_0402_5%

1 2

R

C_SCI#<37>

E

E

C_SMI#< 37>

PUSB#<30>

C

DGPU_RST#<19>

DGPU_PWROK<47,49>

GPIO27 if pull down to turn off 1.8V VR

DGPU_PWR_EN#<42>

+3VALW

*

+1.8VS

+3VS

101910K_0402_5%R101910K_0402_5%

1 2

R102010K_0402_5% R102010K_0402_5%

1 2

R102310K_0402_5% R102310K_0402_5%

1 2

R102710K_0402_5% R102710K_0402_5%

R102910K_0402_5% R102910K_0402_5%

R103110K_0402_5% R103110K_0402_5%

1 2

R103410K_0402_5% R103410K_0402_5%

1 2

R103510K_0402_5% R103510K_0402_5%

1 2

R103610K_0402_5% R103610K_0402_5%

1 2

R103710K_0402_5% R103710K_0402_5%

1 2

R103810K_0402_5% R103810K_0402_5%

1 2

R103910K_0402_5% R103910K_0402_5%

PCH_TEMP_ALERT#

1 2

R1040 10K_0402_5%R1040 10K_0402_5%

+3VALW

NV_ALE
Enable Intel Anti-Theft

Technology：8.2K PU to +3VS

Disable Intel Anti-Theft
Technology：floating(internal PD)

NV_CLE

DMI termination voltage.
weak internal PU, don't PD

G

PIO0

G

PIO1

G

PIO6

C_SCI#

E

E

C_SMI#

PUSB#

C

G

PIO15

DGPU_RST#

DGPU_PWROK

GPIO22

GPIO28

GPIO34

12

GPIO35

12

DGPU_PWR_EN#

GPIO37

GPIO38

GPIO39

GPIO45

GPIO46

GPIO48

GPIO57

VGA_EN <48>

2008/08/12 2009/08/12

2008/08/12 2009/08/12

2008/08/12 2009/08/12

U

U

46F

46F

Y3

MBUSY# / GPIO0

B

C38

ACH1 / GPIO1

T

D37

T

ACH2 / GPIO6

J32

T

ACH3 / GPIO7

F10

PIO8

G

K9

L

AN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

IBEXPEAK-M_FCBGA1071

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

+3VS

+3VS

+3VALW

2

LKOUT_PCIE6N

C
C

LKOUT_PCIE6P

C

LKOUT_PCIE7N

C

LKOUT_PCIE7P

A

20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

1 2

R1022 10K_0402_5%R1022 10K_0402_5%

1 2

R1033 1K_0402_5%R1033 1K_0402_5%

1 2

R1182 10K_0402_5%R1182 10K_0402_5%

R1021 10K_0402_5%R1021 10K_0402_5%

@

@

1 2

R1041 10K_0402_5%

R1041 10K_0402_5%

@

@

1 2

R1042 10K_0402_5%

R1042 10K_0402_5%

PCH_TEMP_ALERT#

12

1

AH45

PECI

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

TP24

AH46

AF48
AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

AF13

M18

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

+

3VS

R

R
10K_0402_5%

10K_0402_5%

1 2

H_PECI

KB_RST#

H_THERMTRIP#_L

INT3_3V#

TP24

1025

1025

ATEA20 < 37>

G

CLK_CPU_BCLK# <5>

CLK_CPU_BCLK <5>

H_PECI <5>

KB_RST# <37>

H_CPUPWRGD <5>

1 2

54.9_0402_1%

54.9_0402_1%

56_0402_5%

56_0402_5%

R1028

R1028

R1030

R1030

12

USB PORT LIST

KB_RST#

H_THERMTRIP# <5>

+VCCP

DEVICEPORT

RIGHT SIDE0

1

LEFT SIDE
CMOS

2

DGPU_PWROK

DGPU_PWR_EN

3
4

RIGHT SIDE

5

CARD READER

6

DGPU_RST#

EC_SCI#

EC_SMI#

7

10
11

WIRELESS8
TV TUNNER9
NEW CARD
BT

12

3G

13

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

IBEX-M(4/6)-PCI/USB/RSVD

IBEX-M(4/6)-PCI/USB/RSVD

NIWBA_LA5371P

1

16 52Tuesday, March 24, 2009

16 52Tuesday, March 24, 2009

16 52Tuesday, March 24, 2009

+3VS

12

R1026

R1026
10K_0402_5%

10K_0402_5%

0.1

0.1

0.1