COMPAL LA-5371P Schematics

A

1 1

B

C

D

E

Compal Confidential

Schematics Document

2 2

Arrandale/Clarksfield

with Intel IBEX PEAK-M core logic

NIWBA

3 3

REV:0.1

4 4

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2008/03/25 2008/04/

C

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Cover Sheet

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

NIWBA_LA5371P

1 52Tuesday, March 24, 2009

E

1 52Tuesday, March 24, 2009

0.1

A

ompal confidential

C

F

ile Name :

V

RAM 64*16

1 1

DDR3*8

page20

PCI-E X16

NVidia N10M-GS

B

ZZ1

Z

1

5.6W_PCB_LA5371P

C

i

ntel

Arrandale/Clarksfield

(UMA/DIS) (DIS)

POWER BD

ower on X1

P L

ED X1 (G) :POWER N

OVO X1

Clock Generator

ICS9LRS3199AKLFT

page12

D

lide Bar LED X 10 (B)

S USER-DEFINED (W) DOLBY (W) LED X 3 WIRELESS LED (G) B

LUETOOTH LED (G) 3G LED (G) HDD LED (G)

E

RIGHT BD VOLUME UP X1 V

OLUME DOWN X1 MUTE X1 MUTE LED X1(G)

Socket-rPGA989

37.5mm*37.5mm

FDI *8

page5~9

DMI *4

Dual Channel

DDR3-800(1.5V) DDR3-1067(1.5V)

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 8G

page 10,11

HDMI CONN

page26

NVidia N10P-GS

switchable

graphic

page26

page19~25

level shift IC

8110T

page27

100MHz

2.7GT/s

switchable

CRT cable

page28

2 2

LVDS Connector

page29

PCI Express Mini card Slot 1

page30

PCI Express Mini card Slot 2

page30

graphic

page28

switchable

graphic

page29

6*PCI-E BUS

Intel Ibex Peak M

FCBGA 951

25mm*25mm

page 13~18

AZALIA

14*USB2.0

6*SATA serial

SPK amplifier

page35

WOOFER amplifier

Audio Codec

Realtek ALC272

page35

CMOS Camera

page40

2Channel Speaker

page36

1Channel Speaker

HP X 1+ MIC_Ext X1

2Channel MIC_Int

page36

PCI Express

SPI ROM BIOS

page38

LPC BUS

BlueTooth CONN

page40

Mini card Slot 3

3 3

page30

USB CONN X1

page40

EC

BCM57790/57780

SIM Card

page30

10/100/1G LAN

page31

RJ45 CONN

page32

Touch Pad

4 4

A

B

ENE KB926D

page37

New Card X1

M-PCIE CONN X 3

Int.KBD

page38

page39

SPI ROM

page39

SATA HDD CONN

SATA ODD CONN

Security Classification

2008/03/24 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

page29

Realtek 5159E MS/MS

page29

pro/SD/SD pro/mmc/XD

page33

ESATA HDD AND USB CONN

page34

Compal Electronics, Inc.

Title

Size Document Numbe r Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

NIWBA_LA5371P

E

2 52Tuesday, March 24, 2009

0.1

A

DR3 Voltage Rails

D

power plane

1 1

+B

State

+5VALW

+3VALW

+1.5V

B

MBUS Control Table

S

5VS

+

+3VS

+

1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+1.8VS

+0.75VS

+1.05VS

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

C

S

OURCE

KB926

+3VALW

KB926

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

D

RAM M2 BATT KE926 SODIMM CLK CHIP

X

V

+3VALW

X

V

3VALW

+

X

V V

+3VS

X

+3VS

X

V

+3VALW

N

WLAN WWAN

X

X X

10x Thermal Sensor

X

X X

X

V

+3VS

N

10x

X

C

ap sensor

board

X

XX

X

V

+3VS

E

N

EW

CARD

X

V

+3VS

XXX X X X X X

P

CH

X

V

+3VALW

X

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

O

X

O

X X

X

OO

X

X X X

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

@ FUNCTION

EVT NON-USE

45@

GIGA@ 100@

3 3

ARRAY@ MONO@

S512@

H512@

S1024@

H1024@

X76@

M1@ (DDR M1 MODE)

3G@ (3G MODE)

10M@

10P@

4 4

UMA@

DIS@

(45 BOM)

(GIGA LAN)

(NON TV POWER SW)

(ARRAY MIC)

FOR X76 BOM

(X76 BOM)

FOR 10M CHIP

FOR 10P CHIP

FOR Auberndale

FOR Auberndale/Clarksfield

(100 LAN)

TVSW@NO_TVSW@

(TV POWER SW)

PCIE PORT LIST

DEVICEPORT

USB PORT LIST

DEVICEPORT

(MONO MIC)

1

NEW CARD 2 3 4

LAN

3G 5 6

TV TUNNER 7 8

0 1WLAN 2 3 4 5 6 7

10 11 12 13

LEFT SIDE RIGHT SIDE CMOS

RIGHT SIDE CARD READER

WIRELESS8 TV TUNNER9 NEW CARD BT

3G

VGA@ FOR NVIDIA PART

A

Security Classification

2008/03/24 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

C

2008/03/24 2008/04/

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numbe r Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Notes List

NIWBA_LA5371P

E

3 52Tuesday, March 24, 2009

0.1

A

GPIO I/O ACTIVE Function Description

G

PIO0

GPIO1

GPIO2

1 1

GPIO3

GPIO4

N

/A

I

N

OUT

N/A

-

H

Hot plug detect for IFP link C

Panel Back-Light brightness(PWM capable)

Panel Power Enable

Panel Back-Light On/Off (PWM)

B

C

P

erformance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N10x GPIO)

P

N 128bit 1024MB DDR3

N10P-GE 128bit 1024MB DDR3

roducts

10P-GS

D

3.09

3.05

FBVDDQ (

GPU+Mem)

(1.5V)(1.5V)

4.09

6.14

4.09 6.14

G (

(W) (W)

21.07

20.97

M

PU

4) (1,5) (6)

emNVCLK

/MCLK NVVDD

(MHz)

6.67

6.73

TBD

V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(

TBD

18.25

17.34

TBD

19.17

17.25

F

2.06

2.03

BVDD

P

CI Express I/O and

(1.05V)

850 75 0.14

0.89

0.88840

PLLVDD

75 0.14

E

I/O and PLLVDD

63 0.07

O

ther

(3.3V)(1.05V)(1.8V)

55 0.18

GPIO5

GPIO6

GPIO7

OUT

-

GPU VID0

GPU VID1

GPU VID2

N10P-LP 128bit 1024MB DDR3

15.48

6.44

TBD

13.95

11.86

1.90

2.85

3.99

5.99

810

0.85

75 0.14

63 0.07

55 0.18

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

2 2

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

3 3

I/O

OUT

I/O

IN

OUT

IN

OUT

IN

I/O

L

Thermal Catastrophic Overtemp

Thermal Alert

Memory VREF switch

L

-

SLI raster sync

AC power detect pin

MEM_VID orPower supply control

- Power supply control

-

Hot plug detect for IFP Link E

Programmable Fan Control

-

Hot plug detect for IFP Link D

-

Hot plug detect for IFP link F

SLI swap ready signal

GPU (4) (1,5) (6)

Products

N10M-GE 64bit 512MB DDR3

N10M-GS 64bit 512MB DDR3

N10M-LP 64bit 512MB DDR3

(W) (W)

13.36

14.29

8.28

Power Sequence

(+3VS)

(1.1VS)

VDD33

PEX_VDD

Mem

2.93

3.10

2.91

NVCLK /MCLK NVVDD

(MHz)

TBD

(V) (A) (W) (A) (W)

TBD

11.89

TBD

11.53

TBD

6.60

10.70

11.53

5.61

FBVDD

0.66

0.70

0.62

FBVDDQ (GPU+Mem) (1.5V)(1.5V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

0.99

2.16

1.05

2.28 3.42

0.93

2.20

The ramp time for any rail must be more than 40us

PEX_VDD can ramp up any time

tNVVDD

PCI Express I/O and (1.05V)

3.24

792 75 0.14

0.83

0.86817

3.3

782

0.82

PLLVDD

75 0.14

I/O and PLLVDD

63 0.07

Other

(3.3V)(1.05V)(1.8V)

100 0.33

(+VGA_CORE)

NVVDD

GPIO5GPIO6 N10M-GS N10P-GS

GPU_VID11GPU_VID011VGA_CORE P-State

0 0.8V

0

0.85V

0.9V

4 4

A

12

0, 10

IFPAB_IOVDD

(1.8VS)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

C

FBVDDQ

Compal Secret Data

2009/03/16 2010/03/15

Compal Secret Data

Deciphered Date

D

tNV-IFPAB_IOVDD

tNV-FBVDDQ

B

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Numbe r Rev

Compal Electronics, Inc.

VGA Notes List

KIWB1/B2_LA4602P

4 52Tuesday, March 24, 2009

E

4 52Tuesday, March 24, 2009

0.1

5

4

3

2

1

D D

Layout rule：10mil width trace length < 0.5", spacing 20mil

JCPU1B

COMP3

R83320_0402_1% R83320_0402_1%

1 2

COMP2

R83420_0402_1% R83420_0402_1%

1 2

COMP1

R83549.9_0402_1% R83549.9_0402_1%

1 2

COMP0

R83749.9_0402_1% R83749.9_0402_1%

1 2

TP_SKTOCC#

H_CATERR#

+VCCP

H_PECI<16>

+VCCP

H_PROCHOT#<51>

H_THERMTRIP#<16>

C C

+VCCP

+1.5V

R855

4.75K_0402_1%

1 2

1.07V

B B

VDDPW RGOOD_R

12

R860

R860 12K_0402_1%

12K_0402_1%

H_CPUPW RGD<16>

FROM POWER VTT POWER GOOD SIGNAL

H_PM_SYNC<15>

PM_DRAM_PW RGD<15>

VCCP_POK<49>

BUF_PLT_RST#<16,19,30,31>

R841 0_0402_5%R841 0_0402_5%

1.5K_0402_5%

12

R84050_04 02_1% R84050_0402_1%

1 2

R842 68_0402_5%R842 68_0402_5%

R850

1 2

R852

1 2

R857

1 2

R858

1 2

R861

1 2

H_PECI_ISO

12

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#_R

12

R84868_0402_5% R84868_0402_5%

H_PM_SYNC_R

0_0402_5%

VCCPW RGOOD_1

0_0402_5%

VCCPW RGOOD_0

0_0402_5%

VDDPW RGOOD_R

0_0402_5%

PLT_RST#_R

12

R862

R862 750_0402_1%

750_0402_1%

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_r PGA,R1P0

MISC THERMAL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PM_EXT_TS#[0] PM_EXT_TS#[1]

PRDY# PREQ#

TCK TMS

TRST#

TDI

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

AR30 AT30

CLK_EXP

E16

CLK_EXP#

D16

A18 A17

F6

SM_RCOMP0

AL1

SM_RCOMP1

AM1

SM_RCOMP2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#1

AP15

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI

AT29

XDP_TDO

AR27 AR29

R853 0_0402_5%R853 0_0402_5%

AP29

XDP_DBRESET#

AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

pins unused by Clarksfield on the rPGA989 Package

1 2

R844 0_0402_5%R844 0_0402_5%

12

CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16>

CLK_EXP <14> CLK_EXP# <14>

DRAMRST# < 10,11>

PM_EXTTS#1_R <10,11>

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PM_EXTTS#0

PM_EXTTS#1

XDP_PREQ#

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

XDP_DBRESET#

1 2

R836 100_0402_1%R 836 100_0402_1%

1 2

R838 24.9_0402_1%R838 24.9_0402_1%

1 2

R839 130_0402_1%R 839 130_0402_1%

Layout Note:Please these resistors near Processor

1 2

R843 10K_0402_5%R843 10K_0402_5%

1 2

R845 10K_0402_5%R845 10K_0402_5%

R846 51_0402_1%@R846 51_0402_1%@

1 2

R847 51_0402_1%@R847 51_0402_1%@

1 2

R849 51_0402_1%@R849 51_0402_1%@

1 2

R851 51_0402_5%R851 51_0402_5%

1 2

R854 51_0402_1%@R854 51_0402_1%@

1 2

R856 51_0402_5%R856 51_0402_5%

1 2

R859

1 2

1K_0402_5%@

+VCCP

+3VS

CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3

Address:100_1100

FAN1 Conn

+VCC_FAN1

EN_FAN1<37>

EN_FAN1

FAN +5VS DROOP

A A

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

+VCC_FAN1

R863 100_0402_5%R863 100_0402_5%

1 2

FAN_SPEED1<37>

+5VS

1

C865

C865 2200P_0402_50V7K

2200P_0402_50V7K

2

R864

10K_0402_5%

C868

1000P_0402_50V7K

C868

C864 10U_0805_10V4ZC864 10U _0805_10V4Z

1 2

U41

1

VEN

2

VIN

3

VO

4

VSET

G990P11U_SO8

+3VS

12

+VCC_FAN1

1

2

Title

Size Document Numb er Rev

Custom

Date: Sheet of

8

GND

7

GND

6

GND

5

GND

+VCC_FAN1

Clarksfiel(1/5)-Thermal/XDP

+5VS

12

@

@ D34

D34 1SS355TE-17_SOD323-2

1SS355TE-17_SOD323-2

D35 BA S16_SOT23-3@D35 BA S16_SOT23-3@

1 2

C866 1U_0603_10V4ZC866 1U_0603_10V4Z

1 2

C867 0.1U_0402_16V4ZC867 0.1U_0402_16V4Z

1 2

40mil

Compal Electronics, Inc.

JP1

1

2

3

4

GND

5

GND

E&T_3801-F03N-01RME@

NIWBA_LA5371P

1

0.2

5 52Tuesday, March 24, 2009

5

4

ayout rule

L

：

race

t

3

2

1

length < 0.5"

J

CPU1A

D

MI_CRX_PTX_N0< 15>

D

MI_CRX_PTX_N1< 15>

D

MI_CRX_PTX_N2< 15> MI_CRX_PTX_N3< 15>

D

MI_CRX_PTX_P0<15>

DMI_CRX_PTX_P1<15>

D D

DMI_CRX_PTX_P2<15> DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N 0<15> DMI_CTX_PRX_N 1<15> DMI_CTX_PRX_N 2<15> DMI_CTX_PRX_N 3<15>

DMI_CTX_PRX_P0<15> DMI_CTX_PRX_P1<15> DMI_CTX_PRX_P2<15> DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15> FDI_CTX_PRX_N1<15> FDI_CTX_PRX_N2<15> FDI_CTX_PRX_N3<15> FDI_CTX_PRX_N4<15> FDI_CTX_PRX_N5<15> FDI_CTX_PRX_N6<15> FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15> FDI_CTX_PRX_P1<15> FDI_CTX_PRX_P2<15> FDI_CTX_PRX_P3<15> FDI_CTX_PRX_P4<15> FDI_CTX_PRX_P5<15>

C C

FDI_CTX_PRX_P6<15> FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15> FDI_LSYNC1<15>

B B

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

A24

D

MI_RX#[0]

C23

D

MI_RX#[1]

B22

MI_RX#[2]

D

A21

MI_RX#[3]

D

B24

D

MI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_r PGA,R1P0

DMI Intel(R) FDI

P

EG_ICOMPI

P

EG_ICOMPO

P

EG_RCOMPO

P

EG_RBIAS

EG_RX#[0]

P P

EG_RX#[1]

P

EG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

E

XP_ICOMPI

B26 A26 B27

E

XP_RBIAS

A25

P

CIE_CRX_GTX_N15

K35

CIE_CRX_GTX_N14

P

J34

P

CIE_CRX_GTX_N13

J33

P

CIE_CRX_GTX_N12

G35

PCIE_CRX_GTX_N11

G32

PCIE_CRX_GTX_N10

F34

PCIE_CRX_GTX_N9

F31

PCIE_CRX_GTX_N8

D35

PCIE_CRX_GTX_N7

E33

PCIE_CRX_GTX_N6

C33

PCIE_CRX_GTX_N5

D32

PCIE_CRX_GTX_N4

B32

PCIE_CRX_GTX_N3

C31

PCIE_CRX_GTX_N2

B28

PCIE_CRX_GTX_N1

B30

PCIE_CRX_GTX_N0

A31

PCIE_CRX_GTX_P15

J35

PCIE_CRX_GTX_P14

H34

PCIE_CRX_GTX_P13

H33

PCIE_CRX_GTX_P12

F35

PCIE_CRX_GTX_P11

G33

PCIE_CRX_GTX_P10

E34

PCIE_CRX_GTX_P9

F32

PCIE_CRX_GTX_P8

D34

PCIE_CRX_GTX_P7

F33

PCIE_CRX_GTX_P6

B33

PCIE_CRX_GTX_P5

D31

PCIE_CRX_GTX_P4

A32

PCIE_CRX_GTX_P3

C30

PCIE_CRX_GTX_P2

A28

PCIE_CRX_GTX_P1

B29

PCIE_CRX_GTX_P0

A30

PCIE_CTX_GRX_C_N 15

L33

PCIE_CTX_GRX_C_N 14

M35

PCIE_CTX_GRX_C_N 13

M33

PCIE_CTX_GRX_C_N 12

M30

PCIE_CTX_GRX_C_N 11

L31

PCIE_CTX_GRX_C_N 10

K32

PCIE_CTX_GRX_C_N 9

M29

PCIE_CTX_GRX_C_N 8

J31

PCIE_CTX_GRX_C_N 7

K29

PCIE_CTX_GRX_C_N 6

H30

PCIE_CTX_GRX_C_N 5

H29

PCIE_CTX_GRX_C_N 4

F29

PCIE_CTX_GRX_C_N 3

E28

PCIE_CTX_GRX_C_N 2

D29

PCIE_CTX_GRX_C_N 1

D27

PCIE_CTX_GRX_C_N 0

C26

PCIE_CTX_GRX_C_P 15

L34

PCIE_CTX_GRX_C_P 14

M34

PCIE_CTX_GRX_C_P 13

M32

PCIE_CTX_GRX_C_P 12

L30

PCIE_CTX_GRX_C_P 11

M31

PCIE_CTX_GRX_C_P 10

K31

PCIE_CTX_GRX_C_P 9

M28

PCIE_CTX_GRX_C_P 8

H31

PCIE_CTX_GRX_C_P 7

K28

PCIE_CTX_GRX_C_P 6

G30

PCIE_CTX_GRX_C_P 5

G29

PCIE_CTX_GRX_C_P 4

F28

PCIE_CTX_GRX_C_P 3

E27

PCIE_CTX_GRX_C_P 2

D28

PCIE_CTX_GRX_C_P 1

C27

PCIE_CTX_GRX_C_P 0

C25

R

865 49.9_0402_1%

1 2

866 750_0402_1%

R

1 2

P

CIE_CRX_GTX_N[0..15] < 19>

PCIE_CRX_GTX_P[0..15] <19>

PCIE Lane Numbers Reversed CFG3-PCI Express Static Lane Reversal

VGA@

C869 0.1U_0402_10V6KC869 0.1U_0402_10V6K

1 2

C870 0.1U_0402_10V6KC870 0.1U_0402_10V6K

1 2

C871 0.1U_0402_10V6KC871 0.1U_0402_10V6K

1 2

C872 0.1U_0402_10V6KC872 0.1U_0402_10V6K

1 2

C873 0.1U_0402_10V6KC873 0.1U_0402_10V6K

1 2

C874 0.1U_0402_10V6KC874 0.1U_0402_10V6K

1 2

C875 0.1U_0402_10V6KC875 0.1U_0402_10V6K

1 2

C876 0.1U_0402_10V6KC876 0.1U_0402_10V6K

1 2

C877 0.1U_0402_10V6KC877 0.1U_0402_10V6K

1 2

C878 0.1U_0402_10V6KC878 0.1U_0402_10V6K

1 2

C879 0.1U_0402_10V6KC879 0.1U_0402_10V6K

1 2

C880 0.1U_0402_10V6KC880 0.1U_0402_10V6K

1 2

C881 0.1U_0402_10V6KC881 0.1U_0402_10V6K

1 2

C882 0.1U_0402_10V6KC882 0.1U_0402_10V6K

1 2

C883 0.1U_0402_10V6KC883 0.1U_0402_10V6K

1 2

C884 0.1U_0402_10V6KC884 0.1U_0402_10V6K

1 2

C885 0.1U_0402_10V6KC885 0.1U_0402_10V6K

1 2

C886 0.1U_0402_10V6KC886 0.1U_0402_10V6K

1 2

C887 0.1U_0402_10V6KC887 0.1U_0402_10V6K

1 2

C888 0.1U_0402_10V6KC888 0.1U_0402_10V6K

1 2

C889 0.1U_0402_10V6KC889 0.1U_0402_10V6K

1 2

C890 0.1U_0402_10V6KC890 0.1U_0402_10V6K

1 2

C891 0.1U_0402_10V6KC891 0.1U_0402_10V6K

1 2

C892 0.1U_0402_10V6KC892 0.1U_0402_10V6K

1 2

C893 0.1U_0402_10V6KC893 0.1U_0402_10V6K

1 2

C894 0.1U_0402_10V6KC894 0.1U_0402_10V6K

1 2

C895 0.1U_0402_10V6KC895 0.1U_0402_10V6K

1 2

C896 0.1U_0402_10V6KC896 0.1U_0402_10V6K

1 2

C897 0.1U_0402_10V6KC897 0.1U_0402_10V6K

1 2

C898 0.1U_0402_10V6KC898 0.1U_0402_10V6K

1 2

C899 0.1U_0402_10V6KC899 0.1U_0402_10V6K

1 2

C900 0.1U_0402_10V6KC900 0.1U_0402_10V6K

1 2

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0

+V_DDR_CPU _REF1

FOR ES1 SAMPLE ONLY

PCIE_CTX_GRX_N[0..15 ] <19>

PCIE_CTX_GRX_P[0..15] <19>

CFG Straps for PROCESSOR

CFG0

PCI-Express Configuration Select

CFG0

Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

1 2

R873 3.01K_0402_1%@R873 3.01K_0402_1%@

1: Single PEG 0: Bifurcation enabled

10=2*8 PEG

R867

@ R867

@

R871

R871 0_0402_5%

0_0402_5%

1 2 1 2

R872

R872 0_0402_5%

0_0402_5%

V_DDR_CPU_R EF0

+

1 2

3.01K_0402_1%

H_RSVD17_R

@

H_RSVD18_R

@

CFG0

CFG3 CFG4

CFG7

J

CPU1E

AP25

SVD1

R

AL25

SVD2

R

AL24

R

SVD3

AL22

R

SVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_r PGA,R1P0

RSVD_NCTF_37

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD_TP_59

RESERVED

RSVD_TP_60

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

R

SVD32

R

SVD33

SVD34

R R

SVD35

RSVD36

RSVD38 RSVD39

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53

RSVD58

KEY RSVD62 RSVD63 RSVD64 RSVD65

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

RSVD64_R RSVD65_R

R868

R868 0_0402_5%

0_0402_5%

R869

R869 0_0402_5%

0_0402_5%

@

12

@

12

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

A A

5

R870 1K_0402_5%DIS@R870 1K_0402 _5%DIS@

1 2

R930 1K_0402_5%DIS@R930 1K_0402 _5%DIS@

1 2

R943 1K_0402_5%DIS@R943 1K_0402 _5%DIS@

1 2

R990 1K_0402_5%DIS@R990 1K_0402 _5%DIS@

1 2

R991 1K_0402_5%DIS@R991 1K_0402 _5%DIS@

1 2

4

CFG3

CFG3-PCI Express Static Lane Reversal

CFG4

CFG4-Display Port Presence

CFG4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

R874 3.01K_0402_1%R874 3.01K_0402_1%

CFG3

1 2

1: Normal Operation

0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

R875

@R875

@

1 2

3.01K_0402_1%

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Clarksfiel(2/5)-DMI/PEG/FDI

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

NIWBA_LA5371P

1

6 52Tuesday, March 24, 2009

0.2

5

CPU1C

J

4

3

J

CPU1D

2

1

D D

C C

B B

DDR_A_D[0..63]<10>

DDR_A_BS0<10> DDR_A_BS1<10> DDR_A_BS2<10>

DDR_A_CAS#<10> DDR_A_RAS#<10> DDR_A_W E#< 10>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

A10

C10

B10

D10

E10

F10

H10

G10

J10

AH5 AF5 AK6 AK7 AF6 AG5

AJ7 AJ6

AJ10

AJ9 AL10 AK12

AK8

AL7 AK11

AL8

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

C7 A7

A8 D8

E6 F7 E9 B7 E7 C6

G8 K7

J8

G7

J7

L7 M6 M8

L9

L6 K8 N8 P9

U7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <10> M_CLK_DDR#0 <10> DDR_CKE0_DIM MA <10>

M_CLK_DDR1 <10> M_CLK_DDR#1 <10> DDR_CKE1_DIM MA <10>

DDR_CS0_DIM MA# <10> DDR_CS1_DIM MA# <10>

M_ODT0 <10> M_ODT1 <10>

DDR_A_DM[0..7] <10>

DDR_A_DQS#[0..7] < 10>

DDR_A_DQS[0..7] <10>

DDR_A_MA[0..15] <10>

DDR_B_D[0..63]<11>

DDR_B_BS0<11> DDR_B_BS1<11> DDR_B_BS2<11>

DDR_B_CAS#<11> DDR_B_RAS#<11> DDR_B_W E#<11>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AF3 AG1

AJ3 AK1 AG4 AG3

AJ4 AH4 AK3 AK4

AM6 AN2

AK5 AK2

AM4 AM3

AP3

AN5

AT4

AN6 AN4 AN3

AT5 AT6

AN7

AP6 AP8 AT9 AT7 AP9

AR10

AT10

AB1

AC5

AC6

G4

G2

G1 G5

M1

M4

W5

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3

H6

J6 J3

J2 J1 J5

K2

L3

K5 K4

N5

R7

Y7

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

W8 W9 M3

V7 V6 M2

AB8 AD6

AC7 AD1

D4 E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 <11> M_CLK_DDR#2 <11> DDR_CKE2_DIM MB <11>

M_CLK_DDR3 <11> M_CLK_DDR#3 <11> DDR_CKE3_DIM MB <11>

DDR_CS2_DIM MB# <11> DDR_CS3_DIM MB# <11>

M_ODT2 <11> M_ODT3 <11>

DDR_B_DM[0..7] <11>

DDR_B_DQS#[0..7] <11>

DDR_B_DQS[0..7] <11>

DDR_B_MA[0..15] < 11>

IC,AUB_CFD_r PGA,R1P0

A A

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(3/5)-DDR III

NIWBA_LA5371P

1

7 52Tuesday, March 24, 2009

0.2

5

V

+

CPU_CORE

J

CPU1F

8A 15A18A

D D

C C

B B

A A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26

AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27

AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

4

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

PROC_DPRSLPVR

CPU VIDS

VTT_SELECT

VSS_SENSE_VTT

SENSE LINES

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

PSI#

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

TT0(1.1V) = 7*0805 22uf under cavity

8*0805 10uf edge caps

3*330uf/6m ohm 1*330uf

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

G15

VTT_SELECT

10U_0805_10V4K

C903

1

2

10U_0805_10V4K

C905

1

@

2

10U_0805_10V4K

C922

1

2

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR _R

1

2

1

2

R877 0_0402_5%R877 0_0402_5%

10U_0805_10V4K

C901

10U_0805_10V4K

C906

@

+VCCP

10U_0805_10V4K

C923

1

2

1 2

10U_0805_10V4K

C902

1

2

10U_0805_10V4K

C907

1

2

PSI# <51>

H_VID[0..6] < 51>

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

H_VTTVID1 = High, 1.05V FOR Auburndale

AN35

AJ34 AJ35

B15 A15

VCC_SENSE VSS_SENSE

1 2 1 2

IMVP_IMON < 51>

0_0402_5%

R878

R879 0_0402_5%R879 0_0402_5%

@

VCCSENSE VSSSENSE

VTT_SENSE <49>

T81PAD@T81PAD

Close to CPU

IC,AUB_CFD_r PGA,R1P0

VCCSENSE

VSSSENSE

5

1 2

R880 100_0402_1%R880 100_0402_1%

1 2

R881 100_0402_1%R881 100_0402_1%

10U_0805_10V4K

C904

1

2

10U_0805_10V4K

C908

1

2

10U_0805_10V4K

1

2

+CPU_CORE

4

VCCP

+

10U_0805_10V4K

C909

1

2

10U_0805_10V4K

C915

C916

1

2

PROC_DPRSLPV R <51>

VTT_SELECT <49>

VCCSENSE <51> VSSSENSE <51>

4

3

+

GFX_CORE

22U_0805_6.3V6M

1

278

600

C

@

2

22U_0805_6.3V6M

12

R313

R313 0_0402_5%

0_0402_5% DIS@

DIS@

+VCCP

10U_0805_10V4K

C917

C918

1

2

C918

1

2

22U_0805_6.3V6M

1

270

274

C

@

2

22U_0805_6.3V6M

1

644

279

C

UMA@

2

22U_0805_6.3V6M

+VCCP

10U_0805_10V4K

1

2

C928

10U_0805_6.3V6M

1

275

271

C

UMA@

2

10U_0805_6.3V6M

+VCCP

1

2

10U_0805_10V4K

C929

1

2

1

2

10U_0805_10V4K

C924

C925

1

2

10U_0805_10V4K

C930

C931

1

2

J

CPU1G

AT21

AXG1

V

AT19

AXG2

V

AT18

V

AXG3

AT16

V

AXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_r PGA,R1P0

GRAPHICS

FDI PEG & DMI

POWER

2

AXG_SENSE

V

SSAXG_SENSE

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

3A

0.6A

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

GFX_VR_EN

GFX_IMON_R

1U_0603_10V4Z

1

2

330U_B2_2.5VM_R15M

1

+

2

1U_0603_10V4Z

C934

1

2

1 2

C910

1

2

C919

1

2

1U_0603_10V4Z

1

2

V

CC_AXG_SENSE <50> SS_AXG_SENSE <50>

V

UMA@

1U_0603_10V4Z

C911

1

2

10U_0805_10V4K

C920

1

2

1

2

1

2

2.2U_0603_6.3V4Z

C935

C936

1

2

GFXVR_VID_0 <50> GFXVR_VID_1 <50> GFXVR_VID_2 <50> GFXVR_VID_3 <50> GFXVR_VID_4 <50> GFXVR_VID_5 <50> GFXVR_VID_6 <50>

R314 0_0402_5%

+1.5V

1U_0603_10V4Z

C913

C912

1

2

10U_0805_10V4K

C921

+VCCP

10U_0805_10V4K

C926

C927

1

2

+VCCP

10U_0805_10V4K

C933

C932

1

2

+1.8VS

10U_0805_10V4K

C937

1

2

1

876

R

FX_IMON_R

G

A

S NO CONNECT

R

DIS@

12

BUT A SMALL AMOUNT OF POWER

(~15MW) MAYBE WASTED

ESIGN GUIDE REV1.1

D

R91

GFX_VR_EN

GFXVR_EN <50> GFXVR_DPRSLPV R <50>

GFXVR_IMON <50>

1U_0603_10V4Z

C914

1

2

R91

1 2

UMA@

VDDQ(CPU) = 5*0402 1uf

2*0805 22uf

TOTAL 3*330uf FOR 2 SO-DIMMs

VDDQ(SO DIMM) = 14*0402 1uf (7*0402 PER CONNECTOR)

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C938

C938

1K_0402_5%

4.7K_0402_5%

VCCPLL(1.8V) = 1*0805 22uf

1*0805 1uf

CPU

1*0805 22uf

1*0603 4.7uf

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(4/5)-PWR

NIWBA_LA5371P

1

8 52Tuesday, March 24, 2009

0.2

5

J

CPU1H

AT20

V

SS1

AT17

V

SS2

AR31

V

SS3

AR28

SS4

V

AR26

SS5

V

AR24

V

SS6

AR23

V

SS7

AR20

D D

C C

B B

AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

V

SS81

V

SS82

V

SS83 SS84

V

SS85

V V

SS86

V

SS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99

VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

K27

J32 J30 J21

J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11

G34 G31 G20

F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11

D33 D30 D26

C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11

A29 A27 A23

4

J

CPU1I

V

SS161

K9

SS162

V

K6

SS163

V

K3

V

SS164

V

SS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178

H8

VSS179

H5

VSS180

H2

VSS181 VSS182 VSS183 VSS184

G9

VSS185

G6

VSS186

G3

VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201

E8

VSS202

E5

VSS203

E2

VSS204 VSS205 VSS206 VSS207

D9

VSS208

D6

VSS209

D3

VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226

B8

VSS227

B6

VSS228

B4

VSS229 VSS230 VSS231 VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

VSS_NCTF1_R VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R

3

CPU_CORE

+

2

PU CORE

C

22U_0805_6.3V6M

C941

C940

C939

1

2

10U_0805_6.3V6M

C952

C951

1

2

10U_0805_6.3V6M

C953

1

22U_0805_6.3V6M

C942

C943

C944

1

2

10U_0805_6.3V6M

C955

C954

1

2

10U_0805_6.3V6M

C956

1

22U_0805_6.3V6M

C945

C946

C947

C948

1

2

10U_0805_6.3V6M

C957

C958

1

C948

1

2

C959

22U_0805_6.3V6M

C950

C949

1

I

nside cavity

2

1

between Inductor and socket

2

10U_0805_6.3V6M

C960

1

2

10U_0805_6.3V6M

C961

C962

1

2

10U_0805_6.3V6M

C964

C963

1

2

Under cavity

+CPU_CORE = 12*0805 22uf INSIDE CAVITY

7*0805 10uf UNDER CAVITY AND 9*0805 10uf BETWEEN INDUCTOR AND SOCKET ON TOP LAYER

4*470uf/4m ohm 2*470uf

2

10U_0805_6.3V6M

C965

1

2

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

10U_0805_6.3V6M

C966

1

2

1

+

2

470U_D2_2VM_R4.5M

C968

C967

1

2

+

2

470U_D2_2VM_R4.5M

C970

C969

1

+

2

22U_0805_6.3V6M

C971

1

2

22U_0805_6.3V6M

C972

1

2

22U_0805_6.3V6M

C973

C974

1

2

470uF 4.5mohm

IC,AUB_CFD_r PGA,R1P0

A A

5

IC,AUB_CFD_r PGA,R1P0

4

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Clarksfiel(5/5)-GND/Bypass

NIWBA_LA5371P

1

9 52Tuesday, March 24, 2009

0.2

5

VREF_DQ_DIMMA

+

VREF_DQ_DIMMA

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

1

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

2

D D

C C

B B

A A

C976

C

C 975

975

1

2

2.2U_0603_6.3V4Z

1

2

D

DR_A_D0

D

DR_A_D1

DR_A_DM0

D

DR_A_D2

DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIM MA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_W E# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIM MA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R889

1 2

10K_0402_5%

0.1U_0402_10V6K

C1002

C1003

1

2

1.5V

+

3A@1.5V

3A@1.5V3A@1.5V

D

DR3 SO-DIMM A

JD

DR1

1

V

REF_DQ

3

V

SS2

5

D

Q0

7

Q1

D

9

SS4

V

11

D

M0

13

V

SS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

10K_0402_5%

12

203

R890

VTT1

205

G1

TYCO_2-2013289-1

VREF_CA

V

SS1 D D

SS3

V QS#0

D

QS0

V

SS6 DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

RESET#

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1

VDD2

A15

A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

2 4

Q4

6

Q5

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

4

1.5V

+

DR_A_D4

D D

DR_A_D5

D

DR_A_DQS#0 DR_A_DQS0

D

DR_A_D6

DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1 DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DRAMRST# <5,11>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 < 7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_10V6K

0.1U_0402_10V6K C980

C980

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R <5,11>

SMB_DATA_S3 <11,12,14,30> SMB_CLK_S3 <11,12,14,30>

D

DR_A_D[0..63]<7>

D

DR_A_DM[0..7]<7>

D

DR_A_DQS[0..7]<7>

DR_A_DQS#[0..7]<7>

D

DR_A_MA[0..15]<7>

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C981

C981

SMBCLK<11,14>

SMBDATA<11,14>

4*0402 1uf

1*0402 2.2uf

3

+

VREF_DQ_DIMMA

1 2

R

882 0_0402_5%

1 2

R

884 0_0402_5%

1 2

R885 0_0402_5%

2

C977

M2@

1

1U_0603_10V4Z X5R

SMBCLK

SMBDATA

U42

1

VDD

2

GND

3

SCL

ISL90727WIE627Z-TK_SC70-6

ISL90727WIE627Z-TK_SC70-6 M2@

M2@

I2C address 5Ch

RW

SDA

6

RH

5

4

2

V

_DDR_CPU_REF

M1@

M2@

M3@

R887

R887 M2@

M2@

12.1k_0402_1%

1 2

VREF_RW_POT0

R888

R888 M2@

M2@

12.1k_0402_1%

1 2

+

V_DDR_CPU_REF

+

V_DDR_M2_REF0

3

2

+VREF_OPAMP_POT0

+3VALW+3VALW +1.5V+1.5V

8

+

-

4

+

P

1

O

G

U43A

U43A M2@

M2@ LM393M_SO8

LM393M_SO8

V_DDR_CPU_REF0

2

C978

C978 M2@

M2@ 1U_0603_10V4Z X5R

1U_0603_10V4Z X5R

1

+

R

883

1K_0402_1%

R886

1K_0402_1%

+V_DDR_M2_REF0

2

1

1.5V

12

+

V_DDR_CPU_REF

12

C979

1U_0603_10V4Z X5R

1U_0603_10V4Z X5R @

@

Layout Note: Place near DIMM

+1.5V

10U_0603_6.3V6M

C982

1

@

2

10U_0603_6.3V6M

C984

C983

@

1

2

+0.75VS

C996

1

2

10U_0603_6.3V6M

C985

C986

1

2

1U_0603_10V4Z

C997

C998

1U_0603_10V4Z

1

2

10U_0603_6.3V6M

C987

1

2

1U_0603_10V4Z

C1000

C999

1

2

10U_0603_6.3V6M

0.1U_0402_10V6K

C988

C989

1

2

10U_0603_6.3V6M

0.1U_0402_10V6K C990

C990

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C991

C991

1

2

0.1U_0402_10V6K

C992

C993

1

2

+

C994

C994 220U_B_2.5VM_R35M

220U_B_2.5VM_R35M

2

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

TOP SLOT

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

NIWBA_LA5371P

1

10 52Tuesday, March 24, 2009

0.2

5

VREF_DQ_DIMMB

+

0.1U_0402_10V6K

0.1U_0402_10V6K C1028

C1028

10K_0402_5%

VREF_DQ_DIMMB

D

DR_B_D0

D

DR_B_D1

DR_B_DM0

D

DR_B_D2

DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R896

1 2

R897 10K_0402_5%R897 10K_0402_5%

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

1

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

2

D D

C C

B B

A A

1

C1005

C

C 1004

1004

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C1027

C1027

1

2

1.5V

+

3A@1.5V

3A@1.5V3A@1.5V

JD

DR2

1

V

REF_DQ

3

V

SS

5

D

Q0

7

Q1

D

9

SS

V

11

D

M0

13

V

SS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

GND2

TYCO_2-2013310-1_204P

TYCO_2-2013310-1_204P CONN@

CONN@

V D D V

QS0#

D

QS0 V DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

A15 A14

VDD

A11

VDD

CK1 CK1#

VDD

BA1 RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS

DM4

VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS

DM6

VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1 BOSS2

SS Q4 Q5 SS

SS

A7

A6 A4

A2 A0

NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

1.5V

+

D D

D DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23DDR_B_D18

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

+VREF_CA

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3

BOT SLOT

5

DR_B_D4 DR_B_D5

DR_B_DQS#0 DR_B_DQS0

DR_B_D6

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

DR_B_DQS#[0..7]<7>

D

DR_B_D[0..63]<7>

D

DR_B_DM[0..7]<7>

D

DR_B_DQS[0..7]<7>

DR_B_MA[0..15]<7>

D

DRAMRST# <5,10>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 < 7> M_CLK_DDR#3 <7>

DDR_B_BS1 < 7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

1

2

0.1U_0402_10V6K

C1009

V_DDR_CPU_REF

2.2U_0603_6.3V4Z

C1018

1

2

3

+

VREF_DQ_DIMMB

R

891

1 2

892 0_0402_5%M2@

R

1 2

R893 0_0402_5%M3@R893 0_0402_5%M3@

2

C1006

M2@

1

1U_0603_10V4Z X5R

SMBCLK<10,14>

SMBDATA<10,14>

SMBCLK

SMBDATA

U44

1

VDD

2

GND

3

SCL

ISL90728WIE627Z-TK_SC70-6

ISL90728WIE627Z-TK_SC70-6 M2@

M2@

I2C address 7Ch

RH

RW

SDA

6

5

4

0_0402_5%M1@

+1.5V+1.5V

1 2

2

+

V_DDR_CPU_REF

R894

R894 M2@

M2@

12.1k_0402_1%

VREF_RW_POT1

R895

R895 M2@

M2@

12.1k_0402_1%

V_DDR_M2_REF1

+

+3VALW+3VALW

5

+

6

-

+VREF_OPAMP_POT1

+

V_DDR_CPU_REF1

CAP 1UF OVERPAGE

8

P

7

O

G

U43B

U43B M2@

M2@

4

LM393M_SO8

+V_DDR_M2_REF1

2

C1008

1U_0603_10V4Z X5R

1

M2@

1

Layout Note: Place near DIMM

+1.5V

10U_0603_6.3V6M

C1012

C1010

1

@

2

C1012

C1011

1

2

10U_0603_6.3V6M

C1013

C1014

C1015

1

2

C1015

1

2

10U_0603_6.3V6M

C1016

1

2

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K C1019

C1017

1

2

C1019

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C1020

C1020

1

2

0.1U_0402_10V6K

C1021

C1022

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

4*0402 1uf

1*0402 2.2uf

Layout Note: Place near DIMM

+0.75VS

VDDSPD (3.3V)=

1U_0603_10V4Z

1*0402 0.1uf 1*0402 2.2uf

PM_EXTTS#1_R <5,10>

SMB_DATA_S3 <10,12,14,30> SMB_CLK_S3 <10,12,14,30>

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

1U_0603_10V4Z

C1024

C1023

1

2

1

2

2008/10/31 2009/10/31

1U_0603_10V4Z

C1026

C1025

1

2

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

NIWBA_LA5371P

Date: Sheet of

1

11 52Tuesday, March 24, 2009

0.2

5

4

3

2

1

D D

C C

CLK GEN TO PCH

1. CLK_DMI

2. CLK_BUF_BCLK

3. CLK_BUF_CKSSCD

4. CLK_BUF_DOT96

5. CLK_14M_PCH

1 2

CLK GEN TO VGA

1. 27M_CLK

1. 27M_CLK_SS

+1.05VS_CK505+1.05VS

R9090_0603_5% R9090_0603_5%

10U_0805_10V4K

C1029

C1030

1

2

C1030

1

2

SCL

SDA

CPU_0

CPU_1

+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

SMB_CLK_S3 SMB_DATA_S3 REF_0/CPU_SEL

CLK_XTAL_IN CLK_XTAL_OUT

CK_PWRGD

R_CLK_BUF_BCLK CLK_BUF_BCLK R_CLK_BUF_BCLK# CLK_BUF_BCLK#

R903 0_0402_5%R903 0_0402_5%

R904 0_0402_5%R904 0_0402_5%

1 2 1 2

33_0402_1%

R899

12

CLK_14M_PCH

CK_PWRGD

CLK_BUF_BCLK <14> CLK_BUF_BCLK# <14>

Q60

2N7002_SOT23-3

Q60

SMB_CLK_S3 <10,11,14,30> SMB_DATA_S3 <10,11,14,30>

CLK_14M_PCH <14>

R908

1 2

10K_0402_5%

13

D

2

G

S

+3VS_CK505

CLK_EN# <51>

U45

1

CLK_BUF_DOT96<14>

CLK_BUF_DOT96#<14>

27M_CLK<19>

27M_CLK_SS<19>

CLK_BUF_CKSSCD<14>

CLK_BUF_CKSSCD#<14>

CLK_DMI<14>

CLK_DMI#<14>

CLK_BUF_DOT96 CLK_BUF_DOT96#

27M_CLK 27M_CLK_SS

CLK_BUF_CKSSCD CLK_BUF_CKSSCD#

CLK_DMI CLK_DMI#

+3VS_CK505

R898 0_0402_5%R898 0_0402_5%

1 2 1 2

R900 0_0402_5%R900 0_0402_5%

R901 33_0402_1%R901 33_0402_1%

1 2

R902 33_0402_1%R902 33_0402_1%

1 2

CLOSE U5

R905 0_0402_5%R905 0_0402_5%

1 2

R906

R907

1 2

0_0402_5%

10K_0402_5%

L_CLK_BUF_DOT96 L_CLK_BUF_DOT96#

27M_CLK_L 27M_CLK_SS_L

CLK_48M_CR_R

L_CLK_DMI L_CLK_DMI#

CPU_STOP#

VDD_DOT

2

VSS_DOT

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11

SRC_1#/SATA#

12

VSS_SRC

13

SRC_2

14

SRC_2#

15

VDD_SRC_IO

16

CPU_STOP#

SLG8SP585VTR_QFN32_5X5

REF_0/CPU_SEL

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

CKPWRGD/PD#

VDD_CPU

CPU_0#

VSS_CPU

CPU_1#

VDD_CPU_IO

VDD_SRC

TGND

33

S IC ICS9LRS3199AKLFT MLF 32P CLK GEN (SA000030P00)1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

C1031

C1032

1

2

C1032

1

2

0.1U_0402_10V6K C1033

C1033

1

2

CLK_48M_CR<33>

1 2

CLK_48M_CR_R

R9100_0402_5% R9100_0402_5%

12

R9110_0402_5%@R9110_0402_5%

@

PIN8 IS GND FOR ICS3197 PIN8 IS 48MHz FOR ICS3199

R9120_0603_5% R9120_0603_5%

+3VS_CK505

1 PCS CAP(0.1u) BY 1 INPUT PIN

0.1U_0402_10V6K

10U_0805_10V4K

C1035

1

2

(Default)

0 133MHz

1

0.1U_0402_10V6K

C1036

C1037

1

2

100MHz 100MHz

0.1U_0402_10V6K

0.1U_0402_10V6K C1038

C1038

1

2

CPU_1PIN 30 CPU_0

133MHz

0.1U_0402_10V6K

C1039

C1040

1

2

C1034

0.1U_0402_10V6K

0.1U_0402_10V6K C1041

C1041

C1042

EMI Capacitor

+1.05VS

1 2

R913 10K_0402_5%@R913 10K_0402_5%@

1 2

R914 10K_0402_5%R914 10K_0402_5%

CLK_14M_PCH

12

10P_0402_50V8J@

12

REF_0/CPU_SEL

10P_0402_50V8J@

C1043

33P_0402_50V8J

CLK_XTAL_OUT

CLK_XTAL_IN

Y6

12

2

14.31818MHZ_16PF_DSX840GA

1

2

1

C1044

33P_0402_50V8J

+3VS

1 2

B B

A A

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

CLOCK GENERATOR

NIWBA_LA5371P

Date: Sheet of

1

12 52Tuesday, March 24, 2009

0.2

5

P

CH_RTCX1

P

1

C

1046

18P_0402_50V8J

2

32.768KHZ_12.5P_1TJS125BJ2A251

SM_INTRUDER#

PCH_INTVRMEN

PCH_SPKR

CH_RTCX2

1 2

R

915 10M_0402_5%

18P_0402_50V8J

1

C

1045

D D

+RTCVCC

R917

1 2

100_0603_1%

2

C1049

0.1U_0402_16V4Z

1

C C

+RTCBATT

+RTCVCC

+3VS

1045

2

R916

1 2

R918

1 2

H：Integrated VRM enable

*

L：Integrated VRM disable

2

1M_0402_5%

330K_0402_5%

1 2

R924 1K_0402_5%@R924 1K_0402_5%@

4IN1

7

X

OUT

NC3NC

GPIO33 = GPO , internal pull-up,should not be pulled low

flash ME core of strap pin pull down

+3VALW+3VALW +3VALW +3VALW +3VS

12

R932

R932 200_0402_5%

200_0402_5% @

@

12

B B

R939

R939 100_0402_1%

100_0402_1% @

@

12

R933

R933 200_0402_5%

200_0402_5% @

@

PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI

12

R940

R940 100_0402_1%

100_0402_1% @

@

R934

R934 20K_0402_5%

20K_0402_5%

@

1 2

R941

R941 10K_0402_1%

10K_0402_1%

@

1 2

R935

R935 20K_0402_5%

20K_0402_5%

@

1 2

12

R942

R942 10K_0402_5%

10K_0402_5% @

@

4

+RTCVCC

HDA_BITCLK_CODEC<35>

HDA_SYNC_CODEC<35>

HDA_RST_CODEC#<35>

HDA_SDOUT_CODEC<35>

C1047

1U_0603_10V4Z

1 2

R920 20K_0402_1%R920 20K_0402_1%

1 2

R921 20K_0402_1%R921 20K_0402_1%

C1048

1U_0603_10V4Z

PCH_SPKR< 35>

HDA_SDIN1<35>

ME_FLASH<37>

+3VALW

SPI_CLK_PCH

1

12

CLRP1

SHORT PADS

2

1

12

CLRP2

SHORT PADS

2

R919 33_0402_5%R919 33_0402_5%

1 2

R923 33_0402_5%R923 33_0402_5%

1 2

R925 33_0402_5%R925 33_0402_5%

1 2

R926 33_0402_5%R926 33_0402_5%

1 2

R927 100K_0402_5%@R927 100K_0402_5%@

1 2

R928 0_0402_5%R928 0_0402_5%

1 2

R929 10K_0402_5%R929 10K_0402_5%

1 2

R1076

1 2

0_0402_5%

GPIO13 = GPI,3.3V,SUS

PCH_RTCX1 PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

BITCLK

HDA_SYNC

PCH_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDOUT

GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SI

SPI_SO_R

3

U46A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_FCBGA1071

RTCIHDA

SPI JTAG

SATA

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

LPC

SERIRQ

SATA0RXN SATA0RXP

SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP

SATA3TXN SATA3TXP

SATA4RXN SATA4RXP

SATA4TXN SATA4TXP

SATA5RXN SATA5RXP

SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

D33 B33 C32 A32

C34

A34

GPIO23

F34

SERIRQ

AB9

AK7 AK6

SATA_ITX_C_DRX_N0

AK11

SATA_ITX_C_DRX_P0

AK9

AH6 AH5

SATA_ITX_C_DRX_N1

AH9

SATA_ITX_C_DRX_P1

AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

SATA_DTX_C_IRX_N4

AD9

SATA_DTX_C_IRX_P4

AD8

SATA_ITX_C_DRX_N4

AD6

SATA_ITX_C_DRX_P4

AD5

AD3 AD1 AB3 AB1

AF16

SATAICOMPPCH_JTAG_RST#

AF15

T3

GPIO21

Y9

GPIO19

V1

2

LPC_AD0 <37,38> LPC_AD1 <37,38> LPC_AD2 <37,38> LPC_AD3 <37,38>

LPC_FRAME# <37,38>

T82 PADT82 PAD

GPIO23 = NATIVE,3.3V,CORE

R931

1 2

37.4_0402_1%

1 2

R936 10K_0402_5%R936 10K_0402_5%

LPC_DRQ0# <38>

SERIRQ <37,38>

+1.05VS

+3VS

DRIVE_LED# <41>

GPIO21 = GPI,3.3V,CORE

GPIO19 = GPI,3.3V,CORE

1

+3VS

12

R92210K_0402_5% R92210K_0402_5%

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

C10500.01U_0402_16V7K C10500.01U_0402_16V7K

12

C10510.01U_0402_16V7K C10510.01U_0402_16V7K

12

C10520.01U_0402_16V7K C10520.01U_0402_16V7K

12

C10530.01U_0402_16V7K C10530.01U_0402_16V7K

12

C10540.01U_0402_16V7K C10540.01U_0402_16V7K

12

C10550.01U_0402_16V7K C10550.01U_0402_16V7K

12

SATA_ITX_DRX_N0

SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N1 SATA_ITX_DRX_P1

SATA_ITX_DRX_N4_CONN

SATA_ITX_DRX_P4_CONN

R937

10K_0402_5%

GPIO21

GPIO19

1 2

SATA_DTX_C_IRX_N0 <34>

SATA_DTX_C_IRX_P0 <34> SATA_ITX_DRX_N0 < 34> SATA_ITX_DRX_P0 <34>

SATA_DTX_C_IRX_N1 <34>

SATA_DTX_C_IRX_P1 <34> SATA_ITX_DRX_N1 < 34>

SATA_ITX_DRX_P1 <34>

SATA_DTX_C_IRX_N4 <34>

SATA_DTX_C_IRX_P4 <34> SATA_ITX_DRX_N4_CONN <34>

SATA_ITX_DRX_P4_CONN <34>

R938

R938 10K_0402_5%

10K_0402_5%

1 2

SPI_CLK_PCH

12

R572

SPI ROM on ME

RefDesPCH Pin

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TCK

A A

PCH_JTAG_RST#

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

R104

No Install

R108

No Install

200ohm

R105

100ohm 100ohm

R109

200ohm

100ohm 100ohm

R110

51ohm 51ohm 51ohm

R97

20Kohm 20Kohm

R107

10Kohm 10Kohm

R110

200ohm

100ohm

200ohm

No Install

20Kohm

10Kohm

No Install

No InstallR106

No Install

51ohm

No Install

No InstallNo Install

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_RST#

PCH_JTAG_TCK

R806 51_0402_5%@R806 51_0402_5%@

1 2

R807 51_0402_5%@R807 51_0402_5%@

1 2

R808 51_0402_5%@R808 51_0402_5%@

1 2

R809 51_0402_5%@R809 51_0402_5%@

1 2

R90 4.7K_0402_5%R90 4.7K_0402_5%

1 2

CRB 1.0 Change to 4.7K

+1.05VS

SPI_SB_CS0# SPI_SO_R SPI_SO_L

+3VS

R944

R945

R946

15_0402_5%

1 2

1 2

R947

15_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

12

SPI_WP#

U37

1

CS# SO WP# GND

VCC

HOLD#

SCLK

SI

2 3 4

MX25L1605AM2C-12G_SO8

8 7 6 5

+3VS

SPI_HOLD# SPI_CLK_PCH

C1056

1 2

0.1U_0402_16V4Z

SPI_SI

R572

33_0402_5%

@

C748

@

C748

22P_0402_50V8J

FOR EVT

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(1/6)-HDA/JTAG/SATA

NIWBA_LA5371P

1

13 52Tuesday, March 24, 2009

0.2

5

P

CIE PORT LIST

DEVICEPORT

1 2 3

D D

4 5 6 7 8

EXP

WLAN

LAN

3G

C C

TV

EXP

WLAN

B B

LAN

3G

TV

A A

CLK_PCIE_EXP_PCH#<30> CLK_PCIE_EXP_PCH<30>

CLK_PCIE_CARD_PCH#<30> CLK_PCIE_CARD_PCH<30>

PCIE_PRX_DTX_N1<30> PCIE_PRX_DTX_P1<30> PCIE_PTX_C_DRX_N1<30> PCIE_PTX_C_DRX_P1<30>

PCIE_PRX_DTX_N2<30> PCIE_PRX_DTX_P2<30> PCIE_PTX_C_DRX_N2<30> PCIE_PTX_C_DRX_P2<30>

PCIE_PRX_DTX_N3<31> PCIE_PRX_DTX_P3<31> PCIE_PTX_C_DRX_N3<31> PCIE_PTX_C_DRX_P3<31>

PCIE_PRX_DTX_N4<30> PCIE_PRX_DTX_P4<30> PCIE_PTX_C_DRX_N4<30> PCIE_PTX_C_DRX_P4<30>

PCIE_PRX_DTX_N6<30> PCIE_PRX_DTX_P6<30> PCIE_PTX_C_DRX_N6<30> PCIE_PTX_C_DRX_P6<30>

CLKREQ_EXP#<30>

CLK_PCIE_WLAN1#<30> CLK_PCIE_WLAN1<30>

WLAN_CLKREQ1#<30>

CLK_PCIE_LAN#<31> CLK_PCIE_LAN<31>

CLKREQ_LAN#<31>

PCIECLKREQ3#<30>

CLK_PCIE_WLAN#<30> CLK_PCIE_WLAN<30>

PCIECLKREQ4#<30>

NEW CARD WLAN LAN 3G X TV TUNNER X X

+3VALW

+3VS

+3VALW

C1058 0.1U_0402_10V6KC1058 0.1U_0402_10V6K

1 2

C1057 0.1U_0402_10V6KC1057 0.1U_0402_10V6K

1 2

C1059 0.1U_0402_10V6KC1059 0.1U_0402_10V6K

1 2

C1060 0.1U_0402_10V6KC1060 0.1U_0402_10V6K

1 2

C1061 0.1U_0402_10V6KC1061 0.1U_0402_10V6K

1 2

C1064 0.1U_0402_10V6KC1064 0.1U_0402_10V6K

1 2

C1062 0.1U_0402_10V6KC1062 0.1U_0402_10V6K

1 2

C1063 0.1U_0402_10V6KC1063 0.1U_0402_10V6K

1 2

C1065 0.1U_0402_10V6KC1065 0.1U_0402_10V6K

1 2

C1066 0.1U_0402_10V6KC1066 0.1U_0402_10V6K

1 2

R967 0_0402_5%R967 0_0402_5%

1 2

R968 0_0402_5%R968 0_0402_5%

1 2

R969 10K_0402_5%R969 10K_0402_5%

1 2

R970 0_0402_5%R970 0_0402_5%

1 2

R971 0_0402_5%R971 0_0402_5%

1 2

R973 10K_0402_5%R973 10K_0402_5%

1 2

R974 0_0402_5%R974 0_0402_5%

1 2

R976 0_0402_5%R976 0_0402_5%

1 2

R977 10K_0402_5%R977 10K_0402_5%

1 2

R978 0_0402_5%R978 0_0402_5%

1 2

R979 0_0402_5%R979 0_0402_5%

1 2

R980 10K_0402_5%R980 10K_0402_5%

1 2

R984 10K_0402_5%R984 10K_0402_5%

1 2

R981 0_0402_5%R981 0_0402_5%

1 2

R982 0_0402_5%R982 0_0402_5%

1 2

R986 10K_0402_5%R986 10K_0402_5%

1 2

R989 10K_0402_5%R989 10K_0402_5%

1 2

GPIO73 = NATIVE,3.3V,SUS

GPIO18 = NATIVE,3.3V,CORE

GPIO20 = NATIVE,3.3V,CORE

GPIO25 = NATIVE,3.3V,SUS

GPIO26 = NATIVE,3.3V,SUS

GPIO44 = NATIVE,3.3V,SUS

GPIO56 = NATIVE,3.3V,SUS

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

CLK_PCIE_EXP_PCH#_R CLK_PCIE_EXP_PCH_R

CLKREQ_EXP#

CLK_PCIE_MCARD_PCH#_R CLK_PCIE_MCARD_PCH_R

CLK_PCIE_CARD_PCH#_R CLK_PCIE_CARD_PCH_R

PCIECLKREQ4#

4

U46B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071

NEW CARD

WLAN

LAN

MINI1

CR

PCI-E*

MINI2

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

Clock Flex

CLKOUTFLEX3 / GPIO67

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N

CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

LID_OUT#

B9

H14

C8

GPIO11 = NATIVE,3.3V,SUS

SMBCLK

SMBDATA

GPIO60 = NATIVE,3.3V,SUS

GPIO60

J14

SML0CLK

C6

SML0DATA

G8

GPIO74 = NATIVE,3.3V,SUS

GPIO74

M14

E10

G12

T13

T11

T9

H1

SML1CLK

SML1DATA

PEG_CLKREQ#

R962

R963

1 2

GPIO47 = 10Kohm PULL DOWN

CLK_PCIE_VGA#

AD43

CLK_PCIE_VGA

AD45

AN4 AN2

CLKOUT_DP_N

AT1

CLKOUT_DP_P

AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

CLK_14M_PCH

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R983 90.9_0402_1%R983 90.9_0402_1%

AF38

T45

P43

T42

N50

1 2

R987

1 2

R988

1 2

22_0402_5%

EC_LID_OUT# < 37>

R959

R959 0_0402_5%

0_0402_5% <BOM Structure>

0_0402_5%

DTS , read from EC

PEG_CLKREQ# <19>

R96410K_0402_5% R96410K_0402_5%

CLK_PCIE_VGA# <19>

CLK_PCIE_VGA <19>

CLK_EXP# <5> CLK_EXP <5>

CLK_DMI# <12> CLK_DMI <12>

CLK_BUF_BCLK# <12> CLK_BUF_BCLK <12>

CLK_BUF_DOT96# < 12> CLK_BUF_DOT96 <12>

CLK_BUF_CKSSCD# <12> CLK_BUF_CKSSCD <12>

CLK_14M_PCH <12>

CLK_PCI_FB <16>

CLK_PCI_DB <38>

CLK_14M_SIO <38>

EC_SMB_CK2

EC_SMB_DA2

+1.05VS

MB_CLK_S3

S

MB_DATA_S3

SMBCLK <10,11>

SMBDATA <10,11>

EC_SMB_CK2 <37>

EC_SMB_DA2 <37>

2

1 2

948 10K_0402_5%

R

1 2

R

950 10K_0402_5%

Q61A

2N7002DW-T/R7_SOT363-6

Q61A

6 1

2

Q61B

3

5

4

SMB_CLK_S3

+3VS

SMB_DATA_S3

EC_THERMAL

+3VS

Q62A

6 1

5

2N7002DW-T/R7_SOT363-6

Q62B

3

2N7002DW-T/R7_SOT363-6

4

EC_SMB_DA2

EC_SMB_CK2

EMI REQUEST 0303

CLK_14M_PCHCLK_PCI_FB

R666

R666 33_0402_5%

33_0402_5% @

@

1 2

C809

C809 22P_0402_50V8J

22P_0402_50V8J

@

1 2

+

S

MBDATA

S

ML0CLK

S

ML0DATA

ML1CLK

S

ML1DATA

PIO74

G

L

ID_OUT#

GPIO60

SMB_CLK_S3 <10,11,12,30>

MBCLK

S

3VS

DDR3*2 AND CLK GEN

SMB_DATA_S3 <10,11,12,30>

+3VS

R965

2.2K_0402_5%

2

R9720_0402_5%

@

1 2

R9750_0402_5%

@

1 2

R667

R667 33_0402_5%

33_0402_5% @

@

C810

C810 22P_0402_50V8J

22P_0402_50V8J

@

SMB_EC_DA2_R

SMB_EC_CK2_R

1 2 949 2.2K_0402_5%

949 2.2K_0402_5%

R

1 2

R

951 2.2K_0402_5%

951 2.2K_0402_5% 1 2

R

952 2.2K_0402_5%

952 2.2K_0402_5% 1 2

R

953 2.2K_0402_5%

953 2.2K_0402_5% 1 2

954 2.2K_0402_5%

R

1 2

R

955 2.2K_0402_5%

955 2.2K_0402_5% 1 2

956 10K_0402_5%

R

1 2

R957 10K_0402_5%R957 10K_0402_5%

1 2

R958 10K_0402_5%R958 10K_0402_5%

SMBCLK

SMBDATA SMB_DATA_S3

R966

2.2K_0402_5%

SMB_EC_DA2_REC_SMB_DA2

SMB_EC_CK2_REC_SMB_CK2

XTAL25_IN

XTAL25_OUT

18P_0402_50V8J

1

3VALW

+

R960

R960 0_0402_5%

0_0402_5%

@

1 2

@

1 2

0_0402_5%

0_0402_5% R961

R961

SMB_EC_DA2_R <19,41>

Nvidia thermall sensor

SMB_EC_CK2_R <19,41>

1 2

R985 1M_0402_5%@ R985 1M_0402_5%@

Y8

@Y8

@

1 2

25MHZ_20P_1BG25000CK1A

C1067

@C1067

@

1

2

SMB_CLK_S3

18P_0402_50V8J

C1068

1

2

@C1068

@

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(2/6)-PCI-E/SMBUS/CLK

NIWBA_LA5371P

1

14 52Tuesday, March 24, 2009

0.2

5

4

3

2

1

D D

DMI_CTX_PRX_N0<6> DMI_CTX_PRX_N1<6> DMI_CTX_PRX_N2<6> DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6> DMI_CTX_PRX_P1<6> DMI_CTX_PRX_P2<6> DMI_CTX_PRX_P3<6>

DMI_CRX_PTX_N0<6> DMI_CRX_PTX_N1<6> DMI_CRX_PTX_N2<6> DMI_CRX_PTX_N3<6>

DMI_CRX_PTX_P0<6> DMI_CRX_PTX_P1<6> DMI_CRX_PTX_P2<6> DMI_CRX_PTX_P3<6>

+1.05VS

1 2

R993 49.9_0402_1%R993 49.9_0402_1%

4mil width and place

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

within 500mil of the PCH

C C

SUS_PWR_DN_ACK<37>

+3VALW

B B

Checklist0.8：MEPWROK can be connect to PWROK if iAMT disable

R998 100K_0402_1%R998 100K_0402_1%

VGATE<51>

ICH_POK<37>

PM_DRAM_PWRGD<5>

+3VALW

R1008 10K_0402_5%R1008 10K_0402_5%

1 2

R1009 10K_0402_5%R1009 10K_0402_5%

1 2

AC_PRESENT<37>

+3VALW

R1012 8.2K_0402_1%R1012 8.2K_0402_1%

R1013 10K_0402_5%R1013 10K_0402_5%

R999 0_0402_5%

R1001 0_0402_5%@R1001 0_0402_5%@

1 2

R1024 0_0402_5%@R1024 0_0402_5%@

PBTN_OUT#<37>

GPIO31 = GPI,3.3V,SUS

1 2

+3VS

R996

R996 10K_0402_5%

10K_0402_5%

12

1 2

R1003 10K_0402_5%

R1006

10K_0402_5%

1 2

R1010 0_0402_5%R1010 0_0402_5%

1 2

0_0402_5%

1 2

PM_DRAM_PWRGD

PM_RSMRST#

12

SUS_PWR_DN_ACK_R

AC_PRESENT_R

GPIO72

GPIO30 = GPI,3.3V,SUS

R1002

SYS_RST#

1 2

PBTN_OUT#

U46C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_FCBGA1071

FDI_CTX_PRX_N0

FDI_INT

WAKE#

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14

BF13

BH13

BJ12

BG14

J12

Y1

FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

PCIE_WAKE#

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

GPIO32 = GPO,3.3V,CORE

GPIO61

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

System Power Management

PMSYNCH

SLP_LAN# / GPIO29

P8

F3

E4

H7

P12

K8

SLP_M#

N2

TP23

BJ10

GPIO29 = GPO,3.3V,SUS

F6

GPIO62

FDI_CTX_PRX_N0 <6> FDI_CTX_PRX_N1 <6> FDI_CTX_PRX_N2 <6> FDI_CTX_PRX_N3 <6> FDI_CTX_PRX_N4 <6> FDI_CTX_PRX_N5 <6> FDI_CTX_PRX_N6 <6> FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6> FDI_CTX_PRX_P1 <6> FDI_CTX_PRX_P2 <6> FDI_CTX_PRX_P3 <6> FDI_CTX_PRX_P4 <6> FDI_CTX_PRX_P5 <6> FDI_CTX_PRX_P6 <6> FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

1K_0402_5%

1 2

R997

PCIE_WAKE# <30,31>

1 2

R1000 10K_0402_5%R1000 10K_0402_5%

+3VALW

+3VS

GPIO61 = NATIVE,3.3V,SUS

GPIO62 = NATIVE,3.3V,SUS

SLP_S5# <37>

SLP_S4# <37>

SLP_S3# <37>

Can be left NC when IAMT is not support on the platfrom

H_PM_SYNC <5>

If not using integrated LAN,signal may be left as NC.

+3VS

PCH_ENBKL_R<29>

PCH_ENVDD_R< 29>

INV_PWM

EDID_CLK<29> EDID_DATA<29>

12

R1308

2.37K_0402_1%

LVDS_ACLK#<29> LVDS_ACLK<29>

LVDS_A0#<29> LVDS_A1#<29> LVDS_A2#<29>

LVDS_A0<29> LVDS_A1<29> LVDS_A2<29>

LVDS_BCLK#<29> LVDS_BCLK<29>

LVDS_B0#<29> LVDS_B1#<29> LVDS_B2#<29>

LVDS_B0<29> LVDS_B1<29> LVDS_B2<29>

DAC_BLU< 28> DAC_GRN<28> DAC_RED<28>

CRT_DDC_CLK<28> CRT_DDC_DATA<28>

CRT_HSYNC<28> CRT_VSYNC< 28>

PCH_ENBKL

PCH_ENVDD

1 2

R1306 10K_0402_5%R1306 10K_0402_5%

1 2

R1307 10K_0402_5%R1307 10K_0402_5%

T110 PADT110 PAD

DAC_BLU DAC_GRN DAC_RED

CRT_IREF

1K_0402_0.5%

R1011

12

U46D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

AB48

L_DDC_CLK

Y45

L_DDC_DATA

AB46

L_CTRL_CLK

V48

L_CTRL_DATA

AP39

LVD_IBG

AP41

LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

AV53

LVDSA_CLK#

AV51

LVDSA_CLK

BB47

LVDSA_DATA#0

BA52

LVDSA_DATA#1

AY48

LVDSA_DATA#2

AV47

LVDSA_DATA#3

BB48

LVDSA_DATA0

BA50

LVDSA_DATA1

AY49

LVDSA_DATA2

AV48

LVDSA_DATA3

AP48

LVDSB_CLK#

AP47

LVDSB_CLK

AY53

LVDSB_DATA#0

AT49

LVDSB_DATA#1

AU52

LVDSB_DATA#2

AT53

LVDSB_DATA#3

AY51

LVDSB_DATA0

AT48

LVDSB_DATA1

AU50

LVDSB_DATA2

AT51

LVDSB_DATA3

AA52

CRT_BLUE

AB53

CRT_GREEN

AD53

CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

AD48

DAC_IREF

AB51

CRT_IRTN

IBEXPEAK-M_FCBGA1071

DAC_BLU

DAC_GRN

DAC_RED

R1162 150_0402_1%UMA@R1162 150_0402_1%UMA@

R1186 150_0402_1%UMA@R1186 150_0402_1%UMA@

R1184 150_0402_1%UMA@R1184 150_0402_1%UMA@

LVDS

CRT

CRT OUT

1 2

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N

Digital Display Interface

DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

R1309 10K_0402_5%R1309 10K_0402_5%

UMA@

R1310

2.2K_0402_5%

HDMICLK_NB HDMIDAT_NB

12

+3VS

12

UMA@

UMA@ R1311

R1311

2.2K_0402_5%

HDMICLK_NB <27> HDMIDAT_NB <27>

TMDS_B_HPD# <27>

TMDS_B_DATA2# <27> TMDS_B_DATA2 <27> TMDS_B_DATA1# <27> TMDS_B_DATA1 <27> TMDS_B_DATA0# <27> TMDS_B_DATA0 <27> TMDS_B_CLK# <27> TMDS_B_CLK <27>

HDMI

RSMRST circuit

R1014

@R1014

@ 0_0402_5%

0_0402_5%

1 2

C

PM_RSMRST#

1

3

E

EC_RSMRST#<37>

A A

5

BAV99DW-7_SOT363

D36B

R1016

1 2

2.2K_0402_5%

4

E

Q3

Q3 MMBT3906_SOT23-3

MMBT3906_SOT23-3

B

1 2

2

R1015 4.7K_0402_5%R1015 4.7K_0402_5%

1

2

4

5

D36A

D36A BAV99DW-7_SOT363

BAV99DW-7_SOT363

6

3

+3VALW

SLP_S3#

SLP_S4#

SLP_S5#

3

1 2

R1004 10K_0402_5%@R1004 10K_0402_5%@

1 2

R1005 10K_0402_5%@R1005 10K_0402_5%@

1 2

R1007 10K_0402_5%@R1007 10K_0402_5%@

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(3/6)-DMI/GPIO/LVDS

NIWBA_LA5371P

1

15 52Tuesday, March 24, 2009

0.2

5

D D

PCI_CBE#3

GPIO18 = NATIVE,5V,CORE GPIO52 = NATIVE,5V,CORE GPIO54 = NATIVE,5V,CORE

C C

GPIO2 = GPI,5V,CORE GPIO3 = GPI,5V,CORE GPIO4 = GPI,5V,CORE GPIO5 = GPI,5V,CORE

DGPU_SELECT#<26,28,29>

PCI_RST#<37,38>

GNT2

Default-Internal pull up

Low=Configures DMI for ESI compatible operation(for servers only.Not for mobile/desktops)

B B

CLK_PCI_LPC<37> CLK_PCI_FB<14>

PCI_REQ0#

PCI_PIRQF# PCI_REQ3#

PCI_REQ1# PCI_FRAME# PCI_TRDY# PCI_PIRQH#

PCI_STOP# PCI_IRDY# PCI_PIRQD#

A A

DGPU_SELECT#

PCI_GNT3#

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

1 8 2 7 3 6 4 5

R1051 1K_0402_5%@R1051 1K_0402_5%@

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

*

PCI_PME#<37>

1 2 1 2

RP3

8.2K_0804_8P4R_5%

RP5

8.2K_0804_8P4R_5%

RP7

8.2K_0804_8P4R_5%

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3#

PCI_GNT0# PCI_GNT1#

PCI_GNT3#

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSEL# PCI_FRAME#

PCI_LOCK#

PCI_STOP# PCI_TRDY#

PLT_RST#

R1044

47_0402_1%

47_0402_1% 47_0402_1%

47_0402_1%

R1045

+3VS +3VS

PCI_PIRQG# PCI_PIRQC#PCI_PIRQB# PCI_PIRQA# PCI_PIRQE#

PCI_DEVSEL# PCI_LOCK# PCI_SERR# PCI_PERR#

*

5

U

46E

H40

D0

A

N34

D1

A

C44

A

D2

A38

D3

A

C36

A

D4

J34

A

D5

A40

A

D6

D45

A

D7

E36

A

D8

H48

D9

A

E40

D10

A

C40

A

D11

M48

A

D12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071

RP4

1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP6

RP6 1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

V_CE#0

N

V_CE#1

N N

V_CE#2 V_CE#3

N

V_DQS0

N

V_DQS1

N

V_DQ0 / NV_IO0 V_DQ1 / NV_IO1

N

V_DQ2 / NV_IO2

N N

V_DQ3 / NV_IO3

N

V_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_ALE NV_CLE

NV_RCOMP

PCI

USB

BUF_PLT_RST#<5,19,30,31>

NV_RB#

NV_WR#0_RE# NV_WR#1_RE#

NV_WE#_CK0 NV_WE#_CK1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

NC7SZ08P5X_NL_SC70-5

4

AY9 BD1 AP15 BD8

C

AV9

implemented, the Braidwood interface

BG8

signals can be left as No Connect (NC).

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

NV_ALE

BD3

NV_CLE

AY6

NV_RCOMP

AU2

AV7

AY8 AY5

AV11 BF5

USB20_N0

H18

USB20_P0

J18

USB20_N1

A18

USB20_P1

C18

USB20_N2

N20

USB20_P2

P20

USB20_N3

J20

USB20_P3

L20

USB20_N4

F20

USB20_P4

G20

USB20_N5

A20

USB20_P5

C20

USB20_N6

M22

USB20_P6

N22

USB20_N7

B21

USB20_P7

D21

USB20_N8

H22

USB20_P8

J22

USB20_N9

E22

USB20_P9

F22

USB20_N10

A22

USB20_P10

C22

USB20_N11

G24

USB20_P11

H24

USB20_N12

L24

USB20_P12

M24

USB20_N13

A24

USB20_P13

C24

USBRBIAS

B25

D25

Within 500 mils minimum spacing to other signal is 15mil

USB_OC#0

N16

USB_OC#1

J16

USB_OC#2

F16

USB_OC#3

L16

USB_OC#4

E14

USB_OC#5

G16

USB_OC#6

F12

USB_OC#7

T15

PCI_GNT0#

PCI_GNT1#

R1046 1K_0402_5%

R1047 1K_0402_5%@R1047 1K_0402_5%@

Boot BIOS Strap

PCI_GNT1#PCI_GNT0#

0

1

1 2

R1049 0_0402_5%R1049 0_0402_5%

@

4

12

R1052

R1052 100K_0402_5%

100K_0402_5%

U49

4

PIO8

G Weak internal PU, don't PD

heck list Rev0.8 section1.23.2 If not

GPIO15

*

：

I

L

ntel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality

H：Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality

it have weak internal PU 20K

GPIO27 Default：Do not connect(floating)

High：Enables the internal VccVRM to have a clean supply for analog rails. no need to use on board filter circuit.

12

R1043 22.6_0402_1%R1043 22.6_0402_1%

@

1 2

R1032

32.4_0402_1%

USB20_N0 <40> USB20_P0 <40> USB20_N1 <34> USB20_P1 <34> USB20_N2 <40> USB20_P2 <40>

USB20_N4 <40> USB20_P4 <40> USB20_N5 <33> USB20_P5 <33>

USB20_N8 <30> USB20_P8 <30> USB20_N9 <30> USB20_P9 <30> USB20_N10 <30> USB20_P10 <30> USB20_N11 <40> USB20_P11 <40>

USB20_N13 <30> USB20_P13 <30>

1 2

GPIO1 = GPI,3.3V,CORE GPIO6 = GPI,3.3V,CORE GPIO7 = GPI,3.3V,CORE GPIO8 = GPO,3.3V,SUS GPIO12 = GPI,3.3V,SUS

RIGHT USB

LEFT USB

USB Camera

RIGHT USB

CARD READER

WLAN

TV

EXPRESS

Bluetooth

3G CARD

USB_OC#0 <34,40>

USB_OC#2 <34,40>

DGPU_PWR_EN#<42>

Intel Anti-Theft Techonlogy

NV_ALE

Boot BIOS Location

LPC

0

1

Reserved(NAND)

0

PCI

11

SPI

*

+3VS

3

1

G

A

Y

2

B

P

5

PLT_RST#

NV_ALE

NV_CLE

3

3VS

+

+3VALW

PCH_TEMP_ALERT#<37>

DIS@

R992 0_0402_5%

SUSP#<30,37,42,47,49>

USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3

USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7

1 2

R994 0_0402_5%

1 2

HYBRID@

RP1

RP1 1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

RP2

RP2 1 8 2 7 3 6 4 5

8.2K_0804_8P4R_5%

High=Enabled

Low=Disable(floating)

R1048 1K_0402_5%@R1048 1K_0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal PU,Do not pull low

R1050 1K_0402_5%@R1050 1K_0402_5%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPIO0 = GPI,3.3V,CORE

1 2

R

101710K_0402_5%R101710K_0402_5%

1 2

R

101810K_0402_5%R101810K_0402_5%

1 2

R

C_SCI#<37>

E

C_SMI#< 37>

PUSB#<30>

C

DGPU_RST#<19>

DGPU_PWROK<47,49>

GPIO27 if pull down to turn off 1.8V VR

DGPU_PWR_EN#<42>

+3VALW

*

+1.8VS

+3VS

101910K_0402_5%R101910K_0402_5%

1 2

R102010K_0402_5% R102010K_0402_5%

1 2

R102310K_0402_5% R102310K_0402_5%

1 2

R102710K_0402_5% R102710K_0402_5%

R102910K_0402_5% R102910K_0402_5%

R103110K_0402_5% R103110K_0402_5%

1 2

R103410K_0402_5% R103410K_0402_5%

1 2

R103510K_0402_5% R103510K_0402_5%

1 2

R103610K_0402_5% R103610K_0402_5%

1 2

R103710K_0402_5% R103710K_0402_5%

1 2

R103810K_0402_5% R103810K_0402_5%

1 2

R103910K_0402_5% R103910K_0402_5%

PCH_TEMP_ALERT#

1 2

R1040 10K_0402_5%R1040 10K_0402_5%

+3VALW

NV_ALE Enable Intel Anti-Theft

Technology：8.2K PU to +3VS

Disable Intel Anti-Theft Technology：floating(internal PD)

NV_CLE

DMI termination voltage. weak internal PU, don't PD

G

PIO0

G

PIO1

G

PIO6

C_SCI#

E

C_SMI#

PUSB#

C

G

PIO15

DGPU_RST#

DGPU_PWROK

GPIO22

GPIO28

GPIO34

12

GPIO35

12

DGPU_PWR_EN#

GPIO37

GPIO38

GPIO39

GPIO45

GPIO46

GPIO48

GPIO57

VGA_EN <48>

2008/08/12 2009/08/12

U

46F

Y3

MBUSY# / GPIO0

B

C38

ACH1 / GPIO1

T

D37

T

ACH2 / GPIO6

J32

T

ACH3 / GPIO7

F10

PIO8

G

K9

L

AN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_FCBGA1071

Compal Secret Data

Deciphered Date

2

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

+3VS

+3VALW

2

LKOUT_PCIE6N

C C

LKOUT_PCIE6P

C

LKOUT_PCIE7N

C

LKOUT_PCIE7P

A

20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

1 2

R1022 10K_0402_5%R1022 10K_0402_5%

1 2

R1033 1K_0402_5%R1033 1K_0402_5%

1 2

R1182 10K_0402_5%R1182 10K_0402_5%

R1021 10K_0402_5%R1021 10K_0402_5%

@

1 2

R1041 10K_0402_5%

@

1 2

R1042 10K_0402_5%

PCH_TEMP_ALERT#

12

1

AH45

PECI

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

TP24

AH46

AF48 AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

AW22

BB22

AY45

AY46

AV43

AV45

AF13

M18

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

P6

C10

+

3VS

R

R 10K_0402_5%

10K_0402_5%

1 2

H_PECI

KB_RST#

H_THERMTRIP#_L

INT3_3V#

TP24

1025

ATEA20 < 37>

G

CLK_CPU_BCLK# <5>

CLK_CPU_BCLK <5>

H_PECI <5>

KB_RST# <37>

H_CPUPWRGD <5>

1 2

54.9_0402_1%

56_0402_5%

R1028

R1030

12

USB PORT LIST

KB_RST#

H_THERMTRIP# <5>

+VCCP

DEVICEPORT

RIGHT SIDE0

1

LEFT SIDE CMOS

2

DGPU_PWROK

DGPU_PWR_EN

3 4

RIGHT SIDE

5

CARD READER

6

DGPU_RST#

EC_SCI#

EC_SMI#

7

10 11

WIRELESS8 TV TUNNER9 NEW CARD BT

12

3G

13

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(4/6)-PCI/USB/RSVD

NIWBA_LA5371P

1

16 52Tuesday, March 24, 2009

+3VS

12

R1026

R1026 10K_0402_5%

10K_0402_5%

0.1

5

1.05VS

+

D

G1.1 no M3

504

@

504

@

L

1 2

10UH_LB2012T100MR_20%

support and not Intel LAN, VCCLAN

+

1.05VS

D D

Source=>GND

R

1055

@R1055

@

1 2

0_0603_5%

R1054

0_0402_5%

12

1

C1074

@C1074

@ 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

C1075 0.1U_0402_16V4ZC1075 0.1U_0402_16V4Z

UPDATE 0210

10U_0603_6.3V6M

C

1084

1083

C C

B B

A A

1

2

+RTCVCC

1

2

1 2

C1104

1 2

C1105

1 2

C1110

1 2

C1111

10U_0603_6.3V6M

C1085

1

2

C1089

1 2

+1.05VS

C1100

1

2

0.1U_0402_16V4Z

+3VALW

0.1U_0402_16V4Z

+3VS

0.1U_0402_16V4Z

+VCCP

VCCP_VCCA_CLK

+

10U_0603_6.3V6M

C1070

C1069

1

@

2

T83PAD T83PAD

1 2

+1.05VS

1U_0402_6.3V6K

C1076

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

C1086

C1087

1

2

+VCCRTCEXT

0.1U_0402_16V4Z

+1.8VS

+VCCADPLLA

+VCCADPLLB

1U_0402_6.3V6K

C1101

1

2

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

1U_0402_6.3V6K

C1102

1

2

+VCCSST

0.2A@3.3V

0.2A@3.3V0.2A@3.3V

0.4A@3.3V

0.4A@3.3V0.4A@3.3V

0.1A@1.1V

0.1A@1.1V0.1A@1.1V

0.1U_0402_16V4Z

C1114

1

2

2mA@3.3V

2mA@3.3V2mA@3.3V

C1120

1

2

1U_0402_6.3V6K

C1115

1

2

0.1U_0402_16V4Z

1U_0402_6.3V6K

+V1.1A_INT_VCCSUS

C1113

1

2

C1119

1

2

1U_0402_6.3V6K

AP51

AP53

AF23

AF24

Y20

AD38

AD39

AD41

AF43

AF41

AF42

V39

V41

V42

Y39

Y41

Y42

V9

AU24

BB51 BB53

BD51 BD53

AH23

AJ35

AH35

AF34

AH34

AF32

V12

Y22

P18

U19

U20

U22

V15

V16

Y16

AT18

0.1U_0402_16V4Z

AU18

A12

IBEXPEAK-M_FCBGA1071

46J

U

V

CCACLK[1]

0.052A

CCACLK[2]

V

CCLAN[1]

VCCLAN[2]

DCPSUSBYP

VCCME[1]

VCCME[2]

VCCME[3]

VCCME[4]

VCCME[5]

VCCME[6]

VCCME[7]

VCCME[8]

VCCME[9]

VCCME[10]

VCCME[11]

VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1] VCCADPLLA[2]

VCCADPLLB[1] VCCADPLLB[2]

VCCIO[21] VCCIO[22] VCCIO[23]

VCCIO[2]

VCCIO[3]

VCCIO[4]

DCPSST

DCPSUS

VCCSUS3_3[29]

VCCSUS3_3[30]

VCCSUS3_3[31]

VCCSUS3_3[32]

VCC3_3[5]

VCC3_3[6]

VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

0.344A

1.998A

0.035A

0.072A

0.073A

3.208A

>1mA

2mA

P

OWER

V

CCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13]

USB

VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

0.163A

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

>1mA

V5REF_SUS

>1mA

Clock and Miscellaneous

0.357A

PCI/GPIO/LPC

VCCSATAPLL[1]

0.032A

VCCSATAPLL[2]

SATA

CPU

6mA

HDA

VCCSUSHDA

RTC PCI/GPIO/LPC

V

CCIO[5]

V

CCIO[6] CCIO[7]

V

CCIO[8]

V

VCCIO[56]

V5REF

VCC3_3[8]

VCC3_3[9]

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16]

VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20]

VCCME[13] VCCME[14] VCCME[15] VCCME[16]

4

V24 V26 Y24 Y26

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

F24

K49

J38

L38

M36

N36

P36

U35

AD13

AK3 AK1

AH22

AT20

AH19

AD20

AF22

AD19 AF20 AF19 AH20

AB19 AB20 AB22 AD22

AA34 Y34 Y35 AA35

L30

+

1.05VS

1U_0402_6.3V6K

C1071

1

2

+3VALW

0.1U_0402_16V4Z

C1080

1

2

+1.05VS

PCH_V5REF_SUS

PCH_V5REF_RUN

+3VS

1

C1093

0.1U_0402_16V4Z

2

+3VS

1 2

C1103 0.1U_0402_16V4ZC1103 0.1U_0402_16V4Z

+1.05VS_VCCAPLL

+1.8VS

C1112

+PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23

1U_0402_6.3V6K

C1118

+3VALW

1

2

10U_0603_6.3V6M

C1106

1

@

2

1U_0402_6.3V6K

1

2

R1062 0_0402_5%R1062 0_0402_5%

1 2

R1063 0_0402_5%R1063 0_0402_5%

1 2

R1064 0_0402_5%R1064 0_0402_5%

1 2

R1065 0_0402_5%R1065 0_0402_5%

1 2

+3VALW

0.1U_0402_16V4Z

C1088

1

2

L506

@L506

@

1 2

1U_0402_6.3V6K

C1108

10UH_LB2012T100MR_20%

1

@

2

+1.05VS

3

+1.05VS

@

1 2

0_0603_5%

R1056

L507

@L507

@

1 2

10UH_LB2012T100MR_20%

10U_0603_6.3V6M

+

1.05VS

C1072

1

2

L505

@L505

@

1 2

10UH_LB2012T100MR_20%

+1.05VS

C1090

1

2

1U_0402_6.3V6K

C1096

C1097

1

2

+3VS

+1.8VS

+1.05VS_VCCFDIPLL

+1.05VS

1

C1107

@C1107

@

2

10uH inductor, 120mA

L40

1 2

10UH_LB2012T100MR_20%

C1094

220U_B_2.5VM_R35M

10uH inductor, 120mA

L42 10UH_LB2012T100MR_20%

10UH_LB2012T100MR_20%

220U_B_2.5VM_R35M

C1094

L42

1 2

C1007

1U_0402_6.3V6K

10U_0603_6.3V6M

C1073

1

2

+1.05VS_APLL

10U_0805_6.3V6M

C1081

1

@

2

1U_0402_6.3V6K

C1091

1

2

10U_0603_6.3V6M

1U_0402_6.3V6K

C1098

1

2

1

+

C104

C104 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

+

C109

C109 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

U

46G

AB24

CCCORE[1]

V

AB26

CCCORE[2]

V

AB28

V

CCCORE[3]

AD26

V

CCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_FCBGA1071

1

12

2

1

2

P

1.524A

0.042A

0.035A

6mA

+VCCADPLLA+1.05VS

R573

R573 0_0402_5%

0_0402_5% @

@

+VCCADPLLB

OWER

0.069A

CRTLVDS

0.030A

VCC CORE

0.059A

HVCMOS

0.061A

DMI

PCI E*

0.156A

NAND / SPI

0.085A

FDI

2

V

VSSA_DAC[1]

VSSA_DAC[2]

VSSA_LVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCCVRM[2]

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

CCADAC[1]

CCADAC[2]

VCCALVDS

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

VCCDMI[1]

VCCDMI[2]

AE50

C1077

AE52

AF53

@

AF51

AH38

AH39

AP43 AP45 AT46 AT45

0.01U_0402_16V7K

AB34

AB35

AD35

AT24

AT16

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

R1060

100_0402_1%

+

3VS_DAC

10U_0805_6.3V6M

0.01U_0402_16V7K

C1078

1

@

2

+VCCA_LVDS

12

R136

R136 0_0402_5%

0_0402_5% DIS@

DIS@

+VCCTX_LVDS

C88

1

C87

C87 UMA@

UMA@

+3VS

+1.8VS

+VCCP

2

1 2

C1082 0.1U_0402_16V4ZC1082 0.1U_0402_16V4Z

1 2

C1092 1U_0402_6.3V6KC1092 1U_0402_6.3V6K

0.1U_0402_16V4Z

C1099

1

2

+3VS

0.1U_0402_16V4Z

C1109

1

2

21

D37

CH751H-40PT_SOD323-2

1 2

1

C1116

0.1U_0402_10V6K

2

R

1053

1 2

0.1U_0402_16V4Z

0_0603_5%

C1079

0_0603_5%

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K 1

C1173

C1173 UMA@

UMA@

2

R1058 0_0402_5%R1058 0_0402_5%

1 2

R1059 0_0402_5%@ R1059 0_0402_5%@

1 2

PCH_V5REF_SUS

1

+

3VS

R135 0.022_0805_1%UMA@R135 0.022_0805_1%UMA@

1 2

0.1uH inductor, 200mA

10U_0805_6.3V6M

10U_0805_6.3V6M 1

2

10U_0805_6.3V6M

100_0402_1%

C1341

C1341 UMA@

UMA@

R1061

1

2

+5VS +3VS+3VALW+5VALW

+3VS

+1.8VS

L12

UMA@L12

UMA@

0.1UH_MLF1608DR10KT_10%_1608

12

+1.8VS

+3VS

1 2

12

R154

R154 0_0402_5%

0_0402_5% DIS@

DIS@

21

D38

CH751H-40PT_SOD323-2

PCH_V5REF_RUN

1

C1117

C1117 1U_0402_6.3V6K

1U_0402_6.3V6K

2

20 mils20 mils

Security Classification

2008/08/12 2009/08/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/08/12 2009/08/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(5/6)-PWR

NIWBA_LA5371P

1

17 52Tuesday, March 24, 2009

0.1

5

U

46I

AY7

SS[159]

V

B11

V

SS[160]

B15

V

SS[161]

B19

D D

C C

B B

A A

B23 B31 B35 B39 B43 B47

BG12

BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49

BB5 BC10 BC14 BC18

BC2 BC22 BC32 BC36 BC40 BC44 BC52

BH9 BD48 BD49

BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50

BE6

BE8

BF3 BF49 BF51

BG18 BG24

BG4

BG50

BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47

BH7

C12

C50

D51

E12

E16

E20

E24

E30

E34

E38

E42

E46

E48

F49

G10 G14 G18

G22 G32 G36 G40 G44 G52

AF39

H16

H20

H30

H34

H38

H42

G2

B7

E6 E8

F5

VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

4

H49

SS[259]

V V V VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

SS[260] SS[261]

H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

3

U

46H

AB16

V

SS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_FCBGA1071

2

AK30

VSS[80]

AK31

VSS[81]

AK32

VSS[82]

AK34

VSS[83]

AK35

VSS[84]

AK38

VSS[85]

AK43

VSS[86]

AK46

VSS[87]

AK49

VSS[88]

AK5

VSS[89]

AK8

VSS[90]

AL2

VSS[91]

AL52

VSS[92]

AM11

VSS[93]

BB44

VSS[94]

AD24

VSS[95]

AM20

VSS[96]

AM22

VSS[97]

AM24

VSS[98]

AM26

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

1

IBEXPEAK-M_FCBGA1071

Security Classification

2008/10/31 2009/10/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2008/10/31 2009/10/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

IBEX-M(6/6)-GND

NIWBA_LA5371P

1

18 52Tuesday, March 24, 2009

0.2

5

CIE_CTX_GRX_P[0..15]

P

CIE_CTX_GRX_P[0..15]<6>

CIE_CTX_GRX_N[0..15]<6>

P

CIE_CRX_GTX_N[0..15]<6>

P

CIE_CRX_GTX_P[0..15]<6>

D D

P

CIE_CTX_GRX_N[0..15]

CIE_CRX_GTX_N[0..15]

P

CIE_CRX_GTX_P[0..15]

P

VGA@

VGA@ PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

C C

B B

BUF_PLT_RST#<5 ,16,30,31>

DGPU_RST#<16>

NC7SZ08P5X_NL_SC70-5 HYBRID@

BUF_PLT_RST#

DGPU_RST#

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15

PEG_CLKREQ#<14>

R1187 0_0402_5%

1 2

2

B

1

A

VGA@

+3VS

5

U16

P

G

3

VGA@

C1122 0.1U_0402_10V6K

1 2

C1123 0.1U_0402_10V6KC1123 0.1U_0402_10V6K

1 2

C1124 0.1U_0402_10V6KC1124 0.1U_0402_10V6K

1 2

C1125 0.1U_0402_10V6KC1125 0.1U_0402_10V6K

1 2

C1126 0.1U_0402_10V6KC1126 0.1U_0402_10V6K

1 2

C1127 0.1U_0402_10V6KC1127 0.1U_0402_10V6K

1 2

C1128 0.1U_0402_10V6KC1128 0.1U_0402_10V6K

1 2

C1129 0.1U_0402_10V6KC1129 0.1U_0402_10V6K

1 2

C1130 0.1U_0402_10V6KC1130 0.1U_0402_10V6K

1 2

C1131 0.1U_0402_10V6KC1131 0.1U_0402_10V6K

1 2

C1132 0.1U_0402_10V6KC1132 0.1U_0402_10V6K

1 2

C1133 0.1U_0402_10V6KC1133 0.1U_0402_10V6K

1 2

C1134 0.1U_0402_10V6KC1134 0.1U_0402_10V6K

1 2

C1135 0.1U_0402_10V6KC1135 0.1U_0402_10V6K

1 2

C1136 0.1U_0402_10V6KC1136 0.1U_0402_10V6K

1 2

C1137 0.1U_0402_10V6KC1137 0.1U_0402_10V6K

1 2

C1138 0.1U_0402_10V6KC1138 0.1U_0402_10V6K

1 2

C1139 0.1U_0402_10V6KC1139 0.1U_0402_10V6K

1 2

C1140 0.1U_0402_10V6KC1140 0.1U_0402_10V6K

1 2

C1141 0.1U_0402_10V6KC1141 0.1U_0402_10V6K

1 2

C1142 0.1U_0402_10V6KC1142 0.1U_0402_10V6K

1 2

C1143 0.1U_0402_10V6KC1143 0.1U_0402_10V6K

1 2

C1144 0.1U_0402_10V6KC1144 0.1U_0402_10V6K

1 2

C1145 0.1U_0402_10V6KC1145 0.1U_0402_10V6K

1 2

C1146 0.1U_0402_10V6KC1146 0.1U_0402_10V6K

1 2

C1148 0.1U_0402_10V6KC1148 0.1U_0402_10V6K

1 2

C1149 0.1U_0402_10V6KC1149 0.1U_0402_10V6K

1 2

C1150 0.1U_0402_10V6KC1150 0.1U_0402_10V6K

1 2

C1151 0.1U_0402_10V6KC1151 0.1U_0402_10V6K

1 2

C1152 0.1U_0402_10V6KC1152 0.1U_0402_10V6K

1 2

C1153 0.1U_0402_10V6KC1153 0.1U_0402_10V6K

1 2

C1154 0.1U_0402_10V6KC1154 0.1U_0402_10V6K

1 2

+3VS_D

1 2

R1080 0_0402_5%@R1080 0_0402_5%@

4

Y

12

R1085

10K_0402_5%

@

CLK_PCIE_VGA<14> CLK_PCIE_VGA#<1 4>

10K_0402_5%VGA@

CLOSE Y4

@

27M_CLK<12>

27M_CLK_SS<12>

PULL UP BY PCH SIDE

PULL UP BY LVDS CONN SIDE

R1092 2.2K_0402_5%

+3VS_D

XTALIN

A A

XTALOUT

Y9

VGA@Y9

VGA@

3

OUT

1

VGA@

C1167

C1167 20P_0402_50V8

20P_0402_50V8

2

27MHZ_16PF_X7T027000BG1H-V

5

GND

IN

R1092 2.2K_0402_5%

R1091 2.2K_0402_5%

VGA@

VGA@ VGA@

PULL UP BY RGB SIDE

4

1

VGA@

1

VGA@

VGA@ C1168

C1168 20P_0402_50V8

20P_0402_50V8

2

1 2

R1089 0_0402_5%

@

1 2

R1090 0_0402_5%

SMB_EC_CK2_R<14,41> SMB_EC_DA2_R<14,41>

VGA_LVDS_SCL<29> VGA_LVDS_SDA<29>

VGA_DDCCLK<28> VGA_DDCDATA<28>

P P P P P P P P P P P PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15

PCIE_CRX_GTX_C_P0 PCIE_CRX_GTX_C_N0 PCIE_CRX_GTX_C_P1 PCIE_CRX_GTX_C_N1 PCIE_CRX_GTX_C_P2 PCIE_CRX_GTX_C_N2 PCIE_CRX_GTX_C_P3 PCIE_CRX_GTX_C_N3 PCIE_CRX_GTX_C_P4 PCIE_CRX_GTX_C_N4 PCIE_CRX_GTX_C_P5 PCIE_CRX_GTX_C_N5 PCIE_CRX_GTX_C_P6 PCIE_CRX_GTX_C_N6 PCIE_CRX_GTX_C_P7 PCIE_CRX_GTX_C_N7 PCIE_CRX_GTX_C_P8 PCIE_CRX_GTX_C_N8 PCIE_CRX_GTX_C_P9 PCIE_CRX_GTX_C_N9 PCIE_CRX_GTX_C_P10 PCIE_CRX_GTX_C_N10 PCIE_CRX_GTX_C_P11 PCIE_CRX_GTX_C_N11 PCIE_CRX_GTX_C_P12 PCIE_CRX_GTX_C_N12 PCIE_CRX_GTX_C_P13 PCIE_CRX_GTX_C_N13 PCIE_CRX_GTX_C_P14 PCIE_CRX_GTX_C_N14 PCIE_CRX_GTX_C_P15 PCIE_CRX_GTX_C_N15

+PLLVDD

4

CIE_CTX_GRX_P0 CIE_CTX_GRX_N0 CIE_CTX_GRX_P1 CIE_CTX_GRX_N1 CIE_CTX_GRX_P2 CIE_CTX_GRX_N2 CIE_CTX_GRX_P3 CIE_CTX_GRX_N3 CIE_CTX_GRX_P4 CIE_CTX_GRX_N4 CIE_CTX_GRX_P5

12

R1079

1 2

R1082 200_0402_5%@R1082 200_0402_5%@

R1084 2.49K_0402_1%

4

12

VGA@

+SP_PLLVDD

XTALIN XTALOUT

XTAL_OUTBUFF XTAL_SSIN

SMB_EC_CK2_R SMB_EC_DA2_R

VGA_LVDS_SCL VGA_LVDS_SDA

HDMI_SCL HDMI_SDA

VGA_DDCCLK VGA_DDCDATA

HDCP_I2CH_SCL HDCP_I2CH_SDA

50A

U

AP17

P

EX_RX0

AN17

P

EX_RX0_N

AN19

P

EX_RX1

AP19

P

EX_RX1_N

AR19

EX_RX2

P

AR20

P

EX_RX2_N

AP20

P

EX_RX3

AN20

P

EX_RX3_N

AN22

P

EX_RX4

AP22

P

EX_RX4_N

AR22

EX_RX5

P

AR23

PEX_RX5_N

AP23

PEX_RX6

AN23

PEX_RX6_N

AN25

PEX_RX7

AP25

PEX_RX7_N

AR25

PEX_RX8

AR26

PEX_RX8_N

AP26

PEX_RX9

AN26

PEX_RX9_N

AN28

PEX_RX10

AP28

PEX_RX10_N

AR28

PEX_RX11

AR29

PEX_RX11_N

AP29

PEX_RX12

AN29

PEX_RX12_N

AN31

PEX_RX13

AP31

PEX_RX13_N

AR31

PEX_RX14

AR32

PEX_RX14_N

AR34

PEX_RX15

AP34

PEX_RX15_N

AL17

PEX_TX0

AM17

PEX_TX0_N

AM18

PEX_TX1

AM19

PEX_TX1_N

AL19

PEX_TX2

AK19

PEX_TX2_N

AL20

PEX_TX3

AM20

PEX_TX3_N

AM21

PEX_TX4

AM22

PEX_TX4_N

AL22

PEX_TX5

AK22

PEX_TX5_N

AL23

PEX_TX6

AM23

PEX_TX6_N

AM24

PEX_TX7

AM25

PEX_TX7_N

AL25

PEX_TX8

AK25

PEX_TX8_N

AL26

PEX_TX9

AM26

PEX_TX9_N

AM27

PEX_TX10

AM28

PEX_TX10_N

AL28

PEX_TX11

AK28

PEX_TX11_N

AK29

PEX_TX12

AL29

PEX_TX12_N

AM29

PEX_TX13

AM30

PEX_TX13_N

AM31

PEX_TX14

AM32

PEX_TX14_N

AN32

PEX_TX15

AP32

PEX_TX15_N

AR16

PEX_REFCLK

AR17

PEX_REFCLK_N

AR13

PEX_CLKREQ_N

AJ17

PEX_TSTCLK_OUT

AJ18

PEX_TSTCLK_OUT_N

AM16

PEX_RST_N

AG21

PEX_TERMP

AE9

PLLVDD

AF9

SP_PLLVDD

AD9

VID_PLLVDD

B1

XTAL_IN

B2

XTAL_OUT

D1

XTAL_OUTBUFF

D2

XTAL_SSIN

E2

I2CS_SCL

E1

I2CS_SDA

E3

I2CC_SCL

E4

I2CC_SDA

G3

I2CB_SCL

G2

I2CB_SDA

G1

I2CA_SCL

G4

I2CA_SDA

F6

I2CH_SCL

G6

I2CH_SDA

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 10M@

10M@

3

art 1 of 7

P

GPIO

MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8

MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13

DVO

PCI EXPRESS

60mA

45mA 45mA

CLK

DACs

I2C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MIOA_D14

MIOB_D0 MIOB_D1 MIOB_D2 MIOB_D3 MIOB_D4 MIOB_D5 MIOB_D6 MIOB_D7 MIOB_D8

MIOB_D9 MIOBD_10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14

MIOA_HSYNC

MIOA_VSYNC

MIOB_HSYNC

MIOB_VSYNC

MIOA_DE

MIOA_CTL3

MIOA_VREF

MIOB_DE

MIOB_CTL3

MIOB_VREF

MIOA_CLKIN

MIOA_CLKOUT

MIOB_CLKIN

MIOB_CLKOUT

MIOA_CLKOUT_N MIOB_CLKOUT_N

MIOACAL_PD_VDDQ

MIOACAL_PU_GND

MIOBCAL_PD_VDDQ

MIOBCAL_PU_GND

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_HSYNC DACB_VSYNC

DACB_VDD DACB_VREF DACB_RSET

G

PIO0

G

PIO1

G

PIO2

G

PIO3 PIO4

G G

PIO5

G

PIO6

G

PIO7

G

PIO8

G

PIO9

PIO10

G GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23

3

K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6

N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6

Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6

N3 L3

W1 W2

N2 P5 N5

Y5 W3 AF1

N4 R4

AE1 V4

T4 W4

U5 T5

AA7 AA6

AM15 AM14 AL14

AM13 AL13

AJ12 AK12 AK13

AK4 AL4 AJ4

AM1 AM2

AG7 AK6 AH7

2008/03/25 2008/04/

N

V_INVTPWM

V

GA_ENVDD_R

V

GA_ENBKL_R

G

PU_VID0

G

PU_VID1

VGA@

1 2

R1068 10K_0402_5%

VGA@

1 2

R1069 10K_0402_5%

@

External Spread Spectrum

OSC_OUT

If External Spread Spectrum not stuff then stuff resistor

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_HSYNC VGA_VSYNC

+DACA_VDD DACA_VREF DACA_RSET

VGA@

VGA@ R1093

R1093 124_0402_1%

124_0402_1%

+DACB_VDD

R1094 10K_0402_5%

Compal Secret Data

H

V

GA_ENVDD_R <29>

V

GA_ENBKL_R <29>

PAD

T85

U52

1

REFOUT

2

XOUT

3

XIN/CLKIN

ASM3P2872AF-06OR_TSOT-23-6@

12

R1086 150_0402_1%VGA@R1086 150_0402_1%VGA@

R1087 150_0402_1%VGA@R1087 150_0402_1%VGA@

R1088 150_0402_1%VGA@R1088 150_0402_1%VGA@

VGA_CRT_R <28> VGA_CRT_G <28> VGA_CRT_B <28 >

VGA_HSYNC <28> VGA_VSYNC <28>

1

VGA@

VGA@ C1163

C1163

0.1U_0402_16V4Z

2

VGA@

12

Deciphered Date

DMI_DETECT_VGA <26>

PAD

84

T

10K_0402_5%

VSS

MODOUT

VDD

R108110K_0402_5% VGA@ R108110K_0402_5% VGA@

R108310K_0402_5% VGA@ R108310K_0402_5% VGA@

CRT OUT

1 2

VGA@

VGA@ C1160

C1160

2

@

12

VGA@

R1066

HDCP_I2CH_SCL

HDCP_I2CH_SDA

6

OSC_SPREAD

5

4

470P_0402_50V7K

1

VGA@

VGA@ C1161

C1161

2

4700P_0402_16V7K

2

G

PU_VID0 <48>

G

PU_VID1 <48>

12

VGA@

R1067

10K_0402_5%

+3VS_D

R1070

2.2K_0402_5%

2.2K_0402_5% VGA@

VGA@

+3VS_D

1

@

@ C1147

C1147

0.1U_0402_16V4Z

2

+1.05VS_D +PLLVDD

+DACA_VDD

1 2

L509MBK1608121YZF_0603

2

VGA@

VGA@ C1162

C1162

4.7U_0603_6.3V6M

1

VGA@

+3VS_D

1

PIO6

G

GPU_VID1 GPU_VID0 VGA_CORE

0

1 0

R1071

2.2K_0402_5%

2.2K_0402_5% VGA@

VGA@

@

@ R1073

R1073

2.2K_0402_5%

OSC_OUT XTAL_OUTBUFF

OSC_SPREAD

L508 MBK1608121YZF_0603

1 2

VGA@

L510

1 2

MBK1608121YZF_0603

Compal Electronics,Ltd.

Title

N10x-GS PCIE,LVDS,GPIO,CLK

Size Document Numbe r Rev

Size Document Number Rev

Custom

Date: Sheet of

PIO5 N10M-GS N10P-GS

G

.8V

00

1

12

@

@ R1072

R1072 10K_0402_5%

10K_0402_5%

R1075 22_0402_5%@R1075 22_0402_5%@

1 2

R1179 22_0402_5%@R1179 22_0402_5%@

1 2

1U_0603_10V4Z

VGA@L510

VGA@

1U_0603_10V4Z

C1164

C1164 VGA@

VGA@

VGA@ C1155

C1155

VGA@

VGA@ C11584700P_0402_16V7K

C11584700P_0402_16V7K

0

0.85V 12

0

.9V

1

VGA@

VGA@ C1121

C1121

0.1U_0402_16V4Z

2

U51

VGA@U51

VGA@

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8

1U_0603_10V4Z

VGA@

VGA@ C1156

C1156

1

2

C1165

A0 A1 A2

GND

VGA@ R1074

VGA@

12

VGA@

VGA@ C1157

C1157

1U_0603_10V4Z

UNDER GPU

VGA@

VGA@ C1159

C1159

0.1U_0402_16V4Z

+SP_PLLVDD+1.05VS_D

1

VGA@

2

0.1U_0402_16V4Z

NIWBA_LA5371P

19 52Tuesday, March 24, 2009

1

19 52Tuesday, March 24, 2009

P

-State

12

0,10

1 2 3 4

12

R1074 100K_0402_1%

100K_0402_1%

R1077

R1077 10K_0402_5%

10K_0402_5% VGA@

VGA@

XTAL_SSIN

R1178

R1178 10K_0402_5%

10K_0402_5% VGA@

VGA@

NEAR GPU

4700P_0402_16V7K

C1166

C1166 VGA@

VGA@

0.1

5

F

BA_CMD[0..30]

F

BA_DQM[0..7]

F

BA_DQS[0..7]

F

BA_DQS#[0..7]

BA_D[0..63]

F

U

50B

D D

C C

+1.5VS_D

B B

R1105

1K_0402_5%

R1109

1K_0402_5%

@

UNDER GPU

10MIL

+FB_VREF

1

C1169

0.01U_0402_16V7K

2

@

+FB_PLLVDD

+1.5VS_D

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

+FB_PLLVDD

+FB_VREF

VGA@

1 2

R1110 10K_0402_5%

AG30 AG32 AH31

AC32 AD30 AN33

AM33

AH30 AH33 AH35 AH34 AH32

AM34 AM35

AC35

AG27

L32

FBA_D0

N33

FBA_D1

L33

FBA_D2

N34

FBA_D3

N35

FBA_D4

P35

FBA_D5

P33

FBA_D6

P34

FBA_D7

K35

FBA_D8

K33

FBA_D9

K34

FBA_D10

H33

FBA_D11

G34

FBA_D12

G33

FBA_D13

E34

FBA_D14

E33

FBA_D15

G31

FBA_D16

F30

FBA_D17

G30

FBA_D18

G32

FBA_D19

K30

FBA_D20

K32

FBA_D21

H30

FBA_D22

K31

FBA_D23

L31

FBA_D24

L30

FBA_D25

M32

FBA_D26

N30

FBA_D27

M30

FBA_D28

P31

FBA_D29

R32

FBA_D30

R30

FBA_D31 FBA_D32 FBA_D33 FBA_D34

AF31

FBA_D35

AF30

FBA_D36

AE30

FBA_D37 FBA_D38 FBA_D39 FBA_D40

AL31

FBA_D41 FBA_D42

AL33

FBA_D43

AK30

FBA_D44

AK32

FBA_D45

AJ30

FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51

AJ33

FBA_D52

AL35

FBA_D53 FBA_D54 FBA_D55

AF33

FBA_D56

AE32

FBA_D57

AF34

FBA_D58

AE35

FBA_D59

AE34

FBA_D60

AE33

FBA_D61

AB32

FBA_D62 FBA_D63

FB_DLLAVDD

AF27

FB_PLLAVDD

J27

FB_VREF

T30

FBA_DEBUG

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 10M@

10M@

Part 2 of 7

MEMORY INTERFACE

4

A

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

BA_CMD[0..30] <24>

F

BA_DQM[0..7] <24>

F

BA_DQS[0..7] <24>

F

BA_DQS#[0..7] <24>

BA_D[0..63] <24>

F

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29

P32 H34 J30 P30 AF32 AL32 AL34 AF35

L35 G35 H31 N32 AD32 AJ31 AJ35 AC34

L34 H35 J32 N31 AE31 AJ32 AJ34 AC33

T32 T31

AC31 AC30

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS#0 FBA_DQS#1 FBA_DQS#2 FBA_DQS#3 FBA_DQS#4 FBA_DQS#5 FBA_DQS#6 FBA_DQS#7

FBA_DQS0 FBA_DQS1 FBA_DQS2 FBA_DQS3 FBA_DQS4 FBA_DQS5 FBA_DQS6 FBA_DQS7

FBA_CLK0 FBA_CLK0#

FBA_CLK1 FBA_CLK1#

PDATE 0216

U

R1095 10K_0402 _5%

FBA_CMD7

R1101 10K_0402 _5%

FBA_CMD15

R1096 10K_0402 _5%

FBA_CMD18

R1098 10K_0402 _5%

FBA_CMD28

R1099 10K_0402 _5%

FBA_CMD30

FBA_CLK0 <24> FBA_CLK0# <24>

FBA_CLK1 <24> FBA_CLK1# <24>

3

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

1 2

VGA@

+1.5VS_D

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

VGA@

R1106 60.4_0402_1%

VGA@

12

R1107 40.2_0402_1%

R1108 40.2_0402_1%

U50C

B13

FBC_D0

D13

FBC_D1

A13

FBC_D2

A14

FBC_D3

C16

FBC_D4

B16

FBC_D5

A17

FBC_D6

D16

FBC_D7

C13

FBC_D8

B11

FBC_D9

C11

FBC_D10

A11

FBC_D11

C10

FBC_D12

C8

FBC_D13

B8

FBC_D14

A8

FBC_D15

E8

FBC_D16

F8

FBC_D17

F10

FBC_D18

F9

FBC_D19

F12

FBC_D20

D8

FBC_D21

D11

FBC_D22

E11

FBC_D23

D12

FBC_D24

E13

FBC_D25

F13

FBC_D26

F14

FBC_D27

F15

FBC_D28

E16

FBC_D29

F16

FBC_D30

F17

FBC_D31

D29

FBC_D32

F27

FBC_D33

F28

FBC_D34

E28

FBC_D35

D26

FBC_D36

F25

FBC_D37

D24

FBC_D38

E25

FBC_D39

E32

FBC_D40

F32

FBC_D41

D33

FBC_D42

E31

FBC_D43

C33

FBC_D44

F29

FBC_D45

D30

FBC_D46

E29

FBC_D47

B29

FBC_D48

C31

FBC_D49

C29

FBC_D50

B31

FBC_D51

C32

FBC_D52

B32

FBC_D53

B35

FBC_D54

B34

FBC_D55

A29

FBC_D56

B28

FBC_D57

A28

FBC_D58

C28

FBC_D59

C26

FBC_D60

D25

FBC_D61

B25

FBC_D62

A25

FBC_D63

K27

FBCAL_PD_VDDQ

L27

FBCAL_PU_GND

M27

FBCAL_TERM_GND

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 10M@

10M@

F

BC_CMD[0..30]

F

BC_DQM[0..7]

F

BC_DQS[0..7]

BC_DQS#[0..7]

F

BC_D[0..63]

F

2

Part 3 of 7

MEMORY INTERFACE C

FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7

FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7

F

BC_CMD[0..30] <25>

F

BC_DQM[0..7] <25>

F

BC_DQS[0..7] <25>

BC_DQS#[0..7] <25>

F

BC_D[0..63] <25>

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8

FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

FBC_DEBUG

FBC_CMD0

C17

FBC_CMD1

B19

FBC_CMD2

D18

FBC_CMD3

F21

FBC_CMD4

A23

FBC_CMD5

D21

FBC_CMD6

B23

FBC_CMD7

E20

FBC_CMD8

G21

FBC_CMD9

F20

FBC_CMD10

F19

FBC_CMD11

F23

FBC_CMD12

A22

FBC_CMD13

C22

FBC_CMD14

B17

FBC_CMD15

F24

FBC_CMD16

C25

FBC_CMD17

E22

FBC_CMD18

C20

FBC_CMD19

B22

FBC_CMD20

A19

FBC_CMD21

D22

FBC_CMD22

D20

FBC_CMD23

E19

FBC_CMD24

D19

FBC_CMD25

F18

FBC_CMD26

C19

FBC_CMD27

F22

FBC_CMD28

C23

FBC_CMD29

B20

FBC_CMD30

A20

FBC_DQM0

A16

FBC_DQM1

D10

FBC_DQM2

F11

FBC_DQM3

D15

FBC_DQM4

D27

FBC_DQM5

D34

FBC_DQM6

A34

FBC_DQM7

D28

FBC_DQS#0

B14

FBC_DQS#1

B10

FBC_DQS#2

D9

FBC_DQS#3

E14

FBC_DQS#4

F26

FBC_DQS#5

D31

FBC_DQS#6

A31

FBC_DQS#7

A26

FBC_DQS0

C14

FBC_DQS1

A10

FBC_DQS2

E10

FBC_DQS3

D14

FBC_DQS4

E26

FBC_DQS5

D32

FBC_DQS6

A32

FBC_DQS7

B26

FBC_CLK0

E17

FBC_CLK0#

D17

FBC_CLK1

D23

FBC_CLK1#

E23

VGA@

G19

VGA@

R1111 10K_0402_5%

1

PDATE 0216

U

R1100 10K_0 402_5%

FBC_CMD7

FBC_CMD15

FBC_CMD18

FBC_CMD28

FBC_CMD30

FBC_CLK0 <25> FBC_CLK0# <25>

FBC_CLK1 <25> FBC_CLK1# <25>

12

+1.5VS_D

1 2

VGA@

R1102 10K_0 402_5%

1 2

VGA@

R1097 10K_0 402_5%

1 2

VGA@

R1103 10K_0 402_5%

1 2

VGA@

R1104 10K_0 402_5%

1 2

VGA@

Place Components Close to BGA

Memory/PKG

+1.05VS_D +FB_PLLVDD

A A

L511 MBK1608121YZF_0603

1 2

VGA@

4.7U 6.3V K X5R 0603

VGA@

C1172

1

2

VGA@

C1170

1U_0603_10V4Z

C1170

1

VGA@

VGA@ C1171

C1171

0.1U_0402_16V4Z

2

DDR3

GDDR3

Must be used 1% resister for driver calibration

FBVDDQ

+1.5VS

+1.8VS

FBCAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND

40.2 ohm

60.4 ohm

40.2 ohm

60.4 ohm 40.2 ohm

NEAR GPU UNDER GPU

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

5

4

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N10x-GS Memory

NIWBA_LA5371P

1

20 52Tuesday, March 24, 2009

0.1

5

GA_LVDS_ACLK<2 9>

V V

GA_LVDS_ACLK#<29>

V

GA_LVDS_A0<29>

VGA_LVDS_A0#<29>

+3VS_D

2

VGA@

5

+3VS_D

VGA_HDMI_CLK+<26>

Q63A

4

Q63B

VGA_LVDS_A1<29> VGA_LVDS_A1#<29> VGA_LVDS_A2<29> VGA_LVDS_A2#<29>

VGA_LVDS_BCLK<29> VGA_LVDS_BCLK#<29> VGA_LVDS_B0<29> VGA_LVDS_B0#<29> VGA_LVDS_B1<29> VGA_LVDS_B1#<29> VGA_LVDS_B2<29> VGA_LVDS_B2#<29>

VGA_HDMI_TX2+<26>

VGA_HDMI_TX2-<26 >

VGA_HDMI_TX1+<26>

VGA_HDMI_TX1-<26 >

VGA_HDMI_TX0+<26>

VGA_HDMI_TX0-<26 >

VGA_HDMI_CLK-<26>

D D

C C

VGA_HDMI_SCL<26>

B B

VGA_HDMI_SDA<26>

6 1

2N7002DW-T/R7_SOT363-6

3

4

12

R1113

4.7K_0402_5%

VGA@

12

R1118

4.7K_0402_5%

VGA@

V

GA_LVDS_ACLK

V

GA_LVDS_ACLK# GA_LVDS_A0

V VGA_LVDS_A0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2#

VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B0 VGA_LVDS_B0# VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_B2 VGA_LVDS_B2#

VGA_HDMI_TX2+ VGA_HDMI_TX2VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_CLK+ VGA_HDMI_CLK-

IFPC_AUX

IFPC_AUX_N

U

50D

AM11

I

FPA_TXC

AM12

I

FPA_TXC_N

AM8

FPA_TXD0

I

AL8

IFPA_TXD0_N

AM10

IFPA_TXD1

AM9

IFPA_TXD1_N

AK10

IFPA_TXD2

AL10

IFPA_TXD2_N

AK11

IFPA_TXD3

AL11

IFPA_TXD3_N

AP13

IFPB_TXC

AN13

IFPB_TXC_N

AN8

IFPB_TXD4

AP8

IFPB_TXD4_N

AP10

IFPB_TXD5

AN10

IFPB_TXD5_N

AR11

IFPB_TXD6

AR10

IFPB_TXD6_N

AN11

IFPB_TXD7

AP11

IFPB_TXD7_N

AM7

IFPC_L0

AM6

IFPC_L0_N

AL5

IFPC_L1

AM5

IFPC_L1_N

AM3

IFPC_L2

AM4

IFPC_L2_N

AP1

IFPC_L3

AR2

IFPC_L3_N

AR8

IFPD_L0

AR7

IFPD_L0_N

AP7

IFPD_L1

AN7

IFPD_L1_N

AN5

IFPD_L2

AP5

IFPD_L2_N

AR5

IFPD_L3

AR4

IFPD_L3_N

AH6

IFPE_L0

AH5

IFPE_L0_N

AH4

IFPE_L1

AG4

IFPE_L1_N

AF4

IFPE_L2

AF5

IFPE_L2_N

AE6

IFPE_L3

AE5

IFPE_L3_N

AL2

IFPF_L0

AL3

IFPF_L0_N

AJ3

IFPF_L1

AJ2

IFPF_L1_N

AJ1

IFPF_L2

AH1

IFPF_L2_N

AH2

IFPF_L3

AH3

IFPF_L3_N

AP2

IFPC_AUX_I2CW_SCL

AN3

IFPC_AUX_I2CW_SDA_N

AP4

IFPD_AUX_I2CX_SCL

AN4

IFPD_AUX_I2CX_SDA_N

AE4

IFPE_AUX_I2CY_SCL

AD4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

3

Part 4 of 7

NC

LVDS/TMDS

VDD_SENSE_0 VDD_SENSE_1 VDD_SENSE_2

GND_SENSE_0 GND_SENSE_1 GND_SENSE_2

TEST

TESTMODE

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

N

C_0

N

C_1 C_2

N NC_3 NC_4 NC_5 NC_6 NC_7 NC_8

NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45 NC_46 NC_47 NC_48

A2 A7 B7 C5 C7 D5 D6 D7 E5 E7 F4 G5 G11 G12 G14 G15 G27 G28 G24 G25 H32 J18 J19 J25 J26 L29 M7 M29 P6 P29 R29 U7 V6 Y4 AA4 AB4 AB7 AC5 AD6 AD29 AE29 AF6 AG6 AG20 AG29 AH29 AJ5 AK15 AL7

D35 P7 AD20

AD19 E35 R7

AP35 AP14 AN14 AN16 AR14 AP16

C3 D3 C4 D4

1 2

TESTMODE JTAG_TCK

JTAG_TDO

JTAG_TRST_N

ROM_SI ROM_SO ROM_SCLK

VGA@

R1112 0_0402_5%

VGA@

R1114 0_0402_5%

1K_0402_5%

1K_0402_5% R1116

VGA@ R1116

VGA@R1118

ROM_SI <23 > ROM_SO <23> ROM_SCLK <23>

PAD

2

+VGASENSE <48>

+3VS_D

12

@

@ R1115

R1115 10K_0402_5%

10K_0402_5%

T86

12

T87

R1117

R1117 10K_0402_5%

10K_0402_5% VGA@

VGA@

1

5V PULL UP IN CONNECTER SIDE

PAD

T89

R1120

VGA@R1120

VGA@

+3VS_D

A A

5

1 2

10K_0402_5%

T89

STRAP0<23> STRAP1<23> STRAP2<23>

4

STRAP0 STRAP1 STRAP2

A4

BUFRST_N

AB5

CEC

W5

STRAP0

W7

STRAP1

V7

STRAP2

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 10M@

10M@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

GENERAL

MULTI_STRAP_REF0_GND

MULTI_STRAP_REF1_GND

3

NC/SPDIF

THERMDP THERMDN

2007/10/15 2008/10/15

A5

N9

M9

B5 B4

SPDIF_IN

1 2

R1119 40.2K_0402_1%

1 2

VGA@

R1121 40.2K_0402_1%

VGA@

Compal Secret Data

Deciphered Date

PAD

T88

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

N10P/N10M LVDS,HDMI

NIWBA_LA5371P

1

21 52Tuesday, March 24, 2009

0.1

5

VGA_CORE

+

VGA@

VGA@ C

C

1181

4700P_0402_16V7K

VGA@

VGA@ C

C

1184

0.01U_0402_16V7K

L512MBK1608121YZF_0603

0.01U_0402_16V7K

VGA@

VGA@ C1185

C1185 .022U_0402_16V7

.022U_0402_16V7

VGA@

VGA@ C1190

C1190

0.22U_0603_10V7K

1

VGA@

C1193

1U_0603_10V4Z

2

D D

+1.05VS_D

C C

1 2

VGA@

4.7U 6.3V K X5R 0603

VGA@

VGA@ C

C

0.01U_0402_16V7K

VGA@

VGA@ C1186

C1186 .022U_0402_16V7

.022U_0402_16V7

VGA@

VGA@ C1191

C1191

0.22U_0603_10V7K

VGA@

C1194

1176

0.1U_0402_16V4Z

VGA@

VGA@ C1195

C1195

VGA@

VGA@ C

C

1174

.015U_0402_16V7K

VGA@

VGA@ C

C

1177

0.01U_0402_16V7K

VGA@

VGA@ C1187

C1187 .022U_0402_16V7

.022U_0402_16V7

1

VGA@

VGA@ C1192

C1192

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

VGA@

VGA@ C1196

C1196

4

VGA@

VGA@ C

C

1182

.015U_0402_16V7K

VGA@

VGA@ C

C

1178

0.01U_0402_16V7K

VGA@

VGA@ C1188

C1188 .022U_0402_16V7

.022U_0402_16V7

UNDER GPU

1

4700P_0402_25V7K

2

VGA@

VGA@ C

C .022U_0402_16V7

.022U_0402_16V7

VGA@

VGA@ C

C

0.01U_0402_16V7K

VGA@

VGA@ C1189

C1189

0.1U_0402_10V7K

1

VGA@

C1197

2

1175

1179

220mA

+IFPAB_PLLVDD

VGA@

VGA@ C

C

1183

.022U_0402_16V7

VGA@

VGA@ C

C

1180

0.01U_0402_16V7K

AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 AD24

L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24

L25 M12 M14 M16 M18 M20 M22 M24

P11

P13

P15

P17

P19

U50G

DD_0

V V

DD_1

V

DD_2

V

DD_3

V

DD_4

V

DD_5 DD_6

V V

DD_7 DD_8

V

DD_9

V V

DD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

3

P

art 7 of 7

22.28A

POWER

DD_56

V V

DD_57

V

DD_58

V

DD_59

V

DD_60

V

DD_61 DD_62

V V

DD_63 DD_64

V

DD_65

V V

DD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99

VDD_100 VDD_101 VDD_102 VDD_103 VDD_104 VDD_105 VDD_106 VDD_107 VDD_108 VDD_109 VDD_110

P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17 V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24

VGA_CORE

+

1

VGA@

VGA@ C1198

C1198

0.1U_0402_16V4Z

2

1

VGA@

VGA@ C1199

C1199

0.1U_0402_16V4Z

2

1

VGA@

VGA@ C1200

C1200

0.1U_0402_16V4Z

2

UNDER GPU (0-150 Mil)

1

VGA@

VGA@ C1201

C1201

0.1U_0402_16V4Z

2

VGA@

VGA@ C1202

C1202 1U_0402_6.3V6K

1U_0402_6.3V6K

1

VGA@

VGA@ C1203

C1203 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS_D

220mA

VGA@

VGA@ L513

+3VS_D

MBK1608121YZF_0603

B B

A A

L513

1 2

C1210

4.7U 6.3V K X5R 0603

C1210

+1.8VS_D

+1.05VS_D

+1.5VS_D

1

1U_0603_10V4Z

2

VGA@

MBK1608121YZF_0603

UNDER GPU

VGA@

VGA@ C1237

C1237

0.01U_0402_16V7K

1

VGA@

VGA@ C1241

C1241

0.1U_0402_16V4Z

2

5

C1213

VGA@

1 2

VGA@

VGA@ C1238

C1238

0.01U_0402_16V7K

1

VGA@

VGA@ C1242

C1242

0.1U_0402_16V4Z

2

C1214

1U_0603_10V4Z

VGA@

L514

4.7U 6.3V K X5R 0603

VGA@

L516

4.7U 6.3V K X5R 0603

VGA@

C1226

0.1U_0402_16V4Z

VGA@

1

VGA@

C1212

1U_0603_10V4Z

2

1

1U_0603_10V4Z

2

VGA@

VGA@ C1239

C1239

0.01U_0402_16V7K

1

VGA@

VGA@ C1243

C1243

0.1U_0402_16V4Z

2

1

C1211

2

VGA@

C1217

VGA@

C1227

VGA@

VGA@ C1240

C1240

0.01U_0402_16V7K

C1215

0.1U_0402_16V4Z

VGA@

C1218

0.1U_0402_16V4Z

C1228

0.1U_0402_16V4Z

VGA@

1

2

1

2

1

2

0.1U_0402_16V4Z

4700P_0402_25V7K

0.1U_0402_16V4Z

4

+IFPD_PLLVDD

+IFPC_PLLVDD

1

2

VGA@

220mA

C1216

150mA

+IFPA_IOVDD

+IFPB_IOVDD

1

VGA@

VGA@ C1219

C1219

VGA@

C1229

VGA@ R1124

VGA@

VGA@ R1125

VGA@

150mA

2

285mA

+IFPC_IOVDD

+IFPD_IOVDD

1

285mA

2

1 2

R1122 1K_0402_5%

@

VGA@

10K_0402_5%

10K_0402_5%VG A@

12

12 12

R1123 1K_0402_5%

R1180

R1124

R1125 R1126

R1126

+1.5VS_D

+IFPAB_PLLVDD +IFPAB_RSET

+IFPA_IOVDD +IFPB_IOVDD

+IFPC_PLLVDD +IFPC_RSET

+IFPC_IOVDD

+IFPD_PLLVDD +IFPD_RSET

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPE_IOVDD +IFPF_IOVDD

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 U50E

U50E

J23

FBVDDQ_0

J24

FBVDDQ_1

J29

FBVDDQ_2

AA27

FBVDDQ_3

AA29

FBVDDQ_4

AA31

FBVDDQ_5

AB27

FBVDDQ_6

AB29

FBVDDQ_7

AC27

FBVDDQ_8

AD27

FBVDDQ_9

AE27

FBVDDQ_10

AJ28

FBVDDQ_11

B18

FBVDDQ_12

E21

FBVDDQ_13

G17

FBVDDQ_14

G18

FBVDDQ_15

G22

FBVDDQ_16

G8

FBVDDQ_17

G9

FBVDDQ_18

H29

FBVDDQ_19

J14

FBVDDQ_20

J15

FBVDDQ_21

J16

FBVDDQ_22

J17

FBVDDQ_23

J20

FBVDDQ_24

J21

FBVDDQ_25

J22

FBVDDQ_26

N27

FBVDDQ_27

P27

FBVDDQ_28

R27

FBVDDQ_29

T27

FBVDDQ_30

U27

FBVDDQ_31

U29

FBVDDQ_32

V27

FBVDDQ_33

V29

FBVDDQ_34

V34

FBVDDQ_35

W27

FBVDDQ_36

Y27

FBVDDQ_37

AK9

IFPAB_PLLVDD

AJ11

IFPAB_RSET

AG9

IFPA_IOVDD

AG10

IFPB_IOVDD

AJ9

IFPC_PLLVDD

AK7

IFPC_RSET

AJ8

IFPC_IOVDD

AC6

IFPD_PLLVDD

AB6

IFPD_RSET

AK8

IFPD_IOVDD

AJ6

IFPEF_PLLVDD

AL1

IFPEF_RSET

AE7

IFPE_IOVDD

AD7

IFPF_IOVDD

N10P-GS-A1_BGA969

Part 5 of 7

3

POWER

10M@

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 PEX_IOVDDQ_15 PEX_IOVDDQ_16 PEX_IOVDDQ_17 PEX_IOVDDQ_18 PEX_IOVDDQ_19 PEX_IOVDDQ_20 PEX_IOVDDQ_21 PEX_IOVDDQ_22 PEX_IOVDDQ_23 PEX_IOVDDQ_24

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4

PEX_PLLVDD

AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16

AK16 AK17 AK21 AK24 AK27

AG14

2A

150mA

1

VGA@

VGA@ C1204

C1204 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

VGA@

VGA@ C1220

C1220

0.1U_0402_16V4Z

2

UNDER GPU

1

VGA@

VGA@ C1205

C1205 10U_0603_6.3V6M

10U_0603_6.3V6M

2

VGA@

VGA@ C1221

C1221 1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@ C1230

C1230

0.01U_0402_16V7K

UNDER GPU

1

VGA@

VGA@ C1206

C1206 10U_0603_6.3V6M

10U_0603_6.3V6M

2

VGA@

VGA@ C1222

C1222 1U_0603_10V4Z

1U_0603_10V4Z

VGA@

VGA@ C1231

C1231

0.1U_0402_10V7K

NEAR GPU (0-750 Mil)

120mA

VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4

10M@

Issued Date

AG19 F7

J10 J11 J12 J13 J9

P9 R9 T9 U9

AA9 AB9 W9 Y9

VGA@

VGA@ C1233

C1233

0.1U_0402_10V7K

VGA@ C1234

C1234

0.1U_0402_10V7K

VGA@

VGA@ C1235

C1235 1U_0603_10V4Z

1U_0603_10V4Z

NEAR GPUUNDER GPU

VGA@

VGA@ C1244

C1244

0.1U_0402_10V7K

VGA@

VGA@ C1245

C1245

0.1U_0402_10V7K

2007/10/15 2008/10/15

+3VS_D

Compal Secret Data

Deciphered Date

2

PEX_SVDD_3V3_0 PEX_SVDD_3V3_1

MIOA_VDDQ_0 MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3

MIOB_VDDQ_0 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

VGA@

VGA@ C1207

C1207 10U_0603_6.3V6M

10U_0603_6.3V6M

2

VGA@

VGA@ C1223

C1223 1U_0603_10V4Z

1U_0603_10V4Z

VGA@

VGA@ C1232

C1232 1U_0603_10V4Z

1U_0603_10V4Z

NEAR GPU

+3VS_D

VGA@

VGA@ C1236

C1236 1U_0603_10V4Z

1U_0603_10V4Z

1

VGA@

VGA@ C1208

C1208 10U_0603_6.3V6M

10U_0603_6.3V6M

2

VGA@

VGA@ C1224

C1224 1U_0603_10V4Z

1U_0603_10V4Z

1

VGA@

VGA@ C1209

C1209 10U_0603_6.3V6M

10U_0603_6.3V6M

2

VGA@

L515

1

2

L515

VGA@

VGA@ C1225

C1225

4.7U 6.3V K X5R 0603

12

MBK1608121YZF_0603

NEAR GPU

+3VS_D

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

C

Date: Sheet of

Compal Electronics, Inc.

N10x-GS POWER

NIWBA_LA5371P

1

22 52Tuesday, March 24, 2009

+1.05VS_D

0.1

5

50F

U

P

art 6 of 7

B3

G

ND_0

B6

ND_1

G

B9

G

ND_2

B12

G

ND_3

B15

ND_4

G

B21

G

ND_5

B24

G

ND_6

B27

ND_7

G

B30

GND_8

B33

GND_9

D D

C C

B B

A A

C34

E12 E15 E18 E24 E27 E30

F31 F34

J31 J34

M11 M13 M15 M17 M19 M21 M23 M25 M31 M34

N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24

R31 R34

T11 T13 T15 T17 T19 T21 T23

T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25

V12 V14 V16

C2

E6 E9

K9

M2 M5

R2 R5

V2 V5 V9

F2

F5 J2 J5

L9

GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96

art 6 of 7

GND

ND_97

G G

ND_98

G

ND_99

ND_100

G G

ND_101

G

ND_102 ND_103

G GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192

V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AK14 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30 AP33

4

S S S ROM_SCLK ROM_SI ROM_SO

X2

S1024@

TRAP2<21>

S

TRAP1<21>

S STRAP0<21> ROM_SCLK<21>

ROM_SI<21>

ROM_SO<21>

GB1 Family GPU Strap Qptions

X76_S1024

X3

H1024@

X76_H1024

X4

S512@

X76_S512

X5

H512@

X76_H512

U50

N10P-GS

10P@

TRAP2 TRAP1 TRAP0

N10P-GS

(0xA34)

N10M-GS

(0xA74)

3

3VS_D

+

12

R

1127

10K_0402_1%

10K_0402_1% VGA@

VGA@

12

R1133

R1133 10K_0402_1%

10K_0402_1% @

@

2

12

R

1128

10K_0402_1%

10K_0402_1% @

@

12

R1134

R1134 10K_0402_1%

10K_0402_1% VGA@

VGA@

12

R

1129

45.3K_0402_1%

45.3K_0402_1% VGA@

VGA@

12

R1135

R1135 10K_0402_1%

10K_0402_1% @

@

12

@

@ R

R

1130

15K_0402_1%

12

R1136

R1136 15K_0402_1%

15K_0402_1% VGA@

VGA@

ROM_SO

Samsung

Hynix PD 15K

64Mx16 PD 15K

64Mx16

PD 10K

ROM_SO

Samsung PD 20K

Hynix PD 15K

64Mx16

PD 10K

12

@

@ R

R

1131

2K_0402_5%

12

X76@

X76@ R1137

R1137 20K_0402_1%

20K_0402_1%

12

@

@ R

R

4.99K_0402_1%

12

R1138

R1138 10K_0402_1%

10K_0402_1% VGA@

VGA@

ROM_SCLK STRAP2GPU ROM_SI

PD 20K

PD 15K

ROM_SCLK STRAP2GPU ROM_SI

PD 15K

1132

GPU DEVIDRAM_CFGGPU DEVID

PU 10K

PD 10K

1

STRAP0STRAP1FB Memory

PU 45K

STRAP0STRAP1FB Memory

PU 45K

N10P-GS-A1_BGA969

N10P-GS-A1_BGA969 10M@

10M@

5

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

N10x-GS GND & STRAP

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

NIWBA_LA5371P

1

23 52Tuesday, March 24, 2009

0.1

5

4

3

2

1

N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001

U57

U56

U55

U54

F

BA_CMD[0..30]<20>

F

BA_DQM[0..7]<20>

F

BA_DQS[0..7]<20>

F

BA_DQS#[0..7]<20>

D D

C C

FBA_D[0..63]<20 >

BA_CMD[0..30]

F

BA_DQM[0..7]

F

BA_DQS[0..7]

BA_DQS#[0..7]

F

FBA_D[0..63]

FBA_CLK0#<20> FBA_CLK1#<20>

R1140

R1140 240_0402_1%

240_0402_1%

VGA@

V

REFC_A1

V

REFD_Q1

F

BA_CMD19

F

BA_CMD25 BA_CMD22

F F

BA_CMD24 BA_CMD0

F FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CMD18

FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS0 FBA_DQS1

FBA_DQM0 FBA_DQM1

FBA_DQS#0 FBA_DQS#1

FBA_CMD15

12

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

1

A

P4

2

A

N3

A

3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3 QL4

D

QL5

D D

QL6

DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BA_D5

F

BA_D1 BA_D7

F F

BA_D0

F

BA_D6 BA_D2

F F

BA_D3 BA_D4

F

FBA_D13 FBA_D9 FBA_D14 FBA_D11 FBA_D12 FBA_D8 FBA_D15 FBA_D10

+1.5VS_D

R1141

R1141 240_0402_1%

240_0402_1%

VGA@

V

REFC_A2

V

REFD_Q2

F

BA_CMD19

F

BA_CMD25 BA_CMD22

F F

BA_CMD24 BA_CMD0

F FBA_CMD2 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CLK0 FBA_CLK0# FBA_CMD18

FBA_CMD30 FBA_CMD29 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS2 FBA_DQS3

FBA_DQM2 FBA_DQM3

FBA_DQS#2 FBA_DQS#3

FBA_CMD15

12

U55

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

1

A

P4

2

A

N3

A

3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3 QL4

D

QL5

D D

QL6

DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BA_D19

F

BA_D22 BA_D18

F F

BA_D23

F

BA_D17 BA_D21

F F

BA_D16 BA_D20

F

FBA_D31 FBA_D28 FBA_D29 FBA_D25 FBA_D27 FBA_D24 FBA_D30 FBA_D26

+1.5VS_D

FBA_CLK1<20>FBA_CLK0<20>

+1.5VS_D

R1142

R1142 240_0402_1%

240_0402_1%

VGA@

V

REFC_A3

V

REFD_Q3

F

BA_CMD19

F

BA_CMD25 BA_CMD4

F F

BA_CMD6 BA_CMD5

F FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CMD7

FBA_CMD28 FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS4 FBA_DQS5

FBA_DQM4 FBA_DQM5

FBA_DQS#4 FBA_DQS#5

FBA_CMD15

12

U56

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

1

A

P4

2

A

N3

A

3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3 QL4

D

QL5

D D

QL6

DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BA_D32

F

BA_D33 BA_D34

F F

BA_D35

F

BA_D36 BA_D37

F F

BA_D38 BA_D39

F

FBA_D40 FBA_D45 FBA_D41 FBA_D46 FBA_D43 FBA_D47 FBA_D42 FBA_D44

+1.5VS_D

R1143

R1143 240_0402_1%

240_0402_1%

VGA@

V

REFC_A4

V

REFD_Q4

F

BA_CMD19

F

BA_CMD25 BA_CMD4

F F

BA_CMD6 BA_CMD5

F FBA_CMD13 FBA_CMD21 FBA_CMD16 FBA_CMD23 FBA_CMD20 FBA_CMD17 FBA_CMD9 FBA_CMD14 FBA_CMD26

FBA_CMD12 FBA_CMD3 FBA_CMD27

FBA_CLK1 FBA_CLK1#

FBA_CMD7

FBA_CMD28 FBA_CMD8 FBA_CMD1 FBA_CMD10 FBA_CMD11

FBA_DQS7 FBA_DQS6

FBA_DQM7 FBA_DQM6

FBA_DQS#7 FBA_DQS#6

FBA_CMD15

12

U57

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

1

A

P4

2

A

N3

A

3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3 QL4

D

QL5

D D

QL6

DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BA_D60

F

BA_D59 BA_D61

F F

BA_D63

F

BA_D56 BA_D58

F F

BA_D57 BA_D62

F

FBA_D48 FBA_D52 FBA_D51 FBA_D54 FBA_D49 FBA_D55 FBA_D50 FBA_D53

+1.5VS_D

10U_0603_6.3V6M

+1.5VS_D

B B

FBA_CLK0

243_0402_1%

243_0402_1% R1139

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

A A

5

R1139 VGA@

VGA@

1 2

12

R1144

R1144 243_0402_1%

243_0402_1% VGA@

VGA@

4

10U_0603_6.3V6M

C1246

+1.5VS_D

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

VGA@

+1.5VS_D

1U_0402_6.3V4Z

1

2

1U_0402_6.3V4Z

VGA@

1

2

10U_0603_6.3V6M

VGA@

C1254

C1255

1

2

1U_0402_6.3V4Z

VGA@

C1265

C1266

1

2

1U_0402_6.3V4Z

VGA@

1

C1247

2

VGA@

1U_0402_6.3V4Z

C1256

1

2

VGA@

1U_0402_6.3V4Z

C1267

1

2

VGA@

10U_0603_6.3V6M

1

C1248

2

10U_0603_6.3V6M

VGA@

1U_0402_6.3V4Z

C1258

C1257

1

2

1U_0402_6.3V4Z

VGA@

1U_0402_6.3V4Z

C1269

C1268

1

2

1U_0402_6.3V4Z

VGA@

1

C1249

2

VGA@

1U_0402_6.3V4Z

C1259

C1260

1

2

1U_0402_6.3V4Z

VGA@

1U_0402_6.3V4Z

C1270

C1271

1

2

1U_0402_6.3V4Z

VGA@

10U_0603_6.3V6M

1

C1251

C1250

2

10U_0603_6.3V6M

VGA@

1U_0402_6.3V4Z

C1262

C1261

1

2

1U_0402_6.3V4Z

VGA@

C1272

1

2

VGA@

1U_0402_6.3V4Z

C1273

1

2

VGA@

3

VGA@

1U_0402_6.3V4Z

VGA@

1

2

VGA@

R1145

1.33K_0402_1%

1.33K_0402_1% VGA@

VGA@

+1.5VS_D

12

VREFD_Q3

VREFC_A3 VREFC_A4

1.33K_0402_1%

VREFC_A1 VREFD_Q2

1.33K_0402_1% VGA@

VGA@

10MIL 10MIL

12

R1147

1.33K_0402_1%

1.33K_0402_1% VGA@

C1263

1

2

+1.5VS_D

1

+

C1264

C1274

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C1264 220U_B_2.5VM_R35M

220U_B_2.5VM_R35M VGA@

VGA@

2

VGA@

2007/10/15 2008/10/15

0.1U_0402_10V6K

1

C1252

VGA@

2

Compal Secret Data

Deciphered Date

2

1.33K_0402_1%

1.33K_0402_1% VGA@

VGA@

R1146

R1148

+1.5VS_D

12

VREFD_Q4

VREFC_A2VREFD_Q1

0.1U_0402_10V6K

1

C1253

VGA@

2

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

C

Date: Sheet of

Compal Electronics, Inc.

VRAM DDRA

NIWBA_LA5371P

1

24 52Tuesday, March 24, 2009

0.1

5

4

3

2

1

N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001

F

BC_CMD[0..30]<20>

F

BC_DQM[0..7]<20>

F

BC_DQS[0..7]<20>

BC_DQS#[0..7]<20>

F

BC_D[0..63]<20>

F

D D

C C

BC_CMD[0..30]

F

BC_DQM[0..7]

F

BC_DQS[0..7]

F

BC_DQS#[0..7]

F

BC_D[0..63]

FBC_CLK0#<20> FBC_CLK1#<20>

R1149

R1149 240_0402_1%

240_0402_1%

VGA@

V

REFC_A5 REFD_Q5

V

F

BC_CMD19 BC_CMD25

F F

BC_CMD22 BC_CMD24

F F

BC_CMD0 BC_CMD2

F F

BC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26

FBC_CMD12 FBC_CMD3 FBC_CMD27

FBC_CLK0 FBC_CLK0# FBC_CMD18

FBC_CMD30 FBC_CMD29 FBC_CMD1 FBC_CMD10 FBC_CMD11

FBC_DQS0 FBC_DQS1

FBC_DQM0 FBC_DQM1

FBC_DQS#0 FBC_DQS#1

FBC_CMD15

12

U58

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

A

1

P4

A

2

N3

A

3

P9

4

A

P3

A

5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3

D

QL4

D

QL5

D

QL6 QL7

D

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BC_D5 BC_D3

F F

BC_D6

F

BC_D0 BC_D4

F F

BC_D1 BC_D7

F F

BC_D2

FBC_D13 FBC_D11 FBC_D14 FBC_D8 FBC_D12 FBC_D10 FBC_D15 FBC_D9

+1.5VS_D

R1150

R1150 240_0402_1%

240_0402_1%

VGA@

V

REFC_A6 REFD_Q6

V

F

BC_CMD19 BC_CMD25

F F

BC_CMD22 BC_CMD24

F F

BC_CMD0 BC_CMD2

F F

BC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26

FBC_CMD12 FBC_CMD3 FBC_CMD27

FBC_CLK0 FBC_CLK0# FBC_CMD18

FBC_CMD30 FBC_CMD29 FBC_CMD1 FBC_CMD10 FBC_CMD11

FBC_DQS2 FBC_DQS3

FBC_DQM2 FBC_DQM3

FBC_DQS#2 FBC_DQS#3

FBC_CMD15

12

U59

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

A

1

P4

A

2

N3

A

3

P9

4

A

P3

A

5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3

D

QL4

D

QL5

D

QL6 QL7

D

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BC_D21 BC_D23

F F

BC_D16

F

BC_D18 BC_D19

F F

BC_D22 BC_D17

F F

BC_D20

FBC_D31 FBC_D25 FBC_D29 FBC_D27 FBC_D28 FBC_D26 FBC_D30 FBC_D24

+1.5VS_D

FBC_CLK1<20>FBC_CLK0<20>

+1.5VS_D

R1151

R1151 240_0402_1%

240_0402_1%

VGA@

V

REFC_A7 REFD_Q7

V

F

BC_CMD19 BC_CMD25

F F

BC_CMD4 BC_CMD6

F F

BC_CMD5 BC_CMD13

F F

BC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26

FBC_CMD12 FBC_CMD3 FBC_CMD27

FBC_CMD7

FBC_CMD28 FBC_CMD8 FBC_CMD1 FBC_CMD10 FBC_CMD11

FBC_DQS4 FBC_DQS5

FBC_DQM4 FBC_DQM5

FBC_DQS#4 FBC_DQS#5

FBC_CMD15

12

U60

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

A

1

P4

A

2

N3

A

3

P9

4

A

P3

A

5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3

D

QL4

D

QL5

D

QL6 QL7

D

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BC_D37 BC_D33

F F

BC_D39

F

BC_D35 BC_D36

F F

BC_D32 BC_D38

F F

BC_D34

FBC_D41 FBC_D46 FBC_D40 FBC_D47 FBC_D44 FBC_D45 FBC_D42 FBC_D43

+1.5VS_D

R1152

R1152 240_0402_1%

240_0402_1%

VGA@

V

REFC_A8 REFD_Q8

V

F

BC_CMD19 BC_CMD25

F F

BC_CMD4 BC_CMD6

F F

BC_CMD5 BC_CMD13

F F

BC_CMD21 FBC_CMD16 FBC_CMD23 FBC_CMD20 FBC_CMD17 FBC_CMD9 FBC_CMD14 FBC_CMD26

FBC_CMD12 FBC_CMD3 FBC_CMD27

FBC_CLK1 FBC_CLK1# FBC_CMD7

FBC_CMD28 FBC_CMD8 FBC_CMD1 FBC_CMD10 FBC_CMD11

FBC_DQS6 FBC_DQS7

FBC_DQM6 FBC_DQM7

FBC_DQS#6 FBC_DQS#7

FBC_CMD15

12

U61

M9

V

REFCA

H2

V

REFDQ

N4

A

0

P8

A

1

P4

A

2

N3

A

3

P9

4

A

P3

A

5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/ODT0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

100-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646D-HCF8_FBGA100

@

D

QL0

D

QL1 QL2

D D

QL3

D

QL4

D

QL5

D

QL6 QL7

D

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E4 F8 F3 F9 H4 H9 G3 H8

D8 C4 C9 C3 A8 A3 B9 A4

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

F

BC_D52 BC_D51

F F

BC_D55

F

BC_D50 BC_D53

F F

BC_D49 BC_D54

F F

BC_D48

FBC_D63 FBC_D57 FBC_D61 FBC_D59 FBC_D60 FBC_D56 FBC_D62 FBC_D58

+1.5VS_D

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

C1277

VGA@

+1.5VS_D

1U_0402_6.3V4Z

C1283

1

2

1U_0402_6.3V4Z

VGA@

+1.5VS_D

1U_0402_6.3V4Z

1U_0402_6.3V4Z VGA@

VGA@

C1294

1

2

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

C1284

1U_0402_6.3V4Z

C1295

1U_0402_6.3V4Z

B B

FBC_CLK0

FBC_CLK0#

FBC_CLK1

FBC_CLK1#

A A

12

R1153

R1153 243_0402_1%

243_0402_1% VGA@

VGA@

12

R1154

R1154 243_0402_1%

243_0402_1% VGA@

VGA@

10U_0603_6.3V6M

1

C1278

C1279

2

VGA@

1U_0402_6.3V4Z

VGA@

C1286

C1285

1

2

1U_0402_6.3V4Z

VGA@

C1296

C1297

1

2

1U_0402_6.3V4Z

1

2

10U_0603_6.3V6M

VGA@

1U_0402_6.3V4Z

VGA@

C1287

1

2

1U_0402_6.3V4Z

VGA@

C1298

1

2

10U_0603_6.3V6M

1

C1281

C1280

2

VGA@

1U_0402_6.3V4Z

VGA@

C1288

C1289

1

2

1U_0402_6.3V4Z

VGA@

C1299

C1300

1

2

1U_0402_6.3V4Z

1

C1282

2

10U_0603_6.3V6M

VGA@

1U_0402_6.3V4Z

VGA@

C1291

C1290

1

2

1U_0402_6.3V4Z

VGA@

C1301

C1302

1

2

1

2

1.33K_0402_1%

C1292

C1303

+1.5VS_D

1

+

C1293

C1293 220U_B_2.5VM_R35M

220U_B_2.5VM_R35M VGA@

VGA@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

1.33K_0402_1%

Compal Secret Data

+1.5VS_D +1.5VS_D

12

R1155

VGA@

10MIL 10MIL

12

R1157

VGA@

Deciphered Date

1

C1275

2

VREFC_A6

VREFD_Q6

VREFC_A5

VREFD_Q5

0.1U_0402_10V6K

VGA@

1.33K_0402_1%

VREFC_A7

12

R1156

VGA@

12

R1158

VGA@

Title

Size Document Number Rev

Custom

Date: Sheet of

VREFD_Q7

VREFC_A8

VREFD_Q8

0.1U_0402_10V6K

1

C1276

VGA@

2

Compal Electronics, Inc.

VRAM DDRA

NIWBA_LA5371P

25 52Tuesday, March 24, 2009

0.1

5

4

3

2

1

5

GA_HDMI_CLK+<21>

V

GA_HDMI_CLK-<21>

V

GA_HDMI_TX0+<21>

V VGA_HDMI_TX0-<21>

D D

L15 MBK1608121YZF_0603DIS@L15 MBK1608121YZF_0603DIS@

VGA_HDMI_SDA<21>

VGA_HDMI_SCL<21>

C C

1 2 1 2

L16 MBK1608121YZF_0603DIS@L16 MBK1608121YZF_0603DIS@

12P_0402_50V8J

C469

DIS@

1

2

1 C470

C470

DIS@

DIS@ 2

12P_0402_50V8J

VGA_HDMI_TX1+<21> VGA_HDMI_TX1-<21> VGA_HDMI_TX2+<21> VGA_HDMI_TX2-<21>

VGA_HDMIDAT_SW VGA_HDMICLK_SW

4

H

C

462 0.1U_0402_16V7KDIS@

1 2

C

461 0.1U_0402_16V7KDIS@

1 2

C

464 0.1U_0402_16V7KDIS@

1 2

C

463 0.1U_0402_16V7KDIS@

1 2

C466 0.1U_0402_16V7KDIS@C466 0.1U_0402_16V7KDIS@

1 2

C465 0.1U_0402_16V7KDIS@C465 0.1U_0402_16V7KDIS@

1 2

C468 0.1U_0402_16V7KDIS@C468 0.1U_0402_16V7KDIS@

1 2

C467 0.1U_0402_16V7KDIS@C467 0.1U_0402_16V7KDIS@

1 2

HDMI_CLK+<27> HDMI_CLK-<27>

HDMI_TX0+<27>

HDMI_TX0-<27> HDMI_TX1+<27> HDMI_TX1-<27> HDMI_TX2+<27> HDMI_TX2-<27>

HDMIDAT_SW<27> HDMICLK_SW<27>

DMI_CLK+_SW

H

DMI_CLK-_SW

H

DMI_TX0+_SW

H

DMI_TX0-_SW HDMI_TX1+_SW HDMI_TX1-_SW HDMI_TX2+_SW HDMI_TX2-_SW

VGA_HDMIDAT_SW VGA_HDMICLK_SW

HDMI_CLK+ HDMI_CLKHDMI_TX0+ HDMI_TX0HDMI_TX1+ HDMI_TX1HDMI_TX2+ HDMI_TX2HDMIDAT_SW HDMICLK_SW

3

H

DMI switch1

HYBRID@

HYBRID@ U

U

68

V

CC CC

48

0

B1

47

1

B1

43

B1

2

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

TS3DV520ERHUR_QFN56_11X5~D

Thermal_GND

V V

CC

V

CC CC

V VCC VCC

SEL

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

2

+

3VS

H

DMI_CLK-_SW

H

4 10 18 27 38 50 56

HDMI_CLK+_CK

2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

3 7 8 11 12 14 15 19 20

DGPU_SELECT#

17

1 6 9 13 16 21 24 28 33 39 44 49 53 55

HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK HDMIDAT_R HDMICLK_R

HYBRID@

0.1U_0402_16V4Z

1

C

995

2

DGPU_SELECT# <16,28,29>

4.7U_0805_10V4Z

HYBRID@

C

1001

DMI_CLK+_SW

H

DMI_TX0-_SW

H

DMI_TX0+_SW

H

DMI_TX1-_SW

HDMI_TX1+_SW

HDMI_TX2-_SW HDMI_TX2+_SW

VGA_HDMIDAT_SW HDMIDAT_R VGA_HDMICLK_SW

HDMI_CLKHDMI_CLK+

HDMI_TX0HDMI_TX0+

HDMI_TX1HDMI_TX1+

HDMI_TX2HDMI_TX2+

HDMICLK_SW HDMIDAT_SW

DIS@

DIS@ DIS@

DIS@

DIS@ DIS@

DIS@

DIS@ DIS@

DIS@

DIS@ DIS@

DIS@

DIS@ DIS@

DIS@

UMA@

UMA@ UMA@

UMA@

UMA@ UMA@

UMA@

UMA@ UMA@

UMA@

UMA@ UMA@

UMA@

UMA@ UMA@

UMA@

1

6380_0402_5%

6380_0402_5% 6400_0402_5%

6400_0402_5%

6420_0402_5%

6420_0402_5% 6440_0402_5%

6440_0402_5%

6730_0402_5%

HDMI_CLK-_CK HDMI_CLK+_CK

HDMI_TX0-_CK HDMI_TX0+_CK

HDMI_TX1-_CK HDMI_TX1+_CK

HDMI_TX2-_CK HDMI_TX2+_CK

H

DMI_CLK-_CK

H

DMI_CLK+_CK

H

DMI_TX0-_CK

H

DMI_TX0+_CK

H

DMI_TX1-_CK

HDMI_TX1+_CK

HDMI_TX2-_CK HDMI_TX2+_CK

HDMICLK_R

HDMICLK_R HDMIDAT_R

R

12

R

12

R

12

R

12

R

12

R6740_0402_5%

12

R6480_0402_5%

12

R6540_0402_5%

12

R6610_0402_5%

12

R6460_0402_5%

12

R6710_0402_5%

12

R6500_0402_5%

12

R6580_0402_5%

12

R6520_0402_5%

12

R6620_0402_5%

12

R6560_0402_5%

12

R6600_0402_5%

12

R6720_0402_5%

12

R6760_0402_5%

12

R6750_0402_5%

12

TMDS pull down (500ohm) resistors G9x only

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

B B

A A

NEAR CONNECT

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

HDMI_TX2-_CK

HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK

1 2

R236 499_0402_1%DIS@R236 499_0402_1%DIS@

1 2

R237 499_0402_1%DIS@R237 499_0402_1%DIS@

1 2

R238 499_0402_1%DIS@R238 499_0402_1%DIS@

1 2

R239 499_0402_1%DIS@R239 499_0402_1%DIS@

1 2

R240 499_0402_1%DIS@R240 499_0402_1%DIS@

1 2

R241 499_0402_1%DIS@R241 499_0402_1%DIS@

1 2

R242 499_0402_1%DIS@R242 499_0402_1%DIS@

1 2

R243 499_0402_1%DIS@R243 499_0402_1%DIS@

L17

1

4

WCM-2012-900T_4P

L18

1

4

WCM-2012-900T_4P

L20

1

4

WCM-2012-900T_4P

L21

1

4

WCM-2012-900T_4P

R251 0_0402_5%@R251 0_0402_5%@ R252 0_0402_5%@R252 0_0402_5%@ R253 0_0402_5%@R253 0_0402_5%@ R254 0_0402_5%@R254 0_0402_5%@ R255 0_0402_5%@R255 0_0402_5%@ R256 0_0402_5%@R256 0_0402_5%@ R257 0_0402_5%@R257 0_0402_5%@ R258 0_0402_5%@R258 0_0402_5%@

5

2

3

2

3

2

3

2

3

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

HDMI_CLK+_CONN

2

HDMI_CLK-_CONN

3

HDMI_TX0+_CONN

2

HDMI_TX0-_CONN

3

HDMI_TX1+_CONN

2

HDMI_TX1-_CONN

3

HDMI_TX2+_CONN

2

HDMI_TX2-_CONN

3

13

D

2

G

DIS@

S

Q2

Q2 2N7002W-T/R7_SOT323-3

2N7002W-T/R7_SOT323-3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_DETECT_VGA<19> HDMI_DETECT<27>

+3VS

HDMI_DET_UMA

HDMI_DET_VGA

4

DGPU_SELECT<28,29>

@

@ D6

D6 RB751V_SOD323

RB751V_SOD323

2 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DGPU_SELECT

R266 0_0402_5%DIS@R266 0_0402_5%DIS@

1 2

R250

10K_0402_1%

1 2

R493

100K_0402_5%

DIS@

1 2

2

HYBRID@

61

Q77A

Q77A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

DIS@

1 2

L19MBK1608121YZF_0603 L19MBK1608121YZF_0603

2008/03/25 2008/04/

3

HDMI_DET_VGA HDMI_DET_UMA

DIS@

DIS@ C472

C472 330P_0402_50V7K

330P_0402_50V7K

+5VS

3

HDMIDAT_R

1

@

2

Compal Secret Data

@ D7

D7 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

Deciphered Date

+5VS

HDMI_DETECTHDMI_DETECT_VGA

+5VS

2

3

@

1

D5

D5 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMIDAT_R HDMICLK_R

3

HDMICLK_R

1

@

2

@ D8

D8 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

2

DGPU_SELECT#DGPU_SELECT#

5

HYBRID@

4

Q77B

Q77B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 UMA@

UMA@

R262 0_0402_5%

R244

@R244

R245

@

1 2

0_0805_5%

2.2K_0402_5%

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

Compal Electronics,Ltd.

Title

Level Shiftter_PS8101T

Size Document Number Rev

Custom

Date: Sheet of

3

12

+5VS

21

D4

D4 RB491D_SC59-3

RB491D_SC59-3

+5VS_HDMI

R246

2.2K_0402_5%

1 2

JHDMI

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

SUYIN_100042MR019S153ZL

KIWB1/B2_LA4601P

1

C471

1

0.1U_0402_16V4Z

2

DDC/CEC_GND

26 52Tuesday, March 24, 2009

CEC

Reserved

GND GND GND GND GND GND GND GND

13 14

2 5 8 11 20 21 22 23 17

0.1

5

D D

4

3

2

1

+3VS

P/N:SA00002D700 (8101T)

12

@

@ R223

R223 0_0402_5%

0_0402_5%

+3VS

12

R225

4.7K_0402_5%

4.7K_0402_5% UMA@

UMA@

12

C C

B B

@

@ R226

R226 0_0402_5%

0_0402_5%

12

@

@ R224

R224 0_0402_5%

0_0402_5%

+3VS

TMDS_B_CLK<15> TMDS_B_CLK#<15>

TMDS_B_DATA0<15> TMDS_B_DATA0#<15>

TMDS_B_DATA1<15> TMDS_B_DATA1#<15>

TMDS_B_DATA2<15> TMDS_B_DATA2#<15>

HDMI_DETECT<26>

R227 R229

HDMICLK_SW<26>

HDMIDAT_SW<26>

4.7K_0402_5%

1 2 1 2

4.7K_0402_5%

R612

4.7K_0402_5%

@R227

@ @R229

@

1 2

HDMICLK_SW

HDMIDAT_SW

HDMI_DETECT

R613

4.7K_0402_5%

4.7K_0402_5% @

@

1 2

P/N:SA00001U900 (CH7318A)

U17

25

OE#

28

29

30

32

34 35

SCL_SINK

SDA_SINK

HPD_SINK

DDC_EN

CFG0 CFG1

output

internal pull down

input

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

PS8101TQFN48G_QFN48_7X7UMA@

VCC VCC VCC VCC VCC VCC VCC VCC

PC1 PC0

REXT

HPD#

SDA

SCL

RT_EN#

OUT_D4+

OUT_D4-

OUT_D3+

OUT_D3-

OUT_D2+

OUT_D2-

OUT_D1+

OUT_D1-

GND GND GND GND GND GND GND GND GND GND

PAD

2 11 15 21 26 33 40 46

R228 4.7K_0402_5%UMA@R228 4.7K_0402_5%UMA@

4

R230 4.7K_0402_5%@R230 4.7K_0402_5%@

3

internal pull down

6

TMDS_B_HPD#

7

8

9

10

13 14

16 17

19 20

22 23

1 5 12 18 24 27 31 36 37 43 49

FOR 7318C PIN6 PULL DOWN 1.2Kohm

PIN7 PULL DOWN 7.5Kohm

PIN7 PULL UP 20Kohm

+3VS

1

UMA@

UMA@ C457

C457

0.1U_0402_16V4Z

2

1 2 1 2

R231 499_0402_1%UMA@R231 499_0402_1%UMA@

1 2

TMDS_B_HPD# <15>

1

UMA@

UMA@ C458

C458

0.1U_0402_16V4Z

2

1

UMA@

UMA@ C459

C459

0.1U_0402_16V4Z

2

+3VS

HDMIDAT_NB <15>

HDMICLK_NB <15>

1

UMA@

UMA@ C460

C460 10U_0805_10V4Z

10U_0805_10V4Z

2

TMDS_B_HPD#

pull up by PCH side

HDMI_CLK+ HDMI_CLK-

HDMI_TX0+ HDMI_TX0-

HDMI_TX1+ HDMI_TX1-

HDMI_TX2+ HDMI_TX2-

HDMI_CLK+ <26> HDMI_CLK- <26>

HDMI_TX0+ <26> HDMI_TX0- <26>

HDMI_TX1+ <26> HDMI_TX1- <26>

HDMI_TX2+ <26> HDMI_TX2- <26>

+3VS

12

R615

R615 20K_0402_1%

20K_0402_1% @

@

R614

7.5K_0402_1%

7.5K_0402_1% @

@

A A

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Level Shiftter_PS8101T

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

KIWB1/B2_LA4601P

1

27 52Tuesday, March 24, 2009

0.1

A

B

+

5VS

C

+

5VS

+

5VS

D

+

5VS

+

5VS

E

D

AC_RED

AC_GRN

D

AC_BLU

VGA_CRT_R

1 1

VGA_CRT_G

2 2

3 3

CRT_DDC_DATA<15>

CRT_DDC_CLK<15>

4 4

VGA_DDCDATA<19>

VGA_DDCCLK<19>

1 2

R

669 0_0402_5%UMA@

1 2

R

670 0_0402_5%UMA@

1 2

R

668 0_0402_5%UMA@

1 2

R1337 0_0402_5%DIS@R1337 0_0402_5%DIS@

1 2

R1338 0_0402_5%DIS@R1338 0_0402_5%DIS@

1 2

R1339 0_0402_5%DIS@R1339 0_0402_5%DIS@

VGA_CRT_R<19> VGA_CRT_G<19> VGA_CRT_B<19>

VGA_HSYNC<19>

DAC_RED<15>

DAC_GRN<15>

DAC_BLU<15>

CRT_HSYNC<15>

DAC_RED DAC_GRN DAC_BLU CRT_HSYNC

CRT_DDC_DATA CRT_DDC_DAT_CONN

CRT_DDC_CLK CRT_DDC_CLK_CONN

2.2K_0402_5%

VGA_DDCDATA

VGA_DDCCLK

A

C

RT_R

RT_G

C

RT_B

CRT_R

CRT_G

CRT_BVGA_CRT_B

+5VS

FSAV330MTC_TSSOP16

UMA@

R1183

2.2K_0402_5%

R1163

DIS@

16

2

5 11 14

3

6 10 13

12

U

DIS only

VCC

1B1 2B1 3B1 4B1

1B2 2B2 3B2 4B2

HYBRID@

+3VS

12

+3VS

12

R1164

2.2K_0402_5%

2.2K_0402_5% DIS@

DIS@

MA only

U47

1

SEL

15

OE#

4

1A

7

2A

9

3A

12

4A

8

GND

12

UMA@

UMA@ R1185

R1185

2.2K_0402_5%

R1343

0_0402_5%

DIS@

DGPU_SELECT#

CRT_R CRT_G CRT_B HSYNC_G_A

+3VS

R1342

0_0402_5%

UMA@

Q71A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+3VS

Q64A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

DGPU_SELECT

1 2

5

4

Q64B

2

2N7002DW-T/R7_SOT363-6

61

DIS@Q64A

DIS@

DGPU_SELECT#

1 2

5

4

Q71B

2

2N7002DW-T/R7_SOT363-6

UMA@Q71A

UMA@

R1341

R1341 0_0402_5%

0_0402_5% HYBRID@

HYBRID@

2.2K_0402_5%

3

DIS@Q64B

DIS@

100P_0402_50V8J

2N7002_SOT23

R1340

R1340 0_0402_5%

0_0402_5% HYBRID@

HYBRID@

3

UMA@Q71B

UMA@

61

+CRT_VCC

DIS@

R1165

DGPU_SELECT# <16,26,29>

L: B1 -> A(VGA) H: B2 -> A(PCH)

+3VS

R1322

R1322 10K_0402_5%

10K_0402_5%

DGPU_SELECT

1 2

13

D

HYBRID@

S

HYBRID@

2

Q25

G

L: B1 -> A(VGA) H: B2 -> A(PCH)

DGPU_SELECT <26,29>

2.2K

12

DIS@

R1166

2.2K_0402_5%

CRT_DDC_DAT_CONN

CRT_DDC_CLK_CONN

1

@

2

@ C1316

C1316 68P_0402_50V8K

68P_0402_50V8K

2

C1315

B

@

CRT_R

CRT_G

CRT_B

CRT_HSYNC<15>

VGA_HSYNC<19>

3

2

12

R1159

R1159 150_0402_1%

150_0402_1%

CLOSE TO CONN

DGPU_SELECT <26,29>

@

@ D

D BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

12

R1160

R1160 150_0402_1%

150_0402_1%

R1373 0_0402_5%UMA@ R1373 0_0402_5%UMA@

R1374 0_0402_5%DIS@ R1374 0_0402_5%DIS@

LUE

CRT_VSYNC<15>

B

12

1 2

1

39

1 2

R1377 0_0402_5%

VGA_VSYNC<19>

R1161

R1161 150_0402_1%

150_0402_1%

UMA@

3

REEN

G

1

2

0.1U_0402_16V4Z

HSYNC_G CRT_HSYNC_1

HSYNC_GHSYNC_G_A

0.1U_0402_16V4Z

R1376 0_0402_5%UMA@ R1376 0_0402_5%UMA@

@

@ D

D

40

BAT54S-7-F_SOT23-3

1

C1304

2

10P_0402_50V8J

C1311

C1333

1 2

R1375 0_0402_5%DIS@ R1375 0_0402_5%DIS@

1 2

1

C1305

2

10P_0402_50V8J

+CRT_VCC

1

2

5

P

2

A

G

3

+CRT_VCC

1

2

5

P

2

A

G

3

+CRT_VCC

3

1

BAT54S-7-F_SOT23-3

2

MBK1608121YZF_0603

1 2

L517

MBK1608121YZF_0603

1 2

L518

MBK1608121YZF_0603

1 2

L519

1

C1306

C1306 10P_0402_50V8J

10P_0402_50V8J

2

R276

1 2

1K_0402_5%

1

4

OE#

Y

U62

U62 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

R275

1 2

1K_0402_5%

1

4

OE#

Y

U69

U69 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

BAT54S-7-F_SOT23-3

@

@ D

D

41

1

2

10P_0402_50V8J

C1307

L: B1 -> A(VGA) H: B2 -> A(PCH)

CRT_VSYNC_1

Place closed to chipset

HYBRID@

C1314

0.1U_0402_16V4Z

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

C

C1314

1

2

5

1

P

2

A

G

3

Compal Secret Data

Deciphered Date

4

OE#

Y

U63

U63 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5 HYBRID@

HYBRID@

L: B1 -> A(VGA) H: B2 -> A(PCH)

ED

R

1

C1308

2

10P_0402_50V8J

CRT_VSYNC_1

SN74AHCT1G125DCKR_SC70-5

D

3

2

@

@ D

D BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

RED

GREEN

BLUE

1

C1309

C1309 10P_0402_50V8J

10P_0402_50V8J

2

3

VGA_HS

1

43

J

+5VS

D42

2 1

RB491D_SC59-3

2

@

@ D

D

44

BAT54S-7-F_SOT23-3

+CRT_VCC

1.1A_6V_SMD1812P110TF

W=40mils

RED

GREEN

BLUE

JVGA_VS

JVGA_HS CRT_DDC_DAT_CONN CRT_DDC_CLK_CONN

1 2

L520 MBK1608121YZF_0603L520 MBK1608121YZF_0603

1 2

L521 MBK1608121YZF_0603L521 MBK1608121YZF_0603

+CRT_VCC

DGPU_SELECTDGPU_SELECT#

1

4

OE#

Y

U65

HYBRID@

Title

Size Document Number Rev

Custom

Date: Sheet of

1

HYBRID@

C1342

0.1U_0402_16V4Z

2

5

P

2

A

G

3

Compal Electronics, Inc.

CRT & TV-OUT Connector

NIWBA_LA5371P

VGA_VS

J

1

CRT Connector

F1

21

1

@

@ C1312

C1312 10P_0402_50V8J

10P_0402_50V8J

2

1

@ C1313

@ 10P_0402_50V8J

10P_0402_50V8J

2

VGA_VSYNC <19>CRT_VSYNC<15>

JVGA_VS

C1313

E

1 2 3 4 5 6 7 8

9 10 11 12

13 14

1

C1310

0.1U_0402_16V4Z

2

JCRT1

1 2 3 4 5 6 7 8 9 10 11 12

GND1 GND2

ACES_87213-1200G

ACES_87213-1200G ME@

ME@

JVGA_HS

28 52Tuesday, March 24, 2009

0.1

5

LCD POWER CIRCUIT

+

LCDVDD

R

1167

150_0603_1%

D D

13

D

G

S

G

R1170

Q65

2N7002_SOT23

LCD_ENVDD

100K_0402_5%

2

DTC124EK

2

12

@R1170

@

+

5VALW

12

R

R 100K_0402_5%

100K_0402_5%

1

OUT

IN

GND

DTC124EKAT146_SC59-3

3

1168

R1169 220K_0402_5%R1169 220K_04 02_5%

1 2

Q67

1

C1318

0.1U_0402_16V4Z

2

Q66

4

+

3VS

S

G

SI2301BDS-T1-E3_SOT23-3

D

1 3

+LCDVDD

W

=60mils

1

C1317

4.7U_0805_10V4Z

2

MBK1608121YZF_0603

1 2

+LCDVDD_CONN

L522

4.7U_0805_10V4Z

W=60mils

C1322

1

2

470P_0402_50V7K

1

C1323

0.1U_0402_16V4Z

2

3

NVT_PWM

I

D

AC_BRIG

D

ISPOFF#

C

1319

@

1

2

@

1

C

1320

2

470P_0402_50V7K

For EMI

@

1

C

1321

2

470P_0402_50V7K

+LCDVDD_CONN

+3VS

@

680P_0402_50V7K

@

C1326

CONN_LVDS_SCL CONN_LVDS_SDA

(60 MIL)

LCD_COLOR<37>

1

INVT_PWM<37>

DAC_BRIG<37>

2

+3VS

R1172

2.2K_0402_5%

2

V

GA LCD/PANEL BD. Conn.

JL

VDS1

R1173

2.2K_0402_5%

DISPOFF#

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

GND41GND

ACES_87142-4041

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

LEDVDD

+

680P_0402_50V7K

LEDVDD

+

CONN_LVDS_B2# CONN_LVDS_B2 CONN_LVDS_BCLK# CONN_LVDS_BCLK CONN_LVDS_B1# CONN_LVDS_B1 CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_B0 CONN_LVDS_B0# CONN_LVDS_A1 CONN_LVDS_A1# CONN_LVDS_A2# CONN_LVDS_A2 CONN_LVDS_ACLK# CONN_LVDS_ACLK

C

1324

@

+LCDVDD_CONN

+3VS

1

+

B

1 2

L

523

MBK1608121YZF_0603

1

2

MBK1608121YZF_0603

1

C

1325

4.7U_0805_25V6-K

2

LVDS switch1

HYBRID@

HYBRID@ U67

U67

C C

B B

A A

VGA_LVDS_A0#<21>

VGA_LVDS_A0<21>

VGA_LVDS_ACLK<21>

VGA_LVDS_ACLK#<21>

VGA_LVDS_A2<21> VGA_LVDS_A2#<21> VGA_LVDS_A1#<21>

VGA_LVDS_A1<21>

VGA_LVDS_SCL<19> VGA_LVDS_SDA<19>

LVDS_A0#<15>

LVDS_A0<15>

LVDS_ACLK<15>

LVDS_ACLK#<15>

LVDS_A2<15> LVDS_A2#<15> LVDS_A1#<15>

LVDS_A1<15>

EDID_CLK<15> EDID_DATA<15>

VGA_LVDS_B0#<21>

VGA_LVDS_B0<21>

VGA_LVDS_B1<21>

VGA_LVDS_B1#<21>

VGA_LVDS_BCLK<21>

VGA_LVDS_BCLK#<21>

VGA_LVDS_B2<21>

VGA_LVDS_B2#<21>

LVDS_B0#<15>

LVDS_B0<15>

LVDS_B1<15> LVDS_B1#<15>

LVDS_BCLK<15>

LVDS_BCLK#<15>

LVDS_B2<15> LVDS_B2#<15>

VGA_LVDS_A0# VGA_LVDS_A0 VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A2 VGA_LVDS_A2# VGA_LVDS_A1# VGA_LVDS_A1 VGA_LVDS_SCL VGA_LVDS_SDA

LVDS_A0# LVDS_A0 LVDS_ACLK LVDS_ACLK# LVDS_A2 LVDS_A2# LVDS_A1# LVDS_A1 EDID_CLK EDID_DATA

TS3DV520ERHUR_QFN56_11X5~D

VGA_LVDS_B0# VGA_LVDS_B0 VGA_LVDS_B1 VGA_LVDS_B1# VGA_LVDS_BCLK VGA_LVDS_BCLK# VGA_LVDS_B2 VGA_LVDS_B2#

LVDS_B0# LVDS_B0 LVDS_B1 LVDS_B1# LVDS_BCLK LVDS_BCLK# LVDS_B2 LVDS_B2#

TS3DV520ERHUR_QFN56_11X5~D

5

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

Thermal_GND

LVDS switch2

HYBRID@

HYBRID@ U66

U66

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

Thermal_GND

VCC VCC VCC VCC VCC VCC VCC

SEL

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VCC VCC VCC VCC VCC VCC VCC

SEL

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

4 10 18 27 38 50 56

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

A8

20

A9

17

1 6 9 13 16 21 24 28 33 39 44 49 53 55

4 10 18 27 38 50 56

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

A8

20

A9

17

1 6 9 13 16 21 24 28 33 39 44 49 53 55

+3VS

HYBRID@

0.1U_0402_16V4Z

CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_ACLK CONN_LVDS_ACLK# CONN_LVDS_A2 CONN_LVDS_A2# CONN_LVDS_A1# CONN_LVDS_A1 CONN_LVDS_SCL CONN_LVDS_SDA

DGPU_SELECT#

L: B1 -> A(VGA) H: B2 -> A(PCH)

+3VS

HYBRID@

0.1U_0402_16V4Z

CONN_LVDS_B0# CONN_LVDS_B0 CONN_LVDS_B1 CONN_LVDS_B1# CONN_LVDS_BCLK CONN_LVDS_BCLK# CONN_LVDS_B2 CONN_LVDS_B2#

DGPU_SELECT#

L: B1 -> A(VGA) H: B2 -> A(PCH)

1

C853

C855

4.7U_0805_10V4Z

2

DGPU_SELECT# <16,26,28>

1

4.7U_0805_10V4Z

2

4

HYBRID@

C854

HYBRID@

C856

VGA_LVDS_SCL VGA_LVDS_SDA

VGA_LVDS_A0 VGA_LVDS_A0#

VGA_LVDS_A1 VGA_LVDS_A1#

VGA_LVDS_A2 VGA_LVDS_A2#

VGA_LVDS_ACLK VGA_LVDS_ACLK#

VGA_LVDS_B0 VGA_LVDS_B0#

VGA_LVDS_B1 VGA_LVDS_B1#

VGA_LVDS_B2 VGA_LVDS_B2#

VGA_LVDS_BCLK VGA_LVDS_BCLK#

EDID_DATA

LVDS_A0 LVDS_A0#

LVDS_A1 LVDS_A1#

LVDS_A2 LVDS_A2#

LVDS_ACLK LVDS_ACLK#

LVDS_B0 LVDS_B0#

LVDS_B1 LVDS_B1#

LVDS_B2 LVDS_B2#

LVDS_BCLK LVDS_BCLK#

CONN_LVDS_SCL

R13600_0402_5% DIS@ R13600_0402_5% DIS@

12

CONN_LVDS_SDA

R13610_0402_5% DIS@ R13610_0402_5% DIS@

12

CONN_LVDS_A0

R13440_0402_5% DIS@ R13440_0402_5% DIS@

12

CONN_LVDS_A0#

R13450_0402_5% DIS@ R13450_0402_5% DIS@

12

R13580_0402_5% DIS@ R13580_0402_5% DIS@

12

R13590_0402_5% DIS@ R13590_0402_5% DIS@

12

R13460_0402_5% DIS@ R13460_0402_5% DIS@

12

R13480_0402_5% DIS@ R13480_0402_5% DIS@

12

R13550_0402_5% DIS@ R13550_0402_5% DIS@

12

R13470_0402_5% DIS@ R13470_0402_5% DIS@

12

R13560_0402_5% DIS@ R13560_0402_5% DIS@

12

R13490_0402_5% DIS@ R13490_0402_5% DIS@

12

R13500_0402_5% DIS@ R13500_0402_5% DIS@

12

R13510_0402_5% DIS@ R13510_0402_5% DIS@

12

R13520_0402_5% DIS@ R13520_0402_5% DIS@

12

R13530_0402_5% DIS@ R13530_0402_5% DIS@

12

R13540_0402_5% DIS@ R13540_0402_5% DIS@

12

R13570_0402_5% DIS@ R13570_0402_5% DIS@

12

CONN_LVDS_A1 CONN_LVDS_A1#

CONN_LVDS_A2 CONN_LVDS_A2#

CONN_LVDS_ACLK CONN_LVDS_ACLK#

CONN_LVDS_B0 CONN_LVDS_B0#

CONN_LVDS_B1 CONN_LVDS_B1#

CONN_LVDS_B2 CONN_LVDS_B2#

CONN_LVDS_BCLK CONN_LVDS_BCLK#

VGA_ENVDD_R<19>

VGA_ENBKL_R<19>

BKOFF#<37>

L: B1 -> A(VGA) H: B2 -> A(PCH)

CONN_LVDS_SCLEDID_CLK

R6300_0402_5% UMA@ R6300_0402_5% UMA@

12

CONN_LVDS_SDA

R6360_0402_5% UMA@ R6360_0402_5% UMA@

12

CONN_LVDS_A0

R6290_0402_5% UMA@ R6290_0402_5% UMA@

12

CONN_LVDS_A0#

R6330_0402_5% UMA@ R6330_0402_5% UMA@

12

CONN_LVDS_A1

R6340_0402_5% UMA@ R6340_0402_5% UMA@

12

CONN_LVDS_A1#

R6350_0402_5% UMA@ R6350_0402_5% UMA@

12

CONN_LVDS_A2

R6370_0402_5% UMA@ R6370_0402_5% UMA@

12

CONN_LVDS_A2#

R6390_0402_5% UMA@ R6390_0402_5% UMA@

12

CONN_LVDS_ACLK

R6410_0402_5% UMA@ R6410_0402_5% UMA@

12

CONN_LVDS_ACLK#

R6430_0402_5% UMA@ R6430_0402_5% UMA@

12

CONN_LVDS_B0

R6450_0402_5% UMA@ R6450_0402_5% UMA@

12

CONN_LVDS_B0#

R6470_0402_5% UMA@ R6470_0402_5% UMA@

12

CONN_LVDS_B1

R6490_0402_5% UMA@ R6490_0402_5% UMA@

12

CONN_LVDS_B1#

R6510_0402_5% UMA@ R6510_0402_5% UMA@

12

CONN_LVDS_B2

R6530_0402_5% UMA@ R6530_0402_5% UMA@

12

CONN_LVDS_B2#

R6550_0402_5% UMA@ R6550_0402_5% UMA@

12

CONN_LVDS_BCLK

R6570_0402_5% UMA@ R6570_0402_5% UMA@

12

CONN_LVDS_BCLK#

R6590_0402_5% UMA@ R6590_0402_5% UMA@

12

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

3

2007/10/15 2008/10/15

Compal Secret Data

PCH_ENBKL_R<15>

PCH_ENVDD_R<15>

Deciphered Date

2

+3VS

12

R1171

4.7K_0402_5%

D45

BKOFF# DISPOFF#

R265 0_0402_5%DIS@R265 0_0402_5%DIS@

R261 0_0402_5%

R263 0_0402_5%

R260 0_0402_5%

D45

CH751H-40PT_SOD323-2

1 2

5

4

Q73B

Q73B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

DIS@

UMA@

1 2

5

4

Q75B

Q75B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

UMA@

4.7K_0402_5%

21

DGPU_SELECT

2

HYBRID@

61

Q73A

Q73A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3

HYBRID@

12

ENBKL<37>

DGPU_SELECT#

2

HYBRID@

61

Q75A

Q75A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

3

HYBRID@

12

Title

Size Document Number Rev

B

Date: Sheet of

DGPU_SELECT <26,28>

L: B1 -> A(PCH) H: B2 -> A(VGA)

ENBKL

R1174

100K_0402_1%

1 2

Compal Electronics, Inc.

LVDS & DVI Connector

LCD_ENVDD

NIWBA_LA5371P

29 52Tuesday, March 24, 2009

1

29 52Tuesday, March 24, 2009

0.1

A

ini-Express Card for 3G Or TV Tuner

M

ini-Express Card for WLAN

M

ini-Express Card(Slot 1-TV TUNNER) 4.0mm high

J

P5

1

3

5

P

CIECLKREQ4#<14>

CLK_PCIE_WLAN#<14>

1 1

EC_TX_P80_DATA<37,38> EC_RX_P80_CLK<37,38>

2 2

CLK_PCIE_WLAN<14>

PCIE_PTX_C_DRX_N6<14> PCIE_PTX_C_DRX_P6<14>

PCIE_PRX_DTX_N6<14> PCIE_PRX_DTX_P6<14> PCIE_PTX_C_DRX_N4<14>

EC_TX_P80_DATA EC_RX_P80_CLK

CIECLKREQ4#

+3VS_TV

TV@

100_0402_1%

100_0402_1% R757

R757 1 2 1 2

R756

100_0402_1%

TV@

TV_POWER_SW<37>

33K_0402_5%

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

FOX_AS0B226-S40N-7F

ME@

+5VS

12

R820

0.1U_0402_16V4Z

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

GND2

AO3414_SOT23-3

Q10

TVSW@

2

G

1

C36

2

TVSW@

13

D

S

4.7U_0805_10V4Z

3VS_TV

+

1.5VS_TV

TV_RST#

+3VS +1.5VS

AO3414_SOT23-3

TVSW@

R801

R801 0_0805_5%

0_0805_5% NO_TVSW@

NO_TVSW@

1 2

Mini-Express Card(Slot 2-WIRELESS) 5.6mm high

JP7

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N 0

TAITW_PFPET0-AFGLBG1ZZ4N 0 ME@

ME@

U22

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

G577BSR91U_QFN20

3.3V

GND

1.5V

GND

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN# LED_WPAN#

+1.5V

GND

+3.3V

GND

1.5Vout

3.3Vout

PERST#

NC NC NC NC NC

NC

OC#

NC

GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

CLK_PCIE_WLAN1#<14>

CLK_PCIE_WLAN1<14>

PCIE_PTX_C_DRX_N2<14> PCIE_PTX_C_DRX_P2<14 >

PCIE_PRX_DTX_N2<14> PCIE_PRX_DTX_P2<14>

PCIE_WAKE# BT_ACTIVE WLAN_ACTIVE WLAN_CLKREQ1#

EC_TX_P80_DATA EC_RX_P80_CLK

R428 0_0402_5%@R428 0_0402_5 %@

1 2

R429 0_0402_5%@R429 0_0402_5%@

1 2

+3VS

100_0402_1%

R436

@

R755

@

@R755

@

1 2 1 2

100_0402_1%

PCIE_WAKE#<15,31>

BT_ACTIVE<40> WLAN_ACTIVE<40>

WLAN_CLKREQ1#<14>

3 3

EC_TX_P80_DATA<37,38> EC_RX_P80_CLK<37,38>

2005/09/27 modified. Base on OPTION GTM351E Datasheet Rev0.1 Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA

+1.5VS

Express Card Power Switch

1

C1330

0.1U_0402_16V4Z

2

+3VS

4 4

1

C1331

0.1U_0402_16V4Z

2

+3VALW

1

C1332

0.1U_0402_16V4Z

2

+3VALW

BUF_PLT_RST#<5,16,19,31>

R438 100K_0402_5%@R 438 100K_0402_5%@

A

SYSON<37,42,47>

SUSP#<16,37,42,47,49>

1 2

CPUSB#<16>

+1.5VS

+3VS

+3VALW

PLT_RST#

SYSON

SUSP#

CPUSB#

C

559

TV@

USB20_N9 <16> USB20_P9 <16>

Q11

13

2

G

TV SW

+1.5VS_CARD1

11 13

+3VS_CARD1

3 5

+3VALW_CARD1

15

19

PERST#

8

16

7

B

+

1.5VS_TV

3VS_TV

1

2

1

2

NC7SZ08P5X_NL_SC70-5

R802

R802 0_0402_5%

0_0402_5% NO_TVSW@

NO_TVSW@

1 2

+1.5VS_TV+3VS_TV

+1.5VS

2Watt

R430 0_0402_5%@R430 0_0402_5 %@

1 2

R431 0_0402_5%R431 0_0402_5%

1 2

R432 0_0402_5%@R432 0_0402_5 %@

1 2

R433 0_0402_5%R433 0_0402_5%

1 2

R434 0_0402_5%@R434 0_040 2_5%@

1 2

R435 0_0402_5%@R435 0_0402_5 %@

1 2

D

S

+

+3VS

40mil

60mil

40mil

B

C

557

4.7U_0805_10V4Z

4.7U_0805_10V4Z TV@

TV@

+

3VS

5

U15

4

Y

3

NO_TVSW@

1 2

+3VALW

1

C1329

0.1U_0402_16V4Z

2

USB20_N8 <16> USB20_P8 <16>

R761300_0 402_5% @ R761300_0402_5% @

12

WLAN_LED#

R760300_0 402_5% R760300_0402_5%

12

+1.5VS_CARD1

+3VS_CARD1

+3VALW_CARD1

2

P

B

1

A

G

TVSW@

1

C565

C565 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C568

C568 10U_0805_10V4Z

10U_0805_10V4Z

2

1

@

@ C571

C571 10U_0805_10V4Z

10U_0805_10V4Z

2

R

821

1 2

33K_0402_5%

1

T

VSW@

C37

0.1U_0402_16V4Z

2

TVSW@

BUF_PLT_RST# <5,16,19,31 >

R8220_0402_5%

TV SW

3G_OFF# <37> WL_OFF# <37>

BUF_PLT_RST# <5 ,16,19,31> +3VALW +3VS

SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 < 10,11,12,14>

WLAN_LED# <41>

Imax = 0.75A

1

C566

0.1U_0402_16V4Z

2

Imax = 1.35A

1

C569

0.1U_0402_16V4Z

2

Imax = 0.275A

1

C572

0.1U_0402_16V4Z

2

+

3VS_TV

C

D

Mini-Express Card(Slot 3-WWAN 3G) 5.6mm high

J

P6

4

5

6

VCC

RST CLK

GND GND

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

1 3 5 7 9

1 2 3

8 9

P6

WAKE# NC NC CLKREQ# GND REFCLKREFCLK+ GND NC NC GND PERn0 PERp0 GND GND PETn0 PETp0 GND NC NC NC NC NC NC NC NC

GND

TAITW_PFPET0-AFGLBG1ZZ4N 0ME@

LED_WWAN#

LED_WLAN#

LED_WPAN#

PCIE_WAKE#<15,31>

BT_ACTIVE<40> WLAN_ACTIVE<40>

PCIECLKREQ3#<14>

CLK_PCIE_CARD_PCH#<14 >

CLK_PCIE_CARD_PCH<14>

Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA

EC_TX_P80_DATA<37,38> EC_RX_P80_CLK<37,38>

EC_TX_P80_DATA EC_RX_P80_CLK

UIM_VPP UIM_DATA

+UIM_PWR

PCIE_WAKE# BT_ACTIVE WLAN_ACTIVE PCIECLKREQ3#

PCIE_PTX_C_DRX_P4<14 >

PCIE_PRX_DTX_N4<14> PCIE_PRX_DTX_P4<14>

R758

R759

12

R437

10K_0402_5%

R1175 0_0402_5%@R1175 0_0402_5%@

R414 0_0402_5%@R414 0_040 2_5%@

1 2

R419 0_0402_5%@R419 0_0402_5%@

1 2

+3VS

100_0402_1%

100_0402_1% 1 2 1 2

100_0402_1%

D21

@D21

@

CM1293-04SO_SOT23-6

1

CH1

2

Vn

3

CH2

JP8

4

GND

5

VPP

6

I/O

7

DET

TAITW_PMPAT6-06GLBS7N14N 0 ME@

CH4

Vp

CH3

New Card 34mm Socket (Left/TOP)

USB20_N10<16>

USB20_P10<16>

CPUSB#<16>

SMB_CLK_S3<10,11,12,14> SMB_DATA_S3<10,11,12,14>

+1.5VS_CARD1

PCIE_WAKE#<15,31>

+3VALW_CARD1

+3VS_CARD1

CLKREQ_EXP#<14>

CLK_PCIE_EXP_PCH#<14> CLK_PCIE_EXP_PCH<14>

PCIE_PRX_DTX_N1<14> PCIE_PRX_DTX_P1<14>

PCIE_PTX_C_DRX_N1<14> PCIE_PTX_C_DRX_P1<14 >

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/10/15 2008/10/15

Compal Secret Data

USB20_N10 USB20_P10

CPUSB#

PERST#

CPUSB#

Deciphered Date

D

3.3V

GND

1.5V

GND

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

+1.5V

GND

+3.3V

GND

+3VS

+UIM_PWR UIM_RST UIM_CLK

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27 28

2 4 6 8

NC

10

NC

12

NC

14

NC

16

NC

18 20

NC

22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

10K_0402_5%

40mil

1

C563

2

JEXP1

GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND

GND GND

SANTA_130832-1_RV

+

3VS

+1.5VS

+UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP

R420 0_0402_5%3G@R420 0_040 2_5%3G@ R422 0_0402_5%@R422 0_0402_5%@

R424 0_0402_5%@R42 4 0_0402_5%@ R425 0_0402_5%@R425 0_04 02_5%@

R426 0_0402_5%@R426 0_04 02_5%@ R427 0_0402_5%@R427 0_0402_ 5%@

USB20_N13 USB20_P13

@

+UIM_PWRUIM_DATA

12

R824

DAN217T146_SC59- 3

1

C564

0.1U_0402_16V4Z

2

4.7U_0805_10V4Z

E

+

3VS

1

3G@

3G@ C

C

562

10U_0805_10V4Z

2

2Watt

1 2 1 2

USB20_N13 <16> USB20_P13 <16>

3G_LED#

+3VS

3

2

D22

@ D22

@

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

Mini-Card/3G/FeliCa/BT

1

3G@

3G@ C

C

558

10U_0805_10V4Z

2

3G_OFF# <37> WL_OFF# <37>

BUF_PLT_RST# < 5,16,19,31> +3VALW +3VS

SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 < 10,11,12,14>

3G_LED# <41>

+1.5VS

1

3G@

3G@ C1327

C1327

0.1U_0402_16V4Z

2

NIWBA_LA5371P

E

1

3G@

3G@ C1328

C1328

0.1U_0402_16V4Z

2

30 52Tuesday, March 24, 2009

0.1

5

D D

+1.2V_LAN

1 2

L36 MBK16081 21YZF_0603L36 MBK1608121YZF_0603

1 2

L34 MBK16081 21YZF_0603L34 MBK1608121YZF_0603

1 2

L35 MBK16081 21YZF_0603L35 MBK1608121YZF_0603

C C

R477 20 0_0402_1%R477 200_0 402_1%

1 2

Y4

1 2

B B

1

25MHZ_20P

C604

C604 27P_0402_50V8J

27P_0402_50V8J

2

1

C592

4.7U_0805_10V4Z

2

1

C594

4.7U_0805_10V4Z

2

1

C598

4.7U_0805_10V4Z

2

PCIE_PRX_DTX_N3<14>

PCIE_PRX_DTX_P3<14> PCIE_PTX_C_DRX_N3<14> PCIE_PTX_C_DRX_P3<14 >

PCIE_WAKE#<15,30> LAN_WAKE#<37>

CLK_PCIE_LAN<14>

CLK_PCIE_LAN#<14>

BUF_PLT_RST#<5,16,19,30>

1

C605

C605 27P_0402_50V8J

27P_0402_50V8J

2

+3V_LAN

+3VS

1

C593

0.1U_0402_16V4Z

2

1

C595

0.1U_0402_16V4Z

2

1

C599

0.1U_0402_16V4Z

2

C596 0.1U_0 402_16V7KC596 0.1U_0402_16V7K C597 0.1U_0 402_16V7KC597 0.1U_0402_16V7K

R462 0_0402_5%@R462 0_040 2_5%@

1 2

R468 1K_0402 _5%R468 1K_0402_5%

1 2

R469 0_0402_5%@R469 0_040 2_5%@

1 2

CLKREQ_LAN#<14 >

R552 10K_040 2_5%R552 10K_04 02_5%

4

+1.2V_LAN

12

R474

1.24K_0402_1%

1 2

+3V_LAN

PCIE_IRX_C_PTX_P3 PCIE_IRX_C_PTX_N3

WAKE#

VMAIN_PRSNT

XTALO

XTALI

U71

42

VDDC

6

VDDC

15

VDDC

41

VDDC

27

AVDDL

33

AVDDL

39

AVDDL

24

GPHY_PLLVDDL

18

PCIE_PLLVDDL

21

PCIE_PLLVDDL

17

PCIE_TXD_P

16

PCIE_TXD_N

22

PCIE_RXD_P

23

PCIE_RXD_N

4

WAKE#

2

REST#

20

PCIE_REFCLK_P

19

PCIE_REFCLK_N

40

VMAIN_PRSINT

1

LOW_PWR

13

XTALO

12

XTALI

26

RDAC

3

CLKREQ#

BCM57780A0KMLG_QFN48_7X7

3

L

AN_BIASVDDH

L

AN_XTALVDDH

LAN_AVDDH

AVDDH

TRD3_N

TRD3_P

TRD2_N

TRD2_P

TRD1_N

TRD1_P

TRD0_P

TRD0_N

MODE

EEDATA

EECLK

SR_LX

SR_VFB

SR_VDD

NC

25

14

30

36

LAN_TX3-

37

LAN_TX3+

38

LAN_TX2-

35

LAN_TX2+

34

LAN_RX1-

31

LAN_RX1+

32

LAN_TX0+

28

LAN_TX0-

29

48

47

46

45

5

LAN_DATA

43

LAN_CLK

44

1.2V OUTPUT

11

8

10

9

0.1U_0402_16V4Z

7

C622

C1336

0.1U_0402_16V4Z

4.7uH

1 2

4.7UH_PG031B-4R7MS_1.1A_20%

+3V_LAN

1

C574

4.7U_0805_10V4Z

2

L33

BIASVDDH

XTALVDDH

LINKLED#

SPD100LED#

SPD1000LED#

TRAFFICLED#

SR_VDDP

PAD

49

2

L

30

1 2

MBK1608121YZF_0603

1334 0.1U_0402_16V4Z

C

1 2

31

L

1 2

MBK1608121YZF_0603

C

1335 0.1U_0402_16V4Z

MBK1608121YZF_0603

1

2

12

L32

1 2

C1340

0.1U_0402_16V4Z

C602

0.1U_0402_16V4Z

C602

LAN_TX3- <32>

LAN_TX3+ <32>

LAN_TX2- <32>

LAN_TX2+ <32>

LAN_RX1- <32>

LAN_RX1+ <32>

LAN_TX0+ <32>

LAN_TX0- <32>

LINKLED# <32>

ACTIVITY# <32>

LAN_CLK

LAN_DATA

+1.2V_LAN

1

2

3V_LAN

+

+3V_LAN

12

1

C603

C603 10U_0805_10V4Z

10U_0805_10V4Z

2

@

@ R443

R443

4.7K_0402_5%

R444

4.7K_0402_5%

12

R445

4.7K_0402_5%

12

@

@ R446

R446

4.7K_0402_5%

1

C588 0.1U_0402_16V4Z

1 2

@

U23

@U23

@

8

VCC

7

WP

6

SCL

5

SDA

AT24C02_SO8

GND

1

A0

2

A1

3

NC

4

+3VALW

@

1 2

L29 MBK1608121YZF_0603

+5VALW

2

G

12

R439

R439 33K_0402_5%

33K_0402_5%

13

D

Q34

Q34 2N7002_SOT23

2N7002_SOT23

S

A A

EN_WOL<3 7>

EN_WOL

5

L29 MBK1608121YZF_0603

1 3

1

C585

0.1U_0603_25V7K

2

D

Q68

G

2

AO3414_SOT23-3

S

2

C581

C581 10U_0805_10V4Z

10U_0805_10V4Z

1

2

C582

0.1U_0402_16V4Z

1

C583

0.1U_0402_16V4Z

2

Layout Notice : Place as close chip as possible.

4

+3V_LAN

1

C584

C584 1U_0603_10V4Z

1U_0603_10V4Z

2

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/25 2008/04/

Compal Secret Data

Deciphered Date

2

Compal Electronics,Ltd.

Title

Broadcom LAN 57780/57790

Size Document Nu mber Rev

C

Date: Sheet of

NIWBA_LA5371P

1

31 52Tuesday, March 24, 2009

0.1

5

C607 0.1U_040 2_16V4ZC607 0.1U_0402_16V4Z

D D

1 2

C608 0.1U_040 2_16V4ZC608 0.1U_0402_16V4Z

1 2

C609 0.1U_040 2_16V4ZC609 0.1U_0402_16V4Z

1 2

C611 0.1U_040 2_16V4ZC611 0.1U_0402_16V4Z

1 2

4

LAN_TX3+<31>

LAN_TX3-<3 1>

LAN_TX2-<31>

LAN_TX2+<31>

LAN_RX1+<31>

LAN_RX1-<31>

LAN_TX0-<31>

LAN_TX0+<31>

LAN_TX3-

LAN_TX2-

LAN_TX2+

LAN_RX1+

LAN_RX1-

LAN_TX0-

TCT

3

T

80

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

350UH_IH-037-2

MCT1 MX1+

MX1-

MCT2 MX2+

MX2-

MCT3 MX3+

MX3-

MCT4 MX4+

MX4-

2

24

MDO3+LAN_TX3+

23

MDO3-

22

MCT2

21

MDO2-

20

MDO2+

19

MCT1

18

MDO1+

17

MDO1-

16

MCT0

15

MDO0-

14

MDO0+LAN_TX0+

13

T80

350uH_NS0013LF

100@

R479 75_0402_5%R479 75_0402_5%

R480 75_0402_5%R480 75_0402_5%

R482 75_0402_5%R482 75_0402_5%

R483 75_0402_5%R483 75_0402_5%

12

RJ45_PRMCT3

1

C C

RJ11+RJ45 CONN

JLAN

ACTIVITY#<31>

+3V_LAN

B B

A A

0.01U_0402_16V7K

LINKLED#<31>

+3V_LAN

C612

0.01U_0402_16V7K

C612

C610

1

2

R485 330_0402_5%R485 330_0402_5%

1

2

RJ45_PR

R481 330_0402_5%R481 330_0402_5%

12

C614

1000P_1206_2KV7K

12

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+

1 2

JLAN

12

Amber LED-

11

Amber LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

FOX_JM36113-P2221-7F

FOX_JM36113-P2221-7F <BOM Structure>

C616

0.1U_0402_16V4Z

C616

16

SHLD4

15

SHLD3

14

SHLD2

13

SHLD1

2

1

2

C617

0.1U_0402_16V4Z

1

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

5

4

3

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN CONTROLLER

KIWB1/B2_LA4601P

1

32 52Tuesday, March 24, 2009

0.1

5

4

3

2

1

513 : CARD_3V3

0 0

521 : change C79 form 4.7u to 0.1u, add R47 100K ohm,

change C526 form 1u to 4.7u

D D

C619

4.7U_0603_6.3V6K

R491 0_0603_5%@R491 0_0603_5%@

+3VS

+3VALW

1 2

R492 0_0603_5%R492 0_0603_5%

1 2

1

2

1

2

keep supply 3.3V to 3V3_IN when S3

Vender suggesttion

C C

R495

R495 100K_0402_5%

100K_0402_5%

1 2

1

C623

C623 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

旁旁旁

旁

XDPWR_SDPWR_MSPW R

C1337

0.1U_0402_16V4Z

RST#

100K change to 4.7u CAP==>

R489 0_0402_5%R489 0_0402_5%

1 2

C618 0.1U_0402_16V4ZC618 0.1U_0402_16V4Z

U25

1

AV_PLL

3

NC

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

USB20_N5<16> USB20_P5<16>

R497

6.19K_0402_1%

3V3_IN RST# MODE SEL XTLO XTLI

1 2

USB20_N5 USB20_P5

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5159-GR_LQFP48_7X7

R498

0_0402_5%

1 2

預

12

VREG

MS_D4

XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6

XD_RDY_SP14

MS_INS#_SP9

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO

EECS EESK

SD_CMD

JR

EAD1

S

DDAT4_XDWP#_MSD7

S

DDAT1_XDD3_MSD1

S

DDAT7_XDD2_MSD2

S

DDAT6_XDD7_MSD3

S

DDAT4_XDWP#_MSD7

S

DDAT2_XDRE# DCD

S S

DWP

SDDAT5_XDD0_MSD6

XDPWR_SDPWR_MSPW R

R490

12

0_0402_5%

12

0_0402_5%

1 2

MS-SCLK

SD-CLK

CLOCK SOURCE

12MHz CRYSTAL INPUT

CLOCK GENERATOR'S 48MHZ INPUT INPUT TO PIN48

C621 1U_0603_16V4ZC621 1U_0603_16V4Z

1 2

10 22 30

NC

43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18

XTAL_CTR 3V3_IN

13 24

15 16 17 36

XDCLE XDCE#

XDALE SDDAT2_XDRE# SDDAT3_XDWE#

XD_RDY SDDAT4_XDWP#_MSD7 SDDAT5_XDD0_MSD6 SDCLK_XDD1_MSCLK SDDAT6_XDD7_MSD3

MS_INS# SDDAT7_XDD2_MSD2 SDDAT0_XDD6_MSD0 SDDAT1_XDD3_MSD1

XDD5_MSBS XDD4_SDDAT1

SDCD SDWP XDCD

12

R496

0_0603_5%

SD_CMD

100K_0402_5%

R1176

R1177

pin 13 (XTAL CTL)

FLOATING

PULL HIGH

1

C620

0.1U_0402_16V4Z

2

XDD4_SDDAT1 SDDAT0_XDD6_MSD0 SDDAT0_XDD6_MSD0 SDDAT3_XDWE#

XDCE# SDDAT2_XDRE# SDCLK_XDD1_MSCLK XDCLE XDALE XD_RDY XDCD

REMARK

EAD1

33

x

D-WP

8

x

D-D3

9

x

D-D2

24

M

S-DATA3

27

D-DAT4

S

30

D-DAT2

S

1

S

D-CD

2

S

D-WP

32

xD-D0

6

xD-D5

7

xD-D4

5

xD-D6

34

xD-WE

3

xD-VCC

4

xD-D7

37

xD-CE

38

xD-RE

10

xD-D1

36

xD-CLE

35

xD-ALE

39

xD-R/B

40

xD-CD

TAITW_R015-A10-LM_NR

TAITW_R015-A10-LM_NR ME@

ME@

23

S

D-DAT5

14

S

D-DAT0

25

S

D-CMD

29

S

D-DAT3

12

S

D-DAT1

S-SCLK

M

S-BS

MS-INS

MS-VCC

SD-CLK SD-DAT6 SD-DAT7

SD-VCC

GND GND

26 13 22 28 15 19 17

20 18 16 21

31 11

41 42

MS-SCLK SD-CLKCLK_48M_CR

M

MS-DATA1 MS-DATA2 MS-DATA0

7IN1-GND 7IN1-GND

R663

R663 33_0402_5%

33_0402_5% @

@

1 2

C805

C805 22P_0402_50V8J

22P_0402_50V8J

@

MSCLK and SDCLK solution

將

SD_DAT1

使使

連連連

S

DDAT5_XDD0_MSD6

S

DDAT0_XDD6_MSD0

S

D_CMD

DDAT3_XDWE#

S

X

DD4_SDDAT1

S-SCLK

M

X

DD5_MSBS

M

S_INS#

SDDAT1_XDD3_MSD1XDD5_MSBS SDDAT7_XDD2_MSD2

SD-CLK SDDAT6_XDD7_MSD3SDDAT6_XDD7_MSD3 SDDAT7_XDD2_MSD2

R665

R665 33_0402_5%

33_0402_5% @

@

1 2

C807

C807 22P_0402_50V8J

22P_0402_50V8J

@

該該該該該該該該

, (

但但但但

RTS5158E側).

RTS5158E的pin23

X

DPWR_SDPWR_MSPW R

R664

R664 33_0402_5%

33_0402_5% @

@

1 2

C806

C806 22P_0402_50V8J

22P_0402_50V8J

@

EMI

B B

CLK_48M_CR<12>

MODE SEL

1

C625

47P_0402_50V8J

A A

2

5

12

R500

@C625

@

R500 0_0402_5%

0_0402_5%

CLK_48M_CR

R499 0_0603_5%R499 0_0603_5%

1 2

C624

1 2

6P_0402_50V8D

6P_0402_50V8D @

@

Y5

12MHZ_16P_6X12000012

12MHZ_16P_6X12000012 @

C626

1 2

6P_0402_50V8D

6P_0402_50V8D @

@

4

@

XTLI

12

XTLO

Security Classification

2006/08/04 2006/10/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

1394+3 in 1 Card

NIWBA_LA5371P

1

33 52Tuesday, March 24, 2009

1.0

A

1 1

SATA_DTX_C_IRX_N0<13> SATA_DTX_C_IRX_P0<13>

+5VS +3VS

1

C627

C627 1000P_0402_50V7K

1000P_0402_50V7K

2

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

1

C628

0.1U_0402_16V4Z

2

1

C629

C629 1U_0603_10V4Z

1U_0603_10V4Z

2

B

S

ATA_ITX_DRX_P0<13>

S

ATA_ITX_DRX_N0<13>

C634 0.01U_04 02_16V7KC634 0.01U_04 02_16V7K

1 2

C633 0.01U_04 02_16V7KC633 0.01U_04 02_16V7K

1 2

1

C630

C630 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C631

C631 10U_0805_10V4Z

10U_0805_10V4Z

2

S

ATA_ITX_DRX_P0 ATA_ITX_DRX_N0

S

SATA_DTX_IRX_N0 SATA_DTX_IRX_P0

+3VS

+5VS

1

@

@ C632

C632

0.1U_0402_16V4Z

2

C

S

ATA HDD Conn.

JH

DD

1

G

ND

2

A

+

3

-

A

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

FOX_LD2122H-S43_NR

ME@

GND GND

D

E

F

G

H

SATA ODD Conn.

JODD

1

SATA_ITX_DRX_P1<13>

SATA_DTX_C_IRX_N1<13> SATA_DTX_C_IRX_P1<13>

23 24

CONN need change to new CONN

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_DTX_IRX_P1

SATA_ITX_DRX_N1<13>

C635 0.01U_0402_16V7KC635 0.01U_0402_16V7K

1 2

C636 0.01U_0402_16V7KC636 0.01U_0402_16V7K

1 2

SATA_ITX_DRX_P1 SATA_ITX_DRX_N1

SATA_DTX_IRX_N1

+5VS

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

OCTEK_SLS-13SB1G_RV

OCTEK_SLS-13SB1G_RV ME@

ME@

2 2

+USB_VCCB

1

+

C733

150U_B_6.3VM_R40M

3 3

SATA_DTX_C_IRX_N4<13> SATA_DTX_C_IRX_P4<13>

C733

2

SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4

SATA_ITX_DRX_P4_CONN<13> SATA_ITX_DRX_N4_CONN<13>

1

C734

C734 470P_0402_50V7K

470P_0402_50V7K

2

W=80mils

USB20_N1<16>

USB20_P1<16>

SATA_ITX_DRX_P4_CONN SATA_ITX_DRX_N4_CONN

SATA_DTX_IRX_N4_CONN

C13380.01U_0402_16V7K C13380.01U_0402_16V7K

12

SATA_DTX_IRX_P4_CONN

C13390.01U_0402_16V7K C13390.01U_0402_16V7K

12

ESATA and USB Conn.

JESATA

USB

USB20_N1 USB20_P1

1 2 3 4

5 6 7 8

9 10 11

12 13 14 15

USB

VBUS DD+ GND

GND A+

ESATA

AGND BB+ GND

GND GND GND GND

TYCO_1759576-1

TYCO_1759576-1 ME@

ME@

A+ = RXP A- = RXN

B- = TXN B+ = TXP

+5VALW

U34

1

C732 0.1U_0402_16V4ZC732 0.1U_0402_16V4Z

4 4

A

12

USB_ON<37,40>

USB_ON

GND

2

IN

3

IN

4

EN

G545A1P1U_SO8

B

+USB_VCCB

OUT OUT OUT OC#

8 7 6 5

1

2

C735

1000P_0402_50V7K@

USB_OC#0 <16,40>

C

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

D

2007/10/15 2008/10/15

E

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

HDD & ODD Connector

NIWBA_LA5371P

G

34 52Tuesday, March 24, 2009

H

0.1

5

4

3

2

1

2 1

J

+

5VS

MBK1608121YZF_0603

1 2

503

L

1

640

640 C

D D

MIC1

WM-64PCY_2P

45@

C C

MIC4

WM-64PCY_2P

45@

C

2

C641

10U_0805_10V4Z

1

GNDA

2

1

GNDA

2

C641

0.1U_0402_16V4Z

1

C655

C655 47P_0402_50V8J

47P_0402_50V8J

2

GNDA

1

C660

C660 47P_0402_50V8J

47P_0402_50V8J

2

ARRAY@

GNDA

A

djustable Output

+MIC2_VREFO

12

+MIC2_VREFO

12

ARRAY@

1

2

3

R5130_0603_5% R 5130_0603_5%

R5200_0603_5%

42MMJ42MM

U

26

N

I

ND

G

S

HDN

G9191-475T1U_SOT 23-5

G9191-475T1U_SOT 23-5 @

@

21

D31

D31 RB751V_SOD323

RB751V_SOD323

ARRAY@

12

R509

4.7K_0402_5%

4.7K_0402_5% ARRAY@

ARRAY@

INT_MIC_L

21

D32

D32 RB751V_SOD323

RB751V_SOD323

ARRAY@

12

R518

4.7K_0402_5%

ARRAY@

INT_MIC_R

5

O

UT

4

B

YP

+

1

@

C642

2

12

R789

4.7K_0402_5%

4.7K_0402_5% MONO@

MONO@

R829

1 2

R731

1 2

R732

1 2

R733

1 2

5VDDA_CODEC

1 @

@

C643

2

4.7U_0805_10V4Z

0.01U_0402_16V7K

4.7U_0805_10V4Z

Internal MIC / Array MIC

0_0402_5%

4.7K_0402_5%

EXT_MIC_L<36>

EXT_MIC_R<36>

external MIC

1

C819

2

@

22P_0402_50V8J

+MIC1_VREFO_L

12

R533

R535

R533

4.7K_0402_5%

INT_MIC_L

INT_MIC_R

MIC Sense R516 place near pin13

Capless HP Sense R517 place near pin34

C820

@

22P_0402_50V8J

1 2

GND

Pin Assignment

B B

LINE-OUT (Pin35/36)

Capless HP-OUT (Pin32/33)

LINE1 (Pin23/24)

MIC1(Pin21/22)

MONO-OUT(Pin37)

MIC2(Pin16/17)

PC Beep

EC Beep

A A

BEEP#<37>

0.1U_0402_16V4Z@

PCH_SPKR<13>

ICH Beep

C667

C666

1

1U_0603_10V4Z

2

C668

1U_0603_10V4Z

5

R524

12

1 2

560_0402_5%

R531

1 2

12

560_0402_5%

10K_0402_5%

Location Function

Internal

External

Internal

+3VS

12

R521

R521 10K_0402_1%

10K_0402_1%

C662

12

1U_0603_10V4Z

R522

R522 10K_0402_1%

10K_0402_1%

1 2

R523 20K_0402_5%R 523 2 0K_0402_5%

1

C

Q37

2

B

2SC2411KT146_SOT2 3-3

E

3

R532

12

D23 RB751V_SOD323

RB751V_SOD323

2 1

@D23

@

Int Speaker

Headphone out

Line in

Mic in

Internal Subwoofer

Internal Mic

C665 1U_0603_10V4ZC665 1U_0603_10V4Z

12

R527

R527 20K_0402_5%

20K_0402_5%

@

1 2

0.1U_0402_16V4Z

LINE_OUTL

PC_BEEPPC_BEEP1

4

LINE_OUTR

R709 0_0402_5%R709 0_0402_ 5%

R710

1

2

22P_0402_50V8J

C811

1 2

H

1

C821

2

@

R7011K_0402_5% R7011K_0402_5 %

R7021K_0402_5% R7021K_0402_5 %

+5VAMP

1

2

0_0402_5%

DA_RST_CODEC#

DA_SYNC_CODEC

DA_SDOUT_CODEC

1 2

R 33_0402_5%

33_0402_5%

1

C808

2

@

22P_0402_50V8J

2.2U_0603_16V6K

1 2

ARRAY@

MIC_JD<36>

PLUG_IN<36>

2.2U_0603_16V6K

HDA_BITCLK_CODEC<13>

HDA_SDOUT_CODEC<13>

HDA_RST_CODEC#<13>

HDA_SYNC_CODEC<13>

W=40mil

1

C812

4.7U_0805_10V4Z

2

12

R712

R711

10K_0402_5%

@

+

5VDDA_CODEC

1

C816

2

1

C649

C648

0.1U_0402_16V4Z

2

10U_0805_10V4Z

0.1U_0402_16V4Z

787

+

E

MI

DA_BITCLK_CODEC

H

@R787

@

3VS

1 2

L

37

MBK1608121YZF_0603

+

3VDD_CODEC

1

C637

2

1

C638

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Place near Pin25 Place near Pin38Place near Pin1

+5VDDA_CODEC

U64

MIC_INTL MIC_INTR

R7031K_0402_5% R7031K_0402_ 5%

R7041K_0402_5%

HDA_SDIN1<13>

GPO_AUD<37>

EAPD<37>

LIN

RIN

1

10K_0402_5%

2

1 2

R734 0_0402_5%MONO@R734 0_04 02_5%MONO@

MIC_INTL

MIC_INTR

1 2

R706 22 _0402_5%

1 2

16

6

15

GAIN0

GAIN1

C813

0.1U_0603_25V7K

3

2

3

5

17

9

7

1

C815

0.1U_0603_25V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MIC_INL

C651

12

MIC_INR

C650

12

MIC_EXTL_C

C6522.2U_0 603_16V6K C6522.2U_0603_16V6K

12

MIC_EXTR_C

C6532.2U_0 603_16V6K C6532.2U_0603_16V6K

12

PC_BEEP

HDA_BITCLK_CODEC

HDA_SDOUT_COD EC

SDATA_IN

HDA_RST_CODEC#

HDA_SYNC_CODEC

SENSEA

R51620K_0402_1% R51620K_04 02_1%

SENSEB

12

R5175.1K_0402_1% R5175.1K_0402_ 1%

R7620_0402_5% R7620_0402_5%

U40

VDD PVDD PVDD

GAIN0

GAIN1

LIN-

RIN-

LIN+

RIN+

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

21

MIC1_L

22

MIC1_R

12

BEEP_IN

6

BITCLK

5

SDATA_OUT

8

SDATA_IN

11

RESET#

10

SYNC

2

GPIO0/DMIC_DATA1/2

3

GPIO1/DMIC_DATA3/4

13

SENSE A

34

SENSE B

47

EAPD

43

NC

4

DVSS

7

DVSS

ALC272-GR_LQFP48

12

NC

SHUTDOWN

TPA6017A2PWPR_TSSOP20

19

8

LOUT-

14

ROUT-

4

LOUT+

18

ROUT+

1

GND

11

GND

13

GND

20

GND

21

GND

10

BYPASS

2008/03/25 2008/04/

+3VDD_CODEC

1

DVDD

DMIC_CLK1/2

DMIC_CLK3/4

LINE2_VREFO

LINE1_VREFO

+3VALW

R707

@

9

DVDD_IO

LOUT1_L

LOUT1_R

LOUT2_L

LOUT2_R

HPOUT_L

HPOUT_R

MONO_OUT

MIC1_VREFO

MIC2_VREFO

1 2

38

AVDD125AVDD2

10K_0402_5%

AMP_OFF# EC_MUTE#

20mil

1

C814

4.7U_0805_10V4Z

2

Compal Secret Data

Deciphered Date

SPDIFO1

SPDIFO2

CPVREF

VREF

JDREF

CBN

CBP

AVSS1 AVSS2

2

R708

Place near Pin9

+IOVDD_CODEC

1

C639

2

0.1U_0402_16V4Z

C_LINE_OUTL

35

C_LINE_OUTR

36

39

NEED TO STUDY (FBMA-L10-160808-800LMT) COPMAL PN:SM01000DI00

41

48

45

33

32

MONO_OUT

37

46

44

20

18

28

19

31

27

40

30

29

26 42

0.1U_0402_16V4Z

1 2

SPK_L1-

SPK_R1-

SPK_L2+

SPK_R2+

1 2

C659 2.2U_0 603_10V6KC659 2.2U_0603_10V6K

C763

0_0402_5%

1 2

R777 0_0402_5%R777 0_0402_5%

1

C842

2

10U_0805_10V4Z

C645 3300P_0603_50V7KC 645 3300P_0603_50V7K

1 2

C646 3300P_0603_50V7KC 646 3300P_0603_50V7K

1 2

R7630_0402_5% R7630_0402_5%

12 R5106 3.4_0402_1% R51063.4_0402_1%

12 R5126 3.4_0402_1% R51263.4_0402_1%

MONO_OUT <36>

+MIC1_VREFO_L

+MIC2_VREFO

1 2

C658 2.2U_0 603_10V6KC658 2.2U_0603_10V6K

+5VAMP +5VS

1

2

SPK_L1- <36>

SPK_R1- <36>

SPK_L2+ <36>

SPK_R2+ < 36>

bead?

2

C764

C764 10U_0805_10V4Z

10U_0805_10V4Z

1

EC_MUTE# <36,37>

SPDIF_OUT <36>

HP_OUTL <36>

HP_OUTR <36>

12

R525

R525 20K_0402_1%

20K_0402_1%

12

R6230_0603_5% R 6230_0603_ 5%

Compal Electronics,Ltd.

Title

HD Audio Codec_ALC272

Size Document Nu mber Rev

C

Date: Sheet of

+1.5VS

LINE_OUTL

LINE_OUTR

Internal Speaker

SPDIF

Headphone

Add 64 ohm serial resistor to avoid ESD

2

1

C823

C822

1

2

10U_0805_10V4Z

0.1U_0402_16V4Z

Close Pin27

GAIN0 GAIN1 0 0 6dB 0 1 10dB 1 0 15.6dB 1 1 21.6dB

+5VAMP +5VAMP

R714

R713

@ R7 13

@

100K_0402_1%

1 2

R715

100K_0402_1%

1 2

NIWBA_LA5371P

1

R714

100K_0402_1%

1 2

GAIN1GAIN0

R716

100K_0402_1%

@

1 2

35 52Tuesday, March 24, 2009

0.1

5

D D

SubWoofer Conn.

Speaker Connector

WOOFER-

WOOFER+

SPK_R1-<35> SPK_R2+<35> SPK_L1-<35> SPK_L2+<35>

C C

SPK_R1SPK_R2+ SPK_L1SPK_L2+

L43 FBMA-L10-160808-121LMT_2PL43 FBMA-L10-160808-121LMT_2P

1 2

L44 FBMA-L10-160808-121LMT_2PL44 FBMA-L10-160808-121LMT_2P

1 2

L45 FBMA-L10-160808-121LMT_2PL45 FBMA-L10-160808-121LMT_2P

1 2

L46 FBMA-L10-160808-121LMT_2PL46 FBMA-L10-160808-121LMT_2P

1 2

L47 FBMA-L10-160808-121LMT_2PL47 FBMA-L10-160808-121LMT_2P

1 2

L48 FBMA-L10-160808-121LMT_2PL48 FBMA-L10-160808-121LMT_2P

1 2

4

20milEMI 20080826

WOWO+ SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_CONN SPK_L2+_CONN

JSPK1

1

2

3

4

5 6

ACES_87213-0600G

7

5

G1

8

6

G2

3

udio Jack

A

MI 20080826

E

L49

EXT_MIC_L<35>

EXT_MIC_R<35>

MIC_JD<35>

EXT_MIC_L

47P_0402_50V8J

EXT_MIC_R

47P_0402_50V8J

MIC_JD

FBMA-L10-160808-121LMT_2P

1

C669

2

GNDA

FBMA-L10-160808-121LMT_2P

1

C671

2

GNDA

L49

1 2

L50

1 2

1

10P_0402_50V8J

2

GNDA

1

10P_0402_50V8J

2

GNDA

2

EXT_MIC_L-2

C670

@ C670

@

EXT_MIC_R-2

C672

@ C672

@

220P_0402_50V7K

1

C67310P_0402_50V8J@C67310P_0402_50V8J @

2

GNDA

GNDAGNDA

220P_0402_50V7K

Audio Jack

MIC IN

JMIC1

1 2

3

4

5

6

G

SINGA_2SJ-0960-C02

SINGA_2SJ-0960-C02 ME@

ME@

1

C675

1 2

C675

Headphone

JHP1

6 1

4

5

7 3 8

2

SINGA_2SJ1533-000111

C674

1 2

R537

@R537

@

1K_0402_5%

12

GNDA

12

R538

@ R538

@ 1K_0402_5%

1K_0402_5%

EMI 20080826

HP_OUTR<35>

HP_OUTL<35>

PLUG_IN<35>

B B

33K_0402_5%

1 2

R620

G1442 SubWoofer Amplifier 1nd = APA3011 (SA00001JM00) 2nd = TPA6211 (SA621110010 )

0.01U_0402_16V7K

0.01U_0402_16V7K 1 2

C760

1U_0603_10V4Z

MONO_OUT<35>

A A

MONO_OUT

1 2

C759

18K_0402_5%

R618

C760

68K_0402_5%

1 2

R619

C761

2.2U_0603_6.3V4Z

C761

+5VAMP

WIN1

WIN2

2

1

1500P_0402_50V7K

1 2

C762

W=40mil

U39

6

VDD

SHUTDOWN#

3

IN+

4

IN-

2

BYPASS

APA3011XA-TRL_MSOP8

GND

Vo+

Vo-

1

5

8

7

WOOFER+

WOOFER-

+3VALW

1 2

R621

R621 10K_0402_5%

10K_0402_5% @

@

0_0402_5%

HP_OUTR

HP_OUTL

PLUG_IN

+5VS

1

C677

0.1U_0402_16V4Z

2

ONLY FOR 15.6W

EC_MUTE#AMP_OFF#

R622

12

L51

1 2

FBMA-L10-160808-121LMT_2P

FBMA-L10-160808-121LMT_2P L52

L52

1 2

FBMA-L10-160808-121LMT_2P

SPDIF_OUT<35>

EC_MUTE# <35,37>

220P_0402_50V7K

PR-OUT

PL-OUT

SPDIF_OUT

C676

12

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2008/03/25 2008/04/

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

AMP,Audio speaker CONN

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

KIWB1/B2_LA4601P

1

36 52Tuesday, March 24, 2009

0.1

+

3VALW

+3VALW

LAN_WAKE#<31>

PCI_PME#<16>

+3VALW

+5VALW

38

L

1 2

FBM-11-160808-601-T_0603

0.1U_0402_16V4Z

1 2

L

39 FBM-11-160808-601-T_0603

C687 22P_0402_50V8J@ C687 22P_0402_50V8J@

1 2

R543 47K_0402_5%R543 47K_0402_5%

0.1U_0402_16V4Z

R830 47K_ 0402_5%

1 2

R831 47K_ 0402_5%@R831 47K_0402_5%@

1 2

683

C

12

C686

@

ENE UPDATE 08/10/21

1 2

R551 0_0 402_5%R551 0_0402_5%

1 2

R554 0_0402_5%@R554 0_0402_5%@

S

G

+3VALW

1 2

R557 100K_0402_1%@R557 100K_ 0402_1%@

1 2

R558 100K_0402_1%@R558 100K_ 0402_1%@

1 2

R559 10K_0402_5%@R559 10K_0402_5%@

R560

1 2

R561

1 2

4.7K_0402_5%@

2

FRD#SPI_SO

FSEL#SPICS#

KSO17

EC_SMB_CK1

EC_SMB_DA1

2

1

E

CAGND

KB_RST#<16>

2

1

D

13

Q38

@

Q38

@

2N7002_SOT23

1

C

1000P_0402_50V7K

2

12

R541 10_0402_5%@R541 10_0402_5%@

KSO[0..15]<38>

KSI[0..7]<38,41>

KSO1

KSO2

+3VALW

R550

R550 10K_0402_5%

10K_0402_5%

@

1 2

+3VALW

+

EC_AVCC

684

0_0402_5%

1 2

2 1

@

RB751V_SOD323

EC_PME#

R810

1 2

R811

1 2

R

779

D24

PWR_LED_SC#<41>

EC_TX_P80_DATA<30,38> EC_RX_P80_CLK<30,38>

PCH_TEMP_ALERT#<16>

4.7K_0402_5%

EC_SMB_DA1

4.7K_0402_5%

0.1U_0402_16V4Z

C678

1

2

G

LPC_FRAME#<13,38>

LPC_AD3<13,38> LPC_AD2<13,38> LPC_AD1<13,38> LPC_AD0<13,38>

CLK_PCI_LPC<16>

PCI_RST#<16,38>

EC_SCI#<16>

KSO[0..15]

KSI[0..7]

EC_SMB_CK1<44> EC_SMB_DA1<44> EC_SMB_CK2<14> EC_SMB_DA2<14>

SLP_S3#<15> SLP_S5#<15>

EC_SMI#<16>

LID_SW#<38>

AC_PRESENT<15>

ME_FLASH<13>

KILL_SW#<38>

FAN_SPEED1<5>

3G_OFF#<30>

ON/OFF#<41>

NUM_LED#<38>

EC_SMB_CK1

+

3VALW

1000P_0402_50V7K

0.1U_0402_16V4Z

ATEA20<16>

SERIRQ<13,38>

KSI3<38,41> KSI4<38>

KSO16<41>

KSO17<41>

C679

1

2

0.1U_0402_16V4Z

EC_TX_P80_DATA EC_RX_P80_CLK

PCH_TEMP_ALERT#

0.1U_0402_16V4Z

C680

1

2

KB_RST#_EC

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI# LID_SW#

FAN_SPEED1

XCLKI XCLKO

1000P_0402_50V7K

C681

1

2

1 2 3 4 5 7 8

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

1000P_0402_50V7K

C682

1

2

A20/GPIO00

LPC & MISC

C682

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

9

VCC

PS2 Interface

C685

G KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0

PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

XCLK1 XCLK0

KB926QFA1_LQFP128

22

VCC

GND

11

EC_AVCC

+

33

96

111

125

67

VCC

AVCC

NVT_PWM/PWM1/GPIO0F

I

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

PWM Output

DA Output

SPI Device Interface

SPI Flash ROM

GPIO

GND

24

35

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

94

69

113

ADP_I/AD2/GPIO3A

CAPS_LED#/GPIO53

SUSP_LED#/GPIO55

EC_SWI#/GPXO06

WL_OFF#/GPXO09

U

29

NVT_PWM

I

AD3/GPIO3B AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A

PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

BKOFF#/GPXO08

GPXO10 GPXO11

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

21

BEEP#

23 26

ACOFF

27

63

BATT_OVP

64 65 66 75

GPO_AUD_R

76

DAC_BRIG

68

EN_FAN1

70

IREF

71 72

83

USB_ON

84 85

TP_LOCK#

86

TP_CLK

87

TP_DATA

88

97 98 99 109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

RCIRRX

73

I2C_INT I2C_INT

74 89

CHARGE_LED0#

90

CAPS_LED#

91

CHARGE_LED1#

92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

SYSON

ACIN

EC_LID_OUT#

EC_ON

MUTE_LED

ICH_POK_EC ICH_POK BKOFF#

WIRELESS_LED#

SUSP# PBTN_OUT#

1

C691

C691 1U_0603_10V4Z

1U_0603_10V4Z

2

I

NVT_PWM <29> BEEP# <35 > NOVO# <41> ACOFF <45>

BATT_TEMP <44> BATT_OVP <45> ADP_I <45>

SUS_PWR_DN_ACK <15> LCD_COLOR <29>

1 2

R823 0 _0402_5%R823 0_0402_5%

DAC_BRIG <29> EN_FAN1 <5> IREF <45> CHGVADJ <45>

EC_MUTE#

EC_MUTE# <35,36>

TP_LOCK# <39> TP_CLK <38>

TP_DATA <38>

EN_WOL <31> BATT_SEL_EC <45> CMOS_OFF# <40>

FRD#SPI_SO <39>

FWR#SPI_SI <39>

SPI_CLK <39>

FSEL#SPICS# <39>

RCIRRX <41>

I2C_INT <41>

FSTCHG <45>

CHARGE_LED0# <39>

CAPS_LED# <38>

CHARGE_LED1# <39>

PWR_LED# <39>

SYSON <30,42 ,47> VR_ON <51> ACIN <43,45>

EC_RSMRST# <15> EC_LID_OUT# <14> EC_ON <41>

MUTE_LED# <41>

BKOFF# <29> WL_OFF# <30> TV_POWER_SW <30>

WIRELESS_LED# <39>

ENE ISSUE CHANGE FROM 4.7uF TO 1uF

R546 10K_0402_5%@R546 10K_0402_5%@

1 2

USB_ON <34,40>

R548 4.7K_0402_5%@R548 4.7K_0402_5%@

1 2

D25 RB751V_SOD3 23D25 RB751V_SOD323

1 2

R555 0 _0402_5%

@

SLP_S4# <15>

ENBKL <29>

EAPD <35>

SUSP# <16,30,42,47 ,49> PBTN_OUT# <15> BT_OFF# <4 0>

SUSP#

GPO_AUD <35>

21

1

2

+3VALW

USB_ON

R547 10K_0402_5%R547 10K_0402_5%

1 2

KB926 SPI STRAP PIN

+3VS

12

R549

R549 10K_0402_5%

10K_0402_5%

ICH_POK <1 5>

1 2

R556 1 0K_0402_5%R556 10K_0402_5%

@

@ C692

C692 1000P_0402_50V7K

1000P_0402_50V7K

+3VS

TP_CLK

TP_DATA

BATT_OVP

BATT_TEMP

ACIN

R544 4.7K_0402_5%R544 4.7K_0402_5%

1 2

R545 4.7K_0402_5%R545 4.7K_0402_5%

1 2

C688 100P_0402_50V8JC688 100P_0402_50V8J

1 2

C689 100P_0402_50V8JC689 100P_0402_50V8J

1 2

C690 100P_0402_50V8JC690 100P_0402_50V8J

+5VS

20080606

ECAGND

needed to update to D3 version SA00001J580

+3VS

R562

2.2K_0402_5%

@

1

@

@ C694

C694 100P_0402_50V8J

100P_0402_50V8J

2

R563

2.2K_0402_5%

@

EC_SMB_CK2 EC_SMB_DA2

1

@

@ C695

C695 100P_0402_50V8J

100P_0402_50V8J

2

1 2

C693 18P_0402_50V8JC693 18P_0402_50V8J

X1

2

NC

3

32.768KHZ_12.5P_1TJS125BJ2A251

NC

C696 18P_0402_50V8JC696 18P_0402_50V8J

IN

OUT

1 2

1

4

12

@

@ R564

R564 20M_0603_5%

20M_0603_5%

XCLKO

XCLKI

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BIOS & EC I/O Port

NIWBA_LA5371P

37 52Tuesday, March 24, 2009

0.1

5

I

NT_KBD Conn.

K

SI[0..7]

D D

C C

KSO[0..15]

KSO2

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

C697 100P_0402_50V8J@C697 100P_0402_50V8J@

1 2

C699 100P_0402_50V8J@C699 100P_0402_50V8J@

1 2

C701 100P_0402_50V8J@C701 100P_0402_50V8J@

1 2

C703 100P_0402_50V8J@C703 100P_0402_50V8J@

1 2

C705 100P_0402_50V8J@C705 100P_0402_50V8J@

1 2

C707 100P_0402_50V8J@C707 100P_0402_50V8J@

1 2

C709 100P_0402_50V8J@C709 100P_0402_50V8J@

1 2

C711 100P_0402_50V8J@C711 100P_0402_50V8J@

1 2

C713 100P_0402_50V8J@C713 100P_0402_50V8J@

1 2

C715 100P_0402_50V8J@C715 100P_0402_50V8J@

1 2

C717 100P_0402_50V8J@C717 100P_0402_50V8J@

1 2

C719 100P_0402_50V8J@C719 100P_0402_50V8J@

1 2

CONN PIN define need double check

KSI[0..7] <37,41>

KSO[0..15] <37>

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

C698 100P_0402_50V8J@C698 100P_0402_50V8J@

C700 100P_0402_50V8J@C700 100P_0402_50V8J@

C702 100P_0402_50V8J@C702 100P_0402_50V8J@

C704 100P_0402_50V8J@C704 100P_0402_50V8J@

C706 100P_0402_50V8J@C706 100P_0402_50V8J@

C708 100P_0402_50V8J@C708 100P_0402_50V8J@

C710 100P_0402_50V8J@C710 100P_0402_50V8J@

C712 100P_0402_50V8J@C712 100P_0402_50V8J@

C714 100P_0402_50V8J@C714 100P_0402_50V8J@

C716 100P_0402_50V8J@C716 100P_0402_50V8J@

C718 100P_0402_50V8J@C718 100P_0402_50V8J@

C720 100P_0402_50V8J@C720 100P_0402_50V8J@

4

1 2

+5VS

3

J

P13

K

SI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

R770470_0402_5% R770470_0402_5%

12

R771470_0402_5% R771470_0402_5%

NUM_LED#<37>

CAPS_LED#<37>

12

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ACES_85201-3005N

P13

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

G1 G2

31 32

+3VALW

2

1 2

R565 0_0402_5%R565 0_0402_5%

EC_TX_P80_DATA<30,37> EC_RX_P80_CLK<30,37>

Lid Switch

+VCC_LID

2

A3212ELHLT-T_SOT23W-3

1

C DEBUG PORT

E

+3VALW

R566 100K_0402_5%R566 100K_0402_5%

1 2

EC_TX_P80_DATA EC_RX_P80_CLK

ACES_85205-0400

JP14

1

2

3

4

ME@

VDD

OUTPUT

GND

1

3

U30

Kill Switch

2

C722

10P_0402_50V8J

1

LID_SW# <37>

To TP/B Conn.

TP_CLK<37> TP_DATA<37>

1

@

@ C724

C724 100P_0402_50V8J

100P_0402_50V8J

2

+5VS

C723

0.1U_0402_16V4Z

1

@

@ C725

C725 100P_0402_50V8J

100P_0402_50V8J

2

TP_CLK TP_DATA

JP15

4

3

2

1

E&T_6905-E04N-00R

ME@

C721

0.1U_0402_16V4Z

1

2

CONN PIN define need double check

+3VALW

B B

KILL_SW#<37>

KILL_SW#

R632

100K_0402_5%

12

LSSM12-P-V-T-R_3P

3

2

1

SW2

FOR LPC SIO DEBUG PORT

JP16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A A

16

17

18

19

20

ACES_85201-2005

ACES_85201-2005 ME@

ME@

5

+5VS

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ0# PCI_RST#

CLK_PCI_DB SERIRQ

+3VS

CLK_14M_SIO <14> LPC_AD0 <13,37> LPC_AD1 <13,37> LPC_AD2 <13,37> LPC_AD3 <13,37>

LPC_FRAME# <13,37> LPC_DRQ0# <13> PCI_RST# <16,37>

CLK_PCI_DB <14>

SERIRQ <13,37>

R567 10K_0402_5%

12

@

4

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/10/15 2008/10/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

KB /SW /LPC Debug Conn.

KIWB1/B2_LA4601P

1

38 52Tuesday, March 24, 2009

0.1

OR EC 16M SPI ROM

F

3VALW

+

20mils

1

C726

0.1U_0402_16V4Z

2

U31

FRD#SPI_SO<37>

FRD#SPI_SO SPI_SO

FSEL#SPICS#<37>

R568 15_0402_5%R568 15_0402_5%

1 2

FSEL#SPICS#

U31

1

CS#

2

SO

3

WP#

4

GND

MX25L1605AM2C-12G_SO8

VCC

HOLD#

SCLK

SI

8 7 6

SPI_SI FWR#SPI_SI

5

12

R812

R812 10K_0402_5%

10K_0402_5%

R569 15_0402_5%R569 15_0402_5%

1 2

R570 15_0402_5%R570 15_0402_5%

1 2

SPI_CLKSPI_CLK_R

SPI_CLK <37>

FWR#SPI_SI <37>

SPI_CLK_R

R571

33_0402_5%

@

C727

22P_0402_50V8J

C727

@

12

0_0402_5%

12P_0402_50V8J

R832

C861

12

@

1

2

@

EMI 3G

WHITE

CHARGE_LED0#<37>

CHARGE_LED1#<37>

AMBER

WHITE

WIRELESS_LED#<37>

WHITE

LED

SC500005B00,If=5mA,Vf=2.7V~3.15V,R=460~390ohm

WHITE

PWR_LED#<37>

CHARGE_LED0#

CHARGE_LED1#

TP_LOCK#<37>

12-21SYGCS530-E1S155TR8_W

BATT_CHG_LED#

R625 470_0402_5%R625 470_0402_5%

1 2

R626 470_0402_5%R626 470_0402_5%

1 2

BATT_LOW_LED#

19-213A-T1D-CP2Q2HY-3T_WHITE

12-21SYGCS530-E1S155TR8_W

LED1

LED4

LED5

R624 750_0402_5%R624 750_0402_5%

21

R577 750_0402_5%R577 750_0402_5%

21

R627 470_0402_5%R627 470_0402_5%

21

1 2

3

2

LED7

12-22-S2ST3D-C30-2C_WHI-ORG

1

+5VALW

+5VS

+5VALW

H13

H13 HOLEA

HOLEA

1

FD1FD1

H1 HOLEAH1HOLEA

1

H7 HOLEAH7HOLEA

1

H15

H15 HOLEA

HOLEA

1

H22

H22 HOLEA

HOLEA

1

H27

H27 HOLEA

HOLEA

1

FD2FD2

H2 HOLEAH2HOLEA

1

H8 HOLEAH8HOLEA

1

H16

H16 HOLEA

HOLEA

1

H23

H23 HOLEA

HOLEA

1

H28

H28 HOLEA

HOLEA

1

FD3FD3

H3 HOLEAH3HOLEA

1

H9 HOLEAH9HOLEA

1

H17

H17 HOLEA

HOLEA

1

H24

H24 HOLEA

HOLEA

1

FD4FD4

H4 HOLEAH4HOLEA

1

H10

H10 HOLEA

HOLEA

1

H18

H18 HOLEA

HOLEA

1

H25

H25 HOLEA

HOLEA

1

H5 HOLEAH5HOLEA

1

H11

H11 HOLEA

HOLEA

1

H19

H19 HOLEA

HOLEA

1

H26

H26 HOLEA

HOLEA

1

H6 HOLEAH6HOLEA

1

H12

H12 HOLEA

HOLEA

1

H20

H20 HOLEA

HOLEA

1

H21

H21 HOLEA

HOLEA

1

Security Classification

2007/10/15 2008/10/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

2007/10/15 2008/10/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LED/EC SPI ROM

NIWBA_LA5371P

39 52Tuesday, March 24, 2009

0.1

A

+

5VALW

B

C

SB Board Conn. 10 pin

U

D

E

C728

+

USB_VCCA

+

USB_VCCA

1

+

2

W

=80mils

1

C729

C729 470P_0402_50V7K

470P_0402_50V7K

2

J

P18

1

2

USB20_P4<16>

USB20_N4<16>

USB20_N0<16>

USB20_P0<16>

USB20_P4 USB20_N4

USB20_N0 USB20_P0

2

3

4

5

6

7

8

ACES_87213-0800G

G

ND

GND

9

10

+

O

UT OUT OUT OC#

USB_VCCA

8 7 6 5

1

2

C731

1000P_0402_50V7K@

USB_OC#2 <16,34>

USB_OC#0 <16,34>

150U_B_6.3VM_R40M

U

33

1

G

C

730 0.1U_0402_16V4Z

1 1

2 2

12

USB_ON<34,37>

USB_ON

ND

2

IN

3

IN

4

EN

G545A1P1U_SO8

+5VS

12

CMOS Camera Conn

+5VS

S

3 3

12

R579

R579 10K_0402_5%

10K_0402_5%

CMOS1

1

OUT

CMOS_OFF#<37>

4 4

2

IN

GND

Q42

Q42 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

S

G

USB20_N2<16> USB20_P2<16>

D

13

Q39

2

SI2301BDS-T1-E3_SOT23-3

C862

1 2

0.01U_0402_16V7K

USB20_N2 USB20_P2

12

R580

R580 0_0603_5%

0_0603_5%

1

C738

C738 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C736

0.1U_0402_16V4Z

2

JP20

1

2

3

4

5

6

GND1

7

GND2

ACES_88266-05001

ACES_88266-05001 ME@

ME@

BT_OFF#<37>

BT_LED#<41>

2

IN

R578

R578 10K_0402_1%

10K_0402_1%

1

OUT

Q40

Q40 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

GND

3

Q43

1

DTC124EKAT146_SC59-3

OUT

IN

GND

3

BT MODULE CONN

C863

1 2

+3VS

2

BT_ACTIVE<30> WLAN_ACTIVE<30>

S

SI2301BDS-T1-E3_SOT23-3

USB20_N11<16> USB20_P11<16>

0.01U_0402_16V7K

+3VS_BT

D

13

Q41

G

2

USB20_N11 USB20_P11 BT_ACTIVE WLAN_ACTIVE BTON_LED

30mils

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z C737

C737

2

MOLEX_53780-0870

10

GND2

9

GND1

8

7

6

5

4

3

2

1

ME@ JP21

ME@

JP21

Security Classification

2006/08/18 2007/8/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2006/08/18 2007/8/18

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power OK, Reset and RTC Circuit, TP

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Power OK, Reset and RTC Circuit, TP

0.1

NIWBA_LA5371P

E

40 52Tuesday, March 24, 2009

0.1

B

ower Bottom Board Conn. 6 pin

P

+

3VALW

R

581

100_0603_5%

@

1 2

I

F NON-CIR DEVICE , MUST TO PU

R582

RCIRRX<37>

RCIRRX

+3VALW

R582

1 2

33_0402_5%

22P_0402_50V8J

1 2

R583 100_0603_5%R583 100_0603_5%

4.7U_0805_10V4Z

C739

C

IR

300_0402_5%

PWR_LED_SC#<37>

1

2

IR1

1

Vout

2

1

2

C740

VCC

3

GND

4

GND

IRM-V538/TR1_3P

NOVO_BTN#

PWR_LED_SC#

NOVO_BTN#

3

1

+

5VALW

12

R

780

ON/OFFBTN#

2

D29

D29 PJSOT24C 3P C/A SOT-23

PJSOT24C 3P C/A SOT-23

J

P23

1

2

3

4

5

6

7

GND

8

GND

ACES_85201-06051

ACES_85201-06051 ME@

ME@

MUTE_LED#<37>

KSO16<37> KSI2<37,38> KSO17<37> KSI3<37,38>

EMI REQUEST 1ST = SCA00000G00

KSI2

ottom Board Conn. 6 pin

+

5VS

12

R

781

750_0402_5%

MUTE_LED# KSO16 KSI2 KSO17 KSI3ON/OFFBTN#

2ST = SCA00000T00

2

3

D30

D30 PACDN042Y3R_SOT23-3

PACDN042Y3R_SOT23-3

1 2 3 4 5 6 7 8

KSI3KSO16

J

P25

1 2 3 4 5 6 GND GND

ACES_85201-06051

ACES_85201-06051 ME@

ME@

KSO17

2

3

D33

D33 PACDN042Y3R_SOT23-3

PACDN042Y3R_SOT23-3

ON/OFF switch

1

Power Button

TOP Side

Bottom Side

EC_ON<37>

2

ON/OFFBTN#

EC_ON

SW1

1 2

3

4

5

6

R587

R587 10K_0402_5%

10K_0402_5%

SMT1-05_4P

D26

1

DAN202UT106_SC70-3

3

2

2N7002_SOT23-3

2

Q44

G

+3VALW

1 2

13

D

S

R584

R584 100K_0402_5%

100K_0402_5%

2

1

ON/OFF#

51_ON#

C741

C741 1000P_0402_50V7K

1000P_0402_50V7K @

@

ON/OFF# <37>

51_ON# <43>

12

D27

D27 RLZTE1120A LL34

RLZTE1120A LL34 @

@

EMI REQUEST 1ST = SCA00000E00

2ST = SCA00000R00

1

BTN FUNCTION

MUTE BTN

DOWN

UP

IDEAPAD BOARD 2PIN

R769

+5VS

1 2

100_0603_5%

KEY MATRIX

IN KSO17 KSO17 KSO16

ACES_87213-0200

4

G2

3

G1

2

1

JP26

1

OUT KSI3 KSI2 KSI2

Slide Board Conn. 10 pin

+3VALW

JP24

R589

R589 100K_0402_5%

100K_0402_5%

D28

NOVO#<37>

51_ON#<43>

NOVO#

51_ON#

1 2

D28

2

3

DAN202UT106_SC70-3

1

NOVO_BTN#

Security Classification

2008/03/25 2008/04/

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS TH E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/03/25 2008/04/

DRIVE_LED#<13>

BT_LED#<40>

WLAN_LED#<30>

3G_LED#<30>

Compal Secret Data

Deciphered Date

DRIVE_LED# BT_LED# WLAN_LED# 3G_LED#

+5VS

I2C_INT<37>

SMB_EC_DA2_R<14,19> SMB_EC_CK2_R<14,19>

R631 0_0402_5%R631 0_0402_5%

R586 0_0402_5%

R586 0_0402_5% R585 0_0402_5%

R585 0_0402_5%

R773470_0402_5% R773470_0402_5%

12

R774470_0402_5% R774470_0402_5%

12

R775470_0402_5% R775470_0402_5%

12

R776470_0402_5% R776470_0402_5%

12

1 2

1 2 1 2

Compal Electronics,Ltd.

Title

Audio Jack & SW connector

Size Document Number Rev

Custom

Date: Sheet of

I2C_INT_R

R_SMB_DA2 R_SMB_CK2

NIWBA_LA5371P

JP24

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1005N

0.1

41 52Tuesday, March 24, 2009

A

B

C

D

E

+

3VALW TO +3VS+5VALW TO +5VS

+

5VALW

U

35

8

D

1

742

C

C 10U_0805_10V4Z

1 1

2

G

2 2

2

B+

R593

R593 20K_0402_5%

20K_0402_5%

13

D

S

10U_0805_10V4Z

Q49

Q49 2N7002_SOT23

2N7002_SOT23

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

R598

R598 0_0402_5%

0_0402_5%

@

1 2

12

R602

R602 470_0603_5%

470_0603_5% @

@

13

D

2

G

Q53

S

2N7002_SOT23

2N7002_SOT23 @

@

+

5VS

1

S

2 3 4

1

743

C

C 10U_0805_10V4Z

10U_0805_10V4Z

2

S S

G

1

744

C

C 1U_0603_10V4Z

1U_0603_10V4Z

2

12

R590

R590 470_0603_5%

470_0603_5%

13

D

S

SUSP

2

G

Q46

Q46 2N7002_SOT23

2N7002_SOT23

1

C751

0.1U_0603_25V7K

2

+1.5V +VCCP+1.8VS +0.75VS

12

R603

R603 470_0603_5%

470_0603_5%

13

D

S

SYSON# SUSP SUSPSUSP

2

G

Q54

Q54 2N7002_SOT23

2N7002_SOT23

12

R604

R604 470_0603_5%

470_0603_5%

13

D

S

2

G

Q55

Q55 2N7002_SOT23

2N7002_SOT23

SUSP

12

R605

R605 470_0603_5%

470_0603_5%

13

D

S

2

G

2

G

Q56

Q56 2N7002_SOT23

2N7002_SOT23

1

2

B+

12

13

D

S

+

3VALW

745

C

C 10U_0805_10V4Z

10U_0805_10V4Z

R594

R594 47K_0402_5%

47K_0402_5%

SI4800BDY-T1-E3_SO8

Q50

Q50 2N7002_SOT23

2N7002_SOT23

8 7 6 5

U

36

D D D D

R599

R599 0_0402_5%

0_0402_5%

1 2

+1.05VS

S S S

G

@

12

R1181

R1181 470_0603_5%

470_0603_5%

13

D

S

+

3VS

1 2

1

3

C

4

10U_0805_10V4Z

2

1

C752

0.1U_0603_25V7K

2

SUSP

2

G

Q69

Q69 2N7002_SOT23

2N7002_SOT23

746

1

747

C

C 1U_0603_10V4Z

1U_0603_10V4Z

2

B+ B+

DGPU_PWR_EN#<16> DGPU_PWR_EN#<16>

D

S

+3VS

1 2

12

R591

R591 470_0603_5%

470_0603_5%

13

SUSP

2

G

Q47

Q47 2N7002_SOT23

2N7002_SOT23

2

8 7 6 5

SI4800BDY-T1-E3_SO8

R595

HYBRID@

47K_0402_5%

DGPU_PWR_EN#

PJ507

2

JUMP_43X79

@

U53

D D D D

2N7002_SOT23

+

1.5V to +1.5VS

SUSPSUSP

2N7002_SOT23

1

HYBRID@U53

HYBRID@

1

S

2

S

3

S

4

G

HYBRID@

2

G

Q80

1.5V

+

1

754

C

C 10U_0805_10V4Z

10U_0805_10V4Z

2

B+

R606

R606 150K_0402_5%

150K_0402_5%

Q57

13

D

2

G

S

+3VS_D +1.5VS_D

13

D

S

1

C765

C765 HYBRID@

HYBRID@

2

0.1U_0603_25V7K

R608

R608 0_0402_5%

0_0402_5%

1 2

@

38

U

8

D

7

D

6

D

5

D

SI4800BDY-T1-E3_SO8

1.5VS_GATE5VS_GATE

1

2

0.1U_0603_25V7K

C757

C757 @

@

+1.5VS

1.5VS

+

1

S

2

S

3

S

4

G

1

755

C

C 10U_0805_10V4Z

10U_0805_10V4Z

2

1

C758

0.1U_0603_25V7K

2

8 7 6 5

R596

1 2

HYBRID@

DGPU_PWR_EN#

1

756

C

C 1U_0603_10V4Z

1U_0603_10V4Z

2

PJ508

2

JUMP_43X79

@

U48

D D D D

SI4800BDY-T1-E3_SO8

47K_0402_5%

1

2

HYBRID@

S S S

G

HYBRID@

2N7002_SOT23

1

1 2 3 4

2

G

Q79

13

D

S

12

R

601

470_0603_5%

13

D

S

SUSP

2

G

Q52

Q52 2N7002_SOT23

2N7002_SOT23

1

C766

C766 HYBRID@

HYBRID@

2

0.1U_0603_25V7K

3 3

+5VALWRTCVREF

Q58

12

@

@ R610

R610 100K_0402_5%

100K_0402_5%

1

100K_0402_5%

SYSON#

DTC124EKAT146_SC59-3

12

R609

R609 10K_0402_5%

10K_0402_5%

SUSP<47,48>

SUSP

DTC124EKAT146_SC59-3

OUT

SUSP#<16,30,37,47,49> SYSON<30,37,47>

2

IN

SYSON

GND

3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EX CEPT AS AU THORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EX CEPT AS AU THORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EX CEPT AS AU THORIZED BY COMPA L ELECTRONICS , INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

+5VALW

12

R611

Q59

1

B+

OUT

2

IN

DGPU_PWR_EN#<16>

GND

3

2006/08/18 2007/8/18

C

+1.05VS

PJ510

2

JUMP_43X79

@

U72

8 7 6 5

SI4800BDY-T1-E3_SO8

R600

1 2

HYBRID@

Compal Secret Data

Deciphered Date

47K_0402_5%

DGPU_PWR_EN#

1

2

HYBRID@U72

HYBRID@

S

D

S

D

S

D

G

D

HYBRID@

2N7002_SOT23

1 2 3 4

2

G

Q82

13

D

S

D

+1.05VS_D

1

C768

C768 HYBRID@

HYBRID@

2

0.1U_0603_25V7K

B+

DGPU_PWR_EN#<16>

Title

Size Document Number Rev

Date: Sheet of

+1.8VS +1.8VS_D

PJ509

Custom

PJ509

2

JUMP_43X79

@

U70

8 7 6 5

SI4800BDY-T1-E3_SO8

R597

1 2

HYBRID@

47K_0402_5%

DGPU_PWR_EN#

Compal Electronics, Inc.

DC Interface

NIWBA_LA5371P

1

2

HYBRID@U70

HYBRID@

S

D

S

D

S

D

G

D

HYBRID@

2N7002_SOT23

1

1 2 3 4

2

E

G

Q81

13

D

S

0.1U_0603_25V7K

42 52Tuesday, March 24, 2009

1

C767

C767 HYBRID@

HYBRID@

2

0.1

A

B

C

D

1 1

2 2

DC030006J00

JDCIN

JDCIN 4602-Q04C-09R 4P P2.5@

4602-Q04C-09R 4P P2.5@

APDIN APDIN1

1

2

3

4

PF101

7A_24VDC_429007.WRML

21

PL101

SMB3025500YA_2P

1 2

12

0.1U_0603_25V7K

PC112

12

100P_0402_50V8J

PC101

1000P_0402_50V7K

100P_0402_50V8J

PC102

12

PC113

0.1U_0603_25V7K

VIN

VINDE-2

VIN

12

PR103

12

100P_0402_50V8J

PC103

PC104

1000P_0402_50V7K

VINDE-1

12

PC106

1000P_0603_50V7K

PR103

82.5K_0402_1%

12

PR107

24.9K_0402_1%

PR106

PR106 215K_0402_1%

215K_0402_1%

1 2

12

VINDE-3

PC107

0.1U_0402_16V7K

PR102

PR102 1M_0402_1%

1M_0402_1%

1 2

VS

8

3

P

+

2

-

G

4

PR109

PR109 10K_0402_5%

10K_0402_5%

12

1

O

PU102A

PU102A LM393DG_SO8

LM393DG_SO8

12

RTCVREF

PC105

0.01U_0402_25V7K

3.3V

VIN

12

PR105

12

PR108

PR105 10K_0402_1%

10K_0402_1%

1 2

PACIN

10K_0402_5%

ACIN <37,45>

PACIN

PR104

10K_0805_5%

12

PD102

RLZ4.3B_LL34

Vin Detector

High 18.135 17.566 17.011 Low 14.866 14.355 14.063

VIN

PD103

LL4148_LL34-2

PD101

LL4148_LL34-2

BATT+

LL4148_LL34-2

200_0603_5%

PR116

200_0603_5%

1 2

100K_0402_1%

22K_0402_1%

RTCVREF

51_ON#<41>

CHGRTCP

560_0603_5%

1 2

3 3

RTC Battery

JRTC

- +

12

PD104

MAXEL_ML1220T10@

PD104

1 2

RB751V-40TE17_SOD323-2

+RTCBATT

+CHGRTC

PR115

560_0603_5%

1 2

SP093MX0000

12

PR101

PR112

PR113

1 2

3.3V

12

PC110

PC110 10U_0603_6.3V6M

10U_0603_6.3V6M

51ON-2

12

PC108

1 2

PU101

G920AT24U_SOT89-3

3

OUT

GND

1

PQ101

TP0610K-T1-E3_SOT23-3

0.22U_0603_25V7K

0.22U_0603_25V7K 51ON-3

PQ101

12

PR114

PR114 200_0603_5%

200_0603_5%

CHGRTCINRTCVREF-1

2

IN

12

PC111

PC111 1U_0805_25V6K

1U_0805_25V6K

2

68_1206_5%

PR110

13

1 2

51ON-1

12

PR111

PR111 68_1206_5%

68_1206_5%

12

PC109

0.1U_0603_25V7K

VS

4 4

Security Classification

2009/01/06 2010/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2010/01/06

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DCIN & DETECTOR

43 52Tuesday, March 24, 2009

D

43 52Tuesday, March 24, 2009

0.1

A

1 1

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C

VMB2

JBATT

2 2

TYCO_1775768-1@

3 3

GND GND

1

2

EC_SMCA

3

EC_SMDA

4

5

6

7

8 9

12

100_0402_1%

PR204

100_0402_1%

PR206

PR209

6.49K_0402_1%

PR211

PR211 10K_0402_5%

10K_0402_5%

PF2

PF2 12A_65V_451012MRL

12A_65V_451012MRL

1 2

21

VMB

SMB3025500YA_2P

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <37>

EC_SMB_DA1 <37>

+3VALW

BATT_TEMP <37>

BATT_SEL_HW <45>

PL201

1 2

A/D

BATT+

12

PC202

0.01U_0402_25V7K

0.01U_0402_25V7K 100K_0603_1%_TH11-4H104FT

100K_0603_1%_TH11-4H104FT

Recovery at 56 degree C

VL

12

PH201

47K_0402_1%

TM-2

PR205

13.7K_0402_1%

12

13.7K_0402_1%

1 2

PR207

15.4K_0402_1%

TM_REF1

12

PC204

12

1000P_0402_50V7K

TM-1

12

PC203

0.22U_0603_25V7K

PR203

1 2

8

5

P

+

6

-

G

4

PR208

PR208 100K_0402_5%

100K_0402_5%

PR210

PR210 100K_0402_5%

100K_0402_5%

7

O

PU102B

LM393DG_SO8

12

VL

PR202

PR202 47K_0402_1%

47K_0402_1%

1 2

TM-3

MAINPWON <46>

13

D

PQ201

2

G

PQ201 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

2010/01/062009/01/06

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

44 52Tuesday, March 24, 2009

D

44 52Tuesday, March 24, 2009

0.1

A

P

Q301

FDS6675BZ_SO8

1 2

8 7

5

12

PD302

PD302 RLZ24B_LL34

RLZ24B_LL34

PR306

PR306 340K_0402_1%

340K_0402_1%

1 2

PR310

54.9K_0402_1%

1 2

V

IN

P

R301

3.3_1210_5%

1 1

3.3_1210_5%

2.2U_0805_25V6K

PR305

PC311

BK-1 BK-2

1 2

1 2 12

1 2

PC301

0.01U_0402_25V7K

@

PR309

340K_0402_1%

1 2 36

4

1 2

24751_VREF ACSET

P

Q302

FDS6675BZ_SO8

1 2 3 6

4

12

PC306

0.01U_0402_25V7K

100K_0402_5%

PR304

@

1 2

PR339

PR339 150_0805_5%

150_0805_5%

PR311

75K_0402_1%

1 2

PC315

0.01U_0402_25V7K@

PC315

PC308

0.1U_0603_25V7K

12

CP setting

PR314

54.9K_0402_1%

24751_VREF

PR320

PR323

12

54.9K_0402_1%

12

5

12

1

0

OVP-3

1 2

PR316

100K_0402_5%

1 2

24751_VREF

12

PR318

PR318 200K_0402_1%

200K_0402_1%

24751_OCP-2

34

PQ307B

PQ307B 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

VS

12

PC329

0.01U_0402_25V7K

8

P

+

-

G

PU302A

4

LM358DR_SO8

0.01U_0402_25V7K

OVP-2

3

2

AO3413_SOT23-3

2

ACSET

24751_OCP-3

61

PQ307A

2

2N7002KDW-2N_SOT363-6

VMB2

12

PR327

OVP-1

340K_0402_1%

12

PR329

499K_0402_1%

12

PR331

105K_0402_1%

PQ306

1 2

0.1U_0603_25V7K

12

24751_VREF

1 3

PC324

CHGVADJ<37>

PC330

0.01U_0402_25V7K

12

LI-3S :13.5V----BATT-OVP=1.5V BATT-OVP=0.1112*BATT+

7

0

OVP-4

2 2

CP Point Setting

90W adapter Vacset=3.3*(127K/(75K+127K))=2.075V CP Point=(Vacset/Vvdac)*(0.1/PR302)=4.19A

65W adapter Vacset=3.3*(115K/(150K+115K))=1.432V CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.89A

Input OVP : 22.3V

ACIN detect : 17.26V

Fsw : 300KHz

100K_0402_5%

3 3

ACOFF 24751_OCP-1

BATT_OVP<37>

1 2

PC326

0.1U_0402_16V7K

340K_0402_1%

PR330

PR330 10K_0402_5%

10K_0402_5%

A/D

4 4

A

8 7

B

5

12

PR313

PC322

+EC_AVCC

1U_0603_10V6K

210K_0402_1%

8

P

G

4

B

P

R302

0.015_1206_1%

+_IN

1

2

PC307

0.1U_0402_16V7K

1 2

PR336

PR336 0_0402_5%

0_0402_5%

24751_ACGOOD#

PR326

5

6

-

B

1 2

24751_OVPSET

1 2

REGN

127K_0402_1%

1 2

+

PU302B

PU302B LM358DR_SO8

LM358DR_SO8

4

3

CHGEN#

12

PC309

24751_ACN

@

24751_ACP

24751_ACDRV#

ACDET

24751_ACOP

PC317

0.47U_0603_16V7K

PR337

PR337 0_0402_5%@

0_0402_5%@

12

24751_VDAC

VADJ

/BATDRV

12

PR324

PR324 0_0402_5%@

0_0402_5%@

VADJ

12

PR328

C

4751_PVCC

2

B

+

P

J301

PU301

1

CHGEN

0.1U_0603_25V7K

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

PVCC

BTST

HIDRV

REGN

LODRV

PGND

LEARN

CELLS

SRP

SRN

BAT

SRSET

IADAPT

28

27

26

25

PH

24

23

22

21

20

19

18

17

29

TP

16

15

100P_0402_50V8J

PC310

PC310 1U_0805_25V6K

1U_0805_25V6K

24751_BTST-1

PR307

2.2_0603_5%

24751_HIDRV

24751_PH

REGN

12

PC316

PC316 1U_0603_10V6K

1U_0603_10V6K

24751_LODRV

ACOFF

CELLS

24751_SRP

24751_SRN

12

SRSET

IADAPT

1 2

PR321

10_0402_5%

1 2

24751_BTST

12

PD301

LL4148_LL34-2

ACOFF <37>

12

PR334

PR334 0_0402_5%

0_0402_5%

PC323

0.1U_0603_25V7K

12

PC327

J301

2

112

JUMP_43X118@

1 2

PC312

0.1U_0603_25V7K

24751_VREF

1 2

BATT_SEL-1

49.9K_0402_1%@

PR315

61

2

PQ310A

PQ310A 2N7002KDW-2N_SOT363-6@

2N7002KDW-2N_SOT363-6@

ICHG setting

12

PR322

PR322 180K_0402_1%

180K_0402_1%

ADP_I <37>

C

HG_B+CHG_B+

1 2

PC303

PQ303

PQ303 SIS412DN-T1-GE3_PAK1212-8

SIS412DN-T1-GE3_PAK1212-8

3 5

241

10U_LF919AS-100M-P3_4.5A_20%

12

PQ305

3 5

241

PR338

49.9K_0402_1%@

1 2

34

PQ310B

PQ310B 2N7002KDW-2N_SOT363-6@

2N7002KDW-2N_SOT363-6@

BAT_SEL

5

PR319

54.9K_0402_1%

12

PC325

0.01U_0402_25V7K

@

12

SI7716ADN-T1-GE3_PAK1212-8

PR332

PR332 0_0402_5%@

0_0402_5%@

PR333 0_0402_5%@PR333 0_0402_5%@

12

IREF Current

1 2

PC304

4.7U_0805_25V6-K

PL302

1 2

PR312

4.7_1206_5%@

24751_SNB

PC318

PC318 820P_0603_50V7K@

820P_0603_50V7K@

12

IREF <37>

4.7U_0805_25V6-K

2.842V 3.3A

CHGVADJ Pre Cell

12

3.3V 4.35V

PC328

499K_0402_1%

1000P_0402_50V7K

0V 4V

"CHGVADJ" connect to EC DA pin

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2010/01/062009/01/06

1 2

PC305

0.01U_0402_25V7K

4.7U_0805_25V6-K

/BATDRV

12

PC331

10U_1206_25V6M

12

24751_SW-1

BATT_SEL_HW <44>

BATT_SEL_EC <37>

D

12

P

C302

1 2

PR308

0.02_1206_1%

1

2

PC319

0.1U_0402_16V7K

1 2

PC320

0.1U_0603_25V7K

RTCVREF

PR317

24751_ACGOOD#

FSTCHG<37>

Title

Size Document Number Rev

Date: Sheet of

P

R303

100K_0402_5%

4

3

12

@

12

100K_0402_5%

Compal Electronics, Inc.

CHARGER

36

241

578

12

PC313

PC321

0.1U_0603_25V7K

24751_VREF

12

PR335

100K_0402_5%

@

13

D

2

G

S

24751_VREF

PR325

PR325 100K_0402_5%

100K_0402_5%

1 2

13

D

PQ309

S

D

PQ309 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

2

G

PQ304

PQ304 FDS6675BZ_SO8

FDS6675BZ_SO8

12

10U_1206_25V6M

PQ311

PQ311 SSM3K7002FU_SC70-3@

SSM3K7002FU_SC70-3@

CHGEN#

BATT+

PC314

10U_1206_25V6M@

ACIN <37,43>

45 52Tuesday, March 24, 2009

0.1

5

B

+

P

J401

JUMP_43X118@

2

112

4

SL6237_B+

I

P

R401

0_0402_5%

1 2

3

2

I

SL6237_B+

1

D D

12

PC405

330P_0402_50V7K

4.7UH_PCMC063T-4R7MN_5.5A_20%

+3VALWP

1

+

PC421

220U_6.3VM_R15

C C

B B

2

VS

PR406

1 2

PR408

1 2

0_0402_5%

10K_0402_1%

@

RLZ5.1B_LL34

12

PC423

0.1U_0402_25V6

1 2

PD402

1 2

PL401

330P_0402_50V7K

12

PC401

10U_1206_25V6M

PR402

4.7_1206_5%

PC414

RB751V-40TE17_SOD323-2

1 2

EN_LDO-1

RB751V-40TE17_SOD323-2@

1 2

MAINPWON <44>

PD401

PD403

PC403

3V_SNB

12

2200P_0402_50V7K

100K_0402_1%

1 2

PR418

0_0402_5%

PQ401

PQ401 SIS412DN-T1-GE3_PAK1212-8

SIS412DN-T1-GE3_PAK1212-8

3 5

241

3 5

241

PQ403

PQ403 SI7716ADN-T1-GE3_PAK1212-8

SI7716ADN-T1-GE3_PAK1212-8

PR412

PR413

1 2

200K_0402_1%

12

BST3A-1

PC411

0.1U_0603_25V7K

1 2

PC417

0.22U_0603_25V7K

1 2

VL

PR417

1 2

806K_0603_1%

12

PR403

2.2_0603_5%

2VREF_ISL6237

0.22U_0603_25V7K

PR419

47K_0402_1%@

1 2

PC419

0.1U_0603_25V7K

UG3

BST3A

12

SW3

LG3

FB3

VL

1 2

PC416

EN_LDO

3/5V_EN1

3/5V_EN2

12

PC420

PC407

PR416

PR416 0_0402_5%

0_0402_5%

1 2

2VREF_ISL6237

33

26

24

25

23

30

32

1

8

20

4

14

27

1 2

TP

UGATE2

BOOT2

PHASE2

LGATE2

OUT2

REFIN2

REF

LDOREFIN

NC

EN_LDO

EN1

EN2

PC418

1U_0603_10V6K

3/5V_VIN

3/5V_NC

12

VL

PC404

10U_1206_25V6M

1 2

PC408

1U_0603_10V6K

3/5V_VCC

3

6

VIN

VCC

TON

NC

2

5

12

3/5V_TON

12

PR420

PR420 0_0402_5%

0_0402_5%

12

PC409

7

LDO

PVCC

UGATE1

BOOT1

PHASE1

LGATE1

PGND

OUT1

POK2

POK1

ILIM1

ILIM2

GND

21

4.7U_0805_6.3V6K

19

15

17

16

18

22

10

11

FB1

9

BYP

29

SKIP

28

13

12

31

PU401

PU401 ISL6237IRZ-T_QFN32_5X5

ISL6237IRZ-T_QFN32_5X5

PC410

1U_0603_10V6K

1 2

HG5

BST5A

PR405

2.2_0603_5%

SW5

LG5

FB5

5V_SKIP

ILM1

ILIM2

BST5A-1

12

PC412

0.1U_0603_25V7K

PR410

PR410 0_0402_5%@

0_0402_5%@

1 2

PR411

PR411 0_0402_5%

0_0402_5%

PR421

PR421 0_0402_5%@

0_0402_5%@

12

PR414

PR414 301K_0402_1%

301K_0402_1%

PR415

PR415 301K_0402_1%

301K_0402_1%

1 2

2VREF_ISL6237

12

PQ402

PQ402 SIS412DN-T1-GE3_PAK1212-8

SIS412DN-T1-GE3_PAK1212-8

3 5

241

3 5

241

PQ404

PQ404 SI7716ADN-T1-GE3_PAK1212-8

SI7716ADN-T1-GE3_PAK1212-8

VL

+3VALWP +3VALW

10U_1206_25V6M

4.7UH_PCMC063T-4R7MN_5.5A_20%

12

PR404

4.7_1206_5%

5V_SNB

12

PC415

330P_0402_50V7K

PL402

PJ402

2

JUMP_43X118@

12

PC406

2200P_0402_50V7K

12

112

12

PC422

0.1U_0402_25V6

+5VALWP

1

+

PC413

2

220U_6.3VM_R15

PR407

61.9K_0402_1%@

1 2

PR409

1 2

0_0402_5%

0.047U_0402_16V7K

A A

5

4

0.047U_0402_16V7K

@

2VREF_ISL6237

Security Classification

2009/01/06 2010/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/06 2010/01/06

Compal Secret Data

Deciphered Date

2

PJ403

+5VALWP +5VALW

2

112

JUMP_43X118@

Compal Electronics, Inc.

Title

3VALW/5VALW

Size Document Number Rev

Tuesday, March 24, 2009

Date: Sheet of

Tuesday, March 24, 2009

0.1Custom

46 52

1

46 52

5

D D

SYSON<30,37,42>

+5VALW

PR518

0_0402_5%

1 2

PR521

422_0603_1%

1 2

PC529

1U_0603_10V6K

4

12

PC526

0.1U_0402_16V7K

@

12

47P_0402_50V8J@

31.6K_0402_1%

PC530

1 2

PR523

1 2

1.5V_V5FILT

1.5V_FB

1 2

PR533

PR533 100K_0402_1%

100K_0402_1%

1.5V_TON

1.5V_EN

12

PC543

0.1U_0402_16V7K

@

2

3

4

5

6

TON

VOUT

V5FILT

VFB

PGOOD

1.5V_PGOOD

R501

P

240K_0402_1%

1 2

1

15

TP

EN_PSV

GND7PGND

8

3

BST_1.5V BST_1.5V-1

1 2

PR519

2.2_0603_5%

PC525

0.1U_0603_25V7K

14

13

12

11

PR117

PR117 10K_0402_1%

10K_0402_1%

10

9

UG_1.5V

1.5V_TRIP

SW_1.5V

1 2

LG_1.5V

VBST

DRVH

LL

TRIP

V5DRV

DRVL

PU501

PU501 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

1 2

+5VALW

12

PC531

4.7U_0805_6.3V6K

4

578

3 6

241

786

5

123

2

1

.5V_IN

12

PC501

10U_1206_25V6M

PQ501

PQ501 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

PL502

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

12

PR520

4.7_1206_5%@

1.5V_SNB

12

PQ506

PC532

SI4634DY-T1-E3_SO8

470P_0402_50V7K@

1

P

J501

2

112

JUMP_43X79@

12

PC502

10U_1206_25V6M

12

PC550

PC549

PC550

0.1U_0402_25V6

2200P_0402_50V7K

+1.5VP

1

+

PC527

2

220U_6.3VM_R15

12

PC528

10U_0603_6.3V6M

12

PC544

330P_0402_50V7K@

+

B

PC545

470P_0402_50V7K@

12

C C

PR526

100K_0402_1%

1 2

SUSP#<16,30,37,42,49>

+5VS

B B

PR529

422_0603_1%

1 2

PC539

1U_0603_10V6K

PR524

30.1K_0402_1%

12

PC536

0.22U_0402_6.3V6K

12

47P_0402_50V8J

@

13.7K_0402_1%

1 2

PC540

1 2

PR531

+3VS

1 2

VCCP_TON

VCCP_EN

VCCP_V5FILT

VCCP_FB

PR535

PR535 100K_0402_1%

100K_0402_1%

PR525

240K_0402_1%

1 2

1

15

TP

2

TON

3

4

5

6

EN_PSV

VOUT

V5FILT

VFB

PGOOD

GND7PGND

DGPU_PWROK <16,49>

PR527

2.2_0603_5%

BST_VCCP BST_VCCP-1

2.2_0603_5%

1 2

0.1U_0603_25V7K

14

VBST

DRVH

LL

TRIP

V5DRV

DRVL

8

PU503

PU503 TPS51117RGYR_QFN14_3.5x3.5

TPS51117RGYR_QFN14_3.5x3.5

UG_VCCP

13

SW_VCCP

12

VCCP_TRIP

1 2

11

PR530

23.7K_0402_1%

10

LG_VCCP

9

PC535

1 2

+5VS

12

PC541

4.7U_0805_6.3V6K

VCCP_IN

12

PC534

PQ507

3 5

241

SIS412DN-T1-GE3_PAK1212-8

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR528

4.7_1206_5%

VCCP_SNB

12

PC542

3 5

241

PC542 680P_0402_50V7K

680P_0402_50V7K

PQ508

PQ508 SI7716ADN-T1-GE3_PAK1212-8

SI7716ADN-T1-GE3_PAK1212-8

12

PC551

10U_1206_25V6M

PL501

1 2

PJ506

2

112

JUMP_43X79

@

PC547

680P_0402_50V7K@

+1.05VSP

PC538

10U_0603_6.3V6M

12

PC546

220P_0402_50V7K@

12

PC552

0.1U_0402_25V6

2200P_0402_50V7K

1

2

12

+

PC537

220U_6.3VM_R15

B+

12

PC548

820P_0603_50V7K@

12

PR532

+1.5V

PR532

31.6K_0402_1%

1

PJ502

1

JUMP_43X79@

2

PU502

2

PC519

4.7U_0805_6.3V6K

A A

PR534

PR534 0_0402_5%

0_0402_5%

SUSP<42,48>

1 2

0.1U_0402_16V7K@

5

PC522

PC519

0.75V_EN

12

13

D

2

G

PQ505

S

SSM3K7002FU_SC70-3

PR515

1K_0402_1%

PR517

1K_0402_1%

0.75V_IN

12

0.75V_REF

12

PC521

0.1U_0402_16V7K

12

PU502

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

+0.75VSP

12

PC523

PC523 10U_0603_6.3V6M

10U_0603_6.3V6M

4

NC

6

5

7

8

9

TP

+3VALW

12

PC520

PC520 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VSP +1.05VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2

PJ503

2

JUMP_43X118@

2010/01/062009/01/06

1

Title

Size Document Number Rev

Date: Sheet of

+1.5VP +1.5V

Compal Electronics, Inc.

1.5V/VCCP/0.75V

2

PJ504

JUMP_43X118@

PJ505

JUMP_43X79@

112

47 52Tuesday, March 24, 2009

1

47 52Tuesday, March 24, 2009

+0.75VS+0.75VSP

0.1

5

4

3

2

1

1 2

P

R637

10K_0402_5%@

U

B

D D

+VGA_PVCC

VGA_EN<16>

C C

GPU_VID1<19>

PR629

10K_0402_5%

PR630

12

10K_0402_1%

1 2

PR635

PR635 1_0402_5%

1_0402_5%

+5VS

PR610

PR610 0_0402_5%

0_0402_5%

GVID1-1

2

12

PC625

0.022U_0402_16V7K

+VGA_VCC

12

PC636

2.2U_0603_6.3V6K

PR616

0_0402_5%

1 2

PR636

PR636 0_0402_5%@

0_0402_5%@

1 2

GVID1-2

61

VGA_EN

PC613

0.1U_0402_16V7K@

PR620

8.2K_0402_1%

1 2

PQ606A

PQ606A 2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

1 2

GVID0-2

34

VGA_FCCM

12

22P_0402_50V8J

PR618

PR618 127K_0402_1%

127K_0402_1%

1

2

3

4

PC638

VIN

VCC

FCCM

EN

16

17

GND

PGOOD

PU601

PU601 ISL6269CRZ-T_QFN16

ISL6269CRZ-T_QFN16

COMP

5

COMP_VGA

12

90.9K_0402_1%

PR633

1 2

COMP_VGA-1

12

PC639

PC639 6800P_0402_25V7K

6800P_0402_25V7K

15UG14

PHASE

FB

6

FSET_VGA

12

VGA_FB

PC637

12

PR619

4.32K_0402_1%

FSET

7

1 2

0.01U_0402_25V7K

12

PR634

2.37K_0402_1%

13

BOOT

VO

8

42.2K_0402_1%

PR609

G_VGA

ST_VGA

1 2

PR611

2.2_0603_5%

12

PVCC

11

LG

10

PGND

9

ISEN

+

3VS

B

ST_VGA-1

1 2

PC614

0.1U_0603_25V7K

+VGA_PVCC

1 2

PR613

2.2_0603_5%@

PC640

1 2

2.2U_0603_6.3V6K

ISEN_VGA

PR614

6.81K_0402_1%

NB10M-GE

(Remove PR620)

NB10P-GE

J605

P

V

GA_IN

12

PC611

10U_1206_25V6M

PQ603

PQ603 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

3 5

241

SW_VGA

+5VS +VGA_COREP

786

5

12

4

LG_VGA

PQ604

123

10U_1206_25V6M

786

5

4

SI4634DY-T1-E3_SO8

P

2

112

JUMP_43X79@

PC612

10U_1206_25V6M

0.88UH_PCMB103E-R88MS_20A_20%

12

VGA_SNB

12

PQ605

123

SI4634DY-T1-E3_SO8

12

PL602

1 2

PR612

4.7_1206_5%

PC618

680P_0402_50V7K

B

+

PC617

330P_0402_50V7K@

1

12

+

2

0_0402_5%

PR615

PR615 @

@

1

+

2

PC615

330U_D2_2.5VY_R9M

+VGASENSE <21>

PC619

330U_D2_2.5VY_R9M

12

PC616

10U_0603_6.3V6M

12

PC633

PC634

10U_0603_6.3V6M

+VGA_COREP +VGA_CORE

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

0 1

0 0

0.92V

GPIO6 GPIO5

GPU_VID1 GPU_VID0 VGA_CORE

0 1

0

0.9V0

1.1V

PJ602

2

112

JUMP_43X118@

PJ603

2

112

JUMP_43X118@

PJ606

JUMP_43X39@

112

2

+1.8VS+1.8VSP

GVID0-1

GPU_VID0<19>

PR621

10K_0402_5%

B B

A A

PR624

12

10K_0402_1%

12

PQ606B

5

2N7002KDW-2N_SOT363-6

PC632

0.022U_0402_16V7K

+3VS

1

PJ607

PJ607 JUMP_43X39@

JUMP_43X39@

PC623

4.7U_0805_6.3V6K

PR632

100K_0402_1%

SUSP<42,47>

1 2

PC631

0.1U_0402_16V7K

PC631

PC623

LDO_1.8V_EN

12

1

2

12

13

D

2

G

S

PQ609

PQ609 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR623

1K_0402_1%

PR628

1.24K_0402_1%

LDO_1.8V_IN

12

LDO_1.8V_REF

12

PC627

0.1U_0402_16V7K

PU603

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

+1.8VSP

12

PC629

PC629 10U_0603_6.3V6M

10U_0603_6.3V6M

NC

6

5

7

8

9

TP

12

PC624

PC624 1U_0402_6.3V6K

1U_0402_6.3V6K

+5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2010/01/062009/01/06

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

VGA_CORE/1.8VS/1.1VS

48 52Tuesday, March 24, 2009

1

48 52Tuesday, March 24, 2009

0.1

5

D D

PJ701

B+

2

JUMP_43X118@

1

2

VTT_B+

4

+1.1V_VCCPP

3

2

1

12

PC701

PR712

0_0402_5%@

C C

B B

SUSP#<16,30,37,42,47>

DGPU_PWROK<16,47>

VTT_SELECT<8>

1 2

PR710

0_0402_5%

1 2

12

PC702

10U_1206_25V6M

VCCP_POK<5>

1 2

PR427

35.7K_0402_1%

12

0.1U_0402_16V7K@

VTT_VCC

12

PC705

2.2U_0603_6.3V6K

VTT_EN-1

PC706

PC709

0_0402_5%

1 2

VTT_COMP

12

22P_0402_50V8J

PR701

3

VIN

4

VCC

5

EN

PC711

6800P_0402_25V7K

VFB=0.6V

12

1.1VS_PGOOD

2

8

GND

PGOOD

PU701

PU701 ISL6268CAZ-T_SSOP16

ISL6268CAZ-T_SSOP16

COMP

FB

6

7

12

VTT_FB

PR713

49.9K_0402_1%

VTT_COMP-1

12

H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V

SW_VTT

UG_VTT

PR702

115K_0402_1%

@

1

16

UG

PHASE

FSET

9

VTT_FSET

12

PR714

57.6K_0402_1%

PR719

1.96K_0402_1%

VTT_BOOT

15

BOOT

PVCC

LG

PGND

ISEN

VO

10

12

PC710

0.01U_0402_25V7K

1 2

PR716

1.58K_0402_1%

PR704

1 2

0_0603_5%

+5VS

12

VTT_PVCC

14

2.2U_0603_6.3V6K

LG_VTT

13

12

VTT_ISEN

11

VTT_BOOT-1

PR706

PR706 0_0603_5%

0_0603_5%

PR707

4.7_0603_5%

1 2

PC704

1 2

2.2K_0402_1%

VTT_FB-1

PR711

1 2

PC703

0.1U_0603_25V7K

VTT_VCC

Rds=4.0mΩ

PQ701

PQ701 SI7686DP-T1-E3_SO8

SI7686DP-T1-E3_SO8

3 5

241

PL701

0.88UH_PCMB103E-R88MS_20A_20%

786

5

4

PQ702

123

SI4634DY-T1-E3_SO8

786

5

4

123

12

VTT_SNB

12

PQ703

SI4634DY-T1-E3_SO8

PL701

1 2

PR709

4.7_1206_5%@

PC707

PC707 680P_0402_50V7K@

680P_0402_50V7K@

PR724

PR724 10_0402_5%

10_0402_5%

1 2

1

+

2

PR725

PR725 0_0402_5%

0_0402_5%

+1.1V_VCCPP

1

+

2

PC714

PC708

330U_D2E_2.5VM

12

PC714

330U_D2E_2.5VM

VTT_SENSE <8>

PJ702

+1.1V_VCCPP +VCCP

A A

Security Classification

2009/01/06 2010/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2009/01/06 2010/01/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

2

112

JUMP_43X118@

PJ703

2

112

JUMP_43X118@

Compal Electronics, Inc.

+1.1VS_VTT

49 52Tuesday, March 24, 2009

1

49 52Tuesday, March 24, 2009

0.1

5

D D

PL801

SMB3025500YA_2P

1 2

PC810

PC810 1000P_0402_50V7K

1000P_0402_50V7K

1 2

PC813

PC813 330P_0402_50V7K

330P_0402_50V7K

PR813

8.66K_0402_1%

8.66K_0402_1% 12

GFX_FB-2

12

PR816

17.8K_0402_1%

PL801

12

PR814

825K_0402_1%

1 2

100P_0402_50V8J

PC822

22P_0402_50V8J

1 2

GFX_FB-1

B+

PR804

10_0402_5%

1 2

C C

B B

VSS_AXG_SENSE<8>

VCC_AXG_SENSE<8>

+GFX_COREP

PR806

10_0402_5%

1 2

150P_0402_50V8J

PC821

4

12

PC802

10U_1206_25V6M

12

PC812

PC812 330P_0402_50V7K

330P_0402_50V7K

1000P_0402_50V7K

1 2

PC817

8.06K_0402_1%

GFXVR_PWRGD

GFXVR_CLKEN#

12

PC818

PR817

GFX_B+

PC803

10U_1206_25V6M

12

PC801

2200P_0402_50V7K

47K_0402_1%

PC806

0.1U_0402_25V6

PR811

+GFX_COREP

12

PR819

1.91K_0402_1%@

12

+5VALW

PR820

10K_0402_1%@

PR801

1_0603_5%

62881_FB

62881_COMP

62881_VW

62881_RBIAS

12

PC807

PC807 1U_0603_10V6K

1U_0603_10V6K

7

VSEN

6

FB

5

COMP

4

VW

3

RBIAS

2

PGOOD

1

CLK_EN#

0_0603_5%

62881_VDD

ISUM+

ISUM-

8

29

AGND

10

9

RTN

ISUM

ISUM+

PU801

PU801 ISL62881HRZ-T_QFN28_4 X4

ISL62881HRZ-T_QFN28_4 X4

VID626VR_ON27DPRSLPVR

28

62881_VR_ON

62881_DPRSLPVR

62881_VID6

3

PR802

11

25

62881_VID5

2

GFXVR_IMON <8>

1 2 12

62881_VIN

12

13

VIN

VDD

IMON

VID5

VID323VID4

24

62881_VID3

62881_VID4

12

PC809

PR803

0.22U_0603_25V7K

PHASE

VSSP

LGATE

VCCP

VID0

VID1

PR803

22.6K_0402_1%

1 2

PR805

2.2_0603_5%

UG_GFX

15

LX_GFX

16

17

LG_GFX

18

62881_VCCP

19

20

21

62881_VID0

62881_VID1

0.22U_0402_6.3V6K

1 2

12

PR834

PR834 10K_0402_1%@

10K_0402_1%@

PR833

PR833 10K_0402_1%

10K_0402_1%

PC808

BST_GFX BST_GFX1

14

BOOT

UGATE

VID2

22

62881_VID2

PR835

1 2

0_0402_5%

@

VSS_AXG_SENSE <8>

1 2

PC811

0.22U_0603_16V7K

PR808

+5VALW

0_0603_5%

PC819

2.2U_0603_6.3V6K

PR8210_0402_5% PR8210_0402_5%

12

PR8220_0402_5% PR8220_0402_5%

12

PR8240_0402_5% PR8240_0402_5%

12

PR8260_0402_5% PR8260_0402_5%

12

PR8270_0402_5% PR8270_0402_5%

12

PR8280_0402_5% PR8280_0402_5%

12

PR8300_0402_5% PR8300_0402_5%

12

PR8310_0402_5% PR8310_0402_5%

12 12

12

578

PQ801

PQ801 AO4474_SO8

AO4474_SO8

3 6

241

PL802

1 2

12

PR812

3.65K_0402_1%

1 2

PR815

2.61K_0402_1%

1 2

PR818

PR818 11K_0402_1%

11K_0402_1%

1 2

PC823

0.1U_0402_16V7K

1 2

PC824

0.033U_0402_16V7K

PR829

82.5_0402_1%

1 2

0.01U_0402_25V7K

PL802

ISUM-2

1 2

3.01K_0402_1%

ISUM-3

1 2

PC825

1

+

12

PR810

2

0_0402_5%

PH801

PH801 10KB_0603_5%_ERTJ1VR1 03J

10KB_0603_5%_ERTJ1VR1 03J

ISUM-1

PR825

1 2

ISUM-4

1 2

1

+

PC814

2

330U_D2E_2.5VM_R9

PR823

PR823 100_0402_1%

100_0402_1%

PC826

PC826 180P_0402_50V8J

180P_0402_50V8J

PC815

330U_D2E_2.5VM_R9

0.56UH_MMD-10CZ-R56M-M1_19A_20%

12

PR809

2.2_1206_5%

GFX_SN

PQ802

3 5

241

TPCA8028_PSO8

1 2

PC820

PC820 680P_0402_50V7K

680P_0402_50V7K

GFXVR_VID_0 <8> GFXVR_VID_1 <8> GFXVR_VID_2 <8> GFXVR_VID_3 <8> GFXVR_VID_4 <8> GFXVR_VID_5 <8> GFXVR_VID_6 <8> GFXVR_EN <8>

PR8320_0402_5% PR8320_0402_5%

GFXVR_DPRSLPVR <8>

ISUM+

ISUM-

1

+GFX_COREP

PJ801

+GFX_COREP

A A

2

112

JUMP_43X118@

PJ802

2

112

JUMP_43X118@

+GFX_CORE

(15A,600mils ,Via NO.= 30)

Security Classification

2009/01/06 2010/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/06 2010/01/06

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Nu mber Rev

Date: Sheet of

Compal Electronics, Inc.

GFX_CORE

50 52Tuesday, March 24, 2009

1

50 52Tuesday, March 24, 2009

0.1

8

H H

7

+

3VS

6

5

4

3

2

1

PR902

1.91K_0402_1%

G G

F F

CPU_CSP2

E E

D D

C C

PR915 470_0402_1%PR915 470_0402_1%

CPU_CSN2

PR918 470_0402_1%PR918 470_0402_1%

CPU_CSN1

PR919 470_0402_1%PR919 470_0402_1%

CPU_CSP1

PR920 470_0402_1%PR920 470_0402_1%

12

PC911

100P_0402_50V8J

12

PC918

100P_0402_50V8J

12

VGATE<15>

CLK_EN#< 12>

VR_ON<37>

12

PR916 0_0402_5%PR916 0_0402_5%

PC912 33P_0402_50V8JPC912 33P_0402_50V8J

PC914 33P_0402_50V8JPC914 33P_0402_50V8J

PC915 33P_0402_50V8JPC915 33P_0402_50V8J

PC917 33P_0402_50V8JPC917 33P_0402_50V8J

12

PR922

0_0402_5%

VSSSENSE

VCCSENSE

1 2

PR904 0_0402_5%PR904 0_0402_5%

1 2

PR905 0_0402_5%PR905 0_0402_5%

1 2

PR906 0_0402_5%PR906 0_0402_5%

1 2

CPU_CSP2-2

1 2

CPU_CSN2-1

1 2

CPU_CSN1-1

1 2

CPU_CSP1-2

1 2

CPU_GNDSNS

CPU_VSNS

CPU_THERM

PR923

0_0402_5%

1 2

PR924 20K_0402_ 1% PR924 20K_0402_ 1%

<8>

1 2

PC908

0.22U_0603_10V7K

CPU_MODE

10

CPU_VR_TT#

1 2

PR925 0_0402_5%PR925 0_0402_5%

+VCCP

<8>

H_PROCHOT#

1

2

3

4

5

6

7

8

9

PR926 68_0402_5%PR926 68_0402_5%

1 2

MODE

GND

CSP2

CSN2

CSN1

CSP1

GNDSNS

VSNS

THERM

VR_TT#

1 2

+5VS

PC903

2.2U_0603_6.3V6K

12

1 2

PC907

68P_0402_50V8J

CPU_VREF

CPU_DROOP

39

40

41

GND

VREF

IMON11DPRSLPVR12PSI#13VID614VID515VID416VID317VID218VID119VID0

CPU_IMON

CPU_DPRSLPVRPROC_DPRSLPVR

<5>

1 2

PR929 0_0402_5%PR929 0_0402_5%

12

PR903

PR903 1K_0402_5%

1K_0402_5%

1 2

PR927

PR927 1K_0402_5%@

1K_0402_5%@

PR907

5.76K_0402_1%

5.76K_0402_1% PR9090_0402_5% PR9090_0402_5%

PR908249K_0402_1% PR908249K_0402_1%

1 2

CPU_VR_ON

CPU_TONSEL CPU_VREF

CPU_ISLEW

37

38

V5FILT

DROOP

PU901

TPS51621RHAR_QFN40_6X6

VID6

1 2

PR930 0_0402_5%PR930 0_0402_5%

PR931 0_0402_5%PR931 0_0402_5%

H_VID6

PSI# CPU_PSI#

CPU_CLK_EN#

34

35

36

ISLEW

VR_ON

TONSEL

CLK_EN#

VID3

VID4

VID5

1 2

PR934 0_0402_5%PR934 0_0402_5%

PR933 0_0402_5%PR933 0_0402_5%

PR932 0_0402_5%PR932 0_0402_5%

PR935 0_0402_5%PR935 0_0402_5%

H_VID3

H_VID4

H_VID5

CPU_B+

+5VS

+3VS

PC902

0.1U_0402_25V6@

UGATE_CPU2

PQ902

3 5

241

SI7686DP-T1-E3_SO8

PR9100_0402_5% PR9100_0402_5%

PR9110_0402_5% PR9110_0402_5%

1 2

12

+5VS

PD1

PD1 1SS355_SOD323-2

1SS355_SOD323-2

1 2

PC910

0.22U_0603_10V7K

+5VS

PC919

0.22U_0603_10V7K

1 2

PD2

PD2 1SS355_SOD323-2

1SS355_SOD323-2

1 2

+5VS

CPU_OSRSEL

CPU_TRIPSEL

CPU_PGOOD

33

31

32

PGOOD

OSRSEL

TRIPSEL

DRVH2

VBST2

DRVL2

V5IN

PGND

DRVL1

VBST1

DRVH1

20

VID0

VID1

VID2

1 2

PR937 0_0402_5%PR937 0_0402_5%

PR939 0_0402_5%PR939 0_0402_5%

PR936 0_0402_5%PR936 0_0402_5%

H_VID0

H_VID2

H_VID1

UGATE_CPU2

30

BOOT_CPU2 BOOT_ CPU2-1

1 2

29

PR917 0_0603_5%

PHASE_CPU2

28

LL2

LGATE_CPU2

27

26

PC916 10U_0603_6.3V6M

25

LGATE_CPU1

24

PHASE_CPU1

23

LL1

BOOT_CPU1 BOOT_ CPU1-1

22

PR921 0_0603_5%PR921 0_0603_5%

UGATE_CPU1

21

1 2

SI7686DP-T1-E3_SO8

PQ903

3 5

241

TPCA8036_PSO8

UGATE_CPU1

PQ906

3 5

241

SI7686DP-T1-E3_SO8

PQ907

3 5

241

TPCA8036_PSO8

PQ901

3 5

241

SI7686DP-T1-E3_SO8

PQ904

3 5

241

TPCA8036_PSO8

PQ905

3 5

241

SI7686DP-T1-E3_SO8

PQ908

3 5

241

TPCA8036_PSO8

12

PR912

2.2_1206_5%

CPU_SNB2

12

PC909

PC909 680P_0402_50V7K

680P_0402_50V7K

PC920

0.1U_0402_25V6@

12

PR938

2.2_1206_5%

CPU_SNB1

12

PC924

PC924 680P_0402_50V7K

680P_0402_50V7K

12

PC905

PC904

10U_1206_25V6M

2200P_0402_50V7K

PL902

0.36UH_PCMC104T-R36MN1R17_30A_20%

0.36UH_PCMC104T-R36MN1R17_30A_20% 1

CPU_CSP2-1

2

12

PR913

17.8K_0402_1%

1 2

PR914

28.7K_0402_1%

PC913

0.033U_0402_16V7K

CPU_CSP2

12

PC922

PC921

PR940

10U_1206_25V6M

2200P_0402_50V7K

PL903

0.36UH_PCMC104T-R36MN1R17_30A_20%

0.36UH_PCMC104T-R36MN1R17_30A_20% 1

CPU_CSP1-1

2

12

17.8K_0402_1%

1 2

PR942

28.7K_0402_1%

PC925

0.033U_0402_16V7K

CPU_CSP1

12

PC906

10U_1206_25V6M

PR901

69.8K_0402_1%

1 2

CPU_SN-2

1 2

12

PC923

10U_1206_25V6M

PR941

69.8K_0402_1%

1 2

CPU_SN-1

1 2

12

PC926

10U_1206_25V6M@

4

3

PH901

PH901 100K_0603_1%_TH11-4H104FT

100K_0603_1%_TH11-4H104FT

12

PC927

10U_1206_25V6M@

4

3

PH902

PH902 100K_0603_1%_TH11-4H104FT

100K_0603_1%_TH11-4H104FT

1

12

+

PC901

220U_25V_M

2

CPU_CSN2

CPU_B+

12

CPU_CSN1

PL901

HCB4532KF-800T90_1812

1 2

B+

+CPU_CORE

<8>

PSI#

H_VID5

IMVP_IMON

B B

A A

8

7

H_VID6

PROC_DPRSLPVR

<8>

H_VID2

H_VID3

H_VID4

<8>

H_VID0

H_VID1

6

<8>

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

PROC_DPRSLPVR

+VCCP

PR943 1K_0402_5%PR943 1K_0402_ 5%

12

PR945 1K_0402_5%PR945 1K_0402_ 5%

12

PR947 1K_0402_5%PR947 1K_0402_ 5%

12

PR949 1K_0402_5%@PR949 1K_0402_5%@

12

PR951 1K_0402_5%@PR951 1K_0402_5%@

12

PR953 1K_0402_5%PR953 1K_0402_ 5%

12

PR955 1K_0402_5%@PR955 1K_0402_5%@

12

PR957 10K_0402_5%PR957 1 0K_0402_5%

12

5

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

PROC_DPRSLPVR

PR944 1K_0402_5%@PR944 1K_0402_5%@

12

PR946 1K_0402_5%@PR946 1K_0402_5%@

12

PR948 1K_0402_5%@PR948 1K_0402_5%@

12

PR950 1K_0402_5%PR950 1K_0402_ 5%

12

PR952 1K_0402_5%PR952 1K_0402_ 5%

12

PR954 1K_0402_5%@PR954 1K_0402_5%@

12

PR956 1K_0402_5%PR956 1K_0402_ 5%

12

PR958 1K_0402_5%@PR958 1K_0402_5%@

12

Security Classification

2009/01/06 2010/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

2009/01/06 2010/01/06

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

2

Compal Electronics, Inc.

CPU_CORE

51 52Tuesday, March 24, 2009

1

0.1

5

4

3

2

Version change list (P.I.R. List) Page 1 of 2

for PWR

Reason for change PG# Modify List Date

1

PhaseItem

D D

1

2

3

4

5

6

C C

7

8

9

10

B B

11

12

13

14

15

16

A A

17

Security Classification

2009/01/06 2009/01/06

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2009/01/06 2009/01/06

Compal Secret Data

Deciphered Date

2

20081022

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

<Doc>

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

52 52Tuesday, March 24, 2009

1

52 52Tuesday, March 24, 2009

0.1

COMPAL LA-5371P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual