Cirrus Logic CS5451A User Manual

CS5451A

VREFIN

VREFOUT

IIN1+ IIN1-

VIN1+

VIN1-

VIN2+ VIN2-

VIN3+ VIN3-

IIN2+ IIN2-

IIN3+

IIN3-

VA+

VD+

AGND

FSO

SDO

SCLK

Voltage

Reference

Serial

Interface

RESET

Decimation Filter

x1, 20

4th Order  Modulator

x1,20

4th Order  Modulator

GAIN

CPD

OWRS

XIN

DGND

VA-

Clock

Pulse Output

Regulator

Six-channel, Delta-sigma Analog-to-digital Converter

Features

• Synchronous Sampling

• On-chip 1.2 V Reference (25 ppm/°C typ.)

• Power Supply Configurations:

- VA+ = +3 V; VA- = -2 V; VD+ = +3 V

- Supply Tolerances: ±10%

• Power Consumption

- 23 mW Typical at VD+ = +3 V

• Simple Four-wire Serial Interface

• Charge pump driver output generates negative power supply.

• Ground-referenced Bipolar Inputs

Description

The CS5451A is a highly integrated delta-sigma ( analog-to-digital converter (ADC) developed for the power measurement industry. The CS5451A combines six  ADCs, decimation filters, and a serial interface on a single chip. The CS5451A interfaces d irectly to a current transformer or shunt to m eas ure curre nt, and to a resis tive divider or transformer to measure voltage. The product features a serial interface for communication with a microcontroller or DSP. The product is initialized and fully functional upon reset, and includes a voltage reference.

ORDERING INFORMATION:

See page 13.

http://www.cirrus.com

APR ‘11

DS635F4

1. PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3. THEORY OF OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.2 Digital Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4.5 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.6 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5. PACKAGE DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . . 13

8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

LIST OF FIGURES

Figure 1. Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3. One Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4. Serial Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5. Generating VA- with a Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CS5451A

2 DS635F4

CS5451A

20 19

IIN2-

VIN2+

IIN2+

RESET

IIN1+ IIN1-

XIN

VIN1-

VIN2-

CPD

DGND

VIN1+

VD+

OWRS

IIN3-

VIN3+

IIN3+

GAIN

VA+ VA -

VREFOUT

VIN3-

FSO

SDO

VREFIN

SCLK

AGND

Differential Current Input 2

Differential Volta g e Input 2

Differential Current Input 2

Reset

Differential Current Input 1 Differential Current Input 1

Master Clock

Differential Volta g e Input 1

Differential Volta g e Input 2

Charge Pump Drive

Digital Ground

Differential Volta g e Input 1

Digital Supply

Output Word Rate Select

Differential Current Input 3

Differential Voltage Input 3

Differential Current Input 3

Current Input Gain

Positive Analog Supply

Negative Analog Supply

Serial Port Enable

Reference Output

Differential Voltage Input 3

Frame Sync

Serial Data Output

Reference Input

Serial Clock Output

Analog Ground

CS5451A

1. PIN DESCRIPTION

Clock Generator

Master Clock Input 25

Control Pins and Serial Data I/O

Serial Clock Output

Serial Data Output 2 Frame Sync 3 Serial Port Enable 4 Current Input Gain

Output Word Rate Select

Reset 24

Analog Inputs/Outputs

Voltage Reference Input 7 Voltage Referenc e Outp ut

Differential V ol tage Inputs 1 1 ,12

18,17 22,21

Differential Current Inputs 13,14

16,15 20,19

Power Supply Connections

Analog Ground 6 Positive Analog Supply 9 Negative Analog Supply 10 Charge Pump Drive

Digital Ground 27 Positive Digital Supply 28

DS635F4 3

XIN - External clock signal or oscillator input.

SCLK - Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is

dependent on the XIN frequency and state of OWRS pin.

SDO -Serial port data output pin. Data will be output at a rate defined by SCLK. FSO - Framing signal indicates when data samples are about to be transmitted on the SDO pin. SE - When SE is low, the output pins of the serial port are tri-stated. GAIN - A logic high sets current channel gain to 1, a logic low sets the gain to 20. If no connection

is made to this pin, it will default to logic low level (through internal 200 k resistor to DGND). OWRS - A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the

OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low

level (through internal 200 k resistor to DGND).

RESET - Low activates Reset, all internal registers are set to their default states.

VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator. VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-

tude of 1.2 V and is referenced to the AGND pin on the converter.

VIN3+, VIN3- - Differential analog input pins for the voltage channel 3. VIN2+, VIN2- - Differential analog input pins for the voltage channel 2.

VIN1+, VIN1- - Differential analog input pins for the voltage channel 1. IIN3+, IIN3- - Differential analog input pins for the current channel 3.

IIN2+, IIN2- - Differential analog input pins for the current channel 2. IIN1+, IIN1- - Differential analog input pins for the current channel 1.

AGND - Analog ground. VA+ - The positive analog supply. Typical +3 V ±10% relative to AGND. VA- - The negative analog supply. Typical -2 V ±10% relative to AGND. CPD - Designed to drive external charge pump circuitry that will produce a negative analog sup-

ply (VA-)voltage.

DGND - Digital Ground. VD+ - The positive digital supply. Typical +3 V ±10% relative to AGND.

CS5451A

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital

Positive Analog

Negative Analog

Voltage Reference Input VREF+ - 1.2 - V

ANALOG CHARACTERISTICS

• Min/Max characteristics and specifications are guaranteed over all Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 3 V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V; VREFIN = +1.2 V. All voltages with respect to 0 V.

• XIN = 4.096 MHz.

Parameter Symbol Min Typ Max Unit

Accuracy (All Channels)

Total Harmonic Distortion THD 74 - - dB Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB Common Mode + Signal on Input VA- - VA+ V Input Sampling Rate - XIN/8 - Hz Analog Inputs (Note 1) Differential Input Voltage Range Gain=20

[(I

IN+) - (IIN-)] or [(VIN+) - (VIN-)] Gain=1

Bipolar Offset Gain=20

Gain=1 Crosstalk (Channel-to-channel) (50, 60 Hz) - -105 - dB Input Capacitance Gain = 20

Gain = 1

Effective Input Impedance Gain=20

Gain=1 Noise (Referred to Input)

0-60 Hz Gain=20

Gain=1 0-1 kHz Gain=20

Gain=1 0-2 kHz Gain=20

Gain=1

Reference Output

Output Voltage REFOUT 1.15 1.2 1.25 V Temperature Coefficient - 25 50 ppm/°C Load Regulation (Output Current 1 A Source or Sink) V Power Supply Rejection PSRR 60 - - dB

Reference Input

Input Voltage Range VREF+ 1.15 1.2 1.25 V Input Capacitance - - 10 pF Input CVF Current - - 1 µA

VD+ VA+

VA-

VIN VIN

VOS VOS

IC IC

EII EII

2.7

-2.2

500

-610mV

3.0

-2.0

1.6

±11.5

±0.5

600

3.3

-1.8

±20

±4.0

2.5 50

3.75 75

mV mV

µV µV µV µV µV µV

V V V

P-P

pF pF

k k

rms rms rms rms rms rms

4 DS635F4

ANALOG CHARACTERISTICS (continued)

PSRR 20

106.07 V

------------------







log=

Parameter Symbol Min Typ Max Unit

Power Supplies

Power Supply Currents I

Typical VA+=VD+=+3V; VA-=-2V I

Power Consumption (Note 2) Without CPD

Power Supply Rejection (DC) 50, 60 Hz (Note 3) Voltage Channel 50, 60 Hz (Note 3) Current Channel

with CPD

D+

ID+ without CPD

With CPD

A+

PSCA PSCD PSCD

PC PC

PSRR PSRR PSRR

50 50 60

CS5451A

4.0

5.0

1.0 27

65 90

5.3

6.3

1.5 35

mA mA mA

mW mW

dB dB dB

Notes:

1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1

2. All outputs unloaded. All inputs CMOS level.

3. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using chargepump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):

DIGITAL CHARACTERISTICS (See Note 4)

• Min/Max characteristics and specifications are guaranteed over all Operating Conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• XIN = 4.096 MHz

Parameter Symbol Min Typ Max Unit

Master Clock Characteristics

Master Clock Frequency XIN 3 4.096 5 MHz Master Clock Duty Cycle 40 - 60 %

Filter Characteristics

High Rate Filter Output Word Rate OWRS = 0

OWRS = 1

Input/Output Characteristics

High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage I

Low-Level Output Voltage I

= -5.0 mA

out

= 5.0 mA

out

Input Leakage Current (Note 5) I 3-State Leakage Current I Digital Output Pin Capacitance C

OWR OWR

IH IL

OL in

out

XIN/2048 XIN/1024

Hz Hz

0.6 VD+ - VD+ V

0.0 - 0.8 V

(VD+) - 1.0 - - V

--0.4V

-±1±10µA

--±10µA

-9-pF

Notes: 4. All measurements performed under static conditions.

5. For OWRS and GAIN

DS635F4 5

pins, input leakage current is 30 µA (Max).

+ 9 hidden pages

Cirrus Logic CS5451A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

LIST OF FIGURES

1. PIN DESCRIPTION

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ANALOG CHARACTERISTICS

ANALOG CHARACTERISTICS (continued)

DIGITAL CHARACTERISTICS (See Note 4)