CS53L21
Low Power, Stereo Analog to Digital Converter
FEATURES
98 dB Dynamic Range (A-wtd)
-88 dB THD+N
Analog Gain Controls
– +32 dB or +16 dB MIC Pre-Amplifiers
– Analog Programmable Gain Amplifier
(PGA)
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold and
Attack/Release Rates
Independent Left/Right Channel Control
Digital Volume Control
High-Pass Filter Disable for DC Measurements
Stereo 3:1 Analog Input MUX
Dual MIC Inputs
– Programmable, Low Noise MIC Bias Levels
– Differential MIC Mix for Common Mode
Noise Rejection
Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
SYSTEM FEATURES
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
– Stereo Record (ADC): 8.72 mW @ 1.8 V
– Stereo Record (MIC to PGA and ADC):
13.73 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– ADC, MIC Pre-Amplifier, PGA
Software Mode (I²C
Hardware Mode (Stand-Alone Control)
Flexible Clocking Options
– Master or Slave Operation
Digital Routing Mixes
– Mono Mixes
®
& SPI™ Control)
1.8 V to 3.3 V
PCM Serial Interface
Digital
Signal
Processing
Engine
High Pass
Filters
Register
Configuration
Hardware Mode
2
C & SPI
or I
Software Mode
Control Data
Reset
Serial Audio
Output
Level Translator
Preliminary Product Information
http://www.cirrus.com
1.8 V to 2.5 V
ALC
ALC
Volume
Controls
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
MUX
MUX
PGA
PGA
MUX
+32 dB
+32 dB
MIC
Bias
Stereo Input 1
Stereo Input 2
Stereo Input 3 /
Mic Input 1 & 2
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
DS700PP1
MAY ‘06
CS53L21
APPLICATIONS
Portable Audio Players
Digital Microphones
Digital Voice Recorders
Voice Recognition Systems
Audio/Video Capture Cards
GENERAL DESCRIPTION
The CS53L21 is a highly integrated, 24-bit, 96 kHz, low
power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment
between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system
applications.
The ADC input path allows independent channel control
of a number of features. An input multiplexer selects between line-level or microphone-level inputs for each
channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low
noise MIC bias voltage supply. A PGA is available for
line or microphone inputs and provides analog gain with
soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp
transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels
appropriately.
The Signal Processing Engine (SPE) controls left/right
channel volume mixing, channel swap and channel
mute functions. All volume-level changes may be configured to occur on soft ramp and zero cross transitions.
The CS53L21 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85° C). The CDB53L21 Customer Demonstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 63 for complete details.
In addition to its many features, the CS53L21 operates
from a low-voltage analog and digital core, making this
A/D ideal for portable systems that require extremely
low power consumption in a minimal amount of space.
2 DS700PP1
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11
SPECIFIED OPERATING CONDITIONS ............................................................................................. 11
ABSOLUTE MAXIMUM RATINGS .......................................................................................................11
ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .................................................................... 12
ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................................... 13
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14
SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 16
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 18
POWER CONSUMPTION .................................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ......................................................................................................................................... 20
4.1.1 Architecture ........................................................................................................................... 20
4.1.2 Line & MIC Inputs .................................................................................................................. 20
4.1.3 Signal Processing Engine ..................................................................................................... 20
4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20
4.1.5 Power Management .............................................................................................................. 20
4.2 Hardware Mode .............................................................................................................................. 21
4.3 Analog Inputs ................................................................................................................................. 22
4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 22
4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23
4.3.3 Digital Routing ....................................................................................................................... 23
4.3.4 Differential Inputs .................................................................................................................. 23
4.3.4.1 External Passive Components ................................................................................... 23
4.3.5 Analog Input Multiplexer ........................................................................................................ 25
4.3.6 MIC & PGA Gain ................................................................................................................... 25
4.3.7 Automatic Level Control (ALC) .............................................................................................. 26
4.3.8 Noise Gate ............................................................................................................................ 27
4.4 Signal Processing Engine ............................................................................................................... 28
4.4.1 Volume Controls .................................................................................................................... 28
4.4.2 Mono Channel Mixer ............................................................................................................. 28
4.5 Serial Port Clocking ........................................................................................................................ 29
4.5.1 Slave ..................................................................................................................................... 30
4.5.2 Master ................................................................................................................................... 30
4.5.3 High-Impedance Digital Output ............................................................................................. 31
4.5.4 Quarter- and Half-Speed Mode .............................................................................................31
4.6 Digital Interface Formats ................................................................................................................ 31
4.7 Initialization ..................................................................................................................................... 32
4.8 Recommended Power-Up Sequence ............................................................................................. 32
4.9 Recommended Power-Down Sequence ........................................................................................ 33
4.10 Software Mode ............................................................................................................................. 34
4.10.1 SPI Control .......................................................................................................................... 34
4.10.2 I²C Control ........................................................................................................................... 34
4.10.3 Memory Address Pointer (MAP) .......................................................................................... 3
4.10.3.1 Map Increment (INCR) ............................................................................................. 36
5. REGISTER QUICK REFERENCE ........................................................................................................ 37
6. REGISTER DESCRIPTION .................................................................................................................. 40
CS53L21
6
DS700PP1 3
CS53L21
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40
6.2 Power Control 1 (Address 02h) ...................................................................................................... 40
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41
6.4 Interface Control (Address 04h) ..................................................................................................... 43
6.5 MIC Control (Address 05h) ............................................................................................................. 44
6.6 ADC Control (Address 06h) ............................................................................................................ 45
6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 47
6.8 SPE Control (Address 09h) ............................................................................................................ 48
6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ................. 49
6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 50
6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 51
6.12 Channel Mixer (Address 18h) ....................................................................................................... 51
6.13 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 52
6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 52
6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 53
6.16 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 54
6.17 Status (Address 20h) (Read Only) ............................................................................................... 55
7. ANALOG PERFORMANCE PLOTS ....................................................................................................56
7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 56
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57
8.1 Auto Detect Enabled ....................................................................................................................... 57
8.2 Auto Detect Disabled ...................................................................................................................... 58
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59
9.1 Power Supply, Grounding ............................................................................................................... 59
9.2 QFN Thermal Pad .......................................................................................................................... 59
10. DIGITAL FILTERS .............................................................................................................................. 60
11. PARAMETER DEFINITIONS .............................................................................................................. 61
12. PACKAGE DIMENSIONS ................................................................................................................. 62
THERMAL CHARACTERISTICS .......................................................................................................... 62
13. ORDERING INFORMATION ............................................................................................................. 63
14. REFERENCES .................................................................................................................................... 63
15. REVISION HISTORY ......................................................................................................................... 64
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10
Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15
Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15
Figure 5.Control Port Timing - I²C ............................................................................................................. 16
Figure 6.Control Port Timing - SPI Format ................................................................................................ 17
Figure 7.Analog Input Architecture ............................................................................................................ 22
Figure 8.MIC Input Mix w/Common Mode Rejection .................................................................................24
Figure 9.Differential Input .......................................................................................................................... 24
Figure 10.ALC ........................................................................................................................................... 26
Figure 11.Noise Gate Attenuation ............................................................................................................. 27
Figure 12.Signal Processing Engine ......................................................................................................... 28
Figure 13.Master Mode Timing ................................................................................................................. 30
Figure 14.Tri-State Serial Port .................................................................................................................. 31
Figure 15.I²S Format ................................................................................................................................. 31
Figure 16.Left-Justified Format ................................................................................................................. 32
Figure 17.Initialization Flow Chart ............................................................................................................. 33
Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34
Figure 19.Control Port Timing, I²C Write ................................................................................................... 35
Figure 20.Control Port Timing, I²C Read ................................................................................................... 35
4 DS700PP1
Figure 21.AIN & PGA Selection ................................................................................................................ 47
Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56
Figure 23.ADC Passband Ripple .............................................................................................................. 60
Figure 24.ADC Stopband Rejection .......................................................................................................... 60
Figure 25.ADC Transition Band ................................................................................................................ 60
Figure 26.ADC Transition Band Detail ...................................................................................................... 60
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Hardware Mode Feature Summary ............................................................................................. 21
Table 3. MCLK/LRCK Ratios .................................................................................................................... 30
CS53L21
DS700PP1 5
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
)
CS53L21
TSTN
LRCK
SDA/CDIN (MCLKDIV2)
SCL/CCLK (I²S/LJ
AD0/CS
(TSTN)
VA_PULLUP
TSTO
AGND
TSTO
SCLK
MCLK
SDOUT (M/S
DGND
303132
29
1
2
)
3
4
5
6
7
8
CS53L21
109
11
NIC
NIC
TSTO
13 14 15 16
12
VA
AGND
VD
TSTO
VL
262728
VQ
Pin Name # Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
LRCK
SDA/CDIN
(MCLKDIV2)
SCL/CCLK
(I²S/LJ)
AD0/CS
(TSTN)
VA_ PULLUP
TSTO
AGND
TSTO
1
serial audio data line.
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
2
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
3
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-
mats for the ADC.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.
4
Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to
DGND for normal operation.
Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA
5
using a 47 kΩ resistor.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
6
nection external to the pin).
7
Analog Ground (Input) - Ground reference for the internal analog section.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
8
nection external to the pin).
RESET
25
FILT+
AIN1B
24
AIN1A
23
AFILTB
22
AFILTA
21
20
AIN2B/BIAS
AIN2A
19
MICIN2/BIAS/AIN3B
18
MICIN1/AIN3A
17
6 DS700PP1
TSTO
NIC
NIC
VA
AGND
TSTO
VQ
FILT+
MICIN1/
AIN3A
MICIN2/
BIAS/AIN3B
AIN2A
AIN2B/BIAS
AFILTA
AFILTB
AIN1A
AIN1B
RESET
VL
VD
DGND
SDOUT
)
(M/S
MCLK
SCLK
TSTN
Thermal Pad
CS53L21
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
9
nection external to the pin).
10
.Not Internally Connected - This pin is not connected internal to the device and may be connected to
11
ground or left “floating”. No other external connection should be made to this pin.
12
Analog Power (Input) - Positive power for the internal analog section.
13
Analog Ground (Input) - Ground reference for the internal analog section.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
14
nection external to the pin).
15
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
16
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-
17
cation table.
Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics
18
specification table. This pin can also be configured as an output to provide a low noise bias supply for an
external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
Analog Input (Input) -
19
table.
Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-
20
cation table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
21
Filter Connection (Output) - Filter connection for the ADC inputs.
22
23
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
24
table.
25
Reset (Input) - The device enters a low power mode when this pin is driven low.
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and
26
host control port. Refer to the Recommended Operating Conditions for appropriate voltages.
27
Digital Power (Input) - Positive power for the internal digital section.
28
Digital Ground (Input) - Ground reference for the internal digital section.
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
29
Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.
30
Master Clock (Input) - Clock source for the delta-sigma modulators.
31
Serial Clock (Input/Output) -- Serial clock for the serial audio interface.
Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal
32
operation.
-
Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59.
The full-scale level is specified in the ADC Analog Characteristics specification
DS700PP1 7
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply.
CS53L21
Pin Name
SW/(HW)
RESET Input
SCL/CCLK
(I²S/LJ)
SDA/CDIN
(MCLKDIV2)
AD0/CS
(DEM)
MCLK Input
LRCK Input/Output
SCLK Input/Output
SDOUT
(M/S)
Input
Input/Output
Input
Input/Output
I/O Driver Receiver
- 1.8 V - 3.3 V
- 1.8 V - 3.3 V, with Hysteresis
1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis
- 1.8 V - 3.3 V
- 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
Table 1. I/O Power Rails
8 DS700PP1
2. TYPICAL CONNECTION DIAGRAMS
CS53L21
+1.8 V or +2.5 V
+1.8 V, +2.5 V
or +3.3 V
Note 1:
Resistors are required for I²C
control port operation
Digital Audio
Processor
See Note 1
1 µF
0.1 µF
VD
VA
0.1 µF
See Note 4
1 µF
47 kΩ
VA_
+1.8 V or +2.5 V
Note 4:
Series resistance in the path of the power supplies must
be avoided.
PULLUP
CS53L21
TSTN
MCLK
SCLK
LRCK
SDOUT
RESET
SCL/CCLK
SDA/CDIN
AD0/CS
AIN1A
AIN1B
AIN2A
AIN2B
BIAS1
MICIN1
AIN3A
1800 pF
1800 pF
1800 pF
1800 pF
1 µF
100 Ω
*
1 µF
*
100 Ω
1 µF
100 Ω
*
1 µF
*
100 Ω
1 µF
100 kΩ
BIAS2
AIN3B/MICIN2
2 k
2 k
Ω
Ω
0.1 µF
VL
FILT+
0.1 µF
R
L
Note 3: The value of RL is dictated
by the microphone cartridge.
AGND
AFILTA
**
150 pF
150 pF
AFILTB
VQ
DGND
* Capacitors must be C0G or equivalent
Left Analog Input 1
100 kΩ
100 kΩ
Right Analog Input 1
Left Analog Input 2
100 kΩ
100 kΩ
Right Analog Input 2
Microphone Input
Microphone Bias
See Note 3
10 µF
1 µF
Figure 1. Typical Connection Diagram (Software Mode)
DS700PP1 9
CS53L21
+1.8V or +2.5V
Digital Audio
Processor
1 µF
VL or DGND (1)
0.1 µF
VD
TSTN
MCLK
SCLK
LRCK
SDOUT/
M/S
RESET
I²S/LJ
MCLKDIV2
0.1 µF
VA
CS53L21
47 kΩ
VA_
PULLUP
AIN1A
AIN1B
FILT+
1800 pF
1800 pF
See Note 4
Note 4:
Series resistance in the path of the power s upplies
(typically used for added filtering ) must be avoided.
100 Ω
*
1 µF
*
100 Ω
1 µF
+1.8V or +2.5V
Left Analog Input 1
100 kΩ
100 kΩ
Right Analog Input 1
10 µF
1 µF
+1.8V, 2.5 V
or +3.3V
0.1 µF
(1) Pull-up to VL (47 kΩ≤for Master Mode.
Pull-down to DGND for Slave Mode .
VL
DGND
AGND
AFILTA
AFILTB
VQ
**
150 pF
* Capacitors must be C0G or equivalent
150 pF
Figure 2. Typical Connection Diagram (Hardware Mode)
10 DS700PP1
CS53L21
3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
= 25° C.)
A
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters Symbol Min Nom Max Units
DC Power Supply (Note 1)
Analog Core
Digital Core
Serial/Control Port Interface
Ambient Temperature Commercial - CNZ
Automotive - DNZ
VA
VD
VL
T
1.65
2.37
1.65
2.37
1.65
2.37
3.14
A
-10
-40
1.8
2.5
1.8
2.5
1.8
2.5
3.3
1.89
2.63
1.89
2.63
1.89
2.63
3.47
-
-
+70
+85
V
V
V
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
V
VA
VD
VL
V
T
T
I
in
IN
IND
stg
A
DC Power Supply Analog
Digital
Serial/Control Port Interface
Input Current (Note 2)
Analog Input Voltage (Note 3)
Digital Input Voltage
(Note 3)
Ambient Operating Temperature (power applied)
Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. The device will operate properly over the full range of the analog, digital core and serial/control port interface supplies.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
-0.3
-0.3
-0.3
-±10mA
AGND-0.7 VA+0.7
-0.3 VL+ 0.4 V
-50 +115 °C
-65 +150 °C
3.0
3.0
4.0
V
V
V
V
DS700PP1 11
CS53L21
ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive
input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 4)
Analog In to ADC (PGA bypassed)
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
PGA Setting: +12 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
-60 dBFS
PGA Setting: +12 dB -1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error SDOUT Code with HPF On
Input
Interchannel Isolation
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
Input Impedance (Note 5) ADC
PGA
MIC
Min Typ Max Min Typ Max Unit
93
90
-
-
-
92
89
85
82
-
-
- -85 -79 - -83 -77 dB
-
-
- -76 - - -74 - dB
-
-
- -74 - - -71 - dB
-0.2- -0.2-dB
- ±100 - - ±100 - ppm/°C
- 352 - - 352 - LSB
-90- -90-dB
0.74•VA
0.75•VA
-
-
-
99
96
-86
-76
-36
98
95
91
88
-88
-35
86
83
78
74
0.78•VA
0.794•VA
0.129•VA
0.022•VA
20
39
50
-
-
-80
-
-
-
-
-
-
-81
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
90
87
-
-
-
89
86
82
79
-
-
-
-
-
-
0.74•VA
0.75•VA
-
-
-
96
93
-84
-73
-33
95
92
88
85
-86
-32
83
80
75
71
0.78•VA
0.794•VA
0.129•VA
0.022•VA
20
39
50
-
-
-78
-
-
-
-
-
-
-80
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
12 DS700PP1
CS53L21
ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input
filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 4)
Analog In to ADC
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
PGA Setting: +12 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
-60 dBFS
PGA Setting: +12 dB -1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error SDOUT Code with HPF On
Input
Interchannel Isolation
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
Input Impedance (Note 5) ADC
PGA
MIC
4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table.
5. Measured between AINxx and AGND.
Min Typ Max Min Typ Max Unit
91
78
-
-
-
90
87
83
80
-
-
- -85 -77 - -83 -75 dB
-
-
- -76 - - -74 - dB
-
-
- -74 - - -71 - dB
- 0.1 - - 0.1 - dB
- ±100 - - ±100 - ppm/°C
- 352 - - 352 - LSB
-90--90-dB
0.74•VA
0.75•VA
18
40
50
99
96
-86
-76
-36
98
95
91
88
-88
-35
86
83
78
74
0.78•VA
0.794•VA
0.129•VA
0.022•VA
-
-
-
-
-
-78
-
-
-
-
-
-
-80
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
88
85
-
-
-
87
84
80
77
-
-
-
-
-
-
0.74•VA
0.75•VA
18
40
50
96
93
-84
-73
-33
95
92
88
85
-86
-32
83
80
75
71
0.78•VA
0.794•VA
0.129•VA
0.022•VA
-
-
-
-
-
-76
-
-
-
-
-
-
-78
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
DS700PP1 13
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 6) Min Typ Max Unit
Passband (Frequency Response) to -0.1 dB corner
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB
Phase Deviation @ 20 Hz
Passband Ripple
Filter Settling Time
6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters
are for Fs = 48 kHz.
CS53L21
0 - 0.4948 Fs
-0.09 - 0.17 dB
0.6 - - Fs
33 - - dB
- 7.6/Fs - s
-
-
-10-Deg
- - 0.17 dB
-10
3.7
24.2
5
/Fs 0 s
-
-
Hz
Hz
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
Parameters Symbol Min Max Units
RESET
MCLK Frequency
MCLK Duty Cycle (Note 8)
pin Low Pulse Width (Note 7)
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
= 15 pF.)
LOAD
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
F
s
F
s
F
s
F
s
1/t
P
t
s(LK-SK)
t
d(MSB)
t
s(SDO-SK)
t
h(SK-SDO)
1-ms
1.024 38.4 MHz
45 55 %
4
8
4
50
45 55 %
-64•FsHz
45 55 %
40 - ns
-52ns
20 - ns
30 - ns
12.5
25
50
100
kHz
kHz
kHz
kHz
14 DS700PP1
Master Mode (Note 9)
CS53L21
Parameters Symbol Min Max Units
Output Sample Rate (LRCK) All Speed Modes
(Note 10)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are
settled.
8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
9. See“Master” on page 30.
10. “MCLK” refers to the external master clock applied.
//
LRCK
t
s(LK-SK)
//
t
P
//
SCLK
SDOUT
t
d(MSB)
Figure 3. Serial Audio Interface Slave Mode Timing
t
h(SK-SDO)
//
MSB MSB-1
//
F
s
1/t
P
t
d(MSB)
t
s(SDO-SK)
t
h(SK-SDO)
//
MCLK
-Hz
45 55 %
- 64•F
45 55 %
-52ns
20 - ns
30 - ns
t
s(SDO-SK)
----------------128
s
Hz
//
LRCK
//
t
P
//
SCLK
//
t
d(MSB)
SDOUT
Figure 4. Serial Audio Interface Master Mode Timing
DS700PP1 15
t
h(SK-SDO)
t
s(SDO-SK)
//
MSB MSB-1
//
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 11)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
f
t
t
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
t
susp
t
ack
scl
irs
buf
t
rc
fc
CS53L21
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 3450 ns
11. Data must be held for sufficient time to bridge the transition time, t
RST
t
SDA
SCL
irs
Stop Start
t
buf
t
t
hdst
low
t
high
t
hdd
Figure 5. Control Port Timing - I²C
t
sud
Repeated
Start
t
sust
t
hdst
, of SCL.
fc
t
f
t
r
Stop
t
susp
16 DS700PP1
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter Symbol Min Max Units
CS53L21
CCLK Clock Frequency
RESET Rising Edge to CS Falling
Falling to CCLK Edge
CS
CS
High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 12)
Rise Time of CCLK and CDIN (Note 13)
Fall Time of CCLK and CDIN (Note 13)
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For f
<1 MHz.
sck
RST
CS
CCLK
t
srs
t
t
sch
css
t
scl
t
dsu
f
sck
t
srs
t
css
t
csh
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
t
f2
t
dh
06.0MHz
20 - ns
20 - ns
1.0 - μs
66 - ns
66 - ns
40 - ns
15 - ns
-100ns
-100ns
t
csh
t
r2
CDIN
Figure 6. Control Port Timing - SPI Format
DS700PP1 17
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 14)
FILT+
MIC BIAS Characteristics
Nominal Voltage MICBIAS_LVL[1:0] = 00
MICBIAS_LVL[1:0] = 01
MICBIAS_LVL[1:0] = 10
MICBIAS_LVL[1:0] = 11
DC Current Source
Power Supply Rejection Ratio (PSRR) 1 kHz
Power Consumption (Normal Operation Worse Case) 1 kHz
Power Supply Rejection Ratio (PSRR) (Note 15) 1 kHz
14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
CS53L21
-
-
-
-VA-V
-
-
-
-
-
-
--30mW
-60-dB
0.5•VA
23
-
0.8•VA
0.7•VA
0.6•VA
0.5•VA
-
50
10
-
-
-
-
-
-
1
-
V
kΩ
μA
V
V
V
V
mA
dB
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 16) Symbol Min Max Units
Input Leakage Current
Input Capacitance
1.8 V - 3.3 V Logic
High-Level Output Voltage (I
Low-Level Output Voltage
High-Level Input Voltage
Low-Level Input Voltage
16. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails.
= -100 μA)
OH
(IOL = 100 μA)
I
in
V
OH
V
OL
V
IH
V
IL
-±10μA
-10pF
VL - 0.2 - V
-0.2V
0.68•VL - V
- 0.32•VL V
18 DS700PP1
POWER CONSUMPTION
See (Note 17)
CS53L21
Power Ctl. Registers Typical Current (mA)
02h 03h
Operation
Reserved bit 6
Reserved bit 5
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
PDN_MICB
PDN_MICA
1
Off
(Note 18)
2 Standby (Note 19)
3 Mono Record ADC1111100111
PGA to ADC
MIC to PGA to ADC
(with Bias)
MIC to PGA to ADC
(no Bias)
4 Stereo Record ADC1111000111
PGA to ADC
MIC to PGA to ADC
(no Bias)
xxxxxxxxxx
xxxxxx1xxx
1110100111
1110100100
1110100101
1100000111
1100000001
i
i
VA
V
PDN_MICBIAS
1.8 0 0 0 0
2.5 0 0 0 0
1.8 0.01 0.02 0 0.05
2.5 0.01 0.03 0 0.10
1.8 1.85 2.03 0.03 7.05
2.5 2.07 3.05 0.05 12.94
1.8 2.35 2.03 0.03 7.95
2.5 2.58 3.08 0.05 14.29
1.8 3.67 2.05 0.03 10.36
2.5 3.95 3.09 0.05 17.71
1.8 3.27 2.03 0.03 9.61
2.5 3.52 3.08 0.05 16.62
1.8 2.69 2.12 0.03 8.72
2.5 2.93 3.18 0.04 15.40
1.8 3.65 2.12 0.03 10.45
2.5 3.91 3.17 0.04 17.84
1.8 5.48 2.11 0.03 13.73
2.5 5.76 3.17 0.04 22.45
i
VD
VL
(Note 20)
Tota l
Power
(mW
rms
)
17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation.
18. RESET
pin 25 held LO, all clocks and data lines are held LO.
19. RESET pin 25 held HI, all clocks and data lines are held HI.
20. VL current will slightly increase in master mode.
DS700PP1 19
4. APPLICATIONS
4.1 Overview
4.1.1 Architecture
The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs
is equal to the system sample rate. The different clock rates maximize power savings while maintaining
high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and
Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input
Master Clock (MCLK).
4.1.2 Line & MIC Inputs
The analog input portion of the A/D allows selection from and configuration of multiple combinations of
stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC
input with common mode rejection), two MIC bias outputs and independent channel control (including a
high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume
controls, including gain, boost, attenuation and inversion are also available.
4.1.3 Signal Processing Engine
CS53L21
The ADC data has independent volume controls and mixing functions such as mono mixes and left/right
channel swaps.
4.1.4 Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
4.1.5 Power Management
Two Software Mode control registers provide independent power-down control of the ADC, PGA, MIC preamp and MIC bias, allowing operation in select applications with minimal power consumption.
20 DS700PP1
4.2 Hardware Mode
A limited feature-set is available when the A/D powers up in Hardware Mode (see “Recommended Power-
Up Sequence” on page 32) and may be controlled via stand-alone control pins. Table 2 shows a list of func-
tions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function Default Configuration Stand-Alone Control Note
Power Control Device
PGAx
ADCx
MIC Bias
MICx Pre-Amplifier
Auto-Detect
Speed Mode Serial Port Slave
Serial Port Master
MCLK Divide
Serial Port Master / Slave Selection
Interface Control ADC
ADC Volume & Gain Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Line/MIC Input Select
ADC mix Volume and Gain Invert
Soft Ramp
Zero Cross
Signal Processing Engine (SPE) MIX
Data Selection (SPE Enable)
Channel Swap ADC
Table 2. Hardware Mode Feature Summary
Powered Up
Powered Up
Powered Up
Powered Down
Powered Down
Enabled - -
Auto-Detect Speed Mode
Single-Speed Mode
(Selectable) “MCLKDIV2” pin 2
(Selectable) “M/S” pin 29
(Selectable) “I²S/LJ” pin 3
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
Enabled
Continuous DC Subtraction
AIN1A to PGAA
AIN1B to PGAB
Disabled
Enabled
Enabled
Disabled - -
ADC Data to SPE - -
ADCA = L; ADCB = R - -
--
--
--
--
--
--
CS53L21
see Section
4.5 on page 29
see Section
4.5 on page 29
see Section
4.6 on page 31
DS700PP1 21
4.3 Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel.
CS53L21
ADCA_MUTE
+20dB
Digital
Boost
ADCA_ATT[7:0]
0/-96dB
1dB steps
Attenuator
SOFTA
MUX
DIGMIX
MUX
MICMIX
ADCA_HPF FREEZE
ADCA_HPF ENABLE
ALC_ARATE[5:0]
ALC_RRATE[5:0]
Σ
ALCA_SRDIS
ALCA_ZCDIS
ALC_ENA
MAX[2:0]
MIN[2:0]
ALC_ENB
ALCB_SRDIS
ALCB_ZCDIS
ADCA_DBOOST
ALC
PCM Serial Interface
MUX
MUX
ADCB_HPF FREEZE
ADCB_HPF ENABLE
ADCB_DBOOST
TO SIGNAL PROCESSING
ENGINE (SPE)
FROM SIGNAL
PROCESSING ENGINE
(SPE)
+20dB
Digital
Boost
SOFTB
Attenuator
ADCB_MUTE
ADCB_ATT[7:0]
0/-96dB
1dB steps
Figure 7. Analog Input Architecture
4.3.1 Digital Code, Offset & DC Measurement
Noise Gate
PDN_ADCA
Multibit
Oversampling
ADC
INV_ADCA
NG_ALL
NG_EN
THRESH[3:0]
NGDELAY[1:0]
PDN_ADCB
Multibit
Oversampling
ADC
INV_ADCB
PGAA_VOL[5:0]
ADC_SNGVOL
SOFTA
ZCROSSA
+12/-3dB
0.5dB steps
PGA
PDN_PGAA
AINA_MUX[1:0]
MICBIAS_LVL[1:0]
PDN_MICBIAS
PGAB_VOL[5:0]
ADC_SNGVOL
SOFTB
ZCROSSB
+12/-3dB
0.5dB steps
PGA
PDN_PGAB
AINB_MUX[1:0]
MUX
MUX
+16/
32 dB
MICA_BOOST
PDN_MICA
MICBIAS
MICBIAS_SEL
+16/
32dB
MICB_BOOST
PDN_MICB
AIN1A
AIN2A
AIN3A/ MICIN1
AIN1B
AIN2B/MICBIAS
AIN3B/ MICIN2/
MICBIAS
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to “Analog Characteristics (Commercial - CNZ)” on page 12 and/or
“Analog Characteristics (Automotive - DNZ)” on page 13 for the specified offset level).
The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel.
DC levels are measured relative to VQ and will be decoded as positive two’s complement binary numbers
above VQ and negative two’s complement binary numbers below VQ.
Software
Controls:
“Status (Address 20h) (Read Only)” on page 55, “ADC Control (Address 06h)” on page 45.
22 DS700PP1
4.3.2 High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the
corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion
result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the A/D with the high-pass filter enabled and the DC offset not “frozen” until the filter settles.
See the Digital Filter Characteristics for filter settling time.
2. Freezing the DC offset.
The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.
If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using
the ADCx_HPFEN bit.
CS53L21
Software
Controls:
“ADC Control (Address 06h)” on page 45.
4.3.3 Digital Routing
The digital output of the ADC may be internally routed to the Signal Processing Engine (SPE). ADC output
volume may be controlled using the ADCMIX [6:0] bits, and channel swaps can be done using the
ADCA[1:0] and ADCB[1:0] bits. This “processed” ADC data can be selected for output in place of the ADC
output data using the DIGMIX bit.
Software
Controls:
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 51, “Inter-
face Control (Address 04h)” on page 43.
4.3.4 Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides common mode rejection of noise in digitally intense PCB’s where the microphone signal traverses long traces,
or across long microphone cables as illustrated in Figure 8.
Since the mixer provides a differential combination of the two signals, the potential input mix may exceed
the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically
attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX
volume control to re-adjust a small signal to desired levels.
The analog inputs may also be used as a differential input pair as illustrated in Figure 9. The two channels
are differentially combined when the MICMIX bit is enabled.
4.3.4.1 External Passive Components
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kW
may be combined with an external capacitor of 1 mF to achieve the cutoff frequency defined by the equation,
An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with
the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
DS700PP1 23
CS53L21
fc
----------------------------------------------- 3 . 1 8 H z==
1
2π 50 kΩ()1 μF()
The MICBIAS series resistor must be selected based on the requirements of the particular microphone
used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.
Software
Controls:
“Interface Control (Address 04h)” on page 43, “MIC Control (Address 05h)” on page 44.
MICBIAS
20
MICIN1
//
+
17
Σ
MICIN2
//
Figure 8. MIC Input Mix w/Common Mode Rejection
+
18
2.5 V
2.15 V
1.25 V
0.35 V
2.15 V
1.25 V
0.35 V
Full-Scale Differential Input Level (MICMIX=1)
= (AINxA - AINxB) = 3.6 V
PP
Figure 9. Differential Input
= 1.27 V
AINxA
AINxB
RMS
VA
24 DS700PP1
4.3.5 Analog Input Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input
source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select
from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up.
Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit
routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the
two input channels.
The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between
these paths, the input resistance to the A/D will change accordingly. Refer to the input resistance characteristics in the Characteristic and Specification Tables for the input resistance of each path.
CS53L21
Software
Controls:
“Power Control 1 (Address 02h)” on page 40, “MIC Control (Address 05h)” on page 44 “ADCx
Input Select, Invert & Mute (Address 07h)” on page 47.
4.3.6 MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,
allowing it to be used for microphone level signals without the need for any external gain. The PGA must
be powered up when using the MIC pre-amp.
The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software
Controls:
“Power Control 1 (Address 02h)” on page 40, “ADCx Input Select, Invert & Mute (Address 07h)” on
page 47, “ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on
page 49, “MIC Control (Address 05h)” on page 44.
DS700PP1 25
4.3.7 Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases
the digital attenuation levels at a programmable attack rate and maintains the resulting level below the
maximum threshold.
When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first
and the PGA gain is then increased at a programmable release rate and maintains the resulting level
above the minimum threshold.
Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set
in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains
the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds.
CS53L21
Software
Controls:
MIN[2:0]
below full scale
(after ALC)
MIN[2:0]
below full scale
Input
ALC
Output
“ALC Enable & Attack Rate (Address 1Ch)” on page 52, “ALC Release Rate (Address 1Dh)” on
page 52, “ALC Threshold (Address 1Eh)” on page 53, “ALCX & PGAX Control: ALCA, PGAA
(Address 0Ah) & ALCB, PGAB (Address 0Bh)” on page 49.
MAX[2:0]
below full scale
ADCx_ATT[7:0] and
PGA Gain and/or
Attenuator
RRATE[5:0]
ARATE[5 :0]
PGAx_VOL[4:0] volume
controls should NOT be
adjusted manually when
ALCx is enabled.
MAX[2:0]
below full scale
Figure 10. ALC
26 DS700PP1
4.3.8 Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Ramp-down time to the maximum setting is affected by the SOFTx bit.
Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog inputs are configured for differential signals (see “Differential Inputs” on page 23“Differential Inputs” on
page 23), enable the NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold.
CS53L21
Software
Controls:
“Noise Gate Configuration & Misc. (Address 1Fh)” on page 54, “ADC Control (Address 06h)” on
page 45.
Output
(dB)
1
=
N
E
G
N
-52 dB
0
=
N
E
G
N
-96 -40
THRESH[2:0]
-64 dB
-80 dB
Maximum Attenuation*
Input (dB)
Figure 11. Noise Gate Attenuation
DS700PP1 27
4.4 Signal Processing Engine
The SPE provides various signal processing functions that apply to the ADC data.
CS53L21
Software
Controls:
“SPE Control (Address 09h)” on page 48
INPUTS FROM ADCA
and ADCB
SIGNAL PROCESSING ENGINE (SPE)
MUTE_ADCMIXA
MUTE_ADCMIXB
ADCMIXA_VOL[6:0]
ADCMIXB_VOL[6:0]
+12dB/-51.5dB
0.5dB steps
VOL
ADCA[1:0]
ADCB[1:0]
Channel
Swap
4.4.1 Volume Controls
The digital volume control functions offer independent control over the ADC signal path into the mixer.
The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft
ramp/zero cross settings.
The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal
to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the
respective volume control register. The attenuation is ramped up and down at the rate specified by the
SPE_SZC[1:0] bits.
Software
Controls:
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 51
4.4.2 Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for the ADC data. This mix
allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap.
Software
Controls:
“Channel Mixer (Address 18h)” on page 51.
Digital Mix to ADC
Serial Interface
Figure 12. Signal Processing Engine
28 DS700PP1
4.5 Serial Port Clocking
The A/D serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
CS53L21
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S
) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in Hardware Mode.
Software
Control:
“MIC Power Control & Speed Control (Address 03h)” on page 41, “SPE Control
(Address 09h)” on page 48.
Pin Setting Selection
Hardware
Control:
“SDOUT, M/S” pin 29
“MCLKDIV2” pin 2
47 kΩ Pull-down
47 kΩ Pull-up
LO
HI
Slave
Master
No Divide
MCLK is divided by 2 prior
to all internal circuitry.
DS700PP1 29
4.5.1 Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Auto-Detect QSM HSM SSM DSM
Disabled
(Software
Mode only)
Enabled
*MCLKDIV2 must be enabled.
4.5.2 Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
512, 768, 1024, 1536,
2048, 3072
1024, 1536, 2048*,
3072*
CS53L21
256, 384, 512, 768,
1024, 1536
512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384*
Table 3. MCLK/LRCK Ratios
128, 192, 256, 384,
512, 768
128, 192, 256, 384
MCLK
÷ 1
÷ 2
0
1
MCLKDIV2
Figure 13. Master Mode Timing
÷ 128
÷ 128
÷ 256
÷ 512
÷ 2
÷ 2
÷ 4
÷ 8
Double
Speed
Single
Speed
Half
Speed
Quarter
Speed
Double
Speed
Single
Speed
Half
Speed
Quarter
Speed
00
01
10
11
SPEED[1:0]
00
01
10
11
LRCK Output
(Equal to Fs)
SCLK Output
30 DS700PP1
4.5.3 High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-impedance state, allowing another device to transmit serial port data without bus contention..
CS53L21
CS53L21
Transmitting Device #1
3ST_SP
Figure 14. Tri-State Serial Port
4.5.4 Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates.
4.6 Digital Interface Formats
The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit depths from
16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK. Figures 15-16 illustrate
the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 14 for exact
timing relationship between clocks and data.
Transmitting Device #2
SDOUT
SCLK/LRCK
Receiving Device
Software
Control:
“Interface Control (Address 04h)” on page 43.
Pin Setting Selection
Hardware
Control:
“I²S/LJ” pin 3
LO
HI
Left-Justified Interface
I²S Interface
LRCK
SCLK
SDIN
MSB LSB
DS700PP1 31
Left Channel Right Channel
MSB
AOUTA / AINxA
Figure 15. I²S Format
AOUTB / AINxB
LSB
MSB
CS53L21
LRCK
SCLK
SDIN
MSB LSB
4.7 Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 33. The A/D enters a
Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators
and control port registers are reset. The internal voltage reference, ADC and switched-capacitor low-pass
filters are powered down.
The device will remain in the Power-Down state until the RESET
cessible once RESET
in “Software Mode” on page 34. If a valid write sequence to the control port is not made within approximately
10 ms, the A/D will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+ will begin powering
up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted
state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
Left Channel Right Channel
AOUTA / AINxA
MSB
AOUTB / AINxB
Figure 16. Left-Justified Format
LSB
pin is brought high. The control port is ac-
is high and the desired register settings can be loaded per the interface descriptions
MSB
4.8 Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6. Set the PDN bit to ‘0’b.
7. Apply LRCK and SCLK for normal operation to begin.
8. Bring RESET
prevent power glitch related issues.
high. After approximately 10 ms, the device will enter Hardware Mode.
low if the analog or digital supplies drop below the recommended operating condition to
32 DS700PP1
4.9 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the A/D in standby,
1. Mute the ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until it reaches a fully
muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to
disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
3. Bring RESET
low.
No Power
1. No audio signal
generated.
CS53L21
Power Off Transition
1. Audible pops.
Reset Transition
1. Pops suppressed .
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Regi sters reset
to default.
RESET = Low?
Control Port
Control Port Valid
No
Write Seq. within
Hardware Mode
Minimal feature
set support.
No
Active
10 ms?
Yes
Yes
Software Mode
Registers setup to
desired settings .
PDN bit = '1'b?
Valid
MCLK Applied?
20 ms delay
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
ADC Initialization
2048 internal
MCLK cycle delay
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
No
Valid
MCLK/LRCK
Ratio?
Yes
Yes
No
No
Standby Mode
1. No audio signal gener ated.
2. Control Port Regi sters retain
settings.
ERROR: Power removed
RESET = Low
Audio signal generat ed per control port or stand-
Normal Operation
alone settings.
PDN bit set to '1'b
(software mode only)
Figure 17. Initialization Flow Chart
DS700PP1 33
4.10 Software Mode
The control port is used to access the registers allowing the A/D to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the
audio sample rates. However, to avoid potential interference problems, the control port pins should remain
static if no operation is required.
The control port operates in two modes: SPI and I²C, with the A/D acting as a slave device. Software Mode
is selected if there is a high-to-low transition on the AD0/CS
I²C Mode is selected by connecting the AD0/CS
selecting the desired AD0 bit address state.
4.10.1 SPI Control
In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the
CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored.
CS53L21
pin after the RESET pin has been brought high.
pin through a resistor to VL or DGND, thereby permanently
Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
CS
0 1 2 3 8 9 12 16 1710 11 13 14 15
CCLK
CDIN
4.10.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS
through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS53L21 is being
reset.
), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
4 5 6 7
CHIP ADDRESS (WRITE) MAP BYTE DATA
1 0 0 1 0 1 0 0
Figure 18. Control Port Timing in SPI Mode
INCR 6 5 4 3 2 1 0 7 6 1 0
DATA +n
7 6 1 0
pin. Pin AD0 forms the least significant bit of the chip address and should be connected
low.
The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W
bit (high for a read, low
for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a
CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W
bit. If the operation is a write,
the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the
operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-
34 DS700PP1
CS53L21
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated
by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input
to the CS53L21 from the microcontroller after each transmitted byte.
SCL
SDA
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
4 5 6 7 24 25
26
SCL
DATA +n
SDA
CHIP ADDRESS (WRITE) MAP BYTE DATA
1 0 0 1 0 1 AD0 0
START
INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
ACK
DATA +1
Figure 19. Control Port Timing, I²C Write
2 3 10 11 17 18 19 25
CHIP ADDRESS (WRITE)
1 0 0 1 0 1 AD0 0
START
MAP BYTE
INCR 6 5 4 3 2 1 0
ACK
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24
STOP
ACK
START
CHIP ADDRESS (READ)
1 0 0 1 0 1 AD0 1
26 27 28
DATA
7 0 7 0 7 0
ACK
DATA +1
ACK
DATA + n
Figure 20. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
ACKACKACK
STOP
NO
ACK
STOP
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
DS700PP1 35
4.10.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.10.3.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
CS53L21
36 DS700PP1
CS53L21
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
AddrFunction7 6543210
01h ID Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
p40
default
02h Power Ctl. 1 Reserved Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
p40
default
03h Speed Ctl. &
Power Ctl. 2
p41
default
04h Interface Ctl. Reserved M/S
p43
default
05h MIC Control
& Misc.
p44
default
06h
ADC Control
p45
default
07h ADC Input
Select
, Invert, Mute
p47
default
08h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
09h SPE Control Reserved SPE_
p48
default
0Ah ALCA SZC &
PGAA Volume
p49
default
0Bh ALCB SZC &
PGAB Volume
p49
default
0Ch ADCA Atten-
uator
p50
default
0Dh ADCB Atten-
uator
1 1011001
0 1(See Note
2 on page
40)
AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_
1 0101110
0 0000000
ADC_SNGVOL ADCB_
0 0000000
ADCB_HPFENADCB_HP
1 0100000
AINB_MUX1 AINB_MUX0AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_
0 0000000
0 1100000
0 0000110
ALCA_SR
DIS
0 0000000
ALCB_SR
DIS
0 0000000
ADCA_
ATT 7
0 0000000
ADCB_
ATT 7
DBOOST
FRZ
ENABLE
ALCA_ZC
DIS
ALCB_ZC
DIS
ADCA_
ATT 6
ADCB_
ATT 6
1(See Note 2
on page 40)
Reserved Reserved Reserved ADC_I²S/LJ DIGMIX MICMIX
ADCA_
DBOOST
ADCA_HPFENADCA_HP
FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0
Reserved PGAA
Reserved PGAB
ADCA_
ATT 5
ADCB_
ATT 5
00000
MCLKDIV2
MICBIAS
MICBIAS_
SEL
FRZ
VOL4
VOL4
ADCA_
ATT 4
ADCB_
ATT 4
MICBIAS_
LVL 1
SOFTB ZCROSSB SOFTA ZCROSSA
PGAA
VOL3
PGAB
VOL3
ADCA_
ATT3
ADCB_
ATT3
MICBIAS_
LVL 0
PGAA
VOL2
PGAB
VOL2
ADCA_
ATT 2
ADCB_
ATT 2
MICB_
BOOST
MUTE
PGAA
VOL1
PGAB
VOL1
ADCA_
ATT 1
ADCB_
ATT 1
MICA_
BOOST
ADCA_
MUTE
PGAA
VOL0
PGAB
VOL0
ADCA_
ATT 0
ADCB_
ATT 0
DS700PP1 37
CS53L21
AddrFunction7 6543210
p50
default
0Eh Vol. Control
ADCMIXA
p51
default
0Fh Vol. Control
ADCMIXB
p51
default
10h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
11h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
12h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
14h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
15h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
16h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
17h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
18h ADC Chan-
nel Mixer
p51
default
19h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
1Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0000000
MUTE_ADC
MIXA
1 0000000
MUTE_ADC
MIXB
1 0000000
1 0000000
1 0000000
0 0000000
0 0000000
0 0000000
1 0001000
0 0000000
0 0000000
Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0
0 0000000
0 0000000
ADCMIXA
VOL6
ADCMIXB
VOL6
ADCMIXA
VOL5
ADCMIXB
VOL5
ADCMIXA
VOL4
ADCMIXB
VOL4
ADCMIXA
VOL3
ADCMIXB
VOL3
ADCMIXA
VOL2
ADCMIXB
VOL2
ADCMIXA
VOL1
ADCMIXB
VOL1
ADCMIXA
VOL0
ADCMIXB
VOL0
default
1Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
1Ch ALC Enable
& Attack Rate
p52
default
0 1111111
0 0000000
ALC_ENB ALC_ENA ALC_ARATE5AALC_RATE
4
0 0000000
ALC_ARATE3ALC_ARATE2ALC_ARATE1ALC_ARATE
0
38 DS700PP1
CS53L21
AddrFunction7 6543210
1Dh ALC Release
Rate
p52
default
1Eh ALC Thresh-
old
p53
default
1Fh Noise Gate
Config
p54
default
20h Status Reserved SP_CLK
p55
default
21h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default
Reserved Reserved ALC_RRATE5ALC_RRATE4ALC_RRATE3ALC_RRATE2ALC_RRATE1ALC_RRATE
0
0 0111111
MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved
0 0000000
NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
0 0000000
SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL
ERR
0 0000000
0 1010000
DS700PP1 39
CS53L21
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
76543210
Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS53L21. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2 Power Control 1 (Address 02h)
76543210
Reserved Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
Notes:
1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the A/D has fully powered up will mute
the selected channel without achieving any power savings.
2. Reserved bits 5 and 6 should always be set “high” by the user to minimize power consumption during
normal operation.
Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit.
40 DS700PP1
CS53L21
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control
1 (Address 02h) Note 1 above.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 47 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page
40.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire A/D will enter a low-power state when this function is enabled. The contents of the control port
registers are retained in this mode.
6.3 MIC Power Control & Speed Control (Address 03h)
76543210
AUTO SPEED1 SPEED0 3-ST_SP PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the A/D when operating as a slave. When
AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 30. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
DS700PP1 41
CS53L21
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the A/D in Master or Slave Mode. QSM is optimized for 8 kHz sample
rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled
(see Auto-Detect Speed Mode (AUTO) above).
Tri-State Serial Port Interface (3ST_SP)
Default: 0
0 - Disable
1 - Enable
Function:
When enabled and the device is configured as a master, all serial port outputs (clocks and data) are placed
in a high impedance state. If the serial port is configured as a slave, only the SDOUT pin will be placed in a
high-impedance state. The other signals will remain as inputs.
Power Down MIC X (PDN_MICX)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone pre-amplifier for channel x will be in a power-down state.
Power Down MIC BIAS (PDN_MICBIAS)
Default: 1
0 - Disable
1 - Enable
Function:
When enabled, the microphone bias circuit will be in a power-down state.
MCLK Divide By 2 (MCLKDIV2)
Default: 0
0 - Disabled
1 - Divide by 2
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
42 DS700PP1
CS53L21
6.4 Interface Control (Address 04h)
76543210
Reserved M/S
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
Reserved Reserved Reserved ADC_I²S/LJ DIGMIX MICMIX
DS700PP1 43
CS53L21
ADC I²S or Left-Justified (ADC_I²S/LJ)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in this section “Digital Interface Formats” on page 31.
Digital Mix (DIGMIX)
Default: 0
DIGMIX SPE_ENABLE Mix Selected
0 x ADC data to ADC serial port, SDOUT data.
1
Function:
Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either “raw” ADC data or SPE processed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional.
0 Reserved
1 SPE Processed ADC data to ADC serial port, SDOUT data.
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
6.5 MIC Control (Address 05h)
76543210
ADC_SNGVOL ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 MICB_BOOST MICA_BOOST
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
44 DS700PP1
CS53L21
ADCx 20 dB Digital Boost (ADCx_DBOOST)
Default: 0
0 - Disabled
1 - Enabled
Function:
Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path.
MIC Bias Select (MICBIAS_SEL)
Default: 0
0 - MICBIAS on AIN3B/MICIN2 pin
1 - MICBIAS on AIN2B pin
Function:
Determines the output pin for the internally generated MICBIAS signal. If set to ‘0’b, the MICBIAS is output
on the AIN3B/MICIN2 pin. If set to ‘1’b, the MICBIAS is output on the AIN2B pin.
MIC Bias Level (MICBIAS_LVL[1:0])
Default: 00
00 - 0.8 x VA
01 - 0.7 x VA
10 - 0.6 x VA
11 - 0.5 x VA
Function:
Determines the output voltage level of the MICBIAS output.
MIC X Preamplifier Boost (MICX_BOOST)
Default: 0
0 - +16 dB Gain
1 - +32 dB Gain
Function:
Determines the amount of gain applied to the microphone preamplifier for channel x.
6.6 ADC Control (Address 06h)
76543210
ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ SOFTB ZCROSSB SOFTA ZCROSSA
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1
0 - High-pass filter is disabled
1 - High-pass filter is enabled
Function:
When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter
will be disabled. For DC measurements, this bit must be cleared to ‘0’. “ADC Digital Filter Characteristics”
on page 14.
DS700PP1 45
CS53L21
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0
0 - Continuous DC Subtraction
1 - Frozen DC Subtraction
Function:
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to ‘1’. See “ADC Digital Filter Characteristics” on page 14.
Soft Ramp CHX Control (SOFTX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital attenuation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period.
PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB
steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible
artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function
is independently monitored and implemented for each channel.
Soft Ramp & Zero Cross Enabled
When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps
and be implemented on a signal zero crossing.
The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
SOFTx ZCROSSx Analog PGA Volume
Digital Attenuator (ADCx_ATT[7:0])
(PGAx_VOL[4:0])
00
01
10
11
Volume changes immediately. Volume changes immediately.
Volume changes at next zero cross time. Volume changes immediately.
Volume changes in 0.5 dB steps. Change volume in 0.125 dB steps.
Volume changes in 0.5 dB steps at every
signal zero-cross.
Change volume in 0.125 dB steps.
46 DS700PP1
CS53L21
6.7 ADCx Input Select, Invert & Mute (Address 07h)
76543210
AINB_MUX1 AINB_MUX0 AINA_MUX1 AINA_MUX0 INV_ADCB INV_ADCA ADCB_MUTE ADCA_MUTE
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
PDN_PGAx AINx_MUX[1:0] Selected Path to ADC
0 00 AIN1x-->PGAx
0 01 AIN2x-->PGAx
0 10 AIN3x/MICINx-->PGAx
0 11 AIN3x/MICINx-->Pre-Amp
100AIN1x
101AIN2x
1 10 AIN3x/MICINx
1 11 Reserved
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See Figure 21.
(+16/+32 dB Gain)-->PGAx
AIN1x
AIN2x
AIN1x
AIN2x
AIN3x / MICINx
+16/
32 dB
MUX
AIN3x
PGA
Decoder
AINx_MUX[1:0]
PDN_PGAx
Figure 21. AIN & PGA Selection
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
MUX
ADC
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
DS700PP1 47
CS53L21
6.8 SPE Control (Address 09h)
76543210
Reserved SPE_ENABLE FREEZE Reserved Reserved Reserved SPE_SZC1 SPE_SZC0
SPE_ENABLE
Default: 0
0 - Reserved
1 - ADC Serial Port to SPE
Function:
Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to
be functional.
Freeze Controls (FREEZE)
Default: 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then
disable the FREEZE bit.
48 DS700PP1
CS53L21
SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
Soft Ramp
Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented
by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4
left/right clock periods.
Soft Ramp on Zero Crossing
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if
the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
76543210
ALCX_SRDIS ALCX_ZCDIS Reserved PGAX_VOL4 PGAX_VOL3 PGAX_VOL2 PGAX_VOL1 PGAX_VOL0
ALCX Soft Ramp Disable (ALCX_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be
dictated by the soft ramp setting. ALC volume-level changes will take effect in one step.
DS700PP1 49
CS53L21
ALCX Zero Cross Disable (ALCX_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not
be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step.
PGA X Gain Control (PGAX_VOL[4:0])
Default: 00000
Binary Code Volume Setting
11000 +12 dB
··· ···
01010 +5 dB
··· ···
00000 0 dB
11111 - 0 . 5 d B
11110 -1 dB
··· ···
11001 -3 dB
11010 -3 dB
Function:
The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are
decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft &
Zero Cross bits (ALCX_SRDIS & ALCX_ZCDIS).
Note: When the ALC is enabled, the PGA is automatically controlled and should not be adjusted manu-
ally.
6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
76543210
ADCx_ATT7 ADCx_ATT6 ADCx_ATT5 ADCx_ATT4 ADCx_ATT3 ADCx_ATT2 ADCx_ATT1 ADCx_ATT0
ADCX Attenuation Control (ADCX_ATT[7:0])
Default: 00h
Binary Code Volume Setting
0111 1111 0 d B
··· ···
0000 0000 0 dB
1111 1111 -1 d B
1111 1110 -2 dB
··· ···
1010 0000 -96 dB
··· ···
1000 0000 -96 dB
50 DS700PP1
CS53L21
Function:
The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits
(SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table
above.
Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)
7 6543210
MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0
Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register.
ADCX Mixer Channel Mute (MUTE_ADCMIXX)
Default: 1
0 - Disabled
1 - Enabled
Function:
The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by
the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]).
ADCX Mixer Volume Control (ADCMIXX_VOL[6:0])
Default = 000 0000
Binary Code Volume Setting
001 1000 +12.0 dB
··· ···
000 0000 0 dB
111 1111 -0.5 dB
111 1110 -1.0 dB
··· ···
001 1001 -51.5 dB
Function:
The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the
SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the
table above.
6.12 Channel Mixer (Address 18h)
76543210
Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0
Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register.
Channel Mixer (ADCx[1:0])
Default: 00
ADCA[1:0] SDOUT ADCB[1:0] SDOUT
00 L 00 R
DS700PP1 51
CS53L21
ADCA[1:0] SDOUT ADCB[1:0] SDOUT
01 01
10 10
11 R 11 L
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
6.13 ALC Enable & Attack Rate (Address 1Ch)
76543210
ALC_ENB ALC_ENA ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
ALC Enable (ALC_ENX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables automatic level control for ADC channel x.
LR+
------------
2
LR+
------------
2
Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
ALC Attack Rate (ARATE[5:0])
Default: 000000
Binary Code Attack Time
000000 Fastest Attack
··· ···
111111 Slow e st A t tack
Function:
Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the
ALC threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSSx bit settings unless the disable bit for each function is enabled.
6.14 ALC Release Rate (Address 1Dh)
76543210
Reserved Reserved ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
ALC Release Rate (RRATE[5:0])
Default: 111111
Binary Code Release Time
000000 Fastest Release
··· ···
111111 S l o w e s t R e le a s e
52 DS700PP1
CS53L21
Function:
Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting
in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting.
The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSS bit settings unless the disable bit for each function is enabled.
6.15 ALC Threshold (Address 1Eh)
76543210
MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved
Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
100 -12
101 -18
110 -24
111 -3 0
Function:
Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack
rate.
Minimum Threshold (MIN[2:0])
Default: 000
Threshold
MIN[2:0]
Setting
(dB)
000 0
001 -3
010 -6
011 -9
100 -12
101 -18
110 -24
111 -3 0
Function:
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set
in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as
a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the
minimum setting. This provides a more natural sound as the ALC attacks and releases.
DS700PP1 53
CS53L21
6.16 Noise Gate Configuration & Misc. (Address 1Fh)
76543210
NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
Noise Gate Channel Gang (NG_ALL)
Default: 0
0 - Disabled
1 - Enabled
Function:
Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect.
Noise Gate Enable (NG_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables the noise gate. Maximum attenuation is relative to all gain settings applied.
Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])
Default: 000
THRESH[2:0]
000 -64 dB -34 dB
001 -67 dB -37 dB
010 -70 dB -40 dB
011 -73 dB -43 dB
100 -76 dB -46 dB
101 -82 dB -52 dB
110 Reserved -58 dB
111 Reserved -64 dB
Minimum Setting
(NG_BOOST = ‘0’b)
Minimum Setting
(NG_BOOST = ‘1’b)
Function:
Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96
dB. NG_BOOST = ‘1’b adds 30 dB to the threshold settings.
Noise Gate Delay Timing (NGDELAY[1:0])
Default: 00
00 - 50 ms
01 - 100 ms
10 - 150 ms
11 - 200 ms
Function:
Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx &
ZCROSS bit settings unless the disable bit for each function is enabled.
54 DS700PP1
CS53L21
6.17 Status (Address 20h) (Read Only)
76543210
Reserved SP_CLKERR Reserved Reserved Reserved Reserved ADCA_OVFL ADCB_OVFL
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” on page 29“Serial Port Clocking” on
page 29 for valid clock ratios.
Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
ADC Overflow (ADCX_OVFL)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the
associated ADC’s.
DS700PP1 55
7. ANALOG PERFORMANCE PLOTS
60
7.1 ADC_FILT+ Capacitor Effects on THD+N
The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion +
noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N
at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB53L21 using an Audio Precision analyzer.
-
CS53L21
-64
-68
-72
-76
d
B
-80
F
S
-84
-88
-92
-96
-100
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects
1 µF
10 µF
22 µF
Legend –
Capacitor Value on ADC_FILT+
56 DS700PP1
8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
CS53L21
Sample Rate
LRCK (kHz)
8 8.1920 12.2880 16.3840 24.5760
11.025 11.2896 16.9344 22.5792 33.8688
12 12.2880 18.4320 24.5760 36.8640
1024x 1536x 2048x* 3072x*
Sample Rate
LRCK (kHz)
16 8.1920 12.2880 16.3840 24.5760
22.05 11.2896 16.9344 22.5792 33.8688
24 12.2880 18.4320 24.5760 36.8640
512x 768x 1024x* 1536x*
Sample Rate
LRCK (kHz)
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
256x 384x 512x* 768x*
Sample Rate
LRCK (kHz)
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
128x 192x 256x* 384x*
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
*The”MCLKDIV2” pin 4 must be set HI.
DS700PP1 57
8.2 Auto Detect Disabled
CS53L21
Sample Rate
LRCK (kHz)
8 - 6.1440 8.1920 12.2880 16.3840 24.5760
11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688
12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
512x 768x 1024x 1536x 2048x 3072x
Sample Rate
LRCK (kHz)
16 - 6.1440 8.1920 12.2880 16.3840 24.5760
22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688
24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
256x 384x 512x 768x 1024x 1536x
Sample Rate
LRCK (kHz)
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
256x 384x 512x 768x
Sample Rate
LRCK (kHz)
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
128x 192x 256x 384x
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
MCLK (MHz)
58 DS700PP1
9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-resolution converter, the CS53L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended
power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be
run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite
bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply
arrangements.
9.2 QFN Thermal Pad
The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration.
CS53L21
DS700PP1 59
10.DIGITAL FILTERS
Figure 23. ADC Passband Ripple Figure 24. ADC Stopband Rejection
CS53L21
Figure 25. ADC Transition Band Figure 26. ADC Transition Band Detail
60 DS700PP1
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
CS53L21
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS700PP1 61
12.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
CS53L21
e Pin #1 Corner
Pin #1 Corner
D
Top View
b
E
Side View
E2
A1
A
L
D2
Bottom View
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A----0.0394----1.001
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.1969 BSC 5.00 BSC 1
D2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
E 0.1969 BSC 5.00 BSC 1
E2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board
θ
JA
-
-
62 DS700PP1
52
38
°C/Watt
-
CS53L21
13.ORDERING INFORMATION
Product Description Package Pb-Free Grade Temp Range Container Order #
Rail CS53L21-CNZ
Tape & Reel CS53L21-CNZR
Rail CS53L21-DNZ
Tape & Reel CS53L21-DNZR
CS53L21 Low-Power Stereo A/D 32L-QFN Yes
CDB53L21
CS53L21 Evaluation
Board
- No - - - CDB53L21
Commercial -10 to +70° C
Automotive -40 to +85° C
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
2. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter
Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the
Audio Engineering Society, September 1997.
3. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signo-
re, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention
of the Audio Engineering Society, November 1988.
4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and
on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.
5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Applica-
tion Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society,
October 1989.
6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven
Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com
DS700PP1 63
15.REVISION HISTORY
Revision Changes
A1
PP1
Initial Release
Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 11.
Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Characteristics
(Commercial - CNZ)” on page 12.
Corrected Interchannel Gain Mismatch specification in “Analog Characteristics (Commercial - CNZ)” on page 12
and “Analog Characteristics (Automotive - DNZ)” on page 13.
Adjusted ADC full scale input voltage specification in “Analog Characteristics (Commercial - CNZ)” on page 12
and “Analog Characteristics (Automotive - DNZ)” on page 13.
Removed t
Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 14.
Adjusted timing specifications t
“Switching Specifications - Serial Port” on page 14.
Adjusted I²C timing specifications t
Modified the Typ. Conn. HW and SW figures by adding a pull-up to the VA_HP pin and changed AFILTA, B cap
values from 1000 pF to 150 pF.
Modified the Pin Descriptions table description for pin 5 to add a pull-up.
Adjusted High-Level Input Voltage specifications V
table in section “Digital Interface Specifications & Characteristics” on page 18.
Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 7 on page 22.
Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 26.
Modified step 2 of the “Recommended Power-Down Sequence” on page 33.
Corrected default values for ALC and Limiter Release Rates shown in “Register Quick Reference” on page 37.
Corrected default value for the SPE_SZC bits in “SPE Control (Address 09h)” on page 48.
Corrected ADC Filter Response shown in Figures 23, 24, 25, and 26 on page 60.
Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 44.
timing specification from table in section “Switching Specifications - Serial Port” on page 14.
d
from 40 ns to 52 ns and t
d(MSB)
from 1000 ns to 3450 ns in table in section “” on page 15.
ack
from 0.65VL to 0.68VL and V
IH
s(SDO-SK)
CS53L21
from 30 ns to 20 ns in table in section
from 0.35VL to 0.32VL in
IL
64 DS700PP1
CS53L21
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and
is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be
made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
DS700PP1 65
CS53L21
66 DS700PP1
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