Cirrus Logic CS53L21 User Manual
CS53L21
Low Power, Stereo Analog to Digital Converter
FEATURES
98 dB Dynamic Range (A-wtd)
-88 dB THD+N
Analog Gain Controls
– +32 dB or +16 dB MIC Pre-Amplifiers
– Analog Programmable Gain Amplifier
(PGA)
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold and
Attack/Release Rates
Independent Left/Right Channel Control
Digital Volume Control
High-Pass Filter Disable for DC Measurements
Stereo 3:1 Analog Input MUX
Dual MIC Inputs
– Programmable, Low Noise MIC Bias Levels
– Differential MIC Mix for Common Mode
Noise Rejection
Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
SYSTEM FEATURES
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
– Stereo Record (ADC): 8.72 mW @ 1.8 V
– Stereo Record (MIC to PGA and ADC):
13.73 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– ADC, MIC Pre-Amplifier, PGA
Software Mode (I²C
Hardware Mode (Stand-Alone Control)
Flexible Clocking Options
– Master or Slave Operation
Digital Routing Mixes
– Mono Mixes
®
& SPI™ Control)
1.8 V to 3.3 V
PCM Serial Interface
Digital
Signal
Processing
Engine
High Pass
Filters
Register
Configuration
Hardware Mode
2
C & SPI
or I
Software Mode
Control Data
Reset
Serial Audio
Output
Level Translator
Preliminary Product Information
http://www.cirrus.com
1.8 V to 2.5 V
ALC
ALC
Volume
Controls
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
MUX
MUX
PGA
PGA
MUX
+32 dB
+32 dB
MIC
Bias
Stereo Input 1
Stereo Input 2
Stereo Input 3 /
Mic Input 1 & 2
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
DS700PP1
MAY ‘06
CS53L21
APPLICATIONS
Portable Audio Players
Digital Microphones
Digital Voice Recorders
Voice Recognition Systems
Audio/Video Capture Cards
GENERAL DESCRIPTION
The CS53L21 is a highly integrated, 24-bit, 96 kHz, low
power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment
between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system
applications.
The ADC input path allows independent channel control
of a number of features. An input multiplexer selects between line-level or microphone-level inputs for each
channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low
noise MIC bias voltage supply. A PGA is available for
line or microphone inputs and provides analog gain with
soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp
transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels
appropriately.
The Signal Processing Engine (SPE) controls left/right
channel volume mixing, channel swap and channel
mute functions. All volume-level changes may be configured to occur on soft ramp and zero cross transitions.
The CS53L21 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85° C). The CDB53L21 Customer Demonstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 63 for complete details.
In addition to its many features, the CS53L21 operates
from a low-voltage analog and digital core, making this
A/D ideal for portable systems that require extremely
low power consumption in a minimal amount of space.
2 DS700PP1
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11
SPECIFIED OPERATING CONDITIONS ............................................................................................. 11
ABSOLUTE MAXIMUM RATINGS .......................................................................................................11
ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .................................................................... 12
ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................................... 13
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 14
SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 16
SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 17
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 18
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 18
POWER CONSUMPTION .................................................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ......................................................................................................................................... 20
4.1.1 Architecture ........................................................................................................................... 20
4.1.2 Line & MIC Inputs .................................................................................................................. 20
4.1.3 Signal Processing Engine ..................................................................................................... 20
4.1.4 Device Control (Hardware or Software Mode) ...................................................................... 20
4.1.5 Power Management .............................................................................................................. 20
4.2 Hardware Mode .............................................................................................................................. 21
4.3 Analog Inputs ................................................................................................................................. 22
4.3.1 Digital Code, Offset & DC Measurement ............................................................................... 22
4.3.2 High-Pass Filter and DC Offset Calibration ........................................................................... 23
4.3.3 Digital Routing ....................................................................................................................... 23
4.3.4 Differential Inputs .................................................................................................................. 23
4.3.4.1 External Passive Components ................................................................................... 23
4.3.5 Analog Input Multiplexer ........................................................................................................ 25
4.3.6 MIC & PGA Gain ................................................................................................................... 25
4.3.7 Automatic Level Control (ALC) .............................................................................................. 26
4.3.8 Noise Gate ............................................................................................................................ 27
4.4 Signal Processing Engine ............................................................................................................... 28
4.4.1 Volume Controls .................................................................................................................... 28
4.4.2 Mono Channel Mixer ............................................................................................................. 28
4.5 Serial Port Clocking ........................................................................................................................ 29
4.5.1 Slave ..................................................................................................................................... 30
4.5.2 Master ................................................................................................................................... 30
4.5.3 High-Impedance Digital Output ............................................................................................. 31
4.5.4 Quarter- and Half-Speed Mode .............................................................................................31
4.6 Digital Interface Formats ................................................................................................................ 31
4.7 Initialization ..................................................................................................................................... 32
4.8 Recommended Power-Up Sequence ............................................................................................. 32
4.9 Recommended Power-Down Sequence ........................................................................................ 33
4.10 Software Mode ............................................................................................................................. 34
4.10.1 SPI Control .......................................................................................................................... 34
4.10.2 I²C Control ........................................................................................................................... 34
4.10.3 Memory Address Pointer (MAP) .......................................................................................... 3
4.10.3.1 Map Increment (INCR) ............................................................................................. 36
5. REGISTER QUICK REFERENCE ........................................................................................................ 37
6. REGISTER DESCRIPTION .................................................................................................................. 40
CS53L21
6
DS700PP1 3
CS53L21
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40
6.2 Power Control 1 (Address 02h) ...................................................................................................... 40
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41
6.4 Interface Control (Address 04h) ..................................................................................................... 43
6.5 MIC Control (Address 05h) ............................................................................................................. 44
6.6 ADC Control (Address 06h) ............................................................................................................ 45
6.7 ADCx Input Select, Invert & Mute (Address 07h) ........................................................................... 47
6.8 SPE Control (Address 09h) ............................................................................................................ 48
6.9 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ................. 49
6.10 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ................................................ 50
6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) .............................. 51
6.12 Channel Mixer (Address 18h) ....................................................................................................... 51
6.13 ALC Enable & Attack Rate (Address 1Ch) ................................................................................... 52
6.14 ALC Release Rate (Address 1Dh) ................................................................................................ 52
6.15 ALC Threshold (Address 1Eh) ...................................................................................................... 53
6.16 Noise Gate Configuration & Misc. (Address 1Fh) ......................................................................... 54
6.17 Status (Address 20h) (Read Only) ............................................................................................... 55
7. ANALOG PERFORMANCE PLOTS ....................................................................................................56
7.1 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 56
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57
8.1 Auto Detect Enabled ....................................................................................................................... 57
8.2 Auto Detect Disabled ...................................................................................................................... 58
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59
9.1 Power Supply, Grounding ............................................................................................................... 59
9.2 QFN Thermal Pad .......................................................................................................................... 59
10. DIGITAL FILTERS .............................................................................................................................. 60
11. PARAMETER DEFINITIONS .............................................................................................................. 61
12. PACKAGE DIMENSIONS ................................................................................................................. 62
THERMAL CHARACTERISTICS .......................................................................................................... 62
13. ORDERING INFORMATION ............................................................................................................. 63
14. REFERENCES .................................................................................................................................... 63
15. REVISION HISTORY ......................................................................................................................... 64
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10
Figure 3.Serial Audio Interface Slave Mode Timing .................................................................................. 15
Figure 4.Serial Audio Interface Master Mode Timing ................................................................................ 15
Figure 5.Control Port Timing - I²C ............................................................................................................. 16
Figure 6.Control Port Timing - SPI Format ................................................................................................ 17
Figure 7.Analog Input Architecture ............................................................................................................ 22
Figure 8.MIC Input Mix w/Common Mode Rejection .................................................................................24
Figure 9.Differential Input .......................................................................................................................... 24
Figure 10.ALC ........................................................................................................................................... 26
Figure 11.Noise Gate Attenuation ............................................................................................................. 27
Figure 12.Signal Processing Engine ......................................................................................................... 28
Figure 13.Master Mode Timing ................................................................................................................. 30
Figure 14.Tri-State Serial Port .................................................................................................................. 31
Figure 15.I²S Format ................................................................................................................................. 31
Figure 16.Left-Justified Format ................................................................................................................. 32
Figure 17.Initialization Flow Chart ............................................................................................................. 33
Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34
Figure 19.Control Port Timing, I²C Write ................................................................................................... 35
Figure 20.Control Port Timing, I²C Read ................................................................................................... 35
4 DS700PP1
Figure 21.AIN & PGA Selection ................................................................................................................ 47
Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56
Figure 23.ADC Passband Ripple .............................................................................................................. 60
Figure 24.ADC Stopband Rejection .......................................................................................................... 60
Figure 25.ADC Transition Band ................................................................................................................ 60
Figure 26.ADC Transition Band Detail ...................................................................................................... 60
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Hardware Mode Feature Summary ............................................................................................. 21
Table 3. MCLK/LRCK Ratios .................................................................................................................... 30
CS53L21
DS700PP1 5
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
)
CS53L21
TSTN
LRCK
SDA/CDIN (MCLKDIV2)
SCL/CCLK (I²S/LJ
AD0/CS
(TSTN)
VA_PULLUP
TSTO
AGND
TSTO
SCLK
MCLK
SDOUT (M/S
DGND
303132
29
1
2
)
3
4
5
6
7
8
CS53L21
109
11
NIC
NIC
TSTO
13 14 15 16
12
VA
AGND
VD
TSTO
VL
262728
VQ
Pin Name # Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
LRCK
SDA/CDIN
(MCLKDIV2)
SCL/CCLK
(I²S/LJ)
AD0/CS
(TSTN)
VA_ PULLUP
TSTO
AGND
TSTO
1
serial audio data line.
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
2
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
3
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-
mats for the ADC.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.
4
Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to
DGND for normal operation.
Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA
5
using a 47 kΩ resistor.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
6
nection external to the pin).
7
Analog Ground (Input) - Ground reference for the internal analog section.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
8
nection external to the pin).
RESET
25
FILT+
AIN1B
24
AIN1A
23
AFILTB
22
AFILTA
21
20
AIN2B/BIAS
AIN2A
19
MICIN2/BIAS/AIN3B
18
MICIN1/AIN3A
17
6 DS700PP1
TSTO
NIC
NIC
VA
AGND
TSTO
VQ
FILT+
MICIN1/
AIN3A
MICIN2/
BIAS/AIN3B
AIN2A
AIN2B/BIAS
AFILTA
AFILTB
AIN1A
AIN1B
RESET
VL
VD
DGND
SDOUT
)
(M/S
MCLK
SCLK
TSTN
Thermal Pad
CS53L21
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
9
nection external to the pin).
10
.Not Internally Connected - This pin is not connected internal to the device and may be connected to
11
ground or left “floating”. No other external connection should be made to this pin.
12
Analog Power (Input) - Positive power for the internal analog section.
13
Analog Ground (Input) - Ground reference for the internal analog section.
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
14
nection external to the pin).
15
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
16
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specifi-
17
cation table.
Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics
18
specification table. This pin can also be configured as an output to provide a low noise bias supply for an
external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
Analog Input (Input) -
19
table.
Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specifi-
20
cation table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table.
21
Filter Connection (Output) - Filter connection for the ADC inputs.
22
23
Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification
24
table.
25
Reset (Input) - The device enters a low power mode when this pin is driven low.
Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and
26
host control port. Refer to the Recommended Operating Conditions for appropriate voltages.
27
Digital Power (Input) - Positive power for the internal digital section.
28
Digital Ground (Input) - Ground reference for the internal digital section.
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
29
Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.
30
Master Clock (Input) - Clock source for the delta-sigma modulators.
31
Serial Clock (Input/Output) -- Serial clock for the serial audio interface.
Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal
32
operation.
-
Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59.
The full-scale level is specified in the ADC Analog Characteristics specification
DS700PP1 7
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply.
CS53L21
Pin Name
SW/(HW)
RESET Input
SCL/CCLK
(I²S/LJ)
SDA/CDIN
(MCLKDIV2)
AD0/CS
(DEM)
MCLK Input
LRCK Input/Output
SCLK Input/Output
SDOUT
(M/S)
Input
Input/Output
Input
Input/Output
I/O Driver Receiver
- 1.8 V - 3.3 V
- 1.8 V - 3.3 V, with Hysteresis
1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis
- 1.8 V - 3.3 V
- 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
Table 1. I/O Power Rails
8 DS700PP1
2. TYPICAL CONNECTION DIAGRAMS
CS53L21
+1.8 V or +2.5 V
+1.8 V, +2.5 V
or +3.3 V
Note 1:
Resistors are required for I²C
control port operation
Digital Audio
Processor
See Note 1
1 µF
0.1 µF
VD
VA
0.1 µF
See Note 4
1 µF
47 kΩ
VA_
+1.8 V or +2.5 V
Note 4:
Series resistance in the path of the power supplies must
be avoided.
PULLUP
CS53L21
TSTN
MCLK
SCLK
LRCK
SDOUT
RESET
SCL/CCLK
SDA/CDIN
AD0/CS
AIN1A
AIN1B
AIN2A
AIN2B
BIAS1
MICIN1
AIN3A
1800 pF
1800 pF
1800 pF
1800 pF
1 µF
100 Ω
*
1 µF
*
100 Ω
1 µF
100 Ω
*
1 µF
*
100 Ω
1 µF
100 kΩ
BIAS2
AIN3B/MICIN2
2 k
2 k
Ω
Ω
0.1 µF
VL
FILT+
0.1 µF
R
L
Note 3: The value of RL is dictated
by the microphone cartridge.
AGND
AFILTA
**
150 pF
150 pF
AFILTB
VQ
DGND
* Capacitors must be C0G or equivalent
Left Analog Input 1
100 kΩ
100 kΩ
Right Analog Input 1
Left Analog Input 2
100 kΩ
100 kΩ
Right Analog Input 2
Microphone Input
Microphone Bias
See Note 3
10 µF
1 µF
Figure 1. Typical Connection Diagram (Software Mode)
DS700PP1 9
CS53L21
+1.8V or +2.5V
Digital Audio
Processor
1 µF
VL or DGND (1)
0.1 µF
VD
TSTN
MCLK
SCLK
LRCK
SDOUT/
M/S
RESET
I²S/LJ
MCLKDIV2
0.1 µF
VA
CS53L21
47 kΩ
VA_
PULLUP
AIN1A
AIN1B
FILT+
1800 pF
1800 pF
See Note 4
Note 4:
Series resistance in the path of the power s upplies
(typically used for added filtering ) must be avoided.
100 Ω
*
1 µF
*
100 Ω
1 µF
+1.8V or +2.5V
Left Analog Input 1
100 kΩ
100 kΩ
Right Analog Input 1
10 µF
1 µF
+1.8V, 2.5 V
or +3.3V
0.1 µF
(1) Pull-up to VL (47 kΩ≤for Master Mode.
Pull-down to DGND for Slave Mode .
VL
DGND
AGND
AFILTA
AFILTB
VQ
**
150 pF
* Capacitors must be C0G or equivalent
150 pF
Figure 2. Typical Connection Diagram (Hardware Mode)
10 DS700PP1
CS53L21
3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
= 25° C.)
A
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters Symbol Min Nom Max Units
DC Power Supply (Note 1)
Analog Core
Digital Core
Serial/Control Port Interface
Ambient Temperature Commercial - CNZ
Automotive - DNZ
VA
VD
VL
T
1.65
2.37
1.65
2.37
1.65
2.37
3.14
A
-10
-40
1.8
2.5
1.8
2.5
1.8
2.5
3.3
1.89
2.63
1.89
2.63
1.89
2.63
3.47
-
-
+70
+85
V
V
V
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
V
VA
VD
VL
V
T
T
I
in
IN
IND
stg
A
DC Power Supply Analog
Digital
Serial/Control Port Interface
Input Current (Note 2)
Analog Input Voltage (Note 3)
Digital Input Voltage
(Note 3)
Ambient Operating Temperature (power applied)
Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. The device will operate properly over the full range of the analog, digital core and serial/control port interface supplies.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
-0.3
-0.3
-0.3
-±10mA
AGND-0.7 VA+0.7
-0.3 VL+ 0.4 V
-50 +115 °C
-65 +150 °C
3.0
3.0
4.0
V
V
V
V
DS700PP1 11
CS53L21
ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive
input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 4)
Analog In to ADC (PGA bypassed)
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
PGA Setting: +12 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
-60 dBFS
PGA Setting: +12 dB -1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error SDOUT Code with HPF On
Input
Interchannel Isolation
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
Input Impedance (Note 5) ADC
PGA
MIC
Min Typ Max Min Typ Max Unit
93
90
-
-
-
92
89
85
82
-
-
- -85 -79 - -83 -77 dB
-
-
- -76 - - -74 - dB
-
-
- -74 - - -71 - dB
-0.2- -0.2-dB
- ±100 - - ±100 - ppm/°C
- 352 - - 352 - LSB
-90- -90-dB
0.74•VA
0.75•VA
-
-
-
99
96
-86
-76
-36
98
95
91
88
-88
-35
86
83
78
74
0.78•VA
0.794•VA
0.129•VA
0.022•VA
20
39
50
-
-
-80
-
-
-
-
-
-
-81
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
90
87
-
-
-
89
86
82
79
-
-
-
-
-
-
0.74•VA
0.75•VA
-
-
-
96
93
-84
-73
-33
95
92
88
85
-86
-32
83
80
75
71
0.78•VA
0.794•VA
0.129•VA
0.022•VA
20
39
50
-
-
-78
-
-
-
-
-
-
-80
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
12 DS700PP1
CS53L21
ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input
filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA = 2.5 V (nominal) VA = 1.8 V (nominal)
Parameter (Note 4)
Analog In to ADC
Dynamic Range A-weighted
unweighted
Total Harmonic Distortion + Noise -1 dBFS
-20 dBFS
-60 dBFS
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
PGA Setting: +12 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
-60 dBFS
PGA Setting: +12 dB -1 dBFS
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted
unweighted
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error SDOUT Code with HPF On
Input
Interchannel Isolation
Full-scale Input Voltage ADC
PGA (0 dB)
MIC (+16 dB)
MIC (+32 dB)
Input Impedance (Note 5) ADC
PGA
MIC
4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table.
5. Measured between AINxx and AGND.
Min Typ Max Min Typ Max Unit
91
78
-
-
-
90
87
83
80
-
-
- -85 -77 - -83 -75 dB
-
-
- -76 - - -74 - dB
-
-
- -74 - - -71 - dB
- 0.1 - - 0.1 - dB
- ±100 - - ±100 - ppm/°C
- 352 - - 352 - LSB
-90--90-dB
0.74•VA
0.75•VA
18
40
50
99
96
-86
-76
-36
98
95
91
88
-88
-35
86
83
78
74
0.78•VA
0.794•VA
0.129•VA
0.022•VA
-
-
-
-
-
-78
-
-
-
-
-
-
-80
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
88
85
-
-
-
87
84
80
77
-
-
-
-
-
-
0.74•VA
0.75•VA
18
40
50
96
93
-84
-73
-33
95
92
88
85
-86
-32
83
80
75
71
0.78•VA
0.794•VA
0.129•VA
0.022•VA
-
-
-
-
-
-76
-
-
-
-
-
-
-78
-
-
-
-
-
0.82•VA
0.83•VA
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
Vpp
Vpp
Vpp
kΩ
kΩ
kΩ
DS700PP1 13
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 6) Min Typ Max Unit
Passband (Frequency Response) to -0.1 dB corner
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB
Phase Deviation @ 20 Hz
Passband Ripple
Filter Settling Time
6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters
are for Fs = 48 kHz.
CS53L21
0 - 0.4948 Fs
-0.09 - 0.17 dB
0.6 - - Fs
33 - - dB
- 7.6/Fs - s
-
-
-10-Deg
- - 0.17 dB
-10
3.7
24.2
5
/Fs 0 s
-
-
Hz
Hz
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
Parameters Symbol Min Max Units
RESET
MCLK Frequency
MCLK Duty Cycle (Note 8)
pin Low Pulse Width (Note 7)
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
= 15 pF.)
LOAD
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
F
s
F
s
F
s
F
s
1/t
P
t
s(LK-SK)
t
d(MSB)
t
s(SDO-SK)
t
h(SK-SDO)
1-ms
1.024 38.4 MHz
45 55 %
4
8
4
50
45 55 %
-64•FsHz
45 55 %
40 - ns
-52ns
20 - ns
30 - ns
12.5
25
50
100
kHz
kHz
kHz
kHz
14 DS700PP1
Master Mode (Note 9)
CS53L21
Parameters Symbol Min Max Units
Output Sample Rate (LRCK) All Speed Modes
(Note 10)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are
settled.
8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
9. See“Master” on page 30.
10. “MCLK” refers to the external master clock applied.
//
LRCK
t
s(LK-SK)
//
t
P
//
SCLK
SDOUT
t
d(MSB)
Figure 3. Serial Audio Interface Slave Mode Timing
t
h(SK-SDO)
//
MSB MSB-1
//
F
s
1/t
P
t
d(MSB)
t
s(SDO-SK)
t
h(SK-SDO)
//
MCLK
-Hz
45 55 %
- 64•F
45 55 %
-52ns
20 - ns
30 - ns
t
s(SDO-SK)
----------------128
s
Hz
//
LRCK
//
t
P
//
SCLK
//
t
d(MSB)
SDOUT
Figure 4. Serial Audio Interface Master Mode Timing
DS700PP1 15
t
h(SK-SDO)
t
s(SDO-SK)
//
MSB MSB-1
//
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency
RESET Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 11)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
f
t
t
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
t
susp
t
ack
scl
irs
buf
t
rc
fc
CS53L21
- 100 kHz
500 - ns
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
0-µs
250 - ns
-1µs
- 300 ns
4.7 - µs
300 3450 ns
11. Data must be held for sufficient time to bridge the transition time, t
RST
t
SDA
SCL
irs
Stop Start
t
buf
t
t
hdst
low
t
high
t
hdd
Figure 5. Control Port Timing - I²C
t
sud
Repeated
Start
t
sust
t
hdst
, of SCL.
fc
t
f
t
r
Stop
t
susp
16 DS700PP1
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter Symbol Min Max Units
CS53L21
CCLK Clock Frequency
RESET Rising Edge to CS Falling
Falling to CCLK Edge
CS
CS
High Time Between Transmissions
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 12)
Rise Time of CCLK and CDIN (Note 13)
Fall Time of CCLK and CDIN (Note 13)
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For f
<1 MHz.
sck
RST
CS
CCLK
t
srs
t
t
sch
css
t
scl
t
dsu
f
sck
t
srs
t
css
t
csh
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
t
f2
t
dh
06.0MHz
20 - ns
20 - ns
1.0 - μs
66 - ns
66 - ns
40 - ns
15 - ns
-100ns
-100ns
t
csh
t
r2
CDIN
Figure 6. Control Port Timing - SPI Format
DS700PP1 17
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 14)
FILT+
MIC BIAS Characteristics
Nominal Voltage MICBIAS_LVL[1:0] = 00
MICBIAS_LVL[1:0] = 01
MICBIAS_LVL[1:0] = 10
MICBIAS_LVL[1:0] = 11
DC Current Source
Power Supply Rejection Ratio (PSRR) 1 kHz
Power Consumption (Normal Operation Worse Case) 1 kHz
Power Supply Rejection Ratio (PSRR) (Note 15) 1 kHz
14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
CS53L21
-
-
-
-VA-V
-
-
-
-
-
-
--30mW
-60-dB
0.5•VA
23
-
0.8•VA
0.7•VA
0.6•VA
0.5•VA
-
50
10
-
-
-
-
-
-
1
-
V
kΩ
μA
V
V
V
V
mA
dB
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 16) Symbol Min Max Units
Input Leakage Current
Input Capacitance
1.8 V - 3.3 V Logic
High-Level Output Voltage (I
Low-Level Output Voltage
High-Level Input Voltage
Low-Level Input Voltage
16. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails.
= -100 μA)
OH
(IOL = 100 μA)
I
in
V
OH
V
OL
V
IH
V
IL
-±10μA
-10pF
VL - 0.2 - V
-0.2V
0.68•VL - V
- 0.32•VL V
18 DS700PP1
POWER CONSUMPTION
See (Note 17)
CS53L21
Power Ctl. Registers Typical Current (mA)
02h 03h
Operation
Reserved bit 6
Reserved bit 5
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
PDN
PDN_MICB
PDN_MICA
1
Off
(Note 18)
2 Standby (Note 19)
3 Mono Record ADC1111100111
PGA to ADC
MIC to PGA to ADC
(with Bias)
MIC to PGA to ADC
(no Bias)
4 Stereo Record ADC1111000111
PGA to ADC
MIC to PGA to ADC
(no Bias)
xxxxxxxxxx
xxxxxx1xxx
1110100111
1110100100
1110100101
1100000111
1100000001
i
i
VA
V
PDN_MICBIAS
1.8 0 0 0 0
2.5 0 0 0 0
1.8 0.01 0.02 0 0.05
2.5 0.01 0.03 0 0.10
1.8 1.85 2.03 0.03 7.05
2.5 2.07 3.05 0.05 12.94
1.8 2.35 2.03 0.03 7.95
2.5 2.58 3.08 0.05 14.29
1.8 3.67 2.05 0.03 10.36
2.5 3.95 3.09 0.05 17.71
1.8 3.27 2.03 0.03 9.61
2.5 3.52 3.08 0.05 16.62
1.8 2.69 2.12 0.03 8.72
2.5 2.93 3.18 0.04 15.40
1.8 3.65 2.12 0.03 10.45
2.5 3.91 3.17 0.04 17.84
1.8 5.48 2.11 0.03 13.73
2.5 5.76 3.17 0.04 22.45
i
VD
VL
(Note 20)
Tota l
Power
(mW
rms
)
17. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation.
18. RESET
pin 25 held LO, all clocks and data lines are held LO.
19. RESET pin 25 held HI, all clocks and data lines are held HI.
20. VL current will slightly increase in master mode.
DS700PP1 19
4. APPLICATIONS
4.1 Overview
4.1.1 Architecture
The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs
is equal to the system sample rate. The different clock rates maximize power savings while maintaining
high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and
Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input
Master Clock (MCLK).
4.1.2 Line & MIC Inputs
The analog input portion of the A/D allows selection from and configuration of multiple combinations of
stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC
input with common mode rejection), two MIC bias outputs and independent channel control (including a
high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume
controls, including gain, boost, attenuation and inversion are also available.
4.1.3 Signal Processing Engine
CS53L21
The ADC data has independent volume controls and mixing functions such as mono mixes and left/right
channel swaps.
4.1.4 Device Control (Hardware or Software Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins.
4.1.5 Power Management
Two Software Mode control registers provide independent power-down control of the ADC, PGA, MIC preamp and MIC bias, allowing operation in select applications with minimal power consumption.
20 DS700PP1
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