Cirrus Logic CS5376A User Manual

CS5376A

Low-power, Multi-channel Decimation Filter

Features

z 1- to 4-channel Digital Decimation Filter

 Multiple On-chip FIR and IIR Coefficient Sets
 Programmable Coefficients for Custom Filters
 Synchronous Operation

z Selectable Output Word Rate

 4000, 2000, 1000, 500, 333, 250 SPS
 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS

z Digital Gain and Offset Corrections
z Test DAC Bit-stream Generator

 Digital Sine Wave Output

z Time Break Controller, General Purpose I/O
z Secondary SPI™ Port, Boundary Scan JTAG
z Microcontroller or EEPROM Configuration
z Small-footprint, 64-pin TQFP Package
z Low Power Consumption

 9 mW per Channel at 500 SPS

z Flexible Power Supplies

 I/O Interface: 3.3 V or 5.0 V
 Digital Logic Core: 3.0 V, 3.3 V or 5.0 V

I

Description

The CS5376A is a multi-function digital filter utilizing a
low-power signal processing architecture to achieve ef­ficient filtering for up to four ∆Σ modulators. By
combining the CS5376A with CS3301A/02A differential
amplifiers, CS5371A/72A ∆Σ modulators, and the
CS4373A ∆Σ test DAC a synchronous, high-resolution,
self-testing, multi-channel me as ur em e nt s yst em can be
designed quickly and easily.

Digital filter coefficients for the CS5376A FIR and IIR fil­ters are included on-chip for a simple setup, or they can
be programmed for custom applications. Selectable dig­ital filter decimation ratios produce output word rates
from 4000 SPS to 1 SPS, resulting in measurement
bandwidths ranging from 1600 Hz down to 400 mHz
when using the on-chip coefficient sets.

The CS5376A includes integrated peripherals to simplify
system design: offset and gain corrections, a test DAC
bit stream generator, a time-break controller, 12 gener­al-purpose I/O pins, a secondary SPI port, and a
boundary scan JTAG port.

ORDERING INFORMATION

See page 106.

http://www.cirrus.com

Se ria l D a ta Ou tp u t P o rt

Decimation and
Filtering Engine

JTAG

Inte rfa c e

TDI

TCK

TRST

TDO

TMS

SDCLK

SDDAT

SDTKI

SDRDY

Modulator Data

Inte rfa c e

MDATA [4:1]

RESET

MFLAG [4:1]

Copyright © Cirrus Logic, Inc. 2008

(All Rights Reserved)

BOOT

Clock and

Synchronization

Serial Peripheral Interface 1

Time Break Controller

Test Bit Stream Controller

General Purpose I/O

Serial Peripheral Interface 2

SPI 1

GPIO

SPI 2

VD (x2)

VDD1

VDD2 (x2)

CLK
SYNC
MCLK
MSYNC

SSI
SCK1
MISO
MOSI

SINT

TIMEB

TBSCLK
TBSDATA

GPIO11:EECS
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4:CS4
GPIO3:CS3
GPIO2:CS2
GPIO1:CS1
GPIO0:CS0

SCK2
SO
SI1
SI2
SI3
SI4

GND1

GND (x2)

GND2 (x2)

SEP ‘08

DS612F4

TABLE OF CONTENTS

1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.1. Digital Filter Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2. Integrated Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.3. System Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.4. Configuration Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2. Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 13

Specified Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3. System Design with CS5376A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2. Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.4. Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.5. System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.6. Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.7. Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.8. Integrated peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2. Bypass Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.3. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5. Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.2. Reset Self-Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.3. Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6. Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.2. Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.3. Master Clock Jitter and Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7. Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.2. MSYNC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.3. Digital Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.4. Modulator Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7.5. Test Bit Stream Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8. Configuration By EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.2. EEPROM Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.3. EEPROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.4. EEPROM Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8.5. Example EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9. Configuration By Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CS5376A

DS612F4 2

9.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

9.2. Microcontroller Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

9.3. Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

9.4. Microcontroller Configuration Commands . . . . . . . . . . . . . . . . . . . . . . .35

9.5. Example Microcontroller Configuration . . . . . . . . . . . . . . . . . . . . . . . . .37

10. Modulator Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10.2. Modulator Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10.3. Modulator Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

10.4. Modulator Data Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

10.5. Modulator Flag Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

11. Digital Filter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.1. Filter Coefficient Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

11.2. Filter Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

12. SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.1. SINC1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

12.2. SINC2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

12.3. SINC3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

12.4. SINC Filter Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

13. FIR Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.1. FIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

13.2. FIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

13.3. On-Chip FIR Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

13.4. Programmable FIR Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

13.5. FIR Filter Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

14. IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14.1. IIR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

14.2. IIR1 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

14.3. IIR2 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

14.4. IIR3 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

14.5. On-Chip IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

14.6. Programmable IIR Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

14.7. IIR Filter Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

15. Gain and Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

15.1. Gain Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

15.2. Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

15.3. Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

16. Serial Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

16.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

16.2. SD Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

16.3. SD Port Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

17. Test Bit Stream Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

17.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

17.2. TBS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

17.3. TBS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

17.4. TBS Data Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

17.5. TBS Sine Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

17.6. TBS Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

CS5376A

DS612F4 3

17.7. TBS Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

18. Time Break Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

18.1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

18.2. Time Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

18.3. Time Break Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

19. General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

19.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

19.2. GPIO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

19.3. GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

19.4. GPIO Input Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

19.5. GPIO Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

20. Serial Peripheral Interface 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

20.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

20.2. SPI 2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

20.3. SPI 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

20.4. SPI 2 Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

21. Boundary Scan JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

21.1. Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

21.2. JTAG Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

22. Device Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

22.1. Changes from CS5376 rev A to CS5376 rev B . . . . . . . . . . . . . . . . . .78

22.2. Changes from CS5376 rev B to CS5376A rev A. . . . . . . . . . . . . . . . .78

23. Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

23.1. SPI 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

23.2. Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

24. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

25. Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

27. Environmental, Manufacturing, & Handling Information. . . . . . 106

28. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

CS5376A

LIST OF FIGURES

Figure 1. CS5376A Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2. Digital Filtering Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 3. FIR and IIR Coefficient Set Selection Word. . . . . . . . . . . . . . . . . . . . .11

Figure 4. MOSI Write Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 5. MISO Read Timing in SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 6. SD Port Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing . . . . . . . . . . . . . . .17

Figure 8. TBS Output Clock and Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9. Multi-Channel System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 10. Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 11. Reset Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 12. Clock Generation Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 13. Synchronization Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

DS612F4 4

Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . .26

Figure 15. SPI 1 EEPROM Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 16. 8 Kbyte EEPROM Memory Organization. . . . . . . . . . . . . . . . . . . . . .28

Figure 17. Serial Peripheral Interface 1 (SPI 1) Block Diagram . . . . . . . . . . . . .32

Figure 18. Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 19. SPI 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 20. Modulator Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 21. Digital Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 22. FIR and IIR Coefficient Set Selection Word. . . . . . . . . . . . . . . . . . . .42

Figure 23. SINC Filter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 24. SINC Filter Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 25. FIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 26. FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 27. Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 28. IIR Filter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 29. IIR Filter Stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 30. Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 31. Serial Data Port Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 32. SD Port Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 33. SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 34. Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . .64

Figure 35. Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 36. GPIO Bi-directional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 37. Serial Peripheral Interface 2 (SPI 2) Block Diagram . . . . . . . . . . . . .70

Figure 38. SPI 2 Master Mode Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 39. SPI 2 Transaction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 40. JTAG Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 41. SPI 1 Control Register SPI1CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 42. SPI 1 Command Register SPI1CMD. . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 43. SPI 1 Data Register SPI1DAT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 44. SPI 1 Data Register SPI1DAT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 45. Hardware Configuration Register CONFIG . . . . . . . . . . . . . . . . . . . .87

Figure 46. GPIO Configuration Register GPCFG0. . . . . . . . . . . . . . . . . . . . . . . 8 8

Figure 47. GPIO Configuration Register GPCFG1. . . . . . . . . . . . . . . . . . . . . . . 8 9

Figure 48. SPI 2 Control Register SPI2CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .90

Figure 49. SPI 2 Command Register SPI2CMD. . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 50. SPI 2 Data Register SPI2DAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 51. Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . .93

Figure 52. Gain Correction Register GAIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 53. Offset Correction Register OFFSET1 . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 54. Time Break Counter Register TIMEBRK. . . . . . . . . . . . . . . . . . . . . .96

Figure 55. Test Bit Stream Configuration Register TBSCFG . . . . . . . . . . . . . . .97

Figure 56. Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . .98

Figure 57. User Defined System Register SYSTEM1. . . . . . . . . . . . . . . . . . . . .99

Figure 58. Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . .100

Figure 59. Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . .101

CS5376A

DS612F4 5

LIST OF TABLES

Table 1. Microcontroller and EEPROM Configuration Commands. . . . . . . . . . .10

Table 2. TBS Configurations Using On-Chip Data . . . . . . . . . . . . . . . . . . . . . . .11

Table 3. SPI 1 and Digital Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 4. Maximum EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 5. EEPROM Boot Configuration Commands . . . . . . . . . . . . . . . . . . . . . .29

Table 6. Example EEPROM File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 7. Microcontroller Boot Configuration Commands . . . . . . . . . . . . . . . . . .35

Table 8. Example Microcontroller Configuration. . . . . . . . . . . . . . . . . . . . . . . . .38

Table 9. SINC Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 10. SINC1 and SINC2 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 11. SINC3 Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 12. FIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 13. SINC + FIR Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 14. FIR1 Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 15. FIR2 Linear Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 16. FIR2 Minimum Phase Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 17. IIR Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 18. IIR Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 19. TBS Configurations Using On-chip Data . . . . . . . . . . . . . . . . . . . . . .65

Table 20. JTAG Instructions and IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 21. JTAG Scan Cell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

CS5376A

DS612F4 6

SDCLK

Serial Data Output Port

Decimation and
Filtering Engine

JTAG

Interface

SDDAT

SDTKI

SDRDY

Modulator Data

Interface

RESET

BOOT

Clock and

Synchronization

Serial Peripheral Interface 1

Time Break Controller

Test Bit Stream Controller

General Purpose I/O

Serial Peripheral Interface 2

SPI 1

GPIO

SPI 2

CS5376A

VD (x2)

VDD1

VDD2 (x2)

CLK
SYNC
MCLK
MSYNC

SSI
SCK1
MISO
MOSI

SINT

TIMEB

TBSCLK
TBSDATA

GPIO11:EECS
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4:CS4
GPIO3:CS3
GPIO2:CS2
GPIO1:CS1
GPIO0:CS0

SCK2
SO
SI1
SI2
SI3
SI4

TDI

TCK

TRST

TDO

TMS

MFLAG [4:1]

MDATA [4:1]

Figure 1. CS5376A Block Diagram

1. GENERAL DESCRIPTION

The CS5376A is a multi-channel digital filter with
integrated system peripherals. Figure 1 illustrates a
simplified block diagram of the CS5376A.

1.1 Digital Filter Features

• Multi-channel decimation filter for
CS5371A/72A ∆Σ modulators.

- 1, 2, 3, or 4 channel concurrent operation.

• Synchronous operation for simultaneous sam­pling in multi-sensor systems.

- Internal synchronization of digital filter

phase to an external SYNC signal.

• Multiple output word rates, including low
bandwidth rates.

- Standard output rates: 4000, 2000, 1000,

500, 333, 250 SPS.

GND1

GND (x2)

GND2 (x2)

- Low bandwidth rates: 200, 125, 100, 50, 40,
25, 20, 10, 5, 1 SPS.

• Flexible digital filter configuration. (See Figure

2)

- Cascaded SINC, FIR, and IIR filters with
selectable output stage.

- Linear and minimum phase FIR low-pass
filter coefficients included.

- 3 Hz Butterworth IIR high-pass filter coef­ficients included.

- FIR and IIR coefficients are programmable
to create a custom filter response.

• Digital gain correction.

- Individual channel gain correction to nor­malize signal amplitudes.

DS612F4 7

CS5376A

Modulator

Input

512 kHz

Sinc Filter

2 - 64000

Gain &

DC Offset

Corrections

FIR1

4

Figure 2. Digital Filtering Stages

FIR2

Output Word Rate from 4000 SPS ~ 1 SPS

• Digital offset correction and calibration.

- Individual channel offset correction to re­move measurement offsets.

- Calibration engine for automatic calcula­tion of offset correction factors.

1.2 Integrated Peripheral Features

• Synchronous operation for simultaneous sam­pling in multi-sensor systems.

- MCLK / MSYNC output signals to syn-

chronize external components.

• High speed serial data output port (SD port).

IIR1 IIR2

2

Output to High Speed Serial Data Port

st

1

Order

2nd Order

• Time break controller to record system timing
information.

- Dedicated TB status bit in the output data
stream.

- Programmable output delay to match sys­tem group delay.

• Additional hardware peripherals simplify sys­tem design.

- 12 General Purpose I/O (GPIO) pins for lo-

cal hardware control.

- Secondary SPI 2 serial port to control local

serial peripherals.

- Asynchronous operation to 4 MHz for di­rect connection to system telemetry.

- JTAG port for boundary scan (IEEE 1149.1
compliant).

- Internal 8-deep data FIFO for flexible out­put timing.

• Digital test bit stream signal generator suitable
for CS4373A ∆Σ test DAC.

- Sine wave output mode for testing total har-

monic distortion.

- Programmable waveform data for custom

test signal generation.

8 DS612F4

1.3 System Level Features

• Flexible configuration options.

- Configuration 'on-the-fly' via microcontrol­ler or system telemetry.

- Fixed configuration via stand-alone boot
EEPROM.

• Low power consumption.

CS5376A

- 37 mW for 4-channel operation at 500 SPS
(9.25 mW/channel).

-40µW standby mode.

• Flexible power supply configurations.

- Separate digital logic core, telemetry I/O,
and modulator I/O power supplies.

- Telemetry I/O and modulator I/O interfaces
operate from 3.3 V or 5 V.

- Digital logic core operates from 3.0 V,

3.3 V or 5 V.

• Small 64-pin TQFP package.

- Total footprint 12 mm x 12 mm plus five
bypass capacitors.

1.4 Configuration Interface

• Configuration from microcontroller or stand-

alone boot EEPROM.

- Microcontroller boot permits reconfigura­tion during operation.

- EEPROM boot sets a fixed operational con­figuration.

• Configuration commands written through Seri­al Peripheral Interface 1. (See Table 1)

- Standardized microcontroller interface us-

ing SPI 1 registers. (See Table 3)

- Commands write digital filter registers, fil-

ter coefficients, and test bit stream data.

- Digital filter registers set hardware config-

uration options.

DS612F4 9

Microcontroller Boot Configuration Commands

CS5376A

Name CMD

24-bit

NOP 000000 - - No Operation
WRITE DF REGISTER 000001 REG DATA Write Digital Filter Register
READ DF REGISTER 000002 REG

WRITE FIR COEFFICIENTS 000003 NUM FIR1

WRITE IIR COEFFICIENTS 000004 a11

WRITE ROM COEFFICIENTS 000005 COEF SEL - Use On-Chip Coefficients
WRITE TBS DATA 000006 NUM TBS

WRITE ROM TBS 000007 - - Use On-Chip TBS Data
FILTER START 000008 - - Start Digital Filter Operation
FILTER STOP 000009 - - Stop Digital Filter Operation

DAT1
24-bit

[DATA]

(FIR COEF)

b11
a22
b21

(TBS DATA)-(TBS DATA)

DAT2

24-bit

-

-

NUM FIR2

(FIR COEF)

b10
a21
b20
b22

Description

Read Digital Filter Register

Write Custom FIR Coefficients

Write Custom IIR Coefficients

Write Custom Test Bit Stream Data

EEPROM Boot Configuration Commands

Name CMD

8-bit

NOP 00 - No Operation
WRITE DF REGISTER 01 REG

WRITE FIR COEFFICIENTS 02 NUM FIR1

WRITE IIR COEFFICIENTS 03 a11

WRITE ROM COEFFICIENTS 04 COEF SEL Use On-Chip Coefficients
WRITE TBS DATA 05 NUM TBS

WRITE ROM TBS 06 - Use On-Chip TBS Data
FILTER START 07 - Start Digital Filter Operation

DATA
24-bit

DATA

NUM FIR2

(FIR COEF)

b10
b11
a21
a22
b20
b21
b22

(TBS DATA)

Description

Write Digital Filter Register

Write Custom FIR Coefficients

Write Custom IIR Coefficients

Write Custom Test Bit Stream Data

[DATA] indicates data word returned from digital filter.
(DATA) indicates multiple words of this type are to be written.

Table 1. Microcontroller and EEPROM Configuration Commands

DS612F4 10

CS5376A

Bits 23:20 19:16 15:12 11:8 7:4 3:0

Selection 0000 0000 IIR2 IIR1 FIR2 FIR1

Bits 15:12 IIR2 Coefficients

0000 3 Hz @ 2000 SPS
0001 3 Hz @ 1000 SPS
0010 3 Hz @ 500 SPS
0011 3 Hz @ 333 SPS
0100 3 Hz @ 250 SPS

Figure 3. FIR and IIR Coefficient Set Selection Word

Test Bit Stream Characteristic Equation:

(Signal Freq) * (# TBS Data) * (Interpolation + 1) = Output Rate
Example: (31.25 Hz) * (1024) * (0x07 + 1) = 256 kHz

Signal

Frequency

(TBSDATA)

10.00 Hz 256 kHz 0x4 0x18

10.00 Hz 512 kHz 0x5 0x31

25.00 Hz 256 kHz 0x4 0x09

25.00 Hz 512 kHz 0x5 0x13

31.25 Hz 256 kHz 0x4 0x07

31.25 Hz 512 kHz 0x5 0x0F

50.00 Hz 256 kHz 0x4 0x04

50.00 Hz 512 kHz 0x5 0x09

125.00 Hz 256 kHz 0x4 0x01

125.00 Hz 512 kHz 0x5 0x03

Bits 11:8 IIR1 Coefficients

0000 3 Hz @ 2000 SPS
0001 3 Hz @ 1000 SPS
0010 3 Hz @ 500 SPS
0011 3 Hz @ 333 SPS
0100 3 Hz @ 250 SPS

Output

Output Rate

Rate

(TBSCLK)

Selection

(RATE)

Bits 3:0 FIR1 Coefficients

0000 Linear Phase
0001 Minimum Phase

Bits 7:4 FIR2 Coefficients

0000 Linear Phase
0001 Minimum Phase

Interpolation

Selection

(INTP)

Table 2. TBS Configurations Using On-Chip Data

DS612F4 11

SPI 1 Registers

Name Addr. Type # Bits Description

SPI1CTRL 00 - 02 R/W 8, 8, 8 SPI 1 Control
SPI1CMD 03 - 05 R/W 8, 8, 8 SPI 1 Command
SPI1DAT1 06 - 08 R/W 8, 8, 8 SPI 1 Data 1
SPI1DAT2 09 - 0B R/W 8, 8, 8 SPI 1 Data 2

Digital Filter Registers

Name Addr. Type # Bits Description

CONFIG 00 R/W 24 Hardware Configuration
RESERVED 01-0D R/W 24 Reserved
GPCFG0 0E R/W 24 GPIO[7:0] Direction, Pull-up Enable, and Data
GPCFG1 0F R/W 24 GPIO[11:8] Direction, Pull-up Enable, and Data
SPI2CTRL 10 R/W 24 SPI 2 Control
SPI2CMD 11 R/W 16 SPI 2 Command
SPI2DAT 12 R/W 24 SPI 2 Data
RESERVED 13-1F R/W 24 Reserved
FILTCFG 20 R/W 24 Digital Filter Configuration
GAIN1 21 R/W 24 Gain Correction Channel 1
GAIN2 22 R/W 24 Gain Correction Channel 2
GAIN3 23 R/W 24 Gain Correction Channel 3
GAIN4 24 R/W 24 Gain Correction Channel 4
OFFSET1 25 R/W 24 Offset Correction Channel 1
OFFSET2 26 R/W 24 Offset Correction Channel 2
OFFSET3 27 R/W 24 Offset Correction Channel 3
OFFSET4 28 R/W 24 Offset Correction Channel 4
TIMEBRK 29 R/W 24 Time Break Delay
TBSCFG 2A R/W 24 Test Bit Stream Configuration
TBSGAIN 2B R/W 24 Test Bit Stream Gain
SYSTEM1 2C R/W 24 User Defined System Register 1
SYSTEM2 2D R/W 24 User Defined System Register 2
VERSION 2E R/W 24 Hardware Version ID
SELFTEST 2F R/W 24 Self-Test Result Code

CS5376A

T able 3. SPI 1 and Digital Filter Registers

DS612F4 12

CS5376A

2. CHARACTERISTICS AND SPECIFICATIONS

• Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.

• Typical performance characteristics and specifications are derived from measurements taken at nomi­nal supply voltages and TA = 25°C.

• GND, GND1, GND2 = 0 V, all voltages with respect to 0 V.

SPECIFIED OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

Logic Core Power Supply VD 2.85 3.0 5.25 V
Microcontroller Interface Power Supply VDD1 3.135 3.3 5.25 V
Modulator Interface Power Supply VDD2 3.135 3.3 5.25 V
Ambient Operating Temperature Industrial (-IQ) T

A

-40 - 85 °C

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Power Supplies Logic Core

Microcontroller Interface

Modulator Interface
Input Current, Any Pin Except Supplies (Note 1) I
Input Current, Power Supplies (Note 1) I
Output Current (Note 1) I
Power Dissipation P
Digital Input Voltages V
Ambient Operating Temperature (Power Applied) T
Storage Temperature Range T

1. Transient currents up to 100 mA will not cause SCR latch-up.

VDD1
VDD2

VD

IN
IN

OUT

DN

IND

A

STG

-0.3

-0.3

-0.3

-±10mA

-±50mA

-±25mA

-500mW

-0.5 VDD+0.5 V

-40 85 °C

-65 150 °C

6.0

6.0

6.0

V
V
V

DS612F4 13

THERMAL CHARACTERISTICS

V

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature T
Junction to Ambient Thermal Impedance Θ
Ambient Operating Temperature (Power Applied) T

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

High-Level Input Drive Voltage V
Low-Level Input Drive Voltage V
High-Level Output Drive Voltage I

Low-Level Output Drive Voltage I
Rise Times, Digital Inputs t

Fall Times, Digital Inputs t
Rise Times, Digital Outputs t
Fall Times, Digital Outputs t
Input Leakage Current (Note 2) I
3-State Leakage Current I
Digital Input Capacitance C
Digital Output Pin Capacitance C

= -40 µA V

out

= +40 µA V

out

J

JA

A

IH

IL

OH
OL

RISE
FALL
RISE
FALL

IN

OZ

IN

OUT

CS5376A

--135°C

-65 °C / W

-40 - +85 °C

0.6 * VDD - VDD V

0.0 - 0.8 V

VDD - 0.3 - VDD V

0.0 - 0.3 V

--100ns

--100ns

--100ns

--100ns

-± 1± 10µA

--± 10µA

-9-pF

-9-pF

Notes: 2. Max leakage for pins with pull-up resistors (TRST, TMS, TDI, SSI, GPIO, MOSI, SCK1) is ±250 µA.

t

risein

t

fa llin

2.6 V

0.9 * VDD

0.1 * VDD

0.7 V

t

rise out

t

fallo ut

0.9 * VDD

4.6

0.1 * VDD

0.4 V

POWER CONSUMPTION

Parameter Symbol Min Typ Max Unit

Operational Power Consumption

1.024 MHz Digital Filter Clock PWR

2.048 MHz Digital Filter Clock PWR

4.096 MHz Digital Filter Clock PWR

8.192 MHz Digital Filter Clock PWR

16.384 MHz Digital Filter Clock PWR

Standby Power Consumption

32 kHz Digital Filter Clock, Filter Stopped PWR

1
2
4
8

16

S

-21-mW

-26-mW

-37-mW

-57-mW

-85-mW

-40-µW

DS612F4 14

SWITCHING CHARACTERISTICS

SPI 1 Interface Timing (External Master)

SSI

CS5376A

MOSI

SCK1

SCLK

MSB MSB - 1

t

1

t

2

t

t

3

t

5

4

Figure 4. MOSI Write Timing in SPI Slave Mode

SSI

MISO

SCK1

SCLK

MSB MSB - 1 LSB

t

t

9

t

7

8

Figure 5. MISO Read Timing in SPI Slave Mode

Parameter Symbol Min Typ Max Unit

MOSI Write Timing

SSI

Enable to Valid Latch Clock t
Data Set-up Time Prior to SCK1 Rising t
Data Hold Time After SCK1 Rising t
SCK1 High Time t
SCK1 Low Time t
SCK1 Falling Prior to SSI

Disable t

MISO Read Timing

SCK1 Falling to New Data Bit t
SCK1 High Time t
SCK1 Low Time t
SSI

Rising to MISO Hi-Z t

10

LSB

t

6

t

10

1
2
3
4
5
6

7
8
9

60 - - ns

60 - - ns
120 - - ns
120 - - ns
120 - - ns

60 - - ns

- - 60 ns
120 - - ns
120 - - ns

--150ns

DS612F4 15

SWITCHING CHARACTERISTICS

Serial Data Port (SD Port)

SDRDY

SDCLK

t

3

SDDAT

t4t

SDTKI

SDTKO

t

1

t

2

5

CS5376A

t

t

6

7

t

t

9

8

Figure 6. SD Port Read Timing

Parameter Symbol Min Typ Max Unit

SDTKI to SDRDY Falling Edge t
SDTKI High Time Width t
SDRDY

Falling Edge to SDCLK Falling Edge t
Data Setup Time Prior to SDCLK Rising t
Data Hold Time After SDCLK Rising t
SDCLK High Time t
SDCLK Low Time t
SDCLK Rising to SDRDY
Data Hold Time After SDRDY
SDRDY

High to SDTKO Rising Edge t

Rising t

Rising t

SDTKO High Time t

10

t10t

11

1
2
3
4
5
6
7
8
9

60 - - ns
60 - 1000 ns
50 - - ns
60 - - ns

60 - - ns
120 - - ns
120 - - ns

60 - - ns

--150ns

- - 60 ns

11

90 - - ns

DS612F4 16

SWITCHING CHARACTERISTICS

CLK, SYNC, MCLK, MSYNC, and MDATAx

SYNC

MCLK

CS5376A

MSYNC

t

msd

MDATAx

Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.

f

MCLK

t

= T

msd

t

= T

msh

Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing

Parameter Symbol Min Typ Max Unit

Master Clock Frequency (Note 3) CLK 32 32.768 33 MHz
Master Clock Duty Cycle DTY 40 - 60 %
Master Clock Rise Time t
Master Clock Fall Time t
Master Clock Jitter JTR - - 300 ps
Synchronization after SYNC rising (Note 4) SYNC -2 - 2 µs
MSYNC Setup Time to MCLK rising t
MCLK rising to Valid MDATA t
MSYNC falling to MCLK rising t

MCLK
MCLK

/ 4 t

t

msh

t

msd

Data1 Data2

2.048 MHz 1.024 MHz

= 122 ns t

msd

t

= 488 ns t

msh

RISE
FALL

msr

mdv

msf

msd
msh

= 244 ns
= 976 ns

- - 20 ns

- - 20 ns

20 - - ns

- - 75 ns

20 - - ns

Notes: 3. Master clock frequencies above or below 32.768 MHz will affect generated clock frequencies.

4. Sampling synchronization between multiple CS5376A devices receiving identical SYNC signals.

DS612F4 17

SWITCHING CHARACTERISTICS

Test Bit Stream (TBS)

t

1

t

2

TBSCLK

TBSDATA

MCLK

Note: Example timing shown for a 256 kHz output rate and no programmable delays.

Figure 8. TBS Output Clock and Data Timing

CS5376A

t

3

t

4

t

5

Parameter Symbol Min Typ Max Unit

TBS Clock Timing

TBS Clock Period t
TBS Clock High Time (Note 5) t
TBS Clock Low Time t

1
2
3

-3.906- µs
40 - 60 %
40 - 60 %

TBS Data Output Timing

TBS Data Bit Rate - 256 - kbps
TBS Data Rising to TBS Clock Rising Setup Time t
TBS Clock Rising to TBS Data Falling Hold Time (Note 6) t

4
5

60 - - ns
60 - - ns

5. TBSCLK phase can be delayed in 1/8 increments. The timing diagram shows no TBSCLK delay.

6. TBSDATA can be delayed from 0 to 63 full bit period s. The tim ing diag ram sho ws no T BSDATA delay.

DS612F4 18

CS5376A

Geophone

or

Hydrophone

Sensor

Geophone

or

Hydrophone

Sensor

Geophone

or

Hydrophone

Sensor

Geophone

or

Hydrophone

Sensor

CS3301A

AMP

AMP

AMP

AMP

CS3302A

CS3301A
CS3302A

CS3301A
CS3302A

CS3301A
CS3302A

Switch
Switch

MUX
MUX

CS5371A
CS5372A

∆Σ

Modulator

CS5371A
CS5372A

∆Σ

Modulator

CS5376A

Digital F ilter

CS4373A

DAC

M
U
X

M
U
X

M
U
X

M
U
X

Figure 9. Multi-Channel System Block Diagram

Test

System T e lemetry

µController

or

Configuration

EEPROM

Communication

Interface

3. SYSTEM DESIGN WITH CS5376A

Figure 9 illustrates a simplified block diagram of
the CS5376A in a multi-channel measurement sys­tem.

Up to four differential sensors are connected
through CS3301A/02A differential amplifiers to
the CS5371A/72A ∆Σ modulators, where analog to
digital conversion occurs. Each modulators 1-bit
output connects to a CS5376A MDATA input,
where the oversampled ∆Σ data is decimated and
filtered to 24-bit output samples at a programmed
output rate. These output samples are buffered in
an 8-deep data FIFO and passed to the system te­lemetry on command.

System self tests are performed by connecting the
CS5376A test bit stream (TBS) generator to the
CS4373A test DAC. Analog tests drive differential
signals from the CS4373A test DAC into the mul­tiplexed inputs of the CS3301A/02A amplifiers or

directly to the sensors through external analog
switches. Digital loopback tests internally connect
the TBS digital output directly to the CS5376A
modulator inputs.

3.1 Power Supplies

The multi-channel system shown in Figure 9 typi­cally operates from a ±2.5 V analog power supply
and a 3.3 V digital power supply. The CS5376A
logic core can be powered from 3 V to minimize
power consumption, if required.

3.2 Reset Control

System reset is required only for the CS5376A de­vice, and is a standard active low signal that can be
generated by a power supply monitor or microcon­troller. Other system devices default to a power­down state when the CS5376A is reset.

DS612F4 19

CS5376A

3.3 Clock Generation

A single 32.768 MHz low-jitter clock input, which
can be generated from a VCXO based PLL, is re­quired to drive the CS5376A device. Clock inputs
for other system devices are driven by clock out­puts from the CS5376A.

3.4 Synchronization

Digital filter phase and analog sample timing of the
four ∆Σ modulators connected to the CS5376A are
synchronized by a rising edge on the SYNC pin. If
a synchronization signal is received identically by
all CS5376A devices in a measurement network,
synchronous sampling across the network is guar­anteed.

3.5 System Configuration

Through the SPI 1 serial port, filter coefficients and
digital filter register settings can either be pro­grammed by a microcontroller or automatically
loaded from an external EEPROM after reset. Sys­tem configuration is only required for the
CS5376A device, as other devices are configured
via the CS5376A General Purpose I/O pins.

Two registers in the digital filter, SYSTEM1 and
SYSTEM2 (0x2C, 0x2D), are provided for user de­fined system information. These are general pur­pose registers that will hold any 24-bit data values
written to them.

3.6 Digital Filter Operation

After analog to digital conversion occurs in the
modulators, the oversampled 1-bit ∆Σ data is read
into the CS5376A through the MDATA pins. The
digital filter then processes data through the en­abled filter stages, decimating it to 24-bit words at
a programmed output word rate. The final 24-bit
samples are concatenated with 8-bit status words
and placed into an output FIFO.

3.7 Data Collection

Data is collected from the CS5376A through the
Serial Data port (SD port). Automatically or upon
request, depending how the SDTKI pin is connect­ed, the SD port initiates serial transactions to trans­fer 32-bit data from the output FIFO to the system
telemetry. The output FIFO has eight data locations
to permit latency in data collection.

3.8 Integrated peripherals

Test Bit Stream (TBS)

A digital signal generator built into the CS5376A
produces a 1-bit ∆Σ sine wave. This digital test bit
stream can be connected to the CS4373A test DAC
to create high quality analog test signals or it can be
internally looped back to the CS5376A MDATA
inputs to test the digital filter and data collection
circuitry.

Time Break

Timing information is recorded during data collec­tion by strobing the TIMEB pin. A dedicated flag
in the sample status bits, TB, is set high to indicate
over which measurement the timing event oc­curred.

General Purpose I/O (GPIO)

Twelve general purpose pins are available on the
CS5376A for system control. Each pin can be set as
input or output, high or low, with an internal pull­up enabled or disabled. The CS3301A/02A,
CS5371A/72A and CS4373A devices in Figure 9
are configured by simple pin settings controlled
through the CS5376A GPIO pins.

Serial Peripheral Interface 2 (SPI 2)

A secondary master mode serial port to communi­cate with external serial peripherals.

JTAG Port

Boundary scan JTAG is IEEE 1149.1 compliant.

20 DS612F4

TRST

TMS
TCK

TDI

TDO

GND

VD

TBSCLK

TBSDATA

DNC

VDD2

MCLK/2

MCLK

MSYNC
MDATA4
MFLAG4

SDDAT

SYNC

CLK

TIMEB

BOOT

RESET

VDD1

GND1

SDTKI

SDTKO

SDCLK

SDRDY

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6

VD

Pad Ring

7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD1 Pad Ring

CS5376A

VDD2 Pad Ring

SINT

Pad Ring

VD

CS5376A

MOSI

MISO

SSI

48

SCK1

47

SSO

46

GPIO11:EECS

45

GPIO10

44

GPIO9

43

GPIO8

42

GPIO7

41

GPIO6

40

VD

39

GND

38

GND2

37

GPIO5

36

GPIO4:CS4

35

GPIO3:CS3

34

GPIO2:CS2

33

GPIO1:CS1

MDATA3

MDATA2

MDATA1

MFLAG3

MFLAG2

Figure 10. Power Supply Block Diagram

4. POWER SUPPLIES

The CS5376A has three sets of power supply in­puts. Two sets supply power to the I/O pins of the
device (VDD1, VDD2), and the third supplies
power to the logic core (VD). The I/O pin power
supplies determine the maximum input and output
voltages when interfacing to peripherals, and the
logic core power supply largely determines the
power consumption of the CS5376A.

4.1 Pin Descriptions

VDD1, GND1 - Pins 54,53

Sets the interface voltage to a microcontroller and
system telemetry. Can be driven with voltages from

3.3 V to 5 V.
VDD1 powers pins 1-5 and 41-64:

TRST, TMS, TCK, TDI, TDO

GND

GND2

MFLAG1

SI4

VDD2

SO

SI3

SI2

SI1

SCK2

GPIO0:CS0

GPIO6 - GPIO11:EECS
SSO

, SCK1, SSI, MISO, MOSI, SINT,
RESET
SDDAT, SDRDY

, BOOT, TIMEB, CLK, SYNC

, SDCLK, SDTKO, SDTKI

VDD2, GND2 - Pins 11, 25, 24, 38

Sets the interface voltage to the modulators, test
DAC, and serial peripherals. Can be driven with
voltages from 3.3 V to 5 V.

VDD2 powers pins 8-37:

TBSCLK, TBSDATA
MCLK/2, MCLK, MSYNC
MDATA1 - MDATA4
MFLAG1 - MFLAG4
SI1 - SI4, SO, SCK2
GPIO0:CS0 - GPIO5

DS612F4 21

CS5376A

VD, GND - Pins 7, 40, 6, 23, 39

Sets the operational voltage of the CS5376A logic
core. Can be driven with voltages from 3 V to 5 V.
A 3 V supply minimizes total power consumption.

4.2 Bypass Capacitors

Each power supply pin should be bypassed with
parallel 1 µF and 0.01 µF caps, or by a single

0.1 µF cap, placed as close as possible to the
CS5376A. Bypass capacitors should be ceramic

(X7R, C0G), tantalum, or other good quality di­electric type.

4.3 Power Consumption

Power consumption of the CS5376A depends pri­marily on the power supply voltage of the logic
core (VD) and the programmed digital filter clock
rate. Digital filter clock rates are selected based on
the required output word rate as explained in “Dig­ital Filter Initialization” on page 41.

22 DS612F4

CS5376A

RESET

Figure 11. Reset Control Block Diagram

Self-Tests

SELFTEST

Register

5. RESET CONTROL

The CS5376A reset signal is active low. When re­leased, a series of self-tests are performed and the
device either actively boots from an external EE­PROM or enters an idle state waiting for microcon­troller configuration.

5.1 Pin Descriptions

RESET - Pin 55

Reset input, active low.

BOOT - Pin 56

Boot mode select, latched following a RESET ris­ing edge.

BOOT = 1 = EEPROM boot
BOOT = 0 = Microcontroller boot

5.2 Reset Self-Tests

After RESET is released but before booting, a se­ries of digital filter self-tests are run. Results are

Self-Test

Type

Program ROM 0x00000A 0x00000F
Data ROM 0x0000A0 0x0000F0
Program RAM 0x000A00 0x000F00
Data RAM 0x00A000 0x00F000
Execution Unit 0x0A0000 0x0F0000

Pass
Code

Fail

Code

BOOT

Pin

1

EEPROM

Boot

0

µController

Boot

combined into the SELFTEST register (0x2F),
with 0x0AAAAA indicating all passed. Self-tests
require 60 ms to complete, after which configura­tion commands are serviced.

5.3 Boot Configurations

The logic state of the BOOT pin after reset deter­mines if the CS5376A actively reads configuration
information from EEPROM or enters an idle state
waiting for a microcontroller to write configuration
commands.

EEPROM Boot

When the BOOT pin is high after reset, the
CS5376A actively reads data from an external seri­al EEPROM and then begins operation in the spec­ified configuration. Configuration commands and
data are encoded in the EEPROM as specified in
the ‘Configuration By EEPROM’ section of this
data sheet, starting on page 26.

Microcontroller Boot

When the BOOT pin is low after reset, the
CS5376A enters an idle state waiting for a micro­controller to write configuration commands and
initialize filter operation. Configuration commands
and data are written as specified in the ‘Configura­tion By Microcontroller’ section of this data sheet,
starting on page 32.

DS612F4 23

CS5376A

Clock DividerCLK

MCLK

Generator

DSPCFG Register

Figure 12. Clock Generation Block Diagram

6. CLOCK GENERATION

The CS5376A requires a 32.768 MHz master clock
input, which is used to generate internal digital fil­ter clocks and external modulator clocks.

6.1 Pin Description

CLK - Pin 58

Clock input, nominal frequency 32.768 MHz.

Internal

and

Clocks

MCLK
Output

ensure recovered clocks have identical phase, sys­tem PLL designs should use a phase/frequency de­tector architecture.

6.3 Master Clock Jitter and Skew

Care must be taken to minimize jitter and skew in
the received master clock as both parameters affect
measurement performance.

6.2 Synchronous Clocking

To guarantee synchronous measurements through­out a sensor network, the CS5376A master clock
should be distributed to arrive at all nodes in phase.
The 32.768 MHz master clock can either be direct­ly distributed through the system telemetry, or re­constructed locally using a VCXO based PLL. To

Jitter in the master clock causes jitter in the gener­ated modulator clocks, resulting in sample timing
errors and increased noise.

Skew in the master clock from node to node creates
a sample timing offset, resulting in systematic mea­surement errors in the reconstructed signal.

24 DS612F4

CS5376A

0

SYNC

1

MSEN

MSYNC

Generator

Figure 13. Synchronization Block Diagram

7. SYNCHRONIZATION

The CS5376A has a dedicated SYNC input that
aligns the internal digital filter phase and generates
an external signal for synchronizing modulator an­alog sampling. By providing simultaneous rising
edges to the SYNC pins of multiple CS5376A de­vices, synchronous sampling across a network can
be guaranteed.

7.1 Pin Description

SYNC - Pin 59

Synchronization input, rising edge triggered.

7.2 MSYNC Generation

Digital

Filter

MSYNC
Output

0
1

TSYNC

Tes t Bit

Stream

phase. Filter convolutions restart, and the next out­put word is available one full sample period later.

Repetitive synchronization is supported when
SYNC events occur at exactly the selected output
word rate. In this case, re-synchronization occurs at
the start of a convolution cycle when the digital fil­ter state machine is already reset.

7.4 Modulator Synchronization

The external MSYNC signal phase aligns modula­tor analog sampling when connected to the
CS5371A/72A MSYNC input. This ensures syn­chronous analog sampling relative to MCLK.

The SYNC signal rising edge is used to generate a
retimed synchronization signal, MSYNC. The
MSYNC signal reinitializes internal digital filter
phase and is driven onto the MSYNC output pin to

Repetitive synchronization of the modulators is
supported when SYNC events occur at exactly the
selected output word rate. In this case, synchroni­zation will occur at the start of analog sampling.

phase align modulator analog sampling.
The MSEN bit in the digital filter CONFIG register

(0x00) enables MSYNC generation. See “Modula­tor Interface” on page 39 for more information
about MSYNC.

7.5 Test Bit Stream Synchronization

When the test bit stream generator is enabled, an
MSYNC signal can reset the internal data pointer.
This restarts the test bit stream from the first data
point to establish a known output signal phase.

7.3 Digital Filter Synchronization

The internal MSYNC signal resets the digital filter
state machine to establish a known digital filter

The TSYNC bit in the digital filter TBSCFG regis­ter (0x2A) enables synchronization of the test bit
stream by MSYNC. When TSYNC is disabled, the
test bit stream phase is not affected by MSYNC.

DS612F4 25

GPIO11:EECS

CS5376A AT25640

Figure 14. EEPROM Configuration Block Diagram

8. CONFIGURATION BY EEPROM

SCK1

MISO

MOSI

CS5376A

VD

387

46

48

50

51

WP VCC HOLD

1

CS

6

SCK

2

SO

5

SI

4

GND

After reset, the CS5376A reads the state of the
BOOT pin to determine a source for configuration
commands. If BOOT is high, the CS5376A ini­tiates serial transactions through the SPI 1 port to
read configuration information from an external
EEPROM.

8.1 Pin Descriptions

Pins required for EEPROM boot are listed here,
other SPI 1 pins are inactive.

GPIO11:EECS - Pin 46

EEPROM chip select output, active low.

SCK1 - Pin 48

Serial clock output, nominally 1.024 MHz.

MOSI - Pin 51

Serial data output pin. Valid on rising edge of
SCK1, transition on falling edge.

MISO - Pin 50

Serial data input pin. Valid on rising edge of SCK1,
transition on falling edge.

8.2 EEPROM Hardware Interface

When booting from EEPROM the CS5376A SPI 1
port actively performs serial transactions, as shown

in Figure 15, to read configuration commands and
data. 8-bit SPI opcodes and 16-bit addresses are
combined to read back 8-bit configuration com­mands and 24-bit configuration data.

System design should include a connection to the
configuration EEPROM for in-circuit reprogram­ming. The CS5376A SPI 1 pins go high impedance
when inactive to support external connections to
the serial bus.

8.3 EEPROM Organization

The boot EEPROM holds the 8-bit commands and
24-bit data required to initialize the CS5376A into
an operational state. Configuration information
starts at memory location 0x10, with addresses
0x00 to 0x0F free for use as manufacturing header
information.

The first serial transaction reads a 1-byte command
from memory location 0x10 and then, depending
on the command type, reads multiple 3-byte data
words to complete the command. Command and
data reads continue until the ‘Filter Start’ command
is recognized.

The maximum number of bytes that can be written
for a single configuration is approximately

26 DS612F4

CS5376A

Instruction Opcode Address Definition

Read 0x03 ADDR[15:0] Read data beginning at the address given in ADDR.

SPI 1 Read from EEPROM

SSI

MOSI

MISO

EECS

Cycle

SCK1

MOSI

READ

CMD
0x03 ADDR

2 BYTE

ADDR

ADDR

DATA1 DATA3DATA2

1 BYTE / 3 BYTE

DATA

18276543

MSB LSB

612345

MISO

EECS

MSB LSB612345

Figure 15. SPI 1 EEPROM Read Transactions

X

DS612F4 27

Write DF Register - 0x01

CS5376A

0000h

Mfg Header

0010h

EEPROM
Manufacturing
Information

8-bit Command
N x 24-bit Data

EEPROM
Command and

8-bit Command

Data Values

N x 24-bit Data

. . .

1FFFh

Figure 16. 8 Kbyte EEPROM Memory Organization

5 KByte (40 Kbit), which includes command over­head:

Memory Requirement Bytes

Digital Filter Registers (22) 154
FIR Coefficients (255+255) 1537
IIR Coefficients (3+5) 25
Test Bit Stream Data (1024) 3076

This EEPROM command writes a data value to the
specified digital filter register. Digital filter regis­ters control hardware peripherals and filtering
functions. See “Digital Filter Registers” on page 86
for the bit definitions of the digital filter registers.

Sample Command:

Write digital filter register 0x00 with data value
0x070431. Then write 0x20 with data 0x000240.

01 00 00 00 07 04 31
01 00 00 20 00 02 40

Write FIR Coefficients - 0x02

This EEPROM command writes custom coeffi­cients for the FIR1 and FIR2 filters. The first two
data words set the number of FIR1 and FIR2 coef­ficients to be written. The remaining data words are
the concatenated FIR1 and FIR2 coefficients.

A maximum of 255 coefficients can be written for
each FIR filter, though the available digital filter
computation cycles will limit their practical size.
See “FIR Filter” on page 47 for more information
about FIR filter coefficients.

‘Filter Start’ Command 1

Sample Command:

Total Bytes 4793

Write FIR1 coefficients 0x00022E, 0x000771 then

Table 4. Maximum EEPROM Configuration

FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
02 00 00 02 00 00 02
00 02 2E 00 07 71 FF FF B9 FF FE 8D

Supported serial configuration EEPROMs are

Write IIR Coefficients - 0x03

SPI mode 0 (0,0) compatible, 16-bit addresses, 8­bit data, larger than 5 KByte (40 KBit). ATMEL
AT25640, AT25128, or similar serial EEPROMs
are recommended.

This EEPROM command writes custom coeffi­cients for the two stage IIR filter. The IIR architec­ture and number of coefficients is fixed, so eight
data words containing coefficient values always

8.4 EEPROM Configuration Commands

immediately follow the command byte. The IIR co­efficient write order is: a11, b10, b11, a21, a22,
b20, b21, and b22. See “IIR Filter” on page 55 for

A summary of available EEPROM commands is

more information about IIR filter coefficients.

shown in Table 5.

28 DS612F4

CS5376A

Sample Command:

Write IIR1 coefficients 0x84BC9D, 0x7DA1B1,
0x825E4F, and IIR2 coefficients 0x83694F,
0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104.

03
84 BC 9D 7D A1 B1 82 5E 4F 83 69 4F
3C AD 5F 3E 51 04 83 5D F8 3E 51 04

Write ROM Coefficients - 0x04

This EEPROM command selects the on-chip coef­ficients for the FIR1, FIR2, IIR 1st order, and IIR
2nd order filters for use by the digital filter. One
data word is required to select which internal coef­ficient sets to use. See “Filter Coefficient Selec­tion” on page 41 for information about selecting
on-chip FIR and IIR coefficient sets.

Sample Command:

Select IIR1 and IIR2 3 Hz @ 500 SPS low-cut co­efficients, with FIR1 and FIR2 linear phase high­cut coefficients. Data word 0x002200.

04 00 22 00

Write TBS Data - 0x05

This EEPROM command writes a custom data set
for the test bit stream (TBS) generator. This com­mand, along with the ability to program the test bit
stream generator interpolation and clock rate, can
create custom frequency test signals.

The first data word sets the number of TBS data to
be written and the remaining data words are the
TBS data values. See “Test Bit Stream Generator”
on page 64 for information about using custom test
bit stream data sets.

Name CMD

8-bit

NOP 00 - No Operation
WRITE DF REGISTER 01 REG

WRITE FIR COEFFICIENTS 02 NUM FIR1

WRITE IIR COEFFICIENTS 03 a11

WRITE ROM COEFFICIENTS 04 COEF SEL Use On-Chip Coefficients
WRITE TBS DATA 05 NUM TBS

WRITE ROM TBS 06 - Use On-Chip TBS Data
FILTER START 07 - Start Digital Filter Operation

DATA
24-bit

DATA

NUM FIR2

(FIR COEF)

b10

b11
a21
a22
b20
b21
b22

(TBS DATA)

Description

Write Digital Filter Register

Write Custom FIR Coefficients

Write Custom IIR Coefficients

Write Custom Test Bit Stream Data

(DATA) indicates multiple words of this type are to be written.

Table 5. EEPROM Boot Configuration Commands

DS612F4 29

CS5376A

Sample Command:

Write test bit stream data 0x000000, 0x0007DA,
0x000FB5, 0x00178F.

05 00 00 04
00 00 00 00 07 DA 00 0F B5 00 17 8F

Write TBS ROM Data - 0x06

This EEPROM command selects the on-chip test
bit stream (TBS) data for use by the TBS generator.
No data words are required for this EEPROM com­mand. See “Test Bit Stream Generator” on page 64
for more information about the on-chip test bit
stream data set.

Sample Command:

06

Filter Start - 0x07

This EEPROM command initializes and starts the
digital filter. Measurement data becomes available
one full sample period after this command is re­ceived. No data words are required for this EE­PROM command.

Sample Command:

07

8.5 Example EEPROM Configuration

Table 6 shows an example EEPROM file for a min­imal CS5376A configuration.

30 DS612F4