Cirrus Logic CS5374 User Manual

INA1+
INB1+

MUX1

MUX2

INB1-

INA1-

GUARD1

+

-

­+

400 Ω 400 Ω

INA2+
INB2+

INB2-

INA2-

+

-

­+

400 Ω 400 Ω

Reset, Clock,

and

Synchronization

INR1- VA+

MFLAG1

MCLK
MSYNC

MFLAG2

MDATA2

GAIN1GAIN2

GUARD2 INR2- INR2+

4th Order

Modulator

4

th

Order

Modulator

INF1- INF1+INR1+

RST

SPITM Serial

Interface

SDI

SDO

SCLK
CS

INF2+INF2-OUT2-OUT2+

OUT1+ OUT1-

CS5374

VA-

GND

VD

VREF-VREF+

VA+
VA-

MDATA1

CS5374

Dual High-performance Amplifier &

Features

 High Input Impedance Differential Amplifier

• Ultra-low input bias: < 1 pA

• Max signal amplitude: 5 Vpp differential

 Fourth Order Delta-Sigma (ΔΣ) Modulator

• Signal Bandwidth: DC to 2 kHz

• Common mode rejection: 110 dB CMRR

 Differential Analog Input, Digital ΔΣ Output

• Multiplexed inputs: INA, INB, 800Ω termination

• Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x

 Excellent Amplifier Noise Performance

•1.5 μVpp between 0.1 Hz and 10 Hz

• 11 nV /

 High Modulator Dynamic Range

• 126 dB SNR @ 215 Hz BW (2 ms sampling)

• 123 dB SNR @ 430 Hz BW (1 ms sampling)

 Low Total Harmonic Distortion

• –118 dB THD typical (0.000126%)

• –108 dB THD maximum (0.0004%)

 Low Power Consumption

• Normal operation: 6.5 mA per channel

• Power down: 15 μA per channel max

 Dual Power Supply Configuration

• VA+ = +2.5 V; VA– = –2.5 V; VD = +3.3 V

√Hz from 200 Hz to 2 kHz

Description

The CS5374 combines two marine seismic analog mea ­surement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a high
input impedance programmable gain differential amplifi­er that buffers analog signals into a high-performance,
fourth-order ΔΣ modulator. The low-noise ΔΣ modulator
converts the analog signal into a one-bit serial bit stream
suitable for the CS5376A digital filter.

Each amplifier has two sets of external inputs, INA and
INB, to simplify system design as inputs from a hydro­phone sensor or the CS4373A test DAC. An internal
800Ω termination can also be selected for noise tests.
Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x,
32x, 64x) and match the CS4373A test DAC output at­tenuation settings for full-scale testing at all gain ranges.
Both the input multiplexer and gain are set by registers
accessed through a standard SPI™ port.

Each fourth-order ΔΣ modulator has very high dynamic
range combined with low total harmonic distortion and
low power consumption. It converts differential analog
signals from the amplifier to an oversampled ΔΣ serial bit
stream which is decimated by the CS5376A digital filter
to a 24-bit output at the final output word rate.

ORDERING INFORMATION

See page 43.

ΔΣ

Modulator

Preliminary Product Information

http://www.cirrus.com

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2010

(All Rights Reserved)

SEP '10

DS862F2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4

SPECIFIED OPERATING CONDITIONS ................................................................................ 4

ABSOLUTE MAXIMUM RATINGS .......................................................................................... 4

THERMAL CHARACTERISTICS ........................... ... .... ... ... ... ....................................... ........... 5

ANALOG CHARACTERISTICS ....................... ................................ ................................ ........ 5

PERFORMANCE SPECIFICATIONS ...................................................................................... 7

CHANNEL PERFORMANCE PLOTS ...................................................................................... 9

DIGITAL CHARACTERISTICS ........................ ................................ ................................ ...... 10

SPI™ INTERFACE TIMING (EXTERNAL MASTER) ............................................................ 12

POWER SUPPLY CHARACTERISTICS ......................... ...................................................... 13

2. GENERAL DESCRIPTION..................................................................................................... 14

3. AMPLIFIER OPERATION ...................................................................................................... 16

3.1 Amplifier Inputs — INA, INB.......................................................................................... 16

3.1.1 Multiplexer Settings — MUX............................................................................... 16

3.1.2 Gain Settings — GAIN........................................................................................ 16

3.2 Amplifier Outputs — OUTR, OUTF............................................................................... 16

3.2.1 Guard Output — GUARD.................................................................................... 16

3.3 Differential Signals . .... ... ... ... .... ... ....................................... ... ...................................... ... 17

4. MODULATOR OPERATION .................................................................................................. 18

4.1 Modulator Anti-Alias Filter............................................................................................. 18

4.2 Modulator Inputs — INR, INF........................................................................................ 19

4.2.1 Modulator Input Impedance ................................................................................ 19

4.2.2 Modulator Idle Tones — OFST.............. .... ... ... ... .... ... ...................................... ... 19

4.3 Modulator Output — MDATA ........................................................................................ 19

4.3.1 Modulator One’s Density............................... ... ... .... ... ...................................... ... 19

4.3.2 Decimated 24-bit Output..................................................................................... 19

4.4 Modulator Stability — MFLAG.... ... ... ....................................... ...................................... 20

4.5 Modulator Clock Input — MCLK.................................................................................... 20

4.6 Modulator Synchronization — MSYNC......................................................................... 20

5. SPI

6. POWER MODES .................................................................................................................... 29

7. VOLTAGE REFERENCE ....................................................................................................... 30

8. POWER SUPPLIES .............................................................................................................. 32

TM

SERIAL PORT ............................................................................................................. 21

5.1 SPI Pin Descriptions ..................................................................................................... 21

5.2 SPI Serial Transactions................................................................................................. 21

5.3 SPI Registers ................................................................................................................23

5.3.1 VERSION — 0x00............................................................................................... 23

5.3.2 AMP1CFG — 0x01 ............................................................................................. 23

5.3.3 AMP2CFG — 0x02 ............................................................................................. 23

5.3.4 ADCCFG — 0x03................................................................................................ 24

5.3.5 PWRCFG — 0x04............................................................................................... 24

5.4 Example: CS5374 Configuration by an External SPI Master........................................ 24

5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port ...................................... 25

5.5.1 CS5376A SPI 1 Transactions ............................................................................. 25

6.1 Normal Operation.......................................................................................................... 29

6.2 Power Down, MCLK Enabled........................................................................................ 29

6.3 Power Down, MCLK Disabled....................................................................................... 29

7.1 VREF Power Supply ..................................................................................................... 30

7.2 VREF RC Filter ............................................................................................................. 30

7.3 VREF PCB Routing....................................................................................................... 30

7.4 VREF Input Impedance................................................................................................. 30

7.5 VREF Accuracy............................................................................................................. 31

8.1 Analog Power Supplies................................................................................................. 32

8.2 Digital Power Supply..................................................................................................... 32

8.3 Power Supply Bypassing .............................................. .... ... ...................................... ... 32

CS5374

CS5374

2

8.4 PCB Layers and Routing............................................................................................... 33

8.5 Power Supply Rejection............................................................................. ................... 33

8.6 SCR Latch-up Considerations....................................................................................... 33

8.7 DC-DC Converters........................................................................................................ 33

9. SPI

10. PIN DESCRIPTIONS ............................................................................................................. 40

11. PACKAGE DIMENSIONS ...................................................................................................... 42

12. ORDERING INFORMATION ................................................................................................. 43

13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........................... 43

14. REVISION HISTORY ............................................................................................................44

TM

REGISTER SUMMARY................................................................................................ 34

9.1 VERSION: 0x00 ................................................................... ... ...................................... 35

9.2 AMP1CFG: 0x01........................................................................................................... 36

9.3 AMP2CFG: 0x02........................................................................................................... 37

9.4 ADCCFG: 0x03 ............................................................................................................. 38

9.5 PWRCFG: 0x04 ............................................................................................................ 38

LIST OF FIGURES

Figure 1. External Anti-alias Filter Components.............................................................................. 6

Figure 2. CS5374 Amplifier Noise Performance........... ... .... ........................................................... 7

Figure 3. CS5374 Noise Performance (1x Gain) ........................................................................... 9

Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance ................................................... 9

Figure 5. Digital Rise and Fall Times SYNC from external system............................................... 10

Figure 6. System Synchronization Diagram.................................................................................. 10

Figure 7. MCLK / MSYNC Timing Detail....................................................................................... 11

Figure 8. SDI Write Timing in SPI Slave Mode ............................................................................. 12

Figure 9. SDO Read Timing in SPI Slave Mode........................................................................... 12

Figure 10. CS5374 System Block Diagram................................................................................... 14

Figure 11. CS5374 Connection Diagram...................................................................................... 15

Figure 12. CS5374 to CS5376A Digital Interface.......................................................................... 15

Figure 13. CS5374 Amplifier Block Diagram................................................................................. 16

Figure 14. CS5374 Modulator Block Diagram............................................................................... 18

Figure 15. SPI Interface Block Diagram........................................................................................ 21

Figure 16. CS5374 (Slave) Serial Transactions with CS5376A (Master)...................................... 22

Figure 17. Power Mode Diagram.................................................................................................. 29

Figure 18. Voltage Reference Circuit............................................................................................30

Figure 19. Power Supply Diagram................................................................................................ 32

Figure 20. Hardware Version ID Register VERSION................................. ... .... ............................ 35

Figure 21. Amplifier 1 Configuration Register AMP1CFG............................................................. 36

Figure 22. Amplifier 2 Configuration Register AMP2CFG............................................................. 37

Figure 23. Modulator 1 & 2 Configuration Register ADCCFG....................................................... 38

Figure 24. Power Configuration Register PWRCFG..................................................................... 39

CS5374

CS5374

LIST OF TABLES

Table 1. 24-bit Output Coding ...................................................................................................... 20

Table 2. SPI Configuration Registers ...........................................................................................23

Table 3. Digital Selections for Gain and Input Mux Control ................................... ... .... ............... 23

Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers .... 24

Table 5. Example CS5376A SPI 1 Transactions to Write and Read the GPCFG0 Register ....... 25

Table 6. Example CS5376A SPI 1 Transactions to Write the CS5374 AMP1CFG Register .......26

Table 7. Example CS5376A SPI 1 Transactions to Write AMP2CFG and ADCCFG .................. 27

Table 8. Example CS5376A SPI 1 Transactions to Write the CS5374 PWRCFG Register ......... 28

3

CS5374

CS5374

1. CHARACTERISTICS AND SPECIFICATIONS

• Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions.

• Typical performance characteristics and specifications are derived from measurements taken at nom­inal supply voltages and T

= 25°C.

A

• GND = 0 V, all voltages with respect to 0 V.

• Device connected as shown in Figure 11 and Figure 12 unless otherwise noted.

SPECIFIED OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

Bipolar Power Supplies

Positive Analog +
Negative Analog (Note 1) +
Positive Digital +

Voltage Reference

[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V

Thermal

Ambient Operating Temperature -CNZ T

2% VA+ 2.45 2.50 2.55 V
2% VA- -2.45 -2.50 -2.55 V
3% VD 3.20 3.30 3.40 V

A

-10 25 70 °C

Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions.

2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance.

3. Channel-to-channel gain accuracy is directly proportional to the voltage reference absolute accuracy.

4. VREF inputs must satisfy: VA- ≤ VREF- < VREF+ ≤ VA+.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Unit

DC Power Supplies Positive Analog

Negative Analog

Digital
Analog Supply Differential [(VA+) - (VA-)] VA
Digital Supply Differential [(VD) - (VA-)] VD
Input Current, Any Pin Except Supplies (Note 5, 6)I
Input Current, Power Supplies (Note 5)I
Output Current (Note 5)I
Power Dissipation PD - 500 mW
Analog Input Voltages V
Digital Input Voltages V
Storage Temperature Range T

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 5. Transient currents up to 100mA will not cause SCR latch-up.

6. Includes continuous over-voltage conditions on the analog input pins.

VA+

VA-

VD

DIFF
DIFF
IN

PWR

OUT

INA
IND

STG

-0.3

-6.8

-0.3

-6.8V

-6.8V

-+10 mA

-+50 mA

-+25 mA

(VA-)-0.5 (VA+)+0.5 V

-0.5 (VD)+0.5 V

-65 150 °C

6.8

0.3

6.8

V
V
V

4

CS5374

CS5374

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Ambient Operating Temperature T
Storage Temperature Range T
Allowable Junction Temperature T
Junction to Ambient Thermal Impedance (4-layer PCB) θ

A

STR

JCT

JA

-10 - 70 °C

-65 - 150 °C

--125°C

-26-°C/W

ANALOG CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Amplifier Inputs

Signal Frequencies BW DC - 2000 Hz
Differential Gain GAIN x1 - x 64
Common Mode Gain (Note 7) GAIN
Common Mode Voltage V
Voltage Range (Signal + Vcm) x1

CM

cm

V

IN

x2 - x64

Full Scale Differential Input x1

x2
x4
x8

V

INFS

x16
x32

x64
Differential Input Impedance Z
Common Mode Input Impedance Z
Input Bias Current I

INDIFF

INCM

IN

Amplifier Outputs

Full Scale Output, Differential V
Output Voltage Range (Signal + Vcm) V
Output Impedance (Note 8)Z
Output Impedance Drift (Note 8)Z
Output Current I
Load Capacitance C

OUT
RNG
OUT

TC

OUT

L

Guard Outputs

Guard Output Voltage V
Guard Output Impedance (Note 8)ZG
Guard Output Current IG
Guard Load Capacitance CG

GUARD

OUT

OUT

L

-x1-

(VA-)+2.5

-

(VA-)+0.7
(VA-)+0.7

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-V

(VA+)-1.25
(VA+)-1.75

5

2.5

1.25
625

312.5

156.25

78.125

V
V

V
mV
mV
mV
mV

-1, 20- TΩ, pF

- 0.5, 40 - TΩ, pF

-140pA

--5V

(VA-)+0.5

-

(VA+)-0.5

-40- Ω

-0.38- Ω/°C

--+25 mA

--100nF

-Vcm-V

-500- Ω

--40μA

--100pF

V

pp
pp
pp

pp
pp
pp
pp

pp

V

Notes: 7. Common mode signals pass thro ug h th e diff er en tial amplifier architecture and are rejected by the

modulator CMRR.

8. Output impedance characteristics are approximate and can vary up to ±30% depending on process
parameters.

5

CS5374

MODULATOR

INR+
INF+

INF­INR-

20nF
C0G

20nF
C0G

680

AMPLIFIER

OUT+

OUT-

680

680

680

CS5374

Figure 1. External Anti-alias Filter Components

CS5374

ANALOG CHARACTERISTICS (CONT.)

Parameter Symbol Min Typ Max Unit

Modulator Inputs

Input Signal Frequencies (Note 9) V
Full-scale Differential AC Input V
Full-scale Differential DC Input V
Input Common Mode Voltage V
Input Voltage Range (V

±Signal) V

cm

Differential Input Impedance INR±

INF±

Single-ended Input Impedance INR±

INF±

External Anti-alias Filter Series Resistance
(Note 10) Differential Capacitance

RNG

ZDIF
ZDIF

ZSE
ZSE

R

C

DIFF

BW

AC
DC

CM

INR
INF

INR
INF

AA

VREF Inputs

[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V
VREF Input Current VREF
VREF Input Noise (Note 11)VREF

II

IN

DC - 2000 Hz

--5V

-2.5 - 2.5 V

(VA-)+2.5

-

(VA-)+0.7

-

-

-

-

-

-

-

20

1

40

2

680

20

-V

(VA+)-1.25

-

-

-

-

-

-

pp

DC

V

kΩ

MΩ

kΩ

MΩ

Ω

nF

-120- µA

--1µV

rms

Notes: 9. The upper bandwidth limit is determined by the selected digital filter cut-off frequency.

10. Anti-alias capacitors are discrete exte rnal components and must be of good quality (C0G, NPO, po ly).
Poor-quality capacitors will degrade total harmonic distortion (THD) performance. See Figure 1 for
external anti-alias filter connections.

11. Maximum integrated noise over the mea surement bandwidth for the voltage reference device attached
to the VREF inputs.

6

CS5374

nV/ Hz

fA/ Hz

0

5

10

15

20

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (Hz)

CS5374 Amplifier In-Band Noise

Noise Density (nV/rtHz)

0

100

200

300

400

0.1

1 10 100 1k

Frequency (Hz)

CS5374 Amplifier Wide Band Noise

Noise Density (nV/rtHz)

10k 100k 1M

Figure 2. CS5374 Amplifier Noise Performance

PERFORMANCE SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

Amplifier Noise

Voltage Noise f
Voltage Noise Density f0 = 200 Hz to 2 kHz VN
Current Noise Density IN

Channel Dynamic Range

Dynamic Range (1/4 ms) DC to 1720 Hz
(1x Gain, Multiple OWRs) (1/2 ms) DC to 860 Hz
(Note 9, 12) (1ms)DCto 430Hz

Dynamic Range 1x
(Multiple Gains, 1 ms OWR) 2x
(Note 9, 12)3x

Channel Distortion

Total Harmonic Distortion 1x
(Note 13)2x

= 0.1 Hz to 10 Hz VN

0

(2 ms) DC to 215 Hz
(4 ms) DC to 108 Hz
(8 ms) DC to 54 Hz

(16 ms) DC to 27 Hz

8x
16x
32x
64x

4x

8x
16x
32x
64x

PP

D

D

-1.5 3 μV

-11 14

-20 -

SNR -

-

121

-

-

-

-

SNR 121

-

-

-

-

-

-

-

-

-

THD

-

-

-

-

105
120
123
126
129
131
135

123
122
120
116

111

105

98

-118

-119

-119

-119

-118

-115

-112

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-108

-

-

-

-

-

-

CS5374

pp

dB
dB
dB
dB
dB
dB
dB

dB
dB
dB
dB
dB
dB
dB

dB
dB
dB
dB
dB
dB
dB

Notes: 12. Dynamic Range defined as 20 log [(RMS full scale) / (RMS idle noise)] where idle noise is measured

with the amplifier input terminated. Dynamic Range is dominated by high-frequency quantization noise
at the 1/4 ms rate and amplifier noise at high gain.

13. Tested with a 31.25 Hz sine wave at 1 ms sampling rate and -1dB amplitude.

7

CS5374

CS5374

PERFORMANCE SPECIFICATIONS (CONT.)

CS5374

Parameter Symbol

Channel Gain Accuracy

Channel Gain, Offset Corrected (Note 3, 14)GAIN

Absolute Gain Accuracy (Note 3, 15)GAIN
Relative Gain Accuracy 2x

(Note 16)4x

8x

GAIN
16x
32x
64x

Gain Drift (Note 17) GAIN

LSB

ABS

REL

TC

-6101194

0xA2E736

-±1+2%

-0.3

-

-

-

-

-

-25-ppm/°C

-

-

-0.1

-0.1

0.1

0.4

0.4

0.3

6101194

0x5D18CA

0.1

-

-

-

-

-

Channel Offset Accuracy

Amplifier Offset Voltage, Input Referred (Note 18)OFST
Amplifier Offset Drift, Input Referred (Note 17)OFST
Modulator Offset Voltage, Differential (OFST
Modulator Offset Voltage, Channel 1 (OFST
Modulator Offset Voltage, Channel 2 (OFST

=1) OFST
=0) OFST

=0) OFST
Modulator Offset Drift (Note 17)OFST
Offset After Calibration (Note 19)OFST
Offset Calibration Range (Note 20)OFST

AMP

ATC

MOD
MOD1
MOD2

MTC

CAL

RNG

- ±250 ±750 µV

-0.3-µV/°C

-±1- mV

--60- mV

--35- mV

-1-µV/°C

-±1- μV

-100- %FS

Channel CMRR and Crosstalk

Common Mode Rejection Ratio CMRR - 110 - dB
Crosstalk, Amplifier Multiplexed Inputs CXT
Crosstalk, Channel-to-Channel CXT

MI

CC

--130- dB

--130- dB

UnitMin Typ Max

LSB
LSB

%
%
%
%
%
%

Notes: 14. Channel Gain is the nominal full-scale 24-bit output code from the CS5376A digital filter for a 5 VPP

differential signal into the CS5374 analog inputs at 1x gain. Value is offset corrected.

15. Absolute gain accuracy tests the matching of 1x gain across multiple CS5374 channels in a system.

16. Relative gain accuracy tests the tra cking of 2x, 4x, 8x, 16x, 32x, 64x gain re lative to 1x gain on a single
CS5374 channel.

17. Specification is for the parameter over the specified temperature range and is for the CS5374 device
only. It does not include the effects of external components.

18. Offset voltage is tested with the amplifier inputs connected to the internal 800 Ω termination.

19. The offset after calibration specification is measured from the digitally calibrated output codes of the
CS5376A digital filter.

20. Offset calibration is performed in the CS5376A digital filter and includes the full-scale sig nal range.

8

CHANNEL PERFORMANCE PLOTS

Figure 3. CS5374 Noise Performance (1x Gain)

Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance

CS5374

CS5374

9

CS5374

0.9 * VD

0.1 * VD

t

fall

t

rise

Figure 5. Digital Rise and Fall Times SYNC from external system.

MCLK

MSYNC

t

MDATA

TDATA

0

SYNC

MFLAG

Figure 6. System Synchronization Diagram

SYNC from External. MCLK, MSYNC, TDATA from CS5376A. MDATA, MFLAG from CS5374.

DIGITAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Digital Inputs

High-level Input Voltage (Note 21)V
Low-level Input Voltage (Note 21)V
Input Leakage Current I
Digital Input Capacitance C
Input Rise Times Except MCLK t
Input Fall Times Except MCLK t

Digital Outputs

High-level Output Voltage, I
Low-level Output Voltage, I

=-40μAV

out

=40μAV

out

High-Z Leakage Current I
Digital Output Capacitance C
Output Rise Times (Note 22) t
Output Fall Times (Note 22) t

IH

IL

IN

IN
RISE
FALL

OH

OL

OZ

OUT
RISE
FALL

CS5374

0.6*VD - VD V

0.0 - 0.8 V

-±1±10μA

-9- pF

--100ns

--100ns

VD - 0.3 - - V

--0.3V

-±1±10μA

-9- pF

--100ns

--100ns

Notes: 21. Device is intended to be driven with CMOS logic levels.

22. Guaranteed by design and/or characterization.

10

CS5374

MCLK

MSYNC

t

0

t

MSS

1 / f

MCLK

t

MSYNC

t

MSH

MDATA

MFLAG

1 / f

MDATA

Figure 7. MCLK / MSYNC Timing Detail

DIGITAL CHARACTERISTICS (CONT.)

Parameter Symbol Min Typ Max Unit

Master Clock Input

MCLK Frequency (Note 23)f
MCLK Duty Cycle MCLK
MCLK Rise Time t
MCLK Fall Time t
MCLK Jitter (in-band or aliased in-band) MCLK
MCLK Jitter (out-of-band) MCLK

Master Sync Input

MSYNC Setup Time to MCLK Falling (Note 24)t
MSYNC Period (Note 24)t
MSYNC Hold Time after MCLK Falling (Note 24)t

MDATA Output

MDATA Output Bit Rate f
MDATA Output One’s Density Range (Note 22)MDAT
Full-scale Output Code, Offset Corrected (Note 25)MDAT

MCLK

DTC
RISE
FALL

IBJ

OBJ

MSS

MSYNC

MSH

MDATA

1D
FS

CS5374

- 2.048 - MHz

40 - 60 %

- - 50 ns

- - 50 ns

--300ps

--1ns

20 366 - ns
40 976 - ns
20 610 - ns

-512-kbits/s

14 - 86 %

0xA2E736 - 0x5D18CA

Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabl ed, the CS5374 device automatically

enters a power-down state. See Power Supply Characteristics for typical power-down timing.

24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,
synchronization instant (t

) is on the next MCLK rising edge.

0

25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.

11

CS5374

MSB MSB - 1 LSB

t

6

t

5

t

4

t

3

t

2

t

1

CS

SDI

SCK

Figure 8. SDI Write Timing in SPI Slave Mode

MSB MSB - 1 LSB

t

9

t

8

t

7

CS

SDO

SCK

t

10

Figure 9. SDO Read Timing in SPI Slave Mode

SPI™ INTERFACE TIMING (EXTERNAL MASTER)

Parameter Symbol Min Typ Max Unit

SDI Write Timing

CS

Enable to Valid Latch Clock t
Data Set-up Time Prior to SCK Rising t
Data Hold Time After SCK Rising t
SCK High Time t
SCK Low Time t
SCK Falling Prior to CS

Disable t

1
2
3
4
5
6

SDO Read Timing

SCK Falling to New Data Bit t
SCK High Time t
SCK Low Time t
SCK Falling Hold Time Prior to CS

Disable t

7
8
9

10

CS5374

60 - - ns
60 - - ns

60 - - ns
120 - - ns
120 - - ns

60 - - ns

- - 90 ns
120 - - ns
120 - - ns

60 - - ns

12

CS5374

CS5374

POWER SUPPLY CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Power Supply Current, ch1 + ch2 combined

Analog Power Supply Current (Note 26)I
Digital Power Supply Current (Note 26)I

A
D

Power Supply Current, ch1 or ch2 only

Analog Power Supply Current (Note 26)I
Digital Power Supply Current (Note 26)I

A
D

Power Down Current, MCLK enabled

Analog Power Supply Current (Note 26)I
Digital Power Supply Current (Note 26)I

A
D

Power Down Current, MCLK disabled

Analog Power Supply Current (Note 26)I
Digital Power Supply Current (Note 26)I
Power Down Timing (after MCLK disabled) (Note 22)PD

A
D

TC

Power Supply Rejection

Power Supply Rejection Ratio (Note 22)PSRR - 100 - dB

-1316mA

-50100μA

-6.58 mA

-2550 μA

- 150 250 μA

-1075 μA

-215μA

-115μA

-40- μS

Notes: 26. All outputs unloaded. Digital inputs forced to VD or GND respectively. Amplifier inputs connected to the

800 Ω internal termination.

13

CS5374

Hydrophone

Sensor

Hydrophone

Sensor

Hydrophone

Sensor

Hydrophone

Sensor

DS

Modulator

Digital Filter

CS5376A

Test
DAC

Microcontroller

or

Configuration

EEPROM

System

Telemetry

AMP

CS4373A

CS5374

DS

Modulator

AMP

M
U
X

DS

Modulator

AMP

M
U
X

CS5374

DS

Modulator

AMP

M
U
X

M
U
X

Figure 10. CS5374 System Block Diagram

CS5374

2. GENERAL DESCRIPTION

The CS5374 combines two marine seismic analog
measurement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a
high input impedance programmable gain differen­tial amplifier that buffers analog signals into a
high-performance, fourth-order ΔΣ modulator. The
low-noise ΔΣ modulator converts the analog signal
into a one-bit serial bit stream suitable for the
CS5376A digital filter.

Each amplifier has two sets of external inputs, INA
and INB, to simplify system design as inputs from
a hydrophone sensor or the CS4373A test DAC. An
internal 800 Ω termination can also be selected for
noise tests. Gain settings are binary weighted (1x,
2x, 4x, 8x, 16x, 32x, 64x) and match the CS4373A
test DAC output attenuation settings for full-scale
testing at all gain ranges. Both the input multiplex-

er and gain are set by registers accessed through a
standard SPI™ port.

Each fourth-order ΔΣ modulator has very high dy­namic range combined with low total harmonic dis­tortion and low power consumption. It converts
differential analog signals from the amplifier to an
oversampled ΔΣ serial bit stream which is decimat­ed by the CS5376A digital filter to a 24-bit output
at the final output word rate.

Figure 10 shows the system-level architecture of a

4-channel acquisition system using two CS5374,
one CS5376A digital filter and one CS4373A test
DAC.

Figure 11 and Figure 12

grams for the CS5374 device when connected to

shows connection dia-

the CS5376A digital filter.

14