Cirrus Logic CS5372A User Manual

CS5371A

Clock

Generator

INF1+

VREF+
VREF-

VA+

VA-

VD

GND

PWDN1

MFLAG1

MDATA1

MCLK
MSYNC

MFLAG2

MDATA2

PWDN2

INF1­INR1-

INR1+

INF2+
INF2­INR2-

INR2+

4th Order

ΔΣ Modulator

4th Order

ΔΣ Modulator

OFST

CS5372A

Clock

Generator

INF+

VREF+
VREF-

VA+

VA-

VD

GND

PWDN

MFLAG

MDATA

MCLK
MSYNC

INF­INR-

INR+

4th Order

ΔΣ Modulator

OFST

CS5371A

CS5372A

Low-power, High-performance

Features

 Fourth-order ΔΣ Architecture
 Clock-jitter-tolerant Architecture
 Input Voltage: 5 V
 Input Signal Bandwidth: DC to 2 kHz
 High Dynamic Range

• 127 dB SNR @ 215 Hz BW (2 ms sampling)

• 124 dB SNR @ 430 Hz BW (1 ms sampling)



Low Total Harmonic Distortion

• -118 dB THD typical (0.000126%)



Low Power Consumption

• Normal operation: 25 mW per channel

• Power down: 10 µW per channel

Small Footprint, 24-pin SSOP package



 Multi-channel System Support

• 1-channel System: CS5371A

• 2-channel System: CS5372A

• 3-channel System: CS5371A + CS5372A

• 4-channel System: CS5372A + CS5372A



Bipolar Power Supply Configuration

• VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V

Fully Differential

pp

ΔΣ

Modulators

Description

The CS5371A and CS5372A are one- and two-channel,
high-dynamic-range, fourth-order ΔΣ modulators intend­ed for geophysical and sonar applications. When
combined with CS3301A / CS3302A differential amplifi­ers, the CS4373A test DAC and CS5376A digital filter, a
small, low-power, self-testing, high-accuracy, multi­channel measurement system results.

The modulators have high dynamic range and low total
harmonic distortion with very low power consumption.
They convert differential analog input signals from the
CS3301A / CS3302A amplifiers to an oversampled seri­al bit stream at 512 kbits per second. This oversampled
bit stream is then decimated by the CS5376A digital filter
to a 24-bit output at the selected output word rate.

In normal operation, power consumption is 5 mA per
channel. Each modulator can be independently powered
down to 500 µA per channel, and by halting the input
clock they will enter a micro-power state using only 2 µA
per channel.

The CS5371A and CS5372A modulators are available in
small 24-pin SSOP packages, providing exceptional per­formance in a very small footprint.

ORDERING INFORMATION

See page 30.

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2010

(All Rights Reserved)

SEP ‘10

DS748F3

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

SPECIFIED OPERATING CONDITIONS.................................................................................4

ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4

TEMPERATURE CONDITIONS ...............................................................................................5

ANALOG INPUT CHARACTERISTICS ................................................................................... 5

PERFORMANCE CHARACTERISTICS..................................... ......................................... .... . 6

PERFORMANCE CHARACTERISTICS (CONT.) .................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... . 7

PERFORMANCE PLOTS.................... ... ... .......................................... ... .... ... ........................... 8

DIGITAL CHARACTERISTICS ................................................................................................9

DIGITAL CHARACTERISTICS (CONT.) ...............................................................................10

DIGITAL CHARACTERISTICS (CONT.) ............................................................................11

POWER SUPPLY CHARACTERISTICS................................................................................ 12

2. SYSTEM DIAGRAM ............................................................................................................13

3. MODULATOR OPERATION ................................................................................................... 14

3.1 One’s Density ...................................... ... .... ... ... ... .......................................... ...................14

3.2 Decimated 24-bit Output ..................................................................................................15

3.3 Synchronization .................................. ... .... ... .......................................... .........................15

3.4 Idle Tones ........................ ... ... .... ...................................... .... ... ... ... ... .... ... .........................15

3.5 Stability ...................................... ... ... ....................................... ... ... ... .... ... ... ... ...................15

4. ANALOG SIGNALS ................................................................................................................ 16

4.1 INR±, INF± Modulator Inputs ........... ... ... .......................................................................... 16

4.2 Input Impedance ........................ ... ... ... ... .... ... ... ... .......................................... ...................16

4.3 Anti-alias Filter .................... ....................................... ... ... .... ... ... ... ... ................................ 17

4.4 Analog Differential Signals ......... ... ... ... ... .... .......................................... ... ... ... .... ... ... ... ... ... 17

5. DIGITAL SIGNALS .................................................................................................................18

5.1 MCLK Connection .. ... .... ... ... ... .... ... ....................................... ... ... ... ... .... ... ... ......................18

5.2 MSYNC Connection ................................... ... ... ... ....................................... ... .... ... ... ... ... ... 18

5.3 MDATA Connection ......................... ... ... .... ... ... ... .......................................... .... ... ... .........19

5.4 MFLAG Connection ...................................... ... ... .... ... ... ...................................................19

5.5 OFST Connection ...................... ... ... ... .......................................... ...................................19

6. POWER MODES ..................................................................................................................... 20

6.1 Normal Operation ................................... .... ... ... ... .... .........................................................20

6.2 Power Down, MCLK Enabled .......................................................................................... 20

6.3 Power Down, MCLK Disabled .................................... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ......20

7. VOLTAGE REFERENCE ........................................................................................................21

7.1 VREF Power Supply ........................... ... .... ... ... ... .... .........................................................21

7.2 VREF RC Filter ................................................................................................................21

7.3 VREF PCB Routing ..........................................................................................................21

7.4 VREF Input Impedance ....................................................................................................21

7.5 VREF Accuracy ................................... ... .... ... ... ................................................................22

8. POWER SUPPLIES ................................................................................................................23

8.1 Power Supply Bypassing .................... ... .... ... ... ... .... ... .......................................... ... ... ... ... 23

8.2 PCB Layers and Routing ........................................... ... ... .... ... ... ... ... .... ... ... ... ...................23

8.3 Power Supply Rejection ... ... ... .... .......................................... ... ... ...................................... 23

8.4 SCR Latch-up Considerations ......................................................................................... 24

8.5 DC-DC Converters . ... .... ... ... .............................................................................................24

9. PIN DESCRIPTION - CS5371A ............................................................................................. 25

10. PIN DESCRIPTION - CS5372A ........................................................................................... 27

11. PACKAGE DIMENSIONS ..................................................................................................... 29

12. ORDERING INFORMATION ................................................................................................ 30

13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ....... ................... 31

14. REVISION HISTORY ........................................................................................................... 32

CS5371A CS5372A

2 DS748F3

LIST OF FIGURES

Figure 1. Anti-alias Filter Components............................................................................................ 5

Figure 2. Modulator Noise Performance......................................................................................... 8

Figure 3. Modulator + CS4373A Test DAC Dynamic Performance ............................... ... ... ... ... .... . 8

Figure 4. Digital Input Rise and Fall Times .....................................................................................9

Figure 5. Digital Output Rise and Fall Times .................................................................................. 9

Figure 6. System Timing Diagram.................................................................................................11

Figure 7. MCLK / MSYNC Timing Detail....................................................................................... 11

Figure 9. Connection Diagram...................................................................................................... 13

Figure 8. System Block Diagram................................................................................................... 13

Figure 10. CS5371A and CS5372A Block Diagrams.................................................................... 14

Figure 11. Analog Signals............................................................................................................. 16

Figure 12. Digital Signals.............................................................................................................. 18

Figure 13. Power Mode Diagram.................................................................................................. 20

Figure 14. Voltage Reference Circuit............................................................................................21

Figure 15. Power Supply Diagram................................................................................................ 23

LIST OF TABLES

Table 1. 24-Bit Output Coding for the CS5371A and CS5372A Modulator and

CS5376A Digital Filter Combination ............................................................................. 15

CS5371A CS5372A

DS748F3 3

CS5371A CS5372A

1. CHARACTERISTICS AND SPECIFICATIONS

• Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.

• Typical performance characteristics and specifications are measured at nominal supply voltages and T

• GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half.

• Device is connected as shown in Figure 9 on page 13 unless otherwise noted.

SPECIFIED OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

Bipolar Power Supplies

Positive Analog ± 2% VA+ 2.45 2.50 2.55 V
Negative Analog (Note 1) ± 2% VA- -2.45 -2.50 -2.55 V
Positive Digital ± 3% VD 3.20 3.30 3.40 V

Voltage Reference

[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V

Thermal

Ambient Operating Temperature Industrial (-ISZ) T

A

-40 25 85 °C

= 25°C.

A

Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions.

2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance.

3. Channel-to-channel gain accuracy is directly proportional to the voltage reference absolute accuracy.

4. VREF inputs must satisfy: VA- ≤ VREF- < VREF+ ≤ VA+.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Parameter

DC Power Supplies Positive Analog

Negative Analog

Digital
Analog Supply Differential (VA+) - (VA-) VA
Digital Supply Differential (VD) - (VA-) VD
Input Current, Power Supplies (Note 5)I
Input Current, Any Pin Except Supplies (Note 5, 6)I
Output Current (Note 5)I

VA+

VA-

VD

DIFF
DIFF

PWR

IN

OUT

-0.5

-6.8

-0.5

-6.8V

-6.8V

-±50mA

-±10mA

-±25mA

6.8

0.5

6.8

Power Dissipation PDN - 500 mW
Analog Input Voltages V
Digital Input Voltages V
Storage Temperature Range T

INA
IND

STG

(VA-) - 0.5 (VA+) + 0.5 V

-0.5 (VD) + 0.5 V

-65 150 ºC

V
V
V

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 5. Transient currents up to ±100 mA will not cause SCR latch-up.

6. Includes continuous over-voltage conditions at the modulator analog input pins.

4 DS748F3

TEMPERATURE CONDITIONS

CS5371A / CS5372A

MODULATOR

INR+
INF+

INF­INR-

20nF
C0G

20nF
C0G

680

CS3301A / CS3302A

AMPLIFIER

OUTR+
OUTF+

OUTF­OUTR-

680

680

680

Figure 1. Anti-alias Filter Components

Parameter Symbol Min Typ Max Unit

Ambient Operating Temperature T
Storage Temperature Range T
Allowable Junction Temperature T
Junction to Ambient Thermal Impedance (4-layer PCB) θ

A

STR

JCT

JA

CS5371A CS5372A

-40 - 85 ºC

-65 - 150 ºC

--125ºC

-65-ºC/W

ANALOG INPUT CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

VREF Input

[VREF+] - [VREF-] (Note 2, 3) VREF - 2.500 - V
VREF- (Note 4)VREF- - VA- - V
VREF Input Current VREF
VREF Input Noise (Note 7)VREF

IMOD

IN

-120- µA

--1µV

rms

Modulator INR±, INF± Inputs

External Anti-alias Filter Series Resistance
(Note 8) Differential Capacitance

Differential Input Impedance INR±

INF±

Single-ended Input Impedance INR±

INF±

R

C

DIFF

ZDIF
ZDIF

ZSE
ZSE

AA

INR
INF

INR
INF

-

-

-

-

-

-

680

20
20

1

40

2

-

-

-

-

-

-

Ω

nF
kΩ

MΩ

kΩ

MΩ

Notes: 7. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached

to the VREF± inputs.

8. Anti-alias capacitors are discrete external components and must be of good qu ality (C0G, NPO, poly).
Poor quality capacitors will degrade total harmonic distortion (THD) performance. See Figure 1 on

page 5

DS748F3 5

CS5371A CS5372A

PERFORMANCE CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Signal Characteristics

Input Signal Frequencies (Note 9, 10) V
Full-scale Differential AC Input (Note 9)V
Full-scale Differential DC Input (Note 9)V
Input Common Mode Voltage (Note 11) V
Input Voltage Range (V

±Signal) (Note 9) V

cm

BW

AC
DC

CM

RNG

Dynamic Performance

Dynamic Range (1/4 ms) DC to 1720 Hz

SNR -

(Note 10, 12) (1/2 ms) DC to 860 Hz

(1 ms) DC to 430 Hz
(2 ms) DC to 215 Hz
(4 ms) DC to 108 Hz
(8 ms) DC to 54 Hz

(16 ms) DC to 27 Hz

Signal-dependent Noise (1 ms) DC to 430 Hz

SDN 100 110 - dB

(Note 13, 14)
Total Harmonic Distortion (Note 14) THD - -118 -112 dB

Linearity (Note 14)LIN ­Total Harmonic Distortion (Note 15)THD - -110 - dB
Linearity (Note 15)LIN ­Common Mode Rejection Ratio CMRR - 110 - dB
Channel Crosstalk (CS5372A only) CXT - -150 - dB

DC - 2000 Hz

--5V

pp

-2.5 - 2.5 V

- (VA-)+2.5 -V

(VA-)+0.7

-

121

-

-

-

-

- (VA+)-1.25 V

109
121
124
127
130
133
136

0.000126 0.000251

0.000316

-

-

-

-

-

-

-

-%

dB
dB
dB
dB
dB
dB
dB

%

Notes: 9. Guaranteed by design and/or characterization.

10. The upper bandwidth limit is determined by the digital filter cut-off frequency.

11. Common mode voltage is defined as the mid-point of the differential signal.

12. Dynamic Range defined as 20 log [ (RMS full scale) / (RMS idle noise) ] where idle noise is measured
from a CS3301A / CS3302A amplifier terminated input at 1x gain.

13. Signal-dependent Noise defined as 20 log [ (RMS full scale) / (RMS signal noise) ] where signal noise
is measured by subtracting out the signal power at the fundamental and harmonic frequencies.

14. Tested with a 31.25 Hz sine wave at -1 dB amplitude and Vcm = (VA-) + 2.50V.

15. Characterized with a 31.25 Hz sine wave at -1 dB amplitude and Vcm = (VA-) + 2.35V. This
corresponds to the output Vcm of the CS4373A test DAC.

6 DS748F3

CS5371A CS5372A

PERFORMANCE CHARACTERISTICS (CONT.)

Parameter Symbol Min Typ Max Unit

Gain Accuracy

Channel to Channel Gain Accuracy (Note 3) GA - ±1 ±2 %
Channel Gain Drift (Note 16)GA

Offset

Offset Voltage, Differential (OFST = 0) OFST - ±1 - mV
Offset Voltage, CS5371A (OFST = 1) OFST - -60 - mV
Offset Voltage, CS5372A channel 1 (OFST = 1) OFST - -60 - mV
Offset Voltage, CS5372A channel 2 (OFST = 1) OFST - -35 - mV
Offset after Calibration (Note 17)OFST
Offset Calibration Range (Note 18)OFST
Offset Voltage Drift (Note 16)OFST

Notes: 16. Specification is for the parameter over the sp ecified temperature range and is for the device only. It does

not include the effects of external comp o nents.

17. Specification applies to the effective off set voltag e calculated from the output codes of the digital filter

following offset calibration and correction.

18. Offset calibration is performed in the digital filter and includes the full-scale signal range.

TC

CAL

RNG

TC

- 22 - ppm/°C

-±1- μV

-100- %FS

-300- nV/°C

DS748F3 7

PERFORMANCE PLOTS

Figure 2. Modulator Noise Performance

Figure 3. Modulator + CS4373A Test DAC Dynamic Performance

CS5371A CS5372A

8 DS748F3

DIGITAL CHARACTERISTICS

0.9 * VD

0.1 * VD

t

fall

t

rise

Figure 4. Digital Input Rise and Fall Times

0.9 * VD

0.1 * VD

t

fall

t

rise

Figure 5. Digital Output Rise and Fall Times

Parameter Symbol Min Typ Max Unit

Digital Inputs

High-level Input Voltage (Note 9, 19)V
Low-level Input Voltage (Note 9, 19)V
Input Leakage Current I
Digital Input Capacitance (N ot e 9) C
Input Rise Times Except MCLK (Note 9) t
Input Fall Times Except MCLK (Note 9) t

Digital Outputs

High-level Output Voltage, I
Low-level Output Voltage, I

=-40μA(Note 9)VOHVD - 0.3 - - V

out

=40μA(Note 9)V

out

High-Z Leakage Current I
Digital Output Capacitance (Note 9) C
Output Rise Times (Note 9) t
Output Fall Times (Note 9) t

IH

IL

IN

IN
RISE
FALL

OL

OZ

OUT
RISE
FALL

CS5371A CS5372A

0.6*VD - VD V

0.0 - 0.8 V

-±1±10μA

-9- pF

--100ns

--100ns

--0.3V

--±10μA

-9- pF

--100ns

--100ns

Notes: 19. Device is intended to be driven with CMOS logic levels.

DS748F3 9

DIGITAL CHARACTERISTICS (CONT.)

Parameter Symbol Min Typ Max Unit

Master Clock Input

MCLK Frequency (Note 20)f
MCLK Period (Note 20)t
MCLK Duty Cycle (Note 9)MCLK
MCLK Rise Time (Note 9)t
MCLK Fall Time (Note 9)t
MCLK Jitter (in-band or aliased in-band) (Note 9)MCLK
MCLK Jitter (out-of-band) (Note 9)MCLK

Master Sync Input

MSYNC Setup Time to MCLK Falling (Note 9, 21)t
MSYNC Period (Note 9, 21)t
MSYNC Hold Time after MCLK Falling (Note 9, 21)t

MDATA Output

MDATA Output Bit Rate f
MDATA Output Bit Period t
MDATA Output One’s Density Range (Note 9)MDAT
Full-scale Output Code (Note 22)MDAT

CLK
mclk

RISE
FALL

OBJ

mss

msync

msh

mdata
mdata

OD

DC

IBJ

FS

CS5371A CS5372A

-2.048- MHz

-488- ns

40 - 60 %

--50ns

--50ns

--300ps

--1ns

20 122 - ns
40 976 - ns
20 122 - ns

- 512 - kbits/s

- 1953 - ns

14 - 86 %

0xA2EBE0

-

0x5D1420

Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power-

down state.

21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant
) is on the next MCLK rising edge.

(t

0

22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter.

10 DS748F3