Cirrus Logic CS5346 User Manual

CS5346

103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux

ADC Features

 Multi-bit Delta–Sigma Modulator  103 dB Dynamic Range  -95 dB THD+N  Stereo 6:1 Input Multiplexer  Programmable Gain Amplifier (PGA)

– ± 12 dB Gain, 0.5-dB Step Size – Zero-crossing, Click-free Transitions

 Stereo Microphone Inputs

– +32 dB Gain Stage – Low-noise Bias Supply

 Up to 192 kHz Sampling Rates

 Selectable 24-bit, Left-justified or I²S Serial

Audio Interface Formats

System Features

 Power-down Mode

 +5 V Analog Power Supply, Nominal

 +3.3 V Digital Power Supply, Nominal  Direct Interface with 3.3 V to 5 V Logic Levels

 Pin Compatible with CS5345 (*See Section 2

for details.)

General Description

The CS5346 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5346 performs stereo analog-to-digital (A/D) conve rsion of 24-bit serial values at sa mple rates up to 192 kHz.

A 6:1 stereo input multiplexe r is inc luded for selecting between line-level and microphone-level inputs. The microphone input path includes a +32 dB gain stage and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of ±12 dB in 0.5 dB steps.

The output of the PGA is followed by an advanced 5thorder, multi-bit delta-sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 8 kHz to 192 kHz in either Slave or Master Mode.

Integrated level translators allow easy interfacing between the CS5346 and other devices operating over a wide range of logic levels.

The CS5346 is available in a 48-pin LQFP package in Commercial (-40° to +85° C) grade. The CDB5346 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 38 for complete details.

3.3 V to 5 V

I²C/SPI

Control Data

Interrupt

Overflow

Reset

Serial Audio

Output

Level Translator

Level

Translator

PCM Serial Interface

High Pass

Filter

High Pass

Filter

Preliminary Product Information

http://www.cirrus.com

3.3 V 5 V

Internal Voltage

Reference

Low-Latency

Anti-Alias Filter

Low-Latency

Anti-Alias Filter

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

PGA

PGAA

MUX

+32 dB

This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice.

Left PGA Output

Right PGA Output

Stereo Input 1 Stereo Input 2 Stereo Input 3

Stereo Input 4 / Mic Input 1 & 2

Stereo Input 5 Stereo Input 6

AUG ‘12

DS861PP3

TABLE OF CONTENTS

1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5

2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS ................................................................................... 8

ABSOLUTE MAXIMUM RATINGS .......................................................................................................8

ANALOG CHARACTERISTICS ............................................................................................................ 9

ANALOG CHARACTERISTICS CONT. .............................................................................................. 10

DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11

DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12

DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 16

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17

4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18

5. APPLICATIONS ................................................................................................................................... 19

5.1 Recommended Power-Up Sequence ............................................................................................. 19

5.2 System Clocking ............................................................................................................................. 19

5.2.1 Master Clock ......................................................................................................................... 19

5.2.2 Master Mode ......................................................................................................................... 20

5.2.3 Slave Mode ........................................................................................................................... 20

5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20

5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................21

5.5 Input Connections ........................................................................................................................... 21

5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21

5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22

5.6 PGA Auxiliary Analog Output ......................................................................................................... 23

5.7 Control Port Description and Timing ............................................................................................... 23

5.7.1 SPI Mode ............................................................................................................................... 23

5.7.2 I²C Mode ................................................................................................................................ 24

5.8 Interrupts and Overflow .................................................................................................................. 25

5.9 Reset .............................................................................................................................................. 26

5.10 Synchronization of Multiple Devices ............................................................................................. 26

5.11 Grounding and Power Supply Decoupling .................................................................................... 26

6. REGISTER QUICK REFERENCE ........................................................................................................ 27

7. REGISTER DESCRIPTION .................................................................................................................. 28

7.1 Chip ID - Register 01h .................................................................................................................... 28

7.2 Power Control - Address 02h ......................................................................................................... 28

7.2.1 Freeze (Bit 7) ......................................................................................................................... 28

7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28

7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28

7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28

7.3 ADC Control - Address 04h ............................................................................................................ 29

7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29

7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29

7.3.3 Mute (Bit 2) ............................................................................................................................ 29

7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29

7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29

7.4 MCLK Frequency - Address 05h .................................................................................................... 30

7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30

7.5 PGAOut Control - Address 06h ...................................................................................................... 30

7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30

7.6 Channel B PGA Control - Address 07h .......................................................................................

CS5346

... 30

2 DS861PP3

7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 30

7.7 Channel A PGA Control - Address 08h .......................................................................................... 31

7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 31

7.8 ADC Input Control - Address 09h ................................................................................................... 31

7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 31

7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 32

7.9 Active Level Control - Address 0Ch ................................................................................................ 32

7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 32

7.10 Status - Address 0Dh ................................................................................................................... 32

7.10.1 Clock Error (Bit 3) ................................................................................................................ 33

7.10.2 Overflow (Bit 1) .................................................................................................................... 33

7.10.3 Underflow (Bit 0) .................................................................................................................. 33

7.11 Status Mask - Address 0Eh .......................................................................................................... 33

7.12 Status Mode MSB - Address 0Fh ................................................................................................. 33

7.13 Status Mode LSB - Address 10h .................................................................................................. 33

8. PARAMETER DEFINITIONS ................................................................................................................ 34

9. FILTER PLOTS .................................................................................................................................. 35

10. PACKAGE DIMENSIONS .................................................................................................................. 37

11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 37

12. ORDERING INFORMATION ......................................................................................................... 38

13. REVISION HISTORY .......................................................................................................................... 38

LIST OF FIGURES

CS5346

Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 15

Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 15

Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 15

Figure 4.Format 1, 24-Bit Data I²S ............................................................................................................ 15

Figure 5.Control Port Timing - I²C Format ................................................................................................. 16

Figure 6.Control Port Timing - SPI Format ................................................................................................ 17

Figure 7.Typical Connection Diagram ....................................................................................................... 18

Figure 8.Master Mode Clocking ................................................................................................................ 20

Figure 9.Analog Input Architecture ............................................................................................................ 21

Figure 10.CS5346 PGA ............................................................................................................................ 22

Figure 11.1 V Figure 12.1 V Figure 13.2 V

Figure 14.Control Port Timing in SPI Mode .............................................................................................. 24

Figure 15.Control Port Timing, I²C Write ................................................................................................... 24

Figure 16.Control Port Timing, I²C Read ................................................................................................... 25

Figure 17.Single-Speed Stopband Rejection ............................................................................................ 35

Figure 18.Single-Speed Stopband Rejection ............................................................................................ 35

Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 35

Figure 20.Single-Speed Passband Ripple ................................................................................................ 35

Figure 21.Double-Speed Stopband Rejection ........................................................................................... 35

Figure 22.Double-Speed Stopband Rejection ........................................................................................... 35

Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 36

Figure 24.Double-Speed Passband Ripple ............................................................................................... 36

Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 36

Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 36

Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 36

Figure 28.Quad-Speed Passband Ripple ................................................................................................. 36

Input Circuit .................................................................................................................. 22

RMS

Input Circuit with RF Filtering ....................................................................................... 22

RMS

Input Circuit .................................................................................................................. 22

RMS

DS861PP3 3

LIST OF TABLES

Table 1. Speed Modes .............................................................................................................................. 19

Table 2. Common Clock Frequencies ....................................................................................................... 19

Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 20

Table 4. Device Revision .......................................................................................................................... 28

Table 5. Freeze-able Bits .......................................................................................................................... 28

Table 6. Functional Mode Selection .......................................................................................................... 29

Table 7. Digital Interface Formats ............................................................................................................. 29

Table 8. MCLK Frequency ........................................................................................................................ 30

Table 9. PGAOut Source Selection ........................................................................................................... 30

Table 10. Example Gain and Attenuation Settings ................................................................................... 31

Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 32

Table 12. Analog Input Multiplexer Selection ............................................................................................ 32

CS5346

4 DS861PP3

1. PIN DESCRIPTIONS - CS5346

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

VLSSDA/CDOUT

AGND

OVFL

SCL/CCLK

AD0/CS

AD1/CDIN

VLC

RST

AIN3A

AIN3B

AIN2A

AIN2B

AIN1A

AIN1B

AFILTB

FILT+

AIN4A/MICIN1

AIN4B/MICIN2

AIN5A

AIN5B

AFILTA

AGND

PGAOUTB

PGAOUTA

AIN6B

AIN6A

MICBIAS

INTVDDGND

MCLK

LRCK

SCLK

SDOUTNCNCNCNC

CS5346

Pin Name # Pin Description

SDA/CDOUT 1

SCL/CCLK 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.

AD0/CS

AD1/CDIN 4

VLC 5

RST

AIN3A AIN3B

AIN2A AIN2B

DS861PP3 5

Serial Control Data (Input/Output) - SDA is a data I/O in I²C

the control port interface in SPI

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;

Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;

CDIN is the input data line for the control port interface in SPI Mode.

Control Port Power (Input) - Determines the required signal level for the control port interface. Refer

to the Recommended Operating Conditions for appropriate voltages.

6 Reset (Input) - The device enters a low-power mode when this pin is driven low.

Stereo Analog Input 3 (Input) - The full-scale level is specified in the Analog Characteristics specifica-

tion table.

Stereo Analog Input 2 (Input) - The full-scale level is specified in the Analog Characteristics specifica-

tion table.

Mode.

is the chip-select signal for SPI format.

Mode. CDOUT is the output data line for

CS5346

AIN1A AIN1B

AGND 13 Analog Ground (Input) - Ground reference for the internal analog section. VA 14 Analog Power (Input) - Positive power for the internal analog section. AFILTA 15 Anti-alias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. AFILTB 16 Anti-alias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.

FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

NC 20

AIN4A/MICIN1 AIN4B/MICIN22122

AIN5A AIN5B

MICBIAS 25

AIN6A AIN6B

PGAOUTA PGAOUTB

AGND 32 Analog Ground (Input) - Ground reference for the internal analog section.

VLS 36

SDOUT 41 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. SCLK 42 Serial Clock (Input/Output) - Serial clock for the serial audio interface.

LRCK 43

MCLK 44 Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators. DGND 45 Digital Ground (Input) - VD 46 Digital Power (Input) - Positive power for the internal digital section. INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred. OVFL 48 Overflow (Output) - Indicates an ADC overflow condition is present.

Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specifica-

tion table.

Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

No Connect - This pin is not connected internally and should be tied to ground to minimize any poten- tial coupling effects.

Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the Ana-

log Characteristics specification table.

Stereo Analog Input 5 (Input) - The full-scale level is specified in the Analog Characteristics specifica-

tion table.

Microphone Bias Supply (Output) - Low

teristics are specified in the DC Electrical Characteristics specification table.

Stereo Analog Input 6 (Input) - The full-scale level is specified in the Analog Characteristics specifica-

tion table.

PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance.

See “PGAOut Source Select (Bit 6)” on page 30.

3031No Connect - These pins are not connected internally and should be tied to ground to minimize any

potential coupling effects.

No Connect - These pins are not connected internally and should be tied to ground to minimize any

potential coupling effects.

Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages.

37 38

No Connect - These pins are not connected internally and should be tied to ground to minimize any

potential coupling effects.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

Ground reference for the internal digital section.

-noise bias supply for external microphone. Electrical charac-

6 DS861PP3

CS5346

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

VLSSDA/CDOUT

AGND

OVFL

SCL/CCLK

AD0/CS

AD1/CDIN

VLC

RST

AIN3A

AIN3B

AIN2A

AIN2B

AIN1A

AIN1B

AFILTB

TSTO

FILT+

TSTI

AIN4A/MICIN1

AIN4B/MICIN2

AIN5A

AIN5B

AFILTA

TSTO

AGND

PGAOUTB

PGAOUTA

AIN6B

AIN6A

MICBIAS

INTVDDGND

MCLK

LRCK

SCLK

SDOUT

NCNCNC

TSTI

CS5345

Compatibility

2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES

The CS5346 is p in compatible with the CS5345 and is a drop in replacement for CS5345 applications where VA = 5 V, VD = 3.3 V, VLS for the remaining pins when replacing the CS5345 in these designs with a CS5346.

 3.3 V, and VLC  3.3 V. The pinout diagram and table below show the requirements

Pin Name

CS5345

CS5346

Pin Name

5VLC VLCControl Port Power (Input) -Limited to nominal 5 or 3.3 V.

14 VA VA Analog Power (Input) - Limited to nominal 5 V.

18 TSTO VQ This pin must be left unconnected.

20 TSTI NC This pin should be tied to ground.

30 VA NC

31 AGND NC This pin should be connected to ground.

35 TSTO NC This pin may be left unconnected.

36 VLS VLS Serial Audio Interface Power (Input) - Limited to nominal 5 or 3.3 V.

37 TSTI NC This pin should be tied to ground.

46 VD VD Digital Power (Input) - Limited to nominal 3.3 V

DS861PP3 7

CS5346

Connection for Compatibility

This pin may be connected to the analog supply voltage. The decoupling capacitor for the CS5345 is not required.

3. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND = DGND = 0 V; All voltages with respect to ground.

Parameters Symbol Min Nom Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied) Commercial T

VD VLS VLC

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V All voltages with respect to ground. (Note 1)

Parameter Symbol Min Max Units

DC Power Supplies: Analog

Digital

Logic - Serial Port

Logic - Control Port

Input Current (Note 2)

Analog Input Voltage

Digital Input Voltage Logic - Serial Port

Logic - Control Port

Ambient Operating Temperature (Power Applied)

Storage Temperature

VLS

VLC

V V

VA VD

INA

IND-S

IND-C

stg

CS5346

4.75

3.13

-40 - +85 C

AGND-0.3 VA+0.3 V

5.0

3.3

-0.3

- 10 mA

-0.3

-50 +125 C

-65 +150 C

5.25

3.47

5.25

+6.0

+3.63

+6.0 +6.0

VLS+0.3 VLC+0.3

V V V V

V V

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.

8 DS861PP3

CS5346

ANALOG CHARACTERISTICS

Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V;

= +25° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz;

PGA gain = 0 dB; All connections as shown in Figure 7 on page 18.

Parameter Symbol Min Typ Max Unit

Analog-to-Digital Converter Characteristics

Dynamic Range (Line Level Inputs)

A-weighted

unweighted

(Note 3) 40 kHz bandwidth unweighted

Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4)

-1 dB

-20 dB

-60 dB

(Note 3) 40 kHz bandwidth -1 dB

Dynamic Range (Mic Level Inputs)

A-weighted

(Note 3) unweighted

Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4)

-20 dB

(Note 3) -60 dB

Interchannel Isolation (Line Level Inputs)

(Mic Level Inputs)

A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA V Gain Error --10 % Interchannel Gain Mismatch - 0.1 - dB

-1 dB

THD+N

Microphone - Level Input Characteristics

Preamplifier Gain 31

Interchannel Gain Mismatch - 0.1 - dB Input Impedance (Note 5) -60-k

97 94

77 74

35.5

103 100

-95

-80

-40

-92

83 80

-80

-60

-20 90 80

32 40

-89

-74

44.7

V/V

dB dB dB

dB dB dB dB

dB dB

dB dB dB

dB dB

3. Valid for Double- and Quad-Speed Modes only.

4. Referred to the typical A/D full-scale input voltage

5. Valid when the microphone-level inputs are selected.

DS861PP3 9

CS5346

ANALOG CHARACTERISTICS CONT.

Parameter Symbol Min Typ Max Unit

Line-Level Input and Programmable Gain Amplifier

Gain Range - 12

-4 Gain Step Size -0.5-dB Absolute Gain Step Error - - 0.4 dB Maximum Input Level - - 0.85*VA V Input Impedance

Selected inputs

Un-selected inputs

Selected Interchannel Input Impedance Mismatch - 5 - %

28.8

Analog Outputs

Dynamic Range (Line Level Inputs)

A-weighted

unweighted

Total Harmonic Distortion + Noise (Line Level Inputs) (Note 6)

-1 dB

THD+N

OUT

-20 dB

-60 dB

Dynamic Range (Mic Level Inputs)

A-weighted

unweighted

Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 6)

-20 dB

-60 dB Frequency Response 10 Hz to 20 kHz -0.1dB - +0.1dB dB Analog In to Analog Out Phase Shift - 180 - deg DC Current draw from a PGAOUT pin I AC-Load Resistance R Load Capacitance C

98 95

77 74

--1A

100 - - k

--20pF

104 101

-80

-81

-41

83 80

-74

-60

-20

+ 12

43.2 38

-74

-68

V/V

k k

dB dB

dB dB dB

dB dB

dB dB dB

6. Referred to the typical A/D Full-Scale Input Voltage.

10 DS861PP3

CS5346

DIGITAL FILTER CHARACTERISTICS

Parameter (Note 7) Symbol Min Typ Max Unit

Single-Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs

Passband Ripple - - 0.035 dB

Stopband 0.5688 - - Fs

Stopband Attenuation 70 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Double-Speed Mode

Passband (-0.1 dB) 0 - 0.4896 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5604 - - Fs

Stopband Attenuation 69 - - dB

Total Group Delay (Fs = Output Sample Rate) t

Quad-Speed Mode

Passband (-0.1 dB) 0 - 0.2604 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5000 - - Fs

Stopband Attenuation 60 - - dB

Total Group Delay (Fs = Output Sample Rate) t

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 8)

Phase Deviation @ 20 Hz (Note 8) -10 -Deg

Passband Ripple -- 0dB

Filter Settling Time

-12/Fs - s

-9/Fs - s

-5/Fs - s

-120-

/Fs s

Hz Hz

7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 17 to 28) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

8. Response shown is for Fs = 48 kHz.

DS861PP3 11

CS5346

DC ELECTRICAL CHARACTERISTICS

AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V (Normal Operation) VD, VLS, VLC = 3.3 V

Power Supply Current VA = 5 V (Power-Down Mode) (Note 9) VLS, VLC, VD = 3.3 V

Power Consumption (Normal Operation) VA = 5 V

VD, VLS, VLC = 3.3 V

(Power-Down Mode) VA = 5V; VD, VLS, VLC = 3.3 V

Power Supply Rejection Ratio (1 kHz) (Note 10) PSRR - 55 - dB

VQ Characteristics

Quiescent Voltage VQ - 0.5 x VA - VDC

Maximum DC Current from VQ I

VQ Output Impedance Z

FILT+ Nominal Voltage FILT+ - VA - VDC

Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC

Current from MICBIAS I

I I

-1 -A

-23 -k

-- 2mA

41 23

0.50

0.54

205

4.2

50 28

250

mA mA

mW mW mW

9. Power-Down Mode is defines as RST = Low with all clock and data lines held static and no analog input.

10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.

12 DS861PP3

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