Cirrus Logic CS5345 User Manual
1.8 V to 5 V
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Output
3.3 V to 5 V 3.3 V to 5 V
MUX
PGA
PCM Serial Interface
Register Configuration
Level
Translator
Left PGA Output
Right PGA Output
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
Level Translator
Reset
I²C/SPI
Control Data
Interrupt
Overflow
CS5345
104 dB, 24-Bit, 192 kHz Stereo Audio ADC
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
System Features
Power-Down Mode
+3.3 V to +5 V Analog Power Supply, Nominal
+3.3 V to +5 V Digital Power Supply, Nominal
Direct Interface with 1.8 V to 5 V Logic Levels
Pin-Compatible with CS4245
General Description
The CS5345 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital
converter. The CS5345 performs stereo analog-to-digital (A/D) conversion of up to 24-bit serial values at
sample rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides
gain/attenuation of ± 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing between the CS5345 and other devices operating over a
wide range of logic levels.
The CS5345 is available in a 48-pin LQFP package in
Commercial (-10° to +70° C) grade. The CDB5345 Customer Demonstration board is also available for device
evaluation and implementation suggestions. Please refer to “Ordering Information” on page 42 for complete
details.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG '12
DS658F4
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ......................................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
SPECIFIED OPERATING CONDITIONS ............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS .......................................................................................................7
ADC ANALOG CHARACTERISTICS ................................................................................................... 8
ADC ANALOG CHARACTERISTICS ................................................................................................. 10
ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... ... ... ... ... 11
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15
DIGITAL INTERFACE CHARACTERISTICS ................... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 20
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT .. ... ... ... .... ... ... ... ... .... ... ... ...... 21
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22
4. APPLICATIONS ................................................................................................................................... 23
4.1 Recommended Power-Up Sequence ............................................................................................. 23
4.2 System Clocking ............................................................................................................................. 23
4.2.1 Master Clock ............................ ... ... .... ... ... ... .... ... .......................................... ... ...................... 23
4.2.2 Master Mode .................................. .... .......................................... ... ... ... ................................ 24
4.2.3 Slave Mode ........................... ... ... ... .... ................................................................................... 24
4.3 High-Pass Filter and DC Offset Calibration .............................................................. ......................24
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................26
4.5 Input Connections ........................................................................................................................... 26
4.6 PGA Auxiliary Analog Output ......................................................................................................... 26
4.7 Control Port Description and Timing ............................................................................................... 27
4.7.1 SPI Mode .................................. ... ... .......................................... ............................................. 27
4.7.2 I²C Mode ................................ .......................................... ...................................................... 27
4.8 Interrupts and Overflow .................................................................................................................. 29
4.9 Reset .............................................................................................................................................. 29
4.10 Synchronization of Multiple Devices ............................................................................................. 29
4.11 Grounding and Power Supply Decoupling .................................................................................... 29
5. REGISTER QUICK REFERENCE ........................................................................................................ 31
6. REGISTER DESCRIPTION .................................................................................................................. 32
6.1 Chip ID - Register 01h .................................................................................................................... 32
6.2 Power Control - Address 02h ......................................................................................................... 32
6.2.1 Freeze (Bit 7) .................................. .... ... .......................................... ...................................... 32
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 32
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 32
6.2.4 Power-Down Device (Bit 0) ...................................................... .... ... ... ... .... ... ......................... 32
6.3 ADC Control - Address 04h ............................................................................................................ 33
6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 33
6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 33
6.3.3 Mute (Bit 2) ............................................................................................................................ 33
6.3.4 High-Pass Filter Freeze (Bit 1) ....... .......................................... ............................................. 33
6.3.5 Master / Slave Mode (Bit 0) ................................... .......................................... ... ................... 33
6.4 MCLK Frequency - Address 05h .................................................................................................... 34
6.4.1 Master Clock Dividers (Bits 6:4) ..... .... .......................................... ... ... ... .... ... ... ... ................... 34
6.5 PGAOut Control - Address 06h ...................................................................................................... 34
6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 34
6.6 Channel B PGA Control - Address 07h .......................................................................................... 34
CS5345
2 DS658F4
6.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 34
6.7 Channel A PGA Control - Address 08h .......................................................................................... 35
6.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 35
6.8 ADC Input Control - Address 09h ................................................................................................... 35
6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 35
6.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 36
6.9 Active Level Control - Address 0Ch ................................................................................................ 36
6.9.1 Active High/Low (Bit 0) .......................................................................................................... 36
6.10 Interrupt Status - Address 0Dh ..................................................................................................... 36
6.10.1 Clock Error (Bit 3) ... ... ... .... ... ... ... ... .... ... ... .......................................... ... .... ... ... ... ... ................ 37
6.10.2 Overflow (Bit 1) .................................................................................................................... 37
6.10.3 Underflow (Bit 0) .................................................................................................................. 37
6.11 Interrupt Mask - Address 0Eh .... ... ... ............................................................................................. 37
6.12 Interrupt Mode MSB - Address 0Fh .............................................................................................. 37
6.13 Interrupt Mode LSB - Address 10h ............................................................................................... 37
7. PARAMETER DEFINITIONS ................................................................................................................ 38
8. FILTER PLOTS .................................................................................................................................. 39
9. PACKAGE DIMENSIONS .................................................................................................................... 41
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 41
11. ORDERING INFORMATION ........................................................................................................ 42
12. REVISION HISTORY ....................................... ... ... ... .... ... ... ... .... ......................................................... 42
LIST OF FIGURES
CS5345
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 18
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 18
Figure 3.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 19
Figure 4.Format 1, I²S up to 24-Bit Data ................................................................................................... 19
Figure 5.Control Port Timing - I²C Format ................................................................................................. 20
Figure 6.Control Port Timing - SPI Format ................................................................................................ 21
Figure 7.Typical Connection Diagram ....................................................................................................... 22
Figure 8.Master Mode Clocking ................................................................................................................ 24
Figure 9.Analog Input Architecture ............................................................................................................ 26
Figure 10.Control Port Timing in SPI Mode ................................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 27
Figure 11.Control Port Timing, I²C Write ................................................................................................... 28
Figure 12.Control Port Timing, I²C Read ................................................................................................... 28
Figure 13.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 14.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 15.Single-Speed Transition Band (Detail) ...................................................................................... 39
Figure 16.Single-Speed Passband Ripple ................................................................................................ 39
Figure 17.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 18.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 19.Double-Speed Transition Band (Detail) .................................................................................... 40
Figure 20.Double-Speed Passband Ripple ............................................................................................... 40
Figure 21.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 23.Quad-Speed Transition Band (Detail) .................................... ................................................... 40
Figure 24.Quad-Speed Passband Ripple .............................. ... .......................................... ... ... .... ... ......... 40
LIST OF TABLES
Table 1. Speed Modes .............................................. ... ... .... .......................................... ... ... ...................... 23
Table 2. Common Clock Frequencies ....................................................................................................... 23
Table 3. MCLK Dividers ............................................................................................................................ 24
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 24
DS658F4 3
CS5345
Table 5. Device Revision .......................................................................................................................... 32
Table 6. Freeze-able Bits .......................................................................................................................... 32
Table 7. Functional Mode Selection ............................. .......................................... ................................... 33
Table 8. Digital Interface Formats ............................................................................................................. 33
Table 9. MCLK Frequency ........................................................................................................................ 34
Table 10. PGAOut Source Selection ......................................................................................................... 34
Table 11. Example Gain and Attenuation Settings ................................................................................... 35
Table 12. PGA Soft Cross or Zero Cross Mode Selection ............... ......................................................... 36
Table 13. Analog Input Multiplexer Selection ............................................................................................ 36
4 DS658F4
1. PIN DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLSSDA/CDOUT
AGND
OVFL
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
VA
AFILTB
VQ
TSTO
FILT+
TSTO
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
AFILTA
TSTO
NC
NC
AGND
AGND
VA
PGAOUTB
PGAOUTA
AIN6B
AIN6A
MICBIAS
INTVDDGND
MCLK
LRCK
SCLK
SDOUTNCNCNCTSTI
CS5345
CS5345
Pin Name # Pin Description
SDA/CDOUT 1
SCL/CCLK 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
AD1/CDIN 4
VLC 5
RESET
AIN3A
AIN3B
AIN2A
AIN2B
DS658F4 5
Serial Control Data (Input/Output) - SDA is a data I/O in I²C
the control port interface in SPI
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
3
CS
Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
6 Reset (Input) - The device enters a low-power mode when this pin is driven low.
78Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
910Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
TM
Mode.
is the chip-select signal for SPI format.
®
Mode. CDOUT is the output data line for
CS5345
AIN1A
AIN1B
AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.
VA 14 Analog Power (Input) - Positive power for the internal analog section.
AFILTA 15 Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB 16 Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ 17 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
TSTO 18 Test Pin (Output) - This pin must be left unconnected.
FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
TSTO 20 Test Pin - This pin must be left unconnected.
AIN4A/MICIN1
AIN4B/MICIN22122
AIN5A
AIN5B
MICBIAS 25
AIN6A
AIN6B
PGAOUTA
PGAOUTB
VA 30 Analog Power (Input) - Positive power for the internal analog section.
AGND
NC
TSTO 35 Test Pin (Output) - This pin must be left unconnected.
VLS 36
TSTI 37 Test Pin (Input) - This pin must be connected to ground.
NC
SDOUT 41 Serial Audio Data Output (Output) - Output for two’ s complement serial audio data.
SCLK 42 Serial Clock (Input/Output)
LRCK 43
MCLK 44 Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators.
DGND 45 Digital Ground (Input) - Ground reference for the internal digital section.
VD 46 Digital Power (Input) - Positive power for the internal digital section.
INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL 48 Overflow (Output) - Indicates an ADC overflow condition is present.
1112Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
Stereo Analog Input 4 / Micropho ne Input 1 & 2 (Input) - The full-scale level is specified in the ADC
Analog Characteristics specification table.
2324Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
Microphone Bias Supply
teristics are specified in the DC Electrical Characteristics specification table.
2627Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
2829PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance.
See “PGAOut Source Select (Bit 6)” on page 34.
31
Analog Ground (Input) - Ground reference for the internal analog section.
32
3334No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
38,
No Connect - These pins are not connected internally and should be tied to ground to minimize any
39,
potential coupling effects.
40
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
(Output) - Low-noise bias supply for external microphone. Electrical charac-
- Serial clock for the serial audio interface.
6 DS658F4
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied) T
VA
VD
VLS
VLC
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
Input Current (Note 3)
Analog Input Voltage
Digital Input Voltage Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Storage Temperature
VLS
VLC
V
V
V
A
VA
VD
I
in
INA
IND-S
IND-C
T
A
T
stg
CS5345
3.13
3.13
1.71
1.71
-10 - +70 C
AGND-0.3 VA+0.3 V
5.0
3.3
3.3
3.3
-0.3
-0.3
-0.3
-0.3
- 10 mA
-0.3
-0.3
-50 +125 C
-65 +150 C
5.25
(Note 1)
5.25
5.25
+6.0
+6.0
+6.0
+6.0
VLS+0.3
VLC+0.3
V
V
V
V
V
V
V
V
V
V
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS658F4 7
CS5345
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz.; All connections as
shown in Figure 7 on page 22.
Line-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
THD+N
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise (Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
THD+N
Line-Level Inputs
Parameter Symbol
Interchannel Isolation - 90 - dB
= -10° to +70° C for Commercial; Input test
A
98
95
-
92
89
-
-
-
-
-
-
-
-
-
93
90
-
89
86
-
-
-
-
-
-
-
-
-
104
101
98
98
95
92
-95
-81
-41
-92
-92
-75
-35
-89
101
98
95
95
92
89
-92
-78
-38
-84
-89
-72
-32
-81
-89
-86
-86
-83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Commercial Grade
UnitMin Typ Max
8 DS658F4
CS5345
DC Accuracy
Gain Error --10 %
Gain Drift -
Line-Level Input Characteristics
Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA V
Input Impedance (Note 4) 6.12 6.8 7.48 k
Maximum Interchannel Input Impedance
Mismatch
-5-%
Line-Level and Microphone-Level Inputs
Commercial Grade
Parameter Symbol
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Programmable Gain Characteristics
Gain Step Size - 0.5 - dB
Absolute Gain Step Error - - 0.4 dB
4. Valid for the selected input pair.
100 - ppm/°C
UnitMin Typ Max
pp
DS658F4 9
ADC ANALOG CHARACTERISTICS
(Continued)
Microphone-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
THD+N
77
74
65
62
77
74
CS5345
83
80
71
68
-
-
-
-
-80
-60
-20
-68
83
80
-
-
-
-
-74
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation - 80 - dB
THD+N
65
62
71
68
-
-
-
-
-80
-60
-20
-68
-
-
-74
-
-
-
dB
dB
dB
dB
dB
dB
DC Accuracy
Gain Error - 5 -%
Gain Drift -
300 - ppm/°C
Microphone-Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.017*VA 0.021*VA V
Input Impedance (Note 7) -60-k
pp
5. Referred to the typical line-level full-scale input voltage
6. Valid for Double- and Quad-Speed Modes only.
7. Valid when the microphone-level inputs are selected.
10 DS658F4
CS5345
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 8, 10) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) t
gd
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 9)
Phase Deviation @ 20 Hz (Note 9) -10 -Deg
Passband Ripple --0dB
Filter Settling Time
-12/Fs - s
-9/Fs - s
-5/Fs - s
-120-
5
10
/Fs s
-
Hz
Hz
8. Filter response is guaranteed by design.
9. Response shown is for Fs = 48 kHz.
10. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 13 to 24) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
DS658F4 11
CS5345
PGAOUT ANALOG CHARACTERISTICS
Test conditions (unless othe rwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or
VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T
wave; Measurement bandwidth: 10 Hz to 20 kHz; Fs = 48/96/192 kHz; Synchronous mode; All connections as
shown in Figure 7 on page 22.
VA = 4.75 V to 5.25 V
Parameter Symbol Min Typ Max Unit
Dynamic Performance with PGA Line-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
Dynamic Performance with PGA Mic-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
= -10° to +70° C; Input test signal: 1 kHz sine
A
THD+N
98
95
92
89
-
-
-
-
-
-
77
74
104
101
98
95
-80
-81
-41
-80
-75
-35
83
80
-
-
-
-
-74
-
-
-74
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
65
62
71
68
-
-
-
-
-74
-60
-20
-68
-68
-
-
-
-
-
dB
dB
dB
dB
dB
dB
11. Referred to the typical Line-Level Full-Scale Input Voltage.
12 DS658F4
PGAOUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Parameter Symbol Min Typ Max Unit
Dynamic Performance with PGA Line-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
Dynamic Performance with PGA Mic Level-Input Selected
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
THD+N
93
90
89
86
77
74
CS5345
101
98
95
92
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
83
80
-74
-74
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise (Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
65
62
71
68
-
-
-
-
-74
-60
-20
-68
-68
-
-
-
-
-
dB
dB
dB
dB
dB
dB
DS658F4 13
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