Cirrus Logic CS49DV8C User Manual
FEATURES
• 32-bit Post-Processor Audio DSP supports Multichannel
®
Dolby
Volume
•
Programmable through DSP Composer
• CS49DV8, supports up to 7.1 Channels of Dolby Volume
processing at 48 kHz, 44.1 kHz or 32 kHz.
— I n put C onf igu rab le for all input/output d igi t al au dio ty pes
2
(I
S, LJ/RJ, and TDM)
— 32-bit data path deli ve rs uncompromised dynamic rang e
— 192 kHz capable integrated S/PDIF transmitter
— DAO can operate in master or slave mode (SCLK &
LRCLK)
• Integrated Clock Manager/PLL
— Capable of operating from a wide variety of external
crystals or external oscillators
• Input Fs Auto Detection, Reporting and Handling
• Sample rate conversion.
• Master & Slave Host Boot Capability via Serial Interface
• SPI interface capable of running up to 25 MHz during run
time
• 1.8V Core and a 3.3V I/O that is tolerant to 5V input
™
CS49DV8C Data Sheet
32-bit Dual Audio DSP Engine
featuring Multichannel Dolby
The new CS49DV8C is the fastest time-to-market, massproduction ready Multichannel Dolby Volume solution available.
The target applications for the CS49DV8C DSP are:
— Soundbars
— DTVs with Integrated Soundbars
— HDTV Stands/Furniture with Integrated Soundbars
— Automotive Head Units
— Automot ive Outboard Amplifiers
— Blu-ray Disc
All of these applications and many more that use volume control
and are subject to playback from sources that do not have consistent volume levels will benefit from the CS49DV8C Dolby Volume
solution.
®
& DVD Receivers / HTiBs
®
Volume
8 Ch. Audio In
S/PDIF
S/PDIF
8 Ch PCM
Audio Out
Serial
Control 1
Ordering Information
See page 27 for ordering information.
Serial
Control 2
32-bit
DSP A
P
X Y P X Y
Ext. Memory Controller
D
M
A
32-bit
DSP B
GPIOUART Debug
STC
TMR1
TMR2
PLL
Preliminary Product Information
Copyright 2008 Cirrus Logic (All Rights Reserved) SEPT ‘08
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to
IMPORTANT NOTICE
“Preliminary” product inf orm ati on describes products that are in production, but for which ful l chara ct eri zati on data is not yet available. Cirrus Logic, Inc. and its sub-
sidiaries (“Cirrus”) bel i eve th at the in f ormat i on co nt ai ne d i n thi s document is accurate and reliable. However, the information is subject to change without noti ce and
is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, includin g those p ertainin g to warra nty, inde mnific ation, and limitat ion of liab ility. No responsib ility is ass umed b y Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property
of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other prod uct s of Cirr us. Thi s consen t does not extend to other copying such as
copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICO NDUCTOR PRODUCTS M AY INVOLVE P OTENTIAL RISKS OF DEATH, P ERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN
PRODUCTS SURGICALLY IMPLANT ED INTO THE BODY, AUTOMOTIVE SA FETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCT S OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS
DISCLAIMS AND MAKES NO WARRANTY, EXPRES S, STATUT ORY OR IM PLIED, INCLUDING THE IMPLIED WA RRANTIES O F MER CHANTABILIT Y AND FITNESS FOR PARTICULAR PURPOSE, W ITH REGARD TO ANY CIRR US PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOM ER OR CUSTOMER'S
CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLO YEES, DISTRIBUTO RS AND OTHER AG ENTS FROM ANY AND ALL LIAB ILITY, INCLUDING ATTO RNEYS'
FEES AND COSTS, THAT MAY RESULT FRO M OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
Dolby is a registered trademarks of Dolby Laboratories, Inc. Dolby Volume is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology
does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in
any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
Motorola and SPI are trademarks of Motorola, Inc.
2
I
C is a registered trademark of Philips Semiconductor.
Logic7 is a registered trademark of Harmon International Industries, Inc.
iPod is a registered trademark of Apple Computer, Inc.
Blu-ray
and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION .
www.cirrus.com
.
2 Copyright 2008 Cirrus Logic, Inc. DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
Table of Contents
1. Documentation Strategy ...................... ..... .... ..... ................................. .... ..... ..... ..............................5
2. Overview ............................ ..... ................................. .... ..... ................................. .... ..... ..... ................5
2.1 Licensing .........................................................................................................................................................7
3. Firmware Supported .......................................... ................................. .... ..... ................................. ..7
4. Hardware Functional Description ................................................ ..... .... ..... .............................. ... ..7
4.1 DSP Core ........................................................................................................................................................7
4.1.1 DSP Memory ......................................................................................................................................7
4.1.2 DMA Controller ...................................................................................................................................7
4.2 On-chip DSP Peripherals ................................................................................................................................8
4.2.1 Digital Audio Input Port (DAI) ..............................................................................................................8
4.2.2 Digital Audio Output Port (DAO) .........................................................................................................8
4.2.3 Serial Control Port 1 & 2 (I
4.2.4 External Memory Interface .................................................................................................................8
4.2.5 GPIO ...................................................................................................................................................8
4.2.6 PLL-based Clock Generator ...............................................................................................................8
4.3 DSP I/O Description ........................................................................................................................................9
4.3.1 Multiplexed Pins .................................................................................................................................9
4.3.2 Termination Requirements ..................................................................................................................9
4.3.3 Pads ...................................................................................................................................................9
4.4 Application Code Security ...............................................................................................................................9
2C®
or SPI™) ............................................................................................ 8
5. Characteristics and Specifications ................................ ..... ................................ ..... ...................10
5.1 Absolute Maximum Ratings ...........................................................................................................................10
5.2 Recommended Operating Conditions ...........................................................................................................10
5.3 Digital DC Characteristics .............................................................................................................................10
5.4 Power Supply Characteristics .......................................................................................................................11
5.5 Thermal Data (128-Pin LQFP) ...................................................................................................................... 11
5.6 Switching Characteristics— RESET ..............................................................................................................12
5.7 Switching Characteristics — XTI ...................................................................................................................13
5.8 Switching Characteristics — Internal Clock ...................................................................................................13
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode ..............................................................14
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode ..........................................................15
5.11 Switching Characteristics — Serial Control Port - I
5.12 Switching Characteristics — Serial Control Port - I
5.13 Switching Characteristics — UART .............................................................................................................18
5.14 Switching Characteristics — Digital Audio Slave Input Port ........................................................................19
5.15 Switching Characteristics — Digital Audio Output Port ...............................................................................20
5.16 Switching Characteristics — SDRAM Interface ...........................................................................................22
2
C Slave Mode .............................................................16
2
C Master Mode ...........................................................17
6. Ordering Information ......................................... ................................. .... ..... .................................27
7. Environmental, Manufac turi ng, and Ha ndling Informa tion ........................................ ..... .... .....27
8. Device Pin-Out Diagram ................. ................................. ..... .... ................................. ..... ..... .........28
8.1 128-Pin LQFP Pin-Out Diagram.................................................................................................................... 28
9. Package Mechanica l Drawings .............................. .... ................................. ..... ............................29
9.1 128-Pin LQFP Package .................................................................................................................................29
10. Revision History ................... ..... ......... ......... .......... ......... ..... ......... ......... .......... ......... ..... ..... .... .....30
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 3
CS49DV8C Data Sheet
32-bit Audio DSP Family
List of Figures
Figure 1. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Serial Control Port - I
Figure 6. Serial Control Port - I
Figure 7. UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Digital Audio Port Timing Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. External Memory Interface - SDRAM Burst Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. External Memory Interface - SDRAM Burst Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. External Memory Interface - SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. External Memory Interface - SDRAM Load Mode Register Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. 128-Pin LQFP Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. 128-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of Tables
Table 1. CS49DV8C Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS49DV8C DSP Memory Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. 128-Pin LQFP Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Copyright 2008 Cirrus Logic, Inc. DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
1. Documentation Strategy
The CS49DV8C data sheet describes the CS49DV8C family of multichannel audio DSPs. This
document should be used in conjunction with the following documents when evaluating or designing a
system around the CS49DV8C family of processors.
Table 1. CS49DV8C Related Documentation
Document Name Description
CS49DV8C Data Sheet This document
Detailed system design information including Typical
CS4953xx Hardware User’s Manual
Connection Diagrams, boot-procedures, pin
descriptions, and other system configuration
information.
Application note contains an Application
Programming Interface (API) used to control the
Dolby Volume firmware.
Includes detailed configuration and usage
information for the GUI development tool.
AN288PPH, “Dolby
DSP Composer
®
Volume Module”
™
User’s Manual
The scope of the CS49DV8C Data Sheet is primarily the hardware specifications of the CS49DV8C
devices. This includes hardware functionality, characteristic data, pinout, and packaging info rmation.
The intended audience for the CS49DV8C Data Sheet is the system PCB designer, MCU programmer,
and the quality control engineer.
2. Overview
The CS49DV8C DSP is designed to provide high-performance volume control using the Dolby Volume
algorithm. The CS49DV8, supports up to 7.1 Channels of Dolby Volume processing at 48 kHz, 44.1 kHz
or 32 kHz while leaving the 2nd core of the DSP completely available for even further processing
functions such as Quadruple Crossover Bass Management, Tone Control, and Multiband Parametric
EQ.
The CS49DV8C DSP, together with Cirrus Logic’s comprehensive li brary of audio pro cessing algorith ms,
enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a
broad array of digital interface products, and audio converters, to meet your audio system-level design
requirements.
The CS49DV8C is available in a 128-pin LQFP package.
Please refer to Table 2 on page 6 for the processor speed and available firmware for the CS49DV8C
product family.
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 5
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 6
Table 2. Device and Firmware Selection Guide
Device
Pre-
Process
Decode Processor A
1
Mid-processor A
1
Mid-processor B
1
Post-processor
• Tone Control
CS49DV8C
300 MIPS
None
• Ste r eo PCM
• Multi-Channel PCM
(2:1 Downsampling Option)
(4:1 Downsampling Option)
®
Dolby
Volume
(Runs on either DSP A or B)
See Section 3. for additional
concurrency information.
Dolby® Volume
(Runs on either DSP A or B)
See Section 3 . for a dditio nal
concurrency information.
• Re-EQ
• PEQ (up to 11 bands)
• Delay
• 7.1 Bass Manager
• Audio Manager
• 1:2 Upsampling
1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.
1
32-bit Audio DSP Family
CS49DV8C Data Sheet
CS49DV8C Data Sheet
32-bit Audio DSP Family
2.1 Licensing
Licenses are required for Dolby Volume and for all of the third party audio processing algorithms. Please
contact your local Cirrus Sales representative for more information.
3. Firmware Supported
The suite of software available for the CS49DV8C family consists of operating systems (OS) and a
library of overlays. The overlays have been divided into three main groups called Decoders, Midprocessors, and Post-processors. All software components are defined as follows:
• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, auto-detection, error
concealment, etc.
• Dolby V ol ume - The CS49DV8C can run Dolby Volume on either DSP A or DSP B. On the DSP that
is not running Dolby Volume, it can run the firmware currently available on the CS4953xx family for
that DSP (A or B).
4. Hardware Functional Description
4.1 DSP Core
The CS49DV8C is a dual-core DSP with separate X and Y data and P code memory spaces. Each core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two
memory access control (MAC) operations per cl ock cycle. Each core has eight 72-bit accumulat ors, four
X- and four Y-data registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between
peripherals such as the digi tal audio input (DAI) and digital audio output (DAO), external memory, or any
DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move
instructions from the DSP core, leaving more MIPS available for signal processing instructions.
CS49DV8C functionality is controlled by application codes that are stored in on-board ROM or
downloaded to the CS49DV8C from a host MCU or external FLASH/EEPROM. Users c an choos e to use
standard audio post-processor modules which are available from Cirrus Logic.
4.1.1 DSP Memory
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS49DV8C DSP Memory Sizes
Memory
Type
X 16k SRAM, 32k ROM 10k SRAM, 8k ROM
DSP A DSP B
Y 24k SRAM, 32k ROM 16k SRAM, 16k ROM
P 8k SRAM, 32k ROM 8k SRAM, 24k ROM
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource
has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 7
CS49DV8C Data Sheet
32-bit Audio DSP Family
memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start
address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt
events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of
accepting PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally support is provided
for audio data input to the DSP via the DAI from an HDMI receiver.
The port has two independent slave-only clock domains. Each dat a input can be independen tly assigned
to a clock domain. The sample rate of the input clock domains can be determined automatically by the
DSP, which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature
allows the input data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports
data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in
slave mode, or the ratio of the two clocks can be set to even mult iples of each other in master mode. The
two ports can also be ganged together into a single c lock domain. Each por t has one serial aud io pin that
can be configured as a 192 kHz SPDIF transmitter (data with embedded clock on a single line).
2C®
4.2.3 Serial Control Port 1 & 2 (I
or SPI™)
There are two on-chip seri al cont rol ports that are capabl e of oper ating as mas ter or slave in either I
SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an
external clock up to 25MHz in SPI mode. This high clock speed enables very fast code download,
control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial
Flash memory or for audio sub-system control.
4.2.4 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.5 GPIO
Many of the CS49DV8C peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an
output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge,
falling edge, active-low, or active-high.
4.2.6 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to
clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain
can be output on the DAO port for driving audio converters. The CS49DV8C default s to runni ng from the
external reference frequency and can be switched to use the PLL output after overlays have been
loaded and configured, either through master boot from an external FLASH or through host control. A
built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1.
2
C or
8 Copyright 2008 Cirrus Logic, Inc. DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS49DV8C pins are multi-functional. For details on pin functionality please refer to the
CS4953xx Hardware User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS49DV8C must be pulled high for proper operation. Please refer to the
CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
resistor is required for proper operation.
Mode select pins on the CS49DV8C are used to select the boot mode upon the rising edge of reset. A
detailed explanation of termination requirements for each communication mode select pin can be found
in the CS4953xx Hardware User’s Manual.
4.3.3 Pads
The CS49DV8C I/O operates from the 3.3 V supply and is 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it
may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored
external to the device.
DS868PP2 Copyright 2008 Cirrus Logic, Inc. 9
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