Cirrus Logic CS4970x4 User Manual
CS4970x4 Data Sheet
Coyote 32-bit
DSP A
D
M
A
Coyote 32-bit
DSP B
Ext. Memory Controller
P
S/PDIF
X Y P X Y
Serial
Control 1
16 Ch PCM
Audio Out
Serial
Control 2
Parallel
Control
GPIO Debug
STC
TMR1
TMR2
PLL
S/PDIF
12 Ch. Audio In /
6 Ch. SA CD In
FEATURES
Multi-standard 32-bit high-definition audio decoding plus
post-processing
Supports high-definition audio formats including:
®
— Dolby Digital
— Dolby
®
—DTS-HD
—DTS-HD
— DTS Express™ 5.1
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1, Dolby
Headphone® 2, Dolby Virtual Speaker® 2, Dolby
Volume® (original), Dolby Volume 258 (lite), Audistry
— DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1,
DTS-ES™ Matrix 6.1, DTS Neo:6®, DTS Neural
Surround
— MPEG-2 AAC
®
—SRS
Circle Surround® II, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
TruVolume™ 7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4®, SRS WOW HD™, SRS CS Headphone™,
SRS Circle Cinema 3D
—THX® Ultra2™, THX Select2
Cirrus Logic’s Applications Library
— Cirrus Original Multi-Channel Surround 2 (COMS2),
Cirrus Band XpandeR
Technology (CVT), Cirrus Intelligent Room Calibration 2
(IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass Manager
Quadruple Crossover, Tone Control, 11- Band
Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4
Upsampler
Plus
TrueHD
®
High Resolution Audio
Master Audio
™
DTS Surround Sensation Speaker
™
LC 5.1
™
™
, SRS Studio Sound HD
™
™
, Cirrus Virtualization
™
High Definition Audio Decoder DSP Family
with Dual 32-bit Engine Technology
Up to 12 Channels of 32-bit Serial Audio Input
Customer Software Security Keys
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI
™/I2C™
ports
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
The CS4970x4 DSP family is an enhanced version of the
CS4953xx DSP family with higher overall performance. In
®
addition to all the mainstream audio processing codes in onchip ROM that the CS4953xx DSP offers, the CS4970x4 device
family also supports the decoding of major high-definition audio
formats. Additionally, the CS4970x4, a dual-core device,
performs the high-definition audio decoding on the first core,
leaving the second core available for audio post-processing and
audio enhancement. The CS4970x4 device supports the most
demanding audio post processing requirements. It provides an
easy upgrade path to systems currently using the CS495xx or
CS4953xx device with minor (or no) hardware and software
changes.
Ordering Information
See page 27 for ordering information.
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © 2014 Cirrus Logic, Inc. FEB 2014
All Rights Reserved DS752F1
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Table of Contents
1 Documentation Strategy .................................... ................................. ................. ................ ......4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(3) to CS4970x4 .................................................................................................5
2.2 Licensing ............................ .... ....................................................... ...........................................................5
3 Code Overlays ............................................................................................................... .............5
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core ............................................ .... ... ... ... .... ... .....................................................................6
4.1.1 DSP Memory ................... ... .... ... ....................................................... ... ... ... .... ... ... ... .....................6
4.1.2 DMA Controller ...... .... ... ....................................................... ... ... ... .... ... ... ... ..................................7
4.2 On-chip DSP Peripherals .........................................................................................................................7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
4.2.3 Serial Control Port 1 & 2 (I
4.2.4 External Memory Interface ..................................... ... ... .... ... ... ... ... .... ...........................................7
4.2.5 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.6 Phase-locked Loop (PLL)-based Clock Generator ....... ....................................................... ........7
4.3 DSP I/O Description .................................................................................................................................8
4.3.1 Multiplexed Pins ................................. .... ... ....................................................... ... ... .....................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ................................ ... .... ... ... ... ....................................................... .....................................8
4.4 Application Code Security ........................................................................................................................8
2
C or SPI) ..........................................................................................7
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ......................................................................................................................8
5.2 Recommended Operating Conditions ......................................................................................................9
5.3 Digital DC Characteristics ........................................................................................................................9
5.4 Power Supply Characteristics .......................................... ... ... ... ...............................................................9
5.5 Thermal Data (128-pin LQFP) ................................................ ................................................................10
5.6 Switching Characteristics—
5.7 Switching Characteristics — XTI .................. ....................................................................... ................... 11
5.8 Switching Characteristics — Internal Clock ............................................................................................12
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode .......................................................13
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode ...................................................14
5.11 Switching Characteristics — Serial Control Port - I
5.12 Switching Characteristics — Serial Control Port - I
5.13 Switching Characteristics — Parallel Control Port - Intel Slave Mode ........................ ... ......................16
5.14 Switching Characteristics — Parallel Control Port - Motorola Slave Mode .........................................19
5.15 Switching Characteristics — Digital Audio Slave Input Port .................................................................21
5.16 Switching Characteristics — Digital Audio Output Port ........................................................................22
5.17 Switching Characteristics — SDRAM Interface ....................................................................................23
RESET ...................................... ............................................. ...................... 11
2
C Slave Mode ... ... ................................................15
2
C Master Mode ....................................................16
6 Ordering Information ...............................................................................................................27
7 Environmental, Manufacturing, and Handling Information .................................................27
8 Device Pin-Out Diagram ..........................................................................................................28
8.1 128-Pin LQFP Pin-Out Diagram .............................................................................................................28
9 Package Mechanical Drawings ...............................................................................................29
9.1 128-Pin LQFP Package Drawing ...........................................................................................................29
10 Revision History .....................................................................................................................30
DS752F1 2
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
List of Figures
Figure 1. RESET Timing .........................................................................................................................................11
Figure 2. XTI Timing ..............................................................................................................................................11
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................13
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................14
Figure 5. Serial Control Port - I
Figure 6. Serial Control Port - I
Figure 7. Parallel Control Port - IntelÒ Slave Mode Read Cycle ........................................... .... ... ... ... ... .... ............17
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................18
Figure 9. Parallel Control Port - MotorolaÒ Slave Mode Read Cycle Timing ........................................................20
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................20
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................21
Figure 12. DAI Slave Timing Diagram ...................................................................................................................21
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................22
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ............... ... ... ... ... .... ... ... ... ...23
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................24
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................24
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....... .... ... ... ... ... .... ... ......................................25
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................26
Figure 19. 128-Pin LQFP Pin-Out Diagram ...........................................................................................................28
Figure 20. 128-Pin LQFP Package Drawing ..........................................................................................................29
2
C Slave Mode Timing ..........................................................................................15
2
C Master Mode Timing .............. .... ... ... ... .... ... ......................................................16
List of Tables
Table 1. CS4970x4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. CS4970x4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS752F1 3
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
1 Documentation Strategy
The CS4970x4 data sheet describes the CS4970x4 family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4970x4 family of processors.
Table 1. CS4970x4 Related Documentation
Document Name Description
CS4970x4 Data Sheet This document
A new consolidated documentation set that includes:
• Detailed system design information including
Typical Connection Diagrams, Boot-Procedures,
CS495314/CS4970x4 System Designer’s Guide
AN288 - CS4953xx/CS4970x4 Firmware User’s Manual
Pin Descriptions, Etc. Also describes use of DSP
Condenser tool.
• Detailed firmware design information including
signal processing flow diagrams and control API
information
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
The scope of the CS4970x4 data sheet is primarily to provide hardware specifications of the CS4970x4 family
of devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4970x4 data sheet is the system PCB designer, MCU programmer, and the
quality control engineer.
2 Overview
The CS4970x4 DSP Family, combined with Cirrus Logic’s comprehensive library of audio processing
algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also
provides a broad array of digital interface products and audio converters to meet your audio system-level
design requirements.
Note: The CS4970x4 is available in a 128-pin LQFP package.
The audio processing features of the CS4970x4 product family are a superset of audio features available in
the CS4953xx product family.
Refer to Table 2 on page 5 for the speed and firmware features of the CS4970x4 product family.
DS752F1 4
32-bit High Definition Audio Decoder DSP Family
Table 2. Device and Firmware Selection Guide
CS4970x4 Data Sheet
Device
CS497014
300MACS
CS497004
300MACS
CS497024
300MACS
1. Additional processing (MPMA, MPMB/VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic
FAE for the latest concurrency matrix.
2. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also
available as a separate post-processing module that is described in the application note AN288PPI.
3. The indicated HD audio decoder algorithms require external SDRAM. Consult your Cirrus Logic FAE for the recommended
SDRAM size for your design.
Decode Processor
(DSP-A)
Stereo PCM
(4:1/2:1 Down-sampling and
1:2/1:4 U-sampling Options)
Multichannel PCM
(4:1/2:1 Down-sampling and
1:2/1:4 Up-sampling Options)
Dolby Digital
MPEG-2 AAC LC 5.1
Dolby Digital Plus
Dolby TrueHD
Same as CS497014 +
DTS, DTS-ES, DTS96/24
DTS-HD Master Audio
DTS-HD High Res Audio
DTS Express 5.1
1
3
Matrix Processor Module
(DSP-A)
Dolby Pro Logic II / IIx / IIz 7.1
SRS Circle Surround II / Circle
2
Surround Auto / Circle
Surround Decoder Optimized
(Stereo In)
2
Cirrus Original Multi-Channel
Surround 2 (Effects / Reverb
Processor)
Crossbar (Down-mix / Up-mix)
(Simultaneous Process)
3
3
Same as CS497014 +
DTS Neo:6, DTS Neural
Surround
1
Virtualizer Processor
Module
(DSP-B)
Cirrus Virtualizer
Technology
Dolby Headphone 2
Dolby Virtual Speaker 2
SRS CS Headphone
SRS TruSurround HD/HD4
1
Post Processor
Module
(DSP-B)
APP
(Advanced Postprocessing)
–Tone Control
–Select 2
–PEQ (up to 11 Bands)
–Delay
(Speaker to Listening
Position Alignment
and/or Lip Sync)
–7.1 Bass Manager
–Audio Manager
–4:1/2:1 Down-sampling
SRS TruVolume 7.1
Multichannel
Dolby Volume
Multichannel
1
2
2.1 Migrating from CS495xx(3) to CS4970x4
CS4970x4 was designed to provide an easy upgrade path from the CS495xx and CS4953x. There are some
small differences the hardware designer should be aware of:
• The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx.
• The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx.
• The CS4970x4 adds support for Time-division multiplexing (TDM) mode on both audio input and output
ports.
• The CS4970x4 does not support external static random access memory (SRAM) operation.
• The CS4970x4 external Synchronous dynamic random access memory (SDRAM) bus speed is fixed at
150 MHz vs. the 120 MHz maximum bus speed for the CS495xx. Some firmware modules also support a
75 MHz CS4970x4 SDRAM bus speed. Refer to AN304 for details.
• The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.
2.2 Licensing
Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the
application notes. Contact your local Cirrus Sales representative for more information.
3 Code Overlays
The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of
overlays. The overlays have been divided into three main groups: decoders, matrix processors, and
postprocessors. All software components are defined in the following list:
DS752F1 5
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audi o- pr oc es sin g subroutines, auto-detection, error concealment, etc.
• Decoders - Any module that initially writes data into the audio I/O buf fers, e.g. AC-3
the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data
2
via I
S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc.
™
, DTS, PCM, etc. All
• Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Postprocessors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are
Dolby ProLogic IIx and DTS Neo:6.
• Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input
channels (n2 channels) with the effect of providing “phantom” speakers to represent the physical audio
channels that were eliminated. Examples are Dolby Headphone 2 an d Dolby V irtual Speaker 2. Generally
speaking, these modules reduce the number of valid channels in the audio I/O buffer.
• Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix
processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific
effects, Dolby Headphone/Virtual Speaker, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay ca n be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
4 Hardware Functional Description
4.1 Coyote DSP Core
The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply
accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumu lators, four X- and four Y-data
registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory , all with out the intervention of the DSP. The DMA engine of floads dat a move instructio ns from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4970x4 is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,
and digital broadcast decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and progra m RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio
formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD master audio.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
DS752F1 6
32-bit High Definition Audio Decoder DSP Family
Table 3. CS4970x4 DSP Memory Sizes
CS4970x4 Data Sheet
Memory
Type
X 16K SRAM, 32K ROM 10K SRAM, 8K ROM
Y 24K SRAM, 32K ROM 16K SRAM, 16K ROM
P 8K SRAM, 32K ROM 8K SRAM, 24K ROM
DSP A DSP B
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its
own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the
peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment
controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmabl e.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6-line) DAI port support s a wide vari ety of dat a input forma t s. The port is capable of accepting
PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally, support is provided for audio data
input to the DSP via the DAI from an HDMI receiver.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off-loads the task of monitorin g the SPDIF rece iver from the host. A time -stam ping feature allows the input dat a
to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data
rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or
the ratio of the two clocks can be set to even multiples of each other in master mode. The two por ts can also b e
ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a
192-kHz SPDIF transmitter (data with embedded clock on a single line).
4.2.3 Serial Control Port 1 & 2 (I
2
C or SPI)
There are two on-chip serial contro l ports that are capable of operating as master or slave in either I
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data
delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for
audio sub-system control.
4.2.4 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.5 General Purpose Input/Output (GPIO)
Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
4.2.6 Phase-locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clo ck the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
2
C or SPI
DS752F1 7
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a
buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4
System Designer’s Guide.
4.3.2 Termination Requirements
Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4
System Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is require d for
proper operation.
Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4970x4 System Designer’s Guide.
4.3.3 Pads
The CS4970x4 I/O operates from the 3.3 V supply and is tolerant within 5 V.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage
and temperature. All data sheet typical parameters are measured under the following conditions:
T=25°C, C
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
DC power supplies: Core supply
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
Storage temperature
CAUTION: Operation at or beyond these limits may result in permanent damage to the de vice. Normal oper ation is
not guaranteed at these extremes.
= 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
L
Parameter Symbol Min Max Unit
V
V
V
V
PLL supply
I/O supply
|VDDA – VDDIO|
VDD
VDDA
VDDIO
I
in
V
filt
V
inio
T
stg
–0.3
–0.3
–0.3
—
2.0
3.6
3.6
0.3
—+/- 10mA
-0.3 3.6 V
-0.3 5.0 V
-65 150 °C
DS752F1 8
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter Symbol Min Typ Max Unit
DC power supplies: Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
Ambient operating temperature
Commercial Grade (CQZ/CVZ)
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
1.89
3.46
3.46
0
T
A
0 +25 + 70
V
V
V
V
°C
Commercial
T
j
0+125ºC
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter Symbol Min Typ Max Unit
High-level input voltage
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
High-level output voltage (IO = -4mA), except XTI, SDRAM
pins
Low-level output voltage (IO = 4mA), except XTI, SDRAM
pins
SDRAM High-level output voltage (IO = -8mA)
SDRAM Low-level output voltage (IO = 8mA)
Input leakage current (all digital pins with internal pull-up
resistors disabled)
Input leakage current (all digital pins with internal pull-up
resistors enabled, and XTI)
V
V
V
ILXTI
V
hys
V
OH
V
V
OH
V
I
IN
I
IN-PU
IH
IL
OL
OL
2.0 — — V
——0.8 V
——0.6 V
—0.4— V
VDDIO * 0.9 — — V
——VDDIO * 0.1V
VDDIO * 0.9 — — V
——VDDIO * 0.1V
—— 5 A
——70 A
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.)
Parameter Min Typ Max Unit
Power supply current:
Core and I/O operating: VDD
PLL operating: VDDA
With external memory and most ports operating: VDDIO
1.Dependent on application firmware and DSP clock speed.
1
—
—
—
350
3.5
120
—
—
—
mA
mA
mA
DS752F1 9
5.5 Thermal Data (128-pin LQFP)
Parameter Symbol Min Typ Max Unit
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Thermal Resistance (Junction to Ambient)
Two-layer Board
Four-layer Board
Thermal Resistance (Junction to Top of Package )
Two-layer Board
Four-layer Board
ja
jt
—
—
—
—
53
44
.45
.39
—
—
—
—
1
2
1
2
°C / Watt
°C / Watt
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers.
3. To calculate the die temperature for a given power dissipation
= Ambient Temperature + [ (Power Dissipation in Watts) * ja ]
j
4. To calculate the case temperature for a given power dissipation
= j - [ (Power Dissipation in Watts) * jt
c
DS752F1 10
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