Cirrus Logic CS4955 User Manual

NTSC/PAL Digital Video Encoder

CS4954
CS4955

Features

z Six DACs providing simultaneous

composite,S-video, and RGB or Component
YUV outputs

z Programmable DAC output currents for low

impedance (37.5 Ω) and high impedance
(150 Ω) loads

z Multi-standard support for NTSC-M, NTSC-

JAPAN, PAL (B, D, G, H, I, M, N,
Combination N)

z ITU R.BT656 input mode supporting

EAV/SAV codes and CCIR601 Master/Slave
input modes

z Programmable HSYNC and VSYNC timing
z Multistandard Teletext (Europe, NABTS,

WST) support

z VBI encoding support
z Wide-Screen Signaling (WSS) support, EIA-J

CPX1204

z NTSC closed caption encoder with interrupt
z CS4955 supports Macrovision copy

protection Version 7

z Host interface configurable

for parallel or I²C® compatible
operation

z On-chip voltage reference

generator

z +3.3 V or +5 V operation,

CMOS, low-power modes,
three-state DACs

CLK
SCL

SDA

PDAT[7:0]

RD

WR

PADR

XTAL_IN

XTAL_OUT

TTXDAT

TTXRQ

VD[7:0]

HSYNC
VSYNC

FIELD

INT

RESET

8

8

Description

The CS4954/5 provides full conversion from digital video
formats YCbCr or YUV to NTSC and PAL Composite,
Y/C (S-video) and RGB, or YUV analog video. Input for­mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU
R.BT656 with support for EAV/SAV codes. Video output
can be formatted to be compatible with NTSC-M, NTSC­J, PAL-B,D,G,H,I,M,N, and Combination N systems.
Closed Caption is supported in NTSC. Teletext is sup­ported for NTSC and PAL.

Six 10-bit DACs provide two channels for an S-Video
output port, one or two composite video outputs, and
three RGB or YUV outputs. Two-times oversampling re­duces the output filter requirements and guarantees no
DAC-related modulation components within the speci­fied bandwidth of any of the supported video standards.

Parallel or high-speed I²C compatible control interfaces are
provided for flexibility in system design. The parallel interface
doubles as a general purpose I/O port when the CS4954/5 is
in I²C mode to help conserve valuable board area.

The CS4954 and CS4955 are available in a 48-pin TQFP
and operate in -40 to +85°C ambient temperature. The
CDB4954/55 Customer Demonstration board is also
available. Please refer to “Ordering Information” on

page 2.

VAA

I²C Interface

Control

Host

Parallel

Interface

Color Sub-carrier Synthesizer

Teletext
Encoder

Video Formatter

Video Timing

Generator

Registers

YCbCr to RBG

Color Space

Converter

DGND

Output

Interpolate

Chroma Amplifier

Chroma Modulate

Burst Insert

Chroma Interpolate

U,V

Y

Luma Interpolate

Luma Amplifier

Sync Insert

RGB

LPF

LPF

Y

Y

RGB

Σ

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

10-Bit

DAC

Voltage

Reference

Current

Reference

TEST

C

CVBS

Y

R

G

B

VREF

ISET

Copyright © Cirrus Logic, Inc. 2006

(All Rights Reserved)

www.cirrus.com

SEPTEMBER '06

DS278F6

1

CS4954 CS4955

ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order#

CS4954

CS4955 CS4955-CQZ

CDB4954/55 CS4954/55 Evaluation Board No - - - CDB4954A/55A

2 DS278F6

NTSC/PAL Digital

Video Encoder

48-TQFP Yes Commercial -40º to +85ºC Rail

CS4954-CQZ

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................................6

AC & DC PARAMETRIC SPECIFICATIONS ............................................................................................6

RECOMMENDED Operating Conditions .......................................................................................................6

THERMAL CHARACTERISTICS ..............................................................................................................6

DC CHARACTERISTICS ..........................................................................................................................6

AC CHARACTERISTICS ..........................................................................................................................8

TIMING CHARACTERISTICS ...................................................................................................................9

2. ADDITIONAL CS4954/5 FEATURES .....................................................................................................11

3. CS4954 INTRODUCTION ......................................................................................................................11

4. FUNCTIONAL DESCRIPTION ...............................................................................................................11

4.1 Video Timing Generator ...............................................................................................................11

4.2 Video Input Formatter ..................................................................................................................12

4.3 Color Subcarrier Synthesizer .......................................................................................................12

4.4 Chroma Path ................................................................................................................................12

4.5 Luma Path ....................................................................................................................................13

4.6 RGB Path and Component YUV Path ..........................................................................................13

4.7 Digital to Analog Converters ........................................................................................................13

4.8 Voltage Reference .......................................................................................................................14

4.9 Current Reference ........................................................................................................................14

4.10 Host Interface ...............................................................................................................................14

4.11 Closed Caption Services ..............................................................................................................14

4.12 Teletext Services ..........................................................................................................................15

4.13 Wide-Screen Signaling Support and CGMS ................................................................................15

4.14 VBI Encoding ...............................................................................................................................15

4.15 Control Registers .........................................................................................................................15

4.16 Testability .....................................................................................................................................15

5. OPERATIONAL DESCRIPTION ............................................................................................................15

5.1 Reset Hierarchy ...........................................................................................................................15

5.2 Video Timing ................................................................................................................................16

5.2.1 Slave Mode Input Interface ...............................................................................................16

5.2.2 Master Mode Input Interface .............................................................................................16

5.2.3 Vertical Timing ...................................................................................................................17

5.2.4 Horizontal Timing ..............................................................................................................17

5.2.5 NTSC Interlaced ................................................................................................................17

5.2.6 PAL Interlaced ...................................................................................................................17

5.2.7 Progressive Scan ..............................................................................................................18

5.2.8 NTSC Progressive Scan ...................................................................................................18

5.2.9 PAL Progressive Scan ......................................................................................................19

5.3 ITU-R.BT656 ................................................................................................................................19

5.4 Digital Video Input Modes ............................................................................................................21

5.5 Multi-standard Output Format Modes ..........................................................................................21

5.6 Subcarrier Generation ..................................................................................................................22

5.7 Subcarrier Compensation ............................................................................................................23

5.8 Closed Caption Insertion ..............................................................................................................23

5.9 Programmable H-sync and V-sync ..............................................................................................24

5.10 Wide Screen Signaling (WSS) and CGMS ..................................................................................24

5.11 Teletext Support ...........................................................................................................................24

5.12 Color Bar Generator .....................................................................................................................26

5.13 VBI encoding ................................................................................................................................27

5.14 Super White/Super Black support ................................................................................................27

5.15 Interrupts ......................................................................................................................................27

5.16 General Purpose I/O Port .............................................................................................................27

6. FILTER RESPONSES ............................................................................................................................29

7. ANALOG ................................................................................................................................................32

7.1 Analog Timing ..............................................................................................................................32

7.2 VREF ............................................................................................................................................32

7.3 ISET .............................................................................................................................................32

7.4 DACs ............................................................................................................................................32

7.4.1 Luminance DAC ................................................................................................................32

7.4.2 Chrominance DAC ............................................................................................................33

7.4.3 CVBS DAC ........................................................................................................................33

7.4.4 Red DAC ...........................................................................................................................33

CS4954 CS4955

DS278F6 3

CS4954 CS4955

7.4.5 Green DAC ....................................................................................................................... 33

7.4.6 Blue DAC .......................................................................................................................... 33

7.4.7 DAC Useage Rules ........................................................................................................... 34

8. PROGRAMMING ................................................................................................................................... 34

8.1 Host Control Interface .................................................................................................................. 34

8.1.1 I²C® Interface ................................................................................................................... 34

8.1.2 8-bit Parallel Interface ....................................................................................................... 35

8.2 Register Description .................................................................................................................... 36

9. BOARD DESIGN AND LAYOUT CONSIDERATIONS ......................................................................... 53

10. PIN DESCRIPTION ............................................................................................................................... 56

11. PACKAGE DRAWING ........................................................................................................................... 58

12. REVISION HISTORY ............................................................................................................................. 59

8.2.1 Control Registers .............................................................................................................. 36

9.1 Power and Ground Planes .......................................................................................................... 53

9.2 Power Supply Decoupling ........................................................................................................... 53

9.3 Digital Interconnect ...................................................................................................................... 53

9.4 Analog Interconnect ..................................................................................................................... 53

9.5 Analog Output Protection ............................................................................................................ 54

9.6 ESD Protection ............................................................................................................................ 54

9.7 External DAC Output Filter .......................................................................................................... 54

4 DS278F6

LIST OF FIGURES

Figure 1. Video Pixel Data and Control Port Timing ..................................................................8

Figure 2. I²C Host Port Timing ...................................................................................................9

Figure 3. Reset Timing.............................................................................................................10

Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing ...................................................16

Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing .................................................16

Figure 6. Vertical Timing ..........................................................................................................18

Figure 7. NTSC Video Interlaced Timing .................................................................................19

Figure 8. PAL Video Interlaced Timing ....................................................................................20

Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing ............................................21

Figure 10. PAL Video Non-Interlaced Progressive Scan Timing .............................................22

Figure 11. CCIR656 Input Mode Timing ..................................................................................22

Figure 12. Teletext Timing (Pulsation Mode) ...........................................................................25

Figure 13. Teletext Timing (Window Mode) .............................................................................25

Figure 14. 1.3 MHz Chrominance low-pass filter transfer characteristic..................................29

Figure 15. 1.3 MHz Chrominance low-pass filter transfer characterstic (passband) ...............29

Figure 16. 650 kHz Chrominance low-pass filter transfer characteristic ..................................29

Figure 17. 650 kHz Chrominance low-pass filter transfer characteristic (passband) ...............29

Figure 18. Chrominance output interpolation filter transfer characteristic (passband).............30

Figure 19. Luminance interpolation filter transfer characteristic ..............................................30

Figure 20. Luminance interpolation filter transfer characterstic (passband) ............................30

Figure 21. Chrominance interpolation filter transfer characteristic for RGB datapath..............30

Figure 22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) ....31

Figure 23. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) ....31

Figure 24. Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB ..............................31

Figure 25. Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale).....................31

Figure 26. I²C Protocol .............................................................................................................35

Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle...............................35

Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle .............................................36

Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle .............................................36

Figure 30. External Low Pass Filter .........................................................................................54

Figure 31. Typical Connection Diagram...................................................................................55

CS4954 CS4955

5 DS278F6

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

CS4954 CS4955

AC & DC PARAMETRIC SPECIFICATIONS

Parameter Symbol Min Max Units

Power Supply VAA/VDD -0.3 6.0 V

Input Current Per Pin (Except Supply Pins) -10 10 mA

Output Current Per Pin (Except Supply Pins) -50 +50 mA

Analog Input Voltage -0.3 VAA + 0.3 V

Digital Input Voltage -0.3 VDD + 0.3 V

Ambient Temperature Power Applied -55 + 125 °C

Storage Temperature -65 + 150 °C

WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

(AGND,DGND = 0 V, all voltages with respect to 0 V

RECOMMENDED Operating Conditions (AGND,DGND = 0 V, all voltages with respect to 0 V.)

Parameter Symbol Min Typ Max Units

Power Supplies: Digital Analog VAA/VDD 3.15

4.75

Operating Ambient Temperature TA -40 +25 +85 °C

Note: Operation outside the ranges is not recommended.

3.3

5.0

3.45

5.25

V

)

THERMAL CHARACTERISTICS

Parameters Symbol Min Typ Max Units

Allowable Junction Temperature - - 150 °C
Junction to Ambient Thermal Impedance - - -

(Four-layer PCB) TQFP

(Two-layer PCB) TQFP θ

Note: Four-layer PCB recommended for operation in environments where TA > 70° C.

DC CHARACTERISTICS (T

Parameter Symbol Min Typ Max Units

Digital Inputs

High level Input Voltage
V [7:0], PDAT [7:0], Hsync/Vsync/CLKIN

High Level Input Voltage I²C

Low level Input Voltage All Inputs - -0.3 - 0.8 V

Input Leakage Current - -10 - +10 μA

Digital Outputs

High Level Output Voltage lo = -4 mA VOH 2.4 - VDD V

Low level Output Voltage lo = 4 mA VOL - - 0.4 V

= 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.)

A

θ

JA-TM

JA-TS

VIH 2.2 - VDD+0.3 V

VIH 0.7 VDD - - V

-45-

-65-

°C/W

6 DS278F6

CS4954 CS4955

Parameter Symbol Min Typ Max Units

Low Level Output Voltage SDA pin only, lo = 6mA VOL - - 0.4 V

Output Leakage Current High-Z Digital Outputs - -10 - +10 μA

Analog Outputs

Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IO 32.9 34.7 36.5 mA

Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IO 8.22 8.68 9.13 mA

LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IB 32.2 33.9 35.7 μA

LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IB 8.04 8.48 8.92 μA

DAC-to-DAC Matching (Note 1)MAT - 2 4 %

Output Compliance (Note 1)VOC 0 - + 1.4 V

Output Impedance (Note 1)ROUT - 15 - kΩ

Output Capacitance (Note 1)COUT - - 30 pF

DAC Output Delay (Note 1)ODEL - 4 12 ns

DAC Rise/Fall Time (Note 1, 5)TRF - 2.5 5 ns

Voltage Reference

Reference Voltage Output VOV 1.170 1.232 1.294 V

Reference Input Current (Note 1)UVC - - 10 μA

Power Supply

Supply Voltage VAA, VDD 3.15

4.75

Digital Supply Current IAA1 - 70 150 mA

Analog Supply Low-Z (Note 6) IAA2 - 100 150 mA

Analog Supply High-Z (Note 7) IAA3 - 60 100 mA

Power Supply Rejection Ratio PSRR 0.02 0.05 V / V

Static Performance

DAC Resolution (Note 1)--10Bits

Differential Non-Linearity (Note 1) DNL -1 +

Integral Non-Linearity (Note 1)INL - 2 +

Dynamic Performance

Differential Gain (Note 1)DG - 2 5 %

Differential Phase (Note 1)DP - +

Hue Accuracy (Note 1)HA - - 2 °

Signal to Noise Ratio SNR 70 - - dB

Saturation Accuracy (Note 1)SAT - 1 2 %

3.3

5.0

0.5 + 1 LSB

1+ 2LSB

0. 5 + 2°

3.45

5.25

V

Notes: 1. Values are by characterization only

2. Output current levels with ISET = 4 kΩ , VREF = 1.232 V.

3. DACs are set to low impedance mode

4. DACs are set to high impedance mode

5. Times for black-to-white-level and white-to-black-level transitions.

6. Low-Z, 3 DACs on

7. High-Z, 6 DACs on

DS278F6 7

CS4954 CS4955

AC CHARACTERISTICS

Parameter Symbol Min Typ Max Units

Pixel Input and Control Port (Figure 1)

Clock Pulse High Time Tch 14.82 18.52 22.58 ns

Clock Pulse Low Time Tcl 14.82 18.52 22.58 ns

Clock to Data Set-up Time Tisu 6 - - ns

Clock to Data Hold Time Tih 0 - - ns

Clock to Data Output Delay Toa - - 17 ns

CLK

T

isu

T

chTcl

V[7:0]

HSYNC

HSYNC

CB/FIELD

/VSYNC

(Inputs)

/VSYNC

(1)

/INT

(Outputs)

T

ih

T

oa

Figure 1. Video Pixel Data and Control Port Timing

8 DS278F6

CS4954 CS4955

TIMING CHARACTERISTICS

Parameter Symbol Min Typ Max Units

I²C Host Port Timing (Figure 2)

SCL Frequency Fclk 1000 kHz

Clock Pulse High Time Tsph 0.1 μs

Clock Pulse Low Time Tspl 0.7 μs

Hold Time (Start Cond.) Tsh 100 ns

Setup Time (Start Cond.) Tssu 100 ns

Data Setup Time Tsds 50 ns

Rise Time Tsr 1 μs

Fall Time Tsf 0.3 μs

Setup Time (Stop Cond.) Tss 100 ns

Bus Free Time Tbuf 100 ns

Data Hold Time Tdh 0 ns

SCL Low to Data Out Valid Tvdo 600 ns

SDA

SCL

T

dh

ds

T

sh

T

vdo

T

ssu

T

ss

T

sh

T

bu

T

sr

T

spi

T

T

sph

T

si

Figure 2. I²C Host Port Timing

DS278F6 9

TIMING CHARACTERISTICS(Continued)

CS4954 CS4955

Parallel Host Port Timing (Figure 27, 28, 29)

Read Cycle Time Trd 60 - - ns

Read Pulse Width Trpw 30 - - ns

Address Setup Time Tas 3 - - ns

Read Address Hold Time Trah 10 - - ns

Read Data Access Time Trda - - 40 ns

Read Data Hold Time Trdh 10 - 50 ns

Write Recovery Time Twr 60 - - ns

Write Pulse Width Twpw 40 - - ns

Write Data Setup Time Twds 8 - - ns

Write Data Hold Time Twdh 3 - - ns

Write-Read/Read-Write Recovery Time Trec 50 - - ns

Address from Write Hold Time Twac 0 - - ns

Reset Timing (Figure 3)

Reset Pulse Width Tres 100 ns

Symbol Min Typ Max Units

RESET*

T

res

Figure 3. Reset Timing

10 DS278F6

CS4954 CS4955

2. ADDITIONAL CS4954/5 FEATURES

• Five programmable DAC output combinations,
including YUV and second composite

• Optional pseudo-progressive scan @ MPEG2
field rates

• Stable color subcarrier for MPEG2 systems

• General purpose input and output pins

• Individual DAC power-down capability

• On-chip color bar generator

• Supports RS170A and ITU R.BT601 compos­ite output timing

• HSYNC and VSYNC output in ITU R.BT656
mode

• Teletext encoding selectable on two composite
and S-video signals

• Programmable saturation, SCH Phase, hue,
brightness and contrast

The CS4954/5 is completely configured and con­trolled via an 8-bit host interface port or an I²C
compatible serial interface. This host port provides
access and control of all CS4954/5 options and fea­tures, such as closed caption insertion, interrupts,
etc.

In order to lower overall system costs, the
CS4954/5 provides an internal voltage reference
that eliminates the requirement for an external, dis­crete, three-pin voltage reference.

In ISO MPEG-2 system configurations, the
CS4954/5 can be augmented with a common color­burst crystal to provide a stable color subcarrier
given an unstable 27 MHz clock input. The use of
the crystal is optional, but the facility to connect
one is provided for MPEG-2 environments in
which the system clock frequency variability is too
wide for accurate color sub-carrier generation.

4. FUNCTIONAL DESCRIPTION

• Device power-down capability

• Super White and Super Black support

3. CS4954 INTRODUCTION

The CS4954/5 is a complete multi-standard digital
video encoder implemented in current CMOS tech­nology. The device can operate at 5 V as well as at

3.3 V. ITU R.BT601- or ITU R.BT656-compliant

digital video input is converted into NTSC-M,
NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I,
PAL-M, PAL-N, or PAL-N Argentina-compatible
analog video. The CS4954/5 is designed to con­nect, without glue logic, to MPEG1 and MPEG2
digital video decoders.

Two 10-bit DAC outputs provide high quality S­Video analog output while another 10-bit DAC si­multaneously generates composite analog video. In
addition, there are three more DACs to provide si­multaneous analog RGB or analog YUV outputs.
The CS4954/5 will accept 8-bit YCbCr or 8-bit
YUV input data.

In the following subsections, the functions of the
CS4954/5 will be described. The descriptions refer
to the device elements shown in the block diagram
on the cover page.

4.1 Video Timing Generator

All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4954/5 can also accept a signal from an optional
color burst crystal on the XTAL_IN &
XTAL_OUT pins. See the section, Color Subcarri­er Synthesizer, for further details.

The Video Timing Generator is responsible for or­chestrating most of the other modules in the device.
It operates in harmony with external sync input
timing, or it can provide external sync timing out­puts. It automatically disables color burst on appro­priate scan lines and automatically generates
serration and equalization pulses on appropriate
scan lines.

DS278F6 11

CS4954 CS4955

The CS4954/5 is designed to function as a video
timing master or video timing slave. In both Master
and Slave Modes, all timing is sampled and assert­ed with the rising edge of the CLK pin.

In most cases, the CS4954/5 will serve as the video
timing master. HSYNC, VSYNC, and FIELD

(1)

are configured as outputs in Master Mode. HSYNC
or FIELD can also be defined as a composite blank­ing output signal in Master Mode. In Master Mode,
the timing of HSYNC, VSYNC, FIELD and Com­posite Blank (CB) signals is programmable. Exact
horizontal and vertical display timing is addressed
in the Operational Description section.

In Slave Mode, HSYNC and VSYNC are typically
configured as input pins and are used to initialize
independent vertical and horizontal timing genera­tors upon their respective falling edges. HSYNC
and VSYNC timing must conform to the ITU­R BT.601 specifications.

The CS4954/5 also provides a ITU R.BT656 Slave
Mode in which the video input stream contains
EAV and SAV codes. In this case, proper HSYNC
and VSYNC timing is extracted automatically
without any inputs other than the V [7:0]. ITU
R.BT656 input data that is sampled with the lead­ing edge of CLK.

In addition, it is also possible to output HSYNC
and VSYNC signals when in ITU R.BT656 Slave
Mode.

4.2 Video Input Formatter

The Video Input Formatter translates YCbCr input
data into YUV information, when necessary, and
splits the luma and chroma information for filter­ing, scaling, and modulation.

4.3 Color Subcarrier Synthesizer

The subcarrier synthesizer is a digital frequency
synthesizer that produces the appropriate subcarri­er frequency for NTSC or PAL. The CS4954/5

generates the color burst frequency based on the
CLK input (27 MHz). Color burst accuracy and
stability are limited by the accuracy of the 27 MHz
input. If the frequency varies, then the color burst
frequency will also vary accordingly.

For environments in which the CLK input varies or
jitters unacceptably, a local crystal frequency refer­ence can be used on the XTAL_IN and
XTAL_OUT pins. In this instance, the input CLK is
continuously compared with the external crystal ref­erence input and the internal timing of the CS4954/5
is automatically adjusted so that the color burst fre­quency remains within tolerance.

Controls are provided for phase adjustment of the
burst to permit color adjustment and phase com­pensation. Chroma hue control is provided by the
CS4954/5 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP).

4.4 Chroma Path

The Video Input Formatter delivers 4:2:2 YUV
outputs to separate chroma and luma data paths.

The chroma output of the Video Input Formatter is
directed to a chroma low-pass 19-tap FIR filter.
The filter bandwidth is selected (or the filter can be
bypassed) via the CONTROL_1 Register. The
passband of the filter is either 650 kHz or 1.3 MHz
and the passband ripple is less than or equal to

0.05 dB. The stopband for the 1.3 MHz selection
begins at 3 MHz with an attenuation of greater than
35 dB. The stopband for the 650 kHz selection be­gins around 1.1 MHz with an attenuation of greater
than 20 dB.

The output of the chroma low-pass filter is connect­ed to the chroma interpolation filter in which up­sampling from 4:2:2 to 4:4:4 is accomplished.
Following the interpolation filter, the U and V
chroma signals pass through two independent vari-

NOTE 1. The FIELD pin (pin 9) remains an output pin in SLAVE mode. However, the FIELD pin state does not

toggle in SLAVE mode and its output state should be considered random.

12 DS278F6

CS4954 CS4955

able gain amplifiers in which the chroma amplitude
can be varied via the U_AMP and V_AMP 8-bit
host addressable registers.

The U and V chroma signals are fed to a quadrature
modulator in which they are combined with the
output from the subcarrier synthesizer to produce
the proper modulated chrominance signal.

The chroma is then interpolated by a factor of two
in order to operate the output DACs at twice the
pixel rate. The interpolation filters enable running
the DACs at twice the pixel rate which helps reduce
the sinx/x roll-off for higher frequencies and reduc­es the complexity of the external analog low pass
filters.

4.5 Luma Path

Along with the chroma output path, the CS4954/5
Video Input Formatter has a parallel luma data out­put to a digital delay line. The delay line is a digital
FIFO. The FIFO depth matches the clock period
delay associated with the more complex chroma
path. Brightness adjustment is also provided via the
8-bit BRIGHTNESS_OFFSET Register.

Following the luma delay, the data is passed
through an interpolation filter that has a program­mable bandwidth, followed by a variable gain am­plifier. The amplifier DC luma gain can be changed
using the the Y_AMP Register.

three pixel clocks. This variable delay is useful to
offset different propagation delays of the luma
baseband and modulated chroma signals. This ad­justable luma delay is available only on the
CVBS_1 output.

4.6 RGB Path and Component YUV Path

The RGB datapath has the same latency as the luma
and chroma path. Therefore all six simultaneous
analog outputs are synchronized. The 4:2:2 YCbCr
data is first interpolated to 4:4:4 and then interpo­lated to 27 MHz. The color space conversion is per­formed at 27 MHz. The coefficients for the color
space conversion conform to the ITU R.BT601
specifications.

After color space conversion, the amplitude of each
component can be independently adjusted via the
R_AMP, G_AMP, and B_AMP 8-bit host address­able registers. A synchronization signal can be add­ed to either one, two or all of the RGB signals. The
synchronization signal conforms to NTSC or PAL
specifications.

Some applications (e.g., projection TVs) require
analog component YUV signals. The chip provides
a programmable mode that outputs component
YUV data. Sync can be added to the luminance sig­nal. Independent gain adjustment of the three com­ponents is provided as well.

The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accom­plished by multiplexing, into the luma data path,
the different sync DC values at the appropriate
times. The digital sync generator takes horizontal
sync and vertical sync timing signals and generates
the appropriate composite sync timing (including
vertical equalization and serration pulses), blank­ing information, and burst flag. The sync edge rates
conform to RS-170A or ITU R.BT601 and ITU
R.BT470 specifications.

It is also possible to delay the luminance signal,
with respect to the chrominance signal, by up to

DS278F6 13

4.7 Digital to Analog Converters

The CS4954/5 provides six discrete 27 MHz DACs
for analog video. The default configuration is one
10-bit DAC for S-video chrominance, one 10-bit
DAC for S-Video luminance, one 10-bit DAC for
composite output, and three 10-bit DACs for RGB
outputs. All six DACs are designed for driving ei­ther low-impedance loads (double terminated
75 Ω) or high-impedance loads (double terminated
300 Ω). There are five different DAC configura­tions to choose from (see Table 1, below).

The DACs can be put into high-impedance mode
via host-addressable control register bits. Each of

CS4954 CS4955

DAC Pin # Mode 1 Mode 2 Mode 3 Mode 4 Mode 5

Y 48 Y Y Y CVBS_2 CVBS_2

C47CCC - -

CVBS 44 CVBS_1 CVBS_1 CVBS_1 CVBS_1 CVBS_1

R 39 R Cr (V) - R Cr (V)

G 40 G Y CVBS_2 G Y

B43BCb (U)- BCb (U)

Tab l e 1. DAC configuration Modes

the six DACs has its own associated DAC enable
bit. In the Disable Mode, the 10-bit DACs source
(or sink) zero current.

When running the DACs with a low-impedance
load, a minimum of three DACs must be powered
down. When running the DACs with a high-imped­ance load, all the DACs can be enabled simulta­neously.

For lower power standby scenarios, the CS4954/5
also provides power shut-off control for the DACs.
Each DAC has an associated DAC shut-off bit.

4.8 Voltage Reference

The CS4954/5 is equipped with an on-board volt­age reference generator (1.232 V) that is used by
the DACs. The internal reference voltage is accu­rate enough to guarantee a maximum of 3% overall
gain error on the analog outputs. However, it is
possible to override the internal reference voltage
by applying an external voltage source to the VREF
pin.

current modes are software selectable via a register
bit.

4.10 Host Interface

The CS4954/5 provides a parallel 8-bit data inter­face for overall configuration and control. The host
interface uses active-low read and write strobes,
along with an active-low address enable signal, to
provide microprocessor-compatible read and write
cycles. Indirect host addressing to the CS4954/5 in­ternal registers is accomplished via an internal ad­dress register that is uniquely accessible via bus
write cycles for the device when the host address
enable signal is asserted.

The CS4954/5 also provides an I²C-compatible se­rial interface for device configuration and control.
This port can operate in standard (up to 100 kb/sec)
or fast (up to 400 kb/sec) modes. When in I²C
mode, the parallel data interface pins, PDAT [7:0],
can be used as a general purpose I/O port controlled
by the I²C interface.

4.9 Current Reference

The DAC output current-per-bit is derived in the
current reference block. The current step is speci­fied by the size of resistor placed between the ISET
current reference pin and electrical ground.

4.11 Closed Caption Services

The CS4954/5 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 cap­tioning can be generated and enabled independent­ly via a set of control registers. When enabled,
clock run-in, start bit, and data bytes are automati-

A 4 kΩ resistor needs to be connected between
ISET pin and GNDA. The DAC output currents are
optimized to drive either a doubly terminated 75 W
load (low impedence mode) or a double terminated

cally inserted at the appropriate video lines. A con­venient interrupt protocol simplifies the software
interface between the host processor and the
CS4954/5.

300 Ω load (high impedence mode). The 2 output

14 DS278F6

CS4954 CS4955

4.12 Teletext Services

The CS4954/5 encodes the most common teletext
formats, such as European Teletext, World Stan­dard Teletext (PAL and NTSC), and North Ameri­can Teletext (NABTS).

Teletext data can be inserted in any of the TV lines
(blanking lines as well as active lines). In addition
the blanking lines can be individually allocated for
Teletext instantiation.

The input timing for teletext data is user program­mable. See the section Teletext Services for further
details.

Teletext data can be independently inserted on ei­ther one or all of the CVBS_1, CVBS_2, or S-video
signals.

4.13 Wide-Screen Signaling Support and

CGMS

Insertion of wide-screen signal encoding for PAL
and NTSC standards is supported and CGMS
(Copy Generation Management System) for NTSC
in Japan. Wide-screen signals are inserted in lines
23 and 336 for PAL, and lines 20 and 283 for
NTSC.

4.14 VBI Encoding

This chip supports the transmission of control sig­nals in the vertical blanking time interval according
to SMPTE RP 188 recommendations. VBI encoded
data can be independently inserted into any or all of
CVBS_1, CVBS_2 or S-video signals.

4.15 Control Registers

The control and configuration of the CS4954/5 is
accomplished primarily through the control regis­ter block. All of the control registers are uniquely
addressable via the internal address register. The
control register bits are initialized during device
RESET.

See the Programming section of this data sheet for
the individual register bit allocations, bit operation­al descriptions, and initialization states.

4.16 Testability

The digital circuits are completely scanned by an
internal scan chain, thus providing close to 100%
fault coverage.

5. OPERATIONAL DESCRIPTION

5.1 Reset Hierarchy

The CS4954/5 is equipped with an active low asyn­chronous reset input pin, RESET. RESET is used to
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4954/5 device RESET
and power-on signal timing requirements and re­strictions.

While the RESET pin is held low, the host interface
in the CS4954/5 is disabled and will not respond to
host-initiated bus cycles. All outputs are valid after
a time period following RESET pin low.

A device RESET initializes the CS4954/5 internal
registers to their default values as described by Ta­ble 9, Control Registers. In the default state, the
CS4954/5 video DACs are disabled and the device
is internally configured to provide blue field video
data to the DACs (any input data present on the
V [7:0] pins is ignored at this time). Otherwise, the
CS4954/5 registers are configured for NTSC-M
output and ITU R.BT601 output timing operation.
At a minimum, the DAC Registers (0x04 and 0x05)
must be written (to enable the DACs) and the
IN_MODE bit of the CONTROL_0 Register
(0x01) must be set (to enable ITU R.BT601 data in­put on V [7:0]) for the CS4954/5 to become opera­tional after RESET.

DS278F6 15

CS4954 CS4955

NTSC 27MHz Clock Count

PAL 27MHz Clock Cou nt

CLK

HSYNC (input)

V[7:0]

(SYNC_DLY=0)

V[7:0]

(SYNC_DLY=1)

1683

1682

1703

1702

Y

Cr

active pixel

• • •

Y

Cb

active pixel

#719

168616851684

1706

17051704

Y Cb Y Cr Y

#720

Cr

Y

active pixel

#720

• • •

• • •

1716

1728

Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing

5.2 Video Timing

5.2.1 Slave Mode Input Interface

In Slave ITU R.BT601 (not ITU-R.BT656 input)
Mode, the CS4954/5 receives signals on VSYNC
and HSYNC as inputs. Slave Mode is the default
following RESET and is changed to Master Mode
via a control register bit (CONTROL_0 [4]). The
CS4954/5 is limited to ITU R.BT601 horizontal
and vertical input timing. All clocking in the
CS4954/5 is generated from the CLK pin. In Slave
Mode, the Sync Generator uses externally provided
horizontal and vertical sync signals to synchronize
the internal timing of the CS4954/5. Video data that
is sent to the CS4954/5 must be synchronized to the
horizontal and vertical sync signals. Figure 4 illus­trates horizontal timing for ITU R.BT601 input in
Slave Mode. Note that the CS4954/5 expects to re­ceive the first active pixel data on clock cycle 245

1

23 128

1

23 128

horizontal blanking

horizontal blanking active pixel#1active pixel

• • •

• • •

129

129

• • •

• • •

244 245

264 265

246 247

266 267

active pixel#1active pixel

Cb

248

268

#2

Y

Cr

(NTSC) when CONTROL_2 Register (0x02) bit
SYNC_DLY = 0. When SYNC_DLY = 1, it expects
the first active pixel data on clock cycle 246 (NTSC).

5.2.2 Master Mode Input Interface

The CS4954/5 defaults to Slave Mode following
RESET high but can be switched into Master Mode
via the MSTR bit in the CONTROL_0 Register
(0x00). In Master Mode, the CS4954/5 uses the
VSYNC, HSYNC and FIELD device pins as out­puts to schedule the proper external delivery of dig­ital video into the V [7:0] pins. Figure 5 illustrates
horizontal timing for the CCIR601 input in Master
Mode.

The timing of the HSYNC
the PROG_HS Registers (0x0D, 0x0E). HSYNC
can be delayed by one full line cycle. The timing of
the VSYNC output is also selectable in the

output is selectable in

#2

NTSC 27MHz Clock Count

PAL 27MHz Clock Count

CLK

HSYNC (ou tpu t)

CB (output)

V[7:0]

1682

1702

Y

• • •

1683

1703

Cr

Y Cb Y Cr Y

active pixel

#720

168616851684

17051704

1706

• • •

• • •

1716

1728

1

23 128

1

23 128

horizontal blank ing

• • •

• • •

129

129

• • •

• • •

244 245

264 265

246 247

266 267

active pixel#1active pixel

248

268

#2

Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing

16 DS278F6

CS4954 CS4955

PROG_VS Register (0x0D). VSYNC can be de­layed by thirteen lines or advanced by eighteen lines.

5.2.3 Vertical Timing

The CS4954/5 can be configured to operate in any
of four different timing modes: PAL, which is 625
vertical lines, 25 frames per second interlaced;
NTSC, which is 525 vertical lines, 30 frames per
second interlaced; and either 625 or 525 line Pseu­do-Progressive Scan (See “Progressive Scan” on

page 18). These modes are selected in the

CONTROL_0 Register (0x00).

The CS4954/5 conforms to standard digital decom­pression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
TV display. 240 active lines total per field are pro­cessed for NTSC, and 288 active lines total per
field are processed for PAL. Frame vertical dimen­sions are 480 lines for NTSC and 576 lines for
PAL. Table 2 specifies active line numbers for both
NTSC and PAL. Refer to Figure 6 for HSYNC,
VSYNC and FIELD signal timing.

Mode Field Active Lines

NTSC 1, 3;

2, 4

PAL 1, 3, 5, 7;

2, 4, 6, 8
NTSC Progressive-Scan NA 22-261
PAL Progressive-Scan NA 23-310

Table 2. Ver t i c a l T im in g

22-261;

285-524

23-310;

336-623

5.2.4 Horizontal Timing

HSYNC is used to synchronize the horizontal-in­put-to-output timing in order to provide proper hor­izontal alignment. HSYNC defaults to an input pin
following RESET but switches to an output in Mas­ter Mode (CONTROL_0 [4] = 1). Horizontal tim­ing is referenced to HSYNC
active video lines, digital video input is to be ap­plied to the V [7:0] inputs for 244 (NTSC) or for
264 (PAL) CLK periods following the leading

transitioning low. For

(falling) edge of HSYNC if the PROG_HS Regis­ters are set to default values.

5.2.5 NTSC Interlaced

The CS4954/5 supports NTSC-M, NTSC-J and
PAL-M modes where there are 525 total lines per
frame, two fixed 262.5-line fields per frame and 30
frames occurring per second. NTSC interlaced ver­tical timing is illustrated in Figure 7. Each field
consists of one line for closed caption, 240 active
lines of video, plus 21.5 lines of blanking.

VSYNC field one transitions low at the beginning
of line four and will remain low for three lines or
2574 pixel cycles (858 × 3). The CS4954/5 exclu­sively reserves line 21 of field one for closed cap­tion insertion. Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 240
lines beginning on active video lines 22 and con­tinuing through line 261. VSYNC field two transi­tions low in the middle of line 266 and stays low for
three line-times and transitions high in the middle
of line 269. The CS4954/5 exclusively reserves line
284 of field two for closed caption insertion. Video
input on the V [7:0] pins is expected between lines
285 through line 525.

5.2.6 PAL Interlaced

The CS4954/5 supports PAL modes B, D, G, H, I,
N, and Combination N, in which there are 625 total
lines per frame, two fixed 312.5 line fields per
frame, and 25 total frames per second. Figure 8 il­lustrates PAL interlaced vertical timing. Each field
consists of 287 active lines of video plus 25.5 lines
of blanking.

VSYNC
will remain low for 2.5 lines or 2160 pixel cycles
(864 × 2.5). Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 287
lines beginning on active video line 24 and continu­ing through line 310.

Field two begins with VSYNC transitioning low
after 312.5 lines from the beginning of field one.

will transition low to begin field one and

DS278F6 17

NTSC Vertical Timing (odd field)

CS4954 CS4955

Line

HSYNC

VSYNC

FIELD

Line

HSYNC

VSYNC

FIELD

Line

HSYNC

VSYNC

FIELD

3

NTSC Vertical Timing (even field)

264 265

PAL Vertical Timing (odd field)

265 1 2

4

5 6

266 267 268 269 270

7 8 9

3 4 5 6

10

271

7

PAL Vertical Timing (even field)

Line

HSYNC

VSYNC

FIELD

311 312

313 314 315 316 317

Figure 6. Vertical Timing

VSYNC stays low for 2.5 line-times and transitions
high with the beginning of line 315. Video input on
the V [7:0] pins is expected between line 336
through line 622.

5.2.7 Progressive Scan

The CS4954/5 supports a pseudo-progessive scan
mode for which “odd” and “even” numbered line
information is presented in “odd” numbered line
positions by varying the vertical blanking timing.
This preserves precise MPEG-2 frame rates of 30
and 25 frames per second. This mode is in contrast
to other digital video encoders, which commonly
support progressive scan by repetitively displaying

318

a 262 line field (524/525 lines for NTSC). The
common method is flawed: over time, the output
display rate will overrun a system-clock-locked
MPEG-2 decompressor and display a field twice
every 8.75 seconds.

5.2.8 NTSC Progressive Scan

VSYNC will transition low at line four to begin
field one and will remain low for three lines or
2574 pixel cycles (858 × 3). NTSC interlaced tim­ing is illustrated in Figure 9. In this mode, the
CS4954/5 expects digital video input at the V [7:0]
pins for 240 lines beginning on active video line 22
and continuing through line 261.

18 DS278F6