Cirrus Logic CS4928-CL, CS4927-CL, CS4926-CL, CS4925-CL, CS4924-CL Datasheet

...

CS4923/4/5/6/7/8/9

Multi-Channel Digital Audio Decoders

l CS4923/4/5/6/7/8 features

— Optional Virtual 3D Output — Simulated Surround and Programmable Effects — Real Time Autodetection of Dolby Digital

DTS

, MPEG Multi-Channel and PCM

— Flexible 6-channel master or slave output

l CS4923/4/5/6/7/8/9 features

— IEC60958/61937 transmitter for co mpressed-

data or linear-PCM output — Dedicated 8 kilobyte input buffer — DAC clock via analog phase-locked loop — Dedicated byte wide or serial host interface — Multiple compressed data input modes — PES layer decode for A/V synchronization — 96-kHz-capable PCM I/O, master or slave — Optional external memory and auto-boot — +3.3-V CMOS low-power, 44-pin package

l CS4923/4/5/6 features

— Capable of Dolby Digital® Group A Performance — Dolby bass manager and crossover filters — Dolby Surround Pro Logic

l CS4925/7: MPEG-2 Multi-Channel Decode r l CS4926/8: DTS Multi-Channel Decoder l CS4929: AAC 2-Channel (Low Complexity)

Decoding

and MPEG-2 Stereo Decoder

Description

The CS4923/4/5/6/7/8 is a family of multi-channel digital audio decoders, with the exception of the CS4929 as the only stereo digital audio decoder. The CS4923/4/5/6 are designed for Dolby Digital and MPEG-2 Stereo decoding. In addition the CS4925 adds MPEG-2 multi-channel decoding capability and the CS4926 provides DTS decoding. The CS4927 is an MPEG-2 multi-channel decoder and the CS4928 is a DTS multi-channe l decoder. The CS492 9 is an AAC 2-channel and MPEG-2 stereo decoder. Each one of the CS4923/4/5/6/7/8/9 provides a complete and flexible solution for multi-channel (or stereo in the case of the CS4929) audio decoding in home A/V receiver/amplifiers, DVD movie players, out-board decoders, laser- disc players, HDTV sets, head-end decoders, set-top boxes, and similar products.

Cirrus Logic’s Crystal Audio Divisio n provides a complete set of audio decoder and auxiliary audio DSP application programs for various applications. For all complementary analog and digital audio I/O, Crystal Audio also provides a complete set of high-quality audio peripherals including: multimedia CODECs, stereo A/D and D/A converters and IEC60958 interfaces. Of special note, the CS4226 is a complementary CODEC providing a digital receiver, stereo A/D converters, and six 20-bit DACs in o ne p ackage.

ORDERING INFORMATION

CS4923xx-CL 44-pin PLCC (xx = ROM revision) CRD4923 Reference design with CS4226 CDB4923 Evaluation board

EMAD7:0,

Digital Audio

Input

PLL

Clock Manager

FILT1

CMPDAT,

SDATAN2

CMPCLK,

SCLKN2

CMPREQ,

LRCLKN2

SCLKN1,

STCCLK2 LRCLKN1 SDATAN1

CLKIN

CLKSEL

RESET

Compressed

Data Input

Interface

FILT2 AGND

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

DAT A7:0,

GPIO7:0

Framer

Shifter

Input Buffer

Controller

RAM Input

Buffer

R/W,

EMOE

GPIO11

DSP Processing

Program

Memory

Program

Memory

DGND[3:1] VD[3:1]

SCDIO,

SCDOUT,

ROM

PSEL,

EMWR

GPIO10

Parallel or Serial Host Interface

24-Bit

RAM

RAM Data

Memory

ROM Data

Memory

STC

GPIO9

A0,

SCCLK

RAM

Output

Buffer

A1,

SCDIN

ABOOT INTREQ

EXTMEM

GPIO8

Output

Formatter

DD DC

MCLK SCLK LRCLK

AUDAT A[2.0]

XMT958

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

AUG ‘99

DS262F2

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

ABSOLUTE MAXIMUM RATINGS ............................................................................................4

RECOMMENDED OPERATING CONDITIONS........................................................................4

DIGITAL D.C. CHARACTERISTICS..........................................................................................4

POWER SUPPLY CHARACTERISTICS...................................................................................4

SWITCHING CHARACTERISTICS—RESET............................................................................5

SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK........................................................6

SWITCHING CHARACTERISTICS—CLKIN .............................................................................7

SWITCHING CHARACTERISTICS—INTEL SWITCHING CHARACTERISTICS—MOTOROLA

SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT................................................16

SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT............................................18

2. FAMILY OVERVIEW ..............................................................................................................20

2.1 Multi-channel Decoder Family of Parts ............................................................................21

2.2 Document Strategy ..........................................................................................................21

2.2.1 Hardware Documentation ...............................................................................22

2.2.2 CS4923/4/5/6/7/8/9 Application Code User’s Guides ..................................... 22

2.3 Using the CS4923/4/5/6/7/8/9 ..........................................................................................22

3. TYPICAL CONNECTION DIAGRAMS ...................................................................................23

3.1 Multiplexed Pins ...............................................................................................................23

3.2 Termination Requirements ...............................................................................................24

3.3 Phase Locked Loop Filter ................................................................................................24

4. POWER ..................................................................................................................................31

4.1 Decoupling .......................................................................................................................31

4.2 Analog Power Conditioning ..............................................................................................31

4.3 Pads .................................................................................................................................31

5. CLOCKING ............................................................................................................................. 32

6. CONTROL .............................................................................................................................. 33

6.1 Boot and Control Mode Overview ....................................................................................33

6.2 Parallel Host Interface ......................................................................................................34

6.2.1 Intel Parallel Host Mode ..................................................................................34

6.2.2 Motorola Parallel Host Mode ...........................................................................36

6.3 SPI Serial Host Interface ..................................................................................................36

6.3.1 SPI Write .........................................................................................................37

6.3.2 SPI Read .........................................................................................................37

CS4923/4/5/6/7/8/9

HOST MODE.....................................................8

HOST MODE ........................................10

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Dolby, Dolby Digital, and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.

C is a registered trademark of Philips Semiconductor.

All other names are trademarks, registered trademarks, or service marks of their respective companies. Preliminary product information describes products whi c h are i n production, but for wh ic h ful l characterization data i s not yet available. Advance p roduct infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accur ate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” wit hout warran ty of

any kind (express or implied) . No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the propert y of Cirru s Logic, Inc. and implie s no licen se under patents, copyri ghts, trademarks, or tr ade secrets. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electro nic, mechanical, photographic, or otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logi c websi t e or di sk may be print ed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS262F2

CS4923/4/5/6/7/8/9

6.4 I2C Serial Host Interface .................................................................................................. 39

6.4.1 I

6.4.2 I

6.5 External Memory .............................................................................................................. 41

6.5.1 External Memory and Autoboot ...................................................................... 43

7. DIGITAL INPUT & OUTPUT .................................................................................................. 44

7.1 Digital Audio Formats ....................................................................................................... 44

7.2 Digital Audio Input Port ....................................................................................................46

7.3 Compressed Data Input Port ........................................................................................... 46

7.4 Parallel Digital Audio Data Input ......................................................................................46

7.5 Digital Audio Output Port ................................................................................................. 47

7.5.1 IEC60958 Output ............................................................................................ 48

8. PIN DESCRIPTIONS .............................................................................................................. 49

9. PACKAGE DIMENSIONS ...................................................................................................... 54

LIST OF FIGURES

Figure 1. RESET Timing.................................................................................................................. 5

Figure 2. Serial Compressed Data Timing ....................................................................................... 6

Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7

Figure 4. CLKIN with CLKSEL = VD = PLL Bypass......................................................................... 7

Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9

Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9

Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11

Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11

Figure 9. SPI Control Port Timing................................................................................................... 13

Figure 10. I

Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17

Figure 12. Digital Audio Output, Data and Clock Timing................................................................19

Figure 13. I2C Control..................................................................................................................... 25

Figure 14. I2C Control with External Memory.................................................................................26

Figure 15. SPI Control.................................................................................................................... 27

Figure 16. SPI Control with External Memory ................................................................................ 28

Figure 17. Intel Parallel Control Mode............................................................................................29

Figure 18. Motorola Parallel Control Mode..................................................................................... 30

Figure 19. SPI Timing..................................................................................................................... 38

Figure 20. I

Figure 21. External Memory Interface............................................................................................42

Figure 22. Run-Time Memory Access............................................................................................42

Figure 23. Autoboot Timing Diagram..............................................................................................43

Figure 24. I

Figure 25. Left Justified Format...................................................................................................... 45

Figure 26. Right Justified................................................................................................................ 45

Figure 27. Multi-Channel Format (M == 20)................................................................................... 45

C Write ......................................................................................................... 39

C Read ......................................................................................................... 39

C Control Port Timing................................................................................................. 15

C Timing .....................................................................................................................40

S Format..................................................................................................................... 45

LIST OF TABLES

Table 1. Silicon Revisions ..............................................................................................................20

Table 2. Host Modes ......................................................................................................................33

Table 3. Host Memory Map............................................................................................................ 34

Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34

Table 5. Parallel Input/Output Registers......................................................................................... 35

Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................36

Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36

Table 8. I

Table 9. Memory Interface Pins...................................................................................................... 41

Table 10. Digital Audio Input Port................................................................................................... 46

Table 11. Compressed Data Input Port.......................................................................................... 46

Table 12. Digital Audio Output Port................................................................................................ 47

Table 13. MCLK/SCLK Master Mode Ratios.................................................................................. 47

DS262F2 3

C Serial Mode Pin Assignments ....................................................................................39

CS4923/4/5/6/7/8/9

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND = 0 V; all voltages with respect to 0 V)

Parameter Symbol Min Max Unit

DC power supplies: Positive digital

Positive analog

||VA| – |VD||

Input current, any pin except supplies I Digital input voltage V Ambient operating temperature (power applied) T Storage temperature T

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND = 0 V; all voltages with respect to 0 V)

IND

Amax

stg

–0.3 –0.3

–0.3 5.5 V

–55 125 –65 150

3.63

0.4

10 mA

V V V

Parameter Symbol Min Typ Max Unit

DC power supplies: Positive digital

Positive analog

||VA| – |VD||

Ambient operating temperature T

3.13

0-70°C

3.3

DIGITAL D.C. CHARACTERISTICS

(TA = 25°C; VA, VD[3:1] = 3.3 V±5%; measurements performed under static conditions.)

Parameter Symbol Min Typ Max Unit

High-level input voltage V Low-level input voltage V High-level output voltage at I Low-level output voltage at I Input leakage current I

= –4.0 mA V

= 4.0 mA V

IL OH OL

2.0 - - V

--0.8V

VD×0.9 - - V

--VD

--1.0µA

POWER SUPPLY CHARACTERISTICS

(TA = 25°C; VA, VD[3:1] = 3.3 V±5%; measurements performed under operating conditions)

Parameter Symbol Min Typ Max Unit

Power supply current: Digital operating: VD[3:1]

Analog operating: VA

225

3.47

0.4

0.1 V

435

V V V

mA mA

4 DS262F2

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—RESET

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)z

Parameter Symbol Min Max Unit

RESET

minimum pulse width low All bidirectional pins high-Z after RESET Configuration bits setup before RESET Configuration bits hold after RESET

high

RESET

RD, WR,

PSEL, ABOOT

All Bidirectional

Outputs

low

high

rst2z

rstl

T T T

rsthld

rstl rst2z rstsu

rstsuTrsthld

100 - ns

-50ns 50 - ns 15 - ns

Figure 1. RESET Timing

DS262F2 5

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Unit

Serial compressed data clock CMPCLK period T CMPDAT setup before CMPCLK high T CMPDAT hold after CMPCLK high T

CMPCLK

CMPDAT

cmpclk

cmpsu cmphld

37 - ns

5-ns 3-ns

cmpsu

cmpclk

cmphld

Figure 2. Serial Compressed Data Timing

6 DS262F2

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—CLKIN

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Unit

CLKIN period for internal DSP clock mode T CLKIN high time for internal DSP clock mode T CLKIN low time for internal DSP clock mode T CLKIN period for external DSP clock mode T CLKIN high time for external DSP clock mode T CLKIN low time for external DSP clock mode T

CLKIN

clki

clkih

clkil clke

clkeh

clkel

20 3800 ns

8ns 8ns

20 25 ns

9ns 9ns

clkih

clki

clkil

Figure 3. CLKIN with CLKSEL = VSS = PLL Enable

CLKIN

clkeh

Figure 4. CLKIN with CLKSEL = VD = PLL Bypass

clke

clkel

DS262F2 7

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—INTEL® HOST MODE

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Unit

Address setup before CS Address hold time after CS Delay between RD Data valid after CS

and RD low for read (Note 1)

CS Data hold time after CS Data high-Z after CS

or RD high to CS and RD low for next read (Note 1)

or RD high to CS and WR low for next write (Note 1)

CS Delay bet ween WR Data setup before CS CS

and WR low for write (Note 1)

Data hold after CS

or WR high to CS and RD low for next read (Note 1)

or WR high to CS and WR low for next write (Note 1)

and RD low or CS and WR low

and RD low or CS and WR low then CS low or CS then RD low and RD low

or RD high

or RD high (Note 2)

then CS low or CS then WR low

or WR high

T T

T T T T

ias iah

icdr

idd

irpw

idhr idis

ird irdtw icdw

idsu

iwpw

idhw iwtrd

iwd

5-ns 5-ns 0

-20ns

DCLK + 10 - ns

5-ns

-15ns 2*DCLK + 10 - ns 2*DCLK + 10 - ns

20 - ns

DCLK + 10 - ns

5-ns 2*DCLK + 10 - ns 2*DCLK + 10 - ns

∞

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows: External CLKIN Mode:

DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot

Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see

CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information)

2. This specification is characterized but not production tested.

8 DS262F2

A1:0

DATA7:0

CS4923/4/5/6/7/8/9

iah

ias

icdr

Figure 5. Intel Parallel Host Mode Read Cycle

idhr

idd

idis

irpw

ird

irdtw

A1:0

DATA7:0

iah

ias

icdw

iwpw

idhw

idsu

iwd

iwtrd

Figure 6. Intel Parallel Host Mode Write Cycle

DS262F2 9

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Unit

Address setup before CS Address hold time after CS Delay between DS Data valid after CS

and DS low for read (Note 3)

CS Data hold time after CS Data high-Z after CS

or DS high to CS and DS low for next read (Note 3)

or DS high to CS and DS low for next write (Note 3)

CS Delay between DS Data setup before CS CS

and DS low for write (Note 3)

setup before CS or DS low

R/W

hold time after CS or DS high

R/W Data hold after CS

or DS high to CS and DS low with R/W high for next read

and DS low

then CS low or CS then DS low

and DS low with R/W high

or DS high after read

or DS high low after read (Note 4)

then CS low or CS then DS low

or DS high

(Note 3)

or DS high to CS and DS low for next write (Note 3)

mas

mah

mcdr

mdd

mrpw

mdhr

mdis

mrdtw

mcdw

mdsu

mwpw

mrwsu

mrwhld

mdhw

mwtrd

mwd

mrd

5-ns

-20ns

DCLK + 10 - ns

5-ns

-15ns 2*DCLK + 10 - ns 2*DCLK + 10 - ns

20 - ns

DCLK + 10 - ns

5-ns 5-ns 5-ns

2*DCLK + 10 - ns

∞

Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows: External CLKIN Mode:

DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot

Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)

4. This specification is characterized but not production tested.

10 DS262F2

A1:0

DATA7:0

R/W

mah

mrwsu

mas

mcdr

mdhr

mdd

mdis

mrpw

mrd

Figure 7. Motorola Parallel Host Mode Read Cycle

CS4923/4/5/6/7/8/9

mrwhld

mrdtw

A1:0

mas

mah

DATA7:0

mdsu

mdhw

mcdw

mwpw

mrwhld

R/W

mrwsu

mwd

mwtrd

Figure 8. Motorola Parallel Host Mode Write Cycle

DS262F2 11

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—SPI CONTROL PORT

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Units

SCCLK clock frequency (Note 5) f

falling to SCCLK rising t

CS Rise time of SCCLK line (Note 11) t Fall time of SCCLK lines (Note 11) t SCCLK low time t SCCLK high time t Setup time SCDIN to SCCLK rising t Hold time SCCLK rising to SCDIN (Note 6) t Transition time from SCCLK to SCDOUT valid (Note 7) t Time from SCCLK rising to INTREQ Rise time for INTREQ

Hold time for INTREQ

from SCCLK rising (Note 9, 11) t

Time from SCCLK falling to CS

rising (Note 8) t

(Note 8) t

rising t High time between active CS Tim e from CS

rising to SCDOUT high-Z (Note 11) t

sck css

r f

scl

sch

cdisu

cdih

scdov

scrh

scrl

sccsh

csht

cscdo

-2000kHz

20 - ns

-50ns

-50ns 150 - ns 150 - ns

50 - ns 50 - ns

-40ns

-200ns

-(Note

10)

0-ns

20 - ns

200 - ns

10 ns

Notes: 5. The specification f

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.

7. SCDOU T sh oul d

8. INTREQ

goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

second-to-last bit of the last byte of data during a read operation as shown.

9. If INTREQ

goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ this condition as a new read transaction. Raise chip select to end the current read transaction and then drop it, followed by the 7-bit address and the R/W

10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time.

11. This time is by design and not tested.

indicates the maximum speed of the hardware. The system designer should be

sck

not

be sampled during this time period.

goes active low again. Treat

bit (set to 1 for a read) to start a new read transaction.

12 DS262F2

DS262F2 13

sccsh

SCCLK

SCDIN

SCDOUT

INTR EQ

css

cscdo

csht

tri-state

scl

cdisu

sch

cdih

A0A6 A5

R/W

scdov

MSB

scdov

scrh

LSB

scrl

CS4923/4/5/6/7/8/9

Figure 9. SPI Control Port Timing

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS— I2C® CONTROL PORT

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Units

SCCLK clock frequency (Note 12) f Bus free time between transmissions t Start-condition hold time (prior to first clock pulse) t Clock low time t Clock high time t SCDIO setup time to SCCLK rising t SCDIO hold time from SCCLK falling (Note 13) t Rise time of SCCLK (Note 14), (Note 18) t Fall time of SCCLK (Note 18) t Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK t Time from SCCLK falling to SCDIO valid during read operation t Time from SCCLK rising to INTREQ Hold time for INTREQ

from SCCLK rising (Note 16) t

rising (Note 15) t

Rise time for INTREQ

Setup time for stop condition t

scl buf

hdst

low

high

sud

hdd

r f

sca

scsdv

scrh

scrl

susp

400 kHz

4.7

4.0

1.2

1.0

250 ns

50 ns

300 ns

40 ns 40 ns

200 ns

0ns

(Note

17)

4.7

Notes: 12. The specification f

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

13. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by design and not tested.

14. This rise time is shorter than that recommended by the I section on SCP communications.

15. INTREQ

goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

last data bit of the last byte of data during a read operation as shown.

16. If INTREQ

goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ this condition as a new read transaction. Send a new start condition followed by the 7-bit address and the R/W

bit (set to 1 for a read). This time is by design and is not tested.

17. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time.

18. This time is by design and not tested.

indicates the maximum speed of the hardware. The system designer should be

scl

C specifications. For more information, see the

goes active low again. Treat

14 DS262F2

DS262F2 15

SCDIO

SCCLK

INTREQ

stop start

buf

hdst

low

sud

hddthigh

rtf

Figure 10. I2C Control Port Timing

scsdv

MSBA0A6 A5

ACK

sca

R/W

780

scrh

LSB

ACK

scrl

stop

susp

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT

(TA = 25°C; VA, VD = 3.3 V±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter Symbol Min Max Unit

SCLKN1(2) period for both Master and Slave mode (Note 19) T

sclki

SCLKN1(2) duty cycle for Master and Slave mode (Note 19) 45 55 % Master Mode (Note 19,20) LRCLKN1(2) delay after SCLKN1(2) transition (Note 21) T

SDATAN1(2) setup to SCLKN1(2) transition (Note 22) T SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) T

lrds

sdsum

sdhm

Slave Mode (Note 23) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition T

Time from LRCLKN1(2) transition to SCLKN1(2) active edge T SDATAN1(2) setup to SCLKN1(2) transition (Note 22) T SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) T

stlr

lrts

sdsus

sdhs

Notes: 19. Master mode timing specifications are characterized, not production tested.

20. Master mode is defined as the CS4923 driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed.

21. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid.

22. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid.

23. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source.

40 - ns

-10ns

10 - ns

5-ns

10 - ns 10 - ns

5-ns 5-ns

16 DS262F2

SCLKN1 SCLKN2

LRCLKN1 LRCLKN2

SDATAN1 SDATAN2

MASTER MODE

lrds

sdsumTsdhm

CS4923/4/5/6/7/8/9

sclki

SLAVE MODE

SCLKN1 SCLKN2

lrts

LRCLKN1 LRCLKN2

sdsus

sdhs

SDATAN1 SDATAN2

Figure 11. Digital Audio Input, Data and Clock Timing

sclki

stlr

DS262F2 17

+ 39 hidden pages

Cirrus Logic CS4928-CL, CS4927-CL, CS4926-CL, CS4925-CL, CS4924-CL Datasheet

TABLE OF CONTENTS

Contacting Cirrus Logic Support

LIST OF FIGURES

LIST OF TABLES

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

DIGITAL D.C. CHARACTERISTICS

POWER SUPPLY CHARACTERISTICS

SWITCHING CHARACTERISTICS—RESET

Figure 1. RESET Timing

SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK

Figure 2. Serial Compressed Data Timing

SWITCHING CHARACTERISTICS—CLKIN

Figure 3. CLKIN with CLKSEL = VSS = PLL Enable

Figure 4. CLKIN with CLKSEL = VD = PLL Bypass

SWITCHING CHARACTERISTICS—INTEL® HOST MODE

Figure 5. Intel Parallel Host Mode Read Cycle

Figure 6. Intel Parallel Host Mode Write Cycle

SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE

Figure 7. Motorola Parallel Host Mode Read Cycle

Figure 8. Motorola Parallel Host Mode Write Cycle

Figure 9. SPI Control Port Timing

Figure 10. I2C Control Port Timing

SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT

Figure 11. Digital Audio Input, Data and Clock Timing