Cirrus Logic CS492, CS493 Series, CS49300, CS4923 Series Manual
CDB4923
CDB49300
Evaluation Board for CS4923/CS49300 Families
Features
l CDB4923 demonstrates 5.1 channel decode
capability of the CS4923 family
l CDB49300 demonstrat es 5.1 chan ne l
decode capability of CS49300 family
l 6 discrete analog outputs driven by CS4340
DACs
l 4 S/PDIF optical outputs
l Accepts analog input, S/PDIF digital input,
Bursty compressed data
l Discrete PLL which can provid e multiple
sampling frequencies
l Interfaces to a personal computer through
the parallel port
l Stake headers provide convenient location
for direct wiring to control signals from offboard microcontroller
l Interface for external memory card
l Digital and analog patch areas
I
Description
The CDB4923 and CDB49300 customer development
boards provide the means to fully evaluate the
CS4923/4/5/6/7/8 and C S49300 family of audio d ecoders. Compressed data can be delivered in IEC61937
format via the S/PDIF port and in bursty mode via the PC
interface. PCM data can be accepted through the digital
input connectors or from the on-board ADC. Six channels of audio are provided on the six analog outputs and
on three optical S/PDIF transmitters. CLKIN for the DSP
can be derived either from the on- boa rd osc illa tor or the
external PLL. MCLK can be extracted from incoming
S/PDIF streams, generated with the external PLL, or
mastered by the audio decoder.
The CDB4923/300 inc orporates a Crystal Multic hannel
Audio Decoder, the CS4340 24-Bit Audio D/A Converter,
the CS8414 Digital Audio Interface Receiver, the
CS8404A Digital Audio Interface Transmitter, and the
CS5334 20-Bit Stereo A/D Converter.
ORDERING INFORMATION
CDB4923 Evaluation Board
CDB49300 Evaluation Board
Digital Input
CS8404A CS8404A CS8404A
DIGITALSOUND
CRYSTAL
PROCESSING
RESET
Control
Interface
™
®
CS8414
PLL
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Digital Output
CS4340
+2.5V
+3.3V
CS492x
CS493xx
PLD
OSC
Patch Area
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
CS4340
CS4340
CS5334
Analog
Output
Stereo
Analog In
JAN ‘00
DS262DB2
1
TABLE OF CONTENTS
1. CDB4923 VS. CDB49300 .........................................................................................................5
1.1 DSP Power ........................................................................................................................ 5
1.2 DSP PLL Filter ...................................................................................................................5
2. OPERATION .............................................................................................................................5
2.1 Power Requirements .........................................................................................................6
2.2 Dolby‚ Considerations ........................................................................................................ 7
3. DIGITAL SIGNAL PROCESSOR ............................................................................................. 7
3.1 Control Signals ...................................................................................................................7
3.2 External Memory ................................................................................................................8
4. CONTROL ................................................................................................................................. 8
5. DATA SELECTION ...................................................................................................................9
5.1 Provided Mode .................................................................................................................10
5.1.1 Control .................................................................................................................10
5.1.2 Data .....................................................................................................................10
5.1.3 Audio Clocking ....................................................................................................12
5.2 External Mode ..................................................................................................................12
6. CLOCKING ............................................................................................................................. 14
6.1 DSP Clock ........................................................................................................................14
6.2 MCLK ............................................................................................................................... 15
6.3 LRCLK and SCLK ............................................................................................................ 15
CDB4923 CDB49300
7. INPUT ...................................................................................................................................... 16
7.1 Analog Input .....................................................................................................................16
7.2 Digital Input ...................................................................................................................... 16
8. OUTPUT .................................................................................................................................. 17
8.1 Analog Output ..................................................................................................................17
8.2 Analog Output Protection Circuitry ...................................................................................17
8.3 Digital Output ................................................................................................................... 17
9. APPENDIX A: SCHEMATICS ......................................................................................18
10. APPENDIX D: BILL OF MATERIALS ..................................................................................34
11. APPENDIX E: EXTERNAL MEMORY SCHEMATICS .....................................................37
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby is a registered trademark of Dolby Laboratories Licensing Corporation
DTS is a registered trademark of DTS, Inc.
Preliminary product info rmation describes products which are i n production, but for which f ul l char act er iza t i on da t a is not yet available. Advance produ ct i nfor mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” without warrant y of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copy rights, trademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logic websi te or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS262DB2
CDB4923 CDB49300
12. APPENDIX F: BOARD CONTROL SOFTWARE ................................................................. 39
13. APPENDIX G: IC COMPONENT LISTING BY FUNCTION ................................................. 42
13.1 Power ............................................................................................................................. 42
13.2 Reset .............................................................................................................................. 42
13.3 Clocking.......................................................................................................................... 42
13.4 Signal Routing/Level Conversion ................................................................................... 42
13.5 DSP ................................................................................................................................ 42
13.6 Input................................................................................................................................ 42
13.7 Output............................................................................................................................. 42
14. APPENDIX H: JUMPERS LISTED BY FUNCTION ............................................................. 43
14.1 Audio Input Jumpers....................................................................................................... 43
14.2 Audio Output Jumpers.................................................................................................... 43
14.3 DSP Jumpers ................................................................................................................. 43
14.4 Power Jumpers............................................................................................................... 44
14.5 System Clocking Jumpers.............................................................................................. 44
15. APPENDIX I: JUMPERS LISTED BY NUMBER .................................................................. 46
16. APPENDIX J: SWITCH SUMMARY ..................................................................................... 47
LIST OF FIGURES
Figure 1. External Memory Example...............................................................................................9
Figure 2. CDB4923/300 Data Paths.............................................................................................. 11
Figure 3. Audio Clocking............................................................................................................... 12
Figure 4. Audio Clocking............................................................................................................... 12
Figure 4. CS492x/CS493xx........................................................................................................... 18
Figure 5. System Power................................................................................................................ 19
Figure 6. PC Interface................................................................................................................... 20
Figure 7. Control Logic.................................................................................................................. 21
Figure 8. Clocking ......................................................................................................................... 22
Figure 9. Analog Input................................................................................................................... 23
Figure 10. Digital Input.................................................................................................................. 24
Figure 11. D/A Converters ............................................................................................................ 25
Figure 12. Analog Output.............................................................................................................. 26
Figure 13. Digital Output ............................................................................................................... 27
Figure 14. Top Layer..................................................................................................................... 28
Figure 15. Bottom Layer................................................................................................................ 29
Figure 16. SSTOP......................................................................................................................... 30
Figure 17. ASYSTOP.................................................................................................................... 31
Figure 18. Layer 2......................................................................................................................... 32
Figure 19. Layer 3......................................................................................................................... 33
Figure 20. CRD4923-MEM Schematic.......................................................................................... 37
Figure 21. CDB49300-MEM Schematic........................................................................................ 38
DS262DB2 3
LIST OF TABLES
Table 1. CS492x/CS493xx Host Interface Mode Selection.............................................................8
Table 2. Data Selection Modes (PLD version AB-X).....................................................................10
Table 3. PROVIDED Data Selection Modes (PLD version AB-X).................................................11
Table 4. Digital Audio Sources......................................................................................................11
Table 5. Clocking Descriptions......................................................................................................12
Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0................................................................... 13
Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1................................................................... 13
Table 8. Clocking Descriptions......................................................................................................13
Table 9. Data Selection Modes (Switch S3, PLD Version AB-X).................................................. 14
Table 10. EXTERNAL Data Selection Modes (PLD Version AB-X).............................................. 14
Table 11. Board Clocking Configurations (J37)............................................................................. 14
Table 12. PCLK Configurations.....................................................................................................15
Table 13. Audio Frequency Selection (J58) ..................................................................................15
Table 14. CS5334 Digital Output Formats (S4).............................................................................16
Table 15. Digital Output Format settings for CS8414 (S1)............................................................16
Table 16. CS4340 Digital Input Formats (S4) ...............................................................................17
Table 17. Digital Input Format settings for CS8404A (S2) ............................................................17
Table 18. CS492x/CS493xx Host Interface Mode Selection.........................................................47
Table 19. CS5334 Digital Output Formats (S4).............................................................................47
Table 20. CS4340 Digital Input Formats (S4) ...............................................................................47
Table 21. Digital Output Format settings for CS8414 (S1)............................................................47
Table 22. PCLK Configurations.....................................................................................................48
Table 23. Digital Input Format settings for CS8404A (S2) ............................................................48
Table 24. Data Selection Modes (Switch S3, PLD Version AB-X) ................................................ 48
CDB4923 CDB49300
4 DS262DB2
CDB4923 CDB49300
1. CDB4923 VS. CDB49300
The CDB4923 and CDB49300 are two customer
development boards built from a single platform the CDB4923/300. This development board replaces the CDB4923 Rev. A and Rev. B.
Although the CDB4923/CDB49300 boards look
very similar, it is important to be aware that when
shipped from the factory, the CDB4923 is configured for only the CS4923 family of audio decoders
and the CDB49300 is configured only for the
CS49300 family of audio decoders.
The features distinguishing the two boards are the
following:
• DSP Power Setting
• DSP PLL Filter Topology
1.1 DSP Power
The CS4923 family is designed to operate with a
core voltage of +3.3 V, and the CDB4923 is
shipped with the DSP Power jumper in the +3.3 V
position. The CS49300 family is designed to operate with a core voltage of +2.5 V, and the
CDB49300 is shipped with the DSP Power jumper
in the +2.5 V position. Attempting to use an audio
decoder on the wrong board (e.g., CS49300 on a
CDB4923) can cause unpredictable results and
damage the decoder.
1.2 DSP PLL Filter
The PLL of the CS4923 is different than that of the
CS49300. Consequently, the optimized external
PLL filters for each family of audio decoders is d ifferent. The CDB4923 is optimized for the CS4923
family and the CDB49300 is optimized for the
CS49300 family. Attempting to use an audio decoder on the wrong board (e.g., CS49300 on a
CDB4923) can cause unpredictable results.
Specifically, the relevant PLL filter components
for the CDB4923 are:
• R246 = 0 Ω
• C155 = 0.22 µF
The relevant PLL filter components for the
CDB49300 are:
• R246 = 33 kΩ
• C155 = 0.22 µF
• C113 = 0.01 µF
Although the boards are tailored for one specific
family of audio decoders, the operation of the
CDB4923 and CDB49300 is effectively the same.
This document will generically refer to the
CDB4923/300 except in those instances where
there is a difference between the boards.
2. OPERATION
The CDB4923/300 is designed to allow full evaluation of the CS4923 family and CS49300 family of
audio DSPs. The members of each audio decoder
family are electrically equivalent, so it is possible
to use any member of the CS4923 family in the
CDB4923 and any member of the CS49300 family
in the CDB49300. In the context of this document,
CS492x should be interpreted as any member of the
CS4923 family and CS493xx should be understood
to be any member of the CS49300 family.
The CDB4923/300 is composed of 8 distinct regions: DSP, Control Interface, Control Logic,
Clocks, Analog I/O, Digital I/O, Patch area, and
Power. Each board region has a number of components and will be briefly discussed below. A more
thorough description of each will be given in dedicated sections of this document which can be
quickly located in the Table of Contents.
The DSP section includes the audio decoder
(CS492x Multichannel Audio Decoder or CS493xx
Universal Audio Decoder) under evaluation, jumpers for controlling DSP power and DSP configuration pins, and stake headers which provide access
to all relevant DSP pins. The jumpers allow the
user to select between +2.5 V or +3.3 V on the DSP
power pins (pre-configured at the factory for the
DS262DB2 5
CDB4923 CDB49300
proper voltage), configure the audio decoder for
different host communication modes and select the
clock source for the DSP (internal PLL or external
clock). The stake headers provide a convenient location for probing signal values and also serve as
the interface to the CRD4923-MEM (for use with
CS492x only) or CDB49300-MEM (for use with
the CS493xx only) external memory expander
cards.
The control interface of the CDB4923/300 is composed of a 25 pin connector designed to accept a
parallel port cable, a programmable logic device
(PLD), and two TTL buffers designed to buffer the
sixteen signal lines coming from the PC. Using the
software provided with the demonstration board,
the user can download code to the DSP, configure
the application code running on the DSP, perform a
reset of the DSP, and deliver compressed audio
files to the DSP. An additional control interface is
provided on the J11 and J12 stake headers when the
PLD is placed into an external interfa ce mode as
described in Data Selection.
The majority of the control logic for this board is
found in the PLD. The PLD latches all signals coming from the parallel port interface, performs all I/O
routing on the board, and provides level conversion
from +5 V to +3.3 V/+2.5 V depending on the setting of the I/O power jumper (J63) for the PLD. A
dip switch is used to control different data/clock
routing configurations. There is also an external reset chip (MAX708) which is responsible for system
reset at power-up and when the digital power begins to fail.
The sources for the main DSP clock on the
CDB4923/300 are the oscillator and the external
PLL. When the oscillator is chosen, the main DSP
clock frequency can be either the 27 MHz or
12.288 MHz oscillator provided with the board.
When properly configured the external PLL can
provide a processor clock frequency ranging from
33 MHz to 81 MHz. When the external PLL is us ed
for the DSP processor clock, it can also be used to
master the system oversampling clock, MCLK.
The CDB4923/300 features six channels of analog
output provided by three CS4340 DACs. The outputs are provide a 3.5 V
signal, and each output
pp
has protection circuitry to protect against speaker
’popping’. A DIP switch is provided for changing
the data format accepted by the CS4340.
There is a stereo analog input on the CDB4923/300
which is designed to interface to line levels of up to
2V
. The analog to digital conversion is per-
rms
formed by the CS5334. A DIP switch is provided
for changing the format of the audio data provided
by the CS5334.
Input and output ports are provided for S/PDIF digital audio streams (IEC60958 and IEC61937). An
incoming S/PDIF stream can be supplied either
with an optical cable or coaxial cable. The S/PDIF
outputs of the CDB4923/300 are all optical. The information from the AUDATA0-2 pins of the
CS492x are transmitted on AOUT_DIG0-2 using
digital audio interface transmitters (CS8404A).
Optical output J43 is connected directly to the
S/PDIF transmitter of the DSP. DIP switches are
provided for changing the serial audio format of the
data provided by the CS8414 and the data accepted
by the CS8404A.
The CDB4923/300 provides both analog and digital patch areas. The digital patch area provides access to both +5 V and DSP Power (voltage of the
CS492x/CS493xx core). These patch areas are very
useful when prototyping circuit modifications.
They can also be used as a place to connect signal
buffers when using the CDB4923/300 in an external interface mode.
2.1 Power Requirements
This board is composed of about 75% digital logic
which is fed by the +5 V power supply. Since the
CS492x is a +3.3 V part and the CS493xx is a
+2.5 V part, there are also +3.3 V and +2.5 V volt-
6 DS262DB2
CDB4923 CDB49300
age regulators on the board (U8 and U27) which
are used to power the DSP and the I/O pads of the
PLD (U11). The +12 V and -12 V supplies are used
to power the input buffers on the analog side of the
board.
The power section of the CDB4923/300 can be
found in Figure 5. The CDB4923/300 requires a
+5 V input on J23 and a digital ground connected
to J24 in order to power the digital section of the
board. The analog portion requires a +12 V supply
on binding post J21, -12 V on J57, and analog
ground connected to J22.
2.2 Dolby Considerations
It should be noted by the system designer that additional circuitry may be required in order to obtain
Dolby Certification (e.g., analog bass management). System requirements are dependent upon
the nature of the end product and which group of
Dolby Certification is required. The designer
should consult the Dolby Licensee Information
Manual and contact Dolby Laboratories to determine exactly what is required to meet Dolby spec ifications for a particular system.
3. DIGITAL SIGNAL PROCESSOR
The CS492x/CS493xx (U1) must be downloaded
with application code and configured for operation
each time that it is powered up. Each time the decoder needs to be reconfigured, the host must send
hardware configuration and application configuration messages to the DSP. A complete description
of the software applications and their messaging
protocol can be found in application notes AN120AN123, AN140 for the CS492x and AN161AN163 for the CS493xx.
Please note that this document and all other documentation pertaining to the CS492x family of decoders can be found at the following website:
http://www.cirrus.com/products/overviews/cs4923.html
This document and all other documentation pertaining to the CS493xx family of decoders can be
found at the following website:
http://www.cirrus.com/products/overviews/cs49300.html
As the focus of the board, the CS492x/CS493xx
performs all processing of digital audio. The DSP
section of the board is illustrated in Figure 4. The
CS492x/CS493xx can be fed compressed data or
linear PCM from various sources. However, it
should be noted that each load of application software for the DSP is designed to process a specific
data type, e.g. DTS application code does not
process linear PCM. Please reference the appropriate software application note (i.e. AN120-AN123,
AN140 or AN161-AN163) to determine which
hardware configurations and audio data types are
supported.
3.1 Control Signals
The host interface to the DSP, which allows code
download and other communication, can be accessed through the parallel port interface (J29) or by
placing the control PLD into an external interface
mode. In the external interface m ode the user can
drive the signal pins of the DSP by tapping into the
signals present on headers J11 and J12. More information on selecting the host control mode can be
found in Data Selection.
The host interface mode of the DSP is selected at
the rising edge of reset and is programmable. The
communication mode is determined by the stat es of
the RD, WR, and PSEL pins when the DSP comes
out of reset, as described in the CS4923/4/5/6/7/8/9
datasheet and the CS49300 datasheet. Each mode is
described in the CS4923/4/5/6/7/8/9 Hardware User’s Guide (AN115) and the CS49300 datasheet.
There are six jumpers used to directly cont rol the
CS492x/CS493xx. Jumpers J2 (WR), J3 (RD), and
J62 (PSEL) are used to select the host interface
mode for the CS492x/CS493xx. Table 1 lists the
jumper settings required for all four host interface
modes. Note that the CDB4923/300 requires
DS262DB2 7
CDB4923 CDB49300
PSEL==1 when configuring for I2C mode because
PSEL and SCDIO are multiplexed onto the same
pin.
Two of the DSP jumpers are designed to act as current measurement points for the CS492x/CS493xx.
Jumper J59 is the analog current measurement
point, and it must be installed for the PLL to function. Jumper J60 is the digital current measurement
point, and it must be installed in order to supply
power to the digital logic of the CS492x/CS493xx.
Jumper J1 is the clock selection jumper. When J1 is
in the ’CLKIN’ position, the clock present on pin 30
of the DSP (CLKIN) will drive the internal DSP
clocks directly. When J1 is in the ’PLL’ position,
the clock present at pin 30 is used as the refer ence
clock for the CS492x/CS493xx internal PLL. The
frequency required for the reference clock when
using the internal PLL is application code depen-
dent, so the relevant application code user’s guide
should be consulted to determine which frequency
to provide.
CRD4923-MEM external memory board is tailored
for the CDB4923. The schematic for CRD4923MEM can be found in Figure 20.
The CS493xx family has integrated DTS tables, so
a ROM is required only for autoboot. The
CS493xx also has a static RAM interface. The
CDB49300-MEM external memory board is tailored for the CDB49300. The CDB49300-MEM
schematic can be found in Figure 21.
The CDB4923/300 has been designed to interface
to both the CRD4923-MEM and CDB49300-MEM
daughter boards. The card plugs directly on to J11
oriented such that the CS492x/CS493xx is not covered, as shown in Figure 1.
Please consult the memory map associa ted with the
revision of ROM installed in the memory card to
determine which code loads are available. The
memory map can be found in the ‘.fmt’ file found
on the included floppy.
4. CONTROL
RD
J3
Table 1. CS492x/CS493xx Host Interface Mode Selection
WRJ2PSEL
J62
011
10X Serial SPI
1 1 0 8-bit Intel
1 1 1 8-bit Motorola
Host Interface Mode
2
Serial I
C (PSEL==SCDIO)
3.2 External Memory
Some CDB4923/300 boards may be shipped with
an external memory board. There two different external memory boards available:
• CRD4923-MEM - external ROM for CS492x
• CDB49300-MEM - external ROM and RAM
for CS493xx
The CS492x requires an external ROM for autoboot, and the CS4926 requires an external ROM
when processing DTS audio streams. The
Control of the CS492x/CS493xx can be accomplished in two ways. The CDB4923/300 is shipped
with a parallel computer cable which can be attached to the parallel port (LPT1, LPT2, or LPT3)
of any computer which has a Windows or DOS
based operating system. The parallel port (J29) interface circuitry is illustrated in Figure 6. The software shipped with the CDB4923/300 is based on
command-line programs which must be executed
from a DOS prompt. The CDB4923/300 software
provides the means to reset the CS492x/CS493xx,
write control data to the DSP, read control data
from the DSP, and deliver compressed audio. A detailed description of the software can be found in
Appendix F: Board Control Software.
Alternatively, the board can be put into a mode
which tri-states all connections between the PLD
and the DSP (full external mode), or a mode that
tri-states the control lines (external control mode)
of the CS492x/CS493xx while still driving the data
8 DS262DB2
CDB4923 CDB49300
Digital Input
Control
Interface
RESET
CS8404A CS8404A CS8404A
CS8414
PLL
Digital Output
CRD4923-MEM
CDB49300-MEM
PLD
OSC
Figure 1. External Memory Example
input ports of the DSP. These configuration allows
the user to drive signals on stake headers J11 and
J12 in order to operate the DSP as if it were part of
an embedded system. The user is responsible for
providing the appropriate clocking signals, control
signals, and data signals to the DSP in full e xterna l
mode, but the user only provides control signals in
exernal control mode.
In the external modes the audio output of the DSP
still drives the on-board DACs and digital transmitters thus allowing the user to access the audio on
the analog and digital output connectors provided
by the CDB4923/300. The stake headers J11 and
J12 can be found in Figure 4.
All on-board clocks and data lines are routed
through the PLD (U11) in order to provide maximum flexibility in the evaluation of different system configurations. The PLD will perform all +5 V
to +3.3 V/+2.5 V conversions between the DSP
and the +5 V parts with which it interacts by configuring the I/O power jumper (J63). The system
can also be configured in an external interface described above. The external modes are detailed in
Data Selection. All PLD modes are selected using
CS4340
+2.5V
+3.3V
CS492x
CS493xx
CS4340
CS4340
CS5334
Patch Area
Analog
Output
Stereo
Analog In
DIP switch S3. The PLD (U11) and switch S3 are
shown in Figure 7.
A specialized IC (U12), the MAX708, has been included on the CDB4923/300 in order to generate a
system reset at power-up, when the digital power
begins to fail, and when the system reset button
(SW1) is depressed. This chip helps to insure consistent operation on the board by providing a
200 ms reset pulse whenever activated.
5. DATA SELECTION
Data selection on the CDB4923/300 refers to the
routing of audio data, audio clocks, control data,
and control clocks. Because the PLD plays such a
crucial role in determining the routing and control
scheme, each data selection mode is also referred to
as a ‘PLD mode.’ It is important to note that Table
2, the PLD Mode table, is based directly upon the
version of the control PLD (U11) used on each particular board. Each PLD has a specific revision
code printed on its label. If your PLD version differs from the one described in this document, contact the factory to determine which feature set is
provided with your board.
DS262DB2 9
CDB4923 CDB49300
The two major PLD modes for the CDB4923/300
are the PROVIDED resource mode and the EXTERNAL interface mode. When a PROVIDED
mode is chosen all clocks are provided by the demonstration board, all audio data passes through the
PLD, and the DSP is controlled by the PC parallel
port interface. The EXTERNAL interface modes
allow the user to drive the audio data and control
pins of the DSP directly by wire-wrapping to stake
headers J11 and J12, bypassing the control PLD. It
should be noted that there are two variants of the
EXTERNAL interface mode. One EXTERNAL
mode provides direct access to all control and audio
data input pins of the CS492x/CS493xx, and the
second EXTERNAL mode allows the user to drive
the control signals of the CS492x/CS493xx while
audio data still comes from the CDB4923/300.
The DIP switch S3 is used to choose the different
routing schemes, and can be found in the Control
schematic of Figure 7. Table 2 provides a general
overview of the available PLD modes.
5.1 Provided Mode
When the user has chosen a PROVIDED resource
mode, the PLD Mode determines the source of audio data for the two data pins of the DSP (CMPDAT—pin 27 and SDATAN1—pin 22) and the
source of the system's oversampling clock
(MCLK). Table 3 lists the routing configurations
for each of the PROVIDED data selection modes.
5.1.1 Control
As mentioned earlier, when a PROVIDED mode
has been selected, all control of the CDB4923/300
is accomplished using the parallel port (J29). A
floppy disk is included with the CDB4923/300
which contains the control software described in
Appendix F: Board Control Software.
5.1.2 Data
All of the Data Selection Modes shown in Table 3
imply PC control. In Table 4, a brief description is
given for each data source listed in Table 3.
The general data flow of the system is illustrated in
Figure 2. A data path is shown for each of the
modes listed in Table 3.
PLD Mode DATA_SEL2 DATA_SEL1 DATA_SEL0 AUDIO DATA, CONTROL,
and CLOCKS
0 LO LO LO EXTERNAL J11
1 LO LO HI EXTERNAL CONTROL
ONLY
2 LO HI LO PROVIDED PC
3 LO HI HI PROVIDED PC
4 HI LO LO PROVIDED PC
5 HI LO HI PROVIDED PC
6 HI HI LO RESERVED
7 HI HI HI RESERVED
NOTE: Because each mode of the Data Selection switch (S3) sets up a different hardware configuration, clock
and data lines may be momentarily directed to many different destinations during mode changes. Without
the proper initiali za tio n pr o ces s aft er a r ec on figuration, strange beha vi or ma y b e o bse r ved . T he re co mmended procedure for pe rfor min g ch ang es to the r outi ng conf igu ratio n is to fir s t gen erate a bo ar d re se t
using the BOARD RESET switch (SW1). The CS492x/CS493xx will then require a soft reset
("CDB30RST.EXE -s" which performs a hardware reset and then sends the soft reset message
0x000001) and the proper hardware and applic ation co nfigurati on mess ages for the new mo de. A thorough description of soft reset, hardware configuration, and application configuration can be found in the
software Application Notes AN115, AN120-123, AN140 or AN161-163.
CONTROL SOURCE
J11
Table 2. Data Selection Modes (PLD version AB-X)
10 DS262DB2
CDB4923 CDB49300
CS4340
XMT958
CS8414
CS8414
Data
CS8404A CS8404ACS8404A
CDI
DAI
Parallel Compressed Data
XMT958
CS492x
CS493x
x
Stereo PCM
CS4340
CS4340
PCM Out
CS5334
Figure 2. CDB4923/300 Data Paths
PLD
Mode
DATA_SEL2 DATA_SEL1 DATA_SEL0 CS492x/CS493xx
CMPDAT
CS492x/CS493xx
SDATAN1
2LO HI LO PC A/D — CS5334 DSP
3LO HI HIS/PDIF — CS8414 S/PDIF — CS8414 CS8414
4HI LO LOS/PDIF — C S8414 A/D — CS5334 CS8414
5HI LO HI A/D — CS5334 A/D — CS5334 OSC/PLL
MCLK
SOURCE
Table 3. PROVIDED Data Selection Modes (PLD version AB-X)
Digital Audio Source Description
S/PDIF - CS8414 The CS8414 (U13) delivers the payload from an IEC60958 (linear PCM) or IEC61937 (nonlinear
PCM) encoded bit-stream. The incoming S/PDIF stream is connected to either J32 or J30.
A/D - CS5334 The CS5334 (U25) delivers stereo PCM which has been enc oded from t he analog i nput signals on
J55 and J56.
PC A compressed digital audio stream is delivered in bursty format to the parallel port of the
CS492x/CS493xx from a fi le on the PC . Thi s tran sfe r mode requires that the CD B492 3/3 00 is in a
parallel communication mode, and the PARLLPLY.EXE program is then used to deliver compressed data through the PC interface.
NOTE: This data source is valid only for compressed audio and can be used only with parallel
communication modes (i.e. INTEL or Motorola mode).
Table 4. Digital Audio Sources
DS262DB2 11
CDB4923 CDB49300
MCLK
Source
Description
CS8414 The CS8414 (U13) derives the sampling fre-
quency (Fs) from an incoming S/PDIF stream
and masters a 256 Fs MCLK
DSP The DSP (U1) masters MCLK, general ly when
using broadcast application code
OSC/PLL The source of the main DSP clock also sup-
plies the system 256 Fs MCLK (see Clocking
for details)
Table 5. Clocking Descriptions
5.1.3 Audio Clocking
The audio clocking scheme is illustrated below in
Figure 3. Note that MCLK is bidirectional with respect to the DSP. When the DSP is slaved to an external MCLK, i.e. the MCLK source is not listed a s
DSP, the DSP will slave to the MCLK of the
CS8414 or the MCLK derived from the on-board
PLL (U26) or the OSCILLATOR (Y1). When the
internal PLL of the CS492x/CS493xx is being
used, however, the DSP will master the MCLK.
Caution must be observed when choosing a particular data selection mode and configuring the DSP
to ensure that there is no contention with the PLD
(U11). Each PLD mode given in Table 3 lists the
associated MCLK master - this table should be referenced whenever reconfiguring the
CDB4923/300. A brief description of each MCLK
source is given in Table 5.
5.2 External Mode
The EXTERNAL mode is designed to allow users
to drive the DSP directly with an external microcontroller. Stake headers J11 and J12 contain all of
the signals required for host communication with
the CS492x/CS493xx. When operating in this
mode the DSP control pins are tri-stated by the
PLD (U11), effectively disabling the PC interface.
Consequently, the software bundled with the demo
board will not be functional.
The main DSP clock is always provided by the
CDB4923/300 (please see the Clocking section to
determine how to select the oscillator or external
PLL), and the output signals AUDATA0-2 are still
routed to the CS8404A S/PDIF transmitters and
CS4340 DACs.
Depending on the EXTERNAL mode selected the
user may be responsible for all data, control, and
clock signals going to the DSP, or just control.
CS8404A
CS8414 MCLK
CS8414
12 DS262DB2
OSC
PLL
NOTE: ALL SIGNALS DRIVEN TO THE CS493xx
CS8404A CS8404A
DIGITAL MCLK / ANALOG MCLK
DSP MCLK
DSP SCLK
DSP LRCLK
DIGITAL SCLK / ANALOG SCLK
DIGITAL LRCLK / ANALOG LRCLK
Figure 3. Audio Clocking
MUST BE +3.3 V LOGIC. Because the
CS493xx does not have +5 V tolerant pads, an
external buffer such a s the 74VHC244 should
be used for level conversion of any signals driven to the DSP. Failure to buffer +5 V signals
can cause permanent damage to the DSP. If
necessary, level shifting buffers can be wired
into the digital patch area of the CDB49300.
CS4340
CS4340
CS4340
CS492x
CS493xx
CS5334
CDB4923 CDB49300
As mentioned above, many of the PLD’s I/O pins
are tri-stated. The complete list of tri-stated pins
for full external mode (PLD Mode 0) can be found
in Table 6. The complete list of tri-stated pins for
external control mode (PLD Mode 1) can be found
in Table 7.
By design, the clocking signals present at the
MCLK, LRCLK, and SCLK pins of the
CS492x/CS493xx are used to drive both the audio
input and output circuitry for the rest of the
CDB4923/300 as shown in Figure 3. This means
that the S/PDIF input, S/PDIF output, analog output and analog input continue to function in the
EXTERNAL modes. The user should only drive
audio clocks in PLD Mode 0. PLD Mode 1 derives
audio clocks from the CS8414.
The three clocking configurations that the user
should be aware of when using PLD Mode 0 are:
• DSP is slave to all audio clocks - user drives
MCLK/SCLK/LRCLK
• DSP masters LRCLK/SCLK - user drives
MCLK
Pin Name Pin
Number
RESET
RD
WR
A1, CDIN 6
A0, SCCLK 7
SCPDIO 19
CS
Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1
36
5
4
18
Pin Name Pin
Number
DATA0 17
DATA1 16
DATA2 15
DATA3 14
DATA4 11
DATA5 10
DATA6 9
DATA7 8
MCLK
Source
J12 The user must provide an oversampling clo ck on
the 23MCLK pin of stake header J12. (NOTE:
This clock signal must be +3.3 V logic when
using CS493xx)
CS8414 The CS8414 (U13) derives the sampling fre-
quency (Fs) from an incoming S/PDIF stream
and masters a 256 Fs MCLK
DSP The DSP (U1) masters MCLK, generally when
using broadcast application code
Description
• DSP masters MCLK/LRCLK/SCLK - user
drives no audio clocks
Pin Name Pin
Number
MCLK 44 DATA0 17
CMPCLK 28 DATA1 16
CMPREQ 29 DATA2 15
CMPDAT 27 DATA3 14
SCLKN1 25 DATA4 11
SLRCLKN1 26 DATA5 10
SDATAN1 22 DATA6 9
RESET
RD 5 A1, CDIN 6
WR 4 A0, SCCLK 7
EXTMEM 21 SCPDIO 19
Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0
36 DATA7 8
Pin Name Pin
CS
Number
18
Table 8. Clocking Descriptions
Only when the correct clocking is present on the
23MCLK, 23LRCLK, and 23SCLK pins (J12),
processed audio can be heard on the analog outputs
(J13 - J20) and the digital outputs (J45 - J47). The
analog outputs J13-J20 can be found in Figure 12,
and the digital outputs can be found in Figure 13.
The information in Table 9 summarizes the operation of switch S3. The table shows the data routing
configuration, the MCLK source, and the method
of board control. This is intended as a quick refer ence and can also be found in Appendix J: Switch
Summary.
DS262DB2 13
CDB4923 CDB49300
6. CLOCKING
There are four major clocks routed across the
CDB4923/300: CLKIN for the DSP, MCLK, LRCLK, and SCLK. CLKIN is only used to drive the
digital logic of the DSP core. MCLK, LRCLK, and
SCLK are used for synchronizing the audio systems of the CDB4923/300.
6.1 DSP Clock
The DSP clock of the CS492x/CS493xx is provided at the CLKIN pin (pin 30). The setting of jumper
J1 (DSP CLOCK) determines whether the
CS492x/CS493xx uses the input clock as the DSP
clock directly (CLKIN position) or uses the input
clock as a reference for the internal PLL ( PLL position).
There are two possible clock sources on the
CDB4923/300. The first is the OSCILLATOR
(Y1). The second option is the external PLL (U26)
which can be configured to provide a processor
clock ranging from 33 MHz to 81 MHz. All clocking circuitry can be found in Figure 8.
Since the PLL (U26) and the OSCILLATOR (Y1)
are co-dependent, only one can be used at any given time. Jumper J37 is used to select the source of
the main DSP clock. It is vital to note that the jumper J37 is a double jumper with two jumpers which
must be moved in unison. If the jumpers are not
moved together, board behavior will be unpredictable. Table 11 lists the oscillator requirements, and
the two different settings for J37, where pins 3 and
4 are connected to the inputs of the PLD. Jumper
J37 can also be found in Figure 8.
In order to use the 27 MHz oscillator directly, Y1
should be populated with the 27 MHz oscillator included with the CDB4923/300 package. Addition-
Clock
Source
Oscillator 27 MHz or
External
PLL
Table 11. Board Clocking Configurat ions (J37)
Y1 J37 - Pin 3 J37 - Pin 4
OSC OSC
12.288 MHz
oscillator
27 MHz
oscillator
PLL PLL
PLD
Mode
0 LO LO LO Data and Control lines accessed via J11 and J12 J12 or DSP J11 & J12
1 LO LO HI S/PDIF -- CS8414 A/D -- CS5334 CS8414 J11 & J12
2 LO HI LO PC A/D -- CS5334 DSP PC
3 LO HI HI S/PDIF -- CS8414 S/PDIF -- CS8414 CS8414 PC
4 HI LO LO S/PDIF -- CS8414 A/D -- CS5334 CS8414 PC
5 HI LO HI A/D -- CS5334 A/D -- CS5334 OSC/PLL PC
6 HI HI LO RESERVED
7 HI HI HI RESERVED
PLD
Mode
0 LO LO LO J12 J12 J12 or DSP
1HIHIHIS/PDIF — CS8414 A/D -- CS5334 CS8414
14 DS262DB2
DATA
SEL2
DATA_SEL2 DATA_SEL1 DATA_SEL0 CS492x/CS493xx
DATA
SEL1
DATA
SEL0
Table 9. Data Selection Modes (Switch S3, PLD Version AB-X)
Table 10. EXTERNAL Data Selection Modes (PLD Version AB-X)
CS492X/CS493XX
CMPDAT
CS492X/CS493XX
SDATAN1
CMPDAT
MCLK
MASTER
CS492x/CS493xx
SDATAN1
CONTROL
SOURCE
MCLK
SOURCE
CDB4923 CDB49300
ally, both jumpers of J37 should be set to the OSC
position. In this clocking configuration you should
not use any modes which list OSC/PLL as the
MCLK source while Y1 is 27 MHz.
In order to use the 12.288 MHz oscillator directly,
Y1 should be populated with the 12.288 MHz oscillator included with the CDB4923/300 package,
and both jumpers of J37 should be set to the OSC
position. The 12.288 MHz oscillator can be used
with those PLD modes naming OSC/PLL as the
MCLK source, as 12.288 MHz is a standard 256Fs
oversampling frequency (256 * 48 kHz).
The choice of 12.288 MHz or 27 MHz is application code dependent. Applications dealing with
IEC61937 packed compressed audio generally require a 12.288 MHz input, while broadcast applications typically require a 27 MHz input. Check the
relevant application code user’s guide (AN120AN123, AN140 or AN161-AN163) for details on
DSP CLKIN frequency.
If the external PLL is to be used, then Y1 must be
populated with a 27 MHz oscillator. The jumpers
of J37 should both be placed in the PLL position.
The CLKIN pin of the DSP will now be driven with
the processor clock (PCLK) output of U26. The
processor clock (PCLK) output can be configured
to generate either a many different frequencies,
based upon the configuration of jumpers J67, J68,
and J72 as listed in Table 12.
When using the external PLL to generate the DSP
clock, the CLKSEL pin (J1) of the
CS492x/CS493xx is typically set to ‘EXT CLK’.
6.2 MCLK
modes can select between an MCLK which is simply the frequency of the on-board oscillator (Y1),
or a programmable MCLK generated by the external PLL (U26).
The source of MCLK is dependent upon the PLD
mode and is indicated by the ‘MCLK SOURCE’
column of Table 9 and Table 24.
U26 is a discrete PLL which can generate many
different audio frequencies in addition to the processor clock discussed above. The frequency of the
audio clock is controlled by the states of the AS1
and AS0 pins which are set with jumpers J70 and
J71. The available audio clock frequencies can be
used to support many different sampling frequencies, depending on the desired MCLK ratio. Table
13 enumerates all possible MCLK frequencies for
the external PLL.
6.3 LRCLK and SCLK
LRCLK and SCLK are assumed to be generated by
the DSP in all cases. The audio clocking diagram
shown in Figure 3, illustrates the clocking scheme
of the CDB4923/300. If it is necessary to provide a
complete slave mode for the DSP, please contact
the factory for details on how to properly configure
the CDB4923/300.
PCLK Frequency J72 J67 J 68
33.33 MHz LOLOLO
54 MHz LO LO HI
66.66 MHz LO HI LO
80 MHz LO HI HI
32 MHz HI LO LO
81 MHz HI LO HI
50 MHz HI HI LO
40 MHz HIHIHI
The system MCLK on the CDB4923/300 can come
Table 12. PCLK Configurations
from four different sources when using a PROVIDED mode. Some PLD modes use the MCLK generated by the CS8414 S/PDIF receiver (U13) when
there is an incoming S/PDIF stream. In PLD mode
2, the DSP generates MCLK when it is decoding a
compressed bit stream delivered by the PC. Some
DS262DB2 15
MCLK Frequency AS1 (J70) AS0 (J71)
24.576 MH z 1 1
12.288 MH z 0 0
11 .28 96 MH z 0 1
8.192 MHz 1 0
Table 13. Audio Frequency Selection (J58)
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