World’s first cost-effective, high-performance 32-bit DSP
that is solely dedicated to enable Audyssey Laboratories
audio processing technologies for today’s high-volume
consumer electronic produ cts
Features: Audyssey Dynamic Volume
TM
, Audyssey EQTM & Audyssey BassXTTM/BassXT-TV
EQ
Audyssey Dynamic Volume eliminates the need for
constant volume adjustments
Audyssey Dynamic EQ enables a reference playback
experience at any desired playback level
Audyssey EQ removes much of the distortion caused by
speaker enclosures and the typical room environment
producing greatly improved sound compared to similar
products without correction
Audyssey BassXT and BassXT-TV are specifically
calibrated to enhance the physical bass respons e of each
product model
Configurable Serial Audio Inputs/Outputs
— Maximum 32-bit @ 192 kHz
(Note: Audyssey Laboratories algorithms support 48 kHz,
44.1 kHz and 32 kHz)
— Integrated 192 kHz capable S/PDIF transmitter
Integrated Clock Manager/PLL
— Can operate from external crystal, external oscillator
Input Fs Auto Detection & Coefficient Loading
Host Control & Boot via Serial Interface
Support for Master (Self) Boot via Serial EEPROM for
single Fs applications (i.e. 48 kHz only via ADC input)
Configurable GPIOs and External Interrupt Input
1.8V Core and a 3.3V I/O that is tolerant to 5V input
Low-power Mode
—“Energy Star® Ready” via low-power mode, 268 µW in
standby
TM
, Audyssey Dynamic
The brand new CS48AU2B device is still based on the same
high-performance 32-bit fixed point Digital Signal Processor
core but instea d is eq uip ped w i th mu ch less memory, tailoring
it for more cost-effective applications which feature Audyssey
Laboratories audio processing technologies. Target
applications are:
TM
— Digital Televisions
—iPod
— A utomotive Head Units (OEM and Aftermarket)
— Automotive Outboard Amplifiers (OEM and Aftermarket)
—Blu-ray
— S oundbars / Sou nd Projectors
The following Audyssey Lab orat orie s al gorithms are currently
supported on the CS48AU2B and more are in development:
While the individual Audyssey processing algorithms have
already been implemented on this DSP, the CS48AU2B is
programmed using the Cirrus proprietary DSP Composer
GUI development tool.
Processing chains combining both standard signal
processing blocks (Tone Control, Bass Management, etc.) in
combination with any combination of Audyssey Laboratories
technology algorithm blocks may be designed using a simple
drag-and-drop interface to create a custom signal flow
specific to your product model. The end result of this is a
software image t hat is d ow n-l oa ded to th e D SP v ia serial host
2
C® or SPITM) or via a serial master (self) boot.
(I
Support for loading of the various Audyssey Laboratories
algorithm coefficient files supplied by Audyssey Laboratories
is easily supported via DSP Composer, enabling the
OEM/ODM to quickly be able to generate the necessary files
for the system microcontroller which have been custom
tailored for each specific model based on the measurement
and analysis performed by Audyssey Laboratories.
Ordering Information:
See page 21 for ordering information
®
Docking Stations
®
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Disc Receivers
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Serial
Control 1
Mu lt ic h ann e l
Audio In
32-bit
S/PDIF
Multichannel
Audio Out
CONFIDENTI
http://www.cirrus.com
DSP
PXY
Copyright 2009 Cirrus LogicMAY ’09
CONFIDENTIALDS876F3
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GPIODebug
Watchdog
TMR1
TMR2
PLL
CS48AU2B Data Sheet
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Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
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ontacting Cirrus Logic Support
or all product questions and inquiries contact a Cirrus Logic Sales Representative.
o find the one nearest to you go to
MPORTANT NOTICE
irrus Logic, Inc. and i ts subsidiaries (“Cirrus”) bel i eve that the information conta ined i n this document is accurate and rel i abl e . However, the information is sub j ec
o change without notice and i s provided “AS IS” without wa rranty of any kin d (express or impl ied). Customer s are advised to obtain the l atest version o f relevan
nformation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sal
upplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is as sumed by Cirru
or the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of thir
arties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights
opyrights, trademarks, trade secr ets or other intell ectual property right s. Cirrus owns the copyright s associated with the informati on contained herei n and give
onsent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consen
oes not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
ERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVER
ROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICA TIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
SE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTH ER
RITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH AP PLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOME R'S RISK AND
IRRUS DISCLAIMS AND MAKES NO WARRANTY, EXP RESS , STATUTOR Y OR IMPLIED, INCLUDING THE IMPLIED WARRAN TIES OF ME RCHANTAB ILIT
ND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
USTOMER'S CUSTOMER USES OR PERM ITS T HE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICAT IONS , CUSTOMER AGREES, BY SUCH USE, TO
ULLY INDEMNIFY CIRRUS, ITS OFFICE RS, DIRECTORS, EMP LOYEES, DISTRIBUTO RS AND OTHER A GENTS FROM A NY AND ALL L IABILITY, INCLUDING
TTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECT ION WITH THESE USES.
irrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names i
his document may be trademarks or service marks of their respective owners.
udyssey, the Audyssey stylized logo and font, Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, and Audyssey BassXT ( implementations for bot
TIB and TV) are either trad emarks or registered trademarks of Audyssey Labora tories. Sale of the CS48AU2B is only authorized to licensees of Audysse
aboratories deemed to be in good standing.
PI is a trademark of Motorola, Inc.
2
C is a registered trademark of Philips Semiconductor.
Pod is a registered trademark of Apple Computer, Inc.
lu-ray and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION.
nergy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.
2Copyright 2009 Cirrus LogicDS876F3
CONFIDENTI
www.cirrus.com
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CONFIDENTIAL
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ELPHI
CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
1. Documentation Strategy
The CS48AU2B Data Sheet describes the CS48AU2B audio processor. This document should be
used in conjunction with the following documents when evaluating or designing a system around the
CS48AU2B of processors.
Table 1. CS48AU2B Related Documentation
Document NameDescription
CS48AU2B Data SheetThis document
Includes detai led system des ign information inc luding
CS485xx Hardware User’s Manual
AN298 - CS485xx Firmware User’s Manual
Typical Connection Diagrams, Boot-Procedures, Pin
Descriptions, etc.
Includes detailed firmware design information
including signal processing flow diagram s and cont rol
API information for the operating system.
FT
TM
DSP Composer
AN298PPMQ, Audyssey Dynamic Volume
Audyssey Dynamic EQ
Application Note
AN298PPMR, Audyssey EQ
Application Note
AN298PPMS, Audyssey BassXT
Module Application Note
The scope of the CS48AU2B Data Sheet is primarily the hardware specifications of the CS48AU2B
of devices. This includes hardware functionality, characteristic data, pinout, and packaging
information.
The intended audience for the CS48AU2B Data Sheet is the system PCB designer, MCU
programmer, and the quality control engineer.
2. Overview
The CS48AU2B DSP is designed to provide high-performance post-processing and mixing of digital
audio. The low-power standby preserves battery life for applications which are always on, but not
necessarily processing audio, such as automotive audio systems. The CS48AU2B is available in a
48-pin QFP package. Please refer to Table 2 on page 7 for the input, output and suggested
applications for this device.
User’s Manual
TM
Firmware Module
TM
Firmware Module
TM
Firmware
TM
Includes detailed configuration and usage
information for the GUI development tool.
Contains descriptio n of API used to co ntrol Audysse y
Dynamic Volume and Audyssey Dynamic EQ
firmware.
DRA
Contains descriptio n of API used to co ntrol Audysse y
EQ firmware.
Contains descriptio n of API used to co ntrol Audysse y
BassXT firmware.
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DELP
2.1 Licensing
Licenses are required for any of the Audyssey Laboratories algorithms listed in Section 3. Please
contact Audyssey Laboratories at sales@audyssey.com
technology. Please send e-mail to trademark@audyssey.com
trademarks.
DS876F3Copyright 2009 Cirrus Logic5
CONFIDENTI
CONFIDENTIAL
for more information on licensing their
for more information on Audyssey
CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
3. Code Overlays
The suite of software avail able fo r t he CS48AU2B consist s o f an o perati ng sys tem (OS) and a l ibrar y
of overlays. The overlays have been divided into three main groups called Matrix-processors,
Virtualizer-processors, and Post-processors. All software components are defined below:
1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, error concealment,
etc.
2. Matrix-processor- Any Module that performs a matrix decode on PCM data to pr oduce mo re
output channels than input channels (2Ön channels). Generally speaking, these modules
increase the number of valid channels in the audio I/O buffer.
3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than
input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the
physical audio channels that were eliminated. Generally speaking, these modules reduce the
number of valid channels in the audio I/O buffer.
4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the
matrix- or virtualizer -process ors. Examples are bass manag ement, audi o manage r, tone control,
Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, Audyssey BassXT, delay, &
customer-specific effects, etc.
The certified DSP firmware or application codes provided by Cirrus Logic (under a licensed to you
from Audyssey Laboratories) may enable some or all of the Audyssey Laboratories algorithms.
These licensed processing blocks can be used in combination with a host standard post-processing
signal blocks (tone control, Bass Management, delays, etc.) or lower level primitives such as a filter
or math function.
A product-specific signal flow is generated by the designer using DSP Composer.
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Once all of the custom coeffic ient fil es supp lied by Audy ssey Lab oratori es have been l oaded and t he
signal flow has been set, the user can perform a “generate delivera bles” inside DSP Composer.
This generates a collection of files that can be easily converted to .c or .h files by the designer for
storage inside the host controller OR can be converted into a small image tha t can either be stored in
an external serial FLASH/EEPROM, or downloaded via a host controller through the
port.
The overlay structure reduces the t ime required t o reconfigu re the DSP when a process ing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For
example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not
need to be reloaded — only the new matrix-processor (the same is true for the other overlays).
Table 2 below lists the firmware available based on device selection. Please refer to AN298,
CS485xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework
modules available.
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6Copyright 2009 Cirrus LogicDS876F3
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Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
Table 2. Device and Firmware Selection Guide
CS48AU2B Data Sheet
Device
Portable Audio Docking Station
CS48AU2B-CQZ
4. Hardware Functional Description
4.1 DSP Core
The CS48AU2B DSP is a single-core DSP with separate X and Y data and P code memory spaces.
The DSP core is a high-performance, 32-bit, fully user-programmable, fixed-point DSP that is
capable of performing two multiply-an d-acc umulate (MAC) operat i ons per clock cycl e. The DSP core
has eight 72-bit accumulators, four X- and four Y-data register s, and 12 index registers.
The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between
peripherals such as the serial control port (SCP), digital audio input (DAI) and digital audio output
(DAO), or any DSP core memory, all without the intervention of the DSP. The DMA engine off loads
data move instructions from the DSP core, leaving more MIPS available for signal processing
instructions.
Suggested
Application
Digital TV
Portable DVD
DVD Mini / Receiver
Multimedia PC Speakers
8 Channel Car Audio
DVD Receiver
High-end Digital TV
12 channel Car Audio
Channel Count
Input/Output
Up to 12 chann el in /12
channel out
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Package
48-pin QFP
FT
CS48AU2B functionality is controlled by DSP firmware or application codes that are downloaded to
the CS48AU2B from a host controller or external serial FLASH/EEPROM.
Users can develop their applications using DSP Composer to create the processing chain and then
compile the image into a series of commands that are sent to the CS48AU2B through the SCP. The
processing application can either load modules (matrix-processors, virtualizers, post-processors)
from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.
4.1.1 DSP Memory
The DSP core has its own on-chip data and program RAM and ROM and does not require external
memory for post-processing applications.
The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P
equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.
4.1.2 DMA Controller
The powerful 8-channel DMA controller can move data betwee n 8 on-chip resources. Each resource
has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing
modes are supported, with flexible start address and increment controls. The service intervals for
each DMA channel, as well as up to 6 interrupt events, are programmable.
CONFIDENTI
DELP
DS876F3Copyright 2009 Cirrus Logic7
CONFIDENTIAL
CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.
Up to 32-bit word lengths are supported. The DAI also supports a time division multiplexed (TDM)
one-line data mode, that packs PCM audio on a single data line the total number possible depends
on the ratio of SCLK to LRCLK. The CS48AU2B supports up to 8.
The port has two independent slave-only clock domains. Each data input can be independently
assigned to a clock domain. The sample rate of the input clock domains can be determined
automatically by the DSP, off-l oading the t ask of monitor ing the SPDIF receiv er from the host. A time stamping feature allows the input data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as
192 kHz. The port can be conf igured as an independent clock domain mastered by the DSP, or as a
clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can
be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with
embedded clock on a single line).
The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple
channels of PCM audio on a single data line.
DRA
4.2.3 Serial Control Port (I
2C®
or SPI™)
FT
The on-chip serial control port is capable of operating as master or slave in either
modes. Master/Slave operation is chosen by mode select pins when the CS48AU2B comes out of
Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode ( SPI clock speed
must always be ≤ (F
the communications interface (SCP_BSY
host (SCP_IRQ
4.2.4 GPIO
Many of the CS48AU2B peripheral pins are multiple xed with GPIO. Each GPIO can be configur ed as
an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising
edge, falling edge, active-low, or active-high.
4.2.5 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used
to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock
domain can be output on the DAO port for driving audio converters. The CS48AU2B defaults to
running from the external reference frequency and is switched to use the PLL output after overlays
have been loaded and configured, either through master boot from an external FLASH or through
host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output
frequency ratio is selectable between 1:1 (default) or 2:1.
4.2.6 Hardware Watchdog Timer
CONFIDENTI
).
/2)). The CS48AU2B serial control port also includes a pin for flow control of
dclk
) and a pin to indicate when the DSP has a message for the
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The CS48AU2B has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS48AU2B will reset itself in the event of a temporary system failure. In
stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
8Copyright 2009 Cirrus LogicDS876F3
CONFIDENTIAL
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