Cirrus Logic CS4812-KM, CS4812 Datasheet
CS4812
Fixed Function Multi-Effects Audio Processor
Features
l DSP for embedded reverb/effects
applications
– 24-bit Audio Processing Engine
– No External RAM required
– Two 24-bit ∆Σ ADCs with 100 dB Dyn. Range
– Two 24-bit ∆Σ DACs with 100 dB Dyn. Range
l Mono Guitar or Mixer Effects firmware
included
l Real time parameter control via messaging
protocol
l Serial Control Port for microcontroller
interface
l Single +5V supply operation
l 100-pin Metric Quad Flat Package (MQFP)
ORDERING INFO
CS4812-KM -10 to +70°C 100-pin MQFP
CDB4812 Electric Guitar Effects w/
Parameter Controls.
Description
The CS4812 is a complete audio effects processing
system on a chip. This device includes a proprietary 24bit audio processing engine with considerable on-chip
RAM, two ADCs and two DACs. A full-featured serial
control port allows interfacing to an external host
microcontroller. Other features such as single +5V
operation simplify system design.
The CS4812, combined with Crystal effects firmware, is
the ideal solution for a variety of effects processing
applications where user parameter control is desired.
The Crystal effects firmware provides a messaging
protocol for the serial control port that allows an external
microcontroller to have real-time parameter control over
the audio effects. The complete processor and effects
solution may be evaluated with the CDB4812
demonstration board. The CDB4812 demonstrates a
host of mono electric guitar effects including a digital
spring reverb, delay, chorus, flange and tremolo with
parameter adjustment capability. Please refer to AN195
for more information on application firmware for the
CS4812.
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Advance Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
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This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
DS291PP3
JUL ‘01
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 14
3. FUNCTIONAL DESCRIPTION ............................................................................................... 17
3.1 Overview .......................................................................................................................... 17
3.2 Analog Inputs ................................................................................................................... 17
3.2.1 Line Level Inputs ................................................................................................. 17
3.2.2 Digital High Pass Filter ........................................................................................ 18
3.3 Analog Outputs ................................................................................................................ 18
3.3.1 Line Level Outputs .............................................................................................. 18
3.4 Clock Generation ............................................................................................................. 19
3.4.1 Clock Source ....................................................................................................... 19
3.5 Serial Control Port ............................................................................................................ 19
3.5.1 SPI Bus ............................................................................................................... 19
3.5.1.1 SPI Master Mode ................................................................................ 20
3.5.1.2 SPI Slave Mode .................................................................................. 20
2
3.5.2 I
3.6 Boot Modes ...................................................................................................................... 26
3.6.1 AutoBoot ............................................................................................................. 26
3.6.2 HostBoot ............................................................................................................. 26
3.7 Resets ............................................................................................................................. 27
4. POWER SUPPLY AND GROUNDING ................................................................................... 28
5. PIN DESCRIPTIONS .............................................................................................................. 29
6. PARAMETER DEFINITIONS .................................................................................................. 33
7. PACKAGE DIMENSIONS ...................................................................................................... 34
C Bus ................................................................................................................ 23
3.5.2.1 I
3.5.2.2 I
CS4812
2
C Master Mode ................................................................................. 23
2
C Slave Mode ................................................................................... 24
LIST OF FIGURES
Figure 1. SPI Control Port Slave Mode Timing .......................................................... 8
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing ..................................... 9
Figure 3. I
Figure 4. I
Figure 5. Typical Connection Diagram, Control Port Slave Mode ........................... 14
Figure 6. Typical Connection Diagram, Control Port I
Figure 7. Typical Connection Diagram, Control Port SPI Master Mode .................. 15
Figure 8. Typical Connection Diagram, Control Port I
Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode .................... 16
Figure 10.Recommended Line Input Buffer .............................................................. 17
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any
kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the
printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2C®
Control Port Slave Mode Timing ...................................................... 11
2C®
Control Port Master Mode (AutoBoot) Timing .................................. 12
2
C Master Mode ................... 15
2
C Slave Mode ..................... 16
2 DS291PP3
Figure 11.Single Ended Input ................................................................................... 18
Figure 12.Butterworth Output Filters ........................................................................ 18
Figure 13.Output Mute Circuit .................................................................................. 19
Figure 14.Control Port Timing, SPI Master Mode AutoBoot ..................................... 20
Figure 15.Control Port Timing, SPI Slave Mode Write ............................................. 20
Figure 16.SPI Slave Write Flow Diagram ................................................................. 21
Figure 17.Control Port Timing, SPI Slave Mode Read ............................................. 21
Figure 18.SPI Slave Mode Read Flow Diagram........................................................ 22
Figure 19.SPI Slave Mode Read Flow Diagram with DSP REQ .............................. 22
Figure 20.Control Port Timing, I
Figure 21.I
2
C Slave Mode Write Flow Diagram ........................................................ 24
Figure 22.Control Port Timing, I
Figure 23.Control Port Timing, I
2
Figure 24.I
Figure 25.I
C Slave Mode Read Flow Diagram ....................................................... 25
2
C Slave Mode Read Flow Diagram with DSP REQ ............................... 26
2
C Master Mode AutoBoot ..................................... 23
2
C Slave Mode Write .............................................. 24
2
C Slave Mode Write .............................................. 24
Figure 26.HostBoot Flow Diagram ........................................................................... 27
Figure 27.CS4812 Suggested Layout ...................................................................... 28
Figure 28.Pin Assignments ...................................................................................... 29
CS4812
DS291PP3 3
1. CHARACTERISTICS AND SPECIFICATIONS
CS4812
ADC CHARACTERISTICS (T
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.)
Parameters Symbol Min Typ Max Units
Analog Input Characteristics
ADC Conversion Stereo Audio channels 16 - 24 Bits
Dynamic Range (A weighted, Note 5)
(unweighted, Note 5)
Total Harmonic Distortion + Noise (Note 1,5)
(PLL enabled) (Note 1,2,5)
Interchannel Isolation - 90 - dB
Interchannel Gain Mismatch - 0.1 - dB
Offset Error (with high pass filter enabled) (Note 6) - - 0 LSB
Full Scale Input Voltage (Differential) 1.9 2.0 2.1 V
Gain Drift (Note 2) - 100 - ppm/°C
Input Resistance 10 - - kΩ
Input Capacitance - - 15 pF
CMOUT Output Voltage - 2.3 - V
Common Mode Rejection Ratio (Note 2) CMRR 60 dB
Group Delay (Fs = Output Sample Rate) (Note 4) t
Group Delay Variation vs. Frequency ∆t
High Pass Filter Characteristics
Frequency Response -3dB (Note 3)
Phase Deviation @ 20 Hz (Note 3) - 10 - Degree
Passband Ripple - - 0 dB
= 25°C; VA, VD = + 5V; -1 dB Full Scale Input Sine wave,
A
-0.14dB (Note 3)
THD+N -
gd
gd
93
90
-
-15/Fs- s
--0µs
-
-
100
97
-92
-92
3.7
20
-
-
-87
-
-
-
dB
dB
dB
rms
Hz
Hz
Notes: 1. Referenced to typical full-scale differential input voltage (2 V
2. Bench tested only.
3. Filter characteristics scale with output sample rate.
4. Group delay for Fs = 48 kHz, t
5. Measured using differential analog input circuit, see Figure 10.
6. Filter Response is not tested but guaranteed by design.
4 DS291PP3
= 15/48 kHz = 313 µs.
gd
rms
).
CS4812
DAC CHARACTERISTICS (T
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.)
Parameters Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified.
DAC Resolution 16 - 24 Bits
Dynamic Range (DAC not muted, A weighted) 95 100 - dB
Total Harmonic Distortion + Noise THD+N - -90 -85 dB
Interchannel Isolation - 90 - dB
Interchannel Gain Mismatch - 0.1 - dB
Offset Voltage (differential) (Note 7) - -20 ± 5 - mV
Offset Voltage (V+/V- relative to CMOUT) (Note 7) - -45/-25 - mV
Full Scale Output Voltage (Differential) 1.9 2.0 2.1 V
Gain Drift (Note 2) - 100 - ppm/°C
Out of Band Energy (Fs/2 to 2Fs, Note 2) - -60 - dBFS
Analog Output Load Resistance
Capacitance
Group Delay (Fs = Input Sample Rate) t
Analog Loopback Performance
Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K - 74 - dB
Power Supply
Power Supply Current Operating
Power Down (Note 8)
Power Supply Rejection (1 kHz, 10 mV
= 25°C; VA, VD = + 5V; -1 dB Full Scale Output Sine wave,
A
10
-
gd
, Note 2) - 50 - dB
rms
-16/Fs- s
-
-
-
-
200
1
100
rms
-
-
-
kΩ
pF
mA
mA
Notes: 7. Measured with DAC calibration disabled.
8. Measured with XTI clock disabled.
DS291PP3 5
CS4812
SWITCHING CHARACTERISTICS (T
Parameters Symbol Min Typ Max Units
Audio ADC’s & DAC’s Sample Rate Fs 30 - 50 kHz
XTI Frequency XTI = 128Fs, 256Fs, 512Fs 3.84 - 25.6 MHz
XTI Duty Cycle XTI = 128Fs, 256Fs, 512Fs (Note 9) 40 - 60 %
XTI Jitter Tolerance - 500 - ps
Low Time (Note 10) 500 - - ns
RST
Notes: 9. Guaranteed by characterization but not tested.
10. On power-up, the CS4812 RST
state.
pin should be asserted until the power supplies have reached steady
= 25 °C; VA, VD = +5V, CL = 30 pF)
A
6 DS291PP3
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE
(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)
Parameter Symbol Min Max Unit
CS4812
SPI Slave Mode (SPI
CCLK Clock Frequency
CCLK Low Time
CCLK High Time
Rise Time of Both CDIN and CCLK Lines
Fall Time of Both CDIN and CCLK Lines
Setup Time CDIN to CCLK Rising
Hold Time CCLK Rising to CDIN (Note 11)
Time from CCLK edge to CDOUT Valid (Note 12)
Rise Time for CDOUT
Fall Time for CDOUT
CS
Falling to CCLK Rising
Time from CCLK Falling to CS
High Time Between Active CS
Time from CCLK Rising to REQ
Rise Time for REQ
Fall Time for REQ
/I2C = 0, SCPM/S = 0, Note 14)
Rising
Rising (Note 13)
f
sck
t
scl
t
sch
t
t
t
cdisu
t
cdih
t
scdov
t
cdor
t
cdof
t
css
t
sccsh
t
csht
t
scrh
t
t
-6MHz
66 - ns
66 - ns
r
f
-100ns
-100ns
40 - ns
15 - ns
-45ns
-25ns
-25ns
20 - ns
0-ns
1-µs
-2*DSPCLK+10ns
rr
rf
-100ns
-100ns
Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.
12. CDOUT should NOT be sampled during this time period.
13. DSPCLK frequency is twice the DSP instruction rate.
14. Timing is guaranteed by characterization. Production test guarantees functionality.
DS291PP3 7
CS4812
A6
csht
t
sccsh
t
7
6
5
LSB
MSB
R/W
A0A6 A5
tri-state
LSB
MSB
cscdo
t
*
rh
t
scdov
t
scdov
t
scrh
t
* See section 3.5.1.2 for a detailed explanation of REQ behavior
Figure 1. SPI Control Port Slave Mode Timing
cdih
t
cdisu
t
rf
t
CDIN
CDOUT
REQ
(output)
CS
sch
t
scl
t
css
t
(input)
f
t
r
t
(input)
SCL/CCLK
8 DS291PP3
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER
(TA = 25°C, VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF)
Parameter Symbol Min Typ Max Units
SPI Master (AutoBoot) Mode (SPI
CCLK Clock Frequency (Note 15)
CCLK Low Time
CCLK High Time
CCLK Rise Time (Note 16)
CCLK Fall Time (Note 16)
RST
rising to CS falling
High Time Between Transmissions
CS
CS
Falling to CCLK Edge
CS
Falling to CDOUT valid
CCLK Falling to CDOUT valid
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CS
rising
/I2C = 0, SCPM/S = 1, Note 14)
f
sck
t
scl
t
sch
t
r2
t
f2
t
srs
t
csh
t
css
t
dv
t
pd
t
dsu
t
dh
t
clcs
-Fs-kHz
-1/(2*Fs)-ns
-1/(2*Fs)-ns
-12-ns
-12-ns
-42-µs
37 - - µs
5--µs
- - 50 ns
--100ns
80 - - ns
80 - - ns
40 - - ns
CS4812
Notes: 15. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after
RST
is de-asserted and before the control port registers have been initialized.
16. Measured with a 2.2 kΩ pull-up resistor to VD.
RST
CS
CCLK
CDIN
CDOUT
t
srs
t
css
t
t
t
sch
scl
t
t
f2
dsu
t
dh
t
r2
clcs
t
csh
t
dv
t
pd
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing
DS291PP3 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C® SLAVE
(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)
Parameter Symbol Min Max Units
2C®
Slave Mode (SPI/I2C = 1, SCPM/S = 0) (Note 17)
I
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
SCL Low Time
SCL High Time
rising to start condition (Note18)
RST
SDA Hold Time from SCL Falling (Note 19)
Rise Time of Both SDA and SCL
Fall Time of Both SDA and SCL
SCL Falling to CS4812 ACK
SCL Falling to SDA Valid During READ
Time from SCL Rising to REQ
Rising (Note 20)
Rise Time for REQ
Fall Time for REQ
Setup Time for Stop Condition
Setup Time for Repeated Start
f
scl
t
buf
t
hdst
t
low
t
high
t
srs
t
hdd
t
sca
t
scsdv
t
scrh
t
t
t
susp
t
sust
t
r
t
f
rr
rf
-100kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
1-ms
0-µs
-1µs
-300ns
-1.3µs
-1.5µs
-2*DSPCLK+10ns
-100ns
-100ns
4.7 - µs
4.7 µs
CS4812
Notes: 17. Use of the I
Semiconductors.
18. Not tested.
19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. DSPCLK frequency is twice the DSP instruction rate.
2
C bus interface requires a license from Philips. I2C is a registered trademark of Philips
10 DS291PP3
CS4812
stop
ACK
LSB
MSBA0A6 A5
ACK
R/W
susp
t
8
7
rr
6
scsdv
t
t
80
sca
t
7
*
scrh
t
* See section 3.5.2.2 for a detailed explanation of REQ behavior
f
t
r
(input)
SCL/CCLK
t
high
t
hdd
t
low
t
hdst
t
rf
t
REQ
6
01
sud
t
start
buf
t
stop
SDA
Control Port Slave Mode Timing
®
C
2
Figure 3. I
DS291PP3 11
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