CIRRUS LOGIC CS44L11 Service Manual

CS44L11

Low Voltage Class-D PWM Headphone Amplifier

Features

 Up to 95 dB Dynamic Range
 1.8 V to 2.4 V Analog and Digital Supplies
 Sample Rates up to 96 kHz
 Digital Tone Control

– 3 Selectable HPF and LPF Corner

Frequencies

– 12 dB Boost for Bass and Treble - 1 dB step

size

 Programmable Digital Volume Control

– +18 to -96 dB in 1 dB steps

 Peak Signal Soft Limiting
 De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
 Selectable Outputs for Each Channel, including

– Channel A: R, L, mono (L + R) / 2, mute
– Channel B: R, L, mono (L + R) / 2, mute

 PWM PopGuard
 23 mW/Channel into 16 Ω @ 2.4 V

®

Description

The CS44L11 is a complete stereo digital-to-PWM
Class-D audio amplifier system controller including in­terpolation, volume control, and a headphone amplifier
in a 16-pin TSSOP package.

The CS44L11 architecture uses a direct-to-digital ap­proach that maintains digital signal integrity to the final
output filter. This minimizes analog interference effects
that can negatively affect system performance.

The CS44L11 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The PWM
amplifier can achieve greater than 90% efficiency. This
efficiency leads to longer battery life for portable sys­tems, smaller device package, less heat sink
requirements, and smaller power supplies.

The CS44L11 is ideal for portable audio, headphone
amplifiers, and mobile phones.

ORDERING INFORMATION

CS44L11-CZZ, Lead Free -10 to 70 °C 16-pin TSSOP

SCL/DIF0

Control Port

Digital Volume

SDIN

SCLK
LRCK

Serial
Audio

Port

Control,

Bass/Treble

Boost,

Compression

Limiting,

De-emphasis

RST

Preliminary Product Information

http://www.cirrus.com

SDA/DEM

Interpolation

Input Sampling Rate

LRCLK/MCLK Ratio

MCLK

Multibit ∆Σ

Modulator with

Correction

Multibit ∆Σ

Modulator with

Correction

VD

PWM

Conversion

PWM

Conversion

Level

Shifter

Level

Shifter

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

VA_HPA

HP_A

GND_HPA

VA_HPB

HP_B

GND_HPB

JULY '05

DS640PP4

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4

PERFORMANCE SPECIFICATIONS....................................................................................................5

SWITCHING CHARACTERISTICS........................... .... ... ... ... .......................................................... .....8

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .................... ... ... ... ..................9

2. TYPICAL CONNECTION DIAGRAMS ... ... ... .... ... .......................................................... ... ... .... ... ... ... ...10

3. REGISTER QUICK REFERENCE ...................... ... .... ... ... ... .... ... ... ... ... .... ... ... ................................... 12

4. REGISTER DESCRIPTIONS ............................................... ... .... ... ... ... ................................................ 13

4.1 Power and Muting Control (address 02h) .....................................................................................13

4.1.1 Soft Ramp and Zero Cross Control (SZC) .......................................................................13

4.1.2 Power Down (PDN) ......................................................................................................... 13

4.1.3 Float Output (FLT) .......................................................................................................... 13

4.1.4 Ramp-Up Bypass (RUPBYP) ........................................................................................... 14

4.1.5 Ramp-Down Bypass (RDNBYP) ...................................................................................... 14

4.2 Channel A Volume Control (address 03h) (VOLA) .............................. ... ... ... .... ... ... ... ................... 14

4.3 Channel B Volume Control (address 04h) (VOLB) .............................. ... ... ... .... ... ... ... ................... 14

4.4 Tone Control (address 05h) .......................................................................................................... 15

4.4.1 Bass Boost Level (BB) ..................................................................................................... 15

4.4.2 Treble Boost Level (TB) ................................................................................................... 15

4.5 Mode Control 1 (address 06h) ...................................................................................................... 15

4.5.1 Bass Boost Corner Frequency (BBCF) ............................................................................ 16

4.5.2 Treble Boost Corner Frequency (TBCF) .......................................................................... 16

4.5.3 Tone Control Mode (TC) .................................................................................................. 17

4.5.4 Tone Control Enable (TC_EN) ........................................................................................ 17

4.5.5 Peak Signal Limiter Enable (LIM_EN) ............................................................................. 17

4.6 Limiter Attack Rate (address 07h) (ARATE) ................................................................................. 18

4.7 Limiter Release Rate (address 08h) (RRATE) ..... ... ... .... ... ...................................................... 18

4.8 Volume and Mixing Control (address 09h) ...................................................................................19

4.8.1 Ramp Speed (RMP_SP) .. ... .......................................................... ... .... ... ... ... ... .... ... ... ... ... 19

4.8.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 19

4.9 Mode Control 2 (address 0Ah) ..................................................................................................... 20

4.9.1 Master Clock Divide Enable (MCLKDIV) ......................................................................... 20

4.9.2 Clock Divide (CLKDIV) ..................................................................................................... 20

4.9.3 Double-Speed Mode (DBS) ............................................................................................. 21

4.9.4 Frequency Shift (FRQSFT) .............................................................................................. 21

4.9.5 De-Emphasis Control (DEM) .......................................................................................... 22

4.10 Mode Control 3 (address 0Bh) ................................................................................................... 23

4.10.1 Digital Interface Formats (DIF) ....................................................................................... 23

4.10.2 Channel A Volume = Channel B Volume (A=B) ....................... ............. ............. ............ 23

4.10.3 Volume Control Bypass (VCBYP) .................................................................................. 23

4.10.4 Control Port Enable (CP_EN) ............................................... ... ... ... .... ... ... ... ... .... ... .........23

4.10.5 Freeze (FREEZE) .......................................... ... .... ... ... ... ... .... ... ... ... ................................ 24

4.11 Revision Indicator (address 0Ch)[Read Only] ...........................................................................24

5. PIN DESCRIPTION ........................... ... ... .......................................................... ... ................................ 25

6. APPLICATIONS ................................................................................................................................. 26

6.1 Grounding and Power Supply Decoupling .................................................................................... 26

6.2 Clock Modes ................................................................................................................................. 26

6.3 De-Emphasis ................................................................................................................................ 26

6.4 PWM PopGuard Transient Control ...............................................................................................26

6.5 Recommended Power-Up Sequence ........................................................................................... 27

6.5.1 Stand-Alone Mode ........................................................................................................

6.5.2 Control Port Mode ............................................................................................................ 27

7. CONTROL PORT INTERFACE ........................................... ... .... ......................................................... 28

CS44L11

... 27

2 DS640PP4

7.1 I²C Format ............................................. .... ... ... ... .... ......................................................................28

7.1.1 Writing in I²C Format ........................................................................................................28

7.1.2 Reading in I²C Format ...................................................................................................... 28

7.2 Memory Address Pointer (MAP) ................................................................................................. 28

7.2.1 INCR (Auto Map Increment Enable) ................................................................................ 28

7.2.2 MAP3-0 (Memory Address Pointer) ................................................................................. 29

8. PARAMETER DEFINITIONS ............................................................................................................... 32

9. REFERENCES .....................................................................................................................................32

10. PACKAGE DIMENSIONS .................................................................................................................33

11. REVISION HISTORY ......................................................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Audio Data Interface Timing...............................................................................................8

Figure 2. Control Port Timing - I²C Format................................................................................................... 9

Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode..................... ... .... ... ... ... ... .... ... ...... ... 10

Figure 4. Typical CS44L11 Connection Diagram Control Port Mode............................. ... ... ... ... .... ... ... ... ... 11

Figure 5. Dynamics Control Block Diagram ...............................................................................................20

Figure 6. De-Emphasis Curve....................................................................................................................22

Figure 7. Control Port Timing, I²C Format.................................................................................................. 29

Figure 8. Single-Speed Stopband Rejection..............................................................................................29

Figure 9. Single-Speed Transition Band....................................................................................................29

Figure 10. Single-Speed Transition Band (Detail)......................................................................................29

Figure 11. Single-Speed Passband Ripple ................................................................................................29

Figure 12. Double-Speed Stopband Rejection........................................................................... .... ............30

Figure 13. Double-Speed Transition Band................................................................................................. 30

Figure 14. Double-Speed Transition Band (Detail) .................................................................................... 30

Figure 15. Double-Speed Passband Ripple............................................................................................... 30

Figure 16. Left-Justified, up to 24-Bit Data................................................................................................. 31

Figure 17. Right-Justified, 24-Bit Data ....................................................................................................... 31

Figure 18. I²S, Up to 24-Bit Data................................................................................................................31

Figure 19. Right-Justified, 16-Bit Data ....................................................................................................... 31

CS44L11

LIST OF TABLES

Table 1. Register Quick Reference............................................................................................................12

Table 2. Example Volume Settings............................................................................................................ 14

Table 3. Example Bass Boost Settings...................................................................................................... 15

Table 4. Example Treble Boost Settings....................................................................................................15

Table 5. Base Boost Corner Frequencies in Single-Speed Mode.............................................................. 16

Table 6. Base Boost Corner Frequencies in Double-Speed Mode ............................................................ 16

Table 7. Treble Boost Corner Frequencies in Single-Speed Mode......... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 16

Table 8. Example Limiter Attack Rate Settings..........................................................................................18

Table 9. Example Limiter Release Rate Settings....................................................................................... 18

Table 10. ATAPI Decode .... ... .... ... .......................................................... ... ................................................ 19

Table 11. Single-Speed Clock Modes - Control Port Mode ....... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 21

Table 12. Single-Speed Clock Modes - Stand-Alone Mode....................................................... .... ... ... ... ... 21

Table 13. Double-Speed Clock Modes - Control Port Mode......................................................................22

Table 14. Digital Interface Format (Stand-Alone Mode).......................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 25

Table 15. Revision History............................... ... .... ... ... ... .... ... ... ................................................................34

DS640PP4 3

CS44L11

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per­formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V)

Parameters Symbol Min Typ Max Units

DC Power Supplies: Headphone

Digital

Ambient Temperature

VA_HPx

VD

T

A

1.7

1.7

-

-

2.5

2.5

V
V

-10 - 70 °C

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaran te e d at th es e extremes.)

Parameters Symbol Min Max Units

DC Power Supplies: Headphone

Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage

Ambient Operating Temperature (power applied)
Storage Temperature

VA_HPx

VD

I

in

V

IND

T

A

T

stg

-0.3

-0.3

3.0

3.0

±10 mA

-0.3 VD + 0.4 V

-55 125 °C

-65 150 °C

V
V

4 DS640PP4

CS44L11

PERFORMANCE SPECIFICATIONS

(Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless
otherwise specified; Fs for Single-Speed Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double-Speed Mode =
96 kHz, SCLK = 6.144 MHz. Test load RL= 16 Ω, CL = 10 pF. Performance results are measured in production
using a 4700 µF capacitor on the VA_HPx pins. Results will be degraded if smaller value capacitors are used.)

Parameter Symbol Min Typ Max Unit

Headphone Output Dynamic Performance for VD = VA_HPx = 2.4 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dBFS

-20 dBFS

-60 dBFS

Interchannel Isolation (1 kHz)

THD+N -

Headphone Output Dynamic Performance for VD = VA_HPx = 1.8 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz)

THD+N -

PWM Headphone Output

Full-Scale Headphone Output Voltage

Headphone Output Quiescent Voltage

Interchannel Gain Mismatch
Modulation Index
Maximum Headphone Output VA_HPx=2.4 V

RMS AC-Current VA_HPx=1.8 V

I

HP

90
88
88
86

95
93
93
91

-60

-

-

-73

-33

-

-

-

-

-55

-

-

-TBD-dB

87
85
85
83

92
90
90
88

-55

-

-

-70

-30

-

-

-

-

-50

-

-

-60-dB

-0.75 x

-Vpp

VA_HP

- 0.5 x

-VDC

VA_HP

-0.1-dB

--85%

-

-

38
28

-

-

dB
dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

dB
dB
dB

mA
mA

Single-Speed Mode Double-Speed Mode

Parameter

Symbol Min Typ Max Min Typ Max Unit

Digital Filter Response (Note 1))

Passband to -0.05 dB corner

(Note 2) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 3)

StopBand
StopBand Attenuation (Note 4)
Group Delay

tgd - 9/Fs - - 4/Fs - s

0

-

0

-

-

-

.4535

-

.4998

­0
0

-

-

-

­.4426
.4984

Fs
Fs
Fs

-.02 - +.08 0 - +0.11 dB

.5465 - - .577 - - Fs

50 - - 55 - - dB

DS640PP4 5

CS44L11

Single-Speed Mode Double-Speed Mode

Parameter

Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Notes:

1. Filter response is not tested but is guaranteed by design.

2. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 8-15) have been
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

3. Referenced to a 1 kHz, full-scale sine wave.

4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is not available in Double-Speed Mode.

Symbol Min Typ Max Min Typ Max Unit

-

--±0.36/Fs

-

-

-

-

-

-

-

-

+.2/-.1

+.05/-.14

+0/-.22

--±1.39/Fs
±0.23/Fs--

(Note 5) dB

s
s

dB
dB

6 DS640PP4

DIGITAL CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance

V

IH

V

IL

I

in

0.7 x VD - - V

POWER AND THERMAL CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V. HP_x outputs unloaded.)

Parameters Symbol Min Typ Max Units

Power Down (Note 6)

Power Supply Current VD = VA_HPx = 2.4 V

VD = VA_HPx = 1.8 V

Normal Operation (Note 7)

Power Supply Current VD = VA_HPx = 2.4 V

VD = VA_HPx = 1.8 V

Total Power Dissipation- VD = VA_HPx = 2.4 V
Normal Operation

Maximum Headphone Power Output
(1 kHz full-scale sine wave VA_HPx = 2.4V
into 16 Ω load) VA_HPx = 1.8V

Power Supply Rejection Ratio
Package Thermal Resistance

(Note 6) VD = VA_HPx = 1.8 V

PSRR - 0 - dB

θ

JA

CS44L11

--0.3 x VDV

--±10µA

-8-pF

-

-

-

-

-

-

-

-

-75-°C/Watt

380
110

14

9

34
16

23
13

-

-

-

-

-

-

-

-

µA
µA

mA
mA

mW
mW

mW
mW

Notes:

6. Power Down Mode is defined as RST

7. Normal operation is defined as RST = HI.

= LOW with all clocks and data lines held static.

DS640PP4 7

SWITCHING CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

Input Sample Rate Single-Speed Mode

Double-Speed Mode

MCLK Duty Cycle
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period Single-Speed Mode

Double-Speed Mode

SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time

Fs
Fs

t

sclkl

t

sclkh

t

sclkw

t

sclkw

t

slrd

t

slrs

t

sdlrs

t

sdh

CS44L11

8

50
40 50 60 %
40 50 60 %
20 - - ns
20 - - ns

1

---------------------­128()Fs

1

------------------­64()Fs

20 - - ns
20 - - ns
20 - - ns
20 - - ns

-

-

50

100

--ns

--ns

kHz
kHz

LRCK

SCLK

SDIN

t

t

slrd

t

sclkw

t

sdlrs

Figure 1. Serial Audio Data Interface Timing

slrs

t

sclkl

t

sdh

t

sclkh

8 DS640PP4

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

p

(GND = 0 V; all voltages with respect to 0 V.)

Parameter Symbol Min Max Unit

SCL Clock Frequency
RST Rising Edge to Start

Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 8)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling (Note 9)

Notes:

8. Data must be held for sufficient time to bridge the transition time, t

9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

5

---------------------

10. for Single-Speed Mode and for Double-Speed Mode.

256 Fs×

5

--------------------­128 Fs×

f

scl

t

irs

t

buf

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

trc, t
tfc, t

t

susp

t

ack

rc
fc

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

-300ns

4.7 - µs

- (Note 10) ns

, of SCL.

fc

CS44L11

RST

t

SDA

SCL

irs

Stop Start

t

buf

t

hdst

t

low

t

high

t

hdd

t

sud

t

ack

Repeated

Start

t

t

sust

t

hdst

Stop

rd

t

t

rc

t

fd

fc

t

sus

Figure 2. Control Port Timing - I²C Format

DS640PP4 9

2. TYPICAL CONNECTION DIAGRAMS

1.8 to 2.4 V
Supply

Low ESR
Tantalum

100µF

+

1.0µF 0.1µF

VA_HPA

7

VD

12 13

VA_HPB

CS44L11

1.8 to 2.4 V
Supply

5

+

1.0µF 0.1µF

Digital
A

udio

Source

Mode

Control

* Filter component values shown are for a 16 Ω load. Please see the CDB44L11 datasheet for information

VD

CS44L11

4

MCLK

3

SCLK

2

LRCK

1

SDIN

9

DEM

16

RST

8

DIF0

10

on how to calculate filter values for other loads.

15

HP_A

HP_B

G

NDGNDGND

6

11

14

100 µH

100 µH

0.22
µF

0.22
µF

220 µF

+

+

220 µF

Ω

16

Headphones

Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode

10 DS640PP4

.8 to 2.4V

Supply

100µF

Low ESR
Tantalum

CS44L11

+

1.0µF 0.1µF

7

VD

12 13

VA_HPA

VA_HPB

1.8 to 2.4 V
Supply

1.8 to 2.4 V
Supply

5

+

1.0µ F 0.1µF

Digital

A

udio

Source

Rpullup

Control

Logic

* Filter component values shown are for a 16

VD

4

MCLK

3

SCLK

2

LRCK

1

SDIN

9

SDA

8

SCL

16

RST

10

mation on how to calculate filter values for other loads.

CS44L11

11

HP_A

14

HP_B

G

NDGNDGND

15

Ω load. Please see the CDB44L11 datasheet for infor-

6

100 µH

100 µH

0.22
µF

0.22
µF

220 µF

+

+

220 µF

Ω

16

Headphones

Figure 4. Typical CS44L11 Connection Diagram Control Port Mode

DS640PP4 11

CS44L11

3. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

Power and Muting

2h

Control

Channel A

3h

Volume Control

Channel B

4h

Volume Control

Tone Control

5h

Mode Control 1

6h

Limiter Attack Rate

7h

Limiter Release Rate

8h

Volume and Mixing

9h

Control

Mode Control2

Ah

default

default

default

default

default

default

default

default

SZC1 SZC0 PDN FLT RUPBYP RDNBYP Reserved Reserved

10100000

VOLA7 VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0

00000000

VOLB7 VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0

00000000

BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

00000000

BBCF1 BBCF0 TBCF1 TBCF0 TC1 TC0 TC_EN LIM_EN

00000000

ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

00010000

RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

00100000

Reserved Reserved RMP_SP1RMP_SP0ATAPI3 ATAPI2 ATAPI1 ATAPI0

00011001

mclkdiv CLKDV1 CLKDV0 DBS FRQSFT1FRQSFT0DEM1 DEM0

Mode Control 3

Bh

Revision Indicator

Ch

default

default

default

00000000

DIF1 DIF0 A=B VCBYP CP_EN FREEZE Reserved Reserved

00000000

Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

0000Read

Only

Table 1. Register Quick Reference

Read

Only

Read

Only

Read

Only

12 DS640PP4

CS44L11

4. REGISTER DESCRIPTIONS

4.1 Power and Muting Control (address 02h)

76543210

SZC1 SZC0 PDN FLT RUPBYP RDNBYP Reserved Reserved

10100000

4.1.1 Soft Ramp and Zero Cross Control (SZC)

Default = 10

00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved

Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.

Ramped Control
Soft Ramp allows level changes, both muting and attenuation, to be implemente d by incrementally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Note: Ramped Control is not available in Double-Speed Mode.

4.1.2 Power Down (PDN)

Default = 1

0 - Disabled
1 - Enabled

Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control

registers are retained in this mode. The powe r-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.

4.1.3 Float Output (FLT)

Default = 0

0 - Disabled
1 - Enabled

Function:
When enabled, this bit will cause the headphone output of the CS44L11 to float when in the power down

state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the

DS640PP4 13

DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the
bias point; however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the tran­sition will be very small, often inaudible. Refer to Section 6.4.

4.1.4 Ramp-Up Bypass (RUPBYP)

Default = 0

0 - Normal
1 - Bypass

Function:
When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the

Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor. When the ramp-up function is bypassed in Single-Ended
applications, there will be an abrupt change in the output signal. Refer to Section 6.4.

4.1.5 Ramp-Down Bypass (RDNBYP)

Default = 0

0 - Disabled
1 - Enabled

Function:

CS44L11

When in normal mode, the duty cycle of the output PWM signal is decreased at a rate deter mined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single-Ended applications to reduce pops in
the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp-down
function is bypassed in Single-Ended applications, there will be an abrupt change in the output signal.
Refer to Section 6.4.

4.2 Channel A Volume Control (address 03h) (VOLA)

4.3 Channel B Volume Control (address 04h) (VOLB)

76543210

VOLx7 VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0

00000000

Default = 0 dB (No attenuation)
Function:
The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to

-96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume
changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB
are equivalent to muting the channel via the ATAPI bits (see Section 4.8.2).

Note: All volume settings greater than +18 dB are interpreted as +18 dB.

Binary Code Decimal Value Volume Setting

00001100 12 +12 dB
00000111 7 +7 dB
00000000 0 0 dB
11000100 -60 -60 dB
10100110 -90 -90 dB

T able 2. Example Volume Settings

14 DS640PP4

CS44L11

4.4 Tone Control (address 05h)

76543210

BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

00000000

4.4.1 Bass Boost Level (BB)

Default = 0 dB (No Bass Boost)
Function:
The level of the shelving Bass Boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB

increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.

Binary Code Decimal Value Boost Setting

0000 0000 0 0 dB
0000 0010 2 +2 dB
0000 0110 6 +6 dB
0000 1001 9 +9 dB
0000 1100 12 +12 dB

Table 3. Example Bass Boost Settings

4.4.2 Treble Boost Level (TB)

Default = 0 dB (No Treble Boost)
Function:
The level of the shelving Treble Boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB

increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB.

Note: Treble Boost is not available in Double-Speed Mode.

Binary Code Decimal Value Boost Setting

0000 0000 0 0 dB
0000 0010 2 +2 dB
0000 0110 6 +6 dB
0000 1001 9 +9 dB
0000 1100 12 +12 dB

Table 4. Example Treble Boost Settings

4.5 Mode Control 1 (address 06h)

76543210

BBCF1 BBCF0 TBCF1 TBCF0 TC1 TC0 TC_EN LIM_EN

00000000

DS640PP4 15

4.5.1 Bass Boost Corner Frequency (BBCF)

Default = 00

00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved

Function:
The Bass Boost corner frequency is user-selectable. The corner frequency is a function of LRCK (sam-

pling frequency), the DBS bit and the BBCF bits as shown in Table 5 and Table 6.

CS44L11

BBCF

48 kHz 24 kHz 12 kHz 8 kHz

Fs

00 50 Hz 25 Hz 12.5 Hz 8.33 Hz
01 100 Hz 50 Hz 25 Hz 16.7 Hz
10 200 Hz 100 Hz 50 Hz 33.3 Hz
11 Reserved Reserved Reserved Reserved

Table 5. Base Boost Corner Frequencies in Single-Speed Mode

BBCF

Fs

00 50 Hz 25 Hz 12.5 Hz 8.33 Hz
01 100 Hz 50 Hz 25 Hz 16.7 Hz
10 200 Hz 100 Hz 50 Hz 33.3 Hz
11 Reserved Reserved Reserved Reserved

Table 6. Base Boost Corner Frequencies in Double-Speed Mode

96 kHz 48 kHz 24 kHz 16 kHz

LRCK in Single-Speed Mode (DBS=0)

LRCK in Double-Speed Mode (DBS=1)

4.5.2 Treble Boost Corner Frequency (TBCF)

Default = 00

00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved

Function:
The Treble Boost corner frequency is user selectable. The corne r freq uen cy is a function of LRCK (sam-

pling frequency) and the TBCF bits as shown in Table 7.

Note: Treble Boost is not available in Double-Speed Mode.

TBCF

Fs

00 2kHz 1kHz 0.5kHz 0.33kHz
01 4 kHz 2 kHz 1 kHz 0.67 kHz
10 7 kHz 3.5 kHz 1.75 kHz 1.17 kHz
11 Reserved Reserved Reserved Reserved

Ta bl e 7 . Treble Boost Corner Frequencies in Single -Speed Mode

16 DS640PP4

48 kHz 24 kHz 12 kHz 8 kHz

LRCK in Single-Speed Mode (DBS=0)

4.5.3 Tone Control Mode (TC)

Default = 00

00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)

Function:
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.

The user-defined settings from the Bass and Treble Boost Level an d Corner Frequency registers are used
when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to Tables 5, 6, and 7).

Note: Treble Boost is not available in Double-Speed Mode.

4.5.4 Tone Control Enable (TC_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:

CS44L11

The Bass Boost and Treble Boost features are active when this function is enabled.

4.5.5 Peak Signal Limiter Enable (LIM_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:
The CS44L11 will limit the maximum signal amplitude to prevent clipping when this function is enabled.

Peak Signal Limiting is performed by firs t decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.

Once the signal has dropped below the clipping level, the attenuation is decreased back to the user-se­lected level, followed by the Bass Boost being increased back to the user-selected level. The release rate
is determined by the Limiter Release Rate register.

Note: The A=B bit should be set to ‘1’ for optimal limiter performance.

DS640PP4 17

CS44L11

4.6 Limiter Attack Rate (address 07h) (ARATE)

76543210

ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

00010000

Default = 10h - 2 LRCK’s per 1/8 dB
Function:
The limiter attack rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value in

the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where {va lue}
is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of change.

A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the
LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 32
00010100 20 1.6
00101000 40 0.8
00111100 60 0.53
01011010 90 0.356

Table 8. Example Limiter Attack Rate Settings

4.7 Limiter Release Rate (address 08h) (RRATE)

76543210

RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

00100000

Default = 20h - 16 LRCK’s per 1/8 dB
Function:
The limiter release rate is user-selec table. Th e rate is a function of sampling frequency, Fs, and the value

in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where
{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of
change.

Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.

Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 512
00010100 20 25
00101000 40 12
00111100 60 8
01011010 90 5

Table 9. Example Limiter Release Rate Settings

18 DS640PP4

CS44L11

4.8 Volume and Mixing Control (address 09h)

76543210

Reserved Reserved RMP_SP1 RMP_SP0 ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

4.8.1 Ramp Speed (RMP_SP)

Default = 01

00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds

Function:
This feature is used in Single-Ended applications to reduce pops in the output caused by the DC-blocking

capacitor. When in Control Port Mode, the Ramp Speed sets the time for the PWM signal to linearly ramp
up and down from the bias point (50% PWM duty cycle). Refer to Section 6.4.

4.8.2 ATAPI Channel Mixing and Muting (ATAPI)

Default = 1001 - HP_A = L, HP_B = R (Stereo)
Function:
The CS44L11 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to

Table 10 and Figure 5 for additional information.

Note: All mixing functions occur prior to the digital volume control.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 HP_A HP_B

0000 MUTE MUTE
0001 MUTE R
0010 MUTE L
0011 MUTE [(L+R)/2]
0100 R MUTE
0101 R R
0110 R L
0111 R [(L+R)/2]
1000 L MUTE
1001 L R
1010 L L
1011 L [(L+R)/2]
1100[(L+R)/2] MUTE
1101[(L+R)/2] R
1110[(L+R)/2] L
1111[(L+R)/2][(L+R)/2]

Table 10. ATAPI Decode

DS640PP4 19

Left Channel

Audio Data

Right Channel

Audio Data

Channel A

Digital

Volume

Control
& Mute

EQ

Σ

Channel B

Digital

Volume

Control

& Mute

Figure 5. Dynamics Control Block Diagram

EQ

CS44L11

HP_A

HP_B

4.9 Mode Control 2 (address 0Ah)

76543210

mclkdiv CLKDV1 CLKDV0 DBS FRQSFT1 FRQSFT0 DEM1 DEM0

00000000

4.9.1 Master Clock Divide Enable (MCLKDIV)

Default = 0
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signa l by 2 prior to all other

internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and L RCK require­ments. Refer to Tables 11, 12, 13, and Section 6.2.

4.9.2 Clock Divide (CL KDIV)

Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to

Tables 11, 12, 13, and Section 6.2.

20 DS640PP4

4.9.3 Double-Speed Mode (DBS)

Default = 0

0 - Single-Speed
1 - Double-Speed (DBS)

Function:
Single-Speed supports 8 kHz to 50 kHz sample rates and Double-Speed supports 50 kHz to 96 kHz sam-

ple rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the use r’s MCL K and LRCK requ irem ents.
Refer to Tables 11, 12, 13, and Section 6.2.

Note: De-emphasis, ramp control, and treble control are not available in Double-Speed Mode.

4.9.4 Frequency Shift (FRQSFT)

Default = 00
Function:
MCLKDIV, DBS, CLKDIV and FRQSFT are set per the us er’s MCLK and LRCK requirements . Refer to

Tables 11, 12, 13, and Section 6.2.

CS44L11

DBS = 0

MCLKDIV = 0

DBS = 0

MCLKDIV = 1

Switching

LRCK

(kHz)

48 256 12.288 512 24.576 0 0 0 0 384
48 512 24.576 1024 49.152 0 0 1 0

44.1 256 11.2896 512 22.5792 0 0 0 0 352.8

44.1 512 22.5792 1024 45.1584 0 0 1 0
32 512 16.384 1024 32.768 0 1 0 0 512
32 1024 32.768 2048 65.536 0 1 1 0
24 512 12.288 1024 24.576 0 1 0 0 384
24 1024 24.576 2048 49.152 0 1 1 0
12 1024 12.288 2048 24.576 1 0 0 0 384
12 2048 24.576 4096 49.152 1 0 1 0

MCLK/

LRCK

MCLK

(MHz)

MCLK/

LRCK

Table 11. Single-Speed Clock Modes - Control Port Mode

MCLK

(MHz) FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0

PWM

LRCK

(kHz)

48 256 12.288 384
48 512 24.576

44.1 256 11.2896 352.8

44.1 512 22.5792
32 1024 32.768 512
24 1024 24.576 384
12 2048 24.576

Table 12. Single-Speed Clock Modes - Stand-Alone Mode

MCLK/

LRCK

MCLK

(MHz)

Switching

Freq. (kHz)

PWM

Freq.
(kHz)

DS640PP4 21

CS44L11

DBS = 1

MCLKDIV = 0

DBS = 1

MCLKDIV = 1

Switching

LRCK

(kHz)

96 128 12.288 256 24.576 0 0 0 0 384
96 256 24.576 512 49.152 0 0 1 0

88.2 128 11.2896 256 22.5792 0 0 0 0 352.8

88.2 256 22.5792 512 45.1584 0 0 1 0

MCLK/

LRCK

MCLK

(MHz)

MCLK/

LRCK

Table 13. Double-Speed Clock Modes - Control Port Mode

MCLK

(MHz) FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0

4.9.5 De-Emphasis Control (DEM)

Default = 00

00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz

Function:
Selects the appropriate digital filte r to maintain the standard 15 µs/50 µs digital de-emphasis filter re-

sponse at 32, 44.1 or 48 kHz sample rates (see Figure 6).

PWM

Freq.
(kHz)

Note: De-emphasis is not available in Double-Speed Mode.

Gain

dB

T1=50 µs

0dB

T2 = 15 µs

-10dB

F1 F2

3.183 kHz 10.61 kHz

Figure 6. De-Emphasis Curve

Frequency

22 DS640PP4

CS44L11

4.10 Mode Control 3 (address 0Bh)

76543210

DIF1 DIF0 A=B VCBYP CP_EN FREEZE HPSEN Reserved

00000000

4.10.1 Digital Interface Formats (DIF)

Default = 00

00 - I²S
01 - Right Justified, 16 bit
10 - Left Justified
11 - Right Justified, 24 bit

Function:
The required relationship between the Left/Right clock, serial clock and seri al data is defined by the Digital

Interface Format and the options are det aile d in Figures 16 through 19.

4.10.2 Channel A Volume = Channel B Volume (A=B)

Default = 0

0 - Disabled
1 - Enabled

Function:
The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume

Control Bytes when this function is disabled. The volume on both HP_A and HP_B a re determined by the
A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.

4.10.3 Volume Control Bypass (VCBYP)

Default = 0

0 - Disabled
1 - Enabled

Function:
The digital volume control section is bypassed when this function is enabled. This disables the digital vol-

ume control, muting, bass boost, treble boost, limiting, and ATAPI functions.

4.10.4 Control Port Enable (CP_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control Port Mode can

be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg­isters and the pin definitions will conform to Control Port Mode. Refer to Section 6.5.2

.

DS640PP4 23

CS44L11

4.10.5 Freeze (FREEZE)

Default = 0

0 - Disabled
1 - Enabled

Function:
This function allows modifications to be made to the registers without the changes being taking effect until

the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneous­ly, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.

4.11 Revision Indicator (address 0Ch)[Read Only]

76543210

Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

00000000

Default = none

0001 - Revision A
0010 - Revision B
0011 - Revision C
etc.

Function:
This read-only register indicates the revision level of the device.

24 DS640PP4

5. PIN DESCRIPTION

CS44L11

Serial Data SDIN RST Reset

Left/Right Clock

Serial Clock
Master Clock
Digital Power

Ground

Digital Power

SCL/DIF0

SDIN 1

LRCK 2

SCLK 3
MCLK 4 Master Clock (Input) - Clock source for the PWM modulator and digital filters. Tables 11, 12, 13 and

VD 5

GND 6, 10

HP_A
HP_B

VA_HPA
VA_HPB

RST 16

Control Port Definitions

SCL 8

SDA 9

Stand-Alone Definitions

DIF0 8

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
Serial Clock (Input) - Serial clock for the serial audio interface.

14 illustrate several standard audio sample rates and required master clock frequencies.

Digital Power (Input) - Positive power supply for the digital section. Refer to "Specified Operating

7

Conditions"

Ground (Input) - Ground Reference.

& 15

Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be added to

11

suppress high frequency switching noise. A DC blocking capacitor is also required. Refer to Typical

14

Connection Diagrams.
Headphone Amplifier Pow er (Input) - Positive power supply for the headphone amplifier. Refer to

12

"Specified Operating Conditions" for appropriate voltages.

13

Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low. The control port cannot be accessed when Reset is low. See Section 6.5.

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
external pull-up resistor to VD in I²C mode.

Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up
resistor to the logic interface voltage.

Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial clock
and serial data is defined by the Digital Interface Format and the options are detailed below

for appropriate voltages.

LRCK GND Headphone B Ground
SCLK HP_B Headphone B Output

MCLK VA_HPB Headphone B Power

VD VA_HPA Headphone A Power

GND HP_A Headphone A Output

VD GND Headphone A Ground

SCL/DIF0 SDA/DEM SDA/DEM

1
2

3
4
5

6
7

8

16
15

14
13
12

11

10

9

DIF0 DESCRIPTION FIGURE

0 I²S, up to 24-bit data 18
1 Right Justified, 16-bit Data 19

Table 14. Digital Interface Format (Stand-Alone Mode)

DEM 9

DS640PP4 25

De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response at

44.1 kHz sample rates. NOTE: De-emphasis is not available in Double- or Quad-Speed Modes. When
DEM is grounded, de-emphasis is disabled.

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any switching converter, the CS44L11 requires careful attention to power supply and grounding ar­rangements to optimize performance. Figures 3 and 4 show the recommended power arrangem ent with VD
and VA_HPx connected to clean supplies. Decoupling capacitors should be located as close to the device
package as possible. If desired, all supply pins may be connected to the same supply, b ut a decoup ling ca­pacitor should still be used on each supply pin.

6.2 Clock Modes

One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated
by the modulator is dependent on the PWM switching frequency. The systems designer will specify the ex­ternal filter based on this switch ing frequency. The obvious implementation in a digital PWM system is to
directly lock the PWM switching rate to the incoming data sample rate. However, this would require a tun­able filter to attenuate the switching frequency across the range of possible sample rates. To simplify the
external filter design and to accommodate sample rates ranging from 8 kHz to 96 kHz the CS44L11 Con­troller uses several clock modes that keep the PWM switching frequency in a small range.

In Control Port Mode, for operation at a particular sample rate the user selects register settings (refer to

Section 4.9 and Tables 11 and 13) based on their MCLK and MCLK/LRCK parameters. When using

Stand-Alone mode, refer to Tables Tables 12 and 14 for available clock modes.

CS44L11

6.3 De-Emphasis

The CS44L11 includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve. The frequency
response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.

The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis
equalization as a means of noise reduction.

6.4 PWM PopGuard Transient Control

The CS44L11 uses PopGuard® technology to minimize the effects of output transients during po wer-up and
power-down. This technique minimizes the audio transients commonly produced by a single-ended, sin­gle-supply converter when it is implemented with external DC-blocking capacitors connected in series with
the audio outputs.

When the device is initially powered-up, the HP_x outputs are cla mped to GND. Following a delay e ach out­put begins to increase the PWM duty cycle toward the quiescent voltage point. By a speed set by the
RMP_SP bit, the HP_x outputs will later reach the bias point (50% PWM duty cycle), and audio output be­gins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the qui­escent voltage, minimizing the power-up transient.

To prevent transients at power-down, the device must first enter its power-down state. When this occurs,
audio output ceases and the PWM duty cycle is decreased until the HP_x outputs reach GND. The time
required to reach GND is determined by the RMP_SP bits. This allows the DC-blocking capaci tors to slowl y
discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is
ready for the next power-on.

To prevent an audio transient at the next power-on, the DC-blocking capacitor s must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to GND. The time that the device must remain in the pow­er-down state is related to the value of the DC-blocking capacitance and the output lo ad. For example, with

26 DS640PP4

a 220 µF capacitor and a 16 Ω load on the headphone outputs, the minimum power-down time will be ap­proximately 0.4 seconds.

Note that ramp-up and ramp-down period ca n be set to zero with the RUPBY P and RDNBYP bits resp ec­tively.

6.5 Recommended Power-Up Sequence

6.5.1 Stand-Alone Mode

1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.

CS44L11

2. Bring RST
sequence. The control port will be accessible at this time.

high. The device will remain in a low power state and will initiate the Stand-Alone power-up

6.5.2 Control Port Mode

1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and the HP_x lines will remain low.

2. Bring RST
sequence. The control port will be accessible at this time.

3. On the CS44L11 the control port pins are shared with stand-alone configuration pins. To enable the
control port, the user must set the CP_EN bit. This is done by performing an I²C write. Once the
control port is enabled, these pins are dedicated to control port functionality.

To prevent audible artifacts, the CP_EN bit (see Section 4.10.4) should be set prior to the completion of
the Stand-Alone power-up sequence (1024/Fs: approximately 21 ms at Fs=48 kHz). Writing this bit will
halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the
CP_EN bit can be set any time after RST
er-up sequence has completed can cause audible artifacts.

high. The device will remain in a low power state and will initiate the Stand-Alone power-up

goes high; however, setting this bit after the Stand-Alone pow-

DS640PP4 27

CS44L11

7. CONTROL PORT INTERFACE

The control port is used to load all the internal settings. The operation of the control port may be completely asyn­chronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.

The CS44L11 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB.
If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written, allowing block reads or writes of successive registers.

7.1 I²C Format

SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to
data relationship as shown in Figure 7. The receiving device should send an acknowledge (ACK) after each
byte received. The chip address is 0010011.

Note: MCLK is required during all I²C transactions.

7.1.1 Writing in I²C Format

To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W
Pointer, MAP, which selects the register to be read or written . The MAP is then fo llowed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS44L11 to ac­knowledge between each byte. To end the transaction, send a STOP condition.

bit (low for a write). The next byte is the Memory Address

7.1.2 Reading in I²C Format

To communicate with the CS44L11, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.

bit (high for a read). The contents of the register pointed to

7.2 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

7.2.1 INCR (Auto Map Increment Enable)

Default = ‘0’
0 - Disabled
1 - Enabled

28 DS640PP4

7.2.2 MAP3-0 (Memory Address Pointer)

Default = ‘0000’

R/W

SDA

SCL

0010011

ACK

DATA
1-8

Note 1

ACK

DATA
1-8

CS44L11

ACK

Start

Stop

Note: If operation is a write,this byte contains the M emo ry Address Pointer, MAP.

Figure 7. Control Port Timing, I²C Format

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normalize d to Fs)

Figure 8. Single-Speed Stopband Rejection Figure 9. Single-Speed Transitio n Band

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100

0.4 0.42 0. 44 0.46 0.48 0. 5 0. 52 0.54 0. 56 0.58 0. 6

Frequency (normalized to Fs)

0

-1

-2

-3

-4

-5

-6

Amplitude (dB)

-7

-8

-9

-10

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

0.5

0.4

0.3

0.2

0.1

0

-0.1

Amplitude (dB)

-0.2

-0.3

-0.4

-0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (normalized to Fs)

Figure 10. Single-Speed Transition Band (Detail) Figure 11. Single-Speed Passband Ripple

DS640PP4 29

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normalized to Fs)

Figure 12. Double-Speed Stopband Rejection Figure 13. Double-Speed Transition Band

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100

0.4 0.42 0. 44 0.46 0.48 0. 5 0. 52 0.54 0. 56 0.58 0. 6

Frequency (normalized to Fs)

CS44L11

0

-1

-2

-3

-4

-5

-6

Amplitude (dB)

-7

-8

-9

-10

0.45 0. 46 0.47 0. 48 0.49 0.5 0.51 0. 52 0.53 0. 54 0. 55

Frequency (normali zed to Fs)

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40

-0.50

0.00 0.05 0.10 0.15 0.20 0. 25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Figure 14. Double-Speed Transition Band (Detail) Figure 15. Double-Speed Passband Ripple

30 DS640PP4

CS44L11

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

Left Channel

+5 +4

Figure 16. Left-Justified, up to 24-Bit Data

LRCK

SCLK

SDATA

0

Left Channel

23 22 21 20 19 18

32 clocks

Figure 17. Right-Justified, 24-Bit Data

LRCK

SCLK

Left Channel

LSB

Right Channel

+3 +2 +1

MSB

-1 -2 -3 -4

65432107

23 22 21 20 19 18

+5 +4

Right Channel

Right Channel

LSB

65432107

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

+5 +4

LRCK

SCLK

SDATA

Left Channel

15 14 13 12 11 10

32 clocks

Figure 19. Right-Justified, 16-Bit Data

LSB

MSB

-1 -2 -3 -4

Figure 18. I²S, Up to 24-Bit Data

6543210987

+5 +4

Right Channel

15 14 13 12 11 10

+3 +2 +1

LSB

6543210987

DS640PP4 31

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are be low the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signa l applied to the other channel. Units in d eci­bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

CS44L11

9. REFERENCES

“The I²C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

32 DS640PP4

10.PACKAGE DIMENSIONS

16L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

CS44L11

1

23

TOP VIEW

D

E

e

2

b

SIDE VIEW

A2

A1

A

SEATING

PLANE

L

1

E1

END VIEW

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.193 0.1969 0.201 4.90 5.00 5.10 1

E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.065 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

µ

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters

Notes:

1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mis­match and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall b e 0.13 mm
total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimen­sion “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS640PP4 33

11.REVISION HISTORY

Release Date Changes

PP1 April 2004 Initial Preliminary Release
PP2

PP3 March 2005

PP4 July 2005

September

2004

Added Lead-free device ordering info rm at ion .

-Corrected “Features” on page 1.

-Corrected Table 11, “Single-Speed Clock Modes - Control Port Mode,” on page 21.

-Corrected Table 12, “Single-Speed Clock Modes - Stand-Alone Mode,” on page 21.

-Corrected Table 13, “Double-Speed Clock Modes - Control Port Mode,” on page 22.
Added last two rows to Table 13, “Double-Speed Clock Modes - Control Port Mode,” on

page 22.

T able 15. Revision History

CS44L11

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To find the one nearest to you go to www.cirrus.com

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34 DS640PP4