CIRRUS LOGIC CS44L11 Service Manual

CS44L11

Low Voltage Class-D PWM Headphone Amplifier

Features

 Up to 95 dB Dynamic Range
 1.8 V to 2.4 V Analog and Digital Supplies
 Sample Rates up to 96 kHz
 Digital Tone Control

– 3 Selectable HPF and LPF Corner

Frequencies

– 12 dB Boost for Bass and Treble - 1 dB step

size

 Programmable Digital Volume Control

– +18 to -96 dB in 1 dB steps

 Peak Signal Soft Limiting
 De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
 Selectable Outputs for Each Channel, including

– Channel A: R, L, mono (L + R) / 2, mute
– Channel B: R, L, mono (L + R) / 2, mute

 PWM PopGuard
 23 mW/Channel into 16 Ω @ 2.4 V

®

Description

The CS44L11 is a complete stereo digital-to-PWM
Class-D audio amplifier system controller including in­terpolation, volume control, and a headphone amplifier
in a 16-pin TSSOP package.

The CS44L11 architecture uses a direct-to-digital ap­proach that maintains digital signal integrity to the final
output filter. This minimizes analog interference effects
that can negatively affect system performance.

The CS44L11 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The PWM
amplifier can achieve greater than 90% efficiency. This
efficiency leads to longer battery life for portable sys­tems, smaller device package, less heat sink
requirements, and smaller power supplies.

The CS44L11 is ideal for portable audio, headphone
amplifiers, and mobile phones.

ORDERING INFORMATION

CS44L11-CZZ, Lead Free -10 to 70 °C 16-pin TSSOP

SCL/DIF0

Control Port

Digital Volume

SDIN

SCLK
LRCK

Serial
Audio

Port

Control,

Bass/Treble

Boost,

Compression

Limiting,

De-emphasis

RST

Preliminary Product Information

http://www.cirrus.com

SDA/DEM

Interpolation

Input Sampling Rate

LRCLK/MCLK Ratio

MCLK

Multibit ∆Σ

Modulator with

Correction

Multibit ∆Σ

Modulator with

Correction

VD

PWM

Conversion

PWM

Conversion

Level

Shifter

Level

Shifter

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright © Cirrus Logic, Inc. 2005

(All Rights Reserved)

VA_HPA

HP_A

GND_HPA

VA_HPB

HP_B

GND_HPB

JULY '05

DS640PP4

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4

PERFORMANCE SPECIFICATIONS....................................................................................................5

SWITCHING CHARACTERISTICS........................... .... ... ... ... .......................................................... .....8

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .................... ... ... ... ..................9

2. TYPICAL CONNECTION DIAGRAMS ... ... ... .... ... .......................................................... ... ... .... ... ... ... ...10

3. REGISTER QUICK REFERENCE ...................... ... .... ... ... ... .... ... ... ... ... .... ... ... ................................... 12

4. REGISTER DESCRIPTIONS ............................................... ... .... ... ... ... ................................................ 13

4.1 Power and Muting Control (address 02h) .....................................................................................13

4.1.1 Soft Ramp and Zero Cross Control (SZC) .......................................................................13

4.1.2 Power Down (PDN) ......................................................................................................... 13

4.1.3 Float Output (FLT) .......................................................................................................... 13

4.1.4 Ramp-Up Bypass (RUPBYP) ........................................................................................... 14

4.1.5 Ramp-Down Bypass (RDNBYP) ...................................................................................... 14

4.2 Channel A Volume Control (address 03h) (VOLA) .............................. ... ... ... .... ... ... ... ................... 14

4.3 Channel B Volume Control (address 04h) (VOLB) .............................. ... ... ... .... ... ... ... ................... 14

4.4 Tone Control (address 05h) .......................................................................................................... 15

4.4.1 Bass Boost Level (BB) ..................................................................................................... 15

4.4.2 Treble Boost Level (TB) ................................................................................................... 15

4.5 Mode Control 1 (address 06h) ...................................................................................................... 15

4.5.1 Bass Boost Corner Frequency (BBCF) ............................................................................ 16

4.5.2 Treble Boost Corner Frequency (TBCF) .......................................................................... 16

4.5.3 Tone Control Mode (TC) .................................................................................................. 17

4.5.4 Tone Control Enable (TC_EN) ........................................................................................ 17

4.5.5 Peak Signal Limiter Enable (LIM_EN) ............................................................................. 17

4.6 Limiter Attack Rate (address 07h) (ARATE) ................................................................................. 18

4.7 Limiter Release Rate (address 08h) (RRATE) ..... ... ... .... ... ...................................................... 18

4.8 Volume and Mixing Control (address 09h) ...................................................................................19

4.8.1 Ramp Speed (RMP_SP) .. ... .......................................................... ... .... ... ... ... ... .... ... ... ... ... 19

4.8.2 ATAPI Channel Mixing and Muting (ATAPI) .................................................................... 19

4.9 Mode Control 2 (address 0Ah) ..................................................................................................... 20

4.9.1 Master Clock Divide Enable (MCLKDIV) ......................................................................... 20

4.9.2 Clock Divide (CLKDIV) ..................................................................................................... 20

4.9.3 Double-Speed Mode (DBS) ............................................................................................. 21

4.9.4 Frequency Shift (FRQSFT) .............................................................................................. 21

4.9.5 De-Emphasis Control (DEM) .......................................................................................... 22

4.10 Mode Control 3 (address 0Bh) ................................................................................................... 23

4.10.1 Digital Interface Formats (DIF) ....................................................................................... 23

4.10.2 Channel A Volume = Channel B Volume (A=B) ....................... ............. ............. ............ 23

4.10.3 Volume Control Bypass (VCBYP) .................................................................................. 23

4.10.4 Control Port Enable (CP_EN) ............................................... ... ... ... .... ... ... ... ... .... ... .........23

4.10.5 Freeze (FREEZE) .......................................... ... .... ... ... ... ... .... ... ... ... ................................ 24

4.11 Revision Indicator (address 0Ch)[Read Only] ...........................................................................24

5. PIN DESCRIPTION ........................... ... ... .......................................................... ... ................................ 25

6. APPLICATIONS ................................................................................................................................. 26

6.1 Grounding and Power Supply Decoupling .................................................................................... 26

6.2 Clock Modes ................................................................................................................................. 26

6.3 De-Emphasis ................................................................................................................................ 26

6.4 PWM PopGuard Transient Control ...............................................................................................26

6.5 Recommended Power-Up Sequence ........................................................................................... 27

6.5.1 Stand-Alone Mode ........................................................................................................

6.5.2 Control Port Mode ............................................................................................................ 27

7. CONTROL PORT INTERFACE ........................................... ... .... ......................................................... 28

CS44L11

... 27

2 DS640PP4

7.1 I²C Format ............................................. .... ... ... ... .... ......................................................................28

7.1.1 Writing in I²C Format ........................................................................................................28

7.1.2 Reading in I²C Format ...................................................................................................... 28

7.2 Memory Address Pointer (MAP) ................................................................................................. 28

7.2.1 INCR (Auto Map Increment Enable) ................................................................................ 28

7.2.2 MAP3-0 (Memory Address Pointer) ................................................................................. 29

8. PARAMETER DEFINITIONS ............................................................................................................... 32

9. REFERENCES .....................................................................................................................................32

10. PACKAGE DIMENSIONS .................................................................................................................33

11. REVISION HISTORY ......................................................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Audio Data Interface Timing...............................................................................................8

Figure 2. Control Port Timing - I²C Format................................................................................................... 9

Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode..................... ... .... ... ... ... ... .... ... ...... ... 10

Figure 4. Typical CS44L11 Connection Diagram Control Port Mode............................. ... ... ... ... .... ... ... ... ... 11

Figure 5. Dynamics Control Block Diagram ...............................................................................................20

Figure 6. De-Emphasis Curve....................................................................................................................22

Figure 7. Control Port Timing, I²C Format.................................................................................................. 29

Figure 8. Single-Speed Stopband Rejection..............................................................................................29

Figure 9. Single-Speed Transition Band....................................................................................................29

Figure 10. Single-Speed Transition Band (Detail)......................................................................................29

Figure 11. Single-Speed Passband Ripple ................................................................................................29

Figure 12. Double-Speed Stopband Rejection........................................................................... .... ............30

Figure 13. Double-Speed Transition Band................................................................................................. 30

Figure 14. Double-Speed Transition Band (Detail) .................................................................................... 30

Figure 15. Double-Speed Passband Ripple............................................................................................... 30

Figure 16. Left-Justified, up to 24-Bit Data................................................................................................. 31

Figure 17. Right-Justified, 24-Bit Data ....................................................................................................... 31

Figure 18. I²S, Up to 24-Bit Data................................................................................................................31

Figure 19. Right-Justified, 16-Bit Data ....................................................................................................... 31

CS44L11

LIST OF TABLES

Table 1. Register Quick Reference............................................................................................................12

Table 2. Example Volume Settings............................................................................................................ 14

Table 3. Example Bass Boost Settings...................................................................................................... 15

Table 4. Example Treble Boost Settings....................................................................................................15

Table 5. Base Boost Corner Frequencies in Single-Speed Mode.............................................................. 16

Table 6. Base Boost Corner Frequencies in Double-Speed Mode ............................................................ 16

Table 7. Treble Boost Corner Frequencies in Single-Speed Mode......... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 16

Table 8. Example Limiter Attack Rate Settings..........................................................................................18

Table 9. Example Limiter Release Rate Settings....................................................................................... 18

Table 10. ATAPI Decode .... ... .... ... .......................................................... ... ................................................ 19

Table 11. Single-Speed Clock Modes - Control Port Mode ....... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 21

Table 12. Single-Speed Clock Modes - Stand-Alone Mode....................................................... .... ... ... ... ... 21

Table 13. Double-Speed Clock Modes - Control Port Mode......................................................................22

Table 14. Digital Interface Format (Stand-Alone Mode).......................... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 25

Table 15. Revision History............................... ... .... ... ... ... .... ... ... ................................................................34

DS640PP4 3

CS44L11

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per­formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V)

Parameters Symbol Min Typ Max Units

DC Power Supplies: Headphone

Digital

Ambient Temperature

VA_HPx

VD

T

A

1.7

1.7

-

-

2.5

2.5

V
V

-10 - 70 °C

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the
device. Normal operation is not guaran te e d at th es e extremes.)

Parameters Symbol Min Max Units

DC Power Supplies: Headphone

Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage

Ambient Operating Temperature (power applied)
Storage Temperature

VA_HPx

VD

I

in

V

IND

T

A

T

stg

-0.3

-0.3

3.0

3.0

±10 mA

-0.3 VD + 0.4 V

-55 125 °C

-65 150 °C

V
V

4 DS640PP4

CS44L11

PERFORMANCE SPECIFICATIONS

(Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless
otherwise specified; Fs for Single-Speed Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double-Speed Mode =
96 kHz, SCLK = 6.144 MHz. Test load RL= 16 Ω, CL = 10 pF. Performance results are measured in production
using a 4700 µF capacitor on the VA_HPx pins. Results will be degraded if smaller value capacitors are used.)

Parameter Symbol Min Typ Max Unit

Headphone Output Dynamic Performance for VD = VA_HPx = 2.4 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dBFS

-20 dBFS

-60 dBFS

Interchannel Isolation (1 kHz)

THD+N -

Headphone Output Dynamic Performance for VD = VA_HPx = 1.8 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dB

-20 dB

-60 dB

Interchannel Isolation (1 kHz)

THD+N -

PWM Headphone Output

Full-Scale Headphone Output Voltage

Headphone Output Quiescent Voltage

Interchannel Gain Mismatch
Modulation Index
Maximum Headphone Output VA_HPx=2.4 V

RMS AC-Current VA_HPx=1.8 V

I

HP

90
88
88
86

95
93
93
91

-60

-

-

-73

-33

-

-

-

-

-55

-

-

-TBD-dB

87
85
85
83

92
90
90
88

-55

-

-

-70

-30

-

-

-

-

-50

-

-

-60-dB

-0.75 x

-Vpp

VA_HP

- 0.5 x

-VDC

VA_HP

-0.1-dB

--85%

-

-

38
28

-

-

dB
dB
dB
dB

dB
dB
dB

dB
dB
dB
dB

dB
dB
dB

mA
mA

Single-Speed Mode Double-Speed Mode

Parameter

Symbol Min Typ Max Min Typ Max Unit

Digital Filter Response (Note 1))

Passband to -0.05 dB corner

(Note 2) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 3)

StopBand
StopBand Attenuation (Note 4)
Group Delay

tgd - 9/Fs - - 4/Fs - s

0

-

0

-

-

-

.4535

-

.4998

­0
0

-

-

-

­.4426
.4984

Fs
Fs
Fs

-.02 - +.08 0 - +0.11 dB

.5465 - - .577 - - Fs

50 - - 55 - - dB

DS640PP4 5

CS44L11

Single-Speed Mode Double-Speed Mode

Parameter

Passband Group Delay Deviation 0 - 40 kHz

0 - 20 kHz

De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

Notes:

1. Filter response is not tested but is guaranteed by design.

2. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 8-15) have been
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

3. Referenced to a 1 kHz, full-scale sine wave.

4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is not available in Double-Speed Mode.

Symbol Min Typ Max Min Typ Max Unit

-

--±0.36/Fs

-

-

-

-

-

-

-

-

+.2/-.1

+.05/-.14

+0/-.22

--±1.39/Fs
±0.23/Fs--

(Note 5) dB

s
s

dB
dB

6 DS640PP4

DIGITAL CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance

V

IH

V

IL

I

in

0.7 x VD - - V

POWER AND THERMAL CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V. HP_x outputs unloaded.)

Parameters Symbol Min Typ Max Units

Power Down (Note 6)

Power Supply Current VD = VA_HPx = 2.4 V

VD = VA_HPx = 1.8 V

Normal Operation (Note 7)

Power Supply Current VD = VA_HPx = 2.4 V

VD = VA_HPx = 1.8 V

Total Power Dissipation- VD = VA_HPx = 2.4 V
Normal Operation

Maximum Headphone Power Output
(1 kHz full-scale sine wave VA_HPx = 2.4V
into 16 Ω load) VA_HPx = 1.8V

Power Supply Rejection Ratio
Package Thermal Resistance

(Note 6) VD = VA_HPx = 1.8 V

PSRR - 0 - dB

θ

JA

CS44L11

--0.3 x VDV

--±10µA

-8-pF

-

-

-

-

-

-

-

-

-75-°C/Watt

380
110

14

9

34
16

23
13

-

-

-

-

-

-

-

-

µA
µA

mA
mA

mW
mW

mW
mW

Notes:

6. Power Down Mode is defined as RST

7. Normal operation is defined as RST = HI.

= LOW with all clocks and data lines held static.

DS640PP4 7

SWITCHING CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

Input Sample Rate Single-Speed Mode

Double-Speed Mode

MCLK Duty Cycle
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period Single-Speed Mode

Double-Speed Mode

SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time

Fs
Fs

t

sclkl

t

sclkh

t

sclkw

t

sclkw

t

slrd

t

slrs

t

sdlrs

t

sdh

CS44L11

8

50
40 50 60 %
40 50 60 %
20 - - ns
20 - - ns

1

---------------------­128()Fs

1

------------------­64()Fs

20 - - ns
20 - - ns
20 - - ns
20 - - ns

-

-

50

100

--ns

--ns

kHz
kHz

LRCK

SCLK

SDIN

t

t

slrd

t

sclkw

t

sdlrs

Figure 1. Serial Audio Data Interface Timing

slrs

t

sclkl

t

sdh

t

sclkh

8 DS640PP4

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

p

(GND = 0 V; all voltages with respect to 0 V.)

Parameter Symbol Min Max Unit

SCL Clock Frequency
RST Rising Edge to Start

Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 8)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling (Note 9)

Notes:

8. Data must be held for sufficient time to bridge the transition time, t

9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

5

---------------------

10. for Single-Speed Mode and for Double-Speed Mode.

256 Fs×

5

--------------------­128 Fs×

f

scl

t

irs

t

buf

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

trc, t
tfc, t

t

susp

t

ack

rc
fc

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs
0-µs

250 - ns

-1µs

-300ns

4.7 - µs

- (Note 10) ns

, of SCL.

fc

CS44L11

RST

t

SDA

SCL

irs

Stop Start

t

buf

t

hdst

t

low

t

high

t

hdd

t

sud

t

ack

Repeated

Start

t

t

sust

t

hdst

Stop

rd

t

t

rc

t

fd

fc

t

sus

Figure 2. Control Port Timing - I²C Format

DS640PP4 9

2. TYPICAL CONNECTION DIAGRAMS

1.8 to 2.4 V
Supply

Low ESR
Tantalum

100µF

+

1.0µF 0.1µF

VA_HPA

7

VD

12 13

VA_HPB

CS44L11

1.8 to 2.4 V
Supply

5

+

1.0µF 0.1µF

Digital
A

udio

Source

Mode

Control

* Filter component values shown are for a 16 Ω load. Please see the CDB44L11 datasheet for information

VD

CS44L11

4

MCLK

3

SCLK

2

LRCK

1

SDIN

9

DEM

16

RST

8

DIF0

10

on how to calculate filter values for other loads.

15

HP_A

HP_B

G

NDGNDGND

6

11

14

100 µH

100 µH

0.22
µF

0.22
µF

220 µF

+

+

220 µF

Ω

16

Headphones

Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode

10 DS640PP4

.8 to 2.4V

Supply

100µF

Low ESR
Tantalum

CS44L11

+

1.0µF 0.1µF

7

VD

12 13

VA_HPA

VA_HPB

1.8 to 2.4 V
Supply

1.8 to 2.4 V
Supply

5

+

1.0µ F 0.1µF

Digital

A

udio

Source

Rpullup

Control

Logic

* Filter component values shown are for a 16

VD

4

MCLK

3

SCLK

2

LRCK

1

SDIN

9

SDA

8

SCL

16

RST

10

mation on how to calculate filter values for other loads.

CS44L11

11

HP_A

14

HP_B

G

NDGNDGND

15

Ω load. Please see the CDB44L11 datasheet for infor-

6

100 µH

100 µH

0.22
µF

0.22
µF

220 µF

+

+

220 µF

Ω

16

Headphones

Figure 4. Typical CS44L11 Connection Diagram Control Port Mode

DS640PP4 11