Cirrus Logic CS44600 User Manual

Features
CS44600
6-Channel Digital Amplifier Controller
> 100 dB Dynamic Range - System Level< 0.03% THD+N @ 1 W - System Level32 kHz to 192 kHz Sample RatesInternal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
Eliminates Clock Jitter Effects – Input Sample Rate Independent Operation
Power Supply Rejection Realtime FeedbackSpread Spectrum Modulation - Reduces EMIPWM Popguard
®
for Single-Ended Mode
PS_SYNC
Control
Auto Fs
Detect
DAI
Serial
Port
PWM
Clock
Volume
/ Limiter
Volume
/ Limiter
SRC
Volume
/ Limiter
XTI
XTO
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
XTAL
Eliminates AM Frequency InterferenceProgrammable Load Compensation FiltersSupport for up to 40 kHz Audio BandwidthDigital Volume Control with Soft Ramp
+24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI™ and I²CSeparate 2.5 V to 5.0 V Serial Port and Host
®
Host Control Interfaces
Control Port Supplies
PSR_RESET PSR_EN PSR_MCLK PSR_SYNC PSR_DATA
PWMOUTA1+ PWMOUTA1­PWMOUTB1+ PWMOUTB1-
PWMOUTA2+ PWMOUTA2­PWMOUTB2+ PWMOUTB2-
PWMOUTA3+ PWMOUTA3­PWMOUTB3+ PWMOUTB3-
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Power
Supply
Rejection
PWM
Conversion
PWM
Conversion
PWM
Conversion
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
INT
http://www.cirrus.com
SPI/I2C Host Control Port
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
PWM
Backend
Control/
Status
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6
MARCH '06
DS633F1
CS44600
General Description
The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP pack­age.The architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter, minimizing analog interference effects which negatively affect system performance.
The CS44600 integrates on-chip digital volume control, peak detect with limiter, de-emphasis, and 7 GPIO’s, allow­ing easy interfacing to many commonly available power stages. The PWM amplifier can achieve greater than 90% efficiency. This efficiency provides for smalle r device package, less heat sink requirements, and smaller power supplies.
The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion an d low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems.
2 DS633F1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
SPECIFIED OPERATING CONDITIONS ..............................................................................................8
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8
DC ELECTRICAL CHARACTERISTICS .......................................... ... ... .... ... ... ... .... ... ... ... ... .... .............. 9
DIGITAL INTERFACE CHARACTERISTICS ........................................................................................ 9
PWM OUTPUT PERFORMANCE CHARACTERISTICS .................................................................... 10
PWM FILTER CHARACTERISTICS ................................................................................................... 11
SWITCHING CHARACTERISTICS - XTI ............................................................................................ 11
SWITCHING CHARACTERISTICS - SYS_CLK .................................................................................. 12
SWITCHING CHARACTERISTICS - PWMOUTA1-B3 ....................................................................... 12
SWITCHING CHARACTERISTICS - PS_SYNC ................................................................................. 12
SWITCHING CHARACTERISTICS - DAI INTERFACE ...................................................................... 13
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................. 14
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................................ 15
2. PIN DESCRIPTIONS ......................................................................................................................... 16
2.1 I/O Pin Characteristics ................................................................................................................ 19
3. TYPICAL CONNECTION DIAGRAMS ......................................................................................20
4. APPLICATIONS ................................................................................................................................... 22
4.1 Overview ................................................................................................. ... ... .... ... ... ...................... 22
4.2 Feature Set Summary ................................................................................................................... 22
4.3 Clock Generation .... ................................................. ... ................................................ ................... 23
4.3.1 FsIn Domain Clocking .......................................................................................................... 24
4.3.2 FsOut Domain Clocking ........................... ... .... ... ... ................................................ .... ... ... ...... 24
4.4 FsIn Clock Domain Modules ......................................................................................................... 26
4.4.1 Digital Audio Input Port .. .... ................................................ ... ... .... ... ...................................... 26
4.4.2 Auto Rate Detect ............................................ ... ................................................................... 30
4.4.3 De-Emphasis ................. ................................................. ... ................................................... 30
4.5 FsOut Clock Domain Modules .......................................................................................................31
4.5.1 Sample Rate Converter .............. ... .... ... ... ... ................................................. ... ... ... .... ............ 31
4.5.2 Load Compensation Filter .................................................................................................... 31
4.5.3 Digital Volume and Mute Control .......................................... ... .... ... ... ... .... ............................31
4.5.4 Peak Detect / Limiter ............................................................................................................ 32
4.5.5 PWM Engines ....... ... ................................................ .... ... ... ... ................................................ 32
4.5.6 Interpolation Filter ....................................... .... ... ... ... ............................................................. 33
4.5.7 Quantizer ................. ... ................................................. ... ...................................................... 33
4.5.8 Modulator ................................................ ... .... ... ... ................................................ ................ 33
4.5.9 PWM Outputs ................................................. ... ... ... .... ... ... ................................................... 33
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback ........................................................ 34
4.6 Control Port Description and Timing ...... .... ................................................................................... 35
4.6.1 SPI Mode ....... ................................................. ... ................................................ ... ................ 35
4.6.2 I²C Mode .. ... ... ... .... ... ... ... .... ................................................ ... ................................................ 36
4.6.3 GPIOs ............................................ .... ... ... ... .... ... ... ............................................. ...................37
4.6.4 Host Interrupt ........................................ ... ... .............................................. ... ... ... ... ................ 37
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 38
5.1 Reset and Power-Up .....................................................................................................................41
5.1.1 PWM PopGuard® Transient Control .................................................................................... 41
5.1.2 Recommended Power-Up Sequence ................................................................................... 41
5.1.3 Recommended PSR Calibration Sequence .................. ... ... ... .... ... ... ... .... ... ... ...................... 42
5.1.4 Recommended Power-Down Sequence .............................................................................. 43
6. REGISTER QUICK REFERENCE ........................................................................................................ 44
7. REGISTER DESCRIPTION .................................................................................................................. 48
7.1 Memory Address Pointer (MAP) .......................... ............................. ............................. ................ 48
CS44600
DS633F1 3
CS44600
7.1.1 Increment (INCR) ................................................................................................................. 48
7.1.2 Memory Address Pointer (MAPx) ......................................................................................... 48
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................................. 48
7.2.1 Chip I.D. (Chip_IDx) ............................................................................................................. 48
7.2.2 Chip Revision (Rev_IDx) ...................................................................................................... 49
7.3 Clock Configuration and Power Control (address 02h) ................................................................. 50
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ........................................................................... 50
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ....................................................... 50
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0]) ............................................. 50
7.3.4 Power Down XTAL (PDN_XTAL) ......................................................................................... 50
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE) ..................... ................................... ... 51
7.3.6 Power Down (PDN) .............................................................................................................. 51
7.4 PWM Channel Power Down Control (address 03h) ...................................................................... 51
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1) ............................................. 51
7.5 Misc. Configuration (address 04h) ................................................................................................ 52
7.5.1 Digital Interface Format (DIFX) ....................... ... ... ... .... ... ................................................ ...... 52
7.5.2 AM Frequency Hopping (AM_FREQ_HOP) ......................................................................... 52
7.5.3 Freeze Controls (FREEZE) .................................................................................................. 52
7.5.4 De-Emphasis Control (DEM[1:0]) ......................................................................................... 53
7.6 Ramp Configuration (address 05h) ............................................................................................... 53
7.6.1 Ramp-Up/Down Setting (RAMP[1:0]) .................................................................................. 53
7.6.2 Ramp Speed (RAMP_SPD[1:0]) .......................... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 53
7.7 Volume Control Configuration (address 06h) ............................................................. ... .... ... ... ... ... 54
7.7.1 Single Volume Control (SNGVOL) ....................................................................................... 54
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0]) .................. ... ... .... ... ... ... .... ... ......................... 54
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) ................................................. 54
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR) ............................. ....... ...... ...... ....... ...... ... 55
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR) ................................................... 55
7.7.6 Auto-Mute (AMUTE) ............................................................................................................. 55
7.8 Master Volume Control - Integer (address 07h) ............................................................................ 56
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) ............................................................ 56
7.9 Master Volume Control - Fraction (address 08h) .......................................................................... 56
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0]) ......................................................... 56
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh) .................................................... 58
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) ..................... ................................... 58
7.11 Channel XX Volume Control1 - Fraction (address 11h) ............................................................ 58
7.12 Channel XX Volume Control2 - Fraction (address 12h) .............................................................. 58
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0]) .................................................... 58
7.13 Channel Mute (address 13h) ....................................................................................................... 59
7.13.1 Independent Channel Mute (CHXX_MUTE) ....................................................................... 59
7.14 Channel Invert (address 14h) ...................... ....................................................... ......................... 59
7.14.1 Invert Signal Polarity (CHXX_INV) ......................................................... ... ... ... ... .... ... ... ... ... 59
7.15 Peak Limiter Control Register (address 15h) ............................................................................. 60
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) ...................................................................... 60
7.15.2 Peak Signal Limiter Enable (LIMIT_EN) .......... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 60
7.16 Limiter Attack Rate (address 16h) .............................................................................................. 60
7.16.1 Attack Rate (ARATE[7:0]) .................................................................................................. 60
7.17 Limiter Release Rate (address 17h) ....................................................................................
7.17.1 Release Rate (RRATE[7:0]) ...............................................................................................61
7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h) .. 61
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0]) .................................. 61
7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h) .... 62
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ......................................... 62
..... 61
4 DS633F1
CS44600
7.20 Interrupt Mode Control (address 28h) ......................................................................................... 62
7.20.1 Interrupt Pin Control (INT1/INT0) .......................................................................................62
7.20.2 Overflow Level/Edge Select (OVFL_L/E) ........................................................................... 63
7.21 Interrupt Mask (address 29h) ...................................................................................................... 63
7.22 Interrupt Status (address 2Ah) (Read Only) ...............................................................................63
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK) ................. .... ... ................................................ ... ... 63
7.22.2 SRC Lock Interrupt (SRC_LOCK) ...................................................................................... 64
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE) ................................................................. 64
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE) ......................... ... .... ... ... ... ... .... ... ......... 64
7.22.5 Mute Complete Interrupt (Mute_DONE) ............. ................................................................ 64
7.22.6 Channel Over Flow Interrupt (OVFL_INT) ....................................................................... ... 64
7.22.7 GPIO Interrupt Condition (GPIO_INT) ....................................................................... ... ......64
7.23 Channel Over Flow Status (address 2Bh) (Read Only) .............................................................. 65
7.23.1 ChXX_OVFL ....................................................................................................................... 65
7.24 GPIO Pin In/Out (address 2Ch) ................................................................................................... 65
7.24.1 GPIO In/Out Selection (GPIOX_I/O) .................................................................................. 65
7.25 GPIO Pin Polarity/Type (address 2Dh) .................................... ... ... ............................................. 65
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T) ...................................................................... 65
7.26 GPIO Pin Level/Edge Trigger (address 2Eh) .............................................................................. 66
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E) ................................................................. 66
7.27 GPIO Status Register (address 2Fh) .......................................................................................... 66
7.27.1 GPIO Pin Status (GPIOX_STATUS) .................................................................................. 66
7.28 GPIO Interrupt Mask Register (address 30h) ........ ... ... ... .... ... ... ... ... .... ... ...................................... 67
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) ................................................................................. 67
7.29 PWM Configuration Register (address 31h) ...............................................................................67
7.29.1 Over Sample Rate Selection (OSRATE) ............................................................................ 67
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG) .. ... .... ... ... ... ... .... ... ... ... ... 67
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG) .. ... .... ... ... ... ... .... ... ... ... ... 67
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) ......................................................... 68
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG) ......................................................... 68
7.30 PWM Minimum Pulse Width Register (address 32h) ................................................................. 68
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-) ................................................. 68
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0]) . ................................................ 68
7.31 PWMOUT Delay Register (address 33h) ................................................................................... 69
7.31.1 Differential Signal Delay (DIFF_DLY[2:0]) .......................... ....................................... ......... 69
7.31.2 Channel Delay Settings (CHNL_DLY[4:0]) ..................... ................................ ................... 69
7.32 PSR and Power Supply Configuration (address 34h) ................................................................. 70
7.32.1 Power Supply Rejection Enable (PSR_EN) ................................................. ... ... .... ... .........70
7.32.2 Power Supply Rejection Reset (PSR_RESET) .................................................................. 70
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN) .................. ... ...... ....... ...... ... 71
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0]) ............ .........................71
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h) ................. ...................................................... 71
7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ..................................................................................... 71
7.33.2 Decimator Scale (DEC_SCALE[18:0]) ............................................................................... 71
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ............................................................................... 72
7.34.1 Decimator Outd (DEC_OUTD[23:0]) .................................................................................. 72
8. PARAMETER DEFINITIONS ................................................................................................................ 73
9. REFERENCES ...................................................................................................................................... 75
10. PACKAGE DIMENSIONS ......................................................................................................... 76
11. THERMAL CHARACTERISTICS ................................. ... ... ... ................................................. ... ... ...... 77
12. ORDERING INFORMATION . ... ... .... ... ................................................ ... .... ... ... ... .... ... ... ... ................... 77
13. REVISION HISTORY .................................................................... ... ... ... ............................................. 77
DS633F1 5
LIST OF FIGURES
Figure 1.Performance Characteristics Evaluation Active Filter Circuit ...................................................... 10
Figure 2.XTI Timings .......................................... .... ... ... ... .... ...................................................................... 11
Figure 3.SYS_CLK Timings ...................................................................................................................... 12
Figure 4.PWMOUTxx Timings ........... ................................................. ... ... ... .... ... ... ... .... ... ......................... 12
Figure 5.PS_SYNC Timings ...................... ... ... ... .... ... ... ... .... ... ... ................................................................ 12
Figure 6.Serial Audio Interface Timing ... ... ... ... .................................................... ... ... .... ... ... ...................... 13
Figure 7.Serial Audio Interface Timing - TDM Mode ................................................................................. 13
Figure 8.Control Port Timing - I²C Format ........................................................................ ... ... ... .... ............ 14
Figure 9.Control Port Timing - SPI Format ............................. ... ... .... ... ... ... ................................................ 15
Figure 10.CS44600 Pinout Diagram ...................................................... ... ... .... ... ... ... .... ............................ 16
Figure 11.Typical Full-Bridge Connection Diagram ............ ... ... ... .... ... ... ... ... ............................................. 20
Figure 12.Typical Half-Bridge Connection Diagram ..................................................................................21
Figure 13.CS44600 Data Flow Diagram (Single Channel Shown) ...........................................................23
Figure 14.Fundamental Mode Crystal Configuration .......... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ......................... 24
Figure 15.3rd Overtone Crystal Configuration .......................................................................................... 25
Figure 16.CS44600 Internal Clock Generation ......................................................................................... 25
Figure 17.I²S Serial Audio Formats ........................................................................................................... 27
Figure 18.Left-Justified Serial Audio Formats ........................................................................................... 27
Figure 19.Right-Justified Serial Audio Formats ......................................................................................... 28
Figure 20.One Line Mode #1 Serial Audio Format .................................................................................... 28
Figure 21.One Line Mode #2 Serial Audio Format .................................................................................... 29
Figure 22.TDM Mode Serial Audio Format ............ ... ................................................ .... ............................ 29
Figure 23.De-Emphasis Curve ............................................ ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 30
Figure 24.Control Port Timing in SPI Mode .............................................................................................. 35
Figure 25.Control Port Timing, I²C Slave Mode Write ...............................................................................36
Figure 26.Control Port Timing, I²C Slave Mode Read ............................................................................... 36
Figure 27.Recommended CS44600 Power Supply Decoupling Layout .................................................... 38
Figure 28.Recommended CS44600 Crystal Circuit Layout ...................................................................... 39
Figure 29.Recommended PSR Circuit Layout ....................................................... ... .... ... ... ... ... .... ... ... ...... 40
Figure 30.PSR Calibration Sequence ....................................................................................................... 43
Figure 31.PWM Output Delay ................................................................................................................... 70
Figure 32.64-Pin LQFP Package Drawing ................................................................................................ 76
CS44600
6 DS633F1
LIST OF TABLES
Table 1. Common DAI_MCLK Frequencies .............................................................................................. 24
Table 2. DAI Serial Audio Port Channel Allocations ................................................................................. 26
Table 3. Load Compensation Example Settings ....................................................................................... 31
Table 4. Typical PWM Switch Rate Settings ............................................................................................. 33
Table 5. Digital Audio Interface Formats ................................................................................................... 52
Table 6. Master Integer Volume Settings .................................................................................................. 56
Table 7. Master Fractional Volume Settings ............................................................................................. 57
Table 8. Channel Integer Volume Settings ............................................................................................... 58
Table 9. Channel Fractional Volume Settings ........................................................................................... 59
Table 10. Limiter Attack Rate Settings ................................... ............................................. ...................... 61
Table 11. Limiter Release Rate Settings ................................................................................................... 61
Table 12. Channel Load Compensation Filter Coarse Adjust ................ ................................................... 62
Table 13. Channel Load Compensation Filter Fine Adjust ........................................................................62
Table 14. PWM Minimum Pulse Width Settings ........................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ......69
Table 15. Differential Signal Delay Settings .............................................................................................. 69
Table 16. Channel Delay Settings ................................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ............................ 69
Table 17. Power Supply Sync Clock Divider Settings ............................................................................... 71
Table 18. Decimator Shift/Scale Coefficient Calculation Examples .......................................................... 72
CS44600
DS633F1 7
CS44600

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and spe cif icat ion s ar e de riv e d from measurements taken at nominal supply voltages and T
= 25°C.)
A

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to ground)
Parameter Symbol Min Typ Max Units
DC Power Supply
Digital 2.5 V VD 2.37 2.5 2.63 V XTAL (Note 1) 2.5 V
3.3 V
5.0 V
PWM Interface 3.3 V
5.0 V
Serial Audio Interface 2.5 V
3.3 V
5.0 V
Control Interface 2.5 V
3.3 V
5.0 V
Ambient Operating Temperature
Commercial -CQZ Automotive -DQZ
VDX 2.37
3.14
4.75
VDP 3.14
4.75
VLS 2.37
3.14
4.75
VLC 2.37
3.14
4.75
T
A
-10
-40
2.5
3.3
5.0
3.3
5.0
2.5
3.3
5.0
2.5
3.3
5.0
-
-
2.63
3.47
5.25
3.47
5.25
2.63
3.47
5.25
2.63
3.47
5.25
+70 +85
V V V
V V
V V V
V V V
°C °C
Notes:
1. When using external crystal, VDX = 3.14 V(min). When using clock signal input, VDX = 2.37 V(min).

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)
Parameters Symbol Min Max Units
DC Power Supply Digital
XTAL
PWM Interface
Serial Audio Interface
Control Interface Input Current (Note 2) I Digital Input Voltage PWM Interface
(Note 3) Serial Audio Interface
Control Interface Ambient Operating Temperature -CQ
(power applied) -DQ Storag e Temperature T
WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
VD VDX VDP
VLS
VLC
in
V
IND-PWM
V
IND-S
V
IND-C
T
stg
A
-0.3
-0.3
-0.3
-0.3
-0.3
10mA
-0.3
-0.3
-0.3
-20
-50
-65 +150 °C
3.5
6.0
6.0
6.0
6.0
VDP+0.4
VLS+0.4
VLC+0.4
+85 +95
V V V V V
V V V
°C °C
8 DS633F1
CS44600

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch Rate = 384 kHz unless otherwise specified.)
Parameter Symbol Min Typ Max Units
Normal Operation (Note 4)
Power Supply Current (Note 5) VD = 2.5 V
VDX = 3.3 V
VDP = 3.3 V
VLS = 3.3 V
VLC = 3.3 V (Note 6)
I I I I
I
D DX DP
LS
LC
-
-
-
-
-
150
2
1.2 150 250
-
-
-
-
­Power Dissipation VD=2.5 V, VDX = VDP = VLS = VLC = 3.3 V - 387 500 mW Power Supply Rejection Ratio (Note 7) (1 kHz)
(60 Hz)
PSRR -
15
-
40
-
­Power-Down Mode (Note 8)
Power Supply Current All Supplies except VDX (Note 9) I
pd
-80-µA
mA mA mA
µA µA
dB dB
4. Normal operation is defined as RST
= HI with a 997 Hz, 0 dBFS input.
5. Current consumption increas es with increasing XTAL clock rates and PWM switch rates. Variance be­tween DAI clock rates is negligible.
6. I
measured with no external loading on the SDA pin.
LC
7. Valid with PSRR function enabled and the recommended external ADC (CS4461) and filtering.
8. Power down mode is defined as RST
9. When RST
pin = LOW, the internal oscillator is active to provide a valid clock for the SYS_CLK output.
pin = LOW with all clock and data lines held static.

DIGITAL INTERFACE CHARACTERISTICS

(GND = 0 V, all voltages with respect to ground)
Parameters (Note 10) Symbol Min Typ Max Units
High-Level Input Voltage XTAL
PWM Interface
Serial Audio Interface
Control Interface
Low-Level Input Voltage XTAL
PWM Interface
Serial Audio Interface
Control Interface
High-Level Output Voltage at I
= -2 mA PWM Interface
o
Serial Audio Interface
V
Control Interface
Low-Level Output Voltage at I
= 2 mA PWM Interface
o
Serial Audio Interface
Control Interface
Input Leakage Current I
0.7xVDX
V
IH
0.7xVDP
0.7xVLS
0.7xVLC
-
V
IL
-
-
-
VDP-1.0
OH
VLS-1.0
VLC-1.0
-
V
OL
-
-
in
--±10µA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input Capacitance - - 8 pF
10. Serial Port signals include: SYS_CLK, DAI_MCLK, DAI_SCLK, DAI_LRCK, DAI_SDIN1-3 Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS
, AD1/CDIN, INT, RST, MUTE
PWM signals include: PWMOUTA1-B3, PSR_MCLK, PSR_SYNC, PSR_DATA, PS_SYNC, GPIO[6:0]
-
-
-
-
0.2xVDX
0.2xVDP
0.2xVLS
0.2xVLC
-
-
-
0.45
0.45
0.45
V V V V
V V V V
V V V
V V V
DS633F1 9
CS44600

PWM OUTPUT PERFORMANCE CHARACTERISTICS

(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576 MHz; PWM Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise specified; Performance measurements taken with a full-scale 997 Hz.)
Parameter Symbol Min Typ Max Unit
Dynamic Performance (Note 11)
24-Bits A-Weighted
unweighted
16-Bits unweighted
Total Harmonic Distortion + Noise (Note 11)
24-Bits 0 dB
THD+N -
-20 dB
-60 dB Idle Channel Noise / Signal-to-Noise Ratio - 110 - dB Interchannel Isolation (1 kHz) - 100 - dB
11. Performance characteristics measured using filter shown in Figure 1.
102
99
-
-
-
108 105
96
-90
-77
-45
-
-
-
-85
-
-
dB dB dB
dB dB dB
PWMOUTxx+
PWMOUTxx-
­+
­+

Figure 1. Performance Characteristics Evaluation Active Filter Circuit

­+
­+
Analog Output
10 DS633F1
CS44600

PWM FILTER CHARACTERISTICS

(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise specified.)
Parameter UnitMin Typ Max
Digital Filter Response (Note 12)
Passband OSRATE = 0b to -0.01 dB corner
to -3 dB corner
OSRATE = 1b (Note 13) to -0.01 dB corner
to -3 dB corner
Frequency Response OSRATE = 0b 10 Hz to 20 kHz OSRATE = 1b (Note 13) 10 Hz to 40 kHz
Group Delay (Note 14) ms De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz
Fs = 48 kHz
12. Filter response is not production tested but is characterized and guaranteed by design.
13. XTAL = 49.152 MHz; PWM Switch Rate = 768 kHz; Fs = 96 kHz to 192 kHz.
14. The equation for the group delay through the sample rate converter with OSRATE = 0b is (8.5 / Fsi) + (10 / Fso) ± (4.5 / Fsi). The equation for the group delay through the sample rate converter with OSRATE = 1b is (8.5 / Fsi) + (20 / Fso) ± (4.5 / Fsi).
0 0 0 0
-0.8
-1.2
-
-
-
-
-
-
-
-
-
-
-
-
1.6
24.0
3.3
44.5
+0.02 +0.02
±0.23 ±0.14 ±0.09
kHz kHz kHz kHz
dB dB
dB dB dB

SWITCHING CHARACTERISTICS - XTI

(VD = 2.5 V, VDP = VLC = VLS = 3.3 V, VDX = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VDX)
Parameter Symbol Min Typ Max Unit
XTI period t XTI high time t XTI low time t XTI Duty Cycle 45 50 55 % External Crystal operating frequency 24.576 --- 54 MHz
clki
clkih
clkil
XTI
t
clkih
t

Figure 2. XTI Timings

clki
t
clkil
18.518 --- 40.69 ns
8.34 --- 22.38 ns
8.34 --- 22.38 ns
DS633F1 11
CS44600

SWITCHING CHARACTERISTICS - SYS_CLK

(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF)
Parameter Symbol Min Typ Max Unit
SYS_CLK Period t SYS_CLK Duty Cycle 45 50 55 %
sclki
18.518 --- --- ns
SYS_CLK
t
sclki

Figure 3. SYS_CLK Timings

SWITCHING CHARACTERISTICS - PWMOUTA1-B3

(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V unless otherwise specified, Cload = 10 pF)
Parameter Symbol Min Typ Max Unit
PWMOUTxx Period t Rise Time of PWMOUTxx VDP = 5.0 V
VDP = 3.3 V
Fall Time of PWMOUTxx VDP = 5.0 V
VDP = 3.3 V
pwm
t
r
t
f
2.60 - 1.18 µs
-
-
-
-
1.6
2.1
1.1
1.4
-
-
-
-
ns ns
ns ns
t
r
t
f
PWMOUTxx
t
pwm

Figure 4. PWMOUTxx Timings

SWITCHING CHARACTERISTICS - PS_SYNC

(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V, Cload = 20 pF)
Parameter Symbol Min Typ Max Unit
PS_SYNC Period t PS_SYNC Duty Cycle 45 50 55 %
psclki
PS_SYNC
t
psclki

Figure 5. PS_SYNC Timings

592.576 --- --- ns
12 DS633F1
CS44600

SWITCHING CHARACTERISTICS - DAI INTERFACE

(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)
Parameters Symbol Min Max Units
RST
pin Low Pulse Width (Note 15) 1-ms DAI_MCLK Duty Cycle (Note 16) 40 60 % DAI_SCLK Duty Cycle 45 55 % DAI_LRCK Duty Cycle 45 55 % DAI Sample Rate (Note 17) F DAI_SDIN Setup Time Before DAI_SCLK Rising Edge t DAI_SDIN Hold Time After DAI_SCLK Rising Edge t DAI_SCLK High Time t
sckh
DAI_SCLK Low Time t DAI_LRCK Setup Time Before DAI_SCLK Rising Edge t DAI_SCLK Rising Edge Before DAI_LRCK Edge t
lrckd
s ds dh
sckl
lrcks
32 192 kHz 10 - ns 10 - ns 20 - ns 20 - ns 25 - ns 25 - ns
15. After powering up, the CS44600, RST
should be held low until after the power supplies and clocks are set-
tled.
16. See Table 1 on page 26 for suggested MCLK frequencies.
17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.
DAI_LRCK
DAI_SCLK
DAI_SDINx
t
lrckd
t
lrcks
t
sckh
t
ds
t
dh
t
sckl

Figure 6. Serial Audio Interface Timing Figure 7. Serial Audio Interface Timing - TDM Mode

DAI_LRCK
(input)
DAI_SCLK
(input)
DAI_SDIN1
t
lrcks
t
lrckd
t
lrcks
t
sckh
t
ds
t
dh
MSB MSB-1
t
sckl
DS633F1 13
CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency f Bus Free Time between Transmissions t Start Condition Hold Time (prior to first clock pulse) t Clock Low time t Clock High Time t Setup Time for Repeated Start Condition t SDA Hold Time from SCL Falling (Note 18) t SDA Setup time to SCL Rising t Rise Time of SCL and SDA t Fall Time SCL and SDA t Setup Time for Stop Condition t
susp
scl
buf
hdst
low high sust
hdd
sud
r f
- 100 kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs 10 - ns
250 - ns
-1000ns
-300ns
4.7 - µs
18. Data must be held for sufficient time to bridge the transition time, t
Repeated
Stop Start
Start
SDA
t
buf
t
hdst
t
high
SCL
t
low
t
hdd
Figure 8. Control Port Timing - I²C Format
t
sud
t
sust
, of SCL.
f
t
hdst
Stop
t
f
t
r
t
susp
14 DS633F1
CS44600

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency f CS
High Time between Transmissions t
CS
Falling to CCLK Edge t CCLK Low Time t CCLK High Time t CDIN to CCLK Rising Setup Time t CCLK Rising to DATA Hold Time (Note 19) t CCLK Falling to CDOUT Stable t Rise Time of CDOUT t Fall Time of CDOUT t Rise Time of CCLK and CDIN (Note 20) t Fall Time of CCLK and CDIN (Note 20) t
sck
csh
css
scl sch dsu
dh
pd
r1 f1 r2 f2
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For f
<1 MHz.
sck
CS
0-6.0MHz
1.0 - - µs 20 - - ns 66 - - ns 66 - - ns 40 - - ns 15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
CCLK
CDIN
CDOUT
t
t
sch
t
dsu
scl
t
f2
t
dh
t
pd
t
css
t
r2

Figure 9. Control Port Timing - SPI Format

t
csh
DS633F1 15

2. PIN DESCRIPTIONS

CS44600
GND
PSR_EN
PS_SYNC
GND
XTI XTO VDX
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1 DAI_SDIN2 DAI_SDIN3
PWMOUTA1+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 2 3
4 5 6 7 8 9 10 11 12 13 14
VDP
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
GND
PWMOUTA2+
CS44600
VDP
PWMOUTA2-
PWMOUTB2+
GND
PWMOUTB2-
PSR_SYNC
PSR_RESET
PSR_DATAL
PSR_MCLK
GND
48
PWMOUTA3+
47
PWMOUTA3-
46
VDP
45
PWMOUTB3+
44
PWMOUTB3-
43
GND
42
NC
41
NC
40
VDP
39
NC
38
NC
37
GND
36
GPIO0
35
NC
VLS
15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VLC
VD
GND
MUTE
SCL/CCLK

Figure 10. CS44600 Pinout Diagram

AD1/CDIN
SDA/CDOUT
INT
AD0/CS
RST
VD
GND
GPIO3
GPIO6
GPIO4
GPIO5
34 33
GPIO1
GPIO2
16 DS633F1
Pin Name Pin # Pin Description
PS_SYNC 3
XTI 5 XTO 6 Crystal Oscillator Output (Output) - Crystal Oscillator output. SYS_CLK 8 DAI_MCLK 9 Digital Audio Input Master Clock (Input) - Master audio clock.
Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the switch mode power supply.
Crystal Oscillator Input (Input) - Crystal Oscillator input or accepts an external clock input signal that is used to drive the internal PWM core logic.
External System Clock (Output) - Clock output. This pin provides a divided down clock derived from the XTI input.
CS44600
DAI_SCLK 10
DAI_LRCK 11
DAI_SDIN1 DAI_SDIN2 DAI_SDIN3
MUTE 20
SCL/CCLK 21
SDA/CDOUT 22
AD1/CDIN 23
AD0/CS
INT 25
RST 26
GPIO6 29
12 1314Digital Audio Input Serial Data (Input) - Input for two’s complement serial audio data.
24
Digital Audio Input Serial Clock (Input) - Serial clock for the Digital Audio Input Inter- face. The clock frequency is a multiple of the Left/Right Clock running at Fs.
Digital Audio Input Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The rate is determined by the sampling fre­quency Fs.
Mute (Input) - The device will perform a hard mute on all channels. All internal registers are not reset to their default settings.
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram.
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram.; CDOUT is the output data line for the control port interface in SPI mode.
Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode.;CDIN is the input data line for the control port interface in SPI mode.
Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS
Interrupt Request (Output) - CMOS or open-drain interrupt request output. This pin is driven to the configured active state to indicate that the PWM Controller has status data that should be read by the host.
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low.
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST be individually controlled by the Host Controller.
is the chip select signal in SPI mode.
condition. It can be configured as a general purpose input or output which can
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
GPIO5 30
GPIO4 31
DS633F1 17
ing a RST be individually controlled by the Host Controller.
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST be individually controlled by the Host Controller.
condition. It can be configured as a general purpose input or output which can
condition. It can be configured as a general purpose input or output which can
GPIO3 32
GPIO2 33
GPIO1 34
GPIO0 35
PSR_MCLK 49
PSR_DATAL 50
CS44600
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow-
ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller.
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST be individually controlled by the Host Controller.
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST be individually controlled by the Host Controller.
General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST be individually controlled by the Host Controller.
Power Supply Rejection Master Clock (Output) - Master audio clock for externa l PSR ADC (CS4461).
Power Supply Rejection Input Serial Data (Input) - Input for serial audio data from external PSR ADC (CS4461).
condition. It can be configured as a general purpose input or output which can
condition. It can be configured as a general purpose input or output which can
condition. It can be configured as a general purpose input or output which can
PSR_SYNC 51
PSR_RESET 52
PSR_EN 2 PWMOUTA1+
PWMOUTA1­PWMOUTB1+ PWMOUTB1­PWMOUTA2+ PWMOUTA2­PWMOUTB2+ PWMOUTB2­PWMOUTA3+ PWMOUTA3­PWMOUTB3+ PWMOUTB3-
VDX 7 Crystal Power (Input) - Positive power supply for the Crystal section. VD 19, 27 Digital Power (Input) - Positive power supply for the digital section.
VLC 17
VLS 16
Power Supply Rejection Sync Clock (Input) - Synchronization signal for external PSR ADC (CS4461).
Power Supply Rejection Reset (Output) - The reset pin for the external Power Supply Rejection circuitry.
Power Supply Rejection Enable (Output) - The enable pin for the external Power Supply Rejection circuitry.
64 63 61 60 58 57
PWM Output (Output) - PWM control signals for the Class D amplifier backend.
55 54 47 46 44 43
Host Interface Power (Input) - Determines the required signal level for the digital input/output signals for the host interface.
Digital Audio Interface Power (Input) - Dete rmines the required signal level fo r the digital input signals for the digital audio interface.
VDP
GND
18 DS633F1
39, 45,
56, 62
1, 4,
18, 28, 36, 42, 48, 53,
PWM Interface Power (Input) - Determines the required signal level for the digital input/output signals for the PWM and GPIO interface.
Digital Ground (Input) - Ground reference for digital circuits.
59
CS44600

2.1 I/O Pin Characteristics

Power
Signal Name
RST VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible. SCL/CCLK VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
Rail I/O Driver Receiver
SDA/CDOUT VLC AD0/CS
AD1/CDIN VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up. INT VLC Output MUTE VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible.
DAI_SDINx VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_SCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_LRCK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_MCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. SYS_CLK VLS Output 2.5-5.0 V, CMOS ­XTI VDX Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-down. XTO VDX Output - -
GPIOx VDP PWMOUTAx+/- VDP Outp ut 3.3/5.0 V, CMOS -
PWMOUTBx+/- VDP Output 3.3/5.0 V, CMOS -
VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up.
Input / Output
Input / Output
2.5-5.0 V, CMOS/Open Drain
2.5-5.0 V, CMOS/Open Drain
3.3/5.0 V, CMOS/Open Drain
2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
-
3.3/5.0 V TTL Compatible.
PSR_MCLK VDP Output 3.3/5.0 V, CMOS ­PSR_SYNC VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up. PSR_DATA VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up. PSR_EN VDP Output 3.3/5.0 V, CMOS ­PSR_RESET VDP Output 3.3/5.0 V, CMOS ­PS_SYNC VDP Output 3.3/5.0 V, CMOS -
DS633F1 19

3. TYPICAL CONNECTION DIAGRAMS

CS44600
+2.5 V
+3.3 V to
+5.0 V
+2.5 V to
+5.0 V
10 µF
+
0.1 µF
0.1 µF
0.1 µF
24.576 MHz to 54 MHz
0.1 µF
Digital
Audio
Processor
0.01 µF
0.01 µF
0.01 µF
XTAL
0.01 µF
0.1 µF
0.01 µF
VD
VD
CS44600
VDX
XTI XTO
VLS
SYS_CLK DAI_MCLK
DAI_SCLK
DAI_LRCK DAI_SDIN1 DAI_SDIN2
DAI_SDIN3
0.1 µF
0.01 µF
VDP
0.1 µF
0.01 µF
0.01 µF
PWMOUTA1+ PWMOUTA1-
GPIO1
PWMOUTB1+
PWMOUTB1-
GPIO2
PWMOUTA2+
PWMOUTA2-
GPIO3
PWMOUTB2+ PWMOUTB2-
GPIO4
PWMOUTA3+ PWMOUTA3-
GPIO5
PWMOUTB3+
PWMOUTB3-
GPIO6 GPIO0
0.1 µF 10 µF
+3.3 V to +5.0 V
PWM IN1
CONTROL
PWM IN2 CONTROL
PWM IN3
CONTROL
PWM IN4 CONTROL
PWM IN5
CONTROL
PWM IN6 CONTROL
OUT1
STATUS
OUT2
STATUS
OUT3
STATUS
OUT4
STATUS
OUT5
STATUS
OUT6
STATUS
Front Left
Front Right
Surr. Left
Surr. Right
Center
Subwoofer
MUTE INT
2 k
RST
SCL/CCLK SDA/CDOUT
AD1/CDIN AD0/CS
VLC
GND
PS_SYNC
PSR_MCLK PSR_SYNC
PSR_DATA
PSR_EN
PSR_RESET
Power Supply Sync Clock
Power Supply Rail
CS4461
ADC
Optional
Micro-
Controller
+2.5 V
to +5.0 V
Note: Resistors are required for
I²C control port operation
2 k
See Note
0.1 µF

Figure 11. Typical Full-Bridge Connection Diagram

20 DS633F1
CS44600
+2.5 V
+3.3 V to
+5.0 V
+2.5 V to
+5.0 V
10 µF
+
0.1 µF
0.1 µF
0.1 µF
24.576 MHz to 54 MHz
0.1 µF
Digital
Audio
Processor
0.01 µF
0.01 µF
0.01 µF
XTAL
0.01 µF
0.1 µF
0.01 µF
VD
VD
CS44600
VDX
XTI XTO
VLS
SYS_CLK DAI_MCLK
DAI_SCLK
DAI_LRCK DAI_SDIN1 DAI_SDIN2
DAI_SDIN3
0.1 µF
0.01 µF
VDP
0.1 µF
0.01 µF
0.01 µF
PWMOUTA1+
PWMOUTA1­PWMOUTB1+
PWMOUTB1-
GPIO3
GPIO0
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
GPIO4
GPIO1
PWMOUTA3+ PWMOUTA3-
PWMOUTB3+ PWMOUTB3-
GPIO5
GPIO2
0.1 µF 10 µF
+3.3 V to +5.0 V
PWM IN1
PWM IN2
CONTROL
PWM IN1
PWM IN2
CONTROL
PWM IN1
PWM IN2
CONTROL
OUT1
Front Left
OUT2
Front Right
STATUS
OUT1
Surr. Left
OUT2
Surr. Right
STATUS
OUT1
Center
OUT2
Subwoofer
STATUS
MUTE
INT
2 k
RST
SCL/CCLK SDA/CDOUT
AD1/CDIN
AD0/CS
VLC
GND
PS_SYNC
PSR_MCLK PSR_SYNC
PSR_DATA
PSR_EN
PSR_RESET
Power Supply Sync Clock
Power Supply Rail
CS4461
ADC
Optional
Micro-
Controller
+2.5 V
to +5.0 V
Note: Resistors are required for
I²C control port operation
2 k
See Note
0.1 µF

Figure 12. Typical Half-Bridge Connection Diagram

DS633F1 21

4. APPLICATIONS

4.1 Overview

The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedb ack in a 64-pin LQFP package. The architecture uses a di rect-t o-digital ap proach that maintains digita l signal integ­rity to the final output filter, minimizing analog interference effects which negatively affect system perfor­mance.
The CS44600 integrates on-chip sample rate conversion, digital volume control, peak detect with volume limiter, de-emphasis, programmab le interrup t condit ions, and th e abilit y to chan ge the PW M switch ra te to eliminate AM frequency interference. The CS44600 also has a programmable load compensation filter, which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency re­sponse. For single-ended half-bridge applications PWM Popguard and realtime power supply feedback reduces noise coupling from the power supp ly. The PWM amplifier can achieve greater than 90% efficiency. This efficiency provides for a smaller device package, less heat sink requirements, and smaller power supplies.
The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems.

4.2 Feature Set Summary

CS44600
®
reduces the transient pops an d clicks
Core Features
2.5 V digital core voltage, VD.
VLC voltage pin for host interface logic levels between 2.5 V and 5.0 V.
VLS voltage pin for digital audio interface logic levels between 2.5 V and 5.0 V.
VDP voltage pin for PWM backend interface logic levels between 3.3 V and 5.0 V.
VDX voltage pin for clock input signals between 2.5 V and 5.0 V.
Clocking
Minimum of 128Fs DAI_MCLK for DAI serial interface.
DAI interface uses automatic detection of LRCK/MCLK ratio to configure internal DAI/SRC clocks.
All PWM Processing clocks generated internally via: – An external crystal - 24.576 MHz to 54 MHz, or – XTI input pin capable of supporting a clock signal at the VDX voltage level.
Programmable divide of XTI by 1, 2, 4, 8 for SYS_CLK output.
Programmable divide of XTI by 32, 64, 128, 256 for PS_SYNC (power supply synchronization signal).
Digital Audio Playback
Supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz sample frequencies.
High performance sample rate converter.
16, 20 and 24 bit audio sample lengths.
De-emphasis for 32 kHz, 44.1 kHz, 48 kHz.
22 DS633F1
Digital volume control with soft ramp.
Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
Peak Detect and Volume Limiter with programmable attack and release rates.
Signal-clipping interrupt indicator.
Additional Features
Contains a two-stage digital output filter for speaker impedance compensation.
Provide s 7 prog ram mabl e GPIO pins with interr upt ge neratio n for easily int erfa cing to a va riety of com-
monly available power state parts. Interrupts can be masked.
Selectable over-sample rate for increased audio bandwidth.
Power supply clock output, PS_SYNC, with programmable divider
CS44600
FsIn FsOut
1,2,4,8
De-
Emphasis
128Fs
DAI_MCLK DAI_LRCK
DAI_SCLK DAI_SDINx
XTO
XTI
SYS_CLK
1, 1.5, 2, 3, 4, 6, 8
Ratio Detect
Digital Audio
Input Port
XTAL / CLKIN

Figure 13. CS44600 Data Flow Diagram (Single Channel Shown)

4.3 Clock Generation

The sources for internal clock generation for the PWM processing are as follows:
FsIn Domain: – DAI_MCLK, minimum 128Fs
FsOut Domain: – XTI/XTO (Fundamental or 3 – Clock signal on XTI (VDX is used to set logic voltage level)
SRC
SRC_MCLK (128Fs)
Master
Volume
Channel
Volume
2-pole Load
Compensation
Filter
2.25 Clock Control
Σ
VOL
MOD_MCLK
PWM_MCLK
1,1.5,
2,4
AM Freq. Hop
(AM_FREQ_HOP)
rd
overtone crystal), or
mute
Over Sample
(OSRATE)
LIMITER
PEAK
DETECT
Over Sample
(OSRATE)
x2
Multibit
Σ∆
Modulator
PSR
Feedback
PWM Engine
Delay
Delay
PWM_OUT+
PWM_OUT-
DS633F1 23
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